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Commit | Line | Data |
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682011ff | 1 | /************************************************************************** |
ac3315c2 | 2 | Intel Pro 1000 for ppcboot/das-u-boot |
682011ff WD |
3 | Drivers are port from Intel's Linux driver e1000-4.3.15 |
4 | and from Etherboot pro 1000 driver by mrakes at vivato dot net | |
5 | tested on both gig copper and gig fiber boards | |
6 | ***************************************************************************/ | |
7 | /******************************************************************************* | |
8 | ||
8bde7f77 | 9 | |
682011ff | 10 | Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. |
8bde7f77 | 11 | |
1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
8bde7f77 | 13 | |
682011ff WD |
14 | Contact Information: |
15 | Linux NICS <linux.nics@intel.com> | |
16 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
17 | ||
18 | *******************************************************************************/ | |
19 | /* | |
20 | * Copyright (C) Archway Digital Solutions. | |
21 | * | |
22 | * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> | |
23 | * 2/9/2002 | |
24 | * | |
25 | * Copyright (C) Linux Networx. | |
26 | * Massive upgrade to work with the new intel gigabit NICs. | |
27 | * <ebiederman at lnxi dot com> | |
2c2668f9 RZ |
28 | * |
29 | * Copyright 2011 Freescale Semiconductor, Inc. | |
682011ff WD |
30 | */ |
31 | ||
c752cd2a | 32 | #include <common.h> |
c6d80a15 | 33 | #include <dm.h> |
5c5e707a | 34 | #include <errno.h> |
cf92e05c | 35 | #include <memalign.h> |
5c5e707a | 36 | #include <pci.h> |
682011ff WD |
37 | #include "e1000.h" |
38 | ||
682011ff WD |
39 | #define TOUT_LOOP 100000 |
40 | ||
81dab9af BM |
41 | #ifdef CONFIG_DM_ETH |
42 | #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v)) | |
43 | #define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a) | |
44 | #else | |
f81ecb5d | 45 | #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) |
682011ff | 46 | #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) |
81dab9af | 47 | #endif |
682011ff | 48 | |
9ea005fb RZ |
49 | #define E1000_DEFAULT_PCI_PBA 0x00000030 |
50 | #define E1000_DEFAULT_PCIE_PBA 0x000a0026 | |
682011ff WD |
51 | |
52 | /* NIC specific static variables go here */ | |
53 | ||
873e8e01 MV |
54 | /* Intel i210 needs the DMA descriptor rings aligned to 128b */ |
55 | #define E1000_BUFFER_ALIGN 128 | |
682011ff | 56 | |
c6d80a15 SG |
57 | /* |
58 | * TODO(sjg@chromium.org): Even with driver model we share these buffers. | |
59 | * Concurrent receiving on multiple active Ethernet devices will not work. | |
60 | * Normally U-Boot does not support this anyway. To fix it in this driver, | |
61 | * move these buffers and the tx/rx pointers to struct e1000_hw. | |
62 | */ | |
873e8e01 MV |
63 | DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); |
64 | DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); | |
65 | DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); | |
682011ff WD |
66 | |
67 | static int tx_tail; | |
68 | static int rx_tail, rx_last; | |
c6d80a15 SG |
69 | #ifdef CONFIG_DM_ETH |
70 | static int num_cards; /* Number of E1000 devices seen so far */ | |
71 | #endif | |
682011ff | 72 | |
d60626f8 | 73 | static struct pci_device_id e1000_supported[] = { |
5c5e707a SG |
74 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, |
75 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) }, | |
76 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) }, | |
77 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) }, | |
78 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) }, | |
79 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) }, | |
80 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) }, | |
81 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) }, | |
82 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) }, | |
83 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) }, | |
84 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) }, | |
85 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) }, | |
86 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) }, | |
87 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) }, | |
88 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) }, | |
89 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) }, | |
90 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) }, | |
aa070789 | 91 | /* E1000 PCIe card */ |
5c5e707a SG |
92 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) }, |
93 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) }, | |
94 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) }, | |
95 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) }, | |
96 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) }, | |
97 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) }, | |
98 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) }, | |
99 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) }, | |
100 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) }, | |
101 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) }, | |
102 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) }, | |
103 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) }, | |
104 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) }, | |
105 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) }, | |
106 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) }, | |
107 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) }, | |
108 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) }, | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) }, | |
118 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) }, | |
119 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, | |
120 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, | |
121 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, | |
95186063 | 122 | |
1bc43437 | 123 | {} |
682011ff WD |
124 | }; |
125 | ||
126 | /* Function forward declarations */ | |
5c5e707a SG |
127 | static int e1000_setup_link(struct e1000_hw *hw); |
128 | static int e1000_setup_fiber_link(struct e1000_hw *hw); | |
129 | static int e1000_setup_copper_link(struct e1000_hw *hw); | |
682011ff WD |
130 | static int e1000_phy_setup_autoneg(struct e1000_hw *hw); |
131 | static void e1000_config_collision_dist(struct e1000_hw *hw); | |
132 | static int e1000_config_mac_to_phy(struct e1000_hw *hw); | |
133 | static int e1000_config_fc_after_link_up(struct e1000_hw *hw); | |
5c5e707a | 134 | static int e1000_check_for_link(struct e1000_hw *hw); |
682011ff | 135 | static int e1000_wait_autoneg(struct e1000_hw *hw); |
aa070789 | 136 | static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, |
682011ff WD |
137 | uint16_t * duplex); |
138 | static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, | |
139 | uint16_t * phy_data); | |
140 | static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, | |
141 | uint16_t phy_data); | |
aa070789 | 142 | static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); |
682011ff WD |
143 | static int e1000_phy_reset(struct e1000_hw *hw); |
144 | static int e1000_detect_gig_phy(struct e1000_hw *hw); | |
aa070789 RZ |
145 | static void e1000_set_media_type(struct e1000_hw *hw); |
146 | ||
147 | static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); | |
7e2d991d | 148 | static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); |
aa070789 | 149 | static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); |
682011ff | 150 | |
8712adfd RI |
151 | #ifndef CONFIG_E1000_NO_NVM |
152 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); | |
f1bcad22 | 153 | static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); |
ecbd2078 RZ |
154 | static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, |
155 | uint16_t words, | |
156 | uint16_t *data); | |
682011ff WD |
157 | /****************************************************************************** |
158 | * Raises the EEPROM's clock input. | |
159 | * | |
160 | * hw - Struct containing variables accessed by shared code | |
161 | * eecd - EECD's current value | |
162 | *****************************************************************************/ | |
2326a94d | 163 | void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) |
682011ff WD |
164 | { |
165 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then | |
166 | * wait 50 microseconds. | |
167 | */ | |
168 | *eecd = *eecd | E1000_EECD_SK; | |
169 | E1000_WRITE_REG(hw, EECD, *eecd); | |
170 | E1000_WRITE_FLUSH(hw); | |
171 | udelay(50); | |
172 | } | |
173 | ||
174 | /****************************************************************************** | |
175 | * Lowers the EEPROM's clock input. | |
176 | * | |
8bde7f77 | 177 | * hw - Struct containing variables accessed by shared code |
682011ff WD |
178 | * eecd - EECD's current value |
179 | *****************************************************************************/ | |
2326a94d | 180 | void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) |
682011ff | 181 | { |
8bde7f77 WD |
182 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
183 | * wait 50 microseconds. | |
682011ff WD |
184 | */ |
185 | *eecd = *eecd & ~E1000_EECD_SK; | |
186 | E1000_WRITE_REG(hw, EECD, *eecd); | |
187 | E1000_WRITE_FLUSH(hw); | |
188 | udelay(50); | |
189 | } | |
190 | ||
191 | /****************************************************************************** | |
192 | * Shift data bits out to the EEPROM. | |
193 | * | |
194 | * hw - Struct containing variables accessed by shared code | |
195 | * data - data to send to the EEPROM | |
196 | * count - number of bits to shift out | |
197 | *****************************************************************************/ | |
198 | static void | |
199 | e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) | |
200 | { | |
201 | uint32_t eecd; | |
202 | uint32_t mask; | |
203 | ||
204 | /* We need to shift "count" bits out to the EEPROM. So, value in the | |
205 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
8bde7f77 | 206 | * In order to do this, "data" must be broken down into bits. |
682011ff WD |
207 | */ |
208 | mask = 0x01 << (count - 1); | |
209 | eecd = E1000_READ_REG(hw, EECD); | |
210 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
211 | do { | |
212 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", | |
213 | * and then raising and then lowering the clock (the SK bit controls | |
214 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM | |
215 | * by setting "DI" to "0" and then raising and then lowering the clock. | |
216 | */ | |
217 | eecd &= ~E1000_EECD_DI; | |
218 | ||
219 | if (data & mask) | |
220 | eecd |= E1000_EECD_DI; | |
221 | ||
222 | E1000_WRITE_REG(hw, EECD, eecd); | |
223 | E1000_WRITE_FLUSH(hw); | |
224 | ||
225 | udelay(50); | |
226 | ||
227 | e1000_raise_ee_clk(hw, &eecd); | |
228 | e1000_lower_ee_clk(hw, &eecd); | |
229 | ||
230 | mask = mask >> 1; | |
231 | ||
232 | } while (mask); | |
233 | ||
234 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
235 | eecd &= ~E1000_EECD_DI; | |
236 | E1000_WRITE_REG(hw, EECD, eecd); | |
237 | } | |
238 | ||
239 | /****************************************************************************** | |
240 | * Shift data bits in from the EEPROM | |
241 | * | |
242 | * hw - Struct containing variables accessed by shared code | |
243 | *****************************************************************************/ | |
244 | static uint16_t | |
aa070789 | 245 | e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) |
682011ff WD |
246 | { |
247 | uint32_t eecd; | |
248 | uint32_t i; | |
249 | uint16_t data; | |
250 | ||
aa070789 RZ |
251 | /* In order to read a register from the EEPROM, we need to shift 'count' |
252 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock | |
253 | * input to the EEPROM (setting the SK bit), and then reading the | |
254 | * value of the "DO" bit. During this "shifting in" process the | |
255 | * "DI" bit should always be clear. | |
682011ff WD |
256 | */ |
257 | ||
258 | eecd = E1000_READ_REG(hw, EECD); | |
259 | ||
260 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
261 | data = 0; | |
262 | ||
aa070789 | 263 | for (i = 0; i < count; i++) { |
682011ff WD |
264 | data = data << 1; |
265 | e1000_raise_ee_clk(hw, &eecd); | |
266 | ||
267 | eecd = E1000_READ_REG(hw, EECD); | |
268 | ||
269 | eecd &= ~(E1000_EECD_DI); | |
270 | if (eecd & E1000_EECD_DO) | |
271 | data |= 1; | |
272 | ||
273 | e1000_lower_ee_clk(hw, &eecd); | |
274 | } | |
275 | ||
276 | return data; | |
277 | } | |
278 | ||
279 | /****************************************************************************** | |
aa070789 | 280 | * Returns EEPROM to a "standby" state |
682011ff WD |
281 | * |
282 | * hw - Struct containing variables accessed by shared code | |
682011ff | 283 | *****************************************************************************/ |
2326a94d | 284 | void e1000_standby_eeprom(struct e1000_hw *hw) |
682011ff | 285 | { |
aa070789 | 286 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
682011ff WD |
287 | uint32_t eecd; |
288 | ||
289 | eecd = E1000_READ_REG(hw, EECD); | |
290 | ||
aa070789 RZ |
291 | if (eeprom->type == e1000_eeprom_microwire) { |
292 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
293 | E1000_WRITE_REG(hw, EECD, eecd); | |
294 | E1000_WRITE_FLUSH(hw); | |
295 | udelay(eeprom->delay_usec); | |
682011ff | 296 | |
aa070789 RZ |
297 | /* Clock high */ |
298 | eecd |= E1000_EECD_SK; | |
299 | E1000_WRITE_REG(hw, EECD, eecd); | |
300 | E1000_WRITE_FLUSH(hw); | |
301 | udelay(eeprom->delay_usec); | |
302 | ||
303 | /* Select EEPROM */ | |
304 | eecd |= E1000_EECD_CS; | |
305 | E1000_WRITE_REG(hw, EECD, eecd); | |
306 | E1000_WRITE_FLUSH(hw); | |
307 | udelay(eeprom->delay_usec); | |
308 | ||
309 | /* Clock low */ | |
310 | eecd &= ~E1000_EECD_SK; | |
311 | E1000_WRITE_REG(hw, EECD, eecd); | |
312 | E1000_WRITE_FLUSH(hw); | |
313 | udelay(eeprom->delay_usec); | |
314 | } else if (eeprom->type == e1000_eeprom_spi) { | |
315 | /* Toggle CS to flush commands */ | |
316 | eecd |= E1000_EECD_CS; | |
317 | E1000_WRITE_REG(hw, EECD, eecd); | |
318 | E1000_WRITE_FLUSH(hw); | |
319 | udelay(eeprom->delay_usec); | |
320 | eecd &= ~E1000_EECD_CS; | |
321 | E1000_WRITE_REG(hw, EECD, eecd); | |
322 | E1000_WRITE_FLUSH(hw); | |
323 | udelay(eeprom->delay_usec); | |
324 | } | |
325 | } | |
326 | ||
327 | /*************************************************************************** | |
328 | * Description: Determines if the onboard NVM is FLASH or EEPROM. | |
329 | * | |
330 | * hw - Struct containing variables accessed by shared code | |
331 | ****************************************************************************/ | |
472d5460 | 332 | static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
aa070789 RZ |
333 | { |
334 | uint32_t eecd = 0; | |
335 | ||
336 | DEBUGFUNC(); | |
337 | ||
338 | if (hw->mac_type == e1000_ich8lan) | |
472d5460 | 339 | return false; |
aa070789 | 340 | |
2c2668f9 | 341 | if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { |
aa070789 RZ |
342 | eecd = E1000_READ_REG(hw, EECD); |
343 | ||
344 | /* Isolate bits 15 & 16 */ | |
345 | eecd = ((eecd >> 15) & 0x03); | |
346 | ||
347 | /* If both bits are set, device is Flash type */ | |
348 | if (eecd == 0x03) | |
472d5460 | 349 | return false; |
aa070789 | 350 | } |
472d5460 | 351 | return true; |
682011ff WD |
352 | } |
353 | ||
354 | /****************************************************************************** | |
aa070789 | 355 | * Prepares EEPROM for access |
8bde7f77 | 356 | * |
682011ff | 357 | * hw - Struct containing variables accessed by shared code |
aa070789 RZ |
358 | * |
359 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This | |
360 | * function should be called before issuing a command to the EEPROM. | |
682011ff | 361 | *****************************************************************************/ |
2326a94d | 362 | int32_t e1000_acquire_eeprom(struct e1000_hw *hw) |
682011ff | 363 | { |
aa070789 RZ |
364 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
365 | uint32_t eecd, i = 0; | |
682011ff | 366 | |
f81ecb5d | 367 | DEBUGFUNC(); |
aa070789 RZ |
368 | |
369 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) | |
370 | return -E1000_ERR_SWFW_SYNC; | |
682011ff WD |
371 | eecd = E1000_READ_REG(hw, EECD); |
372 | ||
95186063 | 373 | if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { |
aa070789 RZ |
374 | /* Request EEPROM Access */ |
375 | if (hw->mac_type > e1000_82544) { | |
376 | eecd |= E1000_EECD_REQ; | |
377 | E1000_WRITE_REG(hw, EECD, eecd); | |
378 | eecd = E1000_READ_REG(hw, EECD); | |
379 | while ((!(eecd & E1000_EECD_GNT)) && | |
380 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { | |
381 | i++; | |
382 | udelay(5); | |
383 | eecd = E1000_READ_REG(hw, EECD); | |
384 | } | |
385 | if (!(eecd & E1000_EECD_GNT)) { | |
386 | eecd &= ~E1000_EECD_REQ; | |
387 | E1000_WRITE_REG(hw, EECD, eecd); | |
388 | DEBUGOUT("Could not acquire EEPROM grant\n"); | |
389 | return -E1000_ERR_EEPROM; | |
390 | } | |
391 | } | |
392 | } | |
682011ff | 393 | |
aa070789 | 394 | /* Setup EEPROM for Read/Write */ |
682011ff | 395 | |
aa070789 RZ |
396 | if (eeprom->type == e1000_eeprom_microwire) { |
397 | /* Clear SK and DI */ | |
398 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); | |
399 | E1000_WRITE_REG(hw, EECD, eecd); | |
682011ff | 400 | |
aa070789 RZ |
401 | /* Set CS */ |
402 | eecd |= E1000_EECD_CS; | |
403 | E1000_WRITE_REG(hw, EECD, eecd); | |
404 | } else if (eeprom->type == e1000_eeprom_spi) { | |
405 | /* Clear SK and CS */ | |
406 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
407 | E1000_WRITE_REG(hw, EECD, eecd); | |
408 | udelay(1); | |
409 | } | |
410 | ||
411 | return E1000_SUCCESS; | |
682011ff WD |
412 | } |
413 | ||
414 | /****************************************************************************** | |
aa070789 RZ |
415 | * Sets up eeprom variables in the hw struct. Must be called after mac_type |
416 | * is configured. Additionally, if this is ICH8, the flash controller GbE | |
417 | * registers must be mapped, or this will crash. | |
682011ff WD |
418 | * |
419 | * hw - Struct containing variables accessed by shared code | |
682011ff | 420 | *****************************************************************************/ |
aa070789 | 421 | static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) |
682011ff | 422 | { |
aa070789 | 423 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
95186063 | 424 | uint32_t eecd; |
aa070789 RZ |
425 | int32_t ret_val = E1000_SUCCESS; |
426 | uint16_t eeprom_size; | |
682011ff | 427 | |
95186063 MV |
428 | if (hw->mac_type == e1000_igb) |
429 | eecd = E1000_READ_REG(hw, I210_EECD); | |
430 | else | |
431 | eecd = E1000_READ_REG(hw, EECD); | |
432 | ||
f81ecb5d | 433 | DEBUGFUNC(); |
aa070789 RZ |
434 | |
435 | switch (hw->mac_type) { | |
436 | case e1000_82542_rev2_0: | |
437 | case e1000_82542_rev2_1: | |
438 | case e1000_82543: | |
439 | case e1000_82544: | |
440 | eeprom->type = e1000_eeprom_microwire; | |
441 | eeprom->word_size = 64; | |
442 | eeprom->opcode_bits = 3; | |
443 | eeprom->address_bits = 6; | |
444 | eeprom->delay_usec = 50; | |
472d5460 YS |
445 | eeprom->use_eerd = false; |
446 | eeprom->use_eewr = false; | |
aa070789 RZ |
447 | break; |
448 | case e1000_82540: | |
449 | case e1000_82545: | |
450 | case e1000_82545_rev_3: | |
451 | case e1000_82546: | |
452 | case e1000_82546_rev_3: | |
453 | eeprom->type = e1000_eeprom_microwire; | |
454 | eeprom->opcode_bits = 3; | |
455 | eeprom->delay_usec = 50; | |
456 | if (eecd & E1000_EECD_SIZE) { | |
457 | eeprom->word_size = 256; | |
458 | eeprom->address_bits = 8; | |
459 | } else { | |
460 | eeprom->word_size = 64; | |
461 | eeprom->address_bits = 6; | |
462 | } | |
472d5460 YS |
463 | eeprom->use_eerd = false; |
464 | eeprom->use_eewr = false; | |
aa070789 RZ |
465 | break; |
466 | case e1000_82541: | |
467 | case e1000_82541_rev_2: | |
468 | case e1000_82547: | |
469 | case e1000_82547_rev_2: | |
470 | if (eecd & E1000_EECD_TYPE) { | |
471 | eeprom->type = e1000_eeprom_spi; | |
472 | eeprom->opcode_bits = 8; | |
473 | eeprom->delay_usec = 1; | |
474 | if (eecd & E1000_EECD_ADDR_BITS) { | |
475 | eeprom->page_size = 32; | |
476 | eeprom->address_bits = 16; | |
477 | } else { | |
478 | eeprom->page_size = 8; | |
479 | eeprom->address_bits = 8; | |
480 | } | |
481 | } else { | |
482 | eeprom->type = e1000_eeprom_microwire; | |
483 | eeprom->opcode_bits = 3; | |
484 | eeprom->delay_usec = 50; | |
485 | if (eecd & E1000_EECD_ADDR_BITS) { | |
486 | eeprom->word_size = 256; | |
487 | eeprom->address_bits = 8; | |
488 | } else { | |
489 | eeprom->word_size = 64; | |
490 | eeprom->address_bits = 6; | |
491 | } | |
492 | } | |
472d5460 YS |
493 | eeprom->use_eerd = false; |
494 | eeprom->use_eewr = false; | |
aa070789 RZ |
495 | break; |
496 | case e1000_82571: | |
497 | case e1000_82572: | |
498 | eeprom->type = e1000_eeprom_spi; | |
499 | eeprom->opcode_bits = 8; | |
500 | eeprom->delay_usec = 1; | |
501 | if (eecd & E1000_EECD_ADDR_BITS) { | |
502 | eeprom->page_size = 32; | |
503 | eeprom->address_bits = 16; | |
504 | } else { | |
505 | eeprom->page_size = 8; | |
506 | eeprom->address_bits = 8; | |
507 | } | |
472d5460 YS |
508 | eeprom->use_eerd = false; |
509 | eeprom->use_eewr = false; | |
aa070789 RZ |
510 | break; |
511 | case e1000_82573: | |
2c2668f9 | 512 | case e1000_82574: |
aa070789 RZ |
513 | eeprom->type = e1000_eeprom_spi; |
514 | eeprom->opcode_bits = 8; | |
515 | eeprom->delay_usec = 1; | |
516 | if (eecd & E1000_EECD_ADDR_BITS) { | |
517 | eeprom->page_size = 32; | |
518 | eeprom->address_bits = 16; | |
519 | } else { | |
520 | eeprom->page_size = 8; | |
521 | eeprom->address_bits = 8; | |
682011ff | 522 | } |
472d5460 | 523 | if (e1000_is_onboard_nvm_eeprom(hw) == false) { |
95186063 MV |
524 | eeprom->use_eerd = true; |
525 | eeprom->use_eewr = true; | |
526 | ||
aa070789 RZ |
527 | eeprom->type = e1000_eeprom_flash; |
528 | eeprom->word_size = 2048; | |
529 | ||
530 | /* Ensure that the Autonomous FLASH update bit is cleared due to | |
531 | * Flash update issue on parts which use a FLASH for NVM. */ | |
532 | eecd &= ~E1000_EECD_AUPDEN; | |
682011ff | 533 | E1000_WRITE_REG(hw, EECD, eecd); |
682011ff | 534 | } |
aa070789 RZ |
535 | break; |
536 | case e1000_80003es2lan: | |
537 | eeprom->type = e1000_eeprom_spi; | |
538 | eeprom->opcode_bits = 8; | |
539 | eeprom->delay_usec = 1; | |
540 | if (eecd & E1000_EECD_ADDR_BITS) { | |
541 | eeprom->page_size = 32; | |
542 | eeprom->address_bits = 16; | |
543 | } else { | |
544 | eeprom->page_size = 8; | |
545 | eeprom->address_bits = 8; | |
546 | } | |
472d5460 YS |
547 | eeprom->use_eerd = true; |
548 | eeprom->use_eewr = false; | |
aa070789 | 549 | break; |
95186063 MV |
550 | case e1000_igb: |
551 | /* i210 has 4k of iNVM mapped as EEPROM */ | |
552 | eeprom->type = e1000_eeprom_invm; | |
553 | eeprom->opcode_bits = 8; | |
554 | eeprom->delay_usec = 1; | |
555 | eeprom->page_size = 32; | |
556 | eeprom->address_bits = 16; | |
557 | eeprom->use_eerd = true; | |
558 | eeprom->use_eewr = false; | |
559 | break; | |
aa070789 RZ |
560 | default: |
561 | break; | |
682011ff WD |
562 | } |
563 | ||
95186063 MV |
564 | if (eeprom->type == e1000_eeprom_spi || |
565 | eeprom->type == e1000_eeprom_invm) { | |
aa070789 RZ |
566 | /* eeprom_size will be an enum [0..8] that maps |
567 | * to eeprom sizes 128B to | |
568 | * 32KB (incremented by powers of 2). | |
569 | */ | |
570 | if (hw->mac_type <= e1000_82547_rev_2) { | |
571 | /* Set to default value for initial eeprom read. */ | |
572 | eeprom->word_size = 64; | |
573 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, | |
574 | &eeprom_size); | |
575 | if (ret_val) | |
576 | return ret_val; | |
577 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) | |
578 | >> EEPROM_SIZE_SHIFT; | |
579 | /* 256B eeprom size was not supported in earlier | |
580 | * hardware, so we bump eeprom_size up one to | |
581 | * ensure that "1" (which maps to 256B) is never | |
582 | * the result used in the shifting logic below. */ | |
583 | if (eeprom_size) | |
584 | eeprom_size++; | |
585 | } else { | |
586 | eeprom_size = (uint16_t)((eecd & | |
587 | E1000_EECD_SIZE_EX_MASK) >> | |
588 | E1000_EECD_SIZE_EX_SHIFT); | |
589 | } | |
590 | ||
591 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); | |
592 | } | |
593 | return ret_val; | |
682011ff WD |
594 | } |
595 | ||
aa070789 RZ |
596 | /****************************************************************************** |
597 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | |
598 | * | |
599 | * hw - Struct containing variables accessed by shared code | |
600 | *****************************************************************************/ | |
601 | static int32_t | |
602 | e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) | |
682011ff | 603 | { |
aa070789 RZ |
604 | uint32_t attempts = 100000; |
605 | uint32_t i, reg = 0; | |
606 | int32_t done = E1000_ERR_EEPROM; | |
682011ff | 607 | |
aa070789 | 608 | for (i = 0; i < attempts; i++) { |
95186063 MV |
609 | if (eerd == E1000_EEPROM_POLL_READ) { |
610 | if (hw->mac_type == e1000_igb) | |
611 | reg = E1000_READ_REG(hw, I210_EERD); | |
612 | else | |
613 | reg = E1000_READ_REG(hw, EERD); | |
614 | } else { | |
615 | if (hw->mac_type == e1000_igb) | |
616 | reg = E1000_READ_REG(hw, I210_EEWR); | |
617 | else | |
618 | reg = E1000_READ_REG(hw, EEWR); | |
619 | } | |
aa070789 RZ |
620 | |
621 | if (reg & E1000_EEPROM_RW_REG_DONE) { | |
622 | done = E1000_SUCCESS; | |
623 | break; | |
624 | } | |
625 | udelay(5); | |
626 | } | |
627 | ||
628 | return done; | |
682011ff WD |
629 | } |
630 | ||
aa070789 RZ |
631 | /****************************************************************************** |
632 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
633 | * | |
634 | * hw - Struct containing variables accessed by shared code | |
635 | * offset - offset of word in the EEPROM to read | |
636 | * data - word read from the EEPROM | |
637 | * words - number of words to read | |
638 | *****************************************************************************/ | |
639 | static int32_t | |
640 | e1000_read_eeprom_eerd(struct e1000_hw *hw, | |
641 | uint16_t offset, | |
642 | uint16_t words, | |
643 | uint16_t *data) | |
682011ff | 644 | { |
aa070789 RZ |
645 | uint32_t i, eerd = 0; |
646 | int32_t error = 0; | |
647 | ||
648 | for (i = 0; i < words; i++) { | |
649 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + | |
650 | E1000_EEPROM_RW_REG_START; | |
651 | ||
95186063 MV |
652 | if (hw->mac_type == e1000_igb) |
653 | E1000_WRITE_REG(hw, I210_EERD, eerd); | |
654 | else | |
655 | E1000_WRITE_REG(hw, EERD, eerd); | |
656 | ||
aa070789 RZ |
657 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
658 | ||
659 | if (error) | |
660 | break; | |
95186063 MV |
661 | |
662 | if (hw->mac_type == e1000_igb) { | |
663 | data[i] = (E1000_READ_REG(hw, I210_EERD) >> | |
664 | E1000_EEPROM_RW_REG_DATA); | |
665 | } else { | |
666 | data[i] = (E1000_READ_REG(hw, EERD) >> | |
aa070789 | 667 | E1000_EEPROM_RW_REG_DATA); |
95186063 | 668 | } |
682011ff | 669 | |
682011ff | 670 | } |
aa070789 RZ |
671 | |
672 | return error; | |
682011ff WD |
673 | } |
674 | ||
2326a94d | 675 | void e1000_release_eeprom(struct e1000_hw *hw) |
682011ff WD |
676 | { |
677 | uint32_t eecd; | |
682011ff | 678 | |
aa070789 RZ |
679 | DEBUGFUNC(); |
680 | ||
681 | eecd = E1000_READ_REG(hw, EECD); | |
682 | ||
683 | if (hw->eeprom.type == e1000_eeprom_spi) { | |
684 | eecd |= E1000_EECD_CS; /* Pull CS high */ | |
685 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ | |
686 | ||
682011ff | 687 | E1000_WRITE_REG(hw, EECD, eecd); |
aa070789 RZ |
688 | |
689 | udelay(hw->eeprom.delay_usec); | |
690 | } else if (hw->eeprom.type == e1000_eeprom_microwire) { | |
691 | /* cleanup eeprom */ | |
692 | ||
693 | /* CS on Microwire is active-high */ | |
694 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); | |
695 | ||
696 | E1000_WRITE_REG(hw, EECD, eecd); | |
697 | ||
698 | /* Rising edge of clock */ | |
699 | eecd |= E1000_EECD_SK; | |
700 | E1000_WRITE_REG(hw, EECD, eecd); | |
701 | E1000_WRITE_FLUSH(hw); | |
702 | udelay(hw->eeprom.delay_usec); | |
703 | ||
704 | /* Falling edge of clock */ | |
705 | eecd &= ~E1000_EECD_SK; | |
706 | E1000_WRITE_REG(hw, EECD, eecd); | |
707 | E1000_WRITE_FLUSH(hw); | |
708 | udelay(hw->eeprom.delay_usec); | |
682011ff | 709 | } |
682011ff WD |
710 | |
711 | /* Stop requesting EEPROM access */ | |
712 | if (hw->mac_type > e1000_82544) { | |
682011ff WD |
713 | eecd &= ~E1000_EECD_REQ; |
714 | E1000_WRITE_REG(hw, EECD, eecd); | |
715 | } | |
7e2d991d TH |
716 | |
717 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); | |
682011ff | 718 | } |
7e2d991d | 719 | |
682011ff | 720 | /****************************************************************************** |
aa070789 | 721 | * Reads a 16 bit word from the EEPROM. |
8bde7f77 | 722 | * |
682011ff | 723 | * hw - Struct containing variables accessed by shared code |
682011ff | 724 | *****************************************************************************/ |
aa070789 RZ |
725 | static int32_t |
726 | e1000_spi_eeprom_ready(struct e1000_hw *hw) | |
682011ff | 727 | { |
aa070789 RZ |
728 | uint16_t retry_count = 0; |
729 | uint8_t spi_stat_reg; | |
682011ff WD |
730 | |
731 | DEBUGFUNC(); | |
732 | ||
aa070789 RZ |
733 | /* Read "Status Register" repeatedly until the LSB is cleared. The |
734 | * EEPROM will signal that the command has been completed by clearing | |
735 | * bit 0 of the internal status register. If it's not cleared within | |
736 | * 5 milliseconds, then error out. | |
737 | */ | |
738 | retry_count = 0; | |
739 | do { | |
740 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, | |
741 | hw->eeprom.opcode_bits); | |
742 | spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); | |
743 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) | |
744 | break; | |
8bde7f77 | 745 | |
aa070789 RZ |
746 | udelay(5); |
747 | retry_count += 5; | |
748 | ||
749 | e1000_standby_eeprom(hw); | |
750 | } while (retry_count < EEPROM_MAX_RETRY_SPI); | |
751 | ||
752 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and | |
753 | * only 0-5mSec on 5V devices) | |
754 | */ | |
755 | if (retry_count >= EEPROM_MAX_RETRY_SPI) { | |
756 | DEBUGOUT("SPI EEPROM Status error\n"); | |
682011ff WD |
757 | return -E1000_ERR_EEPROM; |
758 | } | |
aa070789 RZ |
759 | |
760 | return E1000_SUCCESS; | |
682011ff WD |
761 | } |
762 | ||
763 | /****************************************************************************** | |
aa070789 | 764 | * Reads a 16 bit word from the EEPROM. |
682011ff | 765 | * |
aa070789 RZ |
766 | * hw - Struct containing variables accessed by shared code |
767 | * offset - offset of word in the EEPROM to read | |
768 | * data - word read from the EEPROM | |
682011ff | 769 | *****************************************************************************/ |
aa070789 RZ |
770 | static int32_t |
771 | e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, | |
772 | uint16_t words, uint16_t *data) | |
682011ff | 773 | { |
aa070789 RZ |
774 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
775 | uint32_t i = 0; | |
682011ff WD |
776 | |
777 | DEBUGFUNC(); | |
778 | ||
aa070789 RZ |
779 | /* If eeprom is not yet detected, do so now */ |
780 | if (eeprom->word_size == 0) | |
781 | e1000_init_eeprom_params(hw); | |
782 | ||
783 | /* A check for invalid values: offset too large, too many words, | |
784 | * and not enough words. | |
785 | */ | |
786 | if ((offset >= eeprom->word_size) || | |
787 | (words > eeprom->word_size - offset) || | |
788 | (words == 0)) { | |
789 | DEBUGOUT("\"words\" parameter out of bounds." | |
790 | "Words = %d, size = %d\n", offset, eeprom->word_size); | |
791 | return -E1000_ERR_EEPROM; | |
792 | } | |
793 | ||
794 | /* EEPROM's that don't use EERD to read require us to bit-bang the SPI | |
795 | * directly. In this case, we need to acquire the EEPROM so that | |
796 | * FW or other port software does not interrupt. | |
797 | */ | |
472d5460 YS |
798 | if (e1000_is_onboard_nvm_eeprom(hw) == true && |
799 | hw->eeprom.use_eerd == false) { | |
aa070789 RZ |
800 | |
801 | /* Prepare the EEPROM for bit-bang reading */ | |
802 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
803 | return -E1000_ERR_EEPROM; | |
804 | } | |
805 | ||
806 | /* Eerd register EEPROM access requires no eeprom aquire/release */ | |
472d5460 | 807 | if (eeprom->use_eerd == true) |
aa070789 RZ |
808 | return e1000_read_eeprom_eerd(hw, offset, words, data); |
809 | ||
aa070789 RZ |
810 | /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have |
811 | * acquired the EEPROM at this point, so any returns should relase it */ | |
812 | if (eeprom->type == e1000_eeprom_spi) { | |
813 | uint16_t word_in; | |
814 | uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; | |
815 | ||
816 | if (e1000_spi_eeprom_ready(hw)) { | |
817 | e1000_release_eeprom(hw); | |
818 | return -E1000_ERR_EEPROM; | |
819 | } | |
820 | ||
821 | e1000_standby_eeprom(hw); | |
822 | ||
823 | /* Some SPI eeproms use the 8th address bit embedded in | |
824 | * the opcode */ | |
825 | if ((eeprom->address_bits == 8) && (offset >= 128)) | |
826 | read_opcode |= EEPROM_A8_OPCODE_SPI; | |
827 | ||
828 | /* Send the READ command (opcode + addr) */ | |
829 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); | |
830 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), | |
831 | eeprom->address_bits); | |
832 | ||
833 | /* Read the data. The address of the eeprom internally | |
834 | * increments with each byte (spi) being read, saving on the | |
835 | * overhead of eeprom setup and tear-down. The address | |
836 | * counter will roll over if reading beyond the size of | |
837 | * the eeprom, thus allowing the entire memory to be read | |
838 | * starting from any offset. */ | |
839 | for (i = 0; i < words; i++) { | |
840 | word_in = e1000_shift_in_ee_bits(hw, 16); | |
841 | data[i] = (word_in >> 8) | (word_in << 8); | |
842 | } | |
843 | } else if (eeprom->type == e1000_eeprom_microwire) { | |
844 | for (i = 0; i < words; i++) { | |
845 | /* Send the READ command (opcode + addr) */ | |
846 | e1000_shift_out_ee_bits(hw, | |
847 | EEPROM_READ_OPCODE_MICROWIRE, | |
848 | eeprom->opcode_bits); | |
849 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), | |
850 | eeprom->address_bits); | |
851 | ||
852 | /* Read the data. For microwire, each word requires | |
853 | * the overhead of eeprom setup and tear-down. */ | |
854 | data[i] = e1000_shift_in_ee_bits(hw, 16); | |
855 | e1000_standby_eeprom(hw); | |
856 | } | |
857 | } | |
858 | ||
859 | /* End this read operation */ | |
860 | e1000_release_eeprom(hw); | |
861 | ||
862 | return E1000_SUCCESS; | |
863 | } | |
864 | ||
f1bcad22 HL |
865 | #ifndef CONFIG_DM_ETH |
866 | /****************************************************************************** | |
867 | * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR | |
868 | * @hw: pointer to the HW structure | |
869 | * @offset: offset within the Shadow Ram to be written to | |
870 | * @words: number of words to write | |
871 | * @data: 16 bit word(s) to be written to the Shadow Ram | |
872 | * | |
873 | * Writes data to Shadow Ram at offset using EEWR register. | |
874 | * | |
875 | * If e1000_update_eeprom_checksum_i210 is not called after this function, the | |
876 | * Shadow Ram will most likely contain an invalid checksum. | |
877 | *****************************************************************************/ | |
878 | static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset, | |
879 | uint16_t words, uint16_t *data) | |
880 | { | |
881 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
882 | uint32_t i, k, eewr = 0; | |
883 | uint32_t attempts = 100000; | |
884 | int32_t ret_val = 0; | |
885 | ||
886 | /* A check for invalid values: offset too large, too many words, | |
887 | * too many words for the offset, and not enough words. | |
888 | */ | |
889 | if ((offset >= eeprom->word_size) || | |
890 | (words > (eeprom->word_size - offset)) || (words == 0)) { | |
891 | DEBUGOUT("nvm parameter(s) out of bounds\n"); | |
892 | ret_val = -E1000_ERR_EEPROM; | |
893 | goto out; | |
894 | } | |
895 | ||
896 | for (i = 0; i < words; i++) { | |
897 | eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | |
898 | | (data[i] << E1000_EEPROM_RW_REG_DATA) | | |
899 | E1000_EEPROM_RW_REG_START; | |
900 | ||
901 | E1000_WRITE_REG(hw, I210_EEWR, eewr); | |
902 | ||
903 | for (k = 0; k < attempts; k++) { | |
904 | if (E1000_EEPROM_RW_REG_DONE & | |
905 | E1000_READ_REG(hw, I210_EEWR)) { | |
906 | ret_val = 0; | |
907 | break; | |
908 | } | |
909 | udelay(5); | |
910 | } | |
911 | ||
912 | if (ret_val) { | |
913 | DEBUGOUT("Shadow RAM write EEWR timed out\n"); | |
914 | break; | |
915 | } | |
916 | } | |
917 | ||
918 | out: | |
919 | return ret_val; | |
920 | } | |
921 | ||
922 | /****************************************************************************** | |
923 | * e1000_pool_flash_update_done_i210 - Pool FLUDONE status. | |
924 | * @hw: pointer to the HW structure | |
925 | * | |
926 | *****************************************************************************/ | |
927 | static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw) | |
928 | { | |
929 | int32_t ret_val = -E1000_ERR_EEPROM; | |
930 | uint32_t i, reg; | |
931 | ||
932 | for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) { | |
933 | reg = E1000_READ_REG(hw, EECD); | |
934 | if (reg & E1000_EECD_FLUDONE_I210) { | |
935 | ret_val = 0; | |
936 | break; | |
937 | } | |
938 | udelay(5); | |
939 | } | |
940 | ||
941 | return ret_val; | |
942 | } | |
943 | ||
944 | /****************************************************************************** | |
945 | * e1000_update_flash_i210 - Commit EEPROM to the flash | |
946 | * @hw: pointer to the HW structure | |
947 | * | |
948 | *****************************************************************************/ | |
949 | static int32_t e1000_update_flash_i210(struct e1000_hw *hw) | |
950 | { | |
951 | int32_t ret_val = 0; | |
952 | uint32_t flup; | |
953 | ||
954 | ret_val = e1000_pool_flash_update_done_i210(hw); | |
955 | if (ret_val == -E1000_ERR_EEPROM) { | |
956 | DEBUGOUT("Flash update time out\n"); | |
957 | goto out; | |
958 | } | |
959 | ||
960 | flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210; | |
961 | E1000_WRITE_REG(hw, EECD, flup); | |
962 | ||
963 | ret_val = e1000_pool_flash_update_done_i210(hw); | |
964 | if (ret_val) | |
965 | DEBUGOUT("Flash update time out\n"); | |
966 | else | |
967 | DEBUGOUT("Flash update complete\n"); | |
968 | ||
969 | out: | |
970 | return ret_val; | |
971 | } | |
972 | ||
973 | /****************************************************************************** | |
974 | * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum | |
975 | * @hw: pointer to the HW structure | |
976 | * | |
977 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
978 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
979 | * value to the EEPROM. Next commit EEPROM data onto the Flash. | |
980 | *****************************************************************************/ | |
981 | static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw) | |
982 | { | |
983 | int32_t ret_val = 0; | |
984 | uint16_t checksum = 0; | |
985 | uint16_t i, nvm_data; | |
986 | ||
987 | /* Read the first word from the EEPROM. If this times out or fails, do | |
988 | * not continue or we could be in for a very long wait while every | |
989 | * EEPROM read fails | |
990 | */ | |
991 | ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data); | |
992 | if (ret_val) { | |
993 | DEBUGOUT("EEPROM read failed\n"); | |
994 | goto out; | |
995 | } | |
996 | ||
997 | if (!(e1000_get_hw_eeprom_semaphore(hw))) { | |
998 | /* Do not use hw->nvm.ops.write, hw->nvm.ops.read | |
999 | * because we do not want to take the synchronization | |
1000 | * semaphores twice here. | |
1001 | */ | |
1002 | ||
1003 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { | |
1004 | ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data); | |
1005 | if (ret_val) { | |
1006 | e1000_put_hw_eeprom_semaphore(hw); | |
1007 | DEBUGOUT("EEPROM Read Error while updating checksum.\n"); | |
1008 | goto out; | |
1009 | } | |
1010 | checksum += nvm_data; | |
1011 | } | |
1012 | checksum = (uint16_t)EEPROM_SUM - checksum; | |
1013 | ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1, | |
1014 | &checksum); | |
1015 | if (ret_val) { | |
1016 | e1000_put_hw_eeprom_semaphore(hw); | |
1017 | DEBUGOUT("EEPROM Write Error while updating checksum.\n"); | |
1018 | goto out; | |
1019 | } | |
1020 | ||
1021 | e1000_put_hw_eeprom_semaphore(hw); | |
1022 | ||
1023 | ret_val = e1000_update_flash_i210(hw); | |
1024 | } else { | |
1025 | ret_val = -E1000_ERR_SWFW_SYNC; | |
1026 | } | |
1027 | ||
1028 | out: | |
1029 | return ret_val; | |
1030 | } | |
1031 | #endif | |
1032 | ||
aa070789 RZ |
1033 | /****************************************************************************** |
1034 | * Verifies that the EEPROM has a valid checksum | |
1035 | * | |
1036 | * hw - Struct containing variables accessed by shared code | |
1037 | * | |
1038 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. | |
1039 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is | |
1040 | * valid. | |
1041 | *****************************************************************************/ | |
114d7fc0 | 1042 | static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
aa070789 | 1043 | { |
114d7fc0 | 1044 | uint16_t i, checksum, checksum_reg, *buf; |
aa070789 RZ |
1045 | |
1046 | DEBUGFUNC(); | |
1047 | ||
114d7fc0 KM |
1048 | /* Allocate a temporary buffer */ |
1049 | buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); | |
1050 | if (!buf) { | |
5c5e707a | 1051 | E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); |
114d7fc0 | 1052 | return -E1000_ERR_EEPROM; |
aa070789 RZ |
1053 | } |
1054 | ||
114d7fc0 KM |
1055 | /* Read the EEPROM */ |
1056 | if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { | |
5c5e707a | 1057 | E1000_ERR(hw, "Unable to read EEPROM!\n"); |
aa070789 RZ |
1058 | return -E1000_ERR_EEPROM; |
1059 | } | |
114d7fc0 KM |
1060 | |
1061 | /* Compute the checksum */ | |
7a341066 | 1062 | checksum = 0; |
114d7fc0 KM |
1063 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) |
1064 | checksum += buf[i]; | |
1065 | checksum = ((uint16_t)EEPROM_SUM) - checksum; | |
1066 | checksum_reg = buf[i]; | |
1067 | ||
1068 | /* Verify it! */ | |
1069 | if (checksum == checksum_reg) | |
1070 | return 0; | |
1071 | ||
1072 | /* Hrm, verification failed, print an error */ | |
5c5e707a SG |
1073 | E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); |
1074 | E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", | |
1075 | checksum_reg, checksum); | |
114d7fc0 KM |
1076 | |
1077 | return -E1000_ERR_EEPROM; | |
aa070789 | 1078 | } |
8712adfd | 1079 | #endif /* CONFIG_E1000_NO_NVM */ |
ecbd2078 RZ |
1080 | |
1081 | /***************************************************************************** | |
1082 | * Set PHY to class A mode | |
1083 | * Assumes the following operations will follow to enable the new class mode. | |
1084 | * 1. Do a PHY soft reset | |
1085 | * 2. Restart auto-negotiation or force link. | |
1086 | * | |
1087 | * hw - Struct containing variables accessed by shared code | |
1088 | ****************************************************************************/ | |
1089 | static int32_t | |
1090 | e1000_set_phy_mode(struct e1000_hw *hw) | |
1091 | { | |
8712adfd | 1092 | #ifndef CONFIG_E1000_NO_NVM |
ecbd2078 RZ |
1093 | int32_t ret_val; |
1094 | uint16_t eeprom_data; | |
1095 | ||
1096 | DEBUGFUNC(); | |
1097 | ||
1098 | if ((hw->mac_type == e1000_82545_rev_3) && | |
1099 | (hw->media_type == e1000_media_type_copper)) { | |
1100 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, | |
1101 | 1, &eeprom_data); | |
1102 | if (ret_val) | |
1103 | return ret_val; | |
1104 | ||
1105 | if ((eeprom_data != EEPROM_RESERVED_WORD) && | |
1106 | (eeprom_data & EEPROM_PHY_CLASS_A)) { | |
1107 | ret_val = e1000_write_phy_reg(hw, | |
1108 | M88E1000_PHY_PAGE_SELECT, 0x000B); | |
1109 | if (ret_val) | |
1110 | return ret_val; | |
1111 | ret_val = e1000_write_phy_reg(hw, | |
1112 | M88E1000_PHY_GEN_CONTROL, 0x8104); | |
1113 | if (ret_val) | |
1114 | return ret_val; | |
1115 | ||
472d5460 | 1116 | hw->phy_reset_disable = false; |
ecbd2078 RZ |
1117 | } |
1118 | } | |
8712adfd | 1119 | #endif |
ecbd2078 RZ |
1120 | return E1000_SUCCESS; |
1121 | } | |
aa070789 | 1122 | |
8712adfd | 1123 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 RZ |
1124 | /*************************************************************************** |
1125 | * | |
1126 | * Obtaining software semaphore bit (SMBI) before resetting PHY. | |
1127 | * | |
1128 | * hw: Struct containing variables accessed by shared code | |
1129 | * | |
1130 | * returns: - E1000_ERR_RESET if fail to obtain semaphore. | |
1131 | * E1000_SUCCESS at any other case. | |
1132 | * | |
1133 | ***************************************************************************/ | |
1134 | static int32_t | |
1135 | e1000_get_software_semaphore(struct e1000_hw *hw) | |
1136 | { | |
1137 | int32_t timeout = hw->eeprom.word_size + 1; | |
1138 | uint32_t swsm; | |
1139 | ||
1140 | DEBUGFUNC(); | |
1141 | ||
f1bcad22 | 1142 | if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb) |
aa070789 RZ |
1143 | return E1000_SUCCESS; |
1144 | ||
1145 | while (timeout) { | |
1146 | swsm = E1000_READ_REG(hw, SWSM); | |
1147 | /* If SMBI bit cleared, it is now set and we hold | |
1148 | * the semaphore */ | |
1149 | if (!(swsm & E1000_SWSM_SMBI)) | |
1150 | break; | |
1151 | mdelay(1); | |
1152 | timeout--; | |
1153 | } | |
1154 | ||
1155 | if (!timeout) { | |
1156 | DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); | |
1157 | return -E1000_ERR_RESET; | |
1158 | } | |
1159 | ||
1160 | return E1000_SUCCESS; | |
1161 | } | |
8712adfd | 1162 | #endif |
aa070789 RZ |
1163 | |
1164 | /*************************************************************************** | |
1165 | * This function clears HW semaphore bits. | |
1166 | * | |
1167 | * hw: Struct containing variables accessed by shared code | |
1168 | * | |
1169 | * returns: - None. | |
1170 | * | |
1171 | ***************************************************************************/ | |
1172 | static void | |
1173 | e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) | |
1174 | { | |
8712adfd | 1175 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 RZ |
1176 | uint32_t swsm; |
1177 | ||
1178 | DEBUGFUNC(); | |
1179 | ||
1180 | if (!hw->eeprom_semaphore_present) | |
1181 | return; | |
1182 | ||
1183 | swsm = E1000_READ_REG(hw, SWSM); | |
1184 | if (hw->mac_type == e1000_80003es2lan) { | |
1185 | /* Release both semaphores. */ | |
1186 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); | |
1187 | } else | |
1188 | swsm &= ~(E1000_SWSM_SWESMBI); | |
1189 | E1000_WRITE_REG(hw, SWSM, swsm); | |
8712adfd | 1190 | #endif |
aa070789 RZ |
1191 | } |
1192 | ||
1193 | /*************************************************************************** | |
1194 | * | |
1195 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting | |
1196 | * adapter or Eeprom access. | |
1197 | * | |
1198 | * hw: Struct containing variables accessed by shared code | |
1199 | * | |
1200 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. | |
1201 | * E1000_SUCCESS at any other case. | |
1202 | * | |
1203 | ***************************************************************************/ | |
1204 | static int32_t | |
1205 | e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) | |
1206 | { | |
8712adfd | 1207 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 RZ |
1208 | int32_t timeout; |
1209 | uint32_t swsm; | |
1210 | ||
1211 | DEBUGFUNC(); | |
1212 | ||
1213 | if (!hw->eeprom_semaphore_present) | |
1214 | return E1000_SUCCESS; | |
1215 | ||
f1bcad22 | 1216 | if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) { |
aa070789 RZ |
1217 | /* Get the SW semaphore. */ |
1218 | if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) | |
1219 | return -E1000_ERR_EEPROM; | |
1220 | } | |
1221 | ||
1222 | /* Get the FW semaphore. */ | |
1223 | timeout = hw->eeprom.word_size + 1; | |
1224 | while (timeout) { | |
1225 | swsm = E1000_READ_REG(hw, SWSM); | |
1226 | swsm |= E1000_SWSM_SWESMBI; | |
1227 | E1000_WRITE_REG(hw, SWSM, swsm); | |
1228 | /* if we managed to set the bit we got the semaphore. */ | |
1229 | swsm = E1000_READ_REG(hw, SWSM); | |
1230 | if (swsm & E1000_SWSM_SWESMBI) | |
1231 | break; | |
1232 | ||
1233 | udelay(50); | |
1234 | timeout--; | |
1235 | } | |
1236 | ||
1237 | if (!timeout) { | |
1238 | /* Release semaphores */ | |
1239 | e1000_put_hw_eeprom_semaphore(hw); | |
1240 | DEBUGOUT("Driver can't access the Eeprom - " | |
1241 | "SWESMBI bit is set.\n"); | |
1242 | return -E1000_ERR_EEPROM; | |
1243 | } | |
8712adfd | 1244 | #endif |
aa070789 RZ |
1245 | return E1000_SUCCESS; |
1246 | } | |
1247 | ||
7e2d991d | 1248 | /* Take ownership of the PHY */ |
aa070789 RZ |
1249 | static int32_t |
1250 | e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) | |
1251 | { | |
1252 | uint32_t swfw_sync = 0; | |
1253 | uint32_t swmask = mask; | |
1254 | uint32_t fwmask = mask << 16; | |
1255 | int32_t timeout = 200; | |
1256 | ||
1257 | DEBUGFUNC(); | |
1258 | while (timeout) { | |
1259 | if (e1000_get_hw_eeprom_semaphore(hw)) | |
1260 | return -E1000_ERR_SWFW_SYNC; | |
1261 | ||
3c63dd53 | 1262 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
76f8cdb2 | 1263 | if (!(swfw_sync & (fwmask | swmask))) |
aa070789 RZ |
1264 | break; |
1265 | ||
1266 | /* firmware currently using resource (fwmask) */ | |
1267 | /* or other software thread currently using resource (swmask) */ | |
1268 | e1000_put_hw_eeprom_semaphore(hw); | |
1269 | mdelay(5); | |
1270 | timeout--; | |
1271 | } | |
1272 | ||
1273 | if (!timeout) { | |
1274 | DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); | |
1275 | return -E1000_ERR_SWFW_SYNC; | |
1276 | } | |
1277 | ||
1278 | swfw_sync |= swmask; | |
1279 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); | |
1280 | ||
1281 | e1000_put_hw_eeprom_semaphore(hw); | |
1282 | return E1000_SUCCESS; | |
1283 | } | |
1284 | ||
7e2d991d TH |
1285 | static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) |
1286 | { | |
1287 | uint32_t swfw_sync = 0; | |
1288 | ||
1289 | DEBUGFUNC(); | |
1290 | while (e1000_get_hw_eeprom_semaphore(hw)) | |
1291 | ; /* Empty */ | |
1292 | ||
1293 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); | |
1294 | swfw_sync &= ~mask; | |
1295 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); | |
1296 | ||
1297 | e1000_put_hw_eeprom_semaphore(hw); | |
1298 | } | |
1299 | ||
472d5460 | 1300 | static bool e1000_is_second_port(struct e1000_hw *hw) |
987b43a1 KM |
1301 | { |
1302 | switch (hw->mac_type) { | |
1303 | case e1000_80003es2lan: | |
1304 | case e1000_82546: | |
1305 | case e1000_82571: | |
1306 | if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) | |
472d5460 | 1307 | return true; |
987b43a1 KM |
1308 | /* Fallthrough */ |
1309 | default: | |
472d5460 | 1310 | return false; |
987b43a1 KM |
1311 | } |
1312 | } | |
1313 | ||
8712adfd | 1314 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 | 1315 | /****************************************************************************** |
e0a75fed | 1316 | * Reads the adapter's MAC address from the EEPROM |
aa070789 | 1317 | * |
e0a75fed HL |
1318 | * hw - Struct containing variables accessed by shared code |
1319 | * enetaddr - buffering where the MAC address will be stored | |
aa070789 | 1320 | *****************************************************************************/ |
e0a75fed HL |
1321 | static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw, |
1322 | unsigned char enetaddr[6]) | |
aa070789 | 1323 | { |
aa070789 RZ |
1324 | uint16_t offset; |
1325 | uint16_t eeprom_data; | |
1326 | int i; | |
1327 | ||
aa070789 RZ |
1328 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
1329 | offset = i >> 1; | |
e0a75fed | 1330 | if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
682011ff WD |
1331 | DEBUGOUT("EEPROM Read Error\n"); |
1332 | return -E1000_ERR_EEPROM; | |
1333 | } | |
5c5e707a SG |
1334 | enetaddr[i] = eeprom_data & 0xff; |
1335 | enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; | |
682011ff | 1336 | } |
987b43a1 | 1337 | |
e0a75fed HL |
1338 | return 0; |
1339 | } | |
1340 | ||
1341 | /****************************************************************************** | |
1342 | * Reads the adapter's MAC address from the RAL/RAH registers | |
1343 | * | |
1344 | * hw - Struct containing variables accessed by shared code | |
1345 | * enetaddr - buffering where the MAC address will be stored | |
1346 | *****************************************************************************/ | |
1347 | static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw, | |
1348 | unsigned char enetaddr[6]) | |
1349 | { | |
1350 | uint16_t offset, tmp; | |
1351 | uint32_t reg_data = 0; | |
1352 | int i; | |
1353 | ||
1354 | if (hw->mac_type != e1000_igb) | |
1355 | return -E1000_ERR_MAC_TYPE; | |
1356 | ||
1357 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { | |
1358 | offset = i >> 1; | |
1359 | ||
1360 | if (offset == 0) | |
1361 | reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); | |
1362 | else if (offset == 1) | |
1363 | reg_data >>= 16; | |
1364 | else if (offset == 2) | |
1365 | reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); | |
1366 | tmp = reg_data & 0xffff; | |
1367 | ||
1368 | enetaddr[i] = tmp & 0xff; | |
1369 | enetaddr[i + 1] = (tmp >> 8) & 0xff; | |
1370 | } | |
1371 | ||
1372 | return 0; | |
1373 | } | |
1374 | ||
1375 | /****************************************************************************** | |
1376 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the | |
1377 | * second function of dual function devices | |
1378 | * | |
1379 | * hw - Struct containing variables accessed by shared code | |
1380 | * enetaddr - buffering where the MAC address will be stored | |
1381 | *****************************************************************************/ | |
1382 | static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) | |
1383 | { | |
1384 | int ret_val; | |
1385 | ||
1386 | if (hw->mac_type == e1000_igb) { | |
1387 | /* i210 preloads MAC address into RAL/RAH registers */ | |
1388 | ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr); | |
1389 | } else { | |
1390 | ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr); | |
1391 | } | |
1392 | if (ret_val) | |
1393 | return ret_val; | |
1394 | ||
987b43a1 KM |
1395 | /* Invert the last bit if this is the second device */ |
1396 | if (e1000_is_second_port(hw)) | |
5c5e707a | 1397 | enetaddr[5] ^= 1; |
987b43a1 | 1398 | |
682011ff WD |
1399 | return 0; |
1400 | } | |
8712adfd | 1401 | #endif |
682011ff WD |
1402 | |
1403 | /****************************************************************************** | |
1404 | * Initializes receive address filters. | |
1405 | * | |
8bde7f77 | 1406 | * hw - Struct containing variables accessed by shared code |
682011ff WD |
1407 | * |
1408 | * Places the MAC address in receive address register 0 and clears the rest | |
1409 | * of the receive addresss registers. Clears the multicast table. Assumes | |
1410 | * the receiver is in reset when the routine is called. | |
1411 | *****************************************************************************/ | |
1412 | static void | |
5c5e707a | 1413 | e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) |
682011ff | 1414 | { |
682011ff WD |
1415 | uint32_t i; |
1416 | uint32_t addr_low; | |
1417 | uint32_t addr_high; | |
1418 | ||
1419 | DEBUGFUNC(); | |
1420 | ||
1421 | /* Setup the receive address. */ | |
1422 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); | |
5c5e707a SG |
1423 | addr_low = (enetaddr[0] | |
1424 | (enetaddr[1] << 8) | | |
1425 | (enetaddr[2] << 16) | (enetaddr[3] << 24)); | |
682011ff | 1426 | |
5c5e707a | 1427 | addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV); |
682011ff WD |
1428 | |
1429 | E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); | |
1430 | E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); | |
1431 | ||
1432 | /* Zero out the other 15 receive addresses. */ | |
1433 | DEBUGOUT("Clearing RAR[1-15]\n"); | |
1434 | for (i = 1; i < E1000_RAR_ENTRIES; i++) { | |
1435 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); | |
1436 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | |
1437 | } | |
1438 | } | |
1439 | ||
1440 | /****************************************************************************** | |
1441 | * Clears the VLAN filer table | |
1442 | * | |
1443 | * hw - Struct containing variables accessed by shared code | |
1444 | *****************************************************************************/ | |
1445 | static void | |
1446 | e1000_clear_vfta(struct e1000_hw *hw) | |
1447 | { | |
1448 | uint32_t offset; | |
1449 | ||
1450 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) | |
1451 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); | |
1452 | } | |
1453 | ||
1454 | /****************************************************************************** | |
1455 | * Set the mac type member in the hw struct. | |
8bde7f77 | 1456 | * |
682011ff WD |
1457 | * hw - Struct containing variables accessed by shared code |
1458 | *****************************************************************************/ | |
aa070789 | 1459 | int32_t |
682011ff WD |
1460 | e1000_set_mac_type(struct e1000_hw *hw) |
1461 | { | |
1462 | DEBUGFUNC(); | |
1463 | ||
1464 | switch (hw->device_id) { | |
1465 | case E1000_DEV_ID_82542: | |
1466 | switch (hw->revision_id) { | |
1467 | case E1000_82542_2_0_REV_ID: | |
1468 | hw->mac_type = e1000_82542_rev2_0; | |
1469 | break; | |
1470 | case E1000_82542_2_1_REV_ID: | |
1471 | hw->mac_type = e1000_82542_rev2_1; | |
1472 | break; | |
1473 | default: | |
1474 | /* Invalid 82542 revision ID */ | |
1475 | return -E1000_ERR_MAC_TYPE; | |
1476 | } | |
1477 | break; | |
1478 | case E1000_DEV_ID_82543GC_FIBER: | |
1479 | case E1000_DEV_ID_82543GC_COPPER: | |
1480 | hw->mac_type = e1000_82543; | |
1481 | break; | |
1482 | case E1000_DEV_ID_82544EI_COPPER: | |
1483 | case E1000_DEV_ID_82544EI_FIBER: | |
1484 | case E1000_DEV_ID_82544GC_COPPER: | |
1485 | case E1000_DEV_ID_82544GC_LOM: | |
1486 | hw->mac_type = e1000_82544; | |
1487 | break; | |
1488 | case E1000_DEV_ID_82540EM: | |
1489 | case E1000_DEV_ID_82540EM_LOM: | |
aa070789 RZ |
1490 | case E1000_DEV_ID_82540EP: |
1491 | case E1000_DEV_ID_82540EP_LOM: | |
1492 | case E1000_DEV_ID_82540EP_LP: | |
682011ff WD |
1493 | hw->mac_type = e1000_82540; |
1494 | break; | |
1495 | case E1000_DEV_ID_82545EM_COPPER: | |
1496 | case E1000_DEV_ID_82545EM_FIBER: | |
1497 | hw->mac_type = e1000_82545; | |
1498 | break; | |
aa070789 RZ |
1499 | case E1000_DEV_ID_82545GM_COPPER: |
1500 | case E1000_DEV_ID_82545GM_FIBER: | |
1501 | case E1000_DEV_ID_82545GM_SERDES: | |
1502 | hw->mac_type = e1000_82545_rev_3; | |
1503 | break; | |
682011ff WD |
1504 | case E1000_DEV_ID_82546EB_COPPER: |
1505 | case E1000_DEV_ID_82546EB_FIBER: | |
aa070789 | 1506 | case E1000_DEV_ID_82546EB_QUAD_COPPER: |
682011ff WD |
1507 | hw->mac_type = e1000_82546; |
1508 | break; | |
aa070789 RZ |
1509 | case E1000_DEV_ID_82546GB_COPPER: |
1510 | case E1000_DEV_ID_82546GB_FIBER: | |
1511 | case E1000_DEV_ID_82546GB_SERDES: | |
1512 | case E1000_DEV_ID_82546GB_PCIE: | |
1513 | case E1000_DEV_ID_82546GB_QUAD_COPPER: | |
1514 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: | |
1515 | hw->mac_type = e1000_82546_rev_3; | |
1516 | break; | |
1517 | case E1000_DEV_ID_82541EI: | |
1518 | case E1000_DEV_ID_82541EI_MOBILE: | |
1519 | case E1000_DEV_ID_82541ER_LOM: | |
1520 | hw->mac_type = e1000_82541; | |
1521 | break; | |
ac3315c2 | 1522 | case E1000_DEV_ID_82541ER: |
aa070789 | 1523 | case E1000_DEV_ID_82541GI: |
aa3b8bf9 | 1524 | case E1000_DEV_ID_82541GI_LF: |
aa070789 | 1525 | case E1000_DEV_ID_82541GI_MOBILE: |
1aeed8d7 WD |
1526 | hw->mac_type = e1000_82541_rev_2; |
1527 | break; | |
aa070789 RZ |
1528 | case E1000_DEV_ID_82547EI: |
1529 | case E1000_DEV_ID_82547EI_MOBILE: | |
1530 | hw->mac_type = e1000_82547; | |
1531 | break; | |
1532 | case E1000_DEV_ID_82547GI: | |
1533 | hw->mac_type = e1000_82547_rev_2; | |
1534 | break; | |
1535 | case E1000_DEV_ID_82571EB_COPPER: | |
1536 | case E1000_DEV_ID_82571EB_FIBER: | |
1537 | case E1000_DEV_ID_82571EB_SERDES: | |
1538 | case E1000_DEV_ID_82571EB_SERDES_DUAL: | |
1539 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
1540 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
1541 | case E1000_DEV_ID_82571PT_QUAD_COPPER: | |
1542 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
1543 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: | |
1544 | hw->mac_type = e1000_82571; | |
1545 | break; | |
1546 | case E1000_DEV_ID_82572EI_COPPER: | |
1547 | case E1000_DEV_ID_82572EI_FIBER: | |
1548 | case E1000_DEV_ID_82572EI_SERDES: | |
1549 | case E1000_DEV_ID_82572EI: | |
1550 | hw->mac_type = e1000_82572; | |
1551 | break; | |
1552 | case E1000_DEV_ID_82573E: | |
1553 | case E1000_DEV_ID_82573E_IAMT: | |
1554 | case E1000_DEV_ID_82573L: | |
1555 | hw->mac_type = e1000_82573; | |
1556 | break; | |
2c2668f9 RZ |
1557 | case E1000_DEV_ID_82574L: |
1558 | hw->mac_type = e1000_82574; | |
1559 | break; | |
aa070789 RZ |
1560 | case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: |
1561 | case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: | |
1562 | case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: | |
1563 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
1564 | hw->mac_type = e1000_80003es2lan; | |
1565 | break; | |
1566 | case E1000_DEV_ID_ICH8_IGP_M_AMT: | |
1567 | case E1000_DEV_ID_ICH8_IGP_AMT: | |
1568 | case E1000_DEV_ID_ICH8_IGP_C: | |
1569 | case E1000_DEV_ID_ICH8_IFE: | |
1570 | case E1000_DEV_ID_ICH8_IFE_GT: | |
1571 | case E1000_DEV_ID_ICH8_IFE_G: | |
1572 | case E1000_DEV_ID_ICH8_IGP_M: | |
1573 | hw->mac_type = e1000_ich8lan; | |
1574 | break; | |
6c499abe MZ |
1575 | case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: |
1576 | case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: | |
95186063 | 1577 | case PCI_DEVICE_ID_INTEL_I210_COPPER: |
6c499abe | 1578 | case PCI_DEVICE_ID_INTEL_I211_COPPER: |
95186063 MV |
1579 | case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: |
1580 | case PCI_DEVICE_ID_INTEL_I210_SERDES: | |
1581 | case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: | |
1582 | case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: | |
1583 | hw->mac_type = e1000_igb; | |
1584 | break; | |
682011ff WD |
1585 | default: |
1586 | /* Should never have loaded on this device */ | |
1587 | return -E1000_ERR_MAC_TYPE; | |
1588 | } | |
1589 | return E1000_SUCCESS; | |
1590 | } | |
1591 | ||
1592 | /****************************************************************************** | |
1593 | * Reset the transmit and receive units; mask and clear all interrupts. | |
1594 | * | |
1595 | * hw - Struct containing variables accessed by shared code | |
1596 | *****************************************************************************/ | |
1597 | void | |
1598 | e1000_reset_hw(struct e1000_hw *hw) | |
1599 | { | |
1600 | uint32_t ctrl; | |
1601 | uint32_t ctrl_ext; | |
682011ff | 1602 | uint32_t manc; |
9ea005fb | 1603 | uint32_t pba = 0; |
95186063 | 1604 | uint32_t reg; |
682011ff WD |
1605 | |
1606 | DEBUGFUNC(); | |
1607 | ||
9ea005fb RZ |
1608 | /* get the correct pba value for both PCI and PCIe*/ |
1609 | if (hw->mac_type < e1000_82571) | |
1610 | pba = E1000_DEFAULT_PCI_PBA; | |
1611 | else | |
1612 | pba = E1000_DEFAULT_PCIE_PBA; | |
1613 | ||
682011ff WD |
1614 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
1615 | if (hw->mac_type == e1000_82542_rev2_0) { | |
1616 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | |
81dab9af BM |
1617 | #ifdef CONFIG_DM_ETH |
1618 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, | |
1619 | hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); | |
1620 | #else | |
682011ff | 1621 | pci_write_config_word(hw->pdev, PCI_COMMAND, |
aa070789 | 1622 | hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); |
81dab9af | 1623 | #endif |
682011ff WD |
1624 | } |
1625 | ||
1626 | /* Clear interrupt mask to stop board from generating interrupts */ | |
1627 | DEBUGOUT("Masking off all interrupts\n"); | |
95186063 MV |
1628 | if (hw->mac_type == e1000_igb) |
1629 | E1000_WRITE_REG(hw, I210_IAM, 0); | |
682011ff WD |
1630 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
1631 | ||
1632 | /* Disable the Transmit and Receive units. Then delay to allow | |
1633 | * any pending transactions to complete before we hit the MAC with | |
1634 | * the global reset. | |
1635 | */ | |
1636 | E1000_WRITE_REG(hw, RCTL, 0); | |
1637 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); | |
1638 | E1000_WRITE_FLUSH(hw); | |
1639 | ||
1640 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ | |
472d5460 | 1641 | hw->tbi_compatibility_on = false; |
682011ff WD |
1642 | |
1643 | /* Delay to allow any outstanding PCI transactions to complete before | |
1644 | * resetting the device | |
1645 | */ | |
1646 | mdelay(10); | |
1647 | ||
1648 | /* Issue a global reset to the MAC. This will reset the chip's | |
1649 | * transmit, receive, DMA, and link units. It will not effect | |
1650 | * the current PCI configuration. The global reset bit is self- | |
1651 | * clearing, and should clear within a microsecond. | |
1652 | */ | |
1653 | DEBUGOUT("Issuing a global reset to MAC\n"); | |
1654 | ctrl = E1000_READ_REG(hw, CTRL); | |
1655 | ||
aa070789 | 1656 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
682011ff WD |
1657 | |
1658 | /* Force a reload from the EEPROM if necessary */ | |
95186063 MV |
1659 | if (hw->mac_type == e1000_igb) { |
1660 | mdelay(20); | |
1661 | reg = E1000_READ_REG(hw, STATUS); | |
1662 | if (reg & E1000_STATUS_PF_RST_DONE) | |
1663 | DEBUGOUT("PF OK\n"); | |
1664 | reg = E1000_READ_REG(hw, I210_EECD); | |
1665 | if (reg & E1000_EECD_AUTO_RD) | |
1666 | DEBUGOUT("EEC OK\n"); | |
1667 | } else if (hw->mac_type < e1000_82540) { | |
682011ff WD |
1668 | /* Wait for reset to complete */ |
1669 | udelay(10); | |
1670 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
1671 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
1672 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
1673 | E1000_WRITE_FLUSH(hw); | |
1674 | /* Wait for EEPROM reload */ | |
1675 | mdelay(2); | |
1676 | } else { | |
1677 | /* Wait for EEPROM reload (it happens automatically) */ | |
1678 | mdelay(4); | |
1679 | /* Dissable HW ARPs on ASF enabled adapters */ | |
1680 | manc = E1000_READ_REG(hw, MANC); | |
1681 | manc &= ~(E1000_MANC_ARP_EN); | |
1682 | E1000_WRITE_REG(hw, MANC, manc); | |
1683 | } | |
1684 | ||
1685 | /* Clear interrupt mask to stop board from generating interrupts */ | |
1686 | DEBUGOUT("Masking off all interrupts\n"); | |
95186063 MV |
1687 | if (hw->mac_type == e1000_igb) |
1688 | E1000_WRITE_REG(hw, I210_IAM, 0); | |
682011ff WD |
1689 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
1690 | ||
1691 | /* Clear any pending interrupt events. */ | |
56b13b1e | 1692 | E1000_READ_REG(hw, ICR); |
682011ff WD |
1693 | |
1694 | /* If MWI was previously enabled, reenable it. */ | |
1695 | if (hw->mac_type == e1000_82542_rev2_0) { | |
81dab9af BM |
1696 | #ifdef CONFIG_DM_ETH |
1697 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); | |
1698 | #else | |
682011ff | 1699 | pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); |
81dab9af | 1700 | #endif |
682011ff | 1701 | } |
95186063 MV |
1702 | if (hw->mac_type != e1000_igb) |
1703 | E1000_WRITE_REG(hw, PBA, pba); | |
aa070789 RZ |
1704 | } |
1705 | ||
1706 | /****************************************************************************** | |
1707 | * | |
1708 | * Initialize a number of hardware-dependent bits | |
1709 | * | |
1710 | * hw: Struct containing variables accessed by shared code | |
1711 | * | |
1712 | * This function contains hardware limitation workarounds for PCI-E adapters | |
1713 | * | |
1714 | *****************************************************************************/ | |
1715 | static void | |
1716 | e1000_initialize_hardware_bits(struct e1000_hw *hw) | |
1717 | { | |
1718 | if ((hw->mac_type >= e1000_82571) && | |
1719 | (!hw->initialize_hw_bits_disable)) { | |
1720 | /* Settings common to all PCI-express silicon */ | |
1721 | uint32_t reg_ctrl, reg_ctrl_ext; | |
1722 | uint32_t reg_tarc0, reg_tarc1; | |
1723 | uint32_t reg_tctl; | |
1724 | uint32_t reg_txdctl, reg_txdctl1; | |
1725 | ||
1726 | /* link autonegotiation/sync workarounds */ | |
1727 | reg_tarc0 = E1000_READ_REG(hw, TARC0); | |
1728 | reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); | |
1729 | ||
1730 | /* Enable not-done TX descriptor counting */ | |
1731 | reg_txdctl = E1000_READ_REG(hw, TXDCTL); | |
1732 | reg_txdctl |= E1000_TXDCTL_COUNT_DESC; | |
1733 | E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); | |
1734 | ||
1735 | reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); | |
1736 | reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; | |
1737 | E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); | |
1738 | ||
95186063 | 1739 | |
aa070789 | 1740 | switch (hw->mac_type) { |
063bb708 AP |
1741 | case e1000_igb: /* IGB is cool */ |
1742 | return; | |
aa070789 RZ |
1743 | case e1000_82571: |
1744 | case e1000_82572: | |
1745 | /* Clear PHY TX compatible mode bits */ | |
1746 | reg_tarc1 = E1000_READ_REG(hw, TARC1); | |
1747 | reg_tarc1 &= ~((1 << 30)|(1 << 29)); | |
1748 | ||
1749 | /* link autonegotiation/sync workarounds */ | |
1750 | reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); | |
1751 | ||
1752 | /* TX ring control fixes */ | |
1753 | reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); | |
1754 | ||
1755 | /* Multiple read bit is reversed polarity */ | |
1756 | reg_tctl = E1000_READ_REG(hw, TCTL); | |
1757 | if (reg_tctl & E1000_TCTL_MULR) | |
1758 | reg_tarc1 &= ~(1 << 28); | |
1759 | else | |
1760 | reg_tarc1 |= (1 << 28); | |
1761 | ||
1762 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); | |
1763 | break; | |
1764 | case e1000_82573: | |
2c2668f9 | 1765 | case e1000_82574: |
aa070789 RZ |
1766 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
1767 | reg_ctrl_ext &= ~(1 << 23); | |
1768 | reg_ctrl_ext |= (1 << 22); | |
1769 | ||
1770 | /* TX byte count fix */ | |
1771 | reg_ctrl = E1000_READ_REG(hw, CTRL); | |
1772 | reg_ctrl &= ~(1 << 29); | |
1773 | ||
1774 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); | |
1775 | E1000_WRITE_REG(hw, CTRL, reg_ctrl); | |
1776 | break; | |
1777 | case e1000_80003es2lan: | |
1778 | /* improve small packet performace for fiber/serdes */ | |
1779 | if ((hw->media_type == e1000_media_type_fiber) | |
1780 | || (hw->media_type == | |
1781 | e1000_media_type_internal_serdes)) { | |
1782 | reg_tarc0 &= ~(1 << 20); | |
1783 | } | |
1784 | ||
1785 | /* Multiple read bit is reversed polarity */ | |
1786 | reg_tctl = E1000_READ_REG(hw, TCTL); | |
1787 | reg_tarc1 = E1000_READ_REG(hw, TARC1); | |
1788 | if (reg_tctl & E1000_TCTL_MULR) | |
1789 | reg_tarc1 &= ~(1 << 28); | |
1790 | else | |
1791 | reg_tarc1 |= (1 << 28); | |
1792 | ||
1793 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); | |
1794 | break; | |
1795 | case e1000_ich8lan: | |
1796 | /* Reduce concurrent DMA requests to 3 from 4 */ | |
1797 | if ((hw->revision_id < 3) || | |
1798 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | |
1799 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) | |
1800 | reg_tarc0 |= ((1 << 29)|(1 << 28)); | |
1801 | ||
1802 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
1803 | reg_ctrl_ext |= (1 << 22); | |
1804 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); | |
1805 | ||
1806 | /* workaround TX hang with TSO=on */ | |
1807 | reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); | |
1808 | ||
1809 | /* Multiple read bit is reversed polarity */ | |
1810 | reg_tctl = E1000_READ_REG(hw, TCTL); | |
1811 | reg_tarc1 = E1000_READ_REG(hw, TARC1); | |
1812 | if (reg_tctl & E1000_TCTL_MULR) | |
1813 | reg_tarc1 &= ~(1 << 28); | |
1814 | else | |
1815 | reg_tarc1 |= (1 << 28); | |
1816 | ||
1817 | /* workaround TX hang with TSO=on */ | |
1818 | reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); | |
1819 | ||
1820 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); | |
1821 | break; | |
1822 | default: | |
1823 | break; | |
1824 | } | |
1825 | ||
1826 | E1000_WRITE_REG(hw, TARC0, reg_tarc0); | |
1827 | } | |
682011ff WD |
1828 | } |
1829 | ||
1830 | /****************************************************************************** | |
1831 | * Performs basic configuration of the adapter. | |
1832 | * | |
1833 | * hw - Struct containing variables accessed by shared code | |
8bde7f77 WD |
1834 | * |
1835 | * Assumes that the controller has previously been reset and is in a | |
682011ff WD |
1836 | * post-reset uninitialized state. Initializes the receive address registers, |
1837 | * multicast table, and VLAN filter table. Calls routines to setup link | |
1838 | * configuration and flow control settings. Clears all on-chip counters. Leaves | |
1839 | * the transmit and receive units disabled and uninitialized. | |
1840 | *****************************************************************************/ | |
1841 | static int | |
5c5e707a | 1842 | e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) |
682011ff | 1843 | { |
aa070789 | 1844 | uint32_t ctrl; |
682011ff WD |
1845 | uint32_t i; |
1846 | int32_t ret_val; | |
1847 | uint16_t pcix_cmd_word; | |
1848 | uint16_t pcix_stat_hi_word; | |
1849 | uint16_t cmd_mmrbc; | |
1850 | uint16_t stat_mmrbc; | |
aa070789 RZ |
1851 | uint32_t mta_size; |
1852 | uint32_t reg_data; | |
1853 | uint32_t ctrl_ext; | |
682011ff | 1854 | DEBUGFUNC(); |
aa070789 RZ |
1855 | /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ |
1856 | if ((hw->mac_type == e1000_ich8lan) && | |
1857 | ((hw->revision_id < 3) || | |
1858 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | |
1859 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { | |
1860 | reg_data = E1000_READ_REG(hw, STATUS); | |
1861 | reg_data &= ~0x80000000; | |
1862 | E1000_WRITE_REG(hw, STATUS, reg_data); | |
682011ff | 1863 | } |
aa070789 | 1864 | /* Do not need initialize Identification LED */ |
682011ff | 1865 | |
aa070789 RZ |
1866 | /* Set the media type and TBI compatibility */ |
1867 | e1000_set_media_type(hw); | |
1868 | ||
1869 | /* Must be called after e1000_set_media_type | |
1870 | * because media_type is used */ | |
1871 | e1000_initialize_hardware_bits(hw); | |
682011ff WD |
1872 | |
1873 | /* Disabling VLAN filtering. */ | |
1874 | DEBUGOUT("Initializing the IEEE VLAN\n"); | |
aa070789 RZ |
1875 | /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ |
1876 | if (hw->mac_type != e1000_ich8lan) { | |
1877 | if (hw->mac_type < e1000_82545_rev_3) | |
1878 | E1000_WRITE_REG(hw, VET, 0); | |
1879 | e1000_clear_vfta(hw); | |
1880 | } | |
682011ff WD |
1881 | |
1882 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ | |
1883 | if (hw->mac_type == e1000_82542_rev2_0) { | |
1884 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | |
81dab9af BM |
1885 | #ifdef CONFIG_DM_ETH |
1886 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, | |
1887 | hw-> | |
1888 | pci_cmd_word & ~PCI_COMMAND_INVALIDATE); | |
1889 | #else | |
682011ff WD |
1890 | pci_write_config_word(hw->pdev, PCI_COMMAND, |
1891 | hw-> | |
1892 | pci_cmd_word & ~PCI_COMMAND_INVALIDATE); | |
81dab9af | 1893 | #endif |
682011ff WD |
1894 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); |
1895 | E1000_WRITE_FLUSH(hw); | |
1896 | mdelay(5); | |
1897 | } | |
1898 | ||
1899 | /* Setup the receive address. This involves initializing all of the Receive | |
1900 | * Address Registers (RARs 0 - 15). | |
1901 | */ | |
5c5e707a | 1902 | e1000_init_rx_addrs(hw, enetaddr); |
682011ff WD |
1903 | |
1904 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ | |
1905 | if (hw->mac_type == e1000_82542_rev2_0) { | |
1906 | E1000_WRITE_REG(hw, RCTL, 0); | |
1907 | E1000_WRITE_FLUSH(hw); | |
1908 | mdelay(1); | |
81dab9af BM |
1909 | #ifdef CONFIG_DM_ETH |
1910 | dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); | |
1911 | #else | |
682011ff | 1912 | pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); |
81dab9af | 1913 | #endif |
682011ff WD |
1914 | } |
1915 | ||
1916 | /* Zero out the Multicast HASH table */ | |
1917 | DEBUGOUT("Zeroing the MTA\n"); | |
aa070789 RZ |
1918 | mta_size = E1000_MC_TBL_SIZE; |
1919 | if (hw->mac_type == e1000_ich8lan) | |
1920 | mta_size = E1000_MC_TBL_SIZE_ICH8LAN; | |
1921 | for (i = 0; i < mta_size; i++) { | |
682011ff | 1922 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
aa070789 RZ |
1923 | /* use write flush to prevent Memory Write Block (MWB) from |
1924 | * occuring when accessing our register space */ | |
1925 | E1000_WRITE_FLUSH(hw); | |
1926 | } | |
e97f7fbb | 1927 | |
aa070789 RZ |
1928 | switch (hw->mac_type) { |
1929 | case e1000_82545_rev_3: | |
1930 | case e1000_82546_rev_3: | |
95186063 | 1931 | case e1000_igb: |
aa070789 RZ |
1932 | break; |
1933 | default: | |
682011ff | 1934 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
aa070789 | 1935 | if (hw->bus_type == e1000_bus_type_pcix) { |
81dab9af BM |
1936 | #ifdef CONFIG_DM_ETH |
1937 | dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, | |
1938 | &pcix_cmd_word); | |
1939 | dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, | |
1940 | &pcix_stat_hi_word); | |
1941 | #else | |
682011ff WD |
1942 | pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, |
1943 | &pcix_cmd_word); | |
1944 | pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, | |
1945 | &pcix_stat_hi_word); | |
81dab9af | 1946 | #endif |
682011ff WD |
1947 | cmd_mmrbc = |
1948 | (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> | |
1949 | PCIX_COMMAND_MMRBC_SHIFT; | |
1950 | stat_mmrbc = | |
1951 | (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> | |
1952 | PCIX_STATUS_HI_MMRBC_SHIFT; | |
1953 | if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) | |
1954 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; | |
1955 | if (cmd_mmrbc > stat_mmrbc) { | |
1956 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; | |
1957 | pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; | |
81dab9af BM |
1958 | #ifdef CONFIG_DM_ETH |
1959 | dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, | |
1960 | pcix_cmd_word); | |
1961 | #else | |
682011ff WD |
1962 | pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, |
1963 | pcix_cmd_word); | |
81dab9af | 1964 | #endif |
682011ff WD |
1965 | } |
1966 | } | |
aa070789 RZ |
1967 | break; |
1968 | } | |
1969 | ||
1970 | /* More time needed for PHY to initialize */ | |
1971 | if (hw->mac_type == e1000_ich8lan) | |
1972 | mdelay(15); | |
95186063 MV |
1973 | if (hw->mac_type == e1000_igb) |
1974 | mdelay(15); | |
682011ff WD |
1975 | |
1976 | /* Call a subroutine to configure the link and setup flow control. */ | |
5c5e707a | 1977 | ret_val = e1000_setup_link(hw); |
682011ff WD |
1978 | |
1979 | /* Set the transmit descriptor write-back policy */ | |
1980 | if (hw->mac_type > e1000_82544) { | |
1981 | ctrl = E1000_READ_REG(hw, TXDCTL); | |
1982 | ctrl = | |
1983 | (ctrl & ~E1000_TXDCTL_WTHRESH) | | |
1984 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
1985 | E1000_WRITE_REG(hw, TXDCTL, ctrl); | |
1986 | } | |
aa070789 | 1987 | |
776e66e8 | 1988 | /* Set the receive descriptor write back policy */ |
776e66e8 RG |
1989 | if (hw->mac_type >= e1000_82571) { |
1990 | ctrl = E1000_READ_REG(hw, RXDCTL); | |
1991 | ctrl = | |
1992 | (ctrl & ~E1000_RXDCTL_WTHRESH) | | |
1993 | E1000_RXDCTL_FULL_RX_DESC_WB; | |
1994 | E1000_WRITE_REG(hw, RXDCTL, ctrl); | |
1995 | } | |
1996 | ||
aa070789 RZ |
1997 | switch (hw->mac_type) { |
1998 | default: | |
1999 | break; | |
2000 | case e1000_80003es2lan: | |
2001 | /* Enable retransmit on late collisions */ | |
2002 | reg_data = E1000_READ_REG(hw, TCTL); | |
2003 | reg_data |= E1000_TCTL_RTLC; | |
2004 | E1000_WRITE_REG(hw, TCTL, reg_data); | |
2005 | ||
2006 | /* Configure Gigabit Carry Extend Padding */ | |
2007 | reg_data = E1000_READ_REG(hw, TCTL_EXT); | |
2008 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
2009 | reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; | |
2010 | E1000_WRITE_REG(hw, TCTL_EXT, reg_data); | |
2011 | ||
2012 | /* Configure Transmit Inter-Packet Gap */ | |
2013 | reg_data = E1000_READ_REG(hw, TIPG); | |
2014 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
2015 | reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
2016 | E1000_WRITE_REG(hw, TIPG, reg_data); | |
2017 | ||
2018 | reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); | |
2019 | reg_data &= ~0x00100000; | |
2020 | E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); | |
2021 | /* Fall through */ | |
2022 | case e1000_82571: | |
2023 | case e1000_82572: | |
2024 | case e1000_ich8lan: | |
2025 | ctrl = E1000_READ_REG(hw, TXDCTL1); | |
2026 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | |
2027 | | E1000_TXDCTL_FULL_TX_DESC_WB; | |
2028 | E1000_WRITE_REG(hw, TXDCTL1, ctrl); | |
2029 | break; | |
2c2668f9 RZ |
2030 | case e1000_82573: |
2031 | case e1000_82574: | |
2032 | reg_data = E1000_READ_REG(hw, GCR); | |
2033 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
2034 | E1000_WRITE_REG(hw, GCR, reg_data); | |
95186063 MV |
2035 | case e1000_igb: |
2036 | break; | |
aa070789 RZ |
2037 | } |
2038 | ||
aa070789 RZ |
2039 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
2040 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { | |
2041 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
2042 | /* Relaxed ordering must be disabled to avoid a parity | |
2043 | * error crash in a PCI slot. */ | |
2044 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
2045 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
2046 | } | |
2047 | ||
682011ff WD |
2048 | return ret_val; |
2049 | } | |
2050 | ||
2051 | /****************************************************************************** | |
2052 | * Configures flow control and link settings. | |
8bde7f77 | 2053 | * |
682011ff | 2054 | * hw - Struct containing variables accessed by shared code |
8bde7f77 | 2055 | * |
682011ff WD |
2056 | * Determines which flow control settings to use. Calls the apropriate media- |
2057 | * specific link configuration function. Configures the flow control settings. | |
2058 | * Assuming the adapter has a valid link partner, a valid link should be | |
8bde7f77 | 2059 | * established. Assumes the hardware has previously been reset and the |
682011ff WD |
2060 | * transmitter and receiver are not enabled. |
2061 | *****************************************************************************/ | |
2062 | static int | |
5c5e707a | 2063 | e1000_setup_link(struct e1000_hw *hw) |
682011ff | 2064 | { |
682011ff | 2065 | int32_t ret_val; |
8712adfd RI |
2066 | #ifndef CONFIG_E1000_NO_NVM |
2067 | uint32_t ctrl_ext; | |
682011ff | 2068 | uint16_t eeprom_data; |
8712adfd | 2069 | #endif |
682011ff WD |
2070 | |
2071 | DEBUGFUNC(); | |
2072 | ||
aa070789 RZ |
2073 | /* In the case of the phy reset being blocked, we already have a link. |
2074 | * We do not have to set it up again. */ | |
2075 | if (e1000_check_phy_reset_block(hw)) | |
2076 | return E1000_SUCCESS; | |
2077 | ||
8712adfd | 2078 | #ifndef CONFIG_E1000_NO_NVM |
682011ff WD |
2079 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
2080 | * that determine the hardware's default PAUSE (flow control) mode, | |
2081 | * a bit that determines whether the HW defaults to enabling or | |
2082 | * disabling auto-negotiation, and the direction of the | |
2083 | * SW defined pins. If there is no SW over-ride of the flow | |
2084 | * control setting, then the variable hw->fc will | |
2085 | * be initialized based on a value in the EEPROM. | |
2086 | */ | |
aa070789 RZ |
2087 | if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, |
2088 | &eeprom_data) < 0) { | |
682011ff WD |
2089 | DEBUGOUT("EEPROM Read Error\n"); |
2090 | return -E1000_ERR_EEPROM; | |
2091 | } | |
8712adfd | 2092 | #endif |
682011ff | 2093 | if (hw->fc == e1000_fc_default) { |
aa070789 RZ |
2094 | switch (hw->mac_type) { |
2095 | case e1000_ich8lan: | |
2096 | case e1000_82573: | |
2c2668f9 | 2097 | case e1000_82574: |
95186063 | 2098 | case e1000_igb: |
682011ff | 2099 | hw->fc = e1000_fc_full; |
aa070789 RZ |
2100 | break; |
2101 | default: | |
8712adfd | 2102 | #ifndef CONFIG_E1000_NO_NVM |
aa070789 RZ |
2103 | ret_val = e1000_read_eeprom(hw, |
2104 | EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); | |
2105 | if (ret_val) { | |
2106 | DEBUGOUT("EEPROM Read Error\n"); | |
2107 | return -E1000_ERR_EEPROM; | |
2108 | } | |
aa070789 RZ |
2109 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
2110 | hw->fc = e1000_fc_none; | |
2111 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == | |
2112 | EEPROM_WORD0F_ASM_DIR) | |
2113 | hw->fc = e1000_fc_tx_pause; | |
2114 | else | |
8712adfd | 2115 | #endif |
aa070789 RZ |
2116 | hw->fc = e1000_fc_full; |
2117 | break; | |
2118 | } | |
682011ff WD |
2119 | } |
2120 | ||
2121 | /* We want to save off the original Flow Control configuration just | |
2122 | * in case we get disconnected and then reconnected into a different | |
2123 | * hub or switch with different Flow Control capabilities. | |
2124 | */ | |
2125 | if (hw->mac_type == e1000_82542_rev2_0) | |
2126 | hw->fc &= (~e1000_fc_tx_pause); | |
2127 | ||
2128 | if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) | |
2129 | hw->fc &= (~e1000_fc_rx_pause); | |
2130 | ||
2131 | hw->original_fc = hw->fc; | |
2132 | ||
2133 | DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); | |
2134 | ||
8712adfd | 2135 | #ifndef CONFIG_E1000_NO_NVM |
682011ff WD |
2136 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
2137 | * polarity value for the SW controlled pins, and setup the | |
2138 | * Extended Device Control reg with that info. | |
2139 | * This is needed because one of the SW controlled pins is used for | |
2140 | * signal detection. So this should be done before e1000_setup_pcs_link() | |
2141 | * or e1000_phy_setup() is called. | |
2142 | */ | |
2143 | if (hw->mac_type == e1000_82543) { | |
2144 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << | |
2145 | SWDPIO__EXT_SHIFT); | |
2146 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
2147 | } | |
8712adfd | 2148 | #endif |
682011ff WD |
2149 | |
2150 | /* Call the necessary subroutine to configure the link. */ | |
2151 | ret_val = (hw->media_type == e1000_media_type_fiber) ? | |
5c5e707a | 2152 | e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); |
682011ff WD |
2153 | if (ret_val < 0) { |
2154 | return ret_val; | |
2155 | } | |
2156 | ||
2157 | /* Initialize the flow control address, type, and PAUSE timer | |
2158 | * registers to their default values. This is done even if flow | |
2159 | * control is disabled, because it does not hurt anything to | |
2160 | * initialize these registers. | |
2161 | */ | |
aa070789 RZ |
2162 | DEBUGOUT("Initializing the Flow Control address, type" |
2163 | "and timer regs\n"); | |
2164 | ||
2165 | /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ | |
2166 | if (hw->mac_type != e1000_ich8lan) { | |
2167 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); | |
2168 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); | |
2169 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); | |
2170 | } | |
682011ff | 2171 | |
682011ff WD |
2172 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
2173 | ||
2174 | /* Set the flow control receive threshold registers. Normally, | |
2175 | * these registers will be set to a default threshold that may be | |
2176 | * adjusted later by the driver's runtime code. However, if the | |
2177 | * ability to transmit pause frames in not enabled, then these | |
8bde7f77 | 2178 | * registers will be set to 0. |
682011ff WD |
2179 | */ |
2180 | if (!(hw->fc & e1000_fc_tx_pause)) { | |
2181 | E1000_WRITE_REG(hw, FCRTL, 0); | |
2182 | E1000_WRITE_REG(hw, FCRTH, 0); | |
2183 | } else { | |
2184 | /* We need to set up the Receive Threshold high and low water marks | |
2185 | * as well as (optionally) enabling the transmission of XON frames. | |
2186 | */ | |
2187 | if (hw->fc_send_xon) { | |
2188 | E1000_WRITE_REG(hw, FCRTL, | |
2189 | (hw->fc_low_water | E1000_FCRTL_XONE)); | |
2190 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
2191 | } else { | |
2192 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); | |
2193 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
2194 | } | |
2195 | } | |
2196 | return ret_val; | |
2197 | } | |
2198 | ||
2199 | /****************************************************************************** | |
2200 | * Sets up link for a fiber based adapter | |
2201 | * | |
2202 | * hw - Struct containing variables accessed by shared code | |
2203 | * | |
2204 | * Manipulates Physical Coding Sublayer functions in order to configure | |
2205 | * link. Assumes the hardware has been previously reset and the transmitter | |
2206 | * and receiver are not enabled. | |
2207 | *****************************************************************************/ | |
2208 | static int | |
5c5e707a | 2209 | e1000_setup_fiber_link(struct e1000_hw *hw) |
682011ff | 2210 | { |
682011ff WD |
2211 | uint32_t ctrl; |
2212 | uint32_t status; | |
2213 | uint32_t txcw = 0; | |
2214 | uint32_t i; | |
2215 | uint32_t signal; | |
2216 | int32_t ret_val; | |
2217 | ||
2218 | DEBUGFUNC(); | |
8bde7f77 WD |
2219 | /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be |
2220 | * set when the optics detect a signal. On older adapters, it will be | |
682011ff WD |
2221 | * cleared when there is a signal |
2222 | */ | |
2223 | ctrl = E1000_READ_REG(hw, CTRL); | |
2224 | if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) | |
2225 | signal = E1000_CTRL_SWDPIN1; | |
2226 | else | |
2227 | signal = 0; | |
2228 | ||
5c5e707a | 2229 | printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, |
682011ff WD |
2230 | ctrl); |
2231 | /* Take the link out of reset */ | |
2232 | ctrl &= ~(E1000_CTRL_LRST); | |
2233 | ||
2234 | e1000_config_collision_dist(hw); | |
2235 | ||
2236 | /* Check for a software override of the flow control settings, and setup | |
2237 | * the device accordingly. If auto-negotiation is enabled, then software | |
2238 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit | |
2239 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if | |
8bde7f77 | 2240 | * auto-negotiation is disabled, then software will have to manually |
682011ff WD |
2241 | * configure the two flow control enable bits in the CTRL register. |
2242 | * | |
2243 | * The possible values of the "fc" parameter are: | |
1aeed8d7 WD |
2244 | * 0: Flow control is completely disabled |
2245 | * 1: Rx flow control is enabled (we can receive pause frames, but | |
2246 | * not send pause frames). | |
2247 | * 2: Tx flow control is enabled (we can send pause frames but we do | |
2248 | * not support receiving pause frames). | |
2249 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
682011ff WD |
2250 | */ |
2251 | switch (hw->fc) { | |
2252 | case e1000_fc_none: | |
2253 | /* Flow control is completely disabled by a software over-ride. */ | |
2254 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); | |
2255 | break; | |
2256 | case e1000_fc_rx_pause: | |
8bde7f77 WD |
2257 | /* RX Flow control is enabled and TX Flow control is disabled by a |
2258 | * software over-ride. Since there really isn't a way to advertise | |
682011ff WD |
2259 | * that we are capable of RX Pause ONLY, we will advertise that we |
2260 | * support both symmetric and asymmetric RX PAUSE. Later, we will | |
2261 | * disable the adapter's ability to send PAUSE frames. | |
2262 | */ | |
2263 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
2264 | break; | |
2265 | case e1000_fc_tx_pause: | |
8bde7f77 | 2266 | /* TX Flow control is enabled, and RX Flow control is disabled, by a |
682011ff WD |
2267 | * software over-ride. |
2268 | */ | |
2269 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); | |
2270 | break; | |
2271 | case e1000_fc_full: | |
2272 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ | |
2273 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
2274 | break; | |
2275 | default: | |
2276 | DEBUGOUT("Flow control param set incorrectly\n"); | |
2277 | return -E1000_ERR_CONFIG; | |
2278 | break; | |
2279 | } | |
2280 | ||
2281 | /* Since auto-negotiation is enabled, take the link out of reset (the link | |
2282 | * will be in reset, because we previously reset the chip). This will | |
2283 | * restart auto-negotiation. If auto-neogtiation is successful then the | |
2284 | * link-up status bit will be set and the flow control enable bits (RFCE | |
2285 | * and TFCE) will be set according to their negotiated value. | |
2286 | */ | |
2287 | DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); | |
2288 | ||
2289 | E1000_WRITE_REG(hw, TXCW, txcw); | |
2290 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2291 | E1000_WRITE_FLUSH(hw); | |
2292 | ||
2293 | hw->txcw = txcw; | |
2294 | mdelay(1); | |
2295 | ||
2296 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" | |
8bde7f77 WD |
2297 | * indication in the Device Status Register. Time-out if a link isn't |
2298 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in | |
682011ff WD |
2299 | * less than 500 milliseconds even if the other end is doing it in SW). |
2300 | */ | |
2301 | if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { | |
2302 | DEBUGOUT("Looking for Link\n"); | |
2303 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { | |
2304 | mdelay(10); | |
2305 | status = E1000_READ_REG(hw, STATUS); | |
2306 | if (status & E1000_STATUS_LU) | |
2307 | break; | |
2308 | } | |
2309 | if (i == (LINK_UP_TIMEOUT / 10)) { | |
8bde7f77 | 2310 | /* AutoNeg failed to achieve a link, so we'll call |
682011ff WD |
2311 | * e1000_check_for_link. This routine will force the link up if we |
2312 | * detect a signal. This will allow us to communicate with | |
2313 | * non-autonegotiating link partners. | |
2314 | */ | |
2315 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); | |
2316 | hw->autoneg_failed = 1; | |
5c5e707a | 2317 | ret_val = e1000_check_for_link(hw); |
682011ff WD |
2318 | if (ret_val < 0) { |
2319 | DEBUGOUT("Error while checking for link\n"); | |
2320 | return ret_val; | |
2321 | } | |
2322 | hw->autoneg_failed = 0; | |
2323 | } else { | |
2324 | hw->autoneg_failed = 0; | |
2325 | DEBUGOUT("Valid Link Found\n"); | |
2326 | } | |
aa070789 RZ |
2327 | } else { |
2328 | DEBUGOUT("No Signal Detected\n"); | |
2329 | return -E1000_ERR_NOLINK; | |
2330 | } | |
2331 | return 0; | |
2332 | } | |
2333 | ||
aa070789 RZ |
2334 | /****************************************************************************** |
2335 | * Make sure we have a valid PHY and change PHY mode before link setup. | |
2336 | * | |
2337 | * hw - Struct containing variables accessed by shared code | |
2338 | ******************************************************************************/ | |
2339 | static int32_t | |
2340 | e1000_copper_link_preconfig(struct e1000_hw *hw) | |
2341 | { | |
2342 | uint32_t ctrl; | |
2343 | int32_t ret_val; | |
2344 | uint16_t phy_data; | |
2345 | ||
2346 | DEBUGFUNC(); | |
2347 | ||
2348 | ctrl = E1000_READ_REG(hw, CTRL); | |
2349 | /* With 82543, we need to force speed and duplex on the MAC equal to what | |
2350 | * the PHY speed and duplex configuration is. In addition, we need to | |
2351 | * perform a hardware reset on the PHY to take it out of reset. | |
2352 | */ | |
2353 | if (hw->mac_type > e1000_82543) { | |
2354 | ctrl |= E1000_CTRL_SLU; | |
2355 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
2356 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2357 | } else { | |
2358 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | |
2359 | | E1000_CTRL_SLU); | |
2360 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2361 | ret_val = e1000_phy_hw_reset(hw); | |
2362 | if (ret_val) | |
2363 | return ret_val; | |
2364 | } | |
2365 | ||
2366 | /* Make sure we have a valid PHY */ | |
2367 | ret_val = e1000_detect_gig_phy(hw); | |
2368 | if (ret_val) { | |
2369 | DEBUGOUT("Error, did not detect valid phy.\n"); | |
2370 | return ret_val; | |
2371 | } | |
5abf13e4 | 2372 | DEBUGOUT("Phy ID = %x\n", hw->phy_id); |
aa070789 | 2373 | |
aa070789 RZ |
2374 | /* Set PHY to class A mode (if necessary) */ |
2375 | ret_val = e1000_set_phy_mode(hw); | |
2376 | if (ret_val) | |
2377 | return ret_val; | |
aa070789 RZ |
2378 | if ((hw->mac_type == e1000_82545_rev_3) || |
2379 | (hw->mac_type == e1000_82546_rev_3)) { | |
2380 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, | |
2381 | &phy_data); | |
2382 | phy_data |= 0x00000008; | |
2383 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, | |
2384 | phy_data); | |
2385 | } | |
2386 | ||
2387 | if (hw->mac_type <= e1000_82543 || | |
2388 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || | |
2389 | hw->mac_type == e1000_82541_rev_2 | |
2390 | || hw->mac_type == e1000_82547_rev_2) | |
472d5460 | 2391 | hw->phy_reset_disable = false; |
aa070789 RZ |
2392 | |
2393 | return E1000_SUCCESS; | |
2394 | } | |
2395 | ||
2396 | /***************************************************************************** | |
2397 | * | |
2398 | * This function sets the lplu state according to the active flag. When | |
2399 | * activating lplu this function also disables smart speed and vise versa. | |
2400 | * lplu will not be activated unless the device autonegotiation advertisment | |
2401 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
2402 | * hw: Struct containing variables accessed by shared code | |
2403 | * active - true to enable lplu false to disable lplu. | |
2404 | * | |
2405 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
2406 | * E1000_SUCCESS at any other case. | |
2407 | * | |
2408 | ****************************************************************************/ | |
2409 | ||
2410 | static int32_t | |
472d5460 | 2411 | e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
aa070789 RZ |
2412 | { |
2413 | uint32_t phy_ctrl = 0; | |
2414 | int32_t ret_val; | |
2415 | uint16_t phy_data; | |
2416 | DEBUGFUNC(); | |
2417 | ||
2418 | if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 | |
2419 | && hw->phy_type != e1000_phy_igp_3) | |
2420 | return E1000_SUCCESS; | |
2421 | ||
2422 | /* During driver activity LPLU should not be used or it will attain link | |
2423 | * from the lowest speeds starting from 10Mbps. The capability is used | |
2424 | * for Dx transitions and states */ | |
2425 | if (hw->mac_type == e1000_82541_rev_2 | |
2426 | || hw->mac_type == e1000_82547_rev_2) { | |
2427 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
2428 | &phy_data); | |
2429 | if (ret_val) | |
2430 | return ret_val; | |
2431 | } else if (hw->mac_type == e1000_ich8lan) { | |
2432 | /* MAC writes into PHY register based on the state transition | |
2433 | * and start auto-negotiation. SW driver can overwrite the | |
2434 | * settings in CSR PHY power control E1000_PHY_CTRL register. */ | |
2435 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); | |
2436 | } else { | |
2437 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
2438 | &phy_data); | |
2439 | if (ret_val) | |
2440 | return ret_val; | |
2441 | } | |
2442 | ||
2443 | if (!active) { | |
2444 | if (hw->mac_type == e1000_82541_rev_2 || | |
2445 | hw->mac_type == e1000_82547_rev_2) { | |
2446 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; | |
2447 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
2448 | phy_data); | |
2449 | if (ret_val) | |
2450 | return ret_val; | |
2451 | } else { | |
2452 | if (hw->mac_type == e1000_ich8lan) { | |
2453 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
2454 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
2455 | } else { | |
2456 | phy_data &= ~IGP02E1000_PM_D3_LPLU; | |
2457 | ret_val = e1000_write_phy_reg(hw, | |
2458 | IGP02E1000_PHY_POWER_MGMT, phy_data); | |
2459 | if (ret_val) | |
2460 | return ret_val; | |
2461 | } | |
2462 | } | |
2463 | ||
2464 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
2465 | * Dx states where the power conservation is most important. During | |
2466 | * driver activity we should enable SmartSpeed, so performance is | |
2467 | * maintained. */ | |
2468 | if (hw->smart_speed == e1000_smart_speed_on) { | |
2469 | ret_val = e1000_read_phy_reg(hw, | |
2470 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2471 | if (ret_val) | |
2472 | return ret_val; | |
2473 | ||
2474 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
2475 | ret_val = e1000_write_phy_reg(hw, | |
2476 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2477 | if (ret_val) | |
2478 | return ret_val; | |
2479 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
2480 | ret_val = e1000_read_phy_reg(hw, | |
2481 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2482 | if (ret_val) | |
2483 | return ret_val; | |
2484 | ||
2485 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2486 | ret_val = e1000_write_phy_reg(hw, | |
2487 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2488 | if (ret_val) | |
2489 | return ret_val; | |
2490 | } | |
2491 | ||
2492 | } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) | |
2493 | || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || | |
2494 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { | |
2495 | ||
2496 | if (hw->mac_type == e1000_82541_rev_2 || | |
2497 | hw->mac_type == e1000_82547_rev_2) { | |
2498 | phy_data |= IGP01E1000_GMII_FLEX_SPD; | |
2499 | ret_val = e1000_write_phy_reg(hw, | |
2500 | IGP01E1000_GMII_FIFO, phy_data); | |
2501 | if (ret_val) | |
2502 | return ret_val; | |
2503 | } else { | |
2504 | if (hw->mac_type == e1000_ich8lan) { | |
2505 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
2506 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
2507 | } else { | |
2508 | phy_data |= IGP02E1000_PM_D3_LPLU; | |
2509 | ret_val = e1000_write_phy_reg(hw, | |
2510 | IGP02E1000_PHY_POWER_MGMT, phy_data); | |
2511 | if (ret_val) | |
2512 | return ret_val; | |
2513 | } | |
2514 | } | |
2515 | ||
2516 | /* When LPLU is enabled we should disable SmartSpeed */ | |
2517 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2518 | &phy_data); | |
2519 | if (ret_val) | |
2520 | return ret_val; | |
2521 | ||
2522 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2523 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
2524 | phy_data); | |
2525 | if (ret_val) | |
2526 | return ret_val; | |
2527 | } | |
2528 | return E1000_SUCCESS; | |
2529 | } | |
2530 | ||
2531 | /***************************************************************************** | |
2532 | * | |
2533 | * This function sets the lplu d0 state according to the active flag. When | |
2534 | * activating lplu this function also disables smart speed and vise versa. | |
2535 | * lplu will not be activated unless the device autonegotiation advertisment | |
2536 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
2537 | * hw: Struct containing variables accessed by shared code | |
2538 | * active - true to enable lplu false to disable lplu. | |
2539 | * | |
2540 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
2541 | * E1000_SUCCESS at any other case. | |
2542 | * | |
2543 | ****************************************************************************/ | |
2544 | ||
2545 | static int32_t | |
472d5460 | 2546 | e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
aa070789 RZ |
2547 | { |
2548 | uint32_t phy_ctrl = 0; | |
2549 | int32_t ret_val; | |
2550 | uint16_t phy_data; | |
2551 | DEBUGFUNC(); | |
2552 | ||
2553 | if (hw->mac_type <= e1000_82547_rev_2) | |
2554 | return E1000_SUCCESS; | |
2555 | ||
2556 | if (hw->mac_type == e1000_ich8lan) { | |
2557 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); | |
95186063 MV |
2558 | } else if (hw->mac_type == e1000_igb) { |
2559 | phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); | |
aa070789 RZ |
2560 | } else { |
2561 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
2562 | &phy_data); | |
2563 | if (ret_val) | |
2564 | return ret_val; | |
2565 | } | |
2566 | ||
2567 | if (!active) { | |
2568 | if (hw->mac_type == e1000_ich8lan) { | |
2569 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
2570 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
95186063 MV |
2571 | } else if (hw->mac_type == e1000_igb) { |
2572 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
2573 | E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); | |
aa070789 RZ |
2574 | } else { |
2575 | phy_data &= ~IGP02E1000_PM_D0_LPLU; | |
2576 | ret_val = e1000_write_phy_reg(hw, | |
2577 | IGP02E1000_PHY_POWER_MGMT, phy_data); | |
2578 | if (ret_val) | |
2579 | return ret_val; | |
2580 | } | |
2581 | ||
95186063 MV |
2582 | if (hw->mac_type == e1000_igb) |
2583 | return E1000_SUCCESS; | |
2584 | ||
aa070789 RZ |
2585 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
2586 | * Dx states where the power conservation is most important. During | |
2587 | * driver activity we should enable SmartSpeed, so performance is | |
2588 | * maintained. */ | |
2589 | if (hw->smart_speed == e1000_smart_speed_on) { | |
2590 | ret_val = e1000_read_phy_reg(hw, | |
2591 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2592 | if (ret_val) | |
2593 | return ret_val; | |
2594 | ||
2595 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
2596 | ret_val = e1000_write_phy_reg(hw, | |
2597 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2598 | if (ret_val) | |
2599 | return ret_val; | |
2600 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
2601 | ret_val = e1000_read_phy_reg(hw, | |
2602 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2603 | if (ret_val) | |
2604 | return ret_val; | |
2605 | ||
2606 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2607 | ret_val = e1000_write_phy_reg(hw, | |
2608 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2609 | if (ret_val) | |
2610 | return ret_val; | |
2611 | } | |
2612 | ||
2613 | ||
2614 | } else { | |
2615 | ||
2616 | if (hw->mac_type == e1000_ich8lan) { | |
2617 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
2618 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); | |
95186063 MV |
2619 | } else if (hw->mac_type == e1000_igb) { |
2620 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
2621 | E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); | |
aa070789 RZ |
2622 | } else { |
2623 | phy_data |= IGP02E1000_PM_D0_LPLU; | |
2624 | ret_val = e1000_write_phy_reg(hw, | |
2625 | IGP02E1000_PHY_POWER_MGMT, phy_data); | |
2626 | if (ret_val) | |
2627 | return ret_val; | |
2628 | } | |
2629 | ||
95186063 MV |
2630 | if (hw->mac_type == e1000_igb) |
2631 | return E1000_SUCCESS; | |
2632 | ||
aa070789 RZ |
2633 | /* When LPLU is enabled we should disable SmartSpeed */ |
2634 | ret_val = e1000_read_phy_reg(hw, | |
2635 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2636 | if (ret_val) | |
2637 | return ret_val; | |
2638 | ||
2639 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2640 | ret_val = e1000_write_phy_reg(hw, | |
2641 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2642 | if (ret_val) | |
2643 | return ret_val; | |
2644 | ||
2645 | } | |
2646 | return E1000_SUCCESS; | |
2647 | } | |
2648 | ||
2649 | /******************************************************************** | |
2650 | * Copper link setup for e1000_phy_igp series. | |
2651 | * | |
2652 | * hw - Struct containing variables accessed by shared code | |
2653 | *********************************************************************/ | |
2654 | static int32_t | |
2655 | e1000_copper_link_igp_setup(struct e1000_hw *hw) | |
2656 | { | |
2657 | uint32_t led_ctrl; | |
2658 | int32_t ret_val; | |
2659 | uint16_t phy_data; | |
2660 | ||
f81ecb5d | 2661 | DEBUGFUNC(); |
aa070789 RZ |
2662 | |
2663 | if (hw->phy_reset_disable) | |
2664 | return E1000_SUCCESS; | |
2665 | ||
2666 | ret_val = e1000_phy_reset(hw); | |
2667 | if (ret_val) { | |
2668 | DEBUGOUT("Error Resetting the PHY\n"); | |
2669 | return ret_val; | |
2670 | } | |
2671 | ||
2672 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ | |
2673 | mdelay(15); | |
2674 | if (hw->mac_type != e1000_ich8lan) { | |
2675 | /* Configure activity LED after PHY reset */ | |
2676 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
2677 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
2678 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
2679 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
2680 | } | |
2681 | ||
2682 | /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ | |
2683 | if (hw->phy_type == e1000_phy_igp) { | |
2684 | /* disable lplu d3 during driver init */ | |
472d5460 | 2685 | ret_val = e1000_set_d3_lplu_state(hw, false); |
aa070789 RZ |
2686 | if (ret_val) { |
2687 | DEBUGOUT("Error Disabling LPLU D3\n"); | |
2688 | return ret_val; | |
2689 | } | |
2690 | } | |
2691 | ||
2692 | /* disable lplu d0 during driver init */ | |
472d5460 | 2693 | ret_val = e1000_set_d0_lplu_state(hw, false); |
aa070789 RZ |
2694 | if (ret_val) { |
2695 | DEBUGOUT("Error Disabling LPLU D0\n"); | |
2696 | return ret_val; | |
2697 | } | |
2698 | /* Configure mdi-mdix settings */ | |
2699 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
2700 | if (ret_val) | |
2701 | return ret_val; | |
2702 | ||
2703 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
2704 | hw->dsp_config_state = e1000_dsp_config_disabled; | |
2705 | /* Force MDI for earlier revs of the IGP PHY */ | |
2706 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | |
2707 | | IGP01E1000_PSCR_FORCE_MDI_MDIX); | |
2708 | hw->mdix = 1; | |
2709 | ||
2710 | } else { | |
2711 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
2712 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
2713 | ||
2714 | switch (hw->mdix) { | |
2715 | case 1: | |
2716 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
2717 | break; | |
2718 | case 2: | |
2719 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
2720 | break; | |
2721 | case 0: | |
2722 | default: | |
2723 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; | |
2724 | break; | |
2725 | } | |
2726 | } | |
2727 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
2728 | if (ret_val) | |
2729 | return ret_val; | |
2730 | ||
2731 | /* set auto-master slave resolution settings */ | |
2732 | if (hw->autoneg) { | |
2733 | e1000_ms_type phy_ms_setting = hw->master_slave; | |
2734 | ||
2735 | if (hw->ffe_config_state == e1000_ffe_config_active) | |
2736 | hw->ffe_config_state = e1000_ffe_config_enabled; | |
2737 | ||
2738 | if (hw->dsp_config_state == e1000_dsp_config_activated) | |
2739 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
2740 | ||
2741 | /* when autonegotiation advertisment is only 1000Mbps then we | |
2742 | * should disable SmartSpeed and enable Auto MasterSlave | |
2743 | * resolution as hardware default. */ | |
2744 | if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { | |
2745 | /* Disable SmartSpeed */ | |
2746 | ret_val = e1000_read_phy_reg(hw, | |
2747 | IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
2748 | if (ret_val) | |
2749 | return ret_val; | |
2750 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2751 | ret_val = e1000_write_phy_reg(hw, | |
2752 | IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
2753 | if (ret_val) | |
2754 | return ret_val; | |
2755 | /* Set auto Master/Slave resolution process */ | |
2756 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, | |
2757 | &phy_data); | |
2758 | if (ret_val) | |
2759 | return ret_val; | |
2760 | phy_data &= ~CR_1000T_MS_ENABLE; | |
2761 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, | |
2762 | phy_data); | |
2763 | if (ret_val) | |
2764 | return ret_val; | |
2765 | } | |
2766 | ||
2767 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | |
2768 | if (ret_val) | |
2769 | return ret_val; | |
2770 | ||
2771 | /* load defaults for future use */ | |
2772 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? | |
2773 | ((phy_data & CR_1000T_MS_VALUE) ? | |
2774 | e1000_ms_force_master : | |
2775 | e1000_ms_force_slave) : | |
2776 | e1000_ms_auto; | |
2777 | ||
2778 | switch (phy_ms_setting) { | |
2779 | case e1000_ms_force_master: | |
2780 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
2781 | break; | |
2782 | case e1000_ms_force_slave: | |
2783 | phy_data |= CR_1000T_MS_ENABLE; | |
2784 | phy_data &= ~(CR_1000T_MS_VALUE); | |
2785 | break; | |
2786 | case e1000_ms_auto: | |
2787 | phy_data &= ~CR_1000T_MS_ENABLE; | |
2788 | default: | |
2789 | break; | |
2790 | } | |
2791 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
2792 | if (ret_val) | |
2793 | return ret_val; | |
2794 | } | |
2795 | ||
2796 | return E1000_SUCCESS; | |
2797 | } | |
2798 | ||
2799 | /***************************************************************************** | |
2800 | * This function checks the mode of the firmware. | |
2801 | * | |
472d5460 | 2802 | * returns - true when the mode is IAMT or false. |
aa070789 | 2803 | ****************************************************************************/ |
472d5460 | 2804 | bool |
aa070789 RZ |
2805 | e1000_check_mng_mode(struct e1000_hw *hw) |
2806 | { | |
2807 | uint32_t fwsm; | |
2808 | DEBUGFUNC(); | |
2809 | ||
2810 | fwsm = E1000_READ_REG(hw, FWSM); | |
2811 | ||
2812 | if (hw->mac_type == e1000_ich8lan) { | |
2813 | if ((fwsm & E1000_FWSM_MODE_MASK) == | |
2814 | (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
472d5460 | 2815 | return true; |
aa070789 RZ |
2816 | } else if ((fwsm & E1000_FWSM_MODE_MASK) == |
2817 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
472d5460 | 2818 | return true; |
aa070789 | 2819 | |
472d5460 | 2820 | return false; |
aa070789 RZ |
2821 | } |
2822 | ||
2823 | static int32_t | |
2824 | e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) | |
2825 | { | |
987b43a1 | 2826 | uint16_t swfw = E1000_SWFW_PHY0_SM; |
aa070789 | 2827 | uint32_t reg_val; |
aa070789 RZ |
2828 | DEBUGFUNC(); |
2829 | ||
987b43a1 | 2830 | if (e1000_is_second_port(hw)) |
aa070789 | 2831 | swfw = E1000_SWFW_PHY1_SM; |
987b43a1 | 2832 | |
aa070789 RZ |
2833 | if (e1000_swfw_sync_acquire(hw, swfw)) |
2834 | return -E1000_ERR_SWFW_SYNC; | |
2835 | ||
2836 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) | |
2837 | & E1000_KUMCTRLSTA_OFFSET) | data; | |
2838 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); | |
2839 | udelay(2); | |
2840 | ||
2841 | return E1000_SUCCESS; | |
2842 | } | |
2843 | ||
2844 | static int32_t | |
2845 | e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) | |
2846 | { | |
987b43a1 | 2847 | uint16_t swfw = E1000_SWFW_PHY0_SM; |
aa070789 | 2848 | uint32_t reg_val; |
aa070789 RZ |
2849 | DEBUGFUNC(); |
2850 | ||
987b43a1 | 2851 | if (e1000_is_second_port(hw)) |
aa070789 | 2852 | swfw = E1000_SWFW_PHY1_SM; |
987b43a1 | 2853 | |
95186063 MV |
2854 | if (e1000_swfw_sync_acquire(hw, swfw)) { |
2855 | debug("%s[%i]\n", __func__, __LINE__); | |
aa070789 | 2856 | return -E1000_ERR_SWFW_SYNC; |
95186063 | 2857 | } |
aa070789 RZ |
2858 | |
2859 | /* Write register address */ | |
2860 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | |
2861 | E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN; | |
2862 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); | |
2863 | udelay(2); | |
2864 | ||
2865 | /* Read the data returned */ | |
2866 | reg_val = E1000_READ_REG(hw, KUMCTRLSTA); | |
2867 | *data = (uint16_t)reg_val; | |
2868 | ||
2869 | return E1000_SUCCESS; | |
2870 | } | |
2871 | ||
2872 | /******************************************************************** | |
2873 | * Copper link setup for e1000_phy_gg82563 series. | |
2874 | * | |
2875 | * hw - Struct containing variables accessed by shared code | |
2876 | *********************************************************************/ | |
2877 | static int32_t | |
2878 | e1000_copper_link_ggp_setup(struct e1000_hw *hw) | |
2879 | { | |
2880 | int32_t ret_val; | |
2881 | uint16_t phy_data; | |
2882 | uint32_t reg_data; | |
2883 | ||
2884 | DEBUGFUNC(); | |
2885 | ||
2886 | if (!hw->phy_reset_disable) { | |
2887 | /* Enable CRS on TX for half-duplex operation. */ | |
2888 | ret_val = e1000_read_phy_reg(hw, | |
2889 | GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
2890 | if (ret_val) | |
2891 | return ret_val; | |
2892 | ||
2893 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
2894 | /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ | |
2895 | phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; | |
2896 | ||
2897 | ret_val = e1000_write_phy_reg(hw, | |
2898 | GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
2899 | if (ret_val) | |
2900 | return ret_val; | |
2901 | ||
2902 | /* Options: | |
2903 | * MDI/MDI-X = 0 (default) | |
2904 | * 0 - Auto for all speeds | |
2905 | * 1 - MDI mode | |
2906 | * 2 - MDI-X mode | |
2907 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
2908 | */ | |
2909 | ret_val = e1000_read_phy_reg(hw, | |
2910 | GG82563_PHY_SPEC_CTRL, &phy_data); | |
2911 | if (ret_val) | |
2912 | return ret_val; | |
2913 | ||
2914 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
2915 | ||
2916 | switch (hw->mdix) { | |
2917 | case 1: | |
2918 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
2919 | break; | |
2920 | case 2: | |
2921 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
2922 | break; | |
2923 | case 0: | |
2924 | default: | |
2925 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
2926 | break; | |
2927 | } | |
2928 | ||
2929 | /* Options: | |
2930 | * disable_polarity_correction = 0 (default) | |
2931 | * Automatic Correction for Reversed Cable Polarity | |
2932 | * 0 - Disabled | |
2933 | * 1 - Enabled | |
2934 | */ | |
2935 | phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
2936 | ret_val = e1000_write_phy_reg(hw, | |
2937 | GG82563_PHY_SPEC_CTRL, phy_data); | |
2938 | ||
2939 | if (ret_val) | |
2940 | return ret_val; | |
2941 | ||
2942 | /* SW Reset the PHY so all changes take effect */ | |
2943 | ret_val = e1000_phy_reset(hw); | |
2944 | if (ret_val) { | |
2945 | DEBUGOUT("Error Resetting the PHY\n"); | |
2946 | return ret_val; | |
2947 | } | |
2948 | } /* phy_reset_disable */ | |
2949 | ||
2950 | if (hw->mac_type == e1000_80003es2lan) { | |
2951 | /* Bypass RX and TX FIFO's */ | |
2952 | ret_val = e1000_write_kmrn_reg(hw, | |
2953 | E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, | |
2954 | E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | |
2955 | | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); | |
2956 | if (ret_val) | |
2957 | return ret_val; | |
2958 | ||
2959 | ret_val = e1000_read_phy_reg(hw, | |
2960 | GG82563_PHY_SPEC_CTRL_2, &phy_data); | |
2961 | if (ret_val) | |
2962 | return ret_val; | |
2963 | ||
2964 | phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
2965 | ret_val = e1000_write_phy_reg(hw, | |
2966 | GG82563_PHY_SPEC_CTRL_2, phy_data); | |
2967 | ||
2968 | if (ret_val) | |
2969 | return ret_val; | |
2970 | ||
2971 | reg_data = E1000_READ_REG(hw, CTRL_EXT); | |
2972 | reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
2973 | E1000_WRITE_REG(hw, CTRL_EXT, reg_data); | |
2974 | ||
2975 | ret_val = e1000_read_phy_reg(hw, | |
2976 | GG82563_PHY_PWR_MGMT_CTRL, &phy_data); | |
2977 | if (ret_val) | |
2978 | return ret_val; | |
2979 | ||
2980 | /* Do not init these registers when the HW is in IAMT mode, since the | |
2981 | * firmware will have already initialized them. We only initialize | |
2982 | * them if the HW is not in IAMT mode. | |
2983 | */ | |
472d5460 | 2984 | if (e1000_check_mng_mode(hw) == false) { |
aa070789 RZ |
2985 | /* Enable Electrical Idle on the PHY */ |
2986 | phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
2987 | ret_val = e1000_write_phy_reg(hw, | |
2988 | GG82563_PHY_PWR_MGMT_CTRL, phy_data); | |
2989 | if (ret_val) | |
2990 | return ret_val; | |
2991 | ||
2992 | ret_val = e1000_read_phy_reg(hw, | |
2993 | GG82563_PHY_KMRN_MODE_CTRL, &phy_data); | |
2994 | if (ret_val) | |
2995 | return ret_val; | |
2996 | ||
2997 | phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
2998 | ret_val = e1000_write_phy_reg(hw, | |
2999 | GG82563_PHY_KMRN_MODE_CTRL, phy_data); | |
3000 | ||
3001 | if (ret_val) | |
3002 | return ret_val; | |
3003 | } | |
3004 | ||
3005 | /* Workaround: Disable padding in Kumeran interface in the MAC | |
3006 | * and in the PHY to avoid CRC errors. | |
3007 | */ | |
3008 | ret_val = e1000_read_phy_reg(hw, | |
3009 | GG82563_PHY_INBAND_CTRL, &phy_data); | |
3010 | if (ret_val) | |
3011 | return ret_val; | |
3012 | phy_data |= GG82563_ICR_DIS_PADDING; | |
3013 | ret_val = e1000_write_phy_reg(hw, | |
3014 | GG82563_PHY_INBAND_CTRL, phy_data); | |
3015 | if (ret_val) | |
3016 | return ret_val; | |
682011ff | 3017 | } |
aa070789 | 3018 | return E1000_SUCCESS; |
682011ff WD |
3019 | } |
3020 | ||
aa070789 RZ |
3021 | /******************************************************************** |
3022 | * Copper link setup for e1000_phy_m88 series. | |
682011ff WD |
3023 | * |
3024 | * hw - Struct containing variables accessed by shared code | |
aa070789 RZ |
3025 | *********************************************************************/ |
3026 | static int32_t | |
3027 | e1000_copper_link_mgp_setup(struct e1000_hw *hw) | |
682011ff | 3028 | { |
682011ff | 3029 | int32_t ret_val; |
682011ff WD |
3030 | uint16_t phy_data; |
3031 | ||
3032 | DEBUGFUNC(); | |
3033 | ||
aa070789 RZ |
3034 | if (hw->phy_reset_disable) |
3035 | return E1000_SUCCESS; | |
682011ff | 3036 | |
aa070789 RZ |
3037 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
3038 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
3039 | if (ret_val) | |
682011ff | 3040 | return ret_val; |
682011ff | 3041 | |
682011ff WD |
3042 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
3043 | ||
682011ff WD |
3044 | /* Options: |
3045 | * MDI/MDI-X = 0 (default) | |
3046 | * 0 - Auto for all speeds | |
3047 | * 1 - MDI mode | |
3048 | * 2 - MDI-X mode | |
3049 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
3050 | */ | |
3051 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
aa070789 | 3052 | |
682011ff WD |
3053 | switch (hw->mdix) { |
3054 | case 1: | |
3055 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
3056 | break; | |
3057 | case 2: | |
3058 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
3059 | break; | |
3060 | case 3: | |
3061 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
3062 | break; | |
3063 | case 0: | |
3064 | default: | |
3065 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
3066 | break; | |
3067 | } | |
682011ff | 3068 | |
682011ff WD |
3069 | /* Options: |
3070 | * disable_polarity_correction = 0 (default) | |
aa070789 | 3071 | * Automatic Correction for Reversed Cable Polarity |
682011ff WD |
3072 | * 0 - Disabled |
3073 | * 1 - Enabled | |
3074 | */ | |
3075 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
aa070789 RZ |
3076 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
3077 | if (ret_val) | |
3078 | return ret_val; | |
682011ff | 3079 | |
aa070789 RZ |
3080 | if (hw->phy_revision < M88E1011_I_REV_4) { |
3081 | /* Force TX_CLK in the Extended PHY Specific Control Register | |
3082 | * to 25MHz clock. | |
3083 | */ | |
3084 | ret_val = e1000_read_phy_reg(hw, | |
3085 | M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
3086 | if (ret_val) | |
3087 | return ret_val; | |
3088 | ||
3089 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
3090 | ||
3091 | if ((hw->phy_revision == E1000_REVISION_2) && | |
3092 | (hw->phy_id == M88E1111_I_PHY_ID)) { | |
3093 | /* Vidalia Phy, set the downshift counter to 5x */ | |
3094 | phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); | |
3095 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
3096 | ret_val = e1000_write_phy_reg(hw, | |
3097 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
3098 | if (ret_val) | |
3099 | return ret_val; | |
3100 | } else { | |
3101 | /* Configure Master and Slave downshift values */ | |
3102 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
3103 | | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
3104 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
3105 | | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
3106 | ret_val = e1000_write_phy_reg(hw, | |
3107 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
3108 | if (ret_val) | |
3109 | return ret_val; | |
3110 | } | |
682011ff WD |
3111 | } |
3112 | ||
3113 | /* SW Reset the PHY so all changes take effect */ | |
3114 | ret_val = e1000_phy_reset(hw); | |
aa070789 | 3115 | if (ret_val) { |
682011ff WD |
3116 | DEBUGOUT("Error Resetting the PHY\n"); |
3117 | return ret_val; | |
3118 | } | |
3119 | ||
aa070789 RZ |
3120 | return E1000_SUCCESS; |
3121 | } | |
3122 | ||
3123 | /******************************************************************** | |
3124 | * Setup auto-negotiation and flow control advertisements, | |
3125 | * and then perform auto-negotiation. | |
3126 | * | |
3127 | * hw - Struct containing variables accessed by shared code | |
3128 | *********************************************************************/ | |
3129 | static int32_t | |
3130 | e1000_copper_link_autoneg(struct e1000_hw *hw) | |
3131 | { | |
3132 | int32_t ret_val; | |
3133 | uint16_t phy_data; | |
3134 | ||
3135 | DEBUGFUNC(); | |
682011ff | 3136 | |
682011ff WD |
3137 | /* Perform some bounds checking on the hw->autoneg_advertised |
3138 | * parameter. If this variable is zero, then set it to the default. | |
3139 | */ | |
3140 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
3141 | ||
3142 | /* If autoneg_advertised is zero, we assume it was not defaulted | |
3143 | * by the calling code so we set to advertise full capability. | |
3144 | */ | |
3145 | if (hw->autoneg_advertised == 0) | |
3146 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
3147 | ||
aa070789 RZ |
3148 | /* IFE phy only supports 10/100 */ |
3149 | if (hw->phy_type == e1000_phy_ife) | |
3150 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; | |
3151 | ||
682011ff WD |
3152 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
3153 | ret_val = e1000_phy_setup_autoneg(hw); | |
aa070789 | 3154 | if (ret_val) { |
682011ff WD |
3155 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
3156 | return ret_val; | |
3157 | } | |
3158 | DEBUGOUT("Restarting Auto-Neg\n"); | |
3159 | ||
3160 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and | |
3161 | * the Auto Neg Restart bit in the PHY control register. | |
3162 | */ | |
aa070789 RZ |
3163 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
3164 | if (ret_val) | |
3165 | return ret_val; | |
3166 | ||
682011ff | 3167 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
aa070789 RZ |
3168 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
3169 | if (ret_val) | |
3170 | return ret_val; | |
3171 | ||
682011ff WD |
3172 | /* Does the user want to wait for Auto-Neg to complete here, or |
3173 | * check at a later time (for example, callback routine). | |
3174 | */ | |
aa070789 RZ |
3175 | /* If we do not wait for autonegtation to complete I |
3176 | * do not see a valid link status. | |
3177 | * wait_autoneg_complete = 1 . | |
3178 | */ | |
682011ff WD |
3179 | if (hw->wait_autoneg_complete) { |
3180 | ret_val = e1000_wait_autoneg(hw); | |
aa070789 RZ |
3181 | if (ret_val) { |
3182 | DEBUGOUT("Error while waiting for autoneg" | |
3183 | "to complete\n"); | |
682011ff WD |
3184 | return ret_val; |
3185 | } | |
3186 | } | |
aa070789 | 3187 | |
472d5460 | 3188 | hw->get_link_status = true; |
aa070789 RZ |
3189 | |
3190 | return E1000_SUCCESS; | |
3191 | } | |
3192 | ||
3193 | /****************************************************************************** | |
3194 | * Config the MAC and the PHY after link is up. | |
3195 | * 1) Set up the MAC to the current PHY speed/duplex | |
3196 | * if we are on 82543. If we | |
3197 | * are on newer silicon, we only need to configure | |
3198 | * collision distance in the Transmit Control Register. | |
3199 | * 2) Set up flow control on the MAC to that established with | |
3200 | * the link partner. | |
3201 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. | |
3202 | * | |
3203 | * hw - Struct containing variables accessed by shared code | |
3204 | ******************************************************************************/ | |
3205 | static int32_t | |
3206 | e1000_copper_link_postconfig(struct e1000_hw *hw) | |
3207 | { | |
3208 | int32_t ret_val; | |
3209 | DEBUGFUNC(); | |
3210 | ||
3211 | if (hw->mac_type >= e1000_82544) { | |
3212 | e1000_config_collision_dist(hw); | |
3213 | } else { | |
3214 | ret_val = e1000_config_mac_to_phy(hw); | |
3215 | if (ret_val) { | |
3216 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | |
3217 | return ret_val; | |
3218 | } | |
3219 | } | |
3220 | ret_val = e1000_config_fc_after_link_up(hw); | |
3221 | if (ret_val) { | |
3222 | DEBUGOUT("Error Configuring Flow Control\n"); | |
682011ff WD |
3223 | return ret_val; |
3224 | } | |
aa070789 RZ |
3225 | return E1000_SUCCESS; |
3226 | } | |
3227 | ||
3228 | /****************************************************************************** | |
3229 | * Detects which PHY is present and setup the speed and duplex | |
3230 | * | |
3231 | * hw - Struct containing variables accessed by shared code | |
3232 | ******************************************************************************/ | |
3233 | static int | |
5c5e707a | 3234 | e1000_setup_copper_link(struct e1000_hw *hw) |
aa070789 | 3235 | { |
aa070789 RZ |
3236 | int32_t ret_val; |
3237 | uint16_t i; | |
3238 | uint16_t phy_data; | |
3239 | uint16_t reg_data; | |
3240 | ||
3241 | DEBUGFUNC(); | |
3242 | ||
3243 | switch (hw->mac_type) { | |
3244 | case e1000_80003es2lan: | |
3245 | case e1000_ich8lan: | |
3246 | /* Set the mac to wait the maximum time between each | |
3247 | * iteration and increase the max iterations when | |
3248 | * polling the phy; this fixes erroneous timeouts at 10Mbps. */ | |
3249 | ret_val = e1000_write_kmrn_reg(hw, | |
3250 | GG82563_REG(0x34, 4), 0xFFFF); | |
3251 | if (ret_val) | |
3252 | return ret_val; | |
3253 | ret_val = e1000_read_kmrn_reg(hw, | |
3254 | GG82563_REG(0x34, 9), ®_data); | |
3255 | if (ret_val) | |
3256 | return ret_val; | |
3257 | reg_data |= 0x3F; | |
3258 | ret_val = e1000_write_kmrn_reg(hw, | |
3259 | GG82563_REG(0x34, 9), reg_data); | |
3260 | if (ret_val) | |
3261 | return ret_val; | |
3262 | default: | |
3263 | break; | |
3264 | } | |
3265 | ||
3266 | /* Check if it is a valid PHY and set PHY mode if necessary. */ | |
3267 | ret_val = e1000_copper_link_preconfig(hw); | |
3268 | if (ret_val) | |
3269 | return ret_val; | |
3270 | switch (hw->mac_type) { | |
3271 | case e1000_80003es2lan: | |
3272 | /* Kumeran registers are written-only */ | |
3273 | reg_data = | |
3274 | E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; | |
3275 | reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; | |
3276 | ret_val = e1000_write_kmrn_reg(hw, | |
3277 | E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); | |
3278 | if (ret_val) | |
3279 | return ret_val; | |
3280 | break; | |
3281 | default: | |
3282 | break; | |
3283 | } | |
3284 | ||
3285 | if (hw->phy_type == e1000_phy_igp || | |
3286 | hw->phy_type == e1000_phy_igp_3 || | |
3287 | hw->phy_type == e1000_phy_igp_2) { | |
3288 | ret_val = e1000_copper_link_igp_setup(hw); | |
3289 | if (ret_val) | |
3290 | return ret_val; | |
95186063 MV |
3291 | } else if (hw->phy_type == e1000_phy_m88 || |
3292 | hw->phy_type == e1000_phy_igb) { | |
aa070789 RZ |
3293 | ret_val = e1000_copper_link_mgp_setup(hw); |
3294 | if (ret_val) | |
3295 | return ret_val; | |
3296 | } else if (hw->phy_type == e1000_phy_gg82563) { | |
3297 | ret_val = e1000_copper_link_ggp_setup(hw); | |
3298 | if (ret_val) | |
3299 | return ret_val; | |
3300 | } | |
3301 | ||
3302 | /* always auto */ | |
3303 | /* Setup autoneg and flow control advertisement | |
3304 | * and perform autonegotiation */ | |
3305 | ret_val = e1000_copper_link_autoneg(hw); | |
3306 | if (ret_val) | |
3307 | return ret_val; | |
682011ff WD |
3308 | |
3309 | /* Check link status. Wait up to 100 microseconds for link to become | |
3310 | * valid. | |
3311 | */ | |
3312 | for (i = 0; i < 10; i++) { | |
aa070789 RZ |
3313 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
3314 | if (ret_val) | |
3315 | return ret_val; | |
3316 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
3317 | if (ret_val) | |
3318 | return ret_val; | |
3319 | ||
682011ff | 3320 | if (phy_data & MII_SR_LINK_STATUS) { |
aa070789 RZ |
3321 | /* Config the MAC and PHY after link is up */ |
3322 | ret_val = e1000_copper_link_postconfig(hw); | |
3323 | if (ret_val) | |
682011ff | 3324 | return ret_val; |
aa070789 | 3325 | |
682011ff | 3326 | DEBUGOUT("Valid link established!!!\n"); |
aa070789 | 3327 | return E1000_SUCCESS; |
682011ff WD |
3328 | } |
3329 | udelay(10); | |
3330 | } | |
3331 | ||
3332 | DEBUGOUT("Unable to establish link!!!\n"); | |
aa070789 | 3333 | return E1000_SUCCESS; |
682011ff WD |
3334 | } |
3335 | ||
3336 | /****************************************************************************** | |
3337 | * Configures PHY autoneg and flow control advertisement settings | |
3338 | * | |
3339 | * hw - Struct containing variables accessed by shared code | |
3340 | ******************************************************************************/ | |
aa070789 | 3341 | int32_t |
682011ff WD |
3342 | e1000_phy_setup_autoneg(struct e1000_hw *hw) |
3343 | { | |
aa070789 | 3344 | int32_t ret_val; |
682011ff WD |
3345 | uint16_t mii_autoneg_adv_reg; |
3346 | uint16_t mii_1000t_ctrl_reg; | |
3347 | ||
3348 | DEBUGFUNC(); | |
3349 | ||
3350 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
aa070789 RZ |
3351 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
3352 | if (ret_val) | |
3353 | return ret_val; | |
682011ff | 3354 | |
aa070789 RZ |
3355 | if (hw->phy_type != e1000_phy_ife) { |
3356 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
3357 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, | |
3358 | &mii_1000t_ctrl_reg); | |
3359 | if (ret_val) | |
3360 | return ret_val; | |
3361 | } else | |
3362 | mii_1000t_ctrl_reg = 0; | |
682011ff WD |
3363 | |
3364 | /* Need to parse both autoneg_advertised and fc and set up | |
3365 | * the appropriate PHY registers. First we will parse for | |
3366 | * autoneg_advertised software override. Since we can advertise | |
3367 | * a plethora of combinations, we need to check each bit | |
3368 | * individually. | |
3369 | */ | |
3370 | ||
3371 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg | |
3372 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
aa070789 | 3373 | * the 1000Base-T Control Register (Address 9). |
682011ff WD |
3374 | */ |
3375 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; | |
3376 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; | |
3377 | ||
3378 | DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); | |
3379 | ||
3380 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
3381 | if (hw->autoneg_advertised & ADVERTISE_10_HALF) { | |
3382 | DEBUGOUT("Advertise 10mb Half duplex\n"); | |
3383 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; | |
3384 | } | |
3385 | ||
3386 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
3387 | if (hw->autoneg_advertised & ADVERTISE_10_FULL) { | |
3388 | DEBUGOUT("Advertise 10mb Full duplex\n"); | |
3389 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; | |
3390 | } | |
3391 | ||
3392 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
3393 | if (hw->autoneg_advertised & ADVERTISE_100_HALF) { | |
3394 | DEBUGOUT("Advertise 100mb Half duplex\n"); | |
3395 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; | |
3396 | } | |
3397 | ||
3398 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
3399 | if (hw->autoneg_advertised & ADVERTISE_100_FULL) { | |
3400 | DEBUGOUT("Advertise 100mb Full duplex\n"); | |
3401 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; | |
3402 | } | |
3403 | ||
3404 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
3405 | if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { | |
3406 | DEBUGOUT | |
3407 | ("Advertise 1000mb Half duplex requested, request denied!\n"); | |
3408 | } | |
3409 | ||
3410 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
3411 | if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { | |
3412 | DEBUGOUT("Advertise 1000mb Full duplex\n"); | |
3413 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; | |
3414 | } | |
3415 | ||
3416 | /* Check for a software override of the flow control settings, and | |
3417 | * setup the PHY advertisement registers accordingly. If | |
3418 | * auto-negotiation is enabled, then software will have to set the | |
3419 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
3420 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. | |
3421 | * | |
3422 | * The possible values of the "fc" parameter are: | |
1aeed8d7 WD |
3423 | * 0: Flow control is completely disabled |
3424 | * 1: Rx flow control is enabled (we can receive pause frames | |
3425 | * but not send pause frames). | |
3426 | * 2: Tx flow control is enabled (we can send pause frames | |
3427 | * but we do not support receiving pause frames). | |
3428 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
682011ff | 3429 | * other: No software override. The flow control configuration |
1aeed8d7 | 3430 | * in the EEPROM is used. |
682011ff WD |
3431 | */ |
3432 | switch (hw->fc) { | |
3433 | case e1000_fc_none: /* 0 */ | |
3434 | /* Flow control (RX & TX) is completely disabled by a | |
3435 | * software over-ride. | |
3436 | */ | |
3437 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
3438 | break; | |
3439 | case e1000_fc_rx_pause: /* 1 */ | |
3440 | /* RX Flow control is enabled, and TX Flow control is | |
3441 | * disabled, by a software over-ride. | |
3442 | */ | |
3443 | /* Since there really isn't a way to advertise that we are | |
3444 | * capable of RX Pause ONLY, we will advertise that we | |
3445 | * support both symmetric and asymmetric RX PAUSE. Later | |
3446 | * (in e1000_config_fc_after_link_up) we will disable the | |
3447 | *hw's ability to send PAUSE frames. | |
3448 | */ | |
3449 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
3450 | break; | |
3451 | case e1000_fc_tx_pause: /* 2 */ | |
3452 | /* TX Flow control is enabled, and RX Flow control is | |
3453 | * disabled, by a software over-ride. | |
3454 | */ | |
3455 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
3456 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
3457 | break; | |
3458 | case e1000_fc_full: /* 3 */ | |
3459 | /* Flow control (both RX and TX) is enabled by a software | |
3460 | * over-ride. | |
3461 | */ | |
3462 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
3463 | break; | |
3464 | default: | |
3465 | DEBUGOUT("Flow control param set incorrectly\n"); | |
3466 | return -E1000_ERR_CONFIG; | |
3467 | } | |
3468 | ||
aa070789 RZ |
3469 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
3470 | if (ret_val) | |
3471 | return ret_val; | |
682011ff WD |
3472 | |
3473 | DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); | |
3474 | ||
aa070789 RZ |
3475 | if (hw->phy_type != e1000_phy_ife) { |
3476 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, | |
3477 | mii_1000t_ctrl_reg); | |
3478 | if (ret_val) | |
3479 | return ret_val; | |
682011ff | 3480 | } |
aa070789 RZ |
3481 | |
3482 | return E1000_SUCCESS; | |
682011ff WD |
3483 | } |
3484 | ||
3485 | /****************************************************************************** | |
3486 | * Sets the collision distance in the Transmit Control register | |
3487 | * | |
3488 | * hw - Struct containing variables accessed by shared code | |
3489 | * | |
3490 | * Link should have been established previously. Reads the speed and duplex | |
3491 | * information from the Device Status register. | |
3492 | ******************************************************************************/ | |
3493 | static void | |
3494 | e1000_config_collision_dist(struct e1000_hw *hw) | |
3495 | { | |
aa070789 RZ |
3496 | uint32_t tctl, coll_dist; |
3497 | ||
3498 | DEBUGFUNC(); | |
3499 | ||
3500 | if (hw->mac_type < e1000_82543) | |
3501 | coll_dist = E1000_COLLISION_DISTANCE_82542; | |
3502 | else | |
3503 | coll_dist = E1000_COLLISION_DISTANCE; | |
682011ff WD |
3504 | |
3505 | tctl = E1000_READ_REG(hw, TCTL); | |
3506 | ||
3507 | tctl &= ~E1000_TCTL_COLD; | |
aa070789 | 3508 | tctl |= coll_dist << E1000_COLD_SHIFT; |
682011ff WD |
3509 | |
3510 | E1000_WRITE_REG(hw, TCTL, tctl); | |
3511 | E1000_WRITE_FLUSH(hw); | |
3512 | } | |
3513 | ||
3514 | /****************************************************************************** | |
3515 | * Sets MAC speed and duplex settings to reflect the those in the PHY | |
3516 | * | |
3517 | * hw - Struct containing variables accessed by shared code | |
3518 | * mii_reg - data to write to the MII control register | |
3519 | * | |
3520 | * The contents of the PHY register containing the needed information need to | |
3521 | * be passed in. | |
3522 | ******************************************************************************/ | |
3523 | static int | |
3524 | e1000_config_mac_to_phy(struct e1000_hw *hw) | |
3525 | { | |
3526 | uint32_t ctrl; | |
3527 | uint16_t phy_data; | |
3528 | ||
3529 | DEBUGFUNC(); | |
3530 | ||
3531 | /* Read the Device Control Register and set the bits to Force Speed | |
3532 | * and Duplex. | |
3533 | */ | |
3534 | ctrl = E1000_READ_REG(hw, CTRL); | |
3535 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
95186063 MV |
3536 | ctrl &= ~(E1000_CTRL_ILOS); |
3537 | ctrl |= (E1000_CTRL_SPD_SEL); | |
682011ff WD |
3538 | |
3539 | /* Set up duplex in the Device Control and Transmit Control | |
3540 | * registers depending on negotiated values. | |
3541 | */ | |
3542 | if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { | |
3543 | DEBUGOUT("PHY Read Error\n"); | |
3544 | return -E1000_ERR_PHY; | |
3545 | } | |
3546 | if (phy_data & M88E1000_PSSR_DPLX) | |
3547 | ctrl |= E1000_CTRL_FD; | |
3548 | else | |
3549 | ctrl &= ~E1000_CTRL_FD; | |
3550 | ||
3551 | e1000_config_collision_dist(hw); | |
3552 | ||
3553 | /* Set up speed in the Device Control register depending on | |
3554 | * negotiated values. | |
3555 | */ | |
3556 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) | |
3557 | ctrl |= E1000_CTRL_SPD_1000; | |
3558 | else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) | |
3559 | ctrl |= E1000_CTRL_SPD_100; | |
3560 | /* Write the configured values back to the Device Control Reg. */ | |
3561 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3562 | return 0; | |
3563 | } | |
3564 | ||
3565 | /****************************************************************************** | |
3566 | * Forces the MAC's flow control settings. | |
8bde7f77 | 3567 | * |
682011ff WD |
3568 | * hw - Struct containing variables accessed by shared code |
3569 | * | |
3570 | * Sets the TFCE and RFCE bits in the device control register to reflect | |
3571 | * the adapter settings. TFCE and RFCE need to be explicitly set by | |
3572 | * software when a Copper PHY is used because autonegotiation is managed | |
3573 | * by the PHY rather than the MAC. Software must also configure these | |
3574 | * bits when link is forced on a fiber connection. | |
3575 | *****************************************************************************/ | |
3576 | static int | |
3577 | e1000_force_mac_fc(struct e1000_hw *hw) | |
3578 | { | |
3579 | uint32_t ctrl; | |
3580 | ||
3581 | DEBUGFUNC(); | |
3582 | ||
3583 | /* Get the current configuration of the Device Control Register */ | |
3584 | ctrl = E1000_READ_REG(hw, CTRL); | |
3585 | ||
3586 | /* Because we didn't get link via the internal auto-negotiation | |
3587 | * mechanism (we either forced link or we got link via PHY | |
3588 | * auto-neg), we have to manually enable/disable transmit an | |
3589 | * receive flow control. | |
3590 | * | |
3591 | * The "Case" statement below enables/disable flow control | |
3592 | * according to the "hw->fc" parameter. | |
3593 | * | |
3594 | * The possible values of the "fc" parameter are: | |
1aeed8d7 WD |
3595 | * 0: Flow control is completely disabled |
3596 | * 1: Rx flow control is enabled (we can receive pause | |
3597 | * frames but not send pause frames). | |
3598 | * 2: Tx flow control is enabled (we can send pause frames | |
3599 | * frames but we do not receive pause frames). | |
3600 | * 3: Both Rx and TX flow control (symmetric) is enabled. | |
682011ff WD |
3601 | * other: No other values should be possible at this point. |
3602 | */ | |
3603 | ||
3604 | switch (hw->fc) { | |
3605 | case e1000_fc_none: | |
3606 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); | |
3607 | break; | |
3608 | case e1000_fc_rx_pause: | |
3609 | ctrl &= (~E1000_CTRL_TFCE); | |
3610 | ctrl |= E1000_CTRL_RFCE; | |
3611 | break; | |
3612 | case e1000_fc_tx_pause: | |
3613 | ctrl &= (~E1000_CTRL_RFCE); | |
3614 | ctrl |= E1000_CTRL_TFCE; | |
3615 | break; | |
3616 | case e1000_fc_full: | |
3617 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); | |
3618 | break; | |
3619 | default: | |
3620 | DEBUGOUT("Flow control param set incorrectly\n"); | |
3621 | return -E1000_ERR_CONFIG; | |
3622 | } | |
3623 | ||
3624 | /* Disable TX Flow Control for 82542 (rev 2.0) */ | |
3625 | if (hw->mac_type == e1000_82542_rev2_0) | |
3626 | ctrl &= (~E1000_CTRL_TFCE); | |
3627 | ||
3628 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3629 | return 0; | |
3630 | } | |
3631 | ||
3632 | /****************************************************************************** | |
3633 | * Configures flow control settings after link is established | |
8bde7f77 | 3634 | * |
682011ff WD |
3635 | * hw - Struct containing variables accessed by shared code |
3636 | * | |
3637 | * Should be called immediately after a valid link has been established. | |
3638 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode | |
3639 | * and autonegotiation is enabled, the MAC flow control settings will be set | |
3640 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE | |
3641 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. | |
3642 | *****************************************************************************/ | |
aa070789 | 3643 | static int32_t |
682011ff WD |
3644 | e1000_config_fc_after_link_up(struct e1000_hw *hw) |
3645 | { | |
3646 | int32_t ret_val; | |
3647 | uint16_t mii_status_reg; | |
3648 | uint16_t mii_nway_adv_reg; | |
3649 | uint16_t mii_nway_lp_ability_reg; | |
3650 | uint16_t speed; | |
3651 | uint16_t duplex; | |
3652 | ||
3653 | DEBUGFUNC(); | |
3654 | ||
3655 | /* Check for the case where we have fiber media and auto-neg failed | |
3656 | * so we had to force link. In this case, we need to force the | |
3657 | * configuration of the MAC to match the "fc" parameter. | |
3658 | */ | |
aa070789 RZ |
3659 | if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) |
3660 | || ((hw->media_type == e1000_media_type_internal_serdes) | |
3661 | && (hw->autoneg_failed)) | |
3662 | || ((hw->media_type == e1000_media_type_copper) | |
3663 | && (!hw->autoneg))) { | |
682011ff WD |
3664 | ret_val = e1000_force_mac_fc(hw); |
3665 | if (ret_val < 0) { | |
3666 | DEBUGOUT("Error forcing flow control settings\n"); | |
3667 | return ret_val; | |
3668 | } | |
3669 | } | |
3670 | ||
3671 | /* Check for the case where we have copper media and auto-neg is | |
3672 | * enabled. In this case, we need to check and see if Auto-Neg | |
3673 | * has completed, and if so, how the PHY and link partner has | |
3674 | * flow control configured. | |
3675 | */ | |
3676 | if (hw->media_type == e1000_media_type_copper) { | |
3677 | /* Read the MII Status Register and check to see if AutoNeg | |
3678 | * has completed. We read this twice because this reg has | |
3679 | * some "sticky" (latched) bits. | |
3680 | */ | |
3681 | if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { | |
5abf13e4 | 3682 | DEBUGOUT("PHY Read Error\n"); |
682011ff WD |
3683 | return -E1000_ERR_PHY; |
3684 | } | |
3685 | if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { | |
5abf13e4 | 3686 | DEBUGOUT("PHY Read Error\n"); |
682011ff WD |
3687 | return -E1000_ERR_PHY; |
3688 | } | |
3689 | ||
3690 | if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { | |
3691 | /* The AutoNeg process has completed, so we now need to | |
3692 | * read both the Auto Negotiation Advertisement Register | |
3693 | * (Address 4) and the Auto_Negotiation Base Page Ability | |
3694 | * Register (Address 5) to determine how flow control was | |
3695 | * negotiated. | |
3696 | */ | |
3697 | if (e1000_read_phy_reg | |
3698 | (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { | |
3699 | DEBUGOUT("PHY Read Error\n"); | |
3700 | return -E1000_ERR_PHY; | |
3701 | } | |
3702 | if (e1000_read_phy_reg | |
3703 | (hw, PHY_LP_ABILITY, | |
3704 | &mii_nway_lp_ability_reg) < 0) { | |
3705 | DEBUGOUT("PHY Read Error\n"); | |
3706 | return -E1000_ERR_PHY; | |
3707 | } | |
3708 | ||
3709 | /* Two bits in the Auto Negotiation Advertisement Register | |
3710 | * (Address 4) and two bits in the Auto Negotiation Base | |
3711 | * Page Ability Register (Address 5) determine flow control | |
3712 | * for both the PHY and the link partner. The following | |
3713 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | |
3714 | * 1999, describes these PAUSE resolution bits and how flow | |
3715 | * control is determined based upon these settings. | |
3716 | * NOTE: DC = Don't Care | |
3717 | * | |
3718 | * LOCAL DEVICE | LINK PARTNER | |
3719 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | |
3720 | *-------|---------|-------|---------|-------------------- | |
1aeed8d7 WD |
3721 | * 0 | 0 | DC | DC | e1000_fc_none |
3722 | * 0 | 1 | 0 | DC | e1000_fc_none | |
3723 | * 0 | 1 | 1 | 0 | e1000_fc_none | |
3724 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
3725 | * 1 | 0 | 0 | DC | e1000_fc_none | |
3726 | * 1 | DC | 1 | DC | e1000_fc_full | |
3727 | * 1 | 1 | 0 | 0 | e1000_fc_none | |
3728 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
682011ff WD |
3729 | * |
3730 | */ | |
3731 | /* Are both PAUSE bits set to 1? If so, this implies | |
3732 | * Symmetric Flow Control is enabled at both ends. The | |
3733 | * ASM_DIR bits are irrelevant per the spec. | |
3734 | * | |
3735 | * For Symmetric Flow Control: | |
3736 | * | |
3737 | * LOCAL DEVICE | LINK PARTNER | |
3738 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
3739 | *-------|---------|-------|---------|-------------------- | |
1aeed8d7 | 3740 | * 1 | DC | 1 | DC | e1000_fc_full |
682011ff WD |
3741 | * |
3742 | */ | |
3743 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
3744 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { | |
3745 | /* Now we need to check if the user selected RX ONLY | |
3746 | * of pause frames. In this case, we had to advertise | |
3747 | * FULL flow control because we could not advertise RX | |
3748 | * ONLY. Hence, we must now check to see if we need to | |
3749 | * turn OFF the TRANSMISSION of PAUSE frames. | |
3750 | */ | |
3751 | if (hw->original_fc == e1000_fc_full) { | |
3752 | hw->fc = e1000_fc_full; | |
3753 | DEBUGOUT("Flow Control = FULL.\r\n"); | |
3754 | } else { | |
3755 | hw->fc = e1000_fc_rx_pause; | |
3756 | DEBUGOUT | |
3757 | ("Flow Control = RX PAUSE frames only.\r\n"); | |
3758 | } | |
3759 | } | |
3760 | /* For receiving PAUSE frames ONLY. | |
3761 | * | |
3762 | * LOCAL DEVICE | LINK PARTNER | |
3763 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
3764 | *-------|---------|-------|---------|-------------------- | |
1aeed8d7 | 3765 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
682011ff WD |
3766 | * |
3767 | */ | |
3768 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
3769 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
3770 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
3771 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) | |
3772 | { | |
3773 | hw->fc = e1000_fc_tx_pause; | |
3774 | DEBUGOUT | |
3775 | ("Flow Control = TX PAUSE frames only.\r\n"); | |
3776 | } | |
3777 | /* For transmitting PAUSE frames ONLY. | |
3778 | * | |
3779 | * LOCAL DEVICE | LINK PARTNER | |
3780 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
3781 | *-------|---------|-------|---------|-------------------- | |
1aeed8d7 | 3782 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
682011ff WD |
3783 | * |
3784 | */ | |
3785 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
3786 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
3787 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
3788 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) | |
3789 | { | |
3790 | hw->fc = e1000_fc_rx_pause; | |
3791 | DEBUGOUT | |
3792 | ("Flow Control = RX PAUSE frames only.\r\n"); | |
3793 | } | |
3794 | /* Per the IEEE spec, at this point flow control should be | |
3795 | * disabled. However, we want to consider that we could | |
3796 | * be connected to a legacy switch that doesn't advertise | |
3797 | * desired flow control, but can be forced on the link | |
3798 | * partner. So if we advertised no flow control, that is | |
3799 | * what we will resolve to. If we advertised some kind of | |
3800 | * receive capability (Rx Pause Only or Full Flow Control) | |
3801 | * and the link partner advertised none, we will configure | |
3802 | * ourselves to enable Rx Flow Control only. We can do | |
3803 | * this safely for two reasons: If the link partner really | |
3804 | * didn't want flow control enabled, and we enable Rx, no | |
3805 | * harm done since we won't be receiving any PAUSE frames | |
3806 | * anyway. If the intent on the link partner was to have | |
3807 | * flow control enabled, then by us enabling RX only, we | |
3808 | * can at least receive pause frames and process them. | |
3809 | * This is a good idea because in most cases, since we are | |
3810 | * predominantly a server NIC, more times than not we will | |
3811 | * be asked to delay transmission of packets than asking | |
3812 | * our link partner to pause transmission of frames. | |
3813 | */ | |
3814 | else if (hw->original_fc == e1000_fc_none || | |
3815 | hw->original_fc == e1000_fc_tx_pause) { | |
3816 | hw->fc = e1000_fc_none; | |
3817 | DEBUGOUT("Flow Control = NONE.\r\n"); | |
3818 | } else { | |
3819 | hw->fc = e1000_fc_rx_pause; | |
3820 | DEBUGOUT | |
3821 | ("Flow Control = RX PAUSE frames only.\r\n"); | |
3822 | } | |
3823 | ||
1aeed8d7 | 3824 | /* Now we need to do one last check... If we auto- |
682011ff WD |
3825 | * negotiated to HALF DUPLEX, flow control should not be |
3826 | * enabled per IEEE 802.3 spec. | |
3827 | */ | |
3828 | e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
3829 | ||
3830 | if (duplex == HALF_DUPLEX) | |
3831 | hw->fc = e1000_fc_none; | |
3832 | ||
3833 | /* Now we call a subroutine to actually force the MAC | |
3834 | * controller to use the correct flow control settings. | |
3835 | */ | |
3836 | ret_val = e1000_force_mac_fc(hw); | |
3837 | if (ret_val < 0) { | |
3838 | DEBUGOUT | |
3839 | ("Error forcing flow control settings\n"); | |
3840 | return ret_val; | |
3841 | } | |
3842 | } else { | |
3843 | DEBUGOUT | |
3844 | ("Copper PHY and Auto Neg has not completed.\r\n"); | |
3845 | } | |
3846 | } | |
aa070789 | 3847 | return E1000_SUCCESS; |
682011ff WD |
3848 | } |
3849 | ||
3850 | /****************************************************************************** | |
3851 | * Checks to see if the link status of the hardware has changed. | |
3852 | * | |
3853 | * hw - Struct containing variables accessed by shared code | |
3854 | * | |
3855 | * Called by any function that needs to check the link status of the adapter. | |
3856 | *****************************************************************************/ | |
3857 | static int | |
5c5e707a | 3858 | e1000_check_for_link(struct e1000_hw *hw) |
682011ff | 3859 | { |
682011ff WD |
3860 | uint32_t rxcw; |
3861 | uint32_t ctrl; | |
3862 | uint32_t status; | |
3863 | uint32_t rctl; | |
3864 | uint32_t signal; | |
3865 | int32_t ret_val; | |
3866 | uint16_t phy_data; | |
3867 | uint16_t lp_capability; | |
3868 | ||
3869 | DEBUGFUNC(); | |
3870 | ||
8bde7f77 WD |
3871 | /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be |
3872 | * set when the optics detect a signal. On older adapters, it will be | |
682011ff WD |
3873 | * cleared when there is a signal |
3874 | */ | |
3875 | ctrl = E1000_READ_REG(hw, CTRL); | |
3876 | if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) | |
3877 | signal = E1000_CTRL_SWDPIN1; | |
3878 | else | |
3879 | signal = 0; | |
3880 | ||
3881 | status = E1000_READ_REG(hw, STATUS); | |
3882 | rxcw = E1000_READ_REG(hw, RXCW); | |
3883 | DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); | |
3884 | ||
3885 | /* If we have a copper PHY then we only want to go out to the PHY | |
3886 | * registers to see if Auto-Neg has completed and/or if our link | |
1aeed8d7 | 3887 | * status has changed. The get_link_status flag will be set if we |
682011ff WD |
3888 | * receive a Link Status Change interrupt or we have Rx Sequence |
3889 | * Errors. | |
3890 | */ | |
3891 | if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { | |
3892 | /* First we want to see if the MII Status Register reports | |
3893 | * link. If so, then we want to get the current speed/duplex | |
3894 | * of the PHY. | |
3895 | * Read the register twice since the link bit is sticky. | |
3896 | */ | |
3897 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { | |
3898 | DEBUGOUT("PHY Read Error\n"); | |
3899 | return -E1000_ERR_PHY; | |
3900 | } | |
3901 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { | |
3902 | DEBUGOUT("PHY Read Error\n"); | |
3903 | return -E1000_ERR_PHY; | |
3904 | } | |
3905 | ||
3906 | if (phy_data & MII_SR_LINK_STATUS) { | |
472d5460 | 3907 | hw->get_link_status = false; |
682011ff WD |
3908 | } else { |
3909 | /* No link detected */ | |
3910 | return -E1000_ERR_NOLINK; | |
3911 | } | |
3912 | ||
3913 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we | |
3914 | * have Si on board that is 82544 or newer, Auto | |
3915 | * Speed Detection takes care of MAC speed/duplex | |
3916 | * configuration. So we only need to configure Collision | |
3917 | * Distance in the MAC. Otherwise, we need to force | |
3918 | * speed/duplex on the MAC to the current PHY speed/duplex | |
3919 | * settings. | |
3920 | */ | |
3921 | if (hw->mac_type >= e1000_82544) | |
3922 | e1000_config_collision_dist(hw); | |
3923 | else { | |
3924 | ret_val = e1000_config_mac_to_phy(hw); | |
3925 | if (ret_val < 0) { | |
3926 | DEBUGOUT | |
3927 | ("Error configuring MAC to PHY settings\n"); | |
3928 | return ret_val; | |
3929 | } | |
3930 | } | |
3931 | ||
8bde7f77 | 3932 | /* Configure Flow Control now that Auto-Neg has completed. First, we |
682011ff WD |
3933 | * need to restore the desired flow control settings because we may |
3934 | * have had to re-autoneg with a different link partner. | |
3935 | */ | |
3936 | ret_val = e1000_config_fc_after_link_up(hw); | |
3937 | if (ret_val < 0) { | |
3938 | DEBUGOUT("Error configuring flow control\n"); | |
3939 | return ret_val; | |
3940 | } | |
3941 | ||
3942 | /* At this point we know that we are on copper and we have | |
3943 | * auto-negotiated link. These are conditions for checking the link | |
1aeed8d7 | 3944 | * parter capability register. We use the link partner capability to |
682011ff WD |
3945 | * determine if TBI Compatibility needs to be turned on or off. If |
3946 | * the link partner advertises any speed in addition to Gigabit, then | |
3947 | * we assume that they are GMII-based, and TBI compatibility is not | |
3948 | * needed. If no other speeds are advertised, we assume the link | |
3949 | * partner is TBI-based, and we turn on TBI Compatibility. | |
3950 | */ | |
3951 | if (hw->tbi_compatibility_en) { | |
3952 | if (e1000_read_phy_reg | |
3953 | (hw, PHY_LP_ABILITY, &lp_capability) < 0) { | |
3954 | DEBUGOUT("PHY Read Error\n"); | |
3955 | return -E1000_ERR_PHY; | |
3956 | } | |
3957 | if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | | |
3958 | NWAY_LPAR_10T_FD_CAPS | | |
3959 | NWAY_LPAR_100TX_HD_CAPS | | |
3960 | NWAY_LPAR_100TX_FD_CAPS | | |
3961 | NWAY_LPAR_100T4_CAPS)) { | |
8bde7f77 | 3962 | /* If our link partner advertises anything in addition to |
682011ff WD |
3963 | * gigabit, we do not need to enable TBI compatibility. |
3964 | */ | |
3965 | if (hw->tbi_compatibility_on) { | |
3966 | /* If we previously were in the mode, turn it off. */ | |
3967 | rctl = E1000_READ_REG(hw, RCTL); | |
3968 | rctl &= ~E1000_RCTL_SBP; | |
3969 | E1000_WRITE_REG(hw, RCTL, rctl); | |
472d5460 | 3970 | hw->tbi_compatibility_on = false; |
682011ff WD |
3971 | } |
3972 | } else { | |
3973 | /* If TBI compatibility is was previously off, turn it on. For | |
3974 | * compatibility with a TBI link partner, we will store bad | |
3975 | * packets. Some frames have an additional byte on the end and | |
3976 | * will look like CRC errors to to the hardware. | |
3977 | */ | |
3978 | if (!hw->tbi_compatibility_on) { | |
472d5460 | 3979 | hw->tbi_compatibility_on = true; |
682011ff WD |
3980 | rctl = E1000_READ_REG(hw, RCTL); |
3981 | rctl |= E1000_RCTL_SBP; | |
3982 | E1000_WRITE_REG(hw, RCTL, rctl); | |
3983 | } | |
3984 | } | |
3985 | } | |
3986 | } | |
3987 | /* If we don't have link (auto-negotiation failed or link partner cannot | |
3988 | * auto-negotiate), the cable is plugged in (we have signal), and our | |
3989 | * link partner is not trying to auto-negotiate with us (we are receiving | |
3990 | * idles or data), we need to force link up. We also need to give | |
3991 | * auto-negotiation time to complete, in case the cable was just plugged | |
3992 | * in. The autoneg_failed flag does this. | |
3993 | */ | |
3994 | else if ((hw->media_type == e1000_media_type_fiber) && | |
3995 | (!(status & E1000_STATUS_LU)) && | |
3996 | ((ctrl & E1000_CTRL_SWDPIN1) == signal) && | |
3997 | (!(rxcw & E1000_RXCW_C))) { | |
3998 | if (hw->autoneg_failed == 0) { | |
3999 | hw->autoneg_failed = 1; | |
4000 | return 0; | |
4001 | } | |
4002 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); | |
4003 | ||
4004 | /* Disable auto-negotiation in the TXCW register */ | |
4005 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); | |
4006 | ||
4007 | /* Force link-up and also force full-duplex. */ | |
4008 | ctrl = E1000_READ_REG(hw, CTRL); | |
4009 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
4010 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
4011 | ||
4012 | /* Configure Flow Control after forcing link up. */ | |
4013 | ret_val = e1000_config_fc_after_link_up(hw); | |
4014 | if (ret_val < 0) { | |
4015 | DEBUGOUT("Error configuring flow control\n"); | |
4016 | return ret_val; | |
4017 | } | |
4018 | } | |
4019 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable | |
4020 | * auto-negotiation in the TXCW register and disable forced link in the | |
4021 | * Device Control register in an attempt to auto-negotiate with our link | |
4022 | * partner. | |
4023 | */ | |
4024 | else if ((hw->media_type == e1000_media_type_fiber) && | |
4025 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | |
4026 | DEBUGOUT | |
4027 | ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); | |
4028 | E1000_WRITE_REG(hw, TXCW, hw->txcw); | |
4029 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); | |
4030 | } | |
4031 | return 0; | |
4032 | } | |
4033 | ||
aa070789 RZ |
4034 | /****************************************************************************** |
4035 | * Configure the MAC-to-PHY interface for 10/100Mbps | |
4036 | * | |
4037 | * hw - Struct containing variables accessed by shared code | |
4038 | ******************************************************************************/ | |
4039 | static int32_t | |
4040 | e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) | |
4041 | { | |
4042 | int32_t ret_val = E1000_SUCCESS; | |
4043 | uint32_t tipg; | |
4044 | uint16_t reg_data; | |
4045 | ||
4046 | DEBUGFUNC(); | |
4047 | ||
4048 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
4049 | ret_val = e1000_write_kmrn_reg(hw, | |
4050 | E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); | |
4051 | if (ret_val) | |
4052 | return ret_val; | |
4053 | ||
4054 | /* Configure Transmit Inter-Packet Gap */ | |
4055 | tipg = E1000_READ_REG(hw, TIPG); | |
4056 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
4057 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; | |
4058 | E1000_WRITE_REG(hw, TIPG, tipg); | |
4059 | ||
4060 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
4061 | ||
4062 | if (ret_val) | |
4063 | return ret_val; | |
4064 | ||
4065 | if (duplex == HALF_DUPLEX) | |
4066 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
4067 | else | |
4068 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
4069 | ||
4070 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
4071 | ||
4072 | return ret_val; | |
4073 | } | |
4074 | ||
4075 | static int32_t | |
4076 | e1000_configure_kmrn_for_1000(struct e1000_hw *hw) | |
4077 | { | |
4078 | int32_t ret_val = E1000_SUCCESS; | |
4079 | uint16_t reg_data; | |
4080 | uint32_t tipg; | |
4081 | ||
4082 | DEBUGFUNC(); | |
4083 | ||
4084 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; | |
4085 | ret_val = e1000_write_kmrn_reg(hw, | |
4086 | E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data); | |
4087 | if (ret_val) | |
4088 | return ret_val; | |
4089 | ||
4090 | /* Configure Transmit Inter-Packet Gap */ | |
4091 | tipg = E1000_READ_REG(hw, TIPG); | |
4092 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
4093 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
4094 | E1000_WRITE_REG(hw, TIPG, tipg); | |
4095 | ||
4096 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
4097 | ||
4098 | if (ret_val) | |
4099 | return ret_val; | |
4100 | ||
4101 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
4102 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
4103 | ||
4104 | return ret_val; | |
4105 | } | |
4106 | ||
682011ff WD |
4107 | /****************************************************************************** |
4108 | * Detects the current speed and duplex settings of the hardware. | |
4109 | * | |
4110 | * hw - Struct containing variables accessed by shared code | |
4111 | * speed - Speed of the connection | |
4112 | * duplex - Duplex setting of the connection | |
4113 | *****************************************************************************/ | |
aa070789 RZ |
4114 | static int |
4115 | e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, | |
4116 | uint16_t *duplex) | |
682011ff WD |
4117 | { |
4118 | uint32_t status; | |
aa070789 RZ |
4119 | int32_t ret_val; |
4120 | uint16_t phy_data; | |
682011ff WD |
4121 | |
4122 | DEBUGFUNC(); | |
4123 | ||
4124 | if (hw->mac_type >= e1000_82543) { | |
4125 | status = E1000_READ_REG(hw, STATUS); | |
4126 | if (status & E1000_STATUS_SPEED_1000) { | |
4127 | *speed = SPEED_1000; | |
4128 | DEBUGOUT("1000 Mbs, "); | |
4129 | } else if (status & E1000_STATUS_SPEED_100) { | |
4130 | *speed = SPEED_100; | |
4131 | DEBUGOUT("100 Mbs, "); | |
4132 | } else { | |
4133 | *speed = SPEED_10; | |
4134 | DEBUGOUT("10 Mbs, "); | |
4135 | } | |
4136 | ||
4137 | if (status & E1000_STATUS_FD) { | |
4138 | *duplex = FULL_DUPLEX; | |
4139 | DEBUGOUT("Full Duplex\r\n"); | |
4140 | } else { | |
4141 | *duplex = HALF_DUPLEX; | |
4142 | DEBUGOUT(" Half Duplex\r\n"); | |
4143 | } | |
4144 | } else { | |
4145 | DEBUGOUT("1000 Mbs, Full Duplex\r\n"); | |
4146 | *speed = SPEED_1000; | |
4147 | *duplex = FULL_DUPLEX; | |
4148 | } | |
aa070789 RZ |
4149 | |
4150 | /* IGP01 PHY may advertise full duplex operation after speed downgrade | |
4151 | * even if it is operating at half duplex. Here we set the duplex | |
4152 | * settings to match the duplex in the link partner's capabilities. | |
4153 | */ | |
4154 | if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { | |
4155 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); | |
4156 | if (ret_val) | |
4157 | return ret_val; | |
4158 | ||
4159 | if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) | |
4160 | *duplex = HALF_DUPLEX; | |
4161 | else { | |
4162 | ret_val = e1000_read_phy_reg(hw, | |
4163 | PHY_LP_ABILITY, &phy_data); | |
4164 | if (ret_val) | |
4165 | return ret_val; | |
4166 | if ((*speed == SPEED_100 && | |
4167 | !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) | |
4168 | || (*speed == SPEED_10 | |
4169 | && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) | |
4170 | *duplex = HALF_DUPLEX; | |
4171 | } | |
4172 | } | |
4173 | ||
4174 | if ((hw->mac_type == e1000_80003es2lan) && | |
4175 | (hw->media_type == e1000_media_type_copper)) { | |
4176 | if (*speed == SPEED_1000) | |
4177 | ret_val = e1000_configure_kmrn_for_1000(hw); | |
4178 | else | |
4179 | ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); | |
4180 | if (ret_val) | |
4181 | return ret_val; | |
4182 | } | |
4183 | return E1000_SUCCESS; | |
682011ff WD |
4184 | } |
4185 | ||
4186 | /****************************************************************************** | |
4187 | * Blocks until autoneg completes or times out (~4.5 seconds) | |
4188 | * | |
4189 | * hw - Struct containing variables accessed by shared code | |
4190 | ******************************************************************************/ | |
4191 | static int | |
4192 | e1000_wait_autoneg(struct e1000_hw *hw) | |
4193 | { | |
4194 | uint16_t i; | |
4195 | uint16_t phy_data; | |
4196 | ||
4197 | DEBUGFUNC(); | |
4198 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); | |
4199 | ||
faa765d4 | 4200 | /* We will wait for autoneg to complete or timeout to expire. */ |
682011ff WD |
4201 | for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
4202 | /* Read the MII Status Register and wait for Auto-Neg | |
4203 | * Complete bit to be set. | |
4204 | */ | |
4205 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { | |
4206 | DEBUGOUT("PHY Read Error\n"); | |
4207 | return -E1000_ERR_PHY; | |
4208 | } | |
4209 | if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { | |
4210 | DEBUGOUT("PHY Read Error\n"); | |
4211 | return -E1000_ERR_PHY; | |
4212 | } | |
4213 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { | |
4214 | DEBUGOUT("Auto-Neg complete.\n"); | |
4215 | return 0; | |
4216 | } | |
4217 | mdelay(100); | |
4218 | } | |
4219 | DEBUGOUT("Auto-Neg timedout.\n"); | |
4220 | return -E1000_ERR_TIMEOUT; | |
4221 | } | |
4222 | ||
4223 | /****************************************************************************** | |
4224 | * Raises the Management Data Clock | |
4225 | * | |
4226 | * hw - Struct containing variables accessed by shared code | |
4227 | * ctrl - Device control register's current value | |
4228 | ******************************************************************************/ | |
4229 | static void | |
4230 | e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) | |
4231 | { | |
4232 | /* Raise the clock input to the Management Data Clock (by setting the MDC | |
4233 | * bit), and then delay 2 microseconds. | |
4234 | */ | |
4235 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); | |
4236 | E1000_WRITE_FLUSH(hw); | |
4237 | udelay(2); | |
4238 | } | |
4239 | ||
4240 | /****************************************************************************** | |
4241 | * Lowers the Management Data Clock | |
4242 | * | |
4243 | * hw - Struct containing variables accessed by shared code | |
4244 | * ctrl - Device control register's current value | |
4245 | ******************************************************************************/ | |
4246 | static void | |
4247 | e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) | |
4248 | { | |
4249 | /* Lower the clock input to the Management Data Clock (by clearing the MDC | |
4250 | * bit), and then delay 2 microseconds. | |
4251 | */ | |
4252 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); | |
4253 | E1000_WRITE_FLUSH(hw); | |
4254 | udelay(2); | |
4255 | } | |
4256 | ||
4257 | /****************************************************************************** | |
4258 | * Shifts data bits out to the PHY | |
4259 | * | |
4260 | * hw - Struct containing variables accessed by shared code | |
4261 | * data - Data to send out to the PHY | |
4262 | * count - Number of bits to shift out | |
4263 | * | |
4264 | * Bits are shifted out in MSB to LSB order. | |
4265 | ******************************************************************************/ | |
4266 | static void | |
4267 | e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) | |
4268 | { | |
4269 | uint32_t ctrl; | |
4270 | uint32_t mask; | |
4271 | ||
4272 | /* We need to shift "count" number of bits out to the PHY. So, the value | |
8bde7f77 | 4273 | * in the "data" parameter will be shifted out to the PHY one bit at a |
682011ff WD |
4274 | * time. In order to do this, "data" must be broken down into bits. |
4275 | */ | |
4276 | mask = 0x01; | |
4277 | mask <<= (count - 1); | |
4278 | ||
4279 | ctrl = E1000_READ_REG(hw, CTRL); | |
4280 | ||
4281 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ | |
4282 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); | |
4283 | ||
4284 | while (mask) { | |
4285 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and | |
4286 | * then raising and lowering the Management Data Clock. A "0" is | |
4287 | * shifted out to the PHY by setting the MDIO bit to "0" and then | |
4288 | * raising and lowering the clock. | |
4289 | */ | |
4290 | if (data & mask) | |
4291 | ctrl |= E1000_CTRL_MDIO; | |
4292 | else | |
4293 | ctrl &= ~E1000_CTRL_MDIO; | |
4294 | ||
4295 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
4296 | E1000_WRITE_FLUSH(hw); | |
4297 | ||
4298 | udelay(2); | |
4299 | ||
4300 | e1000_raise_mdi_clk(hw, &ctrl); | |
4301 | e1000_lower_mdi_clk(hw, &ctrl); | |
4302 | ||
4303 | mask = mask >> 1; | |
4304 | } | |
4305 | } | |
4306 | ||
4307 | /****************************************************************************** | |
4308 | * Shifts data bits in from the PHY | |
4309 | * | |
4310 | * hw - Struct containing variables accessed by shared code | |
4311 | * | |
8bde7f77 | 4312 | * Bits are shifted in in MSB to LSB order. |
682011ff WD |
4313 | ******************************************************************************/ |
4314 | static uint16_t | |
4315 | e1000_shift_in_mdi_bits(struct e1000_hw *hw) | |
4316 | { | |
4317 | uint32_t ctrl; | |
4318 | uint16_t data = 0; | |
4319 | uint8_t i; | |
4320 | ||
4321 | /* In order to read a register from the PHY, we need to shift in a total | |
4322 | * of 18 bits from the PHY. The first two bit (turnaround) times are used | |
4323 | * to avoid contention on the MDIO pin when a read operation is performed. | |
4324 | * These two bits are ignored by us and thrown away. Bits are "shifted in" | |
4325 | * by raising the input to the Management Data Clock (setting the MDC bit), | |
4326 | * and then reading the value of the MDIO bit. | |
4327 | */ | |
4328 | ctrl = E1000_READ_REG(hw, CTRL); | |
4329 | ||
4330 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ | |
4331 | ctrl &= ~E1000_CTRL_MDIO_DIR; | |
4332 | ctrl &= ~E1000_CTRL_MDIO; | |
4333 | ||
4334 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
4335 | E1000_WRITE_FLUSH(hw); | |
4336 | ||
4337 | /* Raise and Lower the clock before reading in the data. This accounts for | |
4338 | * the turnaround bits. The first clock occurred when we clocked out the | |
4339 | * last bit of the Register Address. | |
4340 | */ | |
4341 | e1000_raise_mdi_clk(hw, &ctrl); | |
4342 | e1000_lower_mdi_clk(hw, &ctrl); | |
4343 | ||
4344 | for (data = 0, i = 0; i < 16; i++) { | |
4345 | data = data << 1; | |
4346 | e1000_raise_mdi_clk(hw, &ctrl); | |
4347 | ctrl = E1000_READ_REG(hw, CTRL); | |
4348 | /* Check to see if we shifted in a "1". */ | |
4349 | if (ctrl & E1000_CTRL_MDIO) | |
4350 | data |= 1; | |
4351 | e1000_lower_mdi_clk(hw, &ctrl); | |
4352 | } | |
4353 | ||
4354 | e1000_raise_mdi_clk(hw, &ctrl); | |
4355 | e1000_lower_mdi_clk(hw, &ctrl); | |
4356 | ||
4357 | return data; | |
4358 | } | |
4359 | ||
4360 | /***************************************************************************** | |
4361 | * Reads the value from a PHY register | |
4362 | * | |
4363 | * hw - Struct containing variables accessed by shared code | |
4364 | * reg_addr - address of the PHY register to read | |
4365 | ******************************************************************************/ | |
4366 | static int | |
4367 | e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) | |
4368 | { | |
4369 | uint32_t i; | |
4370 | uint32_t mdic = 0; | |
4371 | const uint32_t phy_addr = 1; | |
4372 | ||
4373 | if (reg_addr > MAX_PHY_REG_ADDRESS) { | |
4374 | DEBUGOUT("PHY Address %d is out of range\n", reg_addr); | |
4375 | return -E1000_ERR_PARAM; | |
4376 | } | |
4377 | ||
4378 | if (hw->mac_type > e1000_82543) { | |
4379 | /* Set up Op-code, Phy Address, and register address in the MDI | |
4380 | * Control register. The MAC will take care of interfacing with the | |
4381 | * PHY to retrieve the desired data. | |
4382 | */ | |
4383 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | | |
4384 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
4385 | (E1000_MDIC_OP_READ)); | |
4386 | ||
4387 | E1000_WRITE_REG(hw, MDIC, mdic); | |
4388 | ||
4389 | /* Poll the ready bit to see if the MDI read completed */ | |
4390 | for (i = 0; i < 64; i++) { | |
4391 | udelay(10); | |
4392 | mdic = E1000_READ_REG(hw, MDIC); | |
4393 | if (mdic & E1000_MDIC_READY) | |
4394 | break; | |
4395 | } | |
4396 | if (!(mdic & E1000_MDIC_READY)) { | |
4397 | DEBUGOUT("MDI Read did not complete\n"); | |
4398 | return -E1000_ERR_PHY; | |
4399 | } | |
4400 | if (mdic & E1000_MDIC_ERROR) { | |
4401 | DEBUGOUT("MDI Error\n"); | |
4402 | return -E1000_ERR_PHY; | |
4403 | } | |
4404 | *phy_data = (uint16_t) mdic; | |
4405 | } else { | |
4406 | /* We must first send a preamble through the MDIO pin to signal the | |
4407 | * beginning of an MII instruction. This is done by sending 32 | |
4408 | * consecutive "1" bits. | |
4409 | */ | |
4410 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
4411 | ||
4412 | /* Now combine the next few fields that are required for a read | |
4413 | * operation. We use this method instead of calling the | |
4414 | * e1000_shift_out_mdi_bits routine five different times. The format of | |
4415 | * a MII read instruction consists of a shift out of 14 bits and is | |
4416 | * defined as follows: | |
4417 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> | |
4418 | * followed by a shift in of 18 bits. This first two bits shifted in | |
4419 | * are TurnAround bits used to avoid contention on the MDIO pin when a | |
4420 | * READ operation is performed. These two bits are thrown away | |
4421 | * followed by a shift in of 16 bits which contains the desired data. | |
4422 | */ | |
4423 | mdic = ((reg_addr) | (phy_addr << 5) | | |
4424 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); | |
4425 | ||
4426 | e1000_shift_out_mdi_bits(hw, mdic, 14); | |
4427 | ||
4428 | /* Now that we've shifted out the read command to the MII, we need to | |
4429 | * "shift in" the 16-bit value (18 total bits) of the requested PHY | |
4430 | * register address. | |
4431 | */ | |
4432 | *phy_data = e1000_shift_in_mdi_bits(hw); | |
4433 | } | |
4434 | return 0; | |
4435 | } | |
4436 | ||
4437 | /****************************************************************************** | |
4438 | * Writes a value to a PHY register | |
4439 | * | |
4440 | * hw - Struct containing variables accessed by shared code | |
4441 | * reg_addr - address of the PHY register to write | |
4442 | * data - data to write to the PHY | |
4443 | ******************************************************************************/ | |
4444 | static int | |
4445 | e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) | |
4446 | { | |
4447 | uint32_t i; | |
4448 | uint32_t mdic = 0; | |
4449 | const uint32_t phy_addr = 1; | |
4450 | ||
4451 | if (reg_addr > MAX_PHY_REG_ADDRESS) { | |
4452 | DEBUGOUT("PHY Address %d is out of range\n", reg_addr); | |
4453 | return -E1000_ERR_PARAM; | |
4454 | } | |
4455 | ||
4456 | if (hw->mac_type > e1000_82543) { | |
4457 | /* Set up Op-code, Phy Address, register address, and data intended | |
4458 | * for the PHY register in the MDI Control register. The MAC will take | |
4459 | * care of interfacing with the PHY to send the desired data. | |
4460 | */ | |
4461 | mdic = (((uint32_t) phy_data) | | |
4462 | (reg_addr << E1000_MDIC_REG_SHIFT) | | |
4463 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
4464 | (E1000_MDIC_OP_WRITE)); | |
4465 | ||
4466 | E1000_WRITE_REG(hw, MDIC, mdic); | |
4467 | ||
4468 | /* Poll the ready bit to see if the MDI read completed */ | |
4469 | for (i = 0; i < 64; i++) { | |
4470 | udelay(10); | |
4471 | mdic = E1000_READ_REG(hw, MDIC); | |
4472 | if (mdic & E1000_MDIC_READY) | |
4473 | break; | |
4474 | } | |
4475 | if (!(mdic & E1000_MDIC_READY)) { | |
4476 | DEBUGOUT("MDI Write did not complete\n"); | |
4477 | return -E1000_ERR_PHY; | |
4478 | } | |
4479 | } else { | |
4480 | /* We'll need to use the SW defined pins to shift the write command | |
4481 | * out to the PHY. We first send a preamble to the PHY to signal the | |
8bde7f77 | 4482 | * beginning of the MII instruction. This is done by sending 32 |
682011ff WD |
4483 | * consecutive "1" bits. |
4484 | */ | |
4485 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
4486 | ||
8bde7f77 | 4487 | /* Now combine the remaining required fields that will indicate a |
682011ff WD |
4488 | * write operation. We use this method instead of calling the |
4489 | * e1000_shift_out_mdi_bits routine for each field in the command. The | |
4490 | * format of a MII write instruction is as follows: | |
4491 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. | |
4492 | */ | |
4493 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | | |
4494 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); | |
4495 | mdic <<= 16; | |
4496 | mdic |= (uint32_t) phy_data; | |
4497 | ||
4498 | e1000_shift_out_mdi_bits(hw, mdic, 32); | |
4499 | } | |
4500 | return 0; | |
4501 | } | |
4502 | ||
aa070789 RZ |
4503 | /****************************************************************************** |
4504 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. | |
4505 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to | |
4506 | * the caller to figure out how to deal with it. | |
4507 | * | |
4508 | * hw - Struct containing variables accessed by shared code | |
4509 | * | |
4510 | * returns: - E1000_BLK_PHY_RESET | |
4511 | * E1000_SUCCESS | |
4512 | * | |
4513 | *****************************************************************************/ | |
4514 | int32_t | |
4515 | e1000_check_phy_reset_block(struct e1000_hw *hw) | |
4516 | { | |
4517 | uint32_t manc = 0; | |
4518 | uint32_t fwsm = 0; | |
4519 | ||
4520 | if (hw->mac_type == e1000_ich8lan) { | |
4521 | fwsm = E1000_READ_REG(hw, FWSM); | |
4522 | return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS | |
4523 | : E1000_BLK_PHY_RESET; | |
4524 | } | |
4525 | ||
4526 | if (hw->mac_type > e1000_82547_rev_2) | |
4527 | manc = E1000_READ_REG(hw, MANC); | |
4528 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
4529 | E1000_BLK_PHY_RESET : E1000_SUCCESS; | |
4530 | } | |
4531 | ||
4532 | /*************************************************************************** | |
4533 | * Checks if the PHY configuration is done | |
4534 | * | |
4535 | * hw: Struct containing variables accessed by shared code | |
4536 | * | |
4537 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
4538 | * E1000_SUCCESS at any other case. | |
4539 | * | |
4540 | ***************************************************************************/ | |
4541 | static int32_t | |
4542 | e1000_get_phy_cfg_done(struct e1000_hw *hw) | |
4543 | { | |
4544 | int32_t timeout = PHY_CFG_TIMEOUT; | |
4545 | uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; | |
4546 | ||
4547 | DEBUGFUNC(); | |
4548 | ||
4549 | switch (hw->mac_type) { | |
4550 | default: | |
4551 | mdelay(10); | |
4552 | break; | |
987b43a1 | 4553 | |
aa070789 RZ |
4554 | case e1000_80003es2lan: |
4555 | /* Separate *_CFG_DONE_* bit for each port */ | |
987b43a1 | 4556 | if (e1000_is_second_port(hw)) |
aa070789 | 4557 | cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; |
987b43a1 KM |
4558 | /* Fall Through */ |
4559 | ||
aa070789 RZ |
4560 | case e1000_82571: |
4561 | case e1000_82572: | |
95186063 | 4562 | case e1000_igb: |
aa070789 | 4563 | while (timeout) { |
95186063 MV |
4564 | if (hw->mac_type == e1000_igb) { |
4565 | if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) | |
4566 | break; | |
4567 | } else { | |
4568 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) | |
4569 | break; | |
4570 | } | |
4571 | mdelay(1); | |
aa070789 RZ |
4572 | timeout--; |
4573 | } | |
4574 | if (!timeout) { | |
4575 | DEBUGOUT("MNG configuration cycle has not " | |
4576 | "completed.\n"); | |
4577 | return -E1000_ERR_RESET; | |
4578 | } | |
4579 | break; | |
4580 | } | |
4581 | ||
4582 | return E1000_SUCCESS; | |
4583 | } | |
4584 | ||
682011ff WD |
4585 | /****************************************************************************** |
4586 | * Returns the PHY to the power-on reset state | |
4587 | * | |
4588 | * hw - Struct containing variables accessed by shared code | |
4589 | ******************************************************************************/ | |
aa070789 | 4590 | int32_t |
682011ff WD |
4591 | e1000_phy_hw_reset(struct e1000_hw *hw) |
4592 | { | |
987b43a1 | 4593 | uint16_t swfw = E1000_SWFW_PHY0_SM; |
aa070789 RZ |
4594 | uint32_t ctrl, ctrl_ext; |
4595 | uint32_t led_ctrl; | |
4596 | int32_t ret_val; | |
682011ff WD |
4597 | |
4598 | DEBUGFUNC(); | |
4599 | ||
aa070789 RZ |
4600 | /* In the case of the phy reset being blocked, it's not an error, we |
4601 | * simply return success without performing the reset. */ | |
4602 | ret_val = e1000_check_phy_reset_block(hw); | |
4603 | if (ret_val) | |
4604 | return E1000_SUCCESS; | |
4605 | ||
682011ff WD |
4606 | DEBUGOUT("Resetting Phy...\n"); |
4607 | ||
4608 | if (hw->mac_type > e1000_82543) { | |
987b43a1 | 4609 | if (e1000_is_second_port(hw)) |
aa070789 | 4610 | swfw = E1000_SWFW_PHY1_SM; |
987b43a1 | 4611 | |
aa070789 RZ |
4612 | if (e1000_swfw_sync_acquire(hw, swfw)) { |
4613 | DEBUGOUT("Unable to acquire swfw sync\n"); | |
4614 | return -E1000_ERR_SWFW_SYNC; | |
4615 | } | |
987b43a1 | 4616 | |
682011ff WD |
4617 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
4618 | * bit. Then, take it out of reset. | |
4619 | */ | |
4620 | ctrl = E1000_READ_REG(hw, CTRL); | |
4621 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); | |
4622 | E1000_WRITE_FLUSH(hw); | |
aa070789 RZ |
4623 | |
4624 | if (hw->mac_type < e1000_82571) | |
4625 | udelay(10); | |
4626 | else | |
4627 | udelay(100); | |
4628 | ||
682011ff WD |
4629 | E1000_WRITE_REG(hw, CTRL, ctrl); |
4630 | E1000_WRITE_FLUSH(hw); | |
aa070789 RZ |
4631 | |
4632 | if (hw->mac_type >= e1000_82571) | |
4633 | mdelay(10); | |
3c63dd53 | 4634 | |
682011ff WD |
4635 | } else { |
4636 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR | |
4637 | * bit to put the PHY into reset. Then, take it out of reset. | |
4638 | */ | |
4639 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
4640 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; | |
4641 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; | |
4642 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
4643 | E1000_WRITE_FLUSH(hw); | |
4644 | mdelay(10); | |
4645 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; | |
4646 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
4647 | E1000_WRITE_FLUSH(hw); | |
4648 | } | |
4649 | udelay(150); | |
aa070789 RZ |
4650 | |
4651 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
4652 | /* Configure activity LED after PHY reset */ | |
4653 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
4654 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
4655 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
4656 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
4657 | } | |
4658 | ||
7e2d991d TH |
4659 | e1000_swfw_sync_release(hw, swfw); |
4660 | ||
aa070789 RZ |
4661 | /* Wait for FW to finish PHY configuration. */ |
4662 | ret_val = e1000_get_phy_cfg_done(hw); | |
4663 | if (ret_val != E1000_SUCCESS) | |
4664 | return ret_val; | |
4665 | ||
4666 | return ret_val; | |
4667 | } | |
4668 | ||
4669 | /****************************************************************************** | |
4670 | * IGP phy init script - initializes the GbE PHY | |
4671 | * | |
4672 | * hw - Struct containing variables accessed by shared code | |
4673 | *****************************************************************************/ | |
4674 | static void | |
4675 | e1000_phy_init_script(struct e1000_hw *hw) | |
4676 | { | |
4677 | uint32_t ret_val; | |
4678 | uint16_t phy_saved_data; | |
4679 | DEBUGFUNC(); | |
4680 | ||
4681 | if (hw->phy_init_script) { | |
4682 | mdelay(20); | |
4683 | ||
4684 | /* Save off the current value of register 0x2F5B to be | |
4685 | * restored at the end of this routine. */ | |
4686 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
4687 | ||
4688 | /* Disabled the PHY transmitter */ | |
4689 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
4690 | ||
4691 | mdelay(20); | |
4692 | ||
4693 | e1000_write_phy_reg(hw, 0x0000, 0x0140); | |
4694 | ||
4695 | mdelay(5); | |
4696 | ||
4697 | switch (hw->mac_type) { | |
4698 | case e1000_82541: | |
4699 | case e1000_82547: | |
4700 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); | |
4701 | ||
4702 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); | |
4703 | ||
4704 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); | |
4705 | ||
4706 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); | |
4707 | ||
4708 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); | |
4709 | ||
4710 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); | |
4711 | ||
4712 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); | |
4713 | ||
4714 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); | |
4715 | ||
4716 | e1000_write_phy_reg(hw, 0x2010, 0x0008); | |
4717 | break; | |
4718 | ||
4719 | case e1000_82541_rev_2: | |
4720 | case e1000_82547_rev_2: | |
4721 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); | |
4722 | break; | |
4723 | default: | |
4724 | break; | |
4725 | } | |
4726 | ||
4727 | e1000_write_phy_reg(hw, 0x0000, 0x3300); | |
4728 | ||
4729 | mdelay(20); | |
4730 | ||
4731 | /* Now enable the transmitter */ | |
56b13b1e ZRR |
4732 | if (!ret_val) |
4733 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
aa070789 RZ |
4734 | |
4735 | if (hw->mac_type == e1000_82547) { | |
4736 | uint16_t fused, fine, coarse; | |
4737 | ||
4738 | /* Move to analog registers page */ | |
4739 | e1000_read_phy_reg(hw, | |
4740 | IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); | |
4741 | ||
4742 | if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { | |
4743 | e1000_read_phy_reg(hw, | |
4744 | IGP01E1000_ANALOG_FUSE_STATUS, &fused); | |
4745 | ||
4746 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; | |
4747 | coarse = fused | |
4748 | & IGP01E1000_ANALOG_FUSE_COARSE_MASK; | |
4749 | ||
4750 | if (coarse > | |
4751 | IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { | |
4752 | coarse -= | |
4753 | IGP01E1000_ANALOG_FUSE_COARSE_10; | |
4754 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; | |
4755 | } else if (coarse | |
4756 | == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) | |
4757 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; | |
4758 | ||
4759 | fused = (fused | |
4760 | & IGP01E1000_ANALOG_FUSE_POLY_MASK) | | |
4761 | (fine | |
4762 | & IGP01E1000_ANALOG_FUSE_FINE_MASK) | | |
4763 | (coarse | |
4764 | & IGP01E1000_ANALOG_FUSE_COARSE_MASK); | |
4765 | ||
4766 | e1000_write_phy_reg(hw, | |
4767 | IGP01E1000_ANALOG_FUSE_CONTROL, fused); | |
4768 | e1000_write_phy_reg(hw, | |
4769 | IGP01E1000_ANALOG_FUSE_BYPASS, | |
4770 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); | |
4771 | } | |
4772 | } | |
4773 | } | |
682011ff WD |
4774 | } |
4775 | ||
4776 | /****************************************************************************** | |
4777 | * Resets the PHY | |
4778 | * | |
4779 | * hw - Struct containing variables accessed by shared code | |
4780 | * | |
aa070789 | 4781 | * Sets bit 15 of the MII Control register |
682011ff | 4782 | ******************************************************************************/ |
aa070789 | 4783 | int32_t |
682011ff WD |
4784 | e1000_phy_reset(struct e1000_hw *hw) |
4785 | { | |
aa070789 | 4786 | int32_t ret_val; |
682011ff WD |
4787 | uint16_t phy_data; |
4788 | ||
4789 | DEBUGFUNC(); | |
4790 | ||
aa070789 RZ |
4791 | /* In the case of the phy reset being blocked, it's not an error, we |
4792 | * simply return success without performing the reset. */ | |
4793 | ret_val = e1000_check_phy_reset_block(hw); | |
4794 | if (ret_val) | |
4795 | return E1000_SUCCESS; | |
4796 | ||
4797 | switch (hw->phy_type) { | |
4798 | case e1000_phy_igp: | |
4799 | case e1000_phy_igp_2: | |
4800 | case e1000_phy_igp_3: | |
4801 | case e1000_phy_ife: | |
95186063 | 4802 | case e1000_phy_igb: |
aa070789 RZ |
4803 | ret_val = e1000_phy_hw_reset(hw); |
4804 | if (ret_val) | |
4805 | return ret_val; | |
4806 | break; | |
4807 | default: | |
4808 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | |
4809 | if (ret_val) | |
4810 | return ret_val; | |
4811 | ||
4812 | phy_data |= MII_CR_RESET; | |
4813 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
4814 | if (ret_val) | |
4815 | return ret_val; | |
4816 | ||
4817 | udelay(1); | |
4818 | break; | |
682011ff | 4819 | } |
aa070789 RZ |
4820 | |
4821 | if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) | |
4822 | e1000_phy_init_script(hw); | |
4823 | ||
4824 | return E1000_SUCCESS; | |
682011ff WD |
4825 | } |
4826 | ||
1aeed8d7 | 4827 | static int e1000_set_phy_type (struct e1000_hw *hw) |
ac3315c2 | 4828 | { |
1aeed8d7 WD |
4829 | DEBUGFUNC (); |
4830 | ||
4831 | if (hw->mac_type == e1000_undefined) | |
4832 | return -E1000_ERR_PHY_TYPE; | |
4833 | ||
4834 | switch (hw->phy_id) { | |
4835 | case M88E1000_E_PHY_ID: | |
4836 | case M88E1000_I_PHY_ID: | |
4837 | case M88E1011_I_PHY_ID: | |
aa070789 | 4838 | case M88E1111_I_PHY_ID: |
1aeed8d7 WD |
4839 | hw->phy_type = e1000_phy_m88; |
4840 | break; | |
4841 | case IGP01E1000_I_PHY_ID: | |
4842 | if (hw->mac_type == e1000_82541 || | |
aa070789 RZ |
4843 | hw->mac_type == e1000_82541_rev_2 || |
4844 | hw->mac_type == e1000_82547 || | |
4845 | hw->mac_type == e1000_82547_rev_2) { | |
1aeed8d7 | 4846 | hw->phy_type = e1000_phy_igp; |
aa070789 RZ |
4847 | break; |
4848 | } | |
4849 | case IGP03E1000_E_PHY_ID: | |
4850 | hw->phy_type = e1000_phy_igp_3; | |
4851 | break; | |
4852 | case IFE_E_PHY_ID: | |
4853 | case IFE_PLUS_E_PHY_ID: | |
4854 | case IFE_C_E_PHY_ID: | |
4855 | hw->phy_type = e1000_phy_ife; | |
4856 | break; | |
4857 | case GG82563_E_PHY_ID: | |
4858 | if (hw->mac_type == e1000_80003es2lan) { | |
4859 | hw->phy_type = e1000_phy_gg82563; | |
1aeed8d7 WD |
4860 | break; |
4861 | } | |
2c2668f9 RZ |
4862 | case BME1000_E_PHY_ID: |
4863 | hw->phy_type = e1000_phy_bm; | |
4864 | break; | |
95186063 MV |
4865 | case I210_I_PHY_ID: |
4866 | hw->phy_type = e1000_phy_igb; | |
4867 | break; | |
1aeed8d7 WD |
4868 | /* Fall Through */ |
4869 | default: | |
4870 | /* Should never have loaded on this device */ | |
4871 | hw->phy_type = e1000_phy_undefined; | |
4872 | return -E1000_ERR_PHY_TYPE; | |
4873 | } | |
4874 | ||
4875 | return E1000_SUCCESS; | |
ac3315c2 AS |
4876 | } |
4877 | ||
682011ff WD |
4878 | /****************************************************************************** |
4879 | * Probes the expected PHY address for known PHY IDs | |
4880 | * | |
4881 | * hw - Struct containing variables accessed by shared code | |
4882 | ******************************************************************************/ | |
aa070789 | 4883 | static int32_t |
682011ff WD |
4884 | e1000_detect_gig_phy(struct e1000_hw *hw) |
4885 | { | |
aa070789 | 4886 | int32_t phy_init_status, ret_val; |
682011ff | 4887 | uint16_t phy_id_high, phy_id_low; |
472d5460 | 4888 | bool match = false; |
682011ff WD |
4889 | |
4890 | DEBUGFUNC(); | |
4891 | ||
aa070789 RZ |
4892 | /* The 82571 firmware may still be configuring the PHY. In this |
4893 | * case, we cannot access the PHY until the configuration is done. So | |
4894 | * we explicitly set the PHY values. */ | |
4895 | if (hw->mac_type == e1000_82571 || | |
4896 | hw->mac_type == e1000_82572) { | |
4897 | hw->phy_id = IGP01E1000_I_PHY_ID; | |
4898 | hw->phy_type = e1000_phy_igp_2; | |
4899 | return E1000_SUCCESS; | |
682011ff | 4900 | } |
aa070789 RZ |
4901 | |
4902 | /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a | |
4903 | * work- around that forces PHY page 0 to be set or the reads fail. | |
4904 | * The rest of the code in this routine uses e1000_read_phy_reg to | |
4905 | * read the PHY ID. So for ESB-2 we need to have this set so our | |
4906 | * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, | |
4907 | * the routines below will figure this out as well. */ | |
4908 | if (hw->mac_type == e1000_80003es2lan) | |
4909 | hw->phy_type = e1000_phy_gg82563; | |
4910 | ||
4911 | /* Read the PHY ID Registers to identify which PHY is onboard. */ | |
4912 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); | |
4913 | if (ret_val) | |
4914 | return ret_val; | |
4915 | ||
682011ff | 4916 | hw->phy_id = (uint32_t) (phy_id_high << 16); |
aa070789 RZ |
4917 | udelay(20); |
4918 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); | |
4919 | if (ret_val) | |
4920 | return ret_val; | |
4921 | ||
682011ff | 4922 | hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); |
aa070789 | 4923 | hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; |
682011ff WD |
4924 | |
4925 | switch (hw->mac_type) { | |
4926 | case e1000_82543: | |
4927 | if (hw->phy_id == M88E1000_E_PHY_ID) | |
472d5460 | 4928 | match = true; |
682011ff WD |
4929 | break; |
4930 | case e1000_82544: | |
4931 | if (hw->phy_id == M88E1000_I_PHY_ID) | |
472d5460 | 4932 | match = true; |
682011ff WD |
4933 | break; |
4934 | case e1000_82540: | |
4935 | case e1000_82545: | |
aa070789 | 4936 | case e1000_82545_rev_3: |
682011ff | 4937 | case e1000_82546: |
aa070789 | 4938 | case e1000_82546_rev_3: |
682011ff | 4939 | if (hw->phy_id == M88E1011_I_PHY_ID) |
472d5460 | 4940 | match = true; |
682011ff | 4941 | break; |
aa070789 | 4942 | case e1000_82541: |
ac3315c2 | 4943 | case e1000_82541_rev_2: |
aa070789 RZ |
4944 | case e1000_82547: |
4945 | case e1000_82547_rev_2: | |
ac3315c2 | 4946 | if(hw->phy_id == IGP01E1000_I_PHY_ID) |
472d5460 | 4947 | match = true; |
ac3315c2 AS |
4948 | |
4949 | break; | |
aa070789 RZ |
4950 | case e1000_82573: |
4951 | if (hw->phy_id == M88E1111_I_PHY_ID) | |
472d5460 | 4952 | match = true; |
aa070789 | 4953 | break; |
2c2668f9 RZ |
4954 | case e1000_82574: |
4955 | if (hw->phy_id == BME1000_E_PHY_ID) | |
472d5460 | 4956 | match = true; |
2c2668f9 | 4957 | break; |
aa070789 RZ |
4958 | case e1000_80003es2lan: |
4959 | if (hw->phy_id == GG82563_E_PHY_ID) | |
472d5460 | 4960 | match = true; |
aa070789 RZ |
4961 | break; |
4962 | case e1000_ich8lan: | |
4963 | if (hw->phy_id == IGP03E1000_E_PHY_ID) | |
472d5460 | 4964 | match = true; |
aa070789 | 4965 | if (hw->phy_id == IFE_E_PHY_ID) |
472d5460 | 4966 | match = true; |
aa070789 | 4967 | if (hw->phy_id == IFE_PLUS_E_PHY_ID) |
472d5460 | 4968 | match = true; |
aa070789 | 4969 | if (hw->phy_id == IFE_C_E_PHY_ID) |
472d5460 | 4970 | match = true; |
aa070789 | 4971 | break; |
95186063 MV |
4972 | case e1000_igb: |
4973 | if (hw->phy_id == I210_I_PHY_ID) | |
4974 | match = true; | |
4975 | break; | |
682011ff WD |
4976 | default: |
4977 | DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); | |
4978 | return -E1000_ERR_CONFIG; | |
4979 | } | |
ac3315c2 AS |
4980 | |
4981 | phy_init_status = e1000_set_phy_type(hw); | |
4982 | ||
4983 | if ((match) && (phy_init_status == E1000_SUCCESS)) { | |
682011ff WD |
4984 | DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); |
4985 | return 0; | |
4986 | } | |
4987 | DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); | |
4988 | return -E1000_ERR_PHY; | |
4989 | } | |
4990 | ||
aa070789 RZ |
4991 | /***************************************************************************** |
4992 | * Set media type and TBI compatibility. | |
4993 | * | |
4994 | * hw - Struct containing variables accessed by shared code | |
4995 | * **************************************************************************/ | |
4996 | void | |
4997 | e1000_set_media_type(struct e1000_hw *hw) | |
4998 | { | |
4999 | uint32_t status; | |
5000 | ||
5001 | DEBUGFUNC(); | |
5002 | ||
5003 | if (hw->mac_type != e1000_82543) { | |
5004 | /* tbi_compatibility is only valid on 82543 */ | |
472d5460 | 5005 | hw->tbi_compatibility_en = false; |
aa070789 RZ |
5006 | } |
5007 | ||
5008 | switch (hw->device_id) { | |
5009 | case E1000_DEV_ID_82545GM_SERDES: | |
5010 | case E1000_DEV_ID_82546GB_SERDES: | |
5011 | case E1000_DEV_ID_82571EB_SERDES: | |
5012 | case E1000_DEV_ID_82571EB_SERDES_DUAL: | |
5013 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
5014 | case E1000_DEV_ID_82572EI_SERDES: | |
5015 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
5016 | hw->media_type = e1000_media_type_internal_serdes; | |
5017 | break; | |
5018 | default: | |
5019 | switch (hw->mac_type) { | |
5020 | case e1000_82542_rev2_0: | |
5021 | case e1000_82542_rev2_1: | |
5022 | hw->media_type = e1000_media_type_fiber; | |
5023 | break; | |
5024 | case e1000_ich8lan: | |
5025 | case e1000_82573: | |
2c2668f9 | 5026 | case e1000_82574: |
95186063 | 5027 | case e1000_igb: |
aa070789 RZ |
5028 | /* The STATUS_TBIMODE bit is reserved or reused |
5029 | * for the this device. | |
5030 | */ | |
5031 | hw->media_type = e1000_media_type_copper; | |
5032 | break; | |
5033 | default: | |
5034 | status = E1000_READ_REG(hw, STATUS); | |
5035 | if (status & E1000_STATUS_TBIMODE) { | |
5036 | hw->media_type = e1000_media_type_fiber; | |
5037 | /* tbi_compatibility not valid on fiber */ | |
472d5460 | 5038 | hw->tbi_compatibility_en = false; |
aa070789 RZ |
5039 | } else { |
5040 | hw->media_type = e1000_media_type_copper; | |
5041 | } | |
5042 | break; | |
5043 | } | |
5044 | } | |
5045 | } | |
5046 | ||
682011ff WD |
5047 | /** |
5048 | * e1000_sw_init - Initialize general software structures (struct e1000_adapter) | |
5049 | * | |
5050 | * e1000_sw_init initializes the Adapter private data structure. | |
5051 | * Fields are initialized based on PCI device information and | |
5052 | * OS network device settings (MTU size). | |
5053 | **/ | |
5054 | ||
5055 | static int | |
5c5e707a | 5056 | e1000_sw_init(struct e1000_hw *hw) |
682011ff | 5057 | { |
682011ff WD |
5058 | int result; |
5059 | ||
5060 | /* PCI config space info */ | |
81dab9af BM |
5061 | #ifdef CONFIG_DM_ETH |
5062 | dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); | |
5063 | dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); | |
5064 | dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, | |
5065 | &hw->subsystem_vendor_id); | |
5066 | dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); | |
5067 | ||
5068 | dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); | |
5069 | dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); | |
5070 | #else | |
682011ff WD |
5071 | pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); |
5072 | pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); | |
5073 | pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, | |
5074 | &hw->subsystem_vendor_id); | |
5075 | pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); | |
5076 | ||
5077 | pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); | |
5078 | pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); | |
81dab9af | 5079 | #endif |
682011ff WD |
5080 | |
5081 | /* identify the MAC */ | |
5082 | result = e1000_set_mac_type(hw); | |
5083 | if (result) { | |
5c5e707a | 5084 | E1000_ERR(hw, "Unknown MAC Type\n"); |
682011ff WD |
5085 | return result; |
5086 | } | |
5087 | ||
aa070789 RZ |
5088 | switch (hw->mac_type) { |
5089 | default: | |
5090 | break; | |
5091 | case e1000_82541: | |
5092 | case e1000_82547: | |
5093 | case e1000_82541_rev_2: | |
5094 | case e1000_82547_rev_2: | |
5095 | hw->phy_init_script = 1; | |
5096 | break; | |
5097 | } | |
5098 | ||
682011ff WD |
5099 | /* flow control settings */ |
5100 | hw->fc_high_water = E1000_FC_HIGH_THRESH; | |
5101 | hw->fc_low_water = E1000_FC_LOW_THRESH; | |
5102 | hw->fc_pause_time = E1000_FC_PAUSE_TIME; | |
5103 | hw->fc_send_xon = 1; | |
5104 | ||
5105 | /* Media type - copper or fiber */ | |
95186063 | 5106 | hw->tbi_compatibility_en = true; |
aa070789 | 5107 | e1000_set_media_type(hw); |
682011ff WD |
5108 | |
5109 | if (hw->mac_type >= e1000_82543) { | |
5110 | uint32_t status = E1000_READ_REG(hw, STATUS); | |
5111 | ||
5112 | if (status & E1000_STATUS_TBIMODE) { | |
5113 | DEBUGOUT("fiber interface\n"); | |
5114 | hw->media_type = e1000_media_type_fiber; | |
5115 | } else { | |
5116 | DEBUGOUT("copper interface\n"); | |
5117 | hw->media_type = e1000_media_type_copper; | |
5118 | } | |
5119 | } else { | |
5120 | hw->media_type = e1000_media_type_fiber; | |
5121 | } | |
5122 | ||
472d5460 | 5123 | hw->wait_autoneg_complete = true; |
682011ff WD |
5124 | if (hw->mac_type < e1000_82543) |
5125 | hw->report_tx_early = 0; | |
5126 | else | |
5127 | hw->report_tx_early = 1; | |
5128 | ||
682011ff WD |
5129 | return E1000_SUCCESS; |
5130 | } | |
5131 | ||
5132 | void | |
5133 | fill_rx(struct e1000_hw *hw) | |
5134 | { | |
5135 | struct e1000_rx_desc *rd; | |
06e07f65 | 5136 | unsigned long flush_start, flush_end; |
682011ff WD |
5137 | |
5138 | rx_last = rx_tail; | |
5139 | rd = rx_base + rx_tail; | |
5140 | rx_tail = (rx_tail + 1) % 8; | |
5141 | memset(rd, 0, 16); | |
06e07f65 | 5142 | rd->buffer_addr = cpu_to_le64((unsigned long)packet); |
873e8e01 MV |
5143 | |
5144 | /* | |
5145 | * Make sure there are no stale data in WB over this area, which | |
5146 | * might get written into the memory while the e1000 also writes | |
5147 | * into the same memory area. | |
5148 | */ | |
06e07f65 ML |
5149 | invalidate_dcache_range((unsigned long)packet, |
5150 | (unsigned long)packet + 4096); | |
873e8e01 | 5151 | /* Dump the DMA descriptor into RAM. */ |
06e07f65 | 5152 | flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); |
873e8e01 MV |
5153 | flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); |
5154 | flush_dcache_range(flush_start, flush_end); | |
5155 | ||
682011ff WD |
5156 | E1000_WRITE_REG(hw, RDT, rx_tail); |
5157 | } | |
5158 | ||
5159 | /** | |
5160 | * e1000_configure_tx - Configure 8254x Transmit Unit after Reset | |
5161 | * @adapter: board private structure | |
5162 | * | |
5163 | * Configure the Tx unit of the MAC after a reset. | |
5164 | **/ | |
5165 | ||
5166 | static void | |
5167 | e1000_configure_tx(struct e1000_hw *hw) | |
5168 | { | |
682011ff | 5169 | unsigned long tctl; |
aa070789 RZ |
5170 | unsigned long tipg, tarc; |
5171 | uint32_t ipgr1, ipgr2; | |
682011ff | 5172 | |
1d8a078b BM |
5173 | E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base)); |
5174 | E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base)); | |
682011ff WD |
5175 | |
5176 | E1000_WRITE_REG(hw, TDLEN, 128); | |
5177 | ||
5178 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
5179 | E1000_WRITE_REG(hw, TDH, 0); | |
5180 | E1000_WRITE_REG(hw, TDT, 0); | |
5181 | tx_tail = 0; | |
5182 | ||
aa070789 RZ |
5183 | /* Set the default values for the Tx Inter Packet Gap timer */ |
5184 | if (hw->mac_type <= e1000_82547_rev_2 && | |
5185 | (hw->media_type == e1000_media_type_fiber || | |
5186 | hw->media_type == e1000_media_type_internal_serdes)) | |
5187 | tipg = DEFAULT_82543_TIPG_IPGT_FIBER; | |
5188 | else | |
5189 | tipg = DEFAULT_82543_TIPG_IPGT_COPPER; | |
5190 | ||
682011ff WD |
5191 | /* Set the default values for the Tx Inter Packet Gap timer */ |
5192 | switch (hw->mac_type) { | |
5193 | case e1000_82542_rev2_0: | |
5194 | case e1000_82542_rev2_1: | |
5195 | tipg = DEFAULT_82542_TIPG_IPGT; | |
aa070789 RZ |
5196 | ipgr1 = DEFAULT_82542_TIPG_IPGR1; |
5197 | ipgr2 = DEFAULT_82542_TIPG_IPGR2; | |
5198 | break; | |
5199 | case e1000_80003es2lan: | |
5200 | ipgr1 = DEFAULT_82543_TIPG_IPGR1; | |
5201 | ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; | |
682011ff WD |
5202 | break; |
5203 | default: | |
aa070789 RZ |
5204 | ipgr1 = DEFAULT_82543_TIPG_IPGR1; |
5205 | ipgr2 = DEFAULT_82543_TIPG_IPGR2; | |
5206 | break; | |
682011ff | 5207 | } |
aa070789 RZ |
5208 | tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT; |
5209 | tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT; | |
682011ff | 5210 | E1000_WRITE_REG(hw, TIPG, tipg); |
682011ff WD |
5211 | /* Program the Transmit Control Register */ |
5212 | tctl = E1000_READ_REG(hw, TCTL); | |
5213 | tctl &= ~E1000_TCTL_CT; | |
5214 | tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | | |
5215 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
aa070789 RZ |
5216 | |
5217 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { | |
5218 | tarc = E1000_READ_REG(hw, TARC0); | |
5219 | /* set the speed mode bit, we'll clear it if we're not at | |
5220 | * gigabit link later */ | |
5221 | /* git bit can be set to 1*/ | |
5222 | } else if (hw->mac_type == e1000_80003es2lan) { | |
5223 | tarc = E1000_READ_REG(hw, TARC0); | |
5224 | tarc |= 1; | |
5225 | E1000_WRITE_REG(hw, TARC0, tarc); | |
5226 | tarc = E1000_READ_REG(hw, TARC1); | |
5227 | tarc |= 1; | |
5228 | E1000_WRITE_REG(hw, TARC1, tarc); | |
5229 | } | |
5230 | ||
682011ff WD |
5231 | |
5232 | e1000_config_collision_dist(hw); | |
aa070789 RZ |
5233 | /* Setup Transmit Descriptor Settings for eop descriptor */ |
5234 | hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; | |
682011ff | 5235 | |
aa070789 RZ |
5236 | /* Need to set up RS bit */ |
5237 | if (hw->mac_type < e1000_82543) | |
5238 | hw->txd_cmd |= E1000_TXD_CMD_RPS; | |
682011ff | 5239 | else |
aa070789 | 5240 | hw->txd_cmd |= E1000_TXD_CMD_RS; |
95186063 MV |
5241 | |
5242 | ||
5243 | if (hw->mac_type == e1000_igb) { | |
5244 | E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); | |
5245 | ||
5246 | uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); | |
5247 | reg_txdctl |= 1 << 25; | |
5248 | E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); | |
5249 | mdelay(20); | |
5250 | } | |
5251 | ||
5252 | ||
5253 | ||
aa070789 | 5254 | E1000_WRITE_REG(hw, TCTL, tctl); |
95186063 MV |
5255 | |
5256 | ||
682011ff WD |
5257 | } |
5258 | ||
5259 | /** | |
5260 | * e1000_setup_rctl - configure the receive control register | |
5261 | * @adapter: Board private structure | |
5262 | **/ | |
5263 | static void | |
5264 | e1000_setup_rctl(struct e1000_hw *hw) | |
5265 | { | |
5266 | uint32_t rctl; | |
5267 | ||
5268 | rctl = E1000_READ_REG(hw, RCTL); | |
5269 | ||
5270 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
5271 | ||
aa070789 RZ |
5272 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
5273 | | E1000_RCTL_RDMTS_HALF; /* | | |
5274 | (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ | |
682011ff WD |
5275 | |
5276 | if (hw->tbi_compatibility_on == 1) | |
5277 | rctl |= E1000_RCTL_SBP; | |
5278 | else | |
5279 | rctl &= ~E1000_RCTL_SBP; | |
5280 | ||
5281 | rctl &= ~(E1000_RCTL_SZ_4096); | |
682011ff WD |
5282 | rctl |= E1000_RCTL_SZ_2048; |
5283 | rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); | |
682011ff WD |
5284 | E1000_WRITE_REG(hw, RCTL, rctl); |
5285 | } | |
5286 | ||
5287 | /** | |
5288 | * e1000_configure_rx - Configure 8254x Receive Unit after Reset | |
5289 | * @adapter: board private structure | |
5290 | * | |
5291 | * Configure the Rx unit of the MAC after a reset. | |
5292 | **/ | |
5293 | static void | |
5294 | e1000_configure_rx(struct e1000_hw *hw) | |
5295 | { | |
aa070789 | 5296 | unsigned long rctl, ctrl_ext; |
682011ff | 5297 | rx_tail = 0; |
1d8a078b | 5298 | |
682011ff WD |
5299 | /* make sure receives are disabled while setting up the descriptors */ |
5300 | rctl = E1000_READ_REG(hw, RCTL); | |
5301 | E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); | |
682011ff | 5302 | if (hw->mac_type >= e1000_82540) { |
682011ff WD |
5303 | /* Set the interrupt throttling rate. Value is calculated |
5304 | * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ | |
1aeed8d7 WD |
5305 | #define MAX_INTS_PER_SEC 8000 |
5306 | #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) | |
682011ff WD |
5307 | E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); |
5308 | } | |
5309 | ||
aa070789 RZ |
5310 | if (hw->mac_type >= e1000_82571) { |
5311 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
5312 | /* Reset delay timers after every interrupt */ | |
5313 | ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; | |
5314 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
5315 | E1000_WRITE_FLUSH(hw); | |
5316 | } | |
682011ff | 5317 | /* Setup the Base and Length of the Rx Descriptor Ring */ |
1d8a078b BM |
5318 | E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base)); |
5319 | E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base)); | |
682011ff WD |
5320 | |
5321 | E1000_WRITE_REG(hw, RDLEN, 128); | |
5322 | ||
5323 | /* Setup the HW Rx Head and Tail Descriptor Pointers */ | |
5324 | E1000_WRITE_REG(hw, RDH, 0); | |
5325 | E1000_WRITE_REG(hw, RDT, 0); | |
682011ff WD |
5326 | /* Enable Receives */ |
5327 | ||
95186063 MV |
5328 | if (hw->mac_type == e1000_igb) { |
5329 | ||
5330 | uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); | |
5331 | reg_rxdctl |= 1 << 25; | |
5332 | E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); | |
5333 | mdelay(20); | |
5334 | } | |
5335 | ||
682011ff | 5336 | E1000_WRITE_REG(hw, RCTL, rctl); |
95186063 | 5337 | |
682011ff WD |
5338 | fill_rx(hw); |
5339 | } | |
5340 | ||
5341 | /************************************************************************** | |
5342 | POLL - Wait for a frame | |
5343 | ***************************************************************************/ | |
5344 | static int | |
5c5e707a | 5345 | _e1000_poll(struct e1000_hw *hw) |
682011ff | 5346 | { |
682011ff | 5347 | struct e1000_rx_desc *rd; |
06e07f65 | 5348 | unsigned long inval_start, inval_end; |
873e8e01 MV |
5349 | uint32_t len; |
5350 | ||
682011ff WD |
5351 | /* return true if there's an ethernet packet ready to read */ |
5352 | rd = rx_base + rx_last; | |
873e8e01 MV |
5353 | |
5354 | /* Re-load the descriptor from RAM. */ | |
06e07f65 | 5355 | inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); |
873e8e01 MV |
5356 | inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); |
5357 | invalidate_dcache_range(inval_start, inval_end); | |
5358 | ||
a40b2dff | 5359 | if (!(rd->status & E1000_RXD_STAT_DD)) |
682011ff | 5360 | return 0; |
5abf13e4 | 5361 | /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ |
873e8e01 | 5362 | /* Packet received, make sure the data are re-loaded from RAM. */ |
a40b2dff | 5363 | len = le16_to_cpu(rd->length); |
06e07f65 ML |
5364 | invalidate_dcache_range((unsigned long)packet, |
5365 | (unsigned long)packet + | |
5366 | roundup(len, ARCH_DMA_MINALIGN)); | |
5c5e707a | 5367 | return len; |
682011ff WD |
5368 | } |
5369 | ||
5c5e707a | 5370 | static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) |
682011ff | 5371 | { |
873e8e01 | 5372 | void *nv_packet = (void *)txpacket; |
682011ff WD |
5373 | struct e1000_tx_desc *txp; |
5374 | int i = 0; | |
06e07f65 | 5375 | unsigned long flush_start, flush_end; |
682011ff WD |
5376 | |
5377 | txp = tx_base + tx_tail; | |
5378 | tx_tail = (tx_tail + 1) % 8; | |
5379 | ||
8aa858cb | 5380 | txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); |
aa070789 | 5381 | txp->lower.data = cpu_to_le32(hw->txd_cmd | length); |
682011ff | 5382 | txp->upper.data = 0; |
873e8e01 MV |
5383 | |
5384 | /* Dump the packet into RAM so e1000 can pick them. */ | |
06e07f65 ML |
5385 | flush_dcache_range((unsigned long)nv_packet, |
5386 | (unsigned long)nv_packet + | |
5387 | roundup(length, ARCH_DMA_MINALIGN)); | |
873e8e01 | 5388 | /* Dump the descriptor into RAM as well. */ |
06e07f65 | 5389 | flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); |
873e8e01 MV |
5390 | flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN); |
5391 | flush_dcache_range(flush_start, flush_end); | |
5392 | ||
682011ff WD |
5393 | E1000_WRITE_REG(hw, TDT, tx_tail); |
5394 | ||
aa070789 | 5395 | E1000_WRITE_FLUSH(hw); |
873e8e01 MV |
5396 | while (1) { |
5397 | invalidate_dcache_range(flush_start, flush_end); | |
5398 | if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) | |
5399 | break; | |
682011ff WD |
5400 | if (i++ > TOUT_LOOP) { |
5401 | DEBUGOUT("e1000: tx timeout\n"); | |
5402 | return 0; | |
5403 | } | |
5404 | udelay(10); /* give the nic a chance to write to the register */ | |
5405 | } | |
5406 | return 1; | |
5407 | } | |
5408 | ||
682011ff | 5409 | static void |
5c5e707a | 5410 | _e1000_disable(struct e1000_hw *hw) |
682011ff | 5411 | { |
682011ff WD |
5412 | /* Turn off the ethernet interface */ |
5413 | E1000_WRITE_REG(hw, RCTL, 0); | |
5414 | E1000_WRITE_REG(hw, TCTL, 0); | |
5415 | ||
5416 | /* Clear the transmit ring */ | |
5417 | E1000_WRITE_REG(hw, TDH, 0); | |
5418 | E1000_WRITE_REG(hw, TDT, 0); | |
5419 | ||
5420 | /* Clear the receive ring */ | |
5421 | E1000_WRITE_REG(hw, RDH, 0); | |
5422 | E1000_WRITE_REG(hw, RDT, 0); | |
5423 | ||
682011ff | 5424 | mdelay(10); |
5c5e707a | 5425 | } |
682011ff | 5426 | |
5c5e707a SG |
5427 | /*reset function*/ |
5428 | static inline int | |
5429 | e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) | |
5430 | { | |
5431 | e1000_reset_hw(hw); | |
5432 | if (hw->mac_type >= e1000_82544) | |
5433 | E1000_WRITE_REG(hw, WUC, 0); | |
5434 | ||
5435 | return e1000_init_hw(hw, enetaddr); | |
682011ff WD |
5436 | } |
5437 | ||
682011ff | 5438 | static int |
5c5e707a | 5439 | _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) |
682011ff | 5440 | { |
682011ff WD |
5441 | int ret_val = 0; |
5442 | ||
5c5e707a | 5443 | ret_val = e1000_reset(hw, enetaddr); |
682011ff WD |
5444 | if (ret_val < 0) { |
5445 | if ((ret_val == -E1000_ERR_NOLINK) || | |
5446 | (ret_val == -E1000_ERR_TIMEOUT)) { | |
5c5e707a | 5447 | E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); |
682011ff | 5448 | } else { |
5c5e707a | 5449 | E1000_ERR(hw, "Hardware Initialization Failed\n"); |
682011ff | 5450 | } |
5c5e707a | 5451 | return ret_val; |
682011ff WD |
5452 | } |
5453 | e1000_configure_tx(hw); | |
5454 | e1000_setup_rctl(hw); | |
5455 | e1000_configure_rx(hw); | |
5c5e707a | 5456 | return 0; |
682011ff WD |
5457 | } |
5458 | ||
aa070789 RZ |
5459 | /****************************************************************************** |
5460 | * Gets the current PCI bus type of hardware | |
5461 | * | |
5462 | * hw - Struct containing variables accessed by shared code | |
5463 | *****************************************************************************/ | |
5464 | void e1000_get_bus_type(struct e1000_hw *hw) | |
5465 | { | |
5466 | uint32_t status; | |
5467 | ||
5468 | switch (hw->mac_type) { | |
5469 | case e1000_82542_rev2_0: | |
5470 | case e1000_82542_rev2_1: | |
5471 | hw->bus_type = e1000_bus_type_pci; | |
5472 | break; | |
5473 | case e1000_82571: | |
5474 | case e1000_82572: | |
5475 | case e1000_82573: | |
2c2668f9 | 5476 | case e1000_82574: |
aa070789 | 5477 | case e1000_80003es2lan: |
aa070789 | 5478 | case e1000_ich8lan: |
95186063 | 5479 | case e1000_igb: |
aa070789 RZ |
5480 | hw->bus_type = e1000_bus_type_pci_express; |
5481 | break; | |
5482 | default: | |
5483 | status = E1000_READ_REG(hw, STATUS); | |
5484 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? | |
5485 | e1000_bus_type_pcix : e1000_bus_type_pci; | |
5486 | break; | |
5487 | } | |
5488 | } | |
5489 | ||
c6d80a15 | 5490 | #ifndef CONFIG_DM_ETH |
ce5207e1 KM |
5491 | /* A list of all registered e1000 devices */ |
5492 | static LIST_HEAD(e1000_hw_list); | |
c6d80a15 | 5493 | #endif |
ce5207e1 | 5494 | |
81dab9af BM |
5495 | #ifdef CONFIG_DM_ETH |
5496 | static int e1000_init_one(struct e1000_hw *hw, int cardnum, | |
5497 | struct udevice *devno, unsigned char enetaddr[6]) | |
5498 | #else | |
5c5e707a SG |
5499 | static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, |
5500 | unsigned char enetaddr[6]) | |
81dab9af | 5501 | #endif |
5c5e707a SG |
5502 | { |
5503 | u32 val; | |
5504 | ||
5505 | /* Assign the passed-in values */ | |
81dab9af | 5506 | #ifdef CONFIG_DM_ETH |
5c5e707a | 5507 | hw->pdev = devno; |
81dab9af BM |
5508 | #else |
5509 | hw->pdev = devno; | |
5510 | #endif | |
5c5e707a SG |
5511 | hw->cardnum = cardnum; |
5512 | ||
5513 | /* Print a debug message with the IO base address */ | |
81dab9af BM |
5514 | #ifdef CONFIG_DM_ETH |
5515 | dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val); | |
5516 | #else | |
5c5e707a | 5517 | pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); |
81dab9af | 5518 | #endif |
5c5e707a SG |
5519 | E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); |
5520 | ||
5521 | /* Try to enable I/O accesses and bus-mastering */ | |
5522 | val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; | |
81dab9af BM |
5523 | #ifdef CONFIG_DM_ETH |
5524 | dm_pci_write_config32(devno, PCI_COMMAND, val); | |
5525 | #else | |
5c5e707a | 5526 | pci_write_config_dword(devno, PCI_COMMAND, val); |
81dab9af | 5527 | #endif |
5c5e707a SG |
5528 | |
5529 | /* Make sure it worked */ | |
81dab9af BM |
5530 | #ifdef CONFIG_DM_ETH |
5531 | dm_pci_read_config32(devno, PCI_COMMAND, &val); | |
5532 | #else | |
5c5e707a | 5533 | pci_read_config_dword(devno, PCI_COMMAND, &val); |
81dab9af | 5534 | #endif |
5c5e707a SG |
5535 | if (!(val & PCI_COMMAND_MEMORY)) { |
5536 | E1000_ERR(hw, "Can't enable I/O memory\n"); | |
5537 | return -ENOSPC; | |
5538 | } | |
5539 | if (!(val & PCI_COMMAND_MASTER)) { | |
5540 | E1000_ERR(hw, "Can't enable bus-mastering\n"); | |
5541 | return -EPERM; | |
5542 | } | |
5543 | ||
5544 | /* Are these variables needed? */ | |
5545 | hw->fc = e1000_fc_default; | |
5546 | hw->original_fc = e1000_fc_default; | |
5547 | hw->autoneg_failed = 0; | |
5548 | hw->autoneg = 1; | |
5549 | hw->get_link_status = true; | |
5550 | #ifndef CONFIG_E1000_NO_NVM | |
5551 | hw->eeprom_semaphore_present = true; | |
5552 | #endif | |
81dab9af BM |
5553 | #ifdef CONFIG_DM_ETH |
5554 | hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, | |
5555 | PCI_REGION_MEM); | |
5556 | #else | |
5c5e707a SG |
5557 | hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, |
5558 | PCI_REGION_MEM); | |
81dab9af | 5559 | #endif |
5c5e707a SG |
5560 | hw->mac_type = e1000_undefined; |
5561 | ||
5562 | /* MAC and Phy settings */ | |
5563 | if (e1000_sw_init(hw) < 0) { | |
5564 | E1000_ERR(hw, "Software init failed\n"); | |
5565 | return -EIO; | |
5566 | } | |
5567 | if (e1000_check_phy_reset_block(hw)) | |
5568 | E1000_ERR(hw, "PHY Reset is blocked!\n"); | |
5569 | ||
5570 | /* Basic init was OK, reset the hardware and allow SPI access */ | |
5571 | e1000_reset_hw(hw); | |
5572 | ||
5573 | #ifndef CONFIG_E1000_NO_NVM | |
5574 | /* Validate the EEPROM and get chipset information */ | |
5c5e707a SG |
5575 | if (e1000_init_eeprom_params(hw)) { |
5576 | E1000_ERR(hw, "EEPROM is invalid!\n"); | |
5577 | return -EINVAL; | |
5578 | } | |
5579 | if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && | |
5580 | e1000_validate_eeprom_checksum(hw)) | |
5581 | return -ENXIO; | |
5c5e707a SG |
5582 | e1000_read_mac_addr(hw, enetaddr); |
5583 | #endif | |
5584 | e1000_get_bus_type(hw); | |
5585 | ||
5586 | #ifndef CONFIG_E1000_NO_NVM | |
5587 | printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", | |
5588 | enetaddr[0], enetaddr[1], enetaddr[2], | |
5589 | enetaddr[3], enetaddr[4], enetaddr[5]); | |
5590 | #else | |
5591 | memset(enetaddr, 0, 6); | |
5592 | printf("e1000: no NVM\n"); | |
5593 | #endif | |
5594 | ||
5595 | return 0; | |
5596 | } | |
5597 | ||
5598 | /* Put the name of a device in a string */ | |
5599 | static void e1000_name(char *str, int cardnum) | |
5600 | { | |
5601 | sprintf(str, "e1000#%u", cardnum); | |
5602 | } | |
5603 | ||
c6d80a15 | 5604 | #ifndef CONFIG_DM_ETH |
5c5e707a SG |
5605 | /************************************************************************** |
5606 | TRANSMIT - Transmit a frame | |
5607 | ***************************************************************************/ | |
5608 | static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) | |
5609 | { | |
5610 | struct e1000_hw *hw = nic->priv; | |
5611 | ||
5612 | return _e1000_transmit(hw, txpacket, length); | |
5613 | } | |
5614 | ||
5615 | /************************************************************************** | |
5616 | DISABLE - Turn off ethernet interface | |
5617 | ***************************************************************************/ | |
5618 | static void | |
5619 | e1000_disable(struct eth_device *nic) | |
5620 | { | |
5621 | struct e1000_hw *hw = nic->priv; | |
5622 | ||
5623 | _e1000_disable(hw); | |
5624 | } | |
5625 | ||
5626 | /************************************************************************** | |
5627 | INIT - set up ethernet interface(s) | |
5628 | ***************************************************************************/ | |
5629 | static int | |
5630 | e1000_init(struct eth_device *nic, bd_t *bis) | |
5631 | { | |
5632 | struct e1000_hw *hw = nic->priv; | |
5633 | ||
5634 | return _e1000_init(hw, nic->enetaddr); | |
5635 | } | |
5636 | ||
5637 | static int | |
5638 | e1000_poll(struct eth_device *nic) | |
5639 | { | |
5640 | struct e1000_hw *hw = nic->priv; | |
5641 | int len; | |
5642 | ||
5643 | len = _e1000_poll(hw); | |
5644 | if (len) { | |
5645 | net_process_received_packet((uchar *)packet, len); | |
5646 | fill_rx(hw); | |
5647 | } | |
5648 | ||
5649 | return len ? 1 : 0; | |
5650 | } | |
5651 | ||
8d9bde0d HL |
5652 | static int e1000_write_hwaddr(struct eth_device *dev) |
5653 | { | |
5654 | #ifndef CONFIG_E1000_NO_NVM | |
5655 | unsigned char *mac = dev->enetaddr; | |
5656 | unsigned char current_mac[6]; | |
5657 | struct e1000_hw *hw = dev->priv; | |
5658 | uint16_t data[3]; | |
5659 | int ret_val, i; | |
5660 | ||
5661 | DEBUGOUT("%s: mac=%pM\n", __func__, mac); | |
5662 | ||
5663 | memset(current_mac, 0, 6); | |
5664 | ||
5665 | /* Read from EEPROM, not from registers, to make sure | |
5666 | * the address is persistently configured | |
5667 | */ | |
5668 | ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac); | |
5669 | DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac); | |
5670 | ||
5671 | /* Only write to EEPROM if the given address is different or | |
5672 | * reading the current address failed | |
5673 | */ | |
5674 | if (!ret_val && memcmp(current_mac, mac, 6) == 0) | |
5675 | return 0; | |
5676 | ||
5677 | for (i = 0; i < 3; ++i) | |
5678 | data[i] = mac[i * 2 + 1] << 8 | mac[i * 2]; | |
5679 | ||
5680 | ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data); | |
5681 | ||
5682 | if (!ret_val) | |
5683 | ret_val = e1000_update_eeprom_checksum_i210(hw); | |
5684 | ||
5685 | return ret_val; | |
5686 | #else | |
5687 | return 0; | |
5688 | #endif | |
5689 | } | |
5690 | ||
682011ff WD |
5691 | /************************************************************************** |
5692 | PROBE - Look for an adapter, this routine's visible to the outside | |
5693 | You should omit the last argument struct pci_device * for a non-PCI NIC | |
5694 | ***************************************************************************/ | |
5695 | int | |
5696 | e1000_initialize(bd_t * bis) | |
5697 | { | |
d60626f8 | 5698 | unsigned int i; |
682011ff | 5699 | pci_dev_t devno; |
5c5e707a | 5700 | int ret; |
682011ff | 5701 | |
f81ecb5d TT |
5702 | DEBUGFUNC(); |
5703 | ||
d60626f8 KM |
5704 | /* Find and probe all the matching PCI devices */ |
5705 | for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { | |
d60626f8 KM |
5706 | /* |
5707 | * These will never get freed due to errors, this allows us to | |
a187559e | 5708 | * perform SPI EEPROM programming from U-Boot, for example. |
d60626f8 KM |
5709 | */ |
5710 | struct eth_device *nic = malloc(sizeof(*nic)); | |
5711 | struct e1000_hw *hw = malloc(sizeof(*hw)); | |
5712 | if (!nic || !hw) { | |
5713 | printf("e1000#%u: Out of Memory!\n", i); | |
4b29bdb0 | 5714 | free(nic); |
d60626f8 KM |
5715 | free(hw); |
5716 | continue; | |
4b29bdb0 KG |
5717 | } |
5718 | ||
d60626f8 | 5719 | /* Make sure all of the fields are initially zeroed */ |
f7ac99fd | 5720 | memset(nic, 0, sizeof(*nic)); |
4b29bdb0 | 5721 | memset(hw, 0, sizeof(*hw)); |
682011ff | 5722 | nic->priv = hw; |
682011ff | 5723 | |
d60626f8 | 5724 | /* Generate a card name */ |
5c5e707a SG |
5725 | e1000_name(nic->name, i); |
5726 | hw->name = nic->name; | |
682011ff | 5727 | |
5c5e707a SG |
5728 | ret = e1000_init_one(hw, i, devno, nic->enetaddr); |
5729 | if (ret) | |
d60626f8 | 5730 | continue; |
ce5207e1 | 5731 | list_add_tail(&hw->list_node, &e1000_hw_list); |
d60626f8 | 5732 | |
5c5e707a | 5733 | hw->nic = nic; |
682011ff | 5734 | |
d60626f8 | 5735 | /* Set up the function pointers and register the device */ |
682011ff WD |
5736 | nic->init = e1000_init; |
5737 | nic->recv = e1000_poll; | |
5738 | nic->send = e1000_transmit; | |
5739 | nic->halt = e1000_disable; | |
8d9bde0d | 5740 | nic->write_hwaddr = e1000_write_hwaddr; |
682011ff | 5741 | eth_register(nic); |
682011ff | 5742 | } |
d60626f8 KM |
5743 | |
5744 | return i; | |
682011ff | 5745 | } |
ce5207e1 KM |
5746 | |
5747 | struct e1000_hw *e1000_find_card(unsigned int cardnum) | |
5748 | { | |
5749 | struct e1000_hw *hw; | |
5750 | ||
5751 | list_for_each_entry(hw, &e1000_hw_list, list_node) | |
5752 | if (hw->cardnum == cardnum) | |
5753 | return hw; | |
5754 | ||
5755 | return NULL; | |
5756 | } | |
c6d80a15 | 5757 | #endif /* !CONFIG_DM_ETH */ |
ce5207e1 KM |
5758 | |
5759 | #ifdef CONFIG_CMD_E1000 | |
5760 | static int do_e1000(cmd_tbl_t *cmdtp, int flag, | |
5761 | int argc, char * const argv[]) | |
5762 | { | |
5c5e707a | 5763 | unsigned char *mac = NULL; |
c6d80a15 SG |
5764 | #ifdef CONFIG_DM_ETH |
5765 | struct eth_pdata *plat; | |
5766 | struct udevice *dev; | |
5767 | char name[30]; | |
5768 | int ret; | |
eb4e8ceb AB |
5769 | #endif |
5770 | #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI) | |
ce5207e1 | 5771 | struct e1000_hw *hw; |
c6d80a15 SG |
5772 | #endif |
5773 | int cardnum; | |
ce5207e1 KM |
5774 | |
5775 | if (argc < 3) { | |
5776 | cmd_usage(cmdtp); | |
5777 | return 1; | |
5778 | } | |
5779 | ||
5780 | /* Make sure we can find the requested e1000 card */ | |
5c5e707a | 5781 | cardnum = simple_strtoul(argv[1], NULL, 10); |
c6d80a15 SG |
5782 | #ifdef CONFIG_DM_ETH |
5783 | e1000_name(name, cardnum); | |
5784 | ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); | |
5785 | if (!ret) { | |
5786 | plat = dev_get_platdata(dev); | |
5787 | mac = plat->enetaddr; | |
5788 | } | |
5789 | #else | |
5c5e707a SG |
5790 | hw = e1000_find_card(cardnum); |
5791 | if (hw) | |
5792 | mac = hw->nic->enetaddr; | |
c6d80a15 | 5793 | #endif |
5c5e707a | 5794 | if (!mac) { |
ce5207e1 KM |
5795 | printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); |
5796 | return 1; | |
5797 | } | |
5798 | ||
5799 | if (!strcmp(argv[2], "print-mac-address")) { | |
ce5207e1 KM |
5800 | printf("%02x:%02x:%02x:%02x:%02x:%02x\n", |
5801 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); | |
5802 | return 0; | |
5803 | } | |
5804 | ||
5805 | #ifdef CONFIG_E1000_SPI | |
eb4e8ceb AB |
5806 | #ifdef CONFIG_DM_ETH |
5807 | hw = dev_get_priv(dev); | |
5808 | #endif | |
ce5207e1 KM |
5809 | /* Handle the "SPI" subcommand */ |
5810 | if (!strcmp(argv[2], "spi")) | |
5811 | return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); | |
5812 | #endif | |
5813 | ||
5814 | cmd_usage(cmdtp); | |
5815 | return 1; | |
5816 | } | |
5817 | ||
5818 | U_BOOT_CMD( | |
5819 | e1000, 7, 0, do_e1000, | |
5820 | "Intel e1000 controller management", | |
5821 | /* */"<card#> print-mac-address\n" | |
5822 | #ifdef CONFIG_E1000_SPI | |
5823 | "e1000 <card#> spi show [<offset> [<length>]]\n" | |
5824 | "e1000 <card#> spi dump <addr> <offset> <length>\n" | |
5825 | "e1000 <card#> spi program <addr> <offset> <length>\n" | |
5826 | "e1000 <card#> spi checksum [update]\n" | |
5827 | #endif | |
5828 | " - Manage the Intel E1000 PCI device" | |
5829 | ); | |
5830 | #endif /* not CONFIG_CMD_E1000 */ | |
c6d80a15 SG |
5831 | |
5832 | #ifdef CONFIG_DM_ETH | |
5833 | static int e1000_eth_start(struct udevice *dev) | |
5834 | { | |
5835 | struct eth_pdata *plat = dev_get_platdata(dev); | |
5836 | struct e1000_hw *hw = dev_get_priv(dev); | |
5837 | ||
5838 | return _e1000_init(hw, plat->enetaddr); | |
5839 | } | |
5840 | ||
5841 | static void e1000_eth_stop(struct udevice *dev) | |
5842 | { | |
5843 | struct e1000_hw *hw = dev_get_priv(dev); | |
5844 | ||
5845 | _e1000_disable(hw); | |
5846 | } | |
5847 | ||
5848 | static int e1000_eth_send(struct udevice *dev, void *packet, int length) | |
5849 | { | |
5850 | struct e1000_hw *hw = dev_get_priv(dev); | |
5851 | int ret; | |
5852 | ||
5853 | ret = _e1000_transmit(hw, packet, length); | |
5854 | ||
5855 | return ret ? 0 : -ETIMEDOUT; | |
5856 | } | |
5857 | ||
5858 | static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) | |
5859 | { | |
5860 | struct e1000_hw *hw = dev_get_priv(dev); | |
5861 | int len; | |
5862 | ||
5863 | len = _e1000_poll(hw); | |
5864 | if (len) | |
5865 | *packetp = packet; | |
5866 | ||
5867 | return len ? len : -EAGAIN; | |
5868 | } | |
5869 | ||
5870 | static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) | |
5871 | { | |
5872 | struct e1000_hw *hw = dev_get_priv(dev); | |
5873 | ||
5874 | fill_rx(hw); | |
5875 | ||
5876 | return 0; | |
5877 | } | |
5878 | ||
5879 | static int e1000_eth_probe(struct udevice *dev) | |
5880 | { | |
5881 | struct eth_pdata *plat = dev_get_platdata(dev); | |
5882 | struct e1000_hw *hw = dev_get_priv(dev); | |
5883 | int ret; | |
5884 | ||
5885 | hw->name = dev->name; | |
21ccce1b | 5886 | ret = e1000_init_one(hw, trailing_strtol(dev->name), |
81dab9af | 5887 | dev, plat->enetaddr); |
c6d80a15 SG |
5888 | if (ret < 0) { |
5889 | printf(pr_fmt("failed to initialize card: %d\n"), ret); | |
5890 | return ret; | |
5891 | } | |
5892 | ||
5893 | return 0; | |
5894 | } | |
5895 | ||
5896 | static int e1000_eth_bind(struct udevice *dev) | |
5897 | { | |
5898 | char name[20]; | |
5899 | ||
5900 | /* | |
5901 | * A simple way to number the devices. When device tree is used this | |
5902 | * is unnecessary, but when the device is just discovered on the PCI | |
5903 | * bus we need a name. We could instead have the uclass figure out | |
5904 | * which devices are different and number them. | |
5905 | */ | |
5906 | e1000_name(name, num_cards++); | |
5907 | ||
5908 | return device_set_name(dev, name); | |
5909 | } | |
5910 | ||
5911 | static const struct eth_ops e1000_eth_ops = { | |
5912 | .start = e1000_eth_start, | |
5913 | .send = e1000_eth_send, | |
5914 | .recv = e1000_eth_recv, | |
5915 | .stop = e1000_eth_stop, | |
5916 | .free_pkt = e1000_free_pkt, | |
5917 | }; | |
5918 | ||
5919 | static const struct udevice_id e1000_eth_ids[] = { | |
5920 | { .compatible = "intel,e1000" }, | |
5921 | { } | |
5922 | }; | |
5923 | ||
5924 | U_BOOT_DRIVER(eth_e1000) = { | |
5925 | .name = "eth_e1000", | |
5926 | .id = UCLASS_ETH, | |
5927 | .of_match = e1000_eth_ids, | |
5928 | .bind = e1000_eth_bind, | |
5929 | .probe = e1000_eth_probe, | |
5930 | .ops = &e1000_eth_ops, | |
5931 | .priv_auto_alloc_size = sizeof(struct e1000_hw), | |
5932 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
5933 | }; | |
5934 | ||
5935 | U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); | |
5936 | #endif |