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682011ff
WD		 1/*******************************************************************************
2
8bde7f77 3
682011ff 4 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
8bde7f77
WD		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
682011ff 9 any later version.
8bde7f77
WD		 10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
682011ff 14 more details.
8bde7f77 15
682011ff 16 You should have received a copy of the GNU General Public License along with
8bde7f77 17 this program; if not, write to the Free Software Foundation, Inc., 59
53677ef1 18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
8bde7f77 19
682011ff
WD		 20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
8bde7f77 22
682011ff
WD		 23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include <common.h>
37#include <malloc.h>
38#include <net.h>
39#include <asm/io.h>
40#include <pci.h>
41
42#define E1000_ERR(args...) printf("e1000: " args)
43
44#ifdef E1000_DEBUG
45#define E1000_DBG(args...) printf("e1000: " args)
46#define DEBUGOUT(fmt,args...) printf(fmt ,##args)
53677ef1 47#define DEBUGFUNC() printf("%s\n", __FUNCTION__);
682011ff
WD		 48#else
49#define E1000_DBG(args...)
50#define DEBUGFUNC()
51#define DEBUGOUT(fmt,args...)
52#endif
53
54/* Forward declarations of structures used by the shared code */
55struct e1000_hw;
56struct e1000_hw_stats;
57
58typedef enum {
59 FALSE = 0,
60 TRUE = 1
61} boolean_t;
62
63/* Enumerated types specific to the e1000 hardware */
64/* Media Access Controlers */
65typedef enum {
66 e1000_undefined = 0,
67 e1000_82542_rev2_0,
68 e1000_82542_rev2_1,
69 e1000_82543,
70 e1000_82544,
71 e1000_82540,
72 e1000_82545,
73 e1000_82546,
ac3315c2
AS		 74 e1000_82541,
75 e1000_82541_rev_2,
682011ff
WD		 76 e1000_num_macs
77} e1000_mac_type;
78
79/* Media Types */
80typedef enum {
81 e1000_media_type_copper = 0,
82 e1000_media_type_fiber = 1,
83 e1000_num_media_types
84} e1000_media_type;
85
86typedef enum {
87 e1000_10_half = 0,
88 e1000_10_full = 1,
89 e1000_100_half = 2,
90 e1000_100_full = 3
91} e1000_speed_duplex_type;
92
93typedef enum {
94 e1000_lan_a = 0,
95 e1000_lan_b = 1
96} e1000_lan_loc;
97
98/* Flow Control Settings */
99typedef enum {
100 e1000_fc_none = 0,
101 e1000_fc_rx_pause = 1,
102 e1000_fc_tx_pause = 2,
103 e1000_fc_full = 3,
104 e1000_fc_default = 0xFF
105} e1000_fc_type;
106
107/* PCI bus types */
108typedef enum {
109 e1000_bus_type_unknown = 0,
110 e1000_bus_type_pci,
111 e1000_bus_type_pcix
112} e1000_bus_type;
113
114/* PCI bus speeds */
115typedef enum {
116 e1000_bus_speed_unknown = 0,
117 e1000_bus_speed_33,
118 e1000_bus_speed_66,
119 e1000_bus_speed_100,
120 e1000_bus_speed_133,
121 e1000_bus_speed_reserved
122} e1000_bus_speed;
123
124/* PCI bus widths */
125typedef enum {
126 e1000_bus_width_unknown = 0,
127 e1000_bus_width_32,
128 e1000_bus_width_64
129} e1000_bus_width;
130
131/* PHY status info structure and supporting enums */
132typedef enum {
133 e1000_cable_length_50 = 0,
134 e1000_cable_length_50_80,
135 e1000_cable_length_80_110,
136 e1000_cable_length_110_140,
137 e1000_cable_length_140,
138 e1000_cable_length_undefined = 0xFF
139} e1000_cable_length;
140
141typedef enum {
142 e1000_10bt_ext_dist_enable_normal = 0,
143 e1000_10bt_ext_dist_enable_lower,
144 e1000_10bt_ext_dist_enable_undefined = 0xFF
145} e1000_10bt_ext_dist_enable;
146
147typedef enum {
148 e1000_rev_polarity_normal = 0,
149 e1000_rev_polarity_reversed,
150 e1000_rev_polarity_undefined = 0xFF
151} e1000_rev_polarity;
152
153typedef enum {
154 e1000_polarity_reversal_enabled = 0,
155 e1000_polarity_reversal_disabled,
156 e1000_polarity_reversal_undefined = 0xFF
157} e1000_polarity_reversal;
158
159typedef enum {
160 e1000_auto_x_mode_manual_mdi = 0,
161 e1000_auto_x_mode_manual_mdix,
162 e1000_auto_x_mode_auto1,
163 e1000_auto_x_mode_auto2,
164 e1000_auto_x_mode_undefined = 0xFF
165} e1000_auto_x_mode;
166
167typedef enum {
168 e1000_1000t_rx_status_not_ok = 0,
169 e1000_1000t_rx_status_ok,
170 e1000_1000t_rx_status_undefined = 0xFF
171} e1000_1000t_rx_status;
172
ac3315c2
AS		 173typedef enum {
174 e1000_phy_m88 = 0,
175 e1000_phy_igp,
176 e1000_phy_igp_2,
177 e1000_phy_undefined = 0xFF
178} e1000_phy_type;
179
682011ff
WD		 180struct e1000_phy_info {
181 e1000_cable_length cable_length;
182 e1000_10bt_ext_dist_enable extended_10bt_distance;
183 e1000_rev_polarity cable_polarity;
184 e1000_polarity_reversal polarity_correction;
185 e1000_auto_x_mode mdix_mode;
186 e1000_1000t_rx_status local_rx;
187 e1000_1000t_rx_status remote_rx;
188};
189
190struct e1000_phy_stats {
191 uint32_t idle_errors;
192 uint32_t receive_errors;
193};
194
195/* Error Codes */
53677ef1
WD		 196#define E1000_SUCCESS 0
197#define E1000_ERR_EEPROM 1
198#define E1000_ERR_PHY 2
199#define E1000_ERR_CONFIG 3
200#define E1000_ERR_PARAM 4
201#define E1000_ERR_MAC_TYPE 5
202#define E1000_ERR_PHY_TYPE 6
203#define E1000_ERR_NOLINK 7
204#define E1000_ERR_TIMEOUT 8
205#define E1000_ERR_RESET 9
206#define E1000_ERR_MASTER_REQUESTS_PENDING 10
207#define E1000_ERR_HOST_INTERFACE_COMMAND 11
208#define E1000_BLK_PHY_RESET 12
682011ff
WD		 209
210/* PCI Device IDs */
53677ef1 211#define E1000_DEV_ID_82542 0x1000
682011ff
WD		 212#define E1000_DEV_ID_82543GC_FIBER 0x1001
213#define E1000_DEV_ID_82543GC_COPPER 0x1004
214#define E1000_DEV_ID_82544EI_COPPER 0x1008
215#define E1000_DEV_ID_82544EI_FIBER 0x1009
216#define E1000_DEV_ID_82544GC_COPPER 0x100C
217#define E1000_DEV_ID_82544GC_LOM 0x100D
53677ef1 218#define E1000_DEV_ID_82540EM 0x100E
682011ff
WD		 219#define E1000_DEV_ID_82540EM_LOM 0x1015
220#define E1000_DEV_ID_82545EM_COPPER 0x100F
221#define E1000_DEV_ID_82545EM_FIBER 0x1011
222#define E1000_DEV_ID_82546EB_COPPER 0x1010
223#define E1000_DEV_ID_82546EB_FIBER 0x1012
53677ef1 224#define E1000_DEV_ID_82541ER 0x1078
aa3b8bf9
WG		 225#define E1000_DEV_ID_82541GI_LF 0x107C
226#define NUM_DEV_IDS 15
682011ff
WD		 227
228#define NODE_ADDRESS_SIZE 6
229#define ETH_LENGTH_OF_ADDRESS 6
230
231/* MAC decode size is 128K - This is the size of BAR0 */
232#define MAC_DECODE_SIZE (128 * 1024)
233
234#define E1000_82542_2_0_REV_ID 2
235#define E1000_82542_2_1_REV_ID 3
236
237#define SPEED_10 10
238#define SPEED_100 100
239#define SPEED_1000 1000
240#define HALF_DUPLEX 1
241#define FULL_DUPLEX 2
242
243/* The sizes (in bytes) of a ethernet packet */
53677ef1 244#define ENET_HEADER_SIZE 14
682011ff
WD		 245#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
246#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
53677ef1 247#define ETHERNET_FCS_SIZE 4
682011ff
WD		 248#define MAXIMUM_ETHERNET_PACKET_SIZE \
249 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
250#define MINIMUM_ETHERNET_PACKET_SIZE \
251 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
53677ef1
WD		 252#define CRC_LENGTH ETHERNET_FCS_SIZE
253#define MAX_JUMBO_FRAME_SIZE 0x3F00
682011ff
WD		 254
255/* 802.1q VLAN Packet Sizes */
53677ef1 256#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
682011ff
WD		 257
258/* Ethertype field values */
259#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
53677ef1
WD		 260#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
261#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
682011ff
WD		 262
263/* Packet Header defines */
264#define IP_PROTOCOL_TCP 6
265#define IP_PROTOCOL_UDP 0x11
266
267/* This defines the bits that are set in the Interrupt Mask
268 * Set/Read Register. Each bit is documented below:
269 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
8bde7f77 270 * o RXSEQ = Receive Sequence Error
682011ff
WD		 271 */
272#define POLL_IMS_ENABLE_MASK ( \
53677ef1 273 E1000_IMS_RXDMT0 | \
682011ff
WD		 274 E1000_IMS_RXSEQ)
275
276/* This defines the bits that are set in the Interrupt Mask
277 * Set/Read Register. Each bit is documented below:
278 * o RXT0 = Receiver Timer Interrupt (ring 0)
279 * o TXDW = Transmit Descriptor Written Back
280 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
281 * o RXSEQ = Receive Sequence Error
282 * o LSC = Link Status Change
283 */
284#define IMS_ENABLE_MASK ( \
53677ef1
WD		 285 E1000_IMS_RXT0 | \
286 E1000_IMS_TXDW | \
287 E1000_IMS_RXDMT0 | \
288 E1000_IMS_RXSEQ | \
682011ff
WD		 289 E1000_IMS_LSC)
290
291/* The number of high/low register pairs in the RAR. The RAR (Receive Address
292 * Registers) holds the directed and multicast addresses that we monitor. We
293 * reserve one of these spots for our directed address, allowing us room for
8bde7f77 294 * E1000_RAR_ENTRIES - 1 multicast addresses.
682011ff
WD		 295 */
296#define E1000_RAR_ENTRIES 16
297
298#define MIN_NUMBER_OF_DESCRIPTORS 8
299#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
300
301/* Receive Descriptor */
302struct e1000_rx_desc {
303 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
304 uint16_t length; /* Length of data DMAed into data buffer */
305 uint16_t csum; /* Packet checksum */
306 uint8_t status; /* Descriptor status */
307 uint8_t errors; /* Descriptor Errors */
308 uint16_t special;
309};
310
311/* Receive Decriptor bit definitions */
53677ef1
WD		 312#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
313#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
314#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
315#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
316#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
317#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
318#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
319#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
320#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
321#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
322#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
323#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
324#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
325#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
682011ff 326#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
53677ef1 327#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
682011ff 328#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
53677ef1 329#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
682011ff
WD		 330#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
331
332/* mask to determine if packets should be dropped due to frame errors */
333#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
53677ef1
WD		 334 E1000_RXD_ERR_CE | \
335 E1000_RXD_ERR_SE | \
336 E1000_RXD_ERR_SEQ | \
337 E1000_RXD_ERR_CXE | \
682011ff
WD		 338 E1000_RXD_ERR_RXE)
339
340/* Transmit Descriptor */
341struct e1000_tx_desc {
342 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
343 union {
344 uint32_t data;
345 struct {
346 uint16_t length; /* Data buffer length */
347 uint8_t cso; /* Checksum offset */
348 uint8_t cmd; /* Descriptor control */
349 } flags;
350 } lower;
351 union {
352 uint32_t data;
353 struct {
354 uint8_t status; /* Descriptor status */
355 uint8_t css; /* Checksum start */
356 uint16_t special;
357 } fields;
358 } upper;
359};
360
361/* Transmit Descriptor bit definitions */
362#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
363#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
364#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
365#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
366#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
367#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
368#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
369#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
370#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
371#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
372#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
373#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
374#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
375#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
376#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
377#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
378#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
379#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
380#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
381#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
382
383/* Offload Context Descriptor */
384struct e1000_context_desc {
385 union {
386 uint32_t ip_config;
387 struct {
388 uint8_t ipcss; /* IP checksum start */
389 uint8_t ipcso; /* IP checksum offset */
390 uint16_t ipcse; /* IP checksum end */
391 } ip_fields;
392 } lower_setup;
393 union {
394 uint32_t tcp_config;
395 struct {
396 uint8_t tucss; /* TCP checksum start */
397 uint8_t tucso; /* TCP checksum offset */
398 uint16_t tucse; /* TCP checksum end */
399 } tcp_fields;
400 } upper_setup;
401 uint32_t cmd_and_length; /* */
402 union {
403 uint32_t data;
404 struct {
405 uint8_t status; /* Descriptor status */
406 uint8_t hdr_len; /* Header length */
407 uint16_t mss; /* Maximum segment size */
408 } fields;
409 } tcp_seg_setup;
410};
411
412/* Offload data descriptor */
413struct e1000_data_desc {
414 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
415 union {
416 uint32_t data;
417 struct {
418 uint16_t length; /* Data buffer length */
419 uint8_t typ_len_ext; /* */
420 uint8_t cmd; /* */
421 } flags;
422 } lower;
423 union {
424 uint32_t data;
425 struct {
426 uint8_t status; /* Descriptor status */
427 uint8_t popts; /* Packet Options */
428 uint16_t special; /* */
429 } fields;
430 } upper;
431};
432
433/* Filters */
53677ef1
WD		 434#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
435#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
682011ff
WD		 436#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
437
438/* Receive Address Register */
439struct e1000_rar {
440 volatile uint32_t low; /* receive address low */
441 volatile uint32_t high; /* receive address high */
442};
443
444/* The number of entries in the Multicast Table Array (MTA). */
445#define E1000_NUM_MTA_REGISTERS 128
446
447/* IPv4 Address Table Entry */
448struct e1000_ipv4_at_entry {
449 volatile uint32_t ipv4_addr; /* IP Address (RW) */
450 volatile uint32_t reserved;
451};
452
453/* Four wakeup IP addresses are supported */
454#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
53677ef1
WD		 455#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
456#define E1000_IP6AT_SIZE 1
682011ff
WD		 457
458/* IPv6 Address Table Entry */
459struct e1000_ipv6_at_entry {
460 volatile uint8_t ipv6_addr[16];
461};
462
463/* Flexible Filter Length Table Entry */
464struct e1000_fflt_entry {
465 volatile uint32_t length; /* Flexible Filter Length (RW) */
466 volatile uint32_t reserved;
467};
468
469/* Flexible Filter Mask Table Entry */
470struct e1000_ffmt_entry {
471 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
472 volatile uint32_t reserved;
473};
474
475/* Flexible Filter Value Table Entry */
476struct e1000_ffvt_entry {
477 volatile uint32_t value; /* Flexible Filter Value (RW) */
478 volatile uint32_t reserved;
479};
480
481/* Four Flexible Filters are supported */
482#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
483
484/* Each Flexible Filter is at most 128 (0x80) bytes in length */
53677ef1 485#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
682011ff
WD		 486
487#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
488#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
489#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
490
491/* Register Set. (82543, 82544)
492 *
493 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
8bde7f77 494 * These registers are physically located on the NIC, but are mapped into the
682011ff
WD		 495 * host memory address space.
496 *
497 * RW - register is both readable and writable
498 * RO - register is read only
499 * WO - register is write only
500 * R/clr - register is read only and is cleared when read
501 * A - register array
502 */
503#define E1000_CTRL 0x00000 /* Device Control - RW */
504#define E1000_STATUS 0x00008 /* Device Status - RO */
505#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
506#define E1000_EERD 0x00014 /* EEPROM Read - RW */
507#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
508#define E1000_MDIC 0x00020 /* MDI Control - RW */
509#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
510#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
511#define E1000_FCT 0x00030 /* Flow Control Type - RW */
512#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
513#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
514#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
515#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
516#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
517#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
518#define E1000_RCTL 0x00100 /* RX Control - RW */
519#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
520#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
521#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
522#define E1000_TCTL 0x00400 /* TX Control - RW */
523#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
524#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
525#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
526#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
527#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
528#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
529#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
530#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
531#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
532#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
533#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
534#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
535#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
536#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
537#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
538#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
539#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
540#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
541#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
542#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
543#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
544#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
545#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
546#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
547#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
548#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
549#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
550#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
551#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
552#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
553#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
554#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
555#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
556#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
557#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
558#define E1000_COLC 0x04028 /* Collision Count - R/clr */
559#define E1000_DC 0x04030 /* Defer Count - R/clr */
560#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
561#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
562#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
563#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
564#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
565#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
566#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
567#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
568#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
569#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
570#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
571#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
572#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
573#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
574#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
575#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
576#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
577#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
578#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
579#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
580#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
581#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
582#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
583#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
584#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
585#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
586#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
587#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
588#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
589#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
590#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
591#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
592#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
593#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
594#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
595#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
596#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
597#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
598#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
599#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
600#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
601#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
602#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
603#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
604#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
605#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
606#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
607#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
608#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
609#define E1000_RA 0x05400 /* Receive Address - RW Array */
610#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
611#define E1000_WUC 0x05800 /* Wakeup Control - RW */
612#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
613#define E1000_WUS 0x05810 /* Wakeup Status - RO */
614#define E1000_MANC 0x05820 /* Management Control - RW */
615#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
616#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
617#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
618#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
619#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
620#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
621#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
622#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
623
624/* Register Set (82542)
625 *
626 * Some of the 82542 registers are located at different offsets than they are
627 * in more current versions of the 8254x. Despite the difference in location,
628 * the registers function in the same manner.
629 */
630#define E1000_82542_CTRL E1000_CTRL
631#define E1000_82542_STATUS E1000_STATUS
632#define E1000_82542_EECD E1000_EECD
633#define E1000_82542_EERD E1000_EERD
634#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
635#define E1000_82542_MDIC E1000_MDIC
636#define E1000_82542_FCAL E1000_FCAL
637#define E1000_82542_FCAH E1000_FCAH
638#define E1000_82542_FCT E1000_FCT
639#define E1000_82542_VET E1000_VET
53677ef1 640#define E1000_82542_RA 0x00040
682011ff
WD		 641#define E1000_82542_ICR E1000_ICR
642#define E1000_82542_ITR E1000_ITR
643#define E1000_82542_ICS E1000_ICS
644#define E1000_82542_IMS E1000_IMS
645#define E1000_82542_IMC E1000_IMC
646#define E1000_82542_RCTL E1000_RCTL
647#define E1000_82542_RDTR 0x00108
648#define E1000_82542_RDBAL 0x00110
649#define E1000_82542_RDBAH 0x00114
650#define E1000_82542_RDLEN 0x00118
651#define E1000_82542_RDH 0x00120
652#define E1000_82542_RDT 0x00128
653#define E1000_82542_FCRTH 0x00160
654#define E1000_82542_FCRTL 0x00168
655#define E1000_82542_FCTTV E1000_FCTTV
656#define E1000_82542_TXCW E1000_TXCW
657#define E1000_82542_RXCW E1000_RXCW
658#define E1000_82542_MTA 0x00200
659#define E1000_82542_TCTL E1000_TCTL
660#define E1000_82542_TIPG E1000_TIPG
661#define E1000_82542_TDBAL 0x00420
662#define E1000_82542_TDBAH 0x00424
663#define E1000_82542_TDLEN 0x00428
664#define E1000_82542_TDH 0x00430
665#define E1000_82542_TDT 0x00438
666#define E1000_82542_TIDV 0x00440
667#define E1000_82542_TBT E1000_TBT
668#define E1000_82542_AIT E1000_AIT
669#define E1000_82542_VFTA 0x00600
670#define E1000_82542_LEDCTL E1000_LEDCTL
671#define E1000_82542_PBA E1000_PBA
672#define E1000_82542_RXDCTL E1000_RXDCTL
673#define E1000_82542_RADV E1000_RADV
674#define E1000_82542_RSRPD E1000_RSRPD
675#define E1000_82542_TXDMAC E1000_TXDMAC
676#define E1000_82542_TXDCTL E1000_TXDCTL
677#define E1000_82542_TADV E1000_TADV
678#define E1000_82542_TSPMT E1000_TSPMT
679#define E1000_82542_CRCERRS E1000_CRCERRS
680#define E1000_82542_ALGNERRC E1000_ALGNERRC
681#define E1000_82542_SYMERRS E1000_SYMERRS
682#define E1000_82542_RXERRC E1000_RXERRC
683#define E1000_82542_MPC E1000_MPC
684#define E1000_82542_SCC E1000_SCC
685#define E1000_82542_ECOL E1000_ECOL
686#define E1000_82542_MCC E1000_MCC
687#define E1000_82542_LATECOL E1000_LATECOL
688#define E1000_82542_COLC E1000_COLC
53677ef1 689#define E1000_82542_DC E1000_DC
682011ff
WD		 690#define E1000_82542_TNCRS E1000_TNCRS
691#define E1000_82542_SEC E1000_SEC
692#define E1000_82542_CEXTERR E1000_CEXTERR
693#define E1000_82542_RLEC E1000_RLEC
694#define E1000_82542_XONRXC E1000_XONRXC
695#define E1000_82542_XONTXC E1000_XONTXC
696#define E1000_82542_XOFFRXC E1000_XOFFRXC
697#define E1000_82542_XOFFTXC E1000_XOFFTXC
698#define E1000_82542_FCRUC E1000_FCRUC
699#define E1000_82542_PRC64 E1000_PRC64
700#define E1000_82542_PRC127 E1000_PRC127
701#define E1000_82542_PRC255 E1000_PRC255
702#define E1000_82542_PRC511 E1000_PRC511
703#define E1000_82542_PRC1023 E1000_PRC1023
704#define E1000_82542_PRC1522 E1000_PRC1522
705#define E1000_82542_GPRC E1000_GPRC
706#define E1000_82542_BPRC E1000_BPRC
707#define E1000_82542_MPRC E1000_MPRC
708#define E1000_82542_GPTC E1000_GPTC
709#define E1000_82542_GORCL E1000_GORCL
710#define E1000_82542_GORCH E1000_GORCH
711#define E1000_82542_GOTCL E1000_GOTCL
712#define E1000_82542_GOTCH E1000_GOTCH
713#define E1000_82542_RNBC E1000_RNBC
714#define E1000_82542_RUC E1000_RUC
715#define E1000_82542_RFC E1000_RFC
716#define E1000_82542_ROC E1000_ROC
717#define E1000_82542_RJC E1000_RJC
718#define E1000_82542_MGTPRC E1000_MGTPRC
719#define E1000_82542_MGTPDC E1000_MGTPDC
720#define E1000_82542_MGTPTC E1000_MGTPTC
721#define E1000_82542_TORL E1000_TORL
722#define E1000_82542_TORH E1000_TORH
723#define E1000_82542_TOTL E1000_TOTL
724#define E1000_82542_TOTH E1000_TOTH
725#define E1000_82542_TPR E1000_TPR
726#define E1000_82542_TPT E1000_TPT
727#define E1000_82542_PTC64 E1000_PTC64
728#define E1000_82542_PTC127 E1000_PTC127
729#define E1000_82542_PTC255 E1000_PTC255
730#define E1000_82542_PTC511 E1000_PTC511
731#define E1000_82542_PTC1023 E1000_PTC1023
732#define E1000_82542_PTC1522 E1000_PTC1522
733#define E1000_82542_MPTC E1000_MPTC
734#define E1000_82542_BPTC E1000_BPTC
735#define E1000_82542_TSCTC E1000_TSCTC
736#define E1000_82542_TSCTFC E1000_TSCTFC
737#define E1000_82542_RXCSUM E1000_RXCSUM
738#define E1000_82542_WUC E1000_WUC
739#define E1000_82542_WUFC E1000_WUFC
740#define E1000_82542_WUS E1000_WUS
741#define E1000_82542_MANC E1000_MANC
742#define E1000_82542_IPAV E1000_IPAV
743#define E1000_82542_IP4AT E1000_IP4AT
744#define E1000_82542_IP6AT E1000_IP6AT
745#define E1000_82542_WUPL E1000_WUPL
746#define E1000_82542_WUPM E1000_WUPM
747#define E1000_82542_FFLT E1000_FFLT
748#define E1000_82542_FFMT E1000_FFMT
749#define E1000_82542_FFVT E1000_FFVT
750
751/* Statistics counters collected by the MAC */
752struct e1000_hw_stats {
753 uint64_t crcerrs;
754 uint64_t algnerrc;
755 uint64_t symerrs;
756 uint64_t rxerrc;
757 uint64_t mpc;
758 uint64_t scc;
759 uint64_t ecol;
760 uint64_t mcc;
761 uint64_t latecol;
762 uint64_t colc;
763 uint64_t dc;
764 uint64_t tncrs;
765 uint64_t sec;
766 uint64_t cexterr;
767 uint64_t rlec;
768 uint64_t xonrxc;
769 uint64_t xontxc;
770 uint64_t xoffrxc;
771 uint64_t xofftxc;
772 uint64_t fcruc;
773 uint64_t prc64;
774 uint64_t prc127;
775 uint64_t prc255;
776 uint64_t prc511;
777 uint64_t prc1023;
778 uint64_t prc1522;
779 uint64_t gprc;
780 uint64_t bprc;
781 uint64_t mprc;
782 uint64_t gptc;
783 uint64_t gorcl;
784 uint64_t gorch;
785 uint64_t gotcl;
786 uint64_t gotch;
787 uint64_t rnbc;
788 uint64_t ruc;
789 uint64_t rfc;
790 uint64_t roc;
791 uint64_t rjc;
792 uint64_t mgprc;
793 uint64_t mgpdc;
794 uint64_t mgptc;
795 uint64_t torl;
796 uint64_t torh;
797 uint64_t totl;
798 uint64_t toth;
799 uint64_t tpr;
800 uint64_t tpt;
801 uint64_t ptc64;
802 uint64_t ptc127;
803 uint64_t ptc255;
804 uint64_t ptc511;
805 uint64_t ptc1023;
806 uint64_t ptc1522;
807 uint64_t mptc;
808 uint64_t bptc;
809 uint64_t tsctc;
810 uint64_t tsctfc;
811};
812
813/* Structure containing variables used by the shared code (e1000_hw.c) */
814struct e1000_hw {
815 pci_dev_t pdev;
816 uint8_t *hw_addr;
817 e1000_mac_type mac_type;
ac3315c2
AS		 818 e1000_phy_type phy_type;
819 uint32_t phy_init_script;
682011ff
WD		 820 e1000_media_type media_type;
821 e1000_lan_loc lan_loc;
822 e1000_fc_type fc;
823#if 0
824 e1000_bus_speed bus_speed;
825 e1000_bus_width bus_width;
826 e1000_bus_type bus_type;
827 uint32_t io_base;
828#endif
829 uint32_t phy_id;
830 uint32_t phy_addr;
831 uint32_t original_fc;
832 uint32_t txcw;
833 uint32_t autoneg_failed;
834#if 0
835 uint32_t max_frame_size;
836 uint32_t min_frame_size;
837 uint32_t mc_filter_type;
838 uint32_t num_mc_addrs;
839 uint32_t collision_delta;
840 uint32_t tx_packet_delta;
841 uint32_t ledctl_default;
842 uint32_t ledctl_mode1;
843 uint32_t ledctl_mode2;
844#endif
845 uint16_t autoneg_advertised;
846 uint16_t pci_cmd_word;
847 uint16_t fc_high_water;
848 uint16_t fc_low_water;
849 uint16_t fc_pause_time;
850#if 0
851 uint16_t current_ifs_val;
852 uint16_t ifs_min_val;
853 uint16_t ifs_max_val;
854 uint16_t ifs_step_size;
855 uint16_t ifs_ratio;
856#endif
857 uint16_t device_id;
858 uint16_t vendor_id;
859 uint16_t subsystem_id;
860 uint16_t subsystem_vendor_id;
861 uint8_t revision_id;
862#if 0
863 uint8_t autoneg;
864 uint8_t mdix;
865 uint8_t forced_speed_duplex;
866 uint8_t wait_autoneg_complete;
867 uint8_t dma_fairness;
868#endif
869#if 0
870 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
871 boolean_t disable_polarity_correction;
872#endif
873 boolean_t get_link_status;
874 boolean_t tbi_compatibility_en;
875 boolean_t tbi_compatibility_on;
876 boolean_t fc_send_xon;
877 boolean_t report_tx_early;
878#if 0
879 boolean_t adaptive_ifs;
880 boolean_t ifs_params_forced;
881 boolean_t in_ifs_mode;
882#endif
883};
884
885#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
886#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
887
888/* Register Bit Masks */
889/* Device Control */
53677ef1
WD		 890#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
891#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
682011ff
WD		 892#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
893#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
53677ef1
WD		 894#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
895#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
682011ff 896#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
53677ef1 897#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
682011ff
WD		 898#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
899#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
900#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
901#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
902#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
903#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
904#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
905#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
906#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
907#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
908#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
909#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
910#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
911#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
912#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
913#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
53677ef1 914#define E1000_CTRL_RST 0x04000000 /* Global reset */
682011ff
WD		 915#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
916#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
53677ef1
WD		 917#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
918#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
682011ff
WD		 919#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
920
921/* Device Status */
53677ef1
WD		 922#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
923#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
924#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
925#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
926#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
927#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
928#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
682011ff 929#define E1000_STATUS_SPEED_MASK 0x000000C0
53677ef1
WD		 930#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
931#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
682011ff 932#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
53677ef1
WD		 933#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
934#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
935#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
936#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
937#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
682011ff
WD		 938#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
939
940/* Constants used to intrepret the masked PCI-X bus speed. */
941#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
942#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
943#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
944
945/* EEPROM/Flash Control */
53677ef1
WD		 946#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
947#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
948#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
949#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
682011ff
WD		 950#define E1000_EECD_FWE_MASK 0x00000030
951#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
952#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
953#define E1000_EECD_FWE_SHIFT 4
954#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
53677ef1
WD		 955#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
956#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
682011ff
WD		 957#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
958
959/* EEPROM Read */
960#define E1000_EERD_START 0x00000001 /* Start Read */
961#define E1000_EERD_DONE 0x00000010 /* Read Done */
962#define E1000_EERD_ADDR_SHIFT 8
963#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
964#define E1000_EERD_DATA_SHIFT 16
965#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
966
967/* Extended Device Control */
53677ef1
WD		 968#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
969#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
682011ff 970#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
53677ef1
WD		 971#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
972#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
682011ff
WD		 973#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
974#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
53677ef1 975#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
682011ff 976#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
53677ef1 977#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */
682011ff 978#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
53677ef1 979#define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */
682011ff
WD		 980#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
981#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
982#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
53677ef1 983#define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */
682011ff 984#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
53677ef1
WD		 985#define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */
986#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
987#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
988#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
682011ff
WD		 989#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
990#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
991#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
992#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
993#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
994#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
995#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
996#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
997#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
998
999/* MDI Control */
1000#define E1000_MDIC_DATA_MASK 0x0000FFFF
1001#define E1000_MDIC_REG_MASK 0x001F0000
1002#define E1000_MDIC_REG_SHIFT 16
1003#define E1000_MDIC_PHY_MASK 0x03E00000
1004#define E1000_MDIC_PHY_SHIFT 21
1005#define E1000_MDIC_OP_WRITE 0x04000000
1006#define E1000_MDIC_OP_READ 0x08000000
1007#define E1000_MDIC_READY 0x10000000
1008#define E1000_MDIC_INT_EN 0x20000000
1009#define E1000_MDIC_ERROR 0x40000000
1010
1011/* LED Control */
1012#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1013#define E1000_LEDCTL_LED0_MODE_SHIFT 0
53677ef1 1014#define E1000_LEDCTL_LED0_IVRT 0x00000040
682011ff
WD		 1015#define E1000_LEDCTL_LED0_BLINK 0x00000080
1016#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1017#define E1000_LEDCTL_LED1_MODE_SHIFT 8
53677ef1 1018#define E1000_LEDCTL_LED1_IVRT 0x00004000
682011ff
WD		 1019#define E1000_LEDCTL_LED1_BLINK 0x00008000
1020#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1021#define E1000_LEDCTL_LED2_MODE_SHIFT 16
53677ef1 1022#define E1000_LEDCTL_LED2_IVRT 0x00400000
682011ff
WD		 1023#define E1000_LEDCTL_LED2_BLINK 0x00800000
1024#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1025#define E1000_LEDCTL_LED3_MODE_SHIFT 24
53677ef1 1026#define E1000_LEDCTL_LED3_IVRT 0x40000000
682011ff
WD		 1027#define E1000_LEDCTL_LED3_BLINK 0x80000000
1028
53677ef1 1029#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
682011ff 1030#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
53677ef1
WD		 1031#define E1000_LEDCTL_MODE_LINK_UP 0x2
1032#define E1000_LEDCTL_MODE_ACTIVITY 0x3
682011ff 1033#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
53677ef1
WD		 1034#define E1000_LEDCTL_MODE_LINK_10 0x5
1035#define E1000_LEDCTL_MODE_LINK_100 0x6
1036#define E1000_LEDCTL_MODE_LINK_1000 0x7
1037#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1038#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1039#define E1000_LEDCTL_MODE_COLLISION 0xA
1040#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1041#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1042#define E1000_LEDCTL_MODE_PAUSED 0xD
1043#define E1000_LEDCTL_MODE_LED_ON 0xE
1044#define E1000_LEDCTL_MODE_LED_OFF 0xF
682011ff
WD		 1045
1046/* Receive Address */
1047#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1048
1049/* Interrupt Cause Read */
53677ef1
WD		 1050#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1051#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1052#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
682011ff
WD		 1053#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1054#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
53677ef1
WD		 1055#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1056#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1057#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
682011ff
WD		 1058#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1059#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1060#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1061#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1062#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1063#define E1000_ICR_TXD_LOW 0x00008000
53677ef1 1064#define E1000_ICR_SRPD 0x00010000
682011ff
WD		 1065
1066/* Interrupt Cause Set */
53677ef1
WD		 1067#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1068#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1069#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
682011ff
WD		 1070#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1071#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
53677ef1
WD		 1072#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1073#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1074#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
682011ff
WD		 1075#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1076#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1077#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1078#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1079#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1080#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
53677ef1 1081#define E1000_ICS_SRPD E1000_ICR_SRPD
682011ff
WD		 1082
1083/* Interrupt Mask Set */
53677ef1
WD		 1084#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1085#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1086#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
682011ff
WD		 1087#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1088#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
53677ef1
WD		 1089#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1090#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1091#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
682011ff
WD		 1092#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1093#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1094#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1095#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1096#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1097#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
53677ef1 1098#define E1000_IMS_SRPD E1000_ICR_SRPD
682011ff
WD		 1099
1100/* Interrupt Mask Clear */
53677ef1
WD		 1101#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1102#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1103#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
682011ff
WD		 1104#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1105#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
53677ef1
WD		 1106#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1107#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1108#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
682011ff
WD		 1109#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1110#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1111#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1112#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1113#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1114#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
53677ef1 1115#define E1000_IMC_SRPD E1000_ICR_SRPD
682011ff
WD		 1116
1117/* Receive Control */
53677ef1
WD		 1118#define E1000_RCTL_RST 0x00000001 /* Software reset */
1119#define E1000_RCTL_EN 0x00000002 /* enable */
1120#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1121#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1122#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1123#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1124#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1125#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1126#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1127#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1128#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1129#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1130#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1131#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1132#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1133#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1134#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1135#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1136#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1137#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
682011ff 1138/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
53677ef1
WD		 1139#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1140#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1141#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1142#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
682011ff 1143/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
53677ef1
WD		 1144#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1145#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1146#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1147#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1148#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1149#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1150#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1151#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1152#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
682011ff
WD		 1153
1154/* Receive Descriptor */
1155#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
53677ef1 1156#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
682011ff 1157#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
53677ef1
WD		 1158#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1159#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
682011ff
WD		 1160
1161/* Flow Control */
1162#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1163#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1164#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1165#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1166
1167/* Receive Descriptor Control */
1168#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1169#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1170#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1171#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1172
1173/* Transmit Descriptor Control */
1174#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1175#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1176#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1177#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1178#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1179#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1180
1181/* Transmit Configuration Word */
53677ef1
WD		 1182#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1183#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
682011ff
WD		 1184#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1185#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1186#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
53677ef1
WD		 1187#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1188#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1189#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1190#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1191#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
682011ff
WD		 1192
1193/* Receive Configuration Word */
53677ef1
WD		 1194#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1195#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1196#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1197#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1198#define E1000_RXCW_C 0x20000000 /* Receive config */
682011ff 1199#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
53677ef1 1200#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
682011ff
WD		 1201
1202/* Transmit Control */
53677ef1
WD		 1203#define E1000_TCTL_RST 0x00000001 /* software reset */
1204#define E1000_TCTL_EN 0x00000002 /* enable tx */
1205#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1206#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1207#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
682011ff
WD		 1208#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1209#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
53677ef1 1210#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
682011ff
WD		 1211#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1212#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1213
1214/* Receive Checksum Control */
1215#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1216#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1217#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1218#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1219
1220/* Definitions for power management and wakeup registers */
1221/* Wake Up Control */
53677ef1 1222#define E1000_WUC_APME 0x00000001 /* APM Enable */
682011ff
WD		 1223#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1224#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1225#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1226
1227/* Wake Up Filter Control */
1228#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
53677ef1
WD		 1229#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1230#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1231#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1232#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1233#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
682011ff
WD		 1234#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1235#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1236#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1237#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1238#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1239#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1240#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1241#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1242#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1243
1244/* Wake Up Status */
1245#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1246#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1247#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1248#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1249#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1250#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1251#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1252#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1253#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1254#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1255#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1256#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1257#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1258
1259/* Management Control */
53677ef1
WD		 1260#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1261#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1262#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1263#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1264#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1265#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1266#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1267#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1268#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1269#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
682011ff 1270 * Filtering */
53677ef1
WD		 1271#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1272#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
682011ff 1273#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
53677ef1
WD		 1274#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1275#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1276#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1277#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
682011ff 1278#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
53677ef1 1279#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
682011ff
WD		 1280
1281#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1282#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1283
1284/* Wake Up Packet Length */
1285#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1286
53677ef1 1287#define E1000_MDALIGN 4096
682011ff
WD		 1288
1289/* EEPROM Commands */
1290#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
1291#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
1292#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
1293#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
1294#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
1295
1296/* EEPROM Word Offsets */
53677ef1
WD		 1297#define EEPROM_COMPAT 0x0003
1298#define EEPROM_ID_LED_SETTINGS 0x0004
682011ff
WD		 1299#define EEPROM_INIT_CONTROL1_REG 0x000A
1300#define EEPROM_INIT_CONTROL2_REG 0x000F
53677ef1
WD		 1301#define EEPROM_FLASH_VERSION 0x0032
1302#define EEPROM_CHECKSUM_REG 0x003F
682011ff
WD		 1303
1304/* Word definitions for ID LED Settings */
1305#define ID_LED_RESERVED_0000 0x0000
1306#define ID_LED_RESERVED_FFFF 0xFFFF
53677ef1 1307#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
8bde7f77
WD		 1308 (ID_LED_OFF1_OFF2 << 8) | \
1309 (ID_LED_DEF1_DEF2 << 4) | \
1310 (ID_LED_DEF1_DEF2))
682011ff
WD		 1311#define ID_LED_DEF1_DEF2 0x1
1312#define ID_LED_DEF1_ON2 0x2
1313#define ID_LED_DEF1_OFF2 0x3
1314#define ID_LED_ON1_DEF2 0x4
53677ef1 1315#define ID_LED_ON1_ON2 0x5
682011ff
WD		 1316#define ID_LED_ON1_OFF2 0x6
1317#define ID_LED_OFF1_DEF2 0x7
1318#define ID_LED_OFF1_ON2 0x8
1319#define ID_LED_OFF1_OFF2 0x9
1320
1321/* Mask bits for fields in Word 0x03 of the EEPROM */
1322#define EEPROM_COMPAT_SERVER 0x0400
1323#define EEPROM_COMPAT_CLIENT 0x0200
1324
1325/* Mask bits for fields in Word 0x0a of the EEPROM */
1326#define EEPROM_WORD0A_ILOS 0x0010
1327#define EEPROM_WORD0A_SWDPIO 0x01E0
1328#define EEPROM_WORD0A_LRST 0x0200
1329#define EEPROM_WORD0A_FD 0x0400
1330#define EEPROM_WORD0A_66MHZ 0x0800
1331
1332/* Mask bits for fields in Word 0x0f of the EEPROM */
1333#define EEPROM_WORD0F_PAUSE_MASK 0x3000
53677ef1
WD		 1334#define EEPROM_WORD0F_PAUSE 0x1000
1335#define EEPROM_WORD0F_ASM_DIR 0x2000
1336#define EEPROM_WORD0F_ANE 0x0800
682011ff
WD		 1337#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1338
1339/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
1340#define EEPROM_SUM 0xBABA
1341
1342/* EEPROM Map defines (WORD OFFSETS)*/
1343#define EEPROM_NODE_ADDRESS_BYTE_0 0
53677ef1 1344#define EEPROM_PBA_BYTE_1 8
682011ff
WD		 1345
1346/* EEPROM Map Sizes (Byte Counts) */
1347#define PBA_SIZE 4
1348
1349/* Collision related configuration parameters */
53677ef1
WD		 1350#define E1000_COLLISION_THRESHOLD 16
1351#define E1000_CT_SHIFT 4
1352#define E1000_COLLISION_DISTANCE 64
1353#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1354#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
682011ff 1355#define E1000_GB_HDX_COLLISION_DISTANCE 512
53677ef1 1356#define E1000_COLD_SHIFT 12
682011ff
WD		 1357
1358/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
1359#define REQ_TX_DESCRIPTOR_MULTIPLE 8
1360#define REQ_RX_DESCRIPTOR_MULTIPLE 8
1361
1362/* Default values for the transmit IPG register */
1363#define DEFAULT_82542_TIPG_IPGT 10
1364#define DEFAULT_82543_TIPG_IPGT_FIBER 9
1365#define DEFAULT_82543_TIPG_IPGT_COPPER 8
1366
1367#define E1000_TIPG_IPGT_MASK 0x000003FF
1368#define E1000_TIPG_IPGR1_MASK 0x000FFC00
1369#define E1000_TIPG_IPGR2_MASK 0x3FF00000
1370
1371#define DEFAULT_82542_TIPG_IPGR1 2
1372#define DEFAULT_82543_TIPG_IPGR1 8
53677ef1 1373#define E1000_TIPG_IPGR1_SHIFT 10
682011ff
WD		 1374
1375#define DEFAULT_82542_TIPG_IPGR2 10
1376#define DEFAULT_82543_TIPG_IPGR2 6
53677ef1 1377#define E1000_TIPG_IPGR2_SHIFT 20
682011ff
WD		 1378
1379#define E1000_TXDMAC_DPP 0x00000001
1380
1381/* Adaptive IFS defines */
1382#define TX_THRESHOLD_START 8
1383#define TX_THRESHOLD_INCREMENT 10
1384#define TX_THRESHOLD_DECREMENT 1
1385#define TX_THRESHOLD_STOP 190
1386#define TX_THRESHOLD_DISABLE 0
1387#define TX_THRESHOLD_TIMER_MS 10000
53677ef1
WD		 1388#define MIN_NUM_XMITS 1000
1389#define IFS_MAX 80
1390#define IFS_STEP 10
1391#define IFS_MIN 40
1392#define IFS_RATIO 4
682011ff
WD		 1393
1394/* PBA constants */
1395#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1396#define E1000_PBA_24K 0x0018
1397#define E1000_PBA_40K 0x0028
1398#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
1399
1400/* Flow Control Constants */
1401#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1402#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
53677ef1 1403#define FLOW_CONTROL_TYPE 0x8808
682011ff
WD		 1404
1405/* The historical defaults for the flow control values are given below. */
53677ef1
WD		 1406#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
1407#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
1408#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
682011ff
WD		 1409
1410/* Flow Control High-Watermark: 43464 bytes */
1411#define E1000_FC_HIGH_THRESH 0xA9C8
1412/* Flow Control Low-Watermark: 43456 bytes */
1413#define E1000_FC_LOW_THRESH 0xA9C0
1414/* Flow Control Pause Time: 858 usec */
1415#define E1000_FC_PAUSE_TIME 0x0680
1416
1417/* PCIX Config space */
53677ef1 1418#define PCIX_COMMAND_REGISTER 0xE6
682011ff
WD		 1419#define PCIX_STATUS_REGISTER_LO 0xE8
1420#define PCIX_STATUS_REGISTER_HI 0xEA
1421
1422#define PCIX_COMMAND_MMRBC_MASK 0x000C
1423#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1424#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1425#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1426#define PCIX_STATUS_HI_MMRBC_4K 0x3
1427#define PCIX_STATUS_HI_MMRBC_2K 0x2
1428
1429/* The number of bits that we need to shift right to move the "pause"
1430 * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
8bde7f77 1431 * in the TXCW register
682011ff
WD		 1432 */
1433#define PAUSE_SHIFT 5
1434
1435/* The number of bits that we need to shift left to move the "SWDPIO"
1436 * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
8bde7f77 1437 * in the CTRL register
682011ff
WD		 1438 */
1439#define SWDPIO_SHIFT 17
1440
1441/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
1442 * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
1443 * Extended CTRL register.
8bde7f77 1444 * in the CTRL register
682011ff
WD		 1445 */
1446#define SWDPIO__EXT_SHIFT 4
1447
1448/* The number of bits that we need to shift left to move the "ILOS"
1449 * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
8bde7f77 1450 * in the CTRL register
682011ff
WD		 1451 */
1452#define ILOS_SHIFT 3
1453
1454#define RECEIVE_BUFFER_ALIGN_SIZE (256)
1455
1456/* The number of milliseconds we wait for auto-negotiation to complete */
53677ef1 1457#define LINK_UP_TIMEOUT 500
682011ff
WD		 1458
1459#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1460
1461/* The carrier extension symbol, as received by the NIC. */
1462#define CARRIER_EXTENSION 0x0F
1463
1464/* TBI_ACCEPT macro definition:
1465 *
1466 * This macro requires:
53677ef1
WD		 1467 * adapter = a pointer to struct e1000_hw
1468 * status = the 8 bit status field of the RX descriptor with EOP set
1469 * error = the 8 bit error field of the RX descriptor with EOP set
1470 * length = the sum of all the length fields of the RX descriptors that
1471 * make up the current frame
1472 * last_byte = the last byte of the frame DMAed by the hardware
1473 * max_frame_length = the maximum frame length we want to accept.
1474 * min_frame_length = the minimum frame length we want to accept.
682011ff 1475 *
8bde7f77 1476 * This macro is a conditional that should be used in the interrupt
682011ff
WD		 1477 * handler's Rx processing routine when RxErrors have been detected.
1478 *
1479 * Typical use:
1480 * ...
1481 * if (TBI_ACCEPT) {
53677ef1
WD		 1482 * accept_frame = TRUE;
1483 * e1000_tbi_adjust_stats(adapter, MacAddress);
1484 * frame_length--;
682011ff 1485 * } else {
53677ef1 1486 * accept_frame = FALSE;
682011ff
WD		 1487 * }
1488 * ...
1489 */
1490
1491#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1492 ((adapter)->tbi_compatibility_on && \
1493 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1494 ((last_byte) == CARRIER_EXTENSION) && \
1495 (((status) & E1000_RXD_STAT_VP) ? \
8bde7f77
WD		 1496 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1497 ((length) <= ((adapter)->max_frame_size + 1))) : \
1498 (((length) > (adapter)->min_frame_size) && \
1499 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
682011ff
WD		 1500
1501/* Structures, enums, and macros for the PHY */
1502
1503/* Bit definitions for the Management Data IO (MDIO) and Management Data
1504 * Clock (MDC) pins in the Device Control Register.
1505 */
53677ef1
WD		 1506#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
1507#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
1508#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
1509#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
1510#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
1511#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
1512#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1513#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
682011ff
WD		 1514
1515/* PHY 1000 MII Register/Bit Definitions */
1516/* PHY Registers defined by IEEE */
53677ef1
WD		 1517#define PHY_CTRL 0x00 /* Control Register */
1518#define PHY_STATUS 0x01 /* Status Regiser */
1519#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1520#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1521#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1522#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1523#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1524#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
1525#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1526#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1527#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1528#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
682011ff
WD		 1529
1530/* M88E1000 Specific Registers */
53677ef1
WD		 1531#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1532#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1533#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1534#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1535#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1536#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
682011ff 1537
53677ef1 1538#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
ac3315c2
AS		 1539
1540/* IGP01E1000 specifics */
53677ef1 1541#define IGP01E1000_IEEE_REGS_PAGE 0x0000
ac3315c2 1542#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
53677ef1 1543#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
ac3315c2
AS		 1544
1545/* IGP01E1000 Specific Registers */
53677ef1
WD		 1546#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
1547#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
1548#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
1549#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
1550#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
1551#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
1552#define IGP02E1000_PHY_POWER_MGMT 0x19
1553#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
682011ff
WD		 1554
1555/* PHY Control Register */
53677ef1
WD		 1556#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1557#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
1558#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1559#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1560#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
1561#define MII_CR_POWER_DOWN 0x0800 /* Power down */
1562#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1563#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
1564#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1565#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
682011ff
WD		 1566
1567/* PHY Status Register */
53677ef1
WD		 1568#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
1569#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
1570#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1571#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1572#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
1573#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1574#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1575#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
1576#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1577#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1578#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1579#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1580#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1581#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1582#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
682011ff
WD		 1583
1584/* Autoneg Advertisement Register */
53677ef1
WD		 1585#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
1586#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1587#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1588#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1589#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1590#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1591#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1592#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1593#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
1594#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
682011ff
WD		 1595
1596/* Link Partner Ability Register (Base Page) */
53677ef1
WD		 1597#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1598#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
1599#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
1600#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
1601#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
1602#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1603#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1604#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
1605#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
1606#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
1607#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
682011ff
WD		 1608
1609/* Autoneg Expansion Register */
53677ef1
WD		 1610#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
1611#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
1612#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
1613#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1614#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
682011ff
WD		 1615
1616/* Next Page TX Register */
53677ef1
WD		 1617#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1618#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
1619 * of different NP
1620 */
1621#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1622 * 0 = cannot comply with msg
1623 */
1624#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1625#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1626 * 0 = sending last NP
1627 */
682011ff
WD		 1628
1629/* Link Partner Next Page Register */
53677ef1
WD		 1630#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1631#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
1632 * of different NP
1633 */
1634#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1635 * 0 = cannot comply with msg
1636 */
1637#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1638#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
1639#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1640 * 0 = sending last NP
1641 */
682011ff
WD		 1642
1643/* 1000BASE-T Control Register */
53677ef1
WD		 1644#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1645#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1646#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1647#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
1648 /* 0=DTE device */
1649#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
1650 /* 0=Configure PHY as Slave */
1651#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
1652 /* 0=Automatic Master/Slave config */
1653#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1654#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1655#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1656#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1657#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
682011ff
WD		 1658
1659/* 1000BASE-T Status Register */
53677ef1
WD		 1660#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1661#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1662#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1663#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1664#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1665#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1666#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
1667#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
682011ff 1668#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
53677ef1 1669#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
682011ff
WD		 1670
1671/* Extended Status Register */
53677ef1
WD		 1672#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
1673#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
1674#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
1675#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
682011ff 1676
53677ef1
WD		 1677#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
1678#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
682011ff 1679
53677ef1
WD		 1680#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
1681 /* (0=enable, 1=disable) */
682011ff
WD		 1682
1683/* M88E1000 PHY Specific Control Register */
53677ef1 1684#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
682011ff 1685#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
53677ef1
WD		 1686#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1687#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
682011ff
WD		 1688 * 0=CLK125 toggling
1689 */
53677ef1
WD		 1690#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1691 /* Manual MDI configuration */
1692#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1693#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
8bde7f77 1694 * 100BASE-TX/10BASE-T:
682011ff
WD		 1695 * MDI Mode
1696 */
53677ef1 1697#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
8bde7f77 1698 * all speeds.
682011ff
WD		 1699 */
1700#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
53677ef1
WD		 1701 /* 1=Enable Extended 10BASE-T distance
1702 * (Lower 10BASE-T RX Threshold)
1703 * 0=Normal 10BASE-T RX Threshold */
1704#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1705 /* 1=5-Bit interface in 100BASE-TX
1706 * 0=MII interface in 100BASE-TX */
1707#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1708#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1709#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1710
1711#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
1712#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
682011ff
WD		 1713#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1714
1715/* M88E1000 PHY Specific Status Register */
53677ef1
WD		 1716#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1717#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1718#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1719#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
1720 * 3=110-140M;4=>140M */
1721#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1722#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1723#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1724#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1725#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1726#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1727#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1728#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
682011ff
WD		 1729
1730#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
53677ef1 1731#define M88E1000_PSSR_MDIX_SHIFT 6
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WD		 1732#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1733
1734/* M88E1000 Extended PHY Specific Control Register */
53677ef1
WD		 1735#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1736#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
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WD		 1737 * Will assert lost lock and bring
1738 * link down if idle not seen
8bde7f77 1739 * within 1ms in 1000BASE-T
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WD		 1740 */
1741/* Number of times we will attempt to autonegotiate before downshifting if we
1742 * are the master */
1743#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1744#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1745#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1746#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1747#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1748/* Number of times we will attempt to autonegotiate before downshifting if we
1749 * are the slave */
1750#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1751#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1752#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1753#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1754#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
53677ef1
WD		 1755#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1756#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1757#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
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WD		 1758
1759/* Bit definitions for valid PHY IDs. */
53677ef1
WD		 1760#define M88E1000_E_PHY_ID 0x01410C50
1761#define M88E1000_I_PHY_ID 0x01410C30
1762#define M88E1011_I_PHY_ID 0x01410C20
1763#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
1764#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
1765#define IGP01E1000_I_PHY_ID 0x02A80380
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WD		 1766
1767/* Miscellaneous PHY bit definitions. */
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WD		 1768#define PHY_PREAMBLE 0xFFFFFFFF
1769#define PHY_SOF 0x01
1770#define PHY_OP_READ 0x02
1771#define PHY_OP_WRITE 0x01
1772#define PHY_TURNAROUND 0x02
1773#define PHY_PREAMBLE_SIZE 32
1774#define MII_CR_SPEED_1000 0x0040
1775#define MII_CR_SPEED_100 0x2000
1776#define MII_CR_SPEED_10 0x0000
1777#define E1000_PHY_ADDRESS 0x01
1778#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1779#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
1780#define PHY_REVISION_MASK 0xFFFFFFF0
1781#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
1782#define REG4_SPEED_MASK 0x01E0
1783#define REG9_SPEED_MASK 0x0300
1784#define ADVERTISE_10_HALF 0x0001
1785#define ADVERTISE_10_FULL 0x0002
1786#define ADVERTISE_100_HALF 0x0004
1787#define ADVERTISE_100_FULL 0x0008
1788#define ADVERTISE_1000_HALF 0x0010
1789#define ADVERTISE_1000_FULL 0x0020
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WD		 1790#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
1791
53677ef1 1792#endif /* _E1000_HW_H_ */
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