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MX31: add accessor function to get a gpio
[people/ms/u-boot.git] / drivers / net / enc28j60.c
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160131bf
PP		 1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License as
4 * published by the Free Software Foundation; either version 2 of
5 * the License, or (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
15 * MA 02111-1307 USA
16 */
17
18#include <config.h>
19#include <common.h>
160131bf
PP		 20#include <net.h>
21#include <asm/arch/hardware.h>
22#include <asm/arch/spi.h>
23
24/*
25 * Control Registers in Bank 0
26 */
27
28#define CTL_REG_ERDPTL 0x00
29#define CTL_REG_ERDPTH 0x01
30#define CTL_REG_EWRPTL 0x02
31#define CTL_REG_EWRPTH 0x03
32#define CTL_REG_ETXSTL 0x04
33#define CTL_REG_ETXSTH 0x05
34#define CTL_REG_ETXNDL 0x06
35#define CTL_REG_ETXNDH 0x07
36#define CTL_REG_ERXSTL 0x08
37#define CTL_REG_ERXSTH 0x09
38#define CTL_REG_ERXNDL 0x0A
39#define CTL_REG_ERXNDH 0x0B
40#define CTL_REG_ERXRDPTL 0x0C
41#define CTL_REG_ERXRDPTH 0x0D
42#define CTL_REG_ERXWRPTL 0x0E
43#define CTL_REG_ERXWRPTH 0x0F
44#define CTL_REG_EDMASTL 0x10
45#define CTL_REG_EDMASTH 0x11
46#define CTL_REG_EDMANDL 0x12
47#define CTL_REG_EDMANDH 0x13
48#define CTL_REG_EDMADSTL 0x14
49#define CTL_REG_EDMADSTH 0x15
50#define CTL_REG_EDMACSL 0x16
51#define CTL_REG_EDMACSH 0x17
52/* these are common in all banks */
53#define CTL_REG_EIE 0x1B
54#define CTL_REG_EIR 0x1C
55#define CTL_REG_ESTAT 0x1D
56#define CTL_REG_ECON2 0x1E
57#define CTL_REG_ECON1 0x1F
58
59/*
60 * Control Registers in Bank 1
61 */
62
63#define CTL_REG_EHT0 0x00
64#define CTL_REG_EHT1 0x01
65#define CTL_REG_EHT2 0x02
66#define CTL_REG_EHT3 0x03
67#define CTL_REG_EHT4 0x04
68#define CTL_REG_EHT5 0x05
69#define CTL_REG_EHT6 0x06
70#define CTL_REG_EHT7 0x07
71#define CTL_REG_EPMM0 0x08
72#define CTL_REG_EPMM1 0x09
73#define CTL_REG_EPMM2 0x0A
74#define CTL_REG_EPMM3 0x0B
75#define CTL_REG_EPMM4 0x0C
76#define CTL_REG_EPMM5 0x0D
77#define CTL_REG_EPMM6 0x0E
78#define CTL_REG_EPMM7 0x0F
79#define CTL_REG_EPMCSL 0x10
80#define CTL_REG_EPMCSH 0x11
81#define CTL_REG_EPMOL 0x14
82#define CTL_REG_EPMOH 0x15
83#define CTL_REG_EWOLIE 0x16
84#define CTL_REG_EWOLIR 0x17
85#define CTL_REG_ERXFCON 0x18
86#define CTL_REG_EPKTCNT 0x19
87
88/*
89 * Control Registers in Bank 2
90 */
91
92#define CTL_REG_MACON1 0x00
93#define CTL_REG_MACON2 0x01
94#define CTL_REG_MACON3 0x02
95#define CTL_REG_MACON4 0x03
96#define CTL_REG_MABBIPG 0x04
97#define CTL_REG_MAIPGL 0x06
98#define CTL_REG_MAIPGH 0x07
99#define CTL_REG_MACLCON1 0x08
100#define CTL_REG_MACLCON2 0x09
101#define CTL_REG_MAMXFLL 0x0A
102#define CTL_REG_MAMXFLH 0x0B
103#define CTL_REG_MAPHSUP 0x0D
104#define CTL_REG_MICON 0x11
105#define CTL_REG_MICMD 0x12
106#define CTL_REG_MIREGADR 0x14
107#define CTL_REG_MIWRL 0x16
108#define CTL_REG_MIWRH 0x17
109#define CTL_REG_MIRDL 0x18
110#define CTL_REG_MIRDH 0x19
111
112/*
113 * Control Registers in Bank 3
114 */
115
116#define CTL_REG_MAADR1 0x00
117#define CTL_REG_MAADR0 0x01
118#define CTL_REG_MAADR3 0x02
119#define CTL_REG_MAADR2 0x03
120#define CTL_REG_MAADR5 0x04
121#define CTL_REG_MAADR4 0x05
122#define CTL_REG_EBSTSD 0x06
123#define CTL_REG_EBSTCON 0x07
124#define CTL_REG_EBSTCSL 0x08
125#define CTL_REG_EBSTCSH 0x09
126#define CTL_REG_MISTAT 0x0A
127#define CTL_REG_EREVID 0x12
128#define CTL_REG_ECOCON 0x15
129#define CTL_REG_EFLOCON 0x17
130#define CTL_REG_EPAUSL 0x18
131#define CTL_REG_EPAUSH 0x19
132
133
134/*
135 * PHY Register
136 */
137
138#define PHY_REG_PHID1 0x02
139#define PHY_REG_PHID2 0x03
140/* taken from the Linux driver */
141#define PHY_REG_PHCON1 0x00
142#define PHY_REG_PHCON2 0x10
143#define PHY_REG_PHLCON 0x14
144
145/*
146 * Receive Filter Register (ERXFCON) bits
147 */
148
149#define ENC_RFR_UCEN 0x80
150#define ENC_RFR_ANDOR 0x40
151#define ENC_RFR_CRCEN 0x20
152#define ENC_RFR_PMEN 0x10
153#define ENC_RFR_MPEN 0x08
154#define ENC_RFR_HTEN 0x04
155#define ENC_RFR_MCEN 0x02
156#define ENC_RFR_BCEN 0x01
157
158/*
159 * ECON1 Register Bits
160 */
161
162#define ENC_ECON1_TXRST 0x80
163#define ENC_ECON1_RXRST 0x40
164#define ENC_ECON1_DMAST 0x20
165#define ENC_ECON1_CSUMEN 0x10
166#define ENC_ECON1_TXRTS 0x08
167#define ENC_ECON1_RXEN 0x04
168#define ENC_ECON1_BSEL1 0x02
169#define ENC_ECON1_BSEL0 0x01
170
171/*
172 * ECON2 Register Bits
173 */
174#define ENC_ECON2_AUTOINC 0x80
175#define ENC_ECON2_PKTDEC 0x40
176#define ENC_ECON2_PWRSV 0x20
177#define ENC_ECON2_VRPS 0x08
178
179/*
180 * EIR Register Bits
181 */
182#define ENC_EIR_PKTIF 0x40
183#define ENC_EIR_DMAIF 0x20
184#define ENC_EIR_LINKIF 0x10
185#define ENC_EIR_TXIF 0x08
186#define ENC_EIR_WOLIF 0x04
187#define ENC_EIR_TXERIF 0x02
188#define ENC_EIR_RXERIF 0x01
189
190/*
191 * ESTAT Register Bits
192 */
193
194#define ENC_ESTAT_INT 0x80
195#define ENC_ESTAT_LATECOL 0x10
196#define ENC_ESTAT_RXBUSY 0x04
197#define ENC_ESTAT_TXABRT 0x02
198#define ENC_ESTAT_CLKRDY 0x01
199
200/*
201 * EIE Register Bits
202 */
203
204#define ENC_EIE_INTIE 0x80
205#define ENC_EIE_PKTIE 0x40
206#define ENC_EIE_DMAIE 0x20
207#define ENC_EIE_LINKIE 0x10
208#define ENC_EIE_TXIE 0x08
209#define ENC_EIE_WOLIE 0x04
210#define ENC_EIE_TXERIE 0x02
211#define ENC_EIE_RXERIE 0x01
212
213/*
214 * MACON1 Register Bits
215 */
216#define ENC_MACON1_LOOPBK 0x10
217#define ENC_MACON1_TXPAUS 0x08
218#define ENC_MACON1_RXPAUS 0x04
219#define ENC_MACON1_PASSALL 0x02
220#define ENC_MACON1_MARXEN 0x01
221
222
223/*
224 * MACON2 Register Bits
225 */
226#define ENC_MACON2_MARST 0x80
227#define ENC_MACON2_RNDRST 0x40
228#define ENC_MACON2_MARXRST 0x08
229#define ENC_MACON2_RFUNRST 0x04
230#define ENC_MACON2_MATXRST 0x02
231#define ENC_MACON2_TFUNRST 0x01
232
233/*
234 * MACON3 Register Bits
235 */
236#define ENC_MACON3_PADCFG2 0x80
237#define ENC_MACON3_PADCFG1 0x40
238#define ENC_MACON3_PADCFG0 0x20
239#define ENC_MACON3_TXCRCEN 0x10
240#define ENC_MACON3_PHDRLEN 0x08
241#define ENC_MACON3_HFRMEN 0x04
242#define ENC_MACON3_FRMLNEN 0x02
243#define ENC_MACON3_FULDPX 0x01
244
245/*
246 * MICMD Register Bits
247 */
248#define ENC_MICMD_MIISCAN 0x02
249#define ENC_MICMD_MIIRD 0x01
250
251/*
252 * MISTAT Register Bits
253 */
254#define ENC_MISTAT_NVALID 0x04
255#define ENC_MISTAT_SCAN 0x02
256#define ENC_MISTAT_BUSY 0x01
257
258/*
259 * PHID1 and PHID2 values
260 */
261#define ENC_PHID1_VALUE 0x0083
262#define ENC_PHID2_VALUE 0x1400
263#define ENC_PHID2_MASK 0xFC00
264
265
266#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */
267#define ENC_RESET 0x00020000 /* pin P1.17 */
268
269#define FAILSAFE_VALUE 5000
270
271/*
272 * Controller memory layout:
273 *
274 * 0x0000 - 0x17ff 6k bytes receive buffer
275 * 0x1800 - 0x1fff 2k bytes transmit buffer
276 */
277/* Use the lower memory for receiver buffer. See errata pt. 5 */
278#define ENC_RX_BUF_START 0x0000
279#define ENC_TX_BUF_START 0x1800
280/* taken from the Linux driver */
281#define ENC_RX_BUF_END 0x17ff
282#define ENC_TX_BUF_END 0x1fff
283
284/* maximum frame length */
285#define ENC_MAX_FRM_LEN 1518
286
287#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
288#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
289#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
290
291
292static unsigned char encReadReg (unsigned char regNo);
293static void encWriteReg (unsigned char regNo, unsigned char data);
294static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
295static void encReadBuff (unsigned short length, unsigned char *pBuff);
296static void encWriteBuff (unsigned short length, unsigned char *pBuff);
297static void encBitSet (unsigned char regNo, unsigned char data);
298static void encBitClr (unsigned char regNo, unsigned char data);
299static void encReset (void);
300static void encInit (unsigned char *pEthAddr);
301static unsigned short phyRead (unsigned char addr);
302static void phyWrite(unsigned char, unsigned short);
303static void encPoll (void);
304static void encRx (void);
305
306#define m_nic_read(reg) encReadReg(reg)
307#define m_nic_write(reg, data) encWriteReg(reg, data)
308#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
309#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
310#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
311
312/* bit field set */
313#define m_nic_bfs(reg, data) encBitSet(reg, data)
314
315/* bit field clear */
316#define m_nic_bfc(reg, data) encBitClr(reg, data)
317
318static unsigned char bank = 0; /* current bank in enc28j60 */
319static unsigned char next_pointer_lsb;
320static unsigned char next_pointer_msb;
321
322static unsigned char buffer[ENC_MAX_FRM_LEN];
323static int rxResetCounter = 0;
324
325#define RX_RESET_COUNTER 1000;
326
327/*-----------------------------------------------------------------------------
328 * Always returns 0
329 */
330int eth_init (bd_t * bis)
331{
332 unsigned char estatVal;
d3f87148 333 uchar enetaddr[6];
160131bf
PP		 334
335 /* configure GPIO */
336 (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
337 (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
338
339 /* CS and RESET active low */
340 PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
341 PUT32 (IO1SET, ENC_RESET);
342
343 spi_init ();
344
345 /* taken from the Linux driver - dangerous stuff here! */
346 /* Wait for CLKRDY to become set (i.e., check that we can communicate with
347 the ENC) */
348 do
349 {
350 estatVal = m_nic_read(CTL_REG_ESTAT);
351 } while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY));
352
353 /* initialize controller */
354 encReset ();
d3f87148
MF		 355 eth_getenv_enetaddr("ethaddr", enetaddr);
356 encInit (enetaddr);
160131bf
PP		 357
358 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
359
360 return 0;
361}
362
363int eth_send (volatile void *packet, int length)
364{
365 /* check frame length, etc. */
366 /* TODO: */
367
368 /* switch to bank 0 */
369 m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
370
371 /* set EWRPT */
372 m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
373 m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
374
375 /* set ETXND */
376 m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
377 m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
378
379 /* set ETXST */
380 m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
381 m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
382
383 /* write packet */
384 m_nic_write_data (length, (unsigned char *) packet);
385
386 /* taken from the Linux driver */
387 /* Verify that the internal transmit logic has not been altered by excessive
388 collisions. See Errata B4 12 and 14.
389 */
390 if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) {
391 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST);
392 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST);
393 }
394 m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
395
396 /* set ECON1.TXRTS */
397 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
398
399 return 0;
400}
401
402
403/*****************************************************************************
404 * This function resets the receiver only. This function may be called from
405 * interrupt-context.
406 */
407static void encReceiverReset (void)
408{
409 unsigned char econ1;
410
411 econ1 = m_nic_read (CTL_REG_ECON1);
412 if ((econ1 & ENC_ECON1_RXRST) == 0) {
413 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
414 rxResetCounter = RX_RESET_COUNTER;
415 }
416}
417
418/*****************************************************************************
419 * receiver reset timer
420 */
421static void encReceiverResetCallback (void)
422{
423 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
424 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
425}
426
427/*-----------------------------------------------------------------------------
428 * Check for received packets. Call NetReceive for each packet. The return
429 * value is ignored by the caller.
430 */
431int eth_rx (void)
432{
433 if (rxResetCounter > 0 && --rxResetCounter == 0) {
434 encReceiverResetCallback ();
435 }
436
437 encPoll ();
438
439 return 0;
440}
441
442void eth_halt (void)
443{
444 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */
445}
446
447/*****************************************************************************/
448
449static void encPoll (void)
450{
451 unsigned char eir_reg;
452 volatile unsigned char estat_reg;
453 unsigned char pkt_cnt;
454
455#ifdef CONFIG_USE_IRQ
456 /* clear global interrupt enable bit in enc28j60 */
457 m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
458#endif
459 estat_reg = m_nic_read (CTL_REG_ESTAT);
460
461 eir_reg = m_nic_read (CTL_REG_EIR);
462
463 if (eir_reg & ENC_EIR_TXIF) {
464 /* clear TXIF bit in EIR */
465 m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
466 }
467
468 /* We have to use pktcnt and not pktif bit, see errata pt. 6 */
469
470 /* move to bank 1 */
471 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
472 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
473
474 /* read pktcnt */
475 pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
476
477 if (pkt_cnt > 0) {
478 if ((eir_reg & ENC_EIR_PKTIF) == 0) {
479 /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
480 }
481 encRx ();
482 /* clear PKTIF bit in EIR, this should not need to be done but it
483 seems like we get problems if we do not */
484 m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
485 }
486
487 if (eir_reg & ENC_EIR_RXERIF) {
488 printf ("encPoll: rx error\n");
489 m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
490 }
491 if (eir_reg & ENC_EIR_TXERIF) {
492 printf ("encPoll: tx error\n");
493 m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
494 }
495
496#ifdef CONFIG_USE_IRQ
497 /* set global interrupt enable bit in enc28j60 */
498 m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
499#endif
500}
501
502static void encRx (void)
503{
504 unsigned short pkt_len;
505 unsigned short copy_len;
506 unsigned short status;
507 unsigned char eir_reg;
508 unsigned char pkt_cnt = 0;
509 unsigned short rxbuf_rdpt;
510
511 /* switch to bank 0 */
512 m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
513
514 m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
515 m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
516
517 do {
518 m_nic_read_data (6, buffer);
519 next_pointer_lsb = buffer[0];
520 next_pointer_msb = buffer[1];
521 pkt_len = buffer[2];
522 pkt_len |= (unsigned short) buffer[3] << 8;
523 status = buffer[4];
524 status |= (unsigned short) buffer[5] << 8;
525
526 if (pkt_len <= ENC_MAX_FRM_LEN)
527 copy_len = pkt_len;
528 else
529 copy_len = 0;
530
531 if ((status & (1L << 7)) == 0) /* check Received Ok bit */
532 copy_len = 0;
533
534 /* taken from the Linux driver */
535 /* check if next pointer is resonable */
536 if ((((unsigned int)next_pointer_msb << 8) |
537 (unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START)
538 copy_len = 0;
539
540 if (copy_len > 0) {
541 m_nic_read_data (copy_len, buffer);
542 }
543
544 /* advance read pointer to next pointer */
545 m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
546 m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
547
548 /* decrease packet counter */
549 m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
550
551 /* taken from the Linux driver */
725671cc
WD		 552 /* Only odd values should be written to ERXRDPTL,
553 * see errata B4 pt.13
3e3b9569
PP		 554 */
555 rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1;
160131bf
PP		 556 if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 |
557 m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt >
558 (m_nic_read(CTL_REG_ERXNDH) << 8 |
559 m_nic_read(CTL_REG_ERXNDL)))) {
560 m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL));
561 m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH));
562 } else {
563 m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF);
564 m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8);
565 }
566
567 /* move to bank 1 */
568 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
569 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
570
571 /* read pktcnt */
572 pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
573
574 /* switch to bank 0 */
575 m_nic_bfc (CTL_REG_ECON1,
576 (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
577
578 if (copy_len == 0) {
579 eir_reg = m_nic_read (CTL_REG_EIR);
580 encReceiverReset ();
581 printf ("eth_rx: copy_len=0\n");
582 continue;
583 }
584
585 NetReceive ((unsigned char *) buffer, pkt_len);
586
587 eir_reg = m_nic_read (CTL_REG_EIR);
588 } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
589}
590
591static void encWriteReg (unsigned char regNo, unsigned char data)
592{
593 spi_lock ();
594 enc_cfg_spi ();
595 enc_enable ();
596
597 spi_write (0x40 | regNo); /* write in regNo */
598 spi_write (data);
599
600 enc_disable ();
601 enc_enable ();
602
603 spi_write (0x1f); /* write reg 0x1f */
604
605 enc_disable ();
606 spi_unlock ();
607}
608
609static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
610{
611 unsigned char readback;
612 int i;
613
614 spi_lock ();
615
616 for (i = 0; i < c; i++) {
617 enc_cfg_spi ();
618 enc_enable ();
619
620 spi_write (0x40 | regNo); /* write in regNo */
621 spi_write (data);
622
623 enc_disable ();
624 enc_enable ();
625
626 spi_write (0x1f); /* write reg 0x1f */
627
628 enc_disable ();
629
630 spi_unlock (); /* we must unlock spi first */
631
632 readback = encReadReg (regNo);
633
634 spi_lock ();
635
636 if (readback == data)
637 break;
638 }
639 spi_unlock ();
640
641 if (i == c) {
642 printf ("enc28j60: write reg %d failed\n", regNo);
643 }
644}
645
646static unsigned char encReadReg (unsigned char regNo)
647{
648 unsigned char rxByte;
649
650 spi_lock ();
651 enc_cfg_spi ();
652 enc_enable ();
653
654 spi_write (0x1f); /* read reg 0x1f */
655
656 bank = spi_read () & 0x3;
657
658 enc_disable ();
659 enc_enable ();
660
661 spi_write (regNo);
662 rxByte = spi_read ();
663
664 /* check if MAC or MII register */
665 if (((bank == 2) && (regNo <= 0x1a)) ||
666 ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
667 /* ignore first byte and read another byte */
668 rxByte = spi_read ();
669 }
670
671 enc_disable ();
672 spi_unlock ();
673
674 return rxByte;
675}
676
677static void encReadBuff (unsigned short length, unsigned char *pBuff)
678{
679 spi_lock ();
680 enc_cfg_spi ();
681 enc_enable ();
682
683 spi_write (0x20 | 0x1a); /* read buffer memory */
684
685 while (length--) {
686 if (pBuff != NULL)
687 *pBuff++ = spi_read ();
688 else
689 spi_write (0);
690 }
691
692 enc_disable ();
693 spi_unlock ();
694}
695
696static void encWriteBuff (unsigned short length, unsigned char *pBuff)
697{
698 spi_lock ();
699 enc_cfg_spi ();
700 enc_enable ();
701
702 spi_write (0x60 | 0x1a); /* write buffer memory */
703
704 spi_write (0x00); /* control byte */
705
706 while (length--)
707 spi_write (*pBuff++);
708
709 enc_disable ();
710 spi_unlock ();
711}
712
713static void encBitSet (unsigned char regNo, unsigned char data)
714{
715 spi_lock ();
716 enc_cfg_spi ();
717 enc_enable ();
718
719 spi_write (0x80 | regNo); /* bit field set */
720 spi_write (data);
721
722 enc_disable ();
723 spi_unlock ();
724}
725
726static void encBitClr (unsigned char regNo, unsigned char data)
727{
728 spi_lock ();
729 enc_cfg_spi ();
730 enc_enable ();
731
732 spi_write (0xA0 | regNo); /* bit field clear */
733 spi_write (data);
734
735 enc_disable ();
736 spi_unlock ();
737}
738
739static void encReset (void)
740{
741 spi_lock ();
742 enc_cfg_spi ();
743 enc_enable ();
744
745 spi_write (0xff); /* soft reset */
746
747 enc_disable ();
748 spi_unlock ();
749
750 /* sleep 1 ms. See errata pt. 2 */
751 udelay (1000);
752}
753
754static void encInit (unsigned char *pEthAddr)
755{
756 unsigned short phid1 = 0;
757 unsigned short phid2 = 0;
758
759 /* switch to bank 0 */
760 m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
761
762 /*
763 * Setup the buffer space. The reset values are valid for the
764 * other pointers.
765 */
766 /* We shall not write to ERXST, see errata pt. 5. Instead we
767 have to make sure that ENC_RX_BUS_START is 0. */
768 m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
769 m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
770
771 /* taken from the Linux driver */
772 m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1);
773 m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1);
774
775 m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
776 m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
777
778 next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
779 next_pointer_msb = (ENC_RX_BUF_START >> 8);
780
781 /* verify identification */
782 phid1 = phyRead (PHY_REG_PHID1);
783 phid2 = phyRead (PHY_REG_PHID2);
784
785 if (phid1 != ENC_PHID1_VALUE
786 || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
787 printf ("ERROR: failed to identify controller\n");
788 printf ("phid1 = %x, phid2 = %x\n",
789 phid1, (phid2 & ENC_PHID2_MASK));
790 printf ("should be phid1 = %x, phid2 = %x\n",
791 ENC_PHID1_VALUE, ENC_PHID2_VALUE);
792 }
793
794 /*
795 * --- MAC Initialization ---
796 */
797
798 /* Pull MAC out of Reset */
799
800 /* switch to bank 2 */
801 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
802 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
803
804 /* enable MAC to receive frames */
805 /* added some bits from the Linux driver */
3e3b9569
PP		 806 m_nic_write_retry (CTL_REG_MACON1
807 ,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS)
808 ,10);
160131bf
PP		 809
810 /* configure pad, tx-crc and duplex */
811 /* added a bit from the Linux driver */
3e3b9569
PP		 812 m_nic_write_retry (CTL_REG_MACON3
813 ,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN)
814 ,10);
160131bf
PP		 815
816 /* added 4 new lines from the Linux driver */
817 /* Allow infinite deferals if the medium is continously busy */
818 m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10);
819
820 /* Late collisions occur beyond 63 bytes */
821 m_nic_write_retry(CTL_REG_MACLCON2, 63, 10);
822
823 /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
824 m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10);
825
826 /*
827 * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
828 * 0x0c for half-duplex. Nothing for full-duplex
829 */
830 m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10);
831
832 /* set maximum frame length */
833 m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
834 m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
835
836 /*
837 * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
838 * and 0x15 for full duplex.
839 */
840 m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
841
842 /* set MAC address */
843
844 /* switch to bank 3 */
845 m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
846
847 m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
848 m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
849 m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
850 m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
851 m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
852 m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
853
854 /*
855 * PHY Initialization taken from the Linux driver
856 */
857
858 /* Prevent automatic loopback of data beeing transmitted by setting
859 ENC_PHCON2_HDLDIS */
860 phyWrite(PHY_REG_PHCON2, (1<<8));
861
862 /* LEDs configuration
863 * LEDA: LACFG = 0100 -> display link status
864 * LEDB: LBCFG = 0111 -> display TX & RX activity
865 * STRCH = 1 -> LED pulses
866 */
867 phyWrite(PHY_REG_PHLCON, 0x0472);
868
869 /* Reset PDPXMD-bit => half duplex */
870 phyWrite(PHY_REG_PHCON1, 0);
871
872 /*
873 * Receive settings
874 */
875
876#ifdef CONFIG_USE_IRQ
877 /* enable interrupts */
878 m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
879 m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
880 m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
881 m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
882 m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
883#endif
884}
885
886/*****************************************************************************
887 *
888 * Description:
889 * Read PHY registers.
890 *
891 * NOTE! This function will change to Bank 2.
892 *
893 * Params:
894 * [in] addr address of the register to read
895 *
896 * Returns:
897 * The value in the register
898 */
899static unsigned short phyRead (unsigned char addr)
900{
901 unsigned short ret = 0;
902
903 /* move to bank 2 */
904 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
905 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
906
907 /* write address to MIREGADR */
908 m_nic_write (CTL_REG_MIREGADR, addr);
909
910 /* set MICMD.MIIRD */
911 m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
912
913 /* taken from the Linux driver */
914 /* move to bank 3 */
915 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
916 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
917
918 /* poll MISTAT.BUSY bit until operation is complete */
919 while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
920 static int cnt = 0;
921
922 if (cnt++ >= 1000) {
923 /* GJ - this seems extremely dangerous! */
924 /* printf("#"); */
925 cnt = 0;
926 }
927 }
928
929 /* taken from the Linux driver */
930 /* move to bank 2 */
931 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
932 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
933
934 /* clear MICMD.MIIRD */
935 m_nic_write (CTL_REG_MICMD, 0);
936
937 ret = (m_nic_read (CTL_REG_MIRDH) << 8);
938 ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
939
940 return ret;
941}
942
943/*****************************************************************************
944 *
945 * Taken from the Linux driver.
946 * Description:
947 * Write PHY registers.
948 *
949 * NOTE! This function will change to Bank 3.
950 *
951 * Params:
952 * [in] addr address of the register to write to
953 * [in] data to be written
954 *
955 * Returns:
956 * None
957 */
958static void phyWrite(unsigned char addr, unsigned short data)
959{
960 /* move to bank 2 */
961 m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
962 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
963
964 /* write address to MIREGADR */
965 m_nic_write(CTL_REG_MIREGADR, addr);
966
967 m_nic_write(CTL_REG_MIWRL, data & 0xff);
968 m_nic_write(CTL_REG_MIWRH, data >> 8);
969
970 /* move to bank 3 */
971 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
972 m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
973
974 /* poll MISTAT.BUSY bit until operation is complete */
975 while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
976 static int cnt = 0;
977
978 if(cnt++ >= 1000) {
979 cnt = 0;
980 }
981 }
982}
"Das U-Boot" Source Tree