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a61a8196 RM |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de | |
4 | * Martin Krause, Martin.Krause@tqs.de | |
5 | * reworked original enc28j60.c | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
a61a8196 RM |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <net.h> | |
12 | #include <spi.h> | |
13 | #include <malloc.h> | |
14 | #include <netdev.h> | |
15 | #include <miiphy.h> | |
16 | #include "enc28j60.h" | |
17 | ||
18 | /* | |
19 | * IMPORTANT: spi_claim_bus() and spi_release_bus() | |
20 | * are called at begin and end of each of the following functions: | |
21 | * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(), | |
22 | * enc_init(), enc_recv(), enc_send(), enc_halt() | |
23 | * ALL other functions assume that the bus has already been claimed! | |
1fd92db8 JH |
24 | * Since net_process_received_packet() might call enc_send() in return, the bus |
25 | * must be released, net_process_received_packet() called and claimed again. | |
a61a8196 RM |
26 | */ |
27 | ||
28 | /* | |
29 | * Controller memory layout. | |
30 | * We only allow 1 frame for transmission and reserve the rest | |
31 | * for reception to handle as many broadcast packets as possible. | |
32 | * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5 | |
33 | * 0x0000 - 0x19ff 6656 bytes receive buffer | |
34 | * 0x1a00 - 0x1fff 1536 bytes transmit buffer = | |
35 | * control(1)+frame(1518)+status(7)+reserve(10). | |
36 | */ | |
37 | #define ENC_RX_BUF_START 0x0000 | |
38 | #define ENC_RX_BUF_END 0x19ff | |
39 | #define ENC_TX_BUF_START 0x1a00 | |
40 | #define ENC_TX_BUF_END 0x1fff | |
41 | #define ENC_MAX_FRM_LEN 1518 | |
42 | #define RX_RESET_COUNTER 1000 | |
43 | ||
44 | /* | |
45 | * For non data transfer functions, like phy read/write, set hwaddr, init | |
46 | * we do not need a full, time consuming init including link ready wait. | |
47 | * This enum helps to bring the chip through the minimum necessary inits. | |
48 | */ | |
49 | enum enc_initstate {none=0, setupdone, linkready}; | |
50 | typedef struct enc_device { | |
51 | struct eth_device *dev; /* back pointer */ | |
52 | struct spi_slave *slave; | |
53 | int rx_reset_counter; | |
54 | u16 next_pointer; | |
55 | u8 bank; /* current bank in enc28j60 */ | |
56 | enum enc_initstate initstate; | |
57 | } enc_dev_t; | |
58 | ||
59 | /* | |
60 | * enc_bset: set bits in a common register | |
61 | * enc_bclr: clear bits in a common register | |
62 | * | |
63 | * making the reg parameter u8 will give a compile time warning if the | |
64 | * functions are called with a register not accessible in all Banks | |
65 | */ | |
66 | static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data) | |
67 | { | |
68 | u8 dout[2]; | |
69 | ||
70 | dout[0] = CMD_BFS(reg); | |
71 | dout[1] = data; | |
72 | spi_xfer(enc->slave, 2 * 8, dout, NULL, | |
73 | SPI_XFER_BEGIN | SPI_XFER_END); | |
74 | } | |
75 | ||
76 | static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data) | |
77 | { | |
78 | u8 dout[2]; | |
79 | ||
80 | dout[0] = CMD_BFC(reg); | |
81 | dout[1] = data; | |
82 | spi_xfer(enc->slave, 2 * 8, dout, NULL, | |
83 | SPI_XFER_BEGIN | SPI_XFER_END); | |
84 | } | |
85 | ||
86 | /* | |
87 | * high byte of the register contains bank number: | |
88 | * 0: no bank switch necessary | |
89 | * 1: switch to bank 0 | |
90 | * 2: switch to bank 1 | |
91 | * 3: switch to bank 2 | |
92 | * 4: switch to bank 3 | |
93 | */ | |
94 | static void enc_set_bank(enc_dev_t *enc, const u16 reg) | |
95 | { | |
96 | u8 newbank = reg >> 8; | |
97 | ||
98 | if (newbank == 0 || newbank == enc->bank) | |
99 | return; | |
100 | switch (newbank) { | |
101 | case 1: | |
102 | enc_bclr(enc, CTL_REG_ECON1, | |
103 | ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); | |
104 | break; | |
105 | case 2: | |
106 | enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); | |
107 | enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); | |
108 | break; | |
109 | case 3: | |
110 | enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0); | |
111 | enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1); | |
112 | break; | |
113 | case 4: | |
114 | enc_bset(enc, CTL_REG_ECON1, | |
115 | ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1); | |
116 | break; | |
117 | } | |
118 | enc->bank = newbank; | |
119 | } | |
120 | ||
121 | /* | |
122 | * local functions to access SPI | |
123 | * | |
124 | * reg: register inside ENC28J60 | |
125 | * data: 8/16 bits to write | |
126 | * c: number of retries | |
127 | * | |
128 | * enc_r8: read 8 bits | |
129 | * enc_r16: read 16 bits | |
130 | * enc_w8: write 8 bits | |
131 | * enc_w16: write 16 bits | |
132 | * enc_w8_retry: write 8 bits, verify and retry | |
133 | * enc_rbuf: read from ENC28J60 into buffer | |
134 | * enc_wbuf: write from buffer into ENC28J60 | |
135 | */ | |
136 | ||
137 | /* | |
138 | * MAC and MII registers need a 3 byte SPI transfer to read, | |
139 | * all other registers need a 2 byte SPI transfer. | |
140 | */ | |
141 | static int enc_reg2nbytes(const u16 reg) | |
142 | { | |
143 | /* check if MAC or MII register */ | |
144 | return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) || | |
145 | (reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) || | |
146 | (reg == CTL_REG_MISTAT)) ? 3 : 2; | |
147 | } | |
148 | ||
149 | /* | |
150 | * Read a byte register | |
151 | */ | |
152 | static u8 enc_r8(enc_dev_t *enc, const u16 reg) | |
153 | { | |
154 | u8 dout[3]; | |
155 | u8 din[3]; | |
156 | int nbytes = enc_reg2nbytes(reg); | |
157 | ||
158 | enc_set_bank(enc, reg); | |
159 | dout[0] = CMD_RCR(reg); | |
160 | spi_xfer(enc->slave, nbytes * 8, dout, din, | |
161 | SPI_XFER_BEGIN | SPI_XFER_END); | |
162 | return din[nbytes-1]; | |
163 | } | |
164 | ||
165 | /* | |
166 | * Read a L/H register pair and return a word. | |
167 | * Must be called with the L register's address. | |
168 | */ | |
169 | static u16 enc_r16(enc_dev_t *enc, const u16 reg) | |
170 | { | |
171 | u8 dout[3]; | |
172 | u8 din[3]; | |
173 | u16 result; | |
174 | int nbytes = enc_reg2nbytes(reg); | |
175 | ||
176 | enc_set_bank(enc, reg); | |
177 | dout[0] = CMD_RCR(reg); | |
178 | spi_xfer(enc->slave, nbytes * 8, dout, din, | |
179 | SPI_XFER_BEGIN | SPI_XFER_END); | |
180 | result = din[nbytes-1]; | |
181 | dout[0]++; /* next register */ | |
182 | spi_xfer(enc->slave, nbytes * 8, dout, din, | |
183 | SPI_XFER_BEGIN | SPI_XFER_END); | |
184 | result |= din[nbytes-1] << 8; | |
185 | return result; | |
186 | } | |
187 | ||
188 | /* | |
189 | * Write a byte register | |
190 | */ | |
191 | static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data) | |
192 | { | |
193 | u8 dout[2]; | |
194 | ||
195 | enc_set_bank(enc, reg); | |
196 | dout[0] = CMD_WCR(reg); | |
197 | dout[1] = data; | |
198 | spi_xfer(enc->slave, 2 * 8, dout, NULL, | |
199 | SPI_XFER_BEGIN | SPI_XFER_END); | |
200 | } | |
201 | ||
202 | /* | |
203 | * Write a L/H register pair. | |
204 | * Must be called with the L register's address. | |
205 | */ | |
206 | static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data) | |
207 | { | |
208 | u8 dout[2]; | |
209 | ||
210 | enc_set_bank(enc, reg); | |
211 | dout[0] = CMD_WCR(reg); | |
212 | dout[1] = data; | |
213 | spi_xfer(enc->slave, 2 * 8, dout, NULL, | |
214 | SPI_XFER_BEGIN | SPI_XFER_END); | |
215 | dout[0]++; /* next register */ | |
216 | dout[1] = data >> 8; | |
217 | spi_xfer(enc->slave, 2 * 8, dout, NULL, | |
218 | SPI_XFER_BEGIN | SPI_XFER_END); | |
219 | } | |
220 | ||
221 | /* | |
222 | * Write a byte register, verify and retry | |
223 | */ | |
224 | static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c) | |
225 | { | |
226 | u8 dout[2]; | |
227 | u8 readback; | |
228 | int i; | |
229 | ||
230 | enc_set_bank(enc, reg); | |
231 | for (i = 0; i < c; i++) { | |
232 | dout[0] = CMD_WCR(reg); | |
233 | dout[1] = data; | |
234 | spi_xfer(enc->slave, 2 * 8, dout, NULL, | |
235 | SPI_XFER_BEGIN | SPI_XFER_END); | |
236 | readback = enc_r8(enc, reg); | |
237 | if (readback == data) | |
238 | break; | |
239 | /* wait 1ms */ | |
240 | udelay(1000); | |
241 | } | |
242 | if (i == c) { | |
243 | printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg); | |
244 | } | |
245 | } | |
246 | ||
247 | /* | |
248 | * Read ENC RAM into buffer | |
249 | */ | |
250 | static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf) | |
251 | { | |
252 | u8 dout[1]; | |
253 | ||
254 | dout[0] = CMD_RBM; | |
255 | spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN); | |
256 | spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END); | |
257 | #ifdef DEBUG | |
258 | puts("Rx:\n"); | |
259 | print_buffer(0, buf, 1, length, 0); | |
260 | #endif | |
261 | } | |
262 | ||
263 | /* | |
264 | * Write buffer into ENC RAM | |
265 | */ | |
266 | static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control) | |
267 | { | |
268 | u8 dout[2]; | |
269 | dout[0] = CMD_WBM; | |
270 | dout[1] = control; | |
271 | spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN); | |
272 | spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END); | |
273 | #ifdef DEBUG | |
274 | puts("Tx:\n"); | |
275 | print_buffer(0, buf, 1, length, 0); | |
276 | #endif | |
277 | } | |
278 | ||
279 | /* | |
280 | * Try to claim the SPI bus. | |
281 | * Print error message on failure. | |
282 | */ | |
283 | static int enc_claim_bus(enc_dev_t *enc) | |
284 | { | |
285 | int rc = spi_claim_bus(enc->slave); | |
286 | if (rc) | |
287 | printf("%s: failed to claim SPI bus\n", enc->dev->name); | |
288 | return rc; | |
289 | } | |
290 | ||
291 | /* | |
292 | * Release previously claimed SPI bus. | |
293 | * This function is mainly for symmetry to enc_claim_bus(). | |
294 | * Let the toolchain decide to inline it... | |
295 | */ | |
296 | static void enc_release_bus(enc_dev_t *enc) | |
297 | { | |
298 | spi_release_bus(enc->slave); | |
299 | } | |
300 | ||
301 | /* | |
302 | * Read PHY register | |
303 | */ | |
09c04c20 | 304 | static u16 enc_phy_read(enc_dev_t *enc, const u8 addr) |
a61a8196 RM |
305 | { |
306 | uint64_t etime; | |
307 | u8 status; | |
308 | ||
309 | enc_w8(enc, CTL_REG_MIREGADR, addr); | |
310 | enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD); | |
311 | /* 1 second timeout - only happens on hardware problem */ | |
312 | etime = get_ticks() + get_tbclk(); | |
313 | /* poll MISTAT.BUSY bit until operation is complete */ | |
314 | do | |
315 | { | |
316 | status = enc_r8(enc, CTL_REG_MISTAT); | |
317 | } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); | |
318 | if (status & ENC_MISTAT_BUSY) { | |
319 | printf("%s: timeout reading phy\n", enc->dev->name); | |
320 | return 0; | |
321 | } | |
322 | enc_w8(enc, CTL_REG_MICMD, 0); | |
323 | return enc_r16(enc, CTL_REG_MIRDL); | |
324 | } | |
325 | ||
326 | /* | |
327 | * Write PHY register | |
328 | */ | |
09c04c20 | 329 | static void enc_phy_write(enc_dev_t *enc, const u8 addr, const u16 data) |
a61a8196 RM |
330 | { |
331 | uint64_t etime; | |
332 | u8 status; | |
333 | ||
334 | enc_w8(enc, CTL_REG_MIREGADR, addr); | |
335 | enc_w16(enc, CTL_REG_MIWRL, data); | |
336 | /* 1 second timeout - only happens on hardware problem */ | |
337 | etime = get_ticks() + get_tbclk(); | |
338 | /* poll MISTAT.BUSY bit until operation is complete */ | |
339 | do | |
340 | { | |
341 | status = enc_r8(enc, CTL_REG_MISTAT); | |
342 | } while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY)); | |
343 | if (status & ENC_MISTAT_BUSY) { | |
344 | printf("%s: timeout writing phy\n", enc->dev->name); | |
345 | return; | |
346 | } | |
347 | } | |
348 | ||
349 | /* | |
350 | * Verify link status, wait if necessary | |
351 | * | |
352 | * Note: with a 10 MBit/s only PHY there is no autonegotiation possible, | |
353 | * half/full duplex is a pure setup matter. For the time being, this driver | |
354 | * will setup in half duplex mode only. | |
355 | */ | |
356 | static int enc_phy_link_wait(enc_dev_t *enc) | |
357 | { | |
358 | u16 status; | |
359 | int duplex; | |
360 | uint64_t etime; | |
361 | ||
362 | #ifdef CONFIG_ENC_SILENTLINK | |
363 | /* check if we have a link, then just return */ | |
09c04c20 | 364 | status = enc_phy_read(enc, PHY_REG_PHSTAT1); |
a61a8196 RM |
365 | if (status & ENC_PHSTAT1_LLSTAT) |
366 | return 0; | |
367 | #endif | |
368 | ||
369 | /* wait for link with 1 second timeout */ | |
370 | etime = get_ticks() + get_tbclk(); | |
371 | while (get_ticks() <= etime) { | |
09c04c20 | 372 | status = enc_phy_read(enc, PHY_REG_PHSTAT1); |
a61a8196 RM |
373 | if (status & ENC_PHSTAT1_LLSTAT) { |
374 | /* now we have a link */ | |
09c04c20 | 375 | status = enc_phy_read(enc, PHY_REG_PHSTAT2); |
a61a8196 RM |
376 | duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0; |
377 | printf("%s: link up, 10Mbps %s-duplex\n", | |
378 | enc->dev->name, duplex ? "full" : "half"); | |
379 | return 0; | |
380 | } | |
381 | udelay(1000); | |
382 | } | |
383 | ||
eae4b2b6 | 384 | /* timeout occurred */ |
a61a8196 RM |
385 | printf("%s: link down\n", enc->dev->name); |
386 | return 1; | |
387 | } | |
388 | ||
389 | /* | |
390 | * This function resets the receiver only. | |
391 | */ | |
392 | static void enc_reset_rx(enc_dev_t *enc) | |
393 | { | |
394 | u8 econ1; | |
395 | ||
396 | econ1 = enc_r8(enc, CTL_REG_ECON1); | |
397 | if ((econ1 & ENC_ECON1_RXRST) == 0) { | |
398 | enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); | |
399 | enc->rx_reset_counter = RX_RESET_COUNTER; | |
400 | } | |
401 | } | |
402 | ||
403 | /* | |
404 | * Reset receiver and reenable it. | |
405 | */ | |
406 | static void enc_reset_rx_call(enc_dev_t *enc) | |
407 | { | |
408 | enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST); | |
409 | enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); | |
410 | } | |
411 | ||
412 | /* | |
413 | * Copy a packet from the receive ring and forward it to | |
414 | * the protocol stack. | |
415 | */ | |
416 | static void enc_receive(enc_dev_t *enc) | |
417 | { | |
1fd92db8 | 418 | u8 *packet = (u8 *)net_rx_packets[0]; |
a61a8196 RM |
419 | u16 pkt_len; |
420 | u16 copy_len; | |
421 | u16 status; | |
a61a8196 RM |
422 | u8 pkt_cnt = 0; |
423 | u16 rxbuf_rdpt; | |
424 | u8 hbuf[6]; | |
425 | ||
426 | enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); | |
427 | do { | |
428 | enc_rbuf(enc, 6, hbuf); | |
429 | enc->next_pointer = hbuf[0] | (hbuf[1] << 8); | |
430 | pkt_len = hbuf[2] | (hbuf[3] << 8); | |
431 | status = hbuf[4] | (hbuf[5] << 8); | |
432 | debug("next_pointer=$%04x pkt_len=%u status=$%04x\n", | |
433 | enc->next_pointer, pkt_len, status); | |
434 | if (pkt_len <= ENC_MAX_FRM_LEN) | |
435 | copy_len = pkt_len; | |
436 | else | |
437 | copy_len = 0; | |
438 | if ((status & (1L << 7)) == 0) /* check Received Ok bit */ | |
439 | copy_len = 0; | |
440 | /* check if next pointer is resonable */ | |
441 | if (enc->next_pointer >= ENC_TX_BUF_START) | |
442 | copy_len = 0; | |
443 | if (copy_len > 0) { | |
444 | enc_rbuf(enc, copy_len, packet); | |
445 | } | |
446 | /* advance read pointer to next pointer */ | |
447 | enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer); | |
448 | /* decrease packet counter */ | |
449 | enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC); | |
450 | /* | |
451 | * Only odd values should be written to ERXRDPTL, | |
452 | * see errata B4 pt.13 | |
453 | */ | |
454 | rxbuf_rdpt = enc->next_pointer - 1; | |
455 | if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) || | |
456 | (rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) { | |
457 | enc_w16(enc, CTL_REG_ERXRDPTL, | |
458 | enc_r16(enc, CTL_REG_ERXNDL)); | |
459 | } else { | |
460 | enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt); | |
461 | } | |
462 | /* read pktcnt */ | |
463 | pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); | |
464 | if (copy_len == 0) { | |
da540665 | 465 | (void)enc_r8(enc, CTL_REG_EIR); |
a61a8196 RM |
466 | enc_reset_rx(enc); |
467 | printf("%s: receive copy_len=0\n", enc->dev->name); | |
468 | continue; | |
469 | } | |
470 | /* | |
1fd92db8 JH |
471 | * Because net_process_received_packet() might call enc_send(), |
472 | * we need to release the SPI bus, call | |
473 | * net_process_received_packet(), reclaim the bus. | |
a61a8196 RM |
474 | */ |
475 | enc_release_bus(enc); | |
1fd92db8 | 476 | net_process_received_packet(packet, pkt_len); |
a61a8196 RM |
477 | if (enc_claim_bus(enc)) |
478 | return; | |
da540665 | 479 | (void)enc_r8(enc, CTL_REG_EIR); |
a61a8196 RM |
480 | } while (pkt_cnt); |
481 | /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ | |
482 | } | |
483 | ||
484 | /* | |
485 | * Poll for completely received packets. | |
486 | */ | |
487 | static void enc_poll(enc_dev_t *enc) | |
488 | { | |
489 | u8 eir_reg; | |
a61a8196 RM |
490 | u8 pkt_cnt; |
491 | ||
da540665 | 492 | (void)enc_r8(enc, CTL_REG_ESTAT); |
a61a8196 RM |
493 | eir_reg = enc_r8(enc, CTL_REG_EIR); |
494 | if (eir_reg & ENC_EIR_TXIF) { | |
495 | /* clear TXIF bit in EIR */ | |
496 | enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF); | |
497 | } | |
498 | /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ | |
499 | pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT); | |
500 | if (pkt_cnt > 0) { | |
501 | if ((eir_reg & ENC_EIR_PKTIF) == 0) { | |
502 | debug("enc_poll: pkt cnt > 0, but pktif not set\n"); | |
503 | } | |
504 | enc_receive(enc); | |
505 | /* | |
506 | * clear PKTIF bit in EIR, this should not need to be done | |
507 | * but it seems like we get problems if we do not | |
508 | */ | |
509 | enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF); | |
510 | } | |
511 | if (eir_reg & ENC_EIR_RXERIF) { | |
512 | printf("%s: rx error\n", enc->dev->name); | |
513 | enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF); | |
514 | } | |
515 | if (eir_reg & ENC_EIR_TXERIF) { | |
516 | printf("%s: tx error\n", enc->dev->name); | |
517 | enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF); | |
518 | } | |
a61a8196 RM |
519 | } |
520 | ||
521 | /* | |
522 | * Completely Reset the ENC | |
523 | */ | |
524 | static void enc_reset(enc_dev_t *enc) | |
525 | { | |
526 | u8 dout[1]; | |
527 | ||
528 | dout[0] = CMD_SRC; | |
529 | spi_xfer(enc->slave, 8, dout, NULL, | |
530 | SPI_XFER_BEGIN | SPI_XFER_END); | |
531 | /* sleep 1 ms. See errata pt. 2 */ | |
532 | udelay(1000); | |
533 | } | |
534 | ||
535 | /* | |
536 | * Initialisation data for most of the ENC registers | |
537 | */ | |
538 | static const u16 enc_initdata[] = { | |
539 | /* | |
540 | * Setup the buffer space. The reset values are valid for the | |
541 | * other pointers. | |
542 | * | |
543 | * We shall not write to ERXST, see errata pt. 5. Instead we | |
544 | * have to make sure that ENC_RX_BUS_START is 0. | |
545 | */ | |
546 | CTL_REG_ERXSTL, ENC_RX_BUF_START, | |
547 | CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8, | |
548 | CTL_REG_ERXNDL, ENC_RX_BUF_END, | |
549 | CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8, | |
550 | CTL_REG_ERDPTL, ENC_RX_BUF_START, | |
551 | CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8, | |
552 | /* | |
553 | * Set the filter to receive only good-CRC, unicast and broadcast | |
554 | * frames. | |
555 | * Note: some DHCP servers return their answers as broadcasts! | |
556 | * So its unwise to remove broadcast from this. This driver | |
557 | * might incur receiver overruns with packet loss on a broadcast | |
558 | * flooded network. | |
559 | */ | |
560 | CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN, | |
561 | ||
562 | /* enable MAC to receive frames */ | |
563 | CTL_REG_MACON1, | |
564 | ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS, | |
565 | ||
566 | /* configure pad, tx-crc and duplex */ | |
567 | CTL_REG_MACON3, | |
568 | ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | | |
569 | ENC_MACON3_FRMLNEN, | |
570 | ||
571 | /* Allow infinite deferals if the medium is continously busy */ | |
572 | CTL_REG_MACON4, ENC_MACON4_DEFER, | |
573 | ||
574 | /* Late collisions occur beyond 63 bytes */ | |
575 | CTL_REG_MACLCON2, 63, | |
576 | ||
577 | /* | |
578 | * Set (low byte) Non-Back-to_Back Inter-Packet Gap. | |
579 | * Recommended 0x12 | |
580 | */ | |
581 | CTL_REG_MAIPGL, 0x12, | |
582 | ||
583 | /* | |
584 | * Set (high byte) Non-Back-to_Back Inter-Packet Gap. | |
585 | * Recommended 0x0c for half-duplex. Nothing for full-duplex | |
586 | */ | |
587 | CTL_REG_MAIPGH, 0x0C, | |
588 | ||
589 | /* set maximum frame length */ | |
590 | CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN, | |
591 | CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8, | |
592 | ||
593 | /* | |
594 | * Set MAC back-to-back inter-packet gap. | |
595 | * Recommended 0x12 for half duplex | |
596 | * and 0x15 for full duplex. | |
597 | */ | |
598 | CTL_REG_MABBIPG, 0x12, | |
599 | ||
600 | /* end of table */ | |
601 | 0xffff | |
602 | }; | |
603 | ||
604 | /* | |
605 | * Wait for the XTAL oscillator to become ready | |
606 | */ | |
607 | static int enc_clock_wait(enc_dev_t *enc) | |
608 | { | |
609 | uint64_t etime; | |
610 | ||
611 | /* one second timeout */ | |
612 | etime = get_ticks() + get_tbclk(); | |
613 | ||
614 | /* | |
615 | * Wait for CLKRDY to become set (i.e., check that we can | |
616 | * communicate with the ENC) | |
617 | */ | |
618 | do | |
619 | { | |
620 | if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) | |
621 | return 0; | |
622 | } while (get_ticks() <= etime); | |
623 | ||
624 | printf("%s: timeout waiting for CLKRDY\n", enc->dev->name); | |
625 | return -1; | |
626 | } | |
627 | ||
628 | /* | |
629 | * Write the MAC address into the ENC | |
630 | */ | |
631 | static int enc_write_macaddr(enc_dev_t *enc) | |
632 | { | |
633 | unsigned char *p = enc->dev->enetaddr; | |
634 | ||
635 | enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5); | |
636 | enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5); | |
637 | enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5); | |
638 | enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5); | |
639 | enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5); | |
640 | enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5); | |
641 | return 0; | |
642 | } | |
643 | ||
644 | /* | |
645 | * Setup most of the ENC registers | |
646 | */ | |
647 | static int enc_setup(enc_dev_t *enc) | |
648 | { | |
649 | u16 phid1 = 0; | |
650 | u16 phid2 = 0; | |
651 | const u16 *tp; | |
652 | ||
653 | /* reset enc struct values */ | |
654 | enc->next_pointer = ENC_RX_BUF_START; | |
655 | enc->rx_reset_counter = RX_RESET_COUNTER; | |
656 | enc->bank = 0xff; /* invalidate current bank in enc28j60 */ | |
657 | ||
658 | /* verify PHY identification */ | |
09c04c20 AF |
659 | phid1 = enc_phy_read(enc, PHY_REG_PHID1); |
660 | phid2 = enc_phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK; | |
a61a8196 RM |
661 | if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) { |
662 | printf("%s: failed to identify PHY. Found %04x:%04x\n", | |
663 | enc->dev->name, phid1, phid2); | |
664 | return -1; | |
665 | } | |
666 | ||
667 | /* now program registers */ | |
668 | for (tp = enc_initdata; *tp != 0xffff; tp += 2) | |
669 | enc_w8_retry(enc, tp[0], tp[1], 10); | |
670 | ||
671 | /* | |
672 | * Prevent automatic loopback of data beeing transmitted by setting | |
673 | * ENC_PHCON2_HDLDIS | |
674 | */ | |
09c04c20 | 675 | enc_phy_write(enc, PHY_REG_PHCON2, (1<<8)); |
a61a8196 RM |
676 | |
677 | /* | |
678 | * LEDs configuration | |
679 | * LEDA: LACFG = 0100 -> display link status | |
680 | * LEDB: LBCFG = 0111 -> display TX & RX activity | |
681 | * STRCH = 1 -> LED pulses | |
682 | */ | |
09c04c20 | 683 | enc_phy_write(enc, PHY_REG_PHLCON, 0x0472); |
a61a8196 RM |
684 | |
685 | /* Reset PDPXMD-bit => half duplex */ | |
09c04c20 | 686 | enc_phy_write(enc, PHY_REG_PHCON1, 0); |
a61a8196 | 687 | |
a61a8196 RM |
688 | return 0; |
689 | } | |
690 | ||
691 | /* | |
692 | * Check if ENC has been initialized. | |
693 | * If not, try to initialize it. | |
694 | * Remember initialized state in struct. | |
695 | */ | |
696 | static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate) | |
697 | { | |
698 | if (enc->initstate >= requiredstate) | |
699 | return 0; | |
700 | ||
701 | if (enc->initstate < setupdone) { | |
702 | /* Initialize the ENC only */ | |
703 | enc_reset(enc); | |
704 | /* if any of functions fails, skip the rest and return an error */ | |
705 | if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) { | |
706 | return -1; | |
707 | } | |
708 | enc->initstate = setupdone; | |
709 | } | |
710 | /* if that's all we need, return here */ | |
711 | if (enc->initstate >= requiredstate) | |
712 | return 0; | |
713 | ||
714 | /* now wait for link ready condition */ | |
715 | if (enc_phy_link_wait(enc)) { | |
716 | return -1; | |
717 | } | |
718 | enc->initstate = linkready; | |
719 | return 0; | |
720 | } | |
721 | ||
722 | #if defined(CONFIG_CMD_MII) | |
723 | /* | |
724 | * Read a PHY register. | |
725 | * | |
726 | * This function is registered with miiphy_register(). | |
727 | */ | |
5a49f174 | 728 | int enc_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) |
a61a8196 | 729 | { |
5a49f174 JH |
730 | u16 value = 0; |
731 | struct eth_device *dev = eth_get_dev_by_name(bus->name); | |
a61a8196 RM |
732 | enc_dev_t *enc; |
733 | ||
734 | if (!dev || phy_adr != 0) | |
735 | return -1; | |
736 | ||
737 | enc = dev->priv; | |
738 | if (enc_claim_bus(enc)) | |
739 | return -1; | |
740 | if (enc_initcheck(enc, setupdone)) { | |
741 | enc_release_bus(enc); | |
742 | return -1; | |
743 | } | |
5a49f174 | 744 | value = enc_phy_read(enc, reg); |
a61a8196 | 745 | enc_release_bus(enc); |
5a49f174 | 746 | return value; |
a61a8196 RM |
747 | } |
748 | ||
749 | /* | |
750 | * Write a PHY register. | |
751 | * | |
752 | * This function is registered with miiphy_register(). | |
753 | */ | |
5a49f174 JH |
754 | int enc_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg, |
755 | u16 value) | |
a61a8196 | 756 | { |
5a49f174 | 757 | struct eth_device *dev = eth_get_dev_by_name(bus->name); |
a61a8196 RM |
758 | enc_dev_t *enc; |
759 | ||
760 | if (!dev || phy_adr != 0) | |
761 | return -1; | |
762 | ||
763 | enc = dev->priv; | |
764 | if (enc_claim_bus(enc)) | |
765 | return -1; | |
766 | if (enc_initcheck(enc, setupdone)) { | |
767 | enc_release_bus(enc); | |
768 | return -1; | |
769 | } | |
09c04c20 | 770 | enc_phy_write(enc, reg, value); |
a61a8196 RM |
771 | enc_release_bus(enc); |
772 | return 0; | |
773 | } | |
774 | #endif | |
775 | ||
776 | /* | |
777 | * Write hardware (MAC) address. | |
778 | * | |
779 | * This function entered into eth_device structure. | |
780 | */ | |
781 | static int enc_write_hwaddr(struct eth_device *dev) | |
782 | { | |
783 | enc_dev_t *enc = dev->priv; | |
784 | ||
785 | if (enc_claim_bus(enc)) | |
786 | return -1; | |
787 | if (enc_initcheck(enc, setupdone)) { | |
788 | enc_release_bus(enc); | |
789 | return -1; | |
790 | } | |
791 | enc_release_bus(enc); | |
792 | return 0; | |
793 | } | |
794 | ||
795 | /* | |
796 | * Initialize ENC28J60 for use. | |
797 | * | |
798 | * This function entered into eth_device structure. | |
799 | */ | |
800 | static int enc_init(struct eth_device *dev, bd_t *bis) | |
801 | { | |
802 | enc_dev_t *enc = dev->priv; | |
803 | ||
804 | if (enc_claim_bus(enc)) | |
805 | return -1; | |
806 | if (enc_initcheck(enc, linkready)) { | |
807 | enc_release_bus(enc); | |
808 | return -1; | |
809 | } | |
810 | /* enable receive */ | |
811 | enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); | |
812 | enc_release_bus(enc); | |
813 | return 0; | |
814 | } | |
815 | ||
816 | /* | |
817 | * Check for received packets. | |
818 | * | |
819 | * This function entered into eth_device structure. | |
820 | */ | |
821 | static int enc_recv(struct eth_device *dev) | |
822 | { | |
823 | enc_dev_t *enc = dev->priv; | |
824 | ||
825 | if (enc_claim_bus(enc)) | |
826 | return -1; | |
827 | if (enc_initcheck(enc, linkready)) { | |
828 | enc_release_bus(enc); | |
829 | return -1; | |
830 | } | |
831 | /* Check for dead receiver */ | |
832 | if (enc->rx_reset_counter > 0) | |
833 | enc->rx_reset_counter--; | |
834 | else | |
835 | enc_reset_rx_call(enc); | |
836 | enc_poll(enc); | |
837 | enc_release_bus(enc); | |
838 | return 0; | |
839 | } | |
840 | ||
841 | /* | |
842 | * Send a packet. | |
843 | * | |
844 | * This function entered into eth_device structure. | |
845 | * | |
846 | * Should we wait here until we have a Link? Or shall we leave that to | |
847 | * protocol retries? | |
848 | */ | |
849 | static int enc_send( | |
850 | struct eth_device *dev, | |
b58cab34 | 851 | void *packet, |
a61a8196 RM |
852 | int length) |
853 | { | |
854 | enc_dev_t *enc = dev->priv; | |
855 | ||
856 | if (enc_claim_bus(enc)) | |
857 | return -1; | |
858 | if (enc_initcheck(enc, linkready)) { | |
859 | enc_release_bus(enc); | |
860 | return -1; | |
861 | } | |
862 | /* setup transmit pointers */ | |
863 | enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START); | |
864 | enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START); | |
865 | enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START); | |
866 | /* write packet to ENC */ | |
867 | enc_wbuf(enc, length, (u8 *) packet, 0x00); | |
868 | /* | |
869 | * Check that the internal transmit logic has not been altered | |
870 | * by excessive collisions. Reset transmitter if so. | |
871 | * See Errata B4 12 and 14. | |
872 | */ | |
873 | if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) { | |
874 | enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); | |
875 | enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST); | |
876 | } | |
877 | enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); | |
878 | /* start transmitting */ | |
879 | enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS); | |
880 | enc_release_bus(enc); | |
881 | return 0; | |
882 | } | |
883 | ||
884 | /* | |
885 | * Finish use of ENC. | |
886 | * | |
887 | * This function entered into eth_device structure. | |
888 | */ | |
889 | static void enc_halt(struct eth_device *dev) | |
890 | { | |
891 | enc_dev_t *enc = dev->priv; | |
892 | ||
893 | if (enc_claim_bus(enc)) | |
894 | return; | |
895 | /* Just disable receiver */ | |
896 | enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN); | |
897 | enc_release_bus(enc); | |
898 | } | |
899 | ||
900 | /* | |
901 | * This is the only exported function. | |
902 | * | |
903 | * It may be called several times with different bus:cs combinations. | |
904 | */ | |
905 | int enc28j60_initialize(unsigned int bus, unsigned int cs, | |
906 | unsigned int max_hz, unsigned int mode) | |
907 | { | |
908 | struct eth_device *dev; | |
909 | enc_dev_t *enc; | |
910 | ||
911 | /* try to allocate, check and clear eth_device object */ | |
912 | dev = malloc(sizeof(*dev)); | |
913 | if (!dev) { | |
914 | return -1; | |
915 | } | |
916 | memset(dev, 0, sizeof(*dev)); | |
917 | ||
918 | /* try to allocate, check and clear enc_dev_t object */ | |
919 | enc = malloc(sizeof(*enc)); | |
920 | if (!enc) { | |
921 | free(dev); | |
922 | return -1; | |
923 | } | |
924 | memset(enc, 0, sizeof(*enc)); | |
925 | ||
926 | /* try to setup the SPI slave */ | |
927 | enc->slave = spi_setup_slave(bus, cs, max_hz, mode); | |
928 | if (!enc->slave) { | |
929 | printf("enc28j60: invalid SPI device %i:%i\n", bus, cs); | |
930 | free(enc); | |
931 | free(dev); | |
932 | return -1; | |
933 | } | |
934 | ||
935 | enc->dev = dev; | |
936 | /* now fill the eth_device object */ | |
937 | dev->priv = enc; | |
938 | dev->init = enc_init; | |
939 | dev->halt = enc_halt; | |
940 | dev->send = enc_send; | |
941 | dev->recv = enc_recv; | |
942 | dev->write_hwaddr = enc_write_hwaddr; | |
943 | sprintf(dev->name, "enc%i.%i", bus, cs); | |
944 | eth_register(dev); | |
945 | #if defined(CONFIG_CMD_MII) | |
5a49f174 JH |
946 | int retval; |
947 | struct mii_dev *mdiodev = mdio_alloc(); | |
948 | if (!mdiodev) | |
949 | return -ENOMEM; | |
950 | strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); | |
951 | mdiodev->read = enc_miiphy_read; | |
952 | mdiodev->write = enc_miiphy_write; | |
953 | ||
954 | retval = mdio_register(mdiodev); | |
955 | if (retval < 0) | |
956 | return retval; | |
a61a8196 RM |
957 | #endif |
958 | return 0; | |
959 | } |