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amd-xgbe: Add a workaround for Tx timestamp issue
[thirdparty/kernel/stable.git] / drivers / net / ethernet / amd / xgbe / xgbe-dev.c
CommitLineData
c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
b4eee84f 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
c5aa9e3b
LT		 10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
b4eee84f 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
c5aa9e3b
LT		 60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#include <linux/phy.h>
c3152d47 118#include <linux/mdio.h>
c5aa9e3b 119#include <linux/clk.h>
801c62d9 120#include <linux/bitrev.h>
b85e4d89 121#include <linux/crc32.h>
c5aa9e3b
LT		 122
123#include "xgbe.h"
124#include "xgbe-common.h"
125
43e0dcf7
LT		 126static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
127{
128 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
129}
130
c5aa9e3b
LT		 131static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
132 unsigned int usec)
133{
134 unsigned long rate;
135 unsigned int ret;
136
137 DBGPR("-->xgbe_usec_to_riwt\n");
138
82a19035 139 rate = pdata->sysclk_rate;
c5aa9e3b
LT		 140
141 /*
142 * Convert the input usec value to the watchdog timer value. Each
143 * watchdog timer value is equivalent to 256 clock cycles.
144 * Calculate the required value as:
145 * ( usec * ( system_clock_mhz / 10^6 ) / 256
146 */
147 ret = (usec * (rate / 1000000)) / 256;
148
149 DBGPR("<--xgbe_usec_to_riwt\n");
150
151 return ret;
152}
153
154static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
155 unsigned int riwt)
156{
157 unsigned long rate;
158 unsigned int ret;
159
160 DBGPR("-->xgbe_riwt_to_usec\n");
161
82a19035 162 rate = pdata->sysclk_rate;
c5aa9e3b
LT		 163
164 /*
165 * Convert the input watchdog timer value to the usec value. Each
166 * watchdog timer value is equivalent to 256 clock cycles.
167 * Calculate the required value as:
168 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
169 */
170 ret = (riwt * 256) / (rate / 1000000);
171
172 DBGPR("<--xgbe_riwt_to_usec\n");
173
174 return ret;
175}
176
177static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
178{
179 struct xgbe_channel *channel;
180 unsigned int i;
181
182 channel = pdata->channel;
183 for (i = 0; i < pdata->channel_count; i++, channel++)
184 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
185 pdata->pblx8);
186
187 return 0;
188}
189
190static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
191{
192 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
193}
194
195static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
196{
197 struct xgbe_channel *channel;
198 unsigned int i;
199
200 channel = pdata->channel;
201 for (i = 0; i < pdata->channel_count; i++, channel++) {
202 if (!channel->tx_ring)
203 break;
204
205 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
206 pdata->tx_pbl);
207 }
208
209 return 0;
210}
211
212static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
213{
214 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
215}
216
217static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
218{
219 struct xgbe_channel *channel;
220 unsigned int i;
221
222 channel = pdata->channel;
223 for (i = 0; i < pdata->channel_count; i++, channel++) {
224 if (!channel->rx_ring)
225 break;
226
227 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
228 pdata->rx_pbl);
229 }
230
231 return 0;
232}
233
234static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
235{
236 struct xgbe_channel *channel;
237 unsigned int i;
238
239 channel = pdata->channel;
240 for (i = 0; i < pdata->channel_count; i++, channel++) {
241 if (!channel->tx_ring)
242 break;
243
244 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
245 pdata->tx_osp_mode);
246 }
247
248 return 0;
249}
250
251static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
252{
253 unsigned int i;
254
853eb16b 255 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 256 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
257
258 return 0;
259}
260
261static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
262{
263 unsigned int i;
264
853eb16b 265 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 266 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
267
268 return 0;
269}
270
271static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
272 unsigned int val)
273{
274 unsigned int i;
275
853eb16b 276 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 277 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
278
279 return 0;
280}
281
282static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
283 unsigned int val)
284{
285 unsigned int i;
286
853eb16b 287 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 288 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
289
290 return 0;
291}
292
293static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
294{
295 struct xgbe_channel *channel;
296 unsigned int i;
297
298 channel = pdata->channel;
299 for (i = 0; i < pdata->channel_count; i++, channel++) {
300 if (!channel->rx_ring)
301 break;
302
303 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
304 pdata->rx_riwt);
305 }
306
307 return 0;
308}
309
310static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
311{
312 return 0;
313}
314
315static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
316{
317 struct xgbe_channel *channel;
318 unsigned int i;
319
320 channel = pdata->channel;
321 for (i = 0; i < pdata->channel_count; i++, channel++) {
322 if (!channel->rx_ring)
323 break;
324
325 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
326 pdata->rx_buf_size);
327 }
328}
329
330static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
331{
332 struct xgbe_channel *channel;
333 unsigned int i;
334
335 channel = pdata->channel;
336 for (i = 0; i < pdata->channel_count; i++, channel++) {
337 if (!channel->tx_ring)
338 break;
339
340 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
341 }
342}
343
174fd259
LT		 344static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
345{
346 struct xgbe_channel *channel;
347 unsigned int i;
348
349 channel = pdata->channel;
350 for (i = 0; i < pdata->channel_count; i++, channel++) {
351 if (!channel->rx_ring)
352 break;
353
354 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1);
355 }
356
357 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
358}
359
5b9dfe29
LT		 360static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
361 unsigned int index, unsigned int val)
362{
363 unsigned int wait;
364 int ret = 0;
365
366 mutex_lock(&pdata->rss_mutex);
367
368 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
369 ret = -EBUSY;
370 goto unlock;
371 }
372
373 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
374
375 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
376 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
377 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
378 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
379
380 wait = 1000;
381 while (wait--) {
382 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
383 goto unlock;
384
385 usleep_range(1000, 1500);
386 }
387
388 ret = -EBUSY;
389
390unlock:
391 mutex_unlock(&pdata->rss_mutex);
392
393 return ret;
394}
395
396static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
397{
398 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
399 unsigned int *key = (unsigned int *)&pdata->rss_key;
400 int ret;
401
402 while (key_regs--) {
403 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
404 key_regs, *key++);
405 if (ret)
406 return ret;
407 }
408
409 return 0;
410}
411
412static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
413{
414 unsigned int i;
415 int ret;
416
417 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
418 ret = xgbe_write_rss_reg(pdata,
419 XGBE_RSS_LOOKUP_TABLE_TYPE, i,
420 pdata->rss_table[i]);
421 if (ret)
422 return ret;
423 }
424
425 return 0;
426}
427
f6ac8628
LT		 428static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
429{
430 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
431
432 return xgbe_write_rss_hash_key(pdata);
433}
434
435static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
436 const u32 *table)
437{
438 unsigned int i;
439
440 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
441 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
442
443 return xgbe_write_rss_lookup_table(pdata);
444}
445
5b9dfe29
LT		 446static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
447{
448 int ret;
449
450 if (!pdata->hw_feat.rss)
451 return -EOPNOTSUPP;
452
453 /* Program the hash key */
454 ret = xgbe_write_rss_hash_key(pdata);
455 if (ret)
456 return ret;
457
458 /* Program the lookup table */
459 ret = xgbe_write_rss_lookup_table(pdata);
460 if (ret)
461 return ret;
462
463 /* Set the RSS options */
464 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
465
466 /* Enable RSS */
467 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
468
469 return 0;
470}
471
472static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
473{
474 if (!pdata->hw_feat.rss)
475 return -EOPNOTSUPP;
476
477 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
478
479 return 0;
480}
481
482static void xgbe_config_rss(struct xgbe_prv_data *pdata)
483{
484 int ret;
485
486 if (!pdata->hw_feat.rss)
487 return;
488
489 if (pdata->netdev->features & NETIF_F_RXHASH)
490 ret = xgbe_enable_rss(pdata);
491 else
492 ret = xgbe_disable_rss(pdata);
493
494 if (ret)
495 netdev_err(pdata->netdev,
496 "error configuring RSS, RSS disabled\n");
497}
498
43e0dcf7
LT		 499static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata,
500 unsigned int queue)
501{
502 unsigned int prio, tc;
503
504 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
505 /* Does this queue handle the priority? */
506 if (pdata->prio2q_map[prio] != queue)
507 continue;
508
509 /* Get the Traffic Class for this priority */
510 tc = pdata->ets->prio_tc[prio];
511
512 /* Check if PFC is enabled for this traffic class */
513 if (pdata->pfc->pfc_en & (1 << tc))
514 return true;
515 }
516
517 return false;
518}
519
c5aa9e3b
LT		 520static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
521{
522 unsigned int max_q_count, q_count;
523 unsigned int reg, reg_val;
524 unsigned int i;
525
526 /* Clear MTL flow control */
853eb16b 527 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 528 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
529
530 /* Clear MAC flow control */
531 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
9fc69aff 532 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
c5aa9e3b
LT		 533 reg = MAC_Q0TFCR;
534 for (i = 0; i < q_count; i++) {
535 reg_val = XGMAC_IOREAD(pdata, reg);
536 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
537 XGMAC_IOWRITE(pdata, reg, reg_val);
538
539 reg += MAC_QTFCR_INC;
540 }
541
542 return 0;
543}
544
545static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
546{
8dba2a2a
LT		 547 struct ieee_pfc *pfc = pdata->pfc;
548 struct ieee_ets *ets = pdata->ets;
c5aa9e3b
LT		 549 unsigned int max_q_count, q_count;
550 unsigned int reg, reg_val;
551 unsigned int i;
552
553 /* Set MTL flow control */
8dba2a2a
LT		 554 for (i = 0; i < pdata->rx_q_count; i++) {
555 unsigned int ehfc = 0;
556
43e0dcf7
LT		 557 if (pdata->rx_rfd[i]) {
558 /* Flow control thresholds are established */
559 if (pfc && ets) {
560 if (xgbe_is_pfc_queue(pdata, i))
8dba2a2a 561 ehfc = 1;
43e0dcf7
LT		 562 } else {
563 ehfc = 1;
8dba2a2a 564 }
8dba2a2a
LT		 565 }
566
567 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc);
568
569 netif_dbg(pdata, drv, pdata->netdev,
570 "flow control %s for RXq%u\n",
571 ehfc ? "enabled" : "disabled", i);
572 }
c5aa9e3b
LT		 573
574 /* Set MAC flow control */
575 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
9fc69aff 576 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
c5aa9e3b
LT		 577 reg = MAC_Q0TFCR;
578 for (i = 0; i < q_count; i++) {
579 reg_val = XGMAC_IOREAD(pdata, reg);
580
581 /* Enable transmit flow control */
582 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
583 /* Set pause time */
584 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
585
586 XGMAC_IOWRITE(pdata, reg, reg_val);
587
588 reg += MAC_QTFCR_INC;
589 }
590
591 return 0;
592}
593
594static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
595{
596 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
597
598 return 0;
599}
600
601static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
602{
603 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
604
605 return 0;
606}
607
608static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
609{
fca2d994
LT		 610 struct ieee_pfc *pfc = pdata->pfc;
611
612 if (pdata->tx_pause || (pfc && pfc->pfc_en))
c5aa9e3b
LT		 613 xgbe_enable_tx_flow_control(pdata);
614 else
615 xgbe_disable_tx_flow_control(pdata);
616
617 return 0;
618}
619
620static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
621{
fca2d994
LT		 622 struct ieee_pfc *pfc = pdata->pfc;
623
624 if (pdata->rx_pause || (pfc && pfc->pfc_en))
c5aa9e3b
LT		 625 xgbe_enable_rx_flow_control(pdata);
626 else
627 xgbe_disable_rx_flow_control(pdata);
628
629 return 0;
630}
631
632static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
633{
fca2d994
LT		 634 struct ieee_pfc *pfc = pdata->pfc;
635
c5aa9e3b
LT		 636 xgbe_config_tx_flow_control(pdata);
637 xgbe_config_rx_flow_control(pdata);
fca2d994
LT		 638
639 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
640 (pfc && pfc->pfc_en) ? 1 : 0);
c5aa9e3b
LT		 641}
642
643static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
644{
645 struct xgbe_channel *channel;
646 unsigned int dma_ch_isr, dma_ch_ier;
647 unsigned int i;
648
649 channel = pdata->channel;
650 for (i = 0; i < pdata->channel_count; i++, channel++) {
651 /* Clear all the interrupts which are set */
652 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
653 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
654
655 /* Clear all interrupt enable bits */
656 dma_ch_ier = 0;
657
658 /* Enable following interrupts
659 * NIE - Normal Interrupt Summary Enable
660 * AIE - Abnormal Interrupt Summary Enable
661 * FBEE - Fatal Bus Error Enable
662 */
663 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
664 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
665 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
666
667 if (channel->tx_ring) {
668 /* Enable the following Tx interrupts
9227dc5e
LT		 669 * TIE - Transmit Interrupt Enable (unless using
670 * per channel interrupts)
c5aa9e3b 671 */
9227dc5e
LT		 672 if (!pdata->per_channel_irq)
673 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
c5aa9e3b
LT		 674 }
675 if (channel->rx_ring) {
676 /* Enable following Rx interrupts
677 * RBUE - Receive Buffer Unavailable Enable
9227dc5e
LT		 678 * RIE - Receive Interrupt Enable (unless using
679 * per channel interrupts)
c5aa9e3b
LT		 680 */
681 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
9227dc5e
LT		 682 if (!pdata->per_channel_irq)
683 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
c5aa9e3b
LT		 684 }
685
686 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
687 }
688}
689
690static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
691{
692 unsigned int mtl_q_isr;
693 unsigned int q_count, i;
694
695 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
696 for (i = 0; i < q_count; i++) {
697 /* Clear all the interrupts which are set */
698 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
699 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
700
701 /* No MTL interrupts to be enabled */
91f87345 702 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
c5aa9e3b
LT		 703 }
704}
705
706static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
707{
23e4eef7
LT		 708 unsigned int mac_ier = 0;
709
710 /* Enable Timestamp interrupt */
711 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
712
713 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
c5aa9e3b
LT		 714
715 /* Enable all counter interrupts */
a3ba7c98
LT		 716 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
717 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
c5aa9e3b
LT		 718}
719
e57f7a3f 720static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
c5aa9e3b 721{
e57f7a3f 722 unsigned int ss;
c3152d47 723
e57f7a3f
LT		 724 switch (speed) {
725 case SPEED_1000:
726 ss = 0x03;
727 break;
728 case SPEED_2500:
729 ss = 0x02;
730 break;
731 case SPEED_10000:
732 ss = 0x00;
733 break;
734 default:
735 return -EINVAL;
736 }
c3152d47 737
e57f7a3f
LT		 738 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss)
739 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss);
c5aa9e3b
LT		 740
741 return 0;
742}
743
b4eee84f
LT		 744static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
745{
746 /* Put the VLAN tag in the Rx descriptor */
747 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
748
749 /* Don't check the VLAN type */
750 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
751
752 /* Check only C-TAG (0x8100) packets */
753 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
754
755 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
756 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
757
758 /* Enable VLAN tag stripping */
759 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
760
761 return 0;
762}
763
764static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
765{
766 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
767
768 return 0;
769}
770
771static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
772{
773 /* Enable VLAN filtering */
774 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
775
776 /* Enable VLAN Hash Table filtering */
777 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
778
779 /* Disable VLAN tag inverse matching */
780 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
781
782 /* Only filter on the lower 12-bits of the VLAN tag */
783 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
784
785 /* In order for the VLAN Hash Table filtering to be effective,
786 * the VLAN tag identifier in the VLAN Tag Register must not
787 * be zero. Set the VLAN tag identifier to "1" to enable the
788 * VLAN Hash Table filtering. This implies that a VLAN tag of
789 * 1 will always pass filtering.
790 */
791 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
792
793 return 0;
794}
795
796static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
797{
798 /* Disable VLAN filtering */
799 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
800
801 return 0;
802}
803
804static u32 xgbe_vid_crc32_le(__le16 vid_le)
805{
806 u32 poly = 0xedb88320; /* CRCPOLY_LE */
807 u32 crc = ~0;
808 u32 temp = 0;
809 unsigned char *data = (unsigned char *)&vid_le;
810 unsigned char data_byte = 0;
811 int i, bits;
812
813 bits = get_bitmask_order(VLAN_VID_MASK);
814 for (i = 0; i < bits; i++) {
815 if ((i % 8) == 0)
816 data_byte = data[i / 8];
817
818 temp = ((crc & 1) ^ data_byte) & 1;
819 crc >>= 1;
820 data_byte >>= 1;
821
822 if (temp)
823 crc ^= poly;
824 }
825
826 return crc;
827}
828
829static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
830{
831 u32 crc;
832 u16 vid;
833 __le16 vid_le;
834 u16 vlan_hash_table = 0;
835
836 /* Generate the VLAN Hash Table value */
837 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
838 /* Get the CRC32 value of the VLAN ID */
839 vid_le = cpu_to_le16(vid);
840 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
841
842 vlan_hash_table |= (1 << crc);
843 }
844
845 /* Set the VLAN Hash Table filtering register */
846 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
847
848 return 0;
849}
850
c5aa9e3b
LT		 851static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
852 unsigned int enable)
853{
854 unsigned int val = enable ? 1 : 0;
855
856 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
857 return 0;
858
34bf65df
LT		 859 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n",
860 enable ? "entering" : "leaving");
c5aa9e3b
LT		 861 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
862
b4eee84f
LT		 863 /* Hardware will still perform VLAN filtering in promiscuous mode */
864 if (enable) {
865 xgbe_disable_rx_vlan_filtering(pdata);
866 } else {
867 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
868 xgbe_enable_rx_vlan_filtering(pdata);
869 }
870
c5aa9e3b
LT		 871 return 0;
872}
873
874static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
875 unsigned int enable)
876{
877 unsigned int val = enable ? 1 : 0;
878
879 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
880 return 0;
881
34bf65df
LT		 882 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n",
883 enable ? "entering" : "leaving");
c5aa9e3b
LT		 884 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
885
886 return 0;
887}
888
b85e4d89
LT		 889static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
890 struct netdev_hw_addr *ha, unsigned int *mac_reg)
c5aa9e3b 891{
c5aa9e3b
LT		 892 unsigned int mac_addr_hi, mac_addr_lo;
893 u8 *mac_addr;
c5aa9e3b 894
b85e4d89
LT		 895 mac_addr_lo = 0;
896 mac_addr_hi = 0;
c5aa9e3b 897
b85e4d89 898 if (ha) {
c5aa9e3b
LT		 899 mac_addr = (u8 *)&mac_addr_lo;
900 mac_addr[0] = ha->addr[0];
901 mac_addr[1] = ha->addr[1];
902 mac_addr[2] = ha->addr[2];
903 mac_addr[3] = ha->addr[3];
904 mac_addr = (u8 *)&mac_addr_hi;
905 mac_addr[0] = ha->addr[4];
906 mac_addr[1] = ha->addr[5];
907
34bf65df
LT		 908 netif_dbg(pdata, drv, pdata->netdev,
909 "adding mac address %pM at %#x\n",
910 ha->addr, *mac_reg);
c5aa9e3b
LT		 911
912 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
b85e4d89 913 }
c5aa9e3b 914
b85e4d89
LT		 915 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
916 *mac_reg += MAC_MACA_INC;
917 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
918 *mac_reg += MAC_MACA_INC;
919}
c5aa9e3b 920
b85e4d89
LT		 921static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
922{
923 struct net_device *netdev = pdata->netdev;
924 struct netdev_hw_addr *ha;
925 unsigned int mac_reg;
926 unsigned int addn_macs;
927
928 mac_reg = MAC_MACA1HR;
929 addn_macs = pdata->hw_feat.addn_mac;
c5aa9e3b 930
b85e4d89
LT		 931 if (netdev_uc_count(netdev) > addn_macs) {
932 xgbe_set_promiscuous_mode(pdata, 1);
933 } else {
934 netdev_for_each_uc_addr(ha, netdev) {
935 xgbe_set_mac_reg(pdata, ha, &mac_reg);
936 addn_macs--;
937 }
938
939 if (netdev_mc_count(netdev) > addn_macs) {
940 xgbe_set_all_multicast_mode(pdata, 1);
941 } else {
942 netdev_for_each_mc_addr(ha, netdev) {
943 xgbe_set_mac_reg(pdata, ha, &mac_reg);
944 addn_macs--;
945 }
c5aa9e3b
LT		 946 }
947 }
948
949 /* Clear remaining additional MAC address entries */
b85e4d89
LT		 950 while (addn_macs--)
951 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
952}
953
954static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
955{
956 struct net_device *netdev = pdata->netdev;
957 struct netdev_hw_addr *ha;
958 unsigned int hash_reg;
959 unsigned int hash_table_shift, hash_table_count;
960 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
961 u32 crc;
962 unsigned int i;
963
964 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
965 hash_table_count = pdata->hw_feat.hash_table_size / 32;
966 memset(hash_table, 0, sizeof(hash_table));
967
968 /* Build the MAC Hash Table register values */
969 netdev_for_each_uc_addr(ha, netdev) {
970 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
971 crc >>= hash_table_shift;
972 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
973 }
974
975 netdev_for_each_mc_addr(ha, netdev) {
976 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
977 crc >>= hash_table_shift;
978 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
c5aa9e3b
LT		 979 }
980
b85e4d89
LT		 981 /* Set the MAC Hash Table registers */
982 hash_reg = MAC_HTR0;
983 for (i = 0; i < hash_table_count; i++) {
984 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
985 hash_reg += MAC_HTR_INC;
986 }
987}
988
989static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
990{
991 if (pdata->hw_feat.hash_table_size)
992 xgbe_set_mac_hash_table(pdata);
993 else
994 xgbe_set_mac_addn_addrs(pdata);
995
c5aa9e3b
LT		 996 return 0;
997}
998
999static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
1000{
1001 unsigned int mac_addr_hi, mac_addr_lo;
1002
1003 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
1004 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
1005 (addr[1] << 8) | (addr[0] << 0);
1006
1007 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
1008 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
1009
1010 return 0;
1011}
1012
b876382b
LT		 1013static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
1014{
1015 struct net_device *netdev = pdata->netdev;
1016 unsigned int pr_mode, am_mode;
1017
1018 pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
1019 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
1020
1021 xgbe_set_promiscuous_mode(pdata, pr_mode);
1022 xgbe_set_all_multicast_mode(pdata, am_mode);
1023
1024 xgbe_add_mac_addresses(pdata);
1025
1026 return 0;
1027}
1028
b03a4a6f
LT		 1029static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
1030 int mmd_reg)
1031{
1032 unsigned long flags;
1033 unsigned int mmd_address, index, offset;
1034 int mmd_data;
1035
1036 if (mmd_reg & MII_ADDR_C45)
1037 mmd_address = mmd_reg & ~MII_ADDR_C45;
1038 else
1039 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1040
1041 /* The PCS registers are accessed using mmio. The underlying
1042 * management interface uses indirect addressing to access the MMD
1043 * register sets. This requires accessing of the PCS register in two
1044 * phases, an address phase and a data phase.
1045 *
1046 * The mmio interface is based on 16-bit offsets and values. All
1047 * register offsets must therefore be adjusted by left shifting the
1048 * offset 1 bit and reading 16 bits of data.
1049 */
1050 mmd_address <<= 1;
1051 index = mmd_address & ~pdata->xpcs_window_mask;
1052 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1053
1054 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1055 XPCS32_IOWRITE(pdata, PCS_V2_WINDOW_SELECT, index);
1056 mmd_data = XPCS16_IOREAD(pdata, offset);
1057 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1058
1059 return mmd_data;
1060}
1061
1062static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
1063 int mmd_reg, int mmd_data)
1064{
1065 unsigned long flags;
1066 unsigned int mmd_address, index, offset;
1067
1068 if (mmd_reg & MII_ADDR_C45)
1069 mmd_address = mmd_reg & ~MII_ADDR_C45;
1070 else
1071 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1072
1073 /* The PCS registers are accessed using mmio. The underlying
1074 * management interface uses indirect addressing to access the MMD
1075 * register sets. This requires accessing of the PCS register in two
1076 * phases, an address phase and a data phase.
1077 *
1078 * The mmio interface is based on 16-bit offsets and values. All
1079 * register offsets must therefore be adjusted by left shifting the
1080 * offset 1 bit and writing 16 bits of data.
1081 */
1082 mmd_address <<= 1;
1083 index = mmd_address & ~pdata->xpcs_window_mask;
1084 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1085
1086 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1087 XPCS32_IOWRITE(pdata, PCS_V2_WINDOW_SELECT, index);
1088 XPCS16_IOWRITE(pdata, offset, mmd_data);
1089 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1090}
1091
1092static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
1093 int mmd_reg)
c5aa9e3b 1094{
ced3fcae 1095 unsigned long flags;
c5aa9e3b
LT		 1096 unsigned int mmd_address;
1097 int mmd_data;
1098
1099 if (mmd_reg & MII_ADDR_C45)
1100 mmd_address = mmd_reg & ~MII_ADDR_C45;
1101 else
1102 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1103
1104 /* The PCS registers are accessed using mmio. The underlying APB3
1105 * management interface uses indirect addressing to access the MMD
1106 * register sets. This requires accessing of the PCS register in two
1107 * phases, an address phase and a data phase.
1108 *
1109 * The mmio interface is based on 32-bit offsets and values. All
1110 * register offsets must therefore be adjusted by left shifting the
1111 * offset 2 bits and reading 32 bits of data.
1112 */
ced3fcae 1113 spin_lock_irqsave(&pdata->xpcs_lock, flags);
b03a4a6f
LT		 1114 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1115 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2);
ced3fcae 1116 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
c5aa9e3b
LT		 1117
1118 return mmd_data;
1119}
1120
b03a4a6f
LT		 1121static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
1122 int mmd_reg, int mmd_data)
c5aa9e3b
LT		 1123{
1124 unsigned int mmd_address;
ced3fcae 1125 unsigned long flags;
c5aa9e3b
LT		 1126
1127 if (mmd_reg & MII_ADDR_C45)
1128 mmd_address = mmd_reg & ~MII_ADDR_C45;
1129 else
1130 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1131
1132 /* The PCS registers are accessed using mmio. The underlying APB3
1133 * management interface uses indirect addressing to access the MMD
1134 * register sets. This requires accessing of the PCS register in two
1135 * phases, an address phase and a data phase.
1136 *
1137 * The mmio interface is based on 32-bit offsets and values. All
1138 * register offsets must therefore be adjusted by left shifting the
b03a4a6f 1139 * offset 2 bits and writing 32 bits of data.
c5aa9e3b 1140 */
ced3fcae 1141 spin_lock_irqsave(&pdata->xpcs_lock, flags);
b03a4a6f
LT		 1142 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1143 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
ced3fcae 1144 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
c5aa9e3b
LT		 1145}
1146
b03a4a6f
LT		 1147static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
1148 int mmd_reg)
1149{
1150 switch (pdata->vdata->xpcs_access) {
1151 case XGBE_XPCS_ACCESS_V1:
1152 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg);
1153
1154 case XGBE_XPCS_ACCESS_V2:
1155 default:
1156 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg);
1157 }
1158}
1159
1160static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
1161 int mmd_reg, int mmd_data)
1162{
1163 switch (pdata->vdata->xpcs_access) {
1164 case XGBE_XPCS_ACCESS_V1:
1165 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data);
1166
1167 case XGBE_XPCS_ACCESS_V2:
1168 default:
1169 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data);
1170 }
1171}
1172
c5aa9e3b
LT		 1173static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
1174{
1175 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
1176}
1177
1178static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
1179{
1180 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
1181
1182 return 0;
1183}
1184
1185static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
1186{
1187 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
1188
1189 return 0;
1190}
1191
c5aa9e3b
LT		 1192static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
1193{
1194 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1195
1196 /* Reset the Tx descriptor
1197 * Set buffer 1 (lo) address to zero
1198 * Set buffer 1 (hi) address to zero
1199 * Reset all other control bits (IC, TTSE, B2L & B1L)
1200 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1201 */
1202 rdesc->desc0 = 0;
1203 rdesc->desc1 = 0;
1204 rdesc->desc2 = 0;
1205 rdesc->desc3 = 0;
08dcc47c
LT		 1206
1207 /* Make sure ownership is written to the descriptor */
ceb8f6be 1208 dma_wmb();
c5aa9e3b
LT		 1209}
1210
1211static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1212{
1213 struct xgbe_ring *ring = channel->tx_ring;
1214 struct xgbe_ring_data *rdata;
c5aa9e3b
LT		 1215 int i;
1216 int start_index = ring->cur;
1217
1218 DBGPR("-->tx_desc_init\n");
1219
1220 /* Initialze all descriptors */
1221 for (i = 0; i < ring->rdesc_count; i++) {
d0a8ba6c 1222 rdata = XGBE_GET_DESC_DATA(ring, i);
c5aa9e3b 1223
08dcc47c
LT		 1224 /* Initialize Tx descriptor */
1225 xgbe_tx_desc_reset(rdata);
1226 }
c5aa9e3b
LT		 1227
1228 /* Update the total number of Tx descriptors */
1229 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1230
1231 /* Update the starting address of descriptor ring */
d0a8ba6c 1232 rdata = XGBE_GET_DESC_DATA(ring, start_index);
c5aa9e3b
LT		 1233 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1234 upper_32_bits(rdata->rdesc_dma));
1235 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1236 lower_32_bits(rdata->rdesc_dma));
1237
1238 DBGPR("<--tx_desc_init\n");
1239}
1240
8dee19e6
LT		 1241static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata,
1242 struct xgbe_ring_data *rdata, unsigned int index)
c5aa9e3b
LT		 1243{
1244 struct xgbe_ring_desc *rdesc = rdata->rdesc;
8dee19e6
LT		 1245 unsigned int rx_usecs = pdata->rx_usecs;
1246 unsigned int rx_frames = pdata->rx_frames;
1247 unsigned int inte;
cfbfd86b 1248 dma_addr_t hdr_dma, buf_dma;
8dee19e6
LT		 1249
1250 if (!rx_usecs && !rx_frames) {
1251 /* No coalescing, interrupt for every descriptor */
1252 inte = 1;
1253 } else {
1254 /* Set interrupt based on Rx frame coalescing setting */
1255 if (rx_frames && !((index + 1) % rx_frames))
1256 inte = 1;
1257 else
1258 inte = 0;
1259 }
c5aa9e3b
LT		 1260
1261 /* Reset the Rx descriptor
174fd259
LT		 1262 * Set buffer 1 (lo) address to header dma address (lo)
1263 * Set buffer 1 (hi) address to header dma address (hi)
1264 * Set buffer 2 (lo) address to buffer dma address (lo)
1265 * Set buffer 2 (hi) address to buffer dma address (hi) and
1266 * set control bits OWN and INTE
c5aa9e3b 1267 */
cfbfd86b
LT		 1268 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off;
1269 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off;
1270 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma));
1271 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma));
1272 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma));
1273 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma));
c5aa9e3b 1274
8dee19e6 1275 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte);
c5aa9e3b
LT		 1276
1277 /* Since the Rx DMA engine is likely running, make sure everything
1278 * is written to the descriptor(s) before setting the OWN bit
1279 * for the descriptor
1280 */
ceb8f6be 1281 dma_wmb();
c5aa9e3b
LT		 1282
1283 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
1284
1285 /* Make sure ownership is written to the descriptor */
ceb8f6be 1286 dma_wmb();
c5aa9e3b
LT		 1287}
1288
1289static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1290{
1291 struct xgbe_prv_data *pdata = channel->pdata;
1292 struct xgbe_ring *ring = channel->rx_ring;
1293 struct xgbe_ring_data *rdata;
c5aa9e3b 1294 unsigned int start_index = ring->cur;
c5aa9e3b
LT		 1295 unsigned int i;
1296
1297 DBGPR("-->rx_desc_init\n");
1298
c5aa9e3b
LT		 1299 /* Initialize all descriptors */
1300 for (i = 0; i < ring->rdesc_count; i++) {
d0a8ba6c 1301 rdata = XGBE_GET_DESC_DATA(ring, i);
08dcc47c 1302
08dcc47c 1303 /* Initialize Rx descriptor */
8dee19e6 1304 xgbe_rx_desc_reset(pdata, rdata, i);
08dcc47c 1305 }
c5aa9e3b
LT		 1306
1307 /* Update the total number of Rx descriptors */
1308 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1309
1310 /* Update the starting address of descriptor ring */
d0a8ba6c 1311 rdata = XGBE_GET_DESC_DATA(ring, start_index);
c5aa9e3b
LT		 1312 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1313 upper_32_bits(rdata->rdesc_dma));
1314 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1315 lower_32_bits(rdata->rdesc_dma));
1316
1317 /* Update the Rx Descriptor Tail Pointer */
d0a8ba6c 1318 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
c5aa9e3b
LT		 1319 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1320 lower_32_bits(rdata->rdesc_dma));
1321
1322 DBGPR("<--rx_desc_init\n");
1323}
1324
23e4eef7
LT		 1325static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1326 unsigned int addend)
1327{
1328 /* Set the addend register value and tell the device */
1329 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1330 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1331
1332 /* Wait for addend update to complete */
1333 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1334 udelay(5);
1335}
1336
1337static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1338 unsigned int nsec)
1339{
1340 /* Set the time values and tell the device */
1341 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1342 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1343 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1344
1345 /* Wait for time update to complete */
1346 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1347 udelay(5);
1348}
1349
1350static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1351{
1352 u64 nsec;
1353
1354 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1355 nsec *= NSEC_PER_SEC;
1356 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1357
1358 return nsec;
1359}
1360
1361static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1362{
aba9777a 1363 unsigned int tx_snr, tx_ssr;
23e4eef7
LT		 1364 u64 nsec;
1365
aba9777a
LT		 1366 if (pdata->vdata->tx_tstamp_workaround) {
1367 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1368 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
1369 } else {
1370 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
1371 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1372 }
1373
23e4eef7
LT		 1374 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1375 return 0;
1376
aba9777a 1377 nsec = tx_ssr;
23e4eef7
LT		 1378 nsec *= NSEC_PER_SEC;
1379 nsec += tx_snr;
1380
1381 return nsec;
1382}
1383
1384static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1385 struct xgbe_ring_desc *rdesc)
1386{
1387 u64 nsec;
1388
1389 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1390 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1391 nsec = le32_to_cpu(rdesc->desc1);
1392 nsec <<= 32;
1393 nsec |= le32_to_cpu(rdesc->desc0);
1394 if (nsec != 0xffffffffffffffffULL) {
1395 packet->rx_tstamp = nsec;
1396 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1397 RX_TSTAMP, 1);
1398 }
1399 }
1400}
1401
1402static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1403 unsigned int mac_tscr)
1404{
1405 /* Set one nano-second accuracy */
1406 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1407
1408 /* Set fine timestamp update */
1409 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1410
1411 /* Overwrite earlier timestamps */
1412 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1413
1414 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1415
1416 /* Exit if timestamping is not enabled */
1417 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1418 return 0;
1419
1420 /* Initialize time registers */
1421 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1422 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1423 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1424 xgbe_set_tstamp_time(pdata, 0, 0);
1425
1426 /* Initialize the timecounter */
1427 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1428 ktime_to_ns(ktime_get_real()));
1429
1430 return 0;
1431}
1432
16958a2b
LT		 1433static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1434 struct xgbe_ring *ring)
1435{
1436 struct xgbe_prv_data *pdata = channel->pdata;
1437 struct xgbe_ring_data *rdata;
1438
ceb8f6be
LT		 1439 /* Make sure everything is written before the register write */
1440 wmb();
1441
16958a2b
LT		 1442 /* Issue a poll command to Tx DMA by writing address
1443 * of next immediate free descriptor */
1444 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1445 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1446 lower_32_bits(rdata->rdesc_dma));
1447
c635eaac 1448 /* Start the Tx timer */
16958a2b
LT		 1449 if (pdata->tx_usecs && !channel->tx_timer_active) {
1450 channel->tx_timer_active = 1;
c635eaac
LT		 1451 mod_timer(&channel->tx_timer,
1452 jiffies + usecs_to_jiffies(pdata->tx_usecs));
16958a2b
LT		 1453 }
1454
1455 ring->tx.xmit_more = 0;
1456}
1457
a9d41981 1458static void xgbe_dev_xmit(struct xgbe_channel *channel)
c5aa9e3b
LT		 1459{
1460 struct xgbe_prv_data *pdata = channel->pdata;
1461 struct xgbe_ring *ring = channel->tx_ring;
1462 struct xgbe_ring_data *rdata;
1463 struct xgbe_ring_desc *rdesc;
1464 struct xgbe_packet_data *packet = &ring->packet_data;
1465 unsigned int csum, tso, vlan;
1466 unsigned int tso_context, vlan_context;
eb79e640 1467 unsigned int tx_set_ic;
c5aa9e3b 1468 int start_index = ring->cur;
a83ef427 1469 int cur_index = ring->cur;
c5aa9e3b
LT		 1470 int i;
1471
a9d41981 1472 DBGPR("-->xgbe_dev_xmit\n");
c5aa9e3b
LT		 1473
1474 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1475 CSUM_ENABLE);
1476 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1477 TSO_ENABLE);
1478 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1479 VLAN_CTAG);
1480
1481 if (tso && (packet->mss != ring->tx.cur_mss))
1482 tso_context = 1;
1483 else
1484 tso_context = 0;
1485
1486 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1487 vlan_context = 1;
1488 else
1489 vlan_context = 0;
1490
eb79e640
LT		 1491 /* Determine if an interrupt should be generated for this Tx:
1492 * Interrupt:
1493 * - Tx frame count exceeds the frame count setting
1494 * - Addition of Tx frame count to the frame count since the
1495 * last interrupt was set exceeds the frame count setting
1496 * No interrupt:
1497 * - No frame count setting specified (ethtool -C ethX tx-frames 0)
1498 * - Addition of Tx frame count to the frame count since the
1499 * last interrupt was set does not exceed the frame count setting
1500 */
1501 ring->coalesce_count += packet->tx_packets;
1502 if (!pdata->tx_frames)
1503 tx_set_ic = 0;
1504 else if (packet->tx_packets > pdata->tx_frames)
1505 tx_set_ic = 1;
1506 else if ((ring->coalesce_count % pdata->tx_frames) <
1507 packet->tx_packets)
1508 tx_set_ic = 1;
1509 else
1510 tx_set_ic = 0;
c5aa9e3b 1511
a83ef427 1512 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
c5aa9e3b
LT		 1513 rdesc = rdata->rdesc;
1514
1515 /* Create a context descriptor if this is a TSO packet */
1516 if (tso_context || vlan_context) {
1517 if (tso_context) {
34bf65df
LT		 1518 netif_dbg(pdata, tx_queued, pdata->netdev,
1519 "TSO context descriptor, mss=%u\n",
1520 packet->mss);
c5aa9e3b
LT		 1521
1522 /* Set the MSS size */
1523 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1524 MSS, packet->mss);
1525
1526 /* Mark it as a CONTEXT descriptor */
1527 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1528 CTXT, 1);
1529
1530 /* Indicate this descriptor contains the MSS */
1531 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1532 TCMSSV, 1);
1533
1534 ring->tx.cur_mss = packet->mss;
1535 }
1536
1537 if (vlan_context) {
34bf65df
LT		 1538 netif_dbg(pdata, tx_queued, pdata->netdev,
1539 "VLAN context descriptor, ctag=%u\n",
1540 packet->vlan_ctag);
c5aa9e3b
LT		 1541
1542 /* Mark it as a CONTEXT descriptor */
1543 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1544 CTXT, 1);
1545
1546 /* Set the VLAN tag */
1547 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1548 VT, packet->vlan_ctag);
1549
1550 /* Indicate this descriptor contains the VLAN tag */
1551 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1552 VLTV, 1);
1553
1554 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1555 }
1556
a83ef427
LT		 1557 cur_index++;
1558 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
c5aa9e3b
LT		 1559 rdesc = rdata->rdesc;
1560 }
1561
1562 /* Update buffer address (for TSO this is the header) */
1563 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1564 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1565
1566 /* Update the buffer length */
1567 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1568 rdata->skb_dma_len);
1569
1570 /* VLAN tag insertion check */
1571 if (vlan)
1572 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1573 TX_NORMAL_DESC2_VLAN_INSERT);
1574
23e4eef7
LT		 1575 /* Timestamp enablement check */
1576 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1577 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1578
c5aa9e3b
LT		 1579 /* Mark it as First Descriptor */
1580 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1581
1582 /* Mark it as a NORMAL descriptor */
1583 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1584
1585 /* Set OWN bit if not the first descriptor */
a83ef427 1586 if (cur_index != start_index)
c5aa9e3b
LT		 1587 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1588
1589 if (tso) {
1590 /* Enable TSO */
1591 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1592 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1593 packet->tcp_payload_len);
1594 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1595 packet->tcp_header_len / 4);
5452b2df
LT		 1596
1597 pdata->ext_stats.tx_tso_packets++;
c5aa9e3b
LT		 1598 } else {
1599 /* Enable CRC and Pad Insertion */
1600 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1601
1602 /* Enable HW CSUM */
1603 if (csum)
1604 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1605 CIC, 0x3);
1606
1607 /* Set the total length to be transmitted */
1608 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1609 packet->length);
1610 }
1611
a83ef427
LT		 1612 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
1613 cur_index++;
1614 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
c5aa9e3b
LT		 1615 rdesc = rdata->rdesc;
1616
1617 /* Update buffer address */
1618 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1619 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1620
1621 /* Update the buffer length */
1622 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1623 rdata->skb_dma_len);
1624
c5aa9e3b
LT		 1625 /* Set OWN bit */
1626 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1627
1628 /* Mark it as NORMAL descriptor */
1629 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1630
1631 /* Enable HW CSUM */
1632 if (csum)
1633 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1634 CIC, 0x3);
1635 }
1636
1637 /* Set LAST bit for the last descriptor */
1638 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1639
eb79e640
LT		 1640 /* Set IC bit based on Tx coalescing settings */
1641 if (tx_set_ic)
1642 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1643
5fb4b86a
LT		 1644 /* Save the Tx info to report back during cleanup */
1645 rdata->tx.packets = packet->tx_packets;
1646 rdata->tx.bytes = packet->tx_bytes;
1647
c5aa9e3b
LT		 1648 /* In case the Tx DMA engine is running, make sure everything
1649 * is written to the descriptor(s) before setting the OWN bit
1650 * for the first descriptor
1651 */
ceb8f6be 1652 dma_wmb();
c5aa9e3b
LT		 1653
1654 /* Set OWN bit for the first descriptor */
d0a8ba6c 1655 rdata = XGBE_GET_DESC_DATA(ring, start_index);
c5aa9e3b
LT		 1656 rdesc = rdata->rdesc;
1657 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1658
34bf65df
LT		 1659 if (netif_msg_tx_queued(pdata))
1660 xgbe_dump_tx_desc(pdata, ring, start_index,
1661 packet->rdesc_count, 1);
c5aa9e3b
LT		 1662
1663 /* Make sure ownership is written to the descriptor */
20986ed8 1664 smp_wmb();
c5aa9e3b 1665
a83ef427 1666 ring->cur = cur_index + 1;
16958a2b
LT		 1667 if (!packet->skb->xmit_more ||
1668 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1669 channel->queue_index)))
1670 xgbe_tx_start_xmit(channel, ring);
1671 else
1672 ring->tx.xmit_more = 1;
c5aa9e3b
LT		 1673
1674 DBGPR(" %s: descriptors %u to %u written\n",
1675 channel->name, start_index & (ring->rdesc_count - 1),
1676 (ring->cur - 1) & (ring->rdesc_count - 1));
1677
a9d41981 1678 DBGPR("<--xgbe_dev_xmit\n");
c5aa9e3b
LT		 1679}
1680
1681static int xgbe_dev_read(struct xgbe_channel *channel)
1682{
5452b2df 1683 struct xgbe_prv_data *pdata = channel->pdata;
c5aa9e3b
LT		 1684 struct xgbe_ring *ring = channel->rx_ring;
1685 struct xgbe_ring_data *rdata;
1686 struct xgbe_ring_desc *rdesc;
1687 struct xgbe_packet_data *packet = &ring->packet_data;
5452b2df 1688 struct net_device *netdev = pdata->netdev;
5b9dfe29 1689 unsigned int err, etlt, l34t;
c5aa9e3b
LT		 1690
1691 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1692
d0a8ba6c 1693 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
c5aa9e3b
LT		 1694 rdesc = rdata->rdesc;
1695
1696 /* Check for data availability */
1697 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1698 return 1;
1699
5449e271 1700 /* Make sure descriptor fields are read after reading the OWN bit */
ceb8f6be 1701 dma_rmb();
5449e271 1702
34bf65df
LT		 1703 if (netif_msg_rx_status(pdata))
1704 xgbe_dump_rx_desc(pdata, ring, ring->cur);
c5aa9e3b 1705
23e4eef7
LT		 1706 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1707 /* Timestamp Context Descriptor */
1708 xgbe_get_rx_tstamp(packet, rdesc);
1709
1710 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1711 CONTEXT, 1);
1712 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1713 CONTEXT_NEXT, 0);
1714 return 0;
1715 }
1716
1717 /* Normal Descriptor, be sure Context Descriptor bit is off */
1718 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1719
1720 /* Indicate if a Context Descriptor is next */
1721 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1722 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1723 CONTEXT_NEXT, 1);
1724
174fd259 1725 /* Get the header length */
5452b2df 1726 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) {
c9f140eb
LT		 1727 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1728 RX_NORMAL_DESC2, HL);
5452b2df
LT		 1729 if (rdata->rx.hdr_len)
1730 pdata->ext_stats.rx_split_header_packets++;
1731 }
174fd259 1732
5b9dfe29
LT		 1733 /* Get the RSS hash */
1734 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1735 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1736 RSS_HASH, 1);
1737
1738 packet->rss_hash = le32_to_cpu(rdesc->desc1);
1739
1740 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1741 switch (l34t) {
1742 case RX_DESC3_L34T_IPV4_TCP:
1743 case RX_DESC3_L34T_IPV4_UDP:
1744 case RX_DESC3_L34T_IPV6_TCP:
1745 case RX_DESC3_L34T_IPV6_UDP:
1746 packet->rss_hash_type = PKT_HASH_TYPE_L4;
b6267d3e 1747 break;
5b9dfe29
LT		 1748 default:
1749 packet->rss_hash_type = PKT_HASH_TYPE_L3;
1750 }
1751 }
1752
c5aa9e3b 1753 /* Get the packet length */
c9f140eb 1754 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
c5aa9e3b
LT		 1755
1756 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1757 /* Not all the data has been transferred for this packet */
1758 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1759 INCOMPLETE, 1);
1760 return 0;
1761 }
1762
1763 /* This is the last of the data for this packet */
1764 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1765 INCOMPLETE, 0);
1766
1767 /* Set checksum done indicator as appropriate */
5452b2df 1768 if (netdev->features & NETIF_F_RXCSUM)
c5aa9e3b
LT		 1769 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1770 CSUM_DONE, 1);
1771
1772 /* Check for errors (only valid in last descriptor) */
1773 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1774 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
34bf65df 1775 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt);
c5aa9e3b 1776
7bba35bd
LT		 1777 if (!err || !etlt) {
1778 /* No error if err is 0 or etlt is 0 */
c52e9c63
LT		 1779 if ((etlt == 0x09) &&
1780 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c5aa9e3b
LT		 1781 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1782 VLAN_CTAG, 1);
1783 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1784 RX_NORMAL_DESC0,
1785 OVT);
34bf65df
LT		 1786 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n",
1787 packet->vlan_ctag);
c5aa9e3b
LT		 1788 }
1789 } else {
1790 if ((etlt == 0x05) || (etlt == 0x06))
1791 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1792 CSUM_DONE, 0);
1793 else
1794 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1795 FRAME, 1);
1796 }
1797
1798 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1799 ring->cur & (ring->rdesc_count - 1), ring->cur);
1800
1801 return 0;
1802}
1803
1804static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1805{
1806 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1807 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1808}
1809
1810static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1811{
1812 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1813 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1814}
1815
9867e8fb
LT		 1816static int xgbe_enable_int(struct xgbe_channel *channel,
1817 enum xgbe_int int_id)
c5aa9e3b
LT		 1818{
1819 unsigned int dma_ch_ier;
1820
9867e8fb 1821 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
c5aa9e3b 1822
c5aa9e3b 1823 switch (int_id) {
c5aa9e3b 1824 case XGMAC_INT_DMA_CH_SR_TI:
9867e8fb 1825 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
c5aa9e3b
LT		 1826 break;
1827 case XGMAC_INT_DMA_CH_SR_TPS:
9867e8fb 1828 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
c5aa9e3b
LT		 1829 break;
1830 case XGMAC_INT_DMA_CH_SR_TBU:
9867e8fb 1831 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
c5aa9e3b
LT		 1832 break;
1833 case XGMAC_INT_DMA_CH_SR_RI:
9867e8fb 1834 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
c5aa9e3b
LT		 1835 break;
1836 case XGMAC_INT_DMA_CH_SR_RBU:
9867e8fb 1837 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
c5aa9e3b
LT		 1838 break;
1839 case XGMAC_INT_DMA_CH_SR_RPS:
9867e8fb
LT		 1840 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1841 break;
1842 case XGMAC_INT_DMA_CH_SR_TI_RI:
1843 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1844 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
c5aa9e3b
LT		 1845 break;
1846 case XGMAC_INT_DMA_CH_SR_FBE:
9867e8fb 1847 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
c5aa9e3b
LT		 1848 break;
1849 case XGMAC_INT_DMA_ALL:
9867e8fb 1850 dma_ch_ier |= channel->saved_ier;
c5aa9e3b
LT		 1851 break;
1852 default:
1853 return -1;
1854 }
1855
9867e8fb
LT		 1856 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1857
c5aa9e3b
LT		 1858 return 0;
1859}
1860
1861static int xgbe_disable_int(struct xgbe_channel *channel,
1862 enum xgbe_int int_id)
1863{
1864 unsigned int dma_ch_ier;
1865
9867e8fb
LT		 1866 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1867
c5aa9e3b 1868 switch (int_id) {
c5aa9e3b 1869 case XGMAC_INT_DMA_CH_SR_TI:
9867e8fb 1870 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
c5aa9e3b
LT		 1871 break;
1872 case XGMAC_INT_DMA_CH_SR_TPS:
9867e8fb 1873 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
c5aa9e3b
LT		 1874 break;
1875 case XGMAC_INT_DMA_CH_SR_TBU:
9867e8fb 1876 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
c5aa9e3b
LT		 1877 break;
1878 case XGMAC_INT_DMA_CH_SR_RI:
9867e8fb 1879 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
c5aa9e3b
LT		 1880 break;
1881 case XGMAC_INT_DMA_CH_SR_RBU:
9867e8fb 1882 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
c5aa9e3b
LT		 1883 break;
1884 case XGMAC_INT_DMA_CH_SR_RPS:
9867e8fb
LT		 1885 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1886 break;
1887 case XGMAC_INT_DMA_CH_SR_TI_RI:
1888 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1889 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
c5aa9e3b
LT		 1890 break;
1891 case XGMAC_INT_DMA_CH_SR_FBE:
9867e8fb 1892 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
c5aa9e3b
LT		 1893 break;
1894 case XGMAC_INT_DMA_ALL:
9867e8fb 1895 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
d0a8ba6c 1896 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
c5aa9e3b
LT		 1897 break;
1898 default:
1899 return -1;
1900 }
1901
9867e8fb
LT		 1902 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1903
c5aa9e3b
LT		 1904 return 0;
1905}
1906
5ffc0335 1907static int __xgbe_exit(struct xgbe_prv_data *pdata)
c5aa9e3b
LT		 1908{
1909 unsigned int count = 2000;
1910
1911 DBGPR("-->xgbe_exit\n");
1912
1913 /* Issue a software reset */
1914 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1915 usleep_range(10, 15);
1916
1917 /* Poll Until Poll Condition */
c7557e6a 1918 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
c5aa9e3b
LT		 1919 usleep_range(500, 600);
1920
1921 if (!count)
1922 return -EBUSY;
1923
1924 DBGPR("<--xgbe_exit\n");
1925
1926 return 0;
1927}
1928
5ffc0335
LT		 1929static int xgbe_exit(struct xgbe_prv_data *pdata)
1930{
1931 int ret;
1932
1933 /* To guard against possible incorrectly generated interrupts,
1934 * issue the software reset twice.
1935 */
1936 ret = __xgbe_exit(pdata);
1937 if (ret)
1938 return ret;
1939
1940 return __xgbe_exit(pdata);
1941}
1942
c5aa9e3b
LT		 1943static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1944{
1945 unsigned int i, count;
1946
a9a4a2d9
LT		 1947 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1948 return 0;
1949
853eb16b 1950 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 1951 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1952
1953 /* Poll Until Poll Condition */
853eb16b 1954 for (i = 0; i < pdata->tx_q_count; i++) {
c5aa9e3b 1955 count = 2000;
c7557e6a 1956 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i,
c5aa9e3b
LT		 1957 MTL_Q_TQOMR, FTQ))
1958 usleep_range(500, 600);
1959
1960 if (!count)
1961 return -EBUSY;
1962 }
1963
1964 return 0;
1965}
1966
1967static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1968{
1969 /* Set enhanced addressing mode */
1970 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1971
1972 /* Set the System Bus mode */
1973 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
9867e8fb 1974 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
c5aa9e3b
LT		 1975}
1976
1977static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1978{
1979 unsigned int arcache, awcache;
1980
1981 arcache = 0;
cfa50c78
LT		 1982 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1983 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1984 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1985 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1986 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1987 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
c5aa9e3b
LT		 1988 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1989
1990 awcache = 0;
cfa50c78
LT		 1991 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1992 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1993 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1994 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1995 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1996 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1997 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1998 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
c5aa9e3b
LT		 1999 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
2000}
2001
2002static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
2003{
2004 unsigned int i;
2005
fca2d994 2006 /* Set Tx to weighted round robin scheduling algorithm */
c5aa9e3b
LT		 2007 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
2008
fca2d994
LT		 2009 /* Set Tx traffic classes to use WRR algorithm with equal weights */
2010 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
2011 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2012 MTL_TSA_ETS);
2013 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
2014 }
c5aa9e3b
LT		 2015
2016 /* Set Rx to strict priority algorithm */
2017 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
2018}
2019
43e0dcf7
LT		 2020static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata,
2021 unsigned int queue,
2022 unsigned int q_fifo_size)
2023{
2024 unsigned int frame_fifo_size;
2025 unsigned int rfa, rfd;
2026
2027 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata));
2028
2029 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) {
2030 /* PFC is active for this queue */
2031 rfa = pdata->pfc_rfa;
2032 rfd = rfa + frame_fifo_size;
2033 if (rfd > XGMAC_FLOW_CONTROL_MAX)
2034 rfd = XGMAC_FLOW_CONTROL_MAX;
2035 if (rfa >= XGMAC_FLOW_CONTROL_MAX)
2036 rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT;
2037 } else {
2038 /* This path deals with just maximum frame sizes which are
2039 * limited to a jumbo frame of 9,000 (plus headers, etc.)
2040 * so we can never exceed the maximum allowable RFA/RFD
2041 * values.
2042 */
2043 if (q_fifo_size <= 2048) {
2044 /* rx_rfd to zero to signal no flow control */
2045 pdata->rx_rfa[queue] = 0;
2046 pdata->rx_rfd[queue] = 0;
2047 return;
2048 }
2049
2050 if (q_fifo_size <= 4096) {
2051 /* Between 2048 and 4096 */
2052 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */
2053 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */
2054 return;
2055 }
2056
2057 if (q_fifo_size <= frame_fifo_size) {
2058 /* Between 4096 and max-frame */
2059 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */
2060 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */
2061 return;
2062 }
2063
2064 if (q_fifo_size <= (frame_fifo_size * 3)) {
2065 /* Between max-frame and 3 max-frames,
2066 * trigger if we get just over a frame of data and
2067 * resume when we have just under half a frame left.
2068 */
2069 rfa = q_fifo_size - frame_fifo_size;
2070 rfd = rfa + (frame_fifo_size / 2);
2071 } else {
2072 /* Above 3 max-frames - trigger when just over
2073 * 2 frames of space available
2074 */
2075 rfa = frame_fifo_size * 2;
2076 rfa += XGMAC_FLOW_CONTROL_UNIT;
2077 rfd = rfa + frame_fifo_size;
2078 }
2079 }
2080
2081 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
2082 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
2083}
2084
2085static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata,
2086 unsigned int *fifo)
2087{
2088 unsigned int q_fifo_size;
2089 unsigned int i;
2090
2091 for (i = 0; i < pdata->rx_q_count; i++) {
2092 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT;
2093
2094 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size);
2095 }
2096}
2097
2098static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2099{
2100 unsigned int i;
2101
2102 for (i = 0; i < pdata->rx_q_count; i++) {
2103 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA,
2104 pdata->rx_rfa[i]);
2105 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD,
2106 pdata->rx_rfd[i]);
2107 }
2108}
2109
586e3cfb 2110static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata)
c5aa9e3b 2111{
9c439e4b 2112 /* The configured value may not be the actual amount of fifo RAM */
bd8255d8
LT		 2113 return min_t(unsigned int, pdata->tx_max_fifo_size,
2114 pdata->hw_feat.tx_fifo_size);
586e3cfb
LT		 2115}
2116
2117static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata)
2118{
586e3cfb 2119 /* The configured value may not be the actual amount of fifo RAM */
bd8255d8
LT		 2120 return min_t(unsigned int, pdata->rx_max_fifo_size,
2121 pdata->hw_feat.rx_fifo_size);
586e3cfb
LT		 2122}
2123
2124static void xgbe_calculate_equal_fifo(unsigned int fifo_size,
2125 unsigned int queue_count,
2126 unsigned int *fifo)
2127{
2128 unsigned int q_fifo_size;
2129 unsigned int p_fifo;
2130 unsigned int i;
2131
2132 q_fifo_size = fifo_size / queue_count;
c5aa9e3b 2133
43e0dcf7
LT		 2134 /* Calculate the fifo setting by dividing the queue's fifo size
2135 * by the fifo allocation increment (with 0 representing the
2136 * base allocation increment so decrement the result by 1).
9c439e4b 2137 */
43e0dcf7 2138 p_fifo = q_fifo_size / XGMAC_FIFO_UNIT;
9c439e4b
LT		 2139 if (p_fifo)
2140 p_fifo--;
c5aa9e3b 2141
43e0dcf7 2142 /* Distribute the fifo equally amongst the queues */
586e3cfb
LT		 2143 for (i = 0; i < queue_count; i++)
2144 fifo[i] = p_fifo;
c5aa9e3b
LT		 2145}
2146
43e0dcf7
LT		 2147static unsigned int xgbe_set_nonprio_fifos(unsigned int fifo_size,
2148 unsigned int queue_count,
2149 unsigned int *fifo)
2150{
2151 unsigned int i;
2152
2153 BUILD_BUG_ON_NOT_POWER_OF_2(XGMAC_FIFO_MIN_ALLOC);
2154
2155 if (queue_count <= IEEE_8021QAZ_MAX_TCS)
2156 return fifo_size;
2157
2158 /* Rx queues 9 and up are for specialized packets,
2159 * such as PTP or DCB control packets, etc. and
2160 * don't require a large fifo
2161 */
2162 for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) {
2163 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1;
2164 fifo_size -= XGMAC_FIFO_MIN_ALLOC;
2165 }
2166
2167 return fifo_size;
2168}
2169
2170static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata)
2171{
2172 unsigned int delay;
2173
2174 /* If a delay has been provided, use that */
2175 if (pdata->pfc->delay)
2176 return pdata->pfc->delay / 8;
2177
2178 /* Allow for two maximum size frames */
2179 delay = xgbe_get_max_frame(pdata);
2180 delay += XGMAC_ETH_PREAMBLE;
2181 delay *= 2;
2182
2183 /* Allow for PFC frame */
2184 delay += XGMAC_PFC_DATA_LEN;
2185 delay += ETH_HLEN + ETH_FCS_LEN;
2186 delay += XGMAC_ETH_PREAMBLE;
2187
2188 /* Allow for miscellaneous delays (LPI exit, cable, etc.) */
2189 delay += XGMAC_PFC_DELAYS;
2190
2191 return delay;
2192}
2193
2194static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata)
2195{
2196 unsigned int count, prio_queues;
2197 unsigned int i;
2198
2199 if (!pdata->pfc->pfc_en)
2200 return 0;
2201
2202 count = 0;
2203 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2204 for (i = 0; i < prio_queues; i++) {
2205 if (!xgbe_is_pfc_queue(pdata, i))
2206 continue;
2207
2208 pdata->pfcq[i] = 1;
2209 count++;
2210 }
2211
2212 return count;
2213}
2214
2215static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata,
2216 unsigned int fifo_size,
2217 unsigned int *fifo)
2218{
2219 unsigned int q_fifo_size, rem_fifo, addn_fifo;
2220 unsigned int prio_queues;
2221 unsigned int pfc_count;
2222 unsigned int i;
2223
2224 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata));
2225 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2226 pfc_count = xgbe_get_pfc_queues(pdata);
2227
2228 if (!pfc_count || ((q_fifo_size * prio_queues) > fifo_size)) {
2229 /* No traffic classes with PFC enabled or can't do lossless */
2230 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
2231 return;
2232 }
2233
2234 /* Calculate how much fifo we have to play with */
2235 rem_fifo = fifo_size - (q_fifo_size * prio_queues);
2236
2237 /* Calculate how much more than base fifo PFC needs, which also
2238 * becomes the threshold activation point (RFA)
2239 */
2240 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata);
2241 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa);
2242
2243 if (pdata->pfc_rfa > q_fifo_size) {
2244 addn_fifo = pdata->pfc_rfa - q_fifo_size;
2245 addn_fifo = XGMAC_FIFO_ALIGN(addn_fifo);
2246 } else {
2247 addn_fifo = 0;
2248 }
2249
2250 /* Calculate DCB fifo settings:
2251 * - distribute remaining fifo between the VLAN priority
2252 * queues based on traffic class PFC enablement and overall
2253 * priority (0 is lowest priority, so start at highest)
2254 */
2255 i = prio_queues;
2256 while (i > 0) {
2257 i--;
2258
2259 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1;
2260
2261 if (!pdata->pfcq[i] || !addn_fifo)
2262 continue;
2263
2264 if (addn_fifo > rem_fifo) {
2265 netdev_warn(pdata->netdev,
2266 "RXq%u cannot set needed fifo size\n", i);
2267 if (!rem_fifo)
2268 continue;
2269
2270 addn_fifo = rem_fifo;
2271 }
2272
2273 fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT);
2274 rem_fifo -= addn_fifo;
2275 }
2276
2277 if (rem_fifo) {
2278 unsigned int inc_fifo = rem_fifo / prio_queues;
2279
2280 /* Distribute remaining fifo across queues */
2281 for (i = 0; i < prio_queues; i++)
2282 fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT);
2283 }
2284}
2285
c5aa9e3b
LT		 2286static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
2287{
9c439e4b 2288 unsigned int fifo_size;
586e3cfb 2289 unsigned int fifo[XGBE_MAX_QUEUES];
c5aa9e3b
LT		 2290 unsigned int i;
2291
586e3cfb
LT		 2292 fifo_size = xgbe_get_tx_fifo_size(pdata);
2293
2294 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo);
c5aa9e3b 2295
853eb16b 2296 for (i = 0; i < pdata->tx_q_count; i++)
586e3cfb 2297 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]);
c5aa9e3b 2298
34bf65df
LT		 2299 netif_info(pdata, drv, pdata->netdev,
2300 "%d Tx hardware queues, %d byte fifo per queue\n",
43e0dcf7 2301 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
c5aa9e3b
LT		 2302}
2303
2304static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
2305{
9c439e4b 2306 unsigned int fifo_size;
586e3cfb 2307 unsigned int fifo[XGBE_MAX_QUEUES];
43e0dcf7 2308 unsigned int prio_queues;
c5aa9e3b
LT		 2309 unsigned int i;
2310
43e0dcf7
LT		 2311 /* Clear any DCB related fifo/queue information */
2312 memset(pdata->pfcq, 0, sizeof(pdata->pfcq));
2313 pdata->pfc_rfa = 0;
2314
586e3cfb 2315 fifo_size = xgbe_get_rx_fifo_size(pdata);
43e0dcf7
LT		 2316 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2317
2318 /* Assign a minimum fifo to the non-VLAN priority queues */
2319 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
586e3cfb 2320
43e0dcf7
LT		 2321 if (pdata->pfc && pdata->ets)
2322 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo);
2323 else
2324 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
c5aa9e3b 2325
853eb16b 2326 for (i = 0; i < pdata->rx_q_count; i++)
586e3cfb 2327 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]);
c5aa9e3b 2328
43e0dcf7
LT		 2329 xgbe_calculate_flow_control_threshold(pdata, fifo);
2330 xgbe_config_flow_control_threshold(pdata);
2331
2332 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) {
2333 netif_info(pdata, drv, pdata->netdev,
2334 "%u Rx hardware queues\n", pdata->rx_q_count);
2335 for (i = 0; i < pdata->rx_q_count; i++)
2336 netif_info(pdata, drv, pdata->netdev,
2337 "RxQ%u, %u byte fifo queue\n", i,
2338 ((fifo[i] + 1) * XGMAC_FIFO_UNIT));
2339 } else {
2340 netif_info(pdata, drv, pdata->netdev,
2341 "%u Rx hardware queues, %u byte fifo per queue\n",
2342 pdata->rx_q_count,
2343 ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2344 }
c5aa9e3b
LT		 2345}
2346
fca2d994 2347static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
c5aa9e3b 2348{
fca2d994
LT		 2349 unsigned int qptc, qptc_extra, queue;
2350 unsigned int prio_queues;
2351 unsigned int ppq, ppq_extra, prio;
2352 unsigned int mask;
2353 unsigned int i, j, reg, reg_val;
2354
2355 /* Map the MTL Tx Queues to Traffic Classes
2356 * Note: Tx Queues >= Traffic Classes
2357 */
2358 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
2359 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
2360
2361 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2362 for (j = 0; j < qptc; j++) {
34bf65df
LT		 2363 netif_dbg(pdata, drv, pdata->netdev,
2364 "TXq%u mapped to TC%u\n", queue, i);
fca2d994
LT		 2365 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2366 Q2TCMAP, i);
2367 pdata->q2tc_map[queue++] = i;
2368 }
2369
2370 if (i < qptc_extra) {
34bf65df
LT		 2371 netif_dbg(pdata, drv, pdata->netdev,
2372 "TXq%u mapped to TC%u\n", queue, i);
fca2d994
LT		 2373 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2374 Q2TCMAP, i);
2375 pdata->q2tc_map[queue++] = i;
2376 }
2377 }
2378
2379 /* Map the 8 VLAN priority values to available MTL Rx queues */
43e0dcf7 2380 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
fca2d994
LT		 2381 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
2382 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
2383
2384 reg = MAC_RQC2R;
2385 reg_val = 0;
2386 for (i = 0, prio = 0; i < prio_queues;) {
2387 mask = 0;
2388 for (j = 0; j < ppq; j++) {
34bf65df
LT		 2389 netif_dbg(pdata, drv, pdata->netdev,
2390 "PRIO%u mapped to RXq%u\n", prio, i);
fca2d994
LT		 2391 mask |= (1 << prio);
2392 pdata->prio2q_map[prio++] = i;
2393 }
2394
2395 if (i < ppq_extra) {
34bf65df
LT		 2396 netif_dbg(pdata, drv, pdata->netdev,
2397 "PRIO%u mapped to RXq%u\n", prio, i);
fca2d994
LT		 2398 mask |= (1 << prio);
2399 pdata->prio2q_map[prio++] = i;
2400 }
2401
2402 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
2403
2404 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
2405 continue;
2406
2407 XGMAC_IOWRITE(pdata, reg, reg_val);
2408 reg += MAC_RQC2_INC;
2409 reg_val = 0;
2410 }
c5aa9e3b
LT		 2411
2412 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2413 reg = MTL_RQDCM0R;
2414 reg_val = 0;
fca2d994 2415 for (i = 0; i < pdata->rx_q_count;) {
c5aa9e3b
LT		 2416 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
2417
fca2d994 2418 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
c5aa9e3b
LT		 2419 continue;
2420
2421 XGMAC_IOWRITE(pdata, reg, reg_val);
2422
2423 reg += MTL_RQDCM_INC;
2424 reg_val = 0;
2425 }
2426}
2427
43e0dcf7 2428static void xgbe_config_tc(struct xgbe_prv_data *pdata)
c5aa9e3b 2429{
43e0dcf7
LT		 2430 unsigned int offset, queue, prio;
2431 u8 i;
c5aa9e3b 2432
43e0dcf7
LT		 2433 netdev_reset_tc(pdata->netdev);
2434 if (!pdata->num_tcs)
2435 return;
2436
2437 netdev_set_num_tc(pdata->netdev, pdata->num_tcs);
2438
2439 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) {
2440 while ((queue < pdata->tx_q_count) &&
2441 (pdata->q2tc_map[queue] == i))
2442 queue++;
2443
2444 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n",
2445 i, offset, queue - 1);
2446 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset);
2447 offset = queue;
2448 }
2449
2450 if (!pdata->ets)
2451 return;
2452
2453 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
2454 netdev_set_prio_tc_map(pdata->netdev, prio,
2455 pdata->ets->prio_tc[prio]);
2456}
2457
2458static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
2459{
2460 struct ieee_ets *ets = pdata->ets;
2461 unsigned int total_weight, min_weight, weight;
2462 unsigned int mask, reg, reg_val;
2463 unsigned int i, prio;
2464
2465 if (!ets)
2466 return;
2467
2468 /* Set Tx to deficit weighted round robin scheduling algorithm (when
2469 * traffic class is using ETS algorithm)
2470 */
2471 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
2472
2473 /* Set Traffic Class algorithms */
2474 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
2475 min_weight = total_weight / 100;
2476 if (!min_weight)
2477 min_weight = 1;
2478
2479 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
2480 /* Map the priorities to the traffic class */
2481 mask = 0;
2482 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
2483 if (ets->prio_tc[prio] == i)
2484 mask |= (1 << prio);
2485 }
2486 mask &= 0xff;
2487
2488 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n",
2489 i, mask);
2490 reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG));
2491 reg_val = XGMAC_IOREAD(pdata, reg);
c5aa9e3b 2492
43e0dcf7
LT		 2493 reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3));
2494 reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3));
2495
2496 XGMAC_IOWRITE(pdata, reg, reg_val);
2497
2498 /* Set the traffic class algorithm */
2499 switch (ets->tc_tsa[i]) {
2500 case IEEE_8021QAZ_TSA_STRICT:
2501 netif_dbg(pdata, drv, pdata->netdev,
2502 "TC%u using SP\n", i);
2503 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2504 MTL_TSA_SP);
2505 break;
2506 case IEEE_8021QAZ_TSA_ETS:
2507 weight = total_weight * ets->tc_tx_bw[i] / 100;
2508 weight = clamp(weight, min_weight, total_weight);
2509
2510 netif_dbg(pdata, drv, pdata->netdev,
2511 "TC%u using DWRR (weight %u)\n", i, weight);
2512 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2513 MTL_TSA_ETS);
2514 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
2515 weight);
2516 break;
2517 }
2518 }
2519
2520 xgbe_config_tc(pdata);
2521}
2522
2523static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
2524{
2525 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
2526 /* Just stop the Tx queues while Rx fifo is changed */
2527 netif_tx_stop_all_queues(pdata->netdev);
2528
2529 /* Suspend Rx so that fifo's can be adjusted */
2530 pdata->hw_if.disable_rx(pdata);
2531 }
2532
2533 xgbe_config_rx_fifo_size(pdata);
2534 xgbe_config_flow_control(pdata);
2535
2536 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
2537 /* Resume Rx */
2538 pdata->hw_if.enable_rx(pdata);
2539
2540 /* Resume Tx queues */
2541 netif_tx_start_all_queues(pdata->netdev);
c5aa9e3b
LT		 2542 }
2543}
2544
2545static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2546{
2547 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
b85e4d89
LT		 2548
2549 /* Filtering is done using perfect filtering and hash filtering */
2550 if (pdata->hw_feat.hash_table_size) {
2551 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2552 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2553 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2554 }
c5aa9e3b
LT		 2555}
2556
2557static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2558{
2559 unsigned int val;
2560
2561 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2562
2563 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2564}
2565
916102c6
LT		 2566static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2567{
e57f7a3f 2568 xgbe_set_speed(pdata, pdata->phy_speed);
916102c6
LT		 2569}
2570
c5aa9e3b
LT		 2571static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2572{
2573 if (pdata->netdev->features & NETIF_F_RXCSUM)
2574 xgbe_enable_rx_csum(pdata);
2575 else
2576 xgbe_disable_rx_csum(pdata);
2577}
2578
2579static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2580{
6e5eed04
LT		 2581 /* Indicate that VLAN Tx CTAGs come from context descriptors */
2582 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2583 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2584
801c62d9
LT		 2585 /* Set the current VLAN Hash Table register value */
2586 xgbe_update_vlan_hash_table(pdata);
2587
2588 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2589 xgbe_enable_rx_vlan_filtering(pdata);
2590 else
2591 xgbe_disable_rx_vlan_filtering(pdata);
2592
c5aa9e3b
LT		 2593 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2594 xgbe_enable_rx_vlan_stripping(pdata);
2595 else
2596 xgbe_disable_rx_vlan_stripping(pdata);
2597}
2598
60265108
LT		 2599static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2600{
2601 bool read_hi;
2602 u64 val;
2603
e5a20b90
LT		 2604 if (pdata->vdata->mmc_64bit) {
2605 switch (reg_lo) {
2606 /* These registers are always 32 bit */
2607 case MMC_RXRUNTERROR:
2608 case MMC_RXJABBERERROR:
2609 case MMC_RXUNDERSIZE_G:
2610 case MMC_RXOVERSIZE_G:
2611 case MMC_RXWATCHDOGERROR:
2612 read_hi = false;
2613 break;
60265108 2614
e5a20b90
LT		 2615 default:
2616 read_hi = true;
2617 }
2618 } else {
2619 switch (reg_lo) {
2620 /* These registers are always 64 bit */
2621 case MMC_TXOCTETCOUNT_GB_LO:
2622 case MMC_TXOCTETCOUNT_G_LO:
2623 case MMC_RXOCTETCOUNT_GB_LO:
2624 case MMC_RXOCTETCOUNT_G_LO:
2625 read_hi = true;
2626 break;
2627
2628 default:
2629 read_hi = false;
2630 }
3947d78a 2631 }
60265108
LT		 2632
2633 val = XGMAC_IOREAD(pdata, reg_lo);
2634
2635 if (read_hi)
2636 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2637
2638 return val;
2639}
2640
c5aa9e3b
LT		 2641static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2642{
2643 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2644 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2645
2646 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
2647 stats->txoctetcount_gb +=
60265108 2648 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
c5aa9e3b
LT		 2649
2650 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
2651 stats->txframecount_gb +=
60265108 2652 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
c5aa9e3b
LT		 2653
2654 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
2655 stats->txbroadcastframes_g +=
60265108 2656 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
c5aa9e3b
LT		 2657
2658 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2659 stats->txmulticastframes_g +=
60265108 2660 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
c5aa9e3b
LT		 2661
2662 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2663 stats->tx64octets_gb +=
60265108 2664 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
c5aa9e3b
LT		 2665
2666 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2667 stats->tx65to127octets_gb +=
60265108 2668 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
c5aa9e3b
LT		 2669
2670 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2671 stats->tx128to255octets_gb +=
60265108 2672 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
c5aa9e3b
LT		 2673
2674 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2675 stats->tx256to511octets_gb +=
60265108 2676 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
c5aa9e3b
LT		 2677
2678 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2679 stats->tx512to1023octets_gb +=
60265108 2680 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
c5aa9e3b
LT		 2681
2682 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2683 stats->tx1024tomaxoctets_gb +=
60265108 2684 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
c5aa9e3b
LT		 2685
2686 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2687 stats->txunicastframes_gb +=
60265108 2688 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
c5aa9e3b
LT		 2689
2690 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2691 stats->txmulticastframes_gb +=
60265108 2692 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
c5aa9e3b
LT		 2693
2694 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2695 stats->txbroadcastframes_g +=
60265108 2696 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
c5aa9e3b
LT		 2697
2698 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2699 stats->txunderflowerror +=
60265108 2700 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
c5aa9e3b
LT		 2701
2702 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2703 stats->txoctetcount_g +=
60265108 2704 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
c5aa9e3b
LT		 2705
2706 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2707 stats->txframecount_g +=
60265108 2708 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
c5aa9e3b
LT		 2709
2710 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2711 stats->txpauseframes +=
60265108 2712 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
c5aa9e3b
LT		 2713
2714 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2715 stats->txvlanframes_g +=
60265108 2716 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
c5aa9e3b
LT		 2717}
2718
2719static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2720{
2721 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2722 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2723
2724 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2725 stats->rxframecount_gb +=
60265108 2726 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
c5aa9e3b
LT		 2727
2728 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2729 stats->rxoctetcount_gb +=
60265108 2730 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
c5aa9e3b
LT		 2731
2732 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2733 stats->rxoctetcount_g +=
60265108 2734 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
c5aa9e3b
LT		 2735
2736 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2737 stats->rxbroadcastframes_g +=
60265108 2738 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
c5aa9e3b
LT		 2739
2740 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2741 stats->rxmulticastframes_g +=
60265108 2742 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
c5aa9e3b
LT		 2743
2744 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2745 stats->rxcrcerror +=
60265108 2746 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
c5aa9e3b
LT		 2747
2748 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2749 stats->rxrunterror +=
60265108 2750 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
c5aa9e3b
LT		 2751
2752 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2753 stats->rxjabbererror +=
60265108 2754 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
c5aa9e3b
LT		 2755
2756 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2757 stats->rxundersize_g +=
60265108 2758 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
c5aa9e3b
LT		 2759
2760 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2761 stats->rxoversize_g +=
60265108 2762 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
c5aa9e3b
LT		 2763
2764 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2765 stats->rx64octets_gb +=
60265108 2766 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
c5aa9e3b
LT		 2767
2768 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2769 stats->rx65to127octets_gb +=
60265108 2770 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
c5aa9e3b
LT		 2771
2772 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2773 stats->rx128to255octets_gb +=
60265108 2774 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
c5aa9e3b
LT		 2775
2776 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2777 stats->rx256to511octets_gb +=
60265108 2778 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
c5aa9e3b
LT		 2779
2780 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2781 stats->rx512to1023octets_gb +=
60265108 2782 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
c5aa9e3b
LT		 2783
2784 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2785 stats->rx1024tomaxoctets_gb +=
60265108 2786 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
c5aa9e3b
LT		 2787
2788 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
2789 stats->rxunicastframes_g +=
60265108 2790 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
c5aa9e3b
LT		 2791
2792 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
2793 stats->rxlengtherror +=
60265108 2794 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
c5aa9e3b
LT		 2795
2796 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
2797 stats->rxoutofrangetype +=
60265108 2798 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
c5aa9e3b
LT		 2799
2800 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
2801 stats->rxpauseframes +=
60265108 2802 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
c5aa9e3b
LT		 2803
2804 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
2805 stats->rxfifooverflow +=
60265108 2806 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
c5aa9e3b
LT		 2807
2808 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
2809 stats->rxvlanframes_gb +=
60265108 2810 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
c5aa9e3b
LT		 2811
2812 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
2813 stats->rxwatchdogerror +=
60265108 2814 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
c5aa9e3b
LT		 2815}
2816
2817static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2818{
2819 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2820
2821 /* Freeze counters */
2822 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2823
2824 stats->txoctetcount_gb +=
60265108 2825 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
c5aa9e3b
LT		 2826
2827 stats->txframecount_gb +=
60265108 2828 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
c5aa9e3b
LT		 2829
2830 stats->txbroadcastframes_g +=
60265108 2831 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
c5aa9e3b
LT		 2832
2833 stats->txmulticastframes_g +=
60265108 2834 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
c5aa9e3b
LT		 2835
2836 stats->tx64octets_gb +=
60265108 2837 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
c5aa9e3b
LT		 2838
2839 stats->tx65to127octets_gb +=
60265108 2840 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
c5aa9e3b
LT		 2841
2842 stats->tx128to255octets_gb +=
60265108 2843 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
c5aa9e3b
LT		 2844
2845 stats->tx256to511octets_gb +=
60265108 2846 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
c5aa9e3b
LT		 2847
2848 stats->tx512to1023octets_gb +=
60265108 2849 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
c5aa9e3b
LT		 2850
2851 stats->tx1024tomaxoctets_gb +=
60265108 2852 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
c5aa9e3b
LT		 2853
2854 stats->txunicastframes_gb +=
60265108 2855 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
c5aa9e3b
LT		 2856
2857 stats->txmulticastframes_gb +=
60265108 2858 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
c5aa9e3b
LT		 2859
2860 stats->txbroadcastframes_g +=
60265108 2861 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
c5aa9e3b
LT		 2862
2863 stats->txunderflowerror +=
60265108 2864 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
c5aa9e3b
LT		 2865
2866 stats->txoctetcount_g +=
60265108 2867 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
c5aa9e3b
LT		 2868
2869 stats->txframecount_g +=
60265108 2870 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
c5aa9e3b
LT		 2871
2872 stats->txpauseframes +=
60265108 2873 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
c5aa9e3b
LT		 2874
2875 stats->txvlanframes_g +=
60265108 2876 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
c5aa9e3b
LT		 2877
2878 stats->rxframecount_gb +=
60265108 2879 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
c5aa9e3b
LT		 2880
2881 stats->rxoctetcount_gb +=
60265108 2882 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
c5aa9e3b
LT		 2883
2884 stats->rxoctetcount_g +=
60265108 2885 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
c5aa9e3b
LT		 2886
2887 stats->rxbroadcastframes_g +=
60265108 2888 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
c5aa9e3b
LT		 2889
2890 stats->rxmulticastframes_g +=
60265108 2891 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
c5aa9e3b
LT		 2892
2893 stats->rxcrcerror +=
60265108 2894 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
c5aa9e3b
LT		 2895
2896 stats->rxrunterror +=
60265108 2897 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
c5aa9e3b
LT		 2898
2899 stats->rxjabbererror +=
60265108 2900 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
c5aa9e3b
LT		 2901
2902 stats->rxundersize_g +=
60265108 2903 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
c5aa9e3b
LT		 2904
2905 stats->rxoversize_g +=
60265108 2906 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
c5aa9e3b
LT		 2907
2908 stats->rx64octets_gb +=
60265108 2909 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
c5aa9e3b
LT		 2910
2911 stats->rx65to127octets_gb +=
60265108 2912 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
c5aa9e3b
LT		 2913
2914 stats->rx128to255octets_gb +=
60265108 2915 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
c5aa9e3b
LT		 2916
2917 stats->rx256to511octets_gb +=
60265108 2918 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
c5aa9e3b
LT		 2919
2920 stats->rx512to1023octets_gb +=
60265108 2921 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
c5aa9e3b
LT		 2922
2923 stats->rx1024tomaxoctets_gb +=
60265108 2924 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
c5aa9e3b
LT		 2925
2926 stats->rxunicastframes_g +=
60265108 2927 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
c5aa9e3b
LT		 2928
2929 stats->rxlengtherror +=
60265108 2930 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
c5aa9e3b
LT		 2931
2932 stats->rxoutofrangetype +=
60265108 2933 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
c5aa9e3b
LT		 2934
2935 stats->rxpauseframes +=
60265108 2936 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
c5aa9e3b
LT		 2937
2938 stats->rxfifooverflow +=
60265108 2939 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
c5aa9e3b
LT		 2940
2941 stats->rxvlanframes_gb +=
60265108 2942 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
c5aa9e3b
LT		 2943
2944 stats->rxwatchdogerror +=
60265108 2945 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
c5aa9e3b
LT		 2946
2947 /* Un-freeze counters */
2948 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2949}
2950
2951static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2952{
2953 /* Set counters to reset on read */
2954 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2955
2956 /* Reset the counters */
2957 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2958}
2959
4b8acdf5
LT		 2960static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata,
2961 unsigned int queue)
2962{
2963 unsigned int tx_status;
2964 unsigned long tx_timeout;
2965
2966 /* The Tx engine cannot be stopped if it is actively processing
2967 * packets. Wait for the Tx queue to empty the Tx fifo. Don't
2968 * wait forever though...
2969 */
2970 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
2971 while (time_before(jiffies, tx_timeout)) {
2972 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
2973 if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) &&
2974 (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0))
2975 break;
2976
2977 usleep_range(500, 1000);
2978 }
2979
2980 if (!time_before(jiffies, tx_timeout))
2981 netdev_info(pdata->netdev,
2982 "timed out waiting for Tx queue %u to empty\n",
2983 queue);
2984}
2985
16edd34e 2986static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
4b8acdf5 2987 unsigned int queue)
16edd34e
LT		 2988{
2989 unsigned int tx_dsr, tx_pos, tx_qidx;
2990 unsigned int tx_status;
2991 unsigned long tx_timeout;
2992
4b8acdf5
LT		 2993 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
2994 return xgbe_txq_prepare_tx_stop(pdata, queue);
2995
16edd34e 2996 /* Calculate the status register to read and the position within */
4b8acdf5 2997 if (queue < DMA_DSRX_FIRST_QUEUE) {
16edd34e 2998 tx_dsr = DMA_DSR0;
4b8acdf5 2999 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
16edd34e 3000 } else {
4b8acdf5 3001 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
16edd34e
LT		 3002
3003 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
3004 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
3005 DMA_DSRX_TPS_START;
3006 }
3007
3008 /* The Tx engine cannot be stopped if it is actively processing
3009 * descriptors. Wait for the Tx engine to enter the stopped or
3010 * suspended state. Don't wait forever though...
3011 */
3012 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
3013 while (time_before(jiffies, tx_timeout)) {
3014 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
3015 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
3016 if ((tx_status == DMA_TPS_STOPPED) ||
3017 (tx_status == DMA_TPS_SUSPENDED))
3018 break;
3019
3020 usleep_range(500, 1000);
3021 }
3022
3023 if (!time_before(jiffies, tx_timeout))
3024 netdev_info(pdata->netdev,
3025 "timed out waiting for Tx DMA channel %u to stop\n",
4b8acdf5 3026 queue);
16edd34e
LT		 3027}
3028
c5aa9e3b
LT		 3029static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
3030{
3031 struct xgbe_channel *channel;
3032 unsigned int i;
3033
3034 /* Enable each Tx DMA channel */
3035 channel = pdata->channel;
3036 for (i = 0; i < pdata->channel_count; i++, channel++) {
3037 if (!channel->tx_ring)
3038 break;
3039
3040 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
3041 }
3042
3043 /* Enable each Tx queue */
853eb16b 3044 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 3045 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
3046 MTL_Q_ENABLED);
3047
3048 /* Enable MAC Tx */
3049 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
3050}
3051
3052static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
3053{
3054 struct xgbe_channel *channel;
3055 unsigned int i;
3056
16edd34e 3057 /* Prepare for Tx DMA channel stop */
4b8acdf5
LT		 3058 for (i = 0; i < pdata->tx_q_count; i++)
3059 xgbe_prepare_tx_stop(pdata, i);
16edd34e 3060
c5aa9e3b
LT		 3061 /* Disable MAC Tx */
3062 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
3063
3064 /* Disable each Tx queue */
853eb16b 3065 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 3066 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
3067
3068 /* Disable each Tx DMA channel */
3069 channel = pdata->channel;
3070 for (i = 0; i < pdata->channel_count; i++, channel++) {
3071 if (!channel->tx_ring)
3072 break;
3073
3074 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
3075 }
3076}
3077
c3727d61
LT		 3078static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata,
3079 unsigned int queue)
3080{
3081 unsigned int rx_status;
3082 unsigned long rx_timeout;
3083
3084 /* The Rx engine cannot be stopped if it is actively processing
3085 * packets. Wait for the Rx queue to empty the Rx fifo. Don't
3086 * wait forever though...
3087 */
3088 rx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
3089 while (time_before(jiffies, rx_timeout)) {
3090 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
3091 if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) &&
3092 (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0))
3093 break;
3094
3095 usleep_range(500, 1000);
3096 }
3097
3098 if (!time_before(jiffies, rx_timeout))
3099 netdev_info(pdata->netdev,
3100 "timed out waiting for Rx queue %u to empty\n",
3101 queue);
3102}
3103
c5aa9e3b
LT		 3104static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
3105{
3106 struct xgbe_channel *channel;
3107 unsigned int reg_val, i;
3108
3109 /* Enable each Rx DMA channel */
3110 channel = pdata->channel;
3111 for (i = 0; i < pdata->channel_count; i++, channel++) {
3112 if (!channel->rx_ring)
3113 break;
3114
3115 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
3116 }
3117
3118 /* Enable each Rx queue */
3119 reg_val = 0;
853eb16b 3120 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 3121 reg_val |= (0x02 << (i << 1));
3122 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
3123
3124 /* Enable MAC Rx */
3125 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
3126 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
3127 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
3128 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
3129}
3130
3131static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
3132{
3133 struct xgbe_channel *channel;
3134 unsigned int i;
3135
3136 /* Disable MAC Rx */
3137 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
3138 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
3139 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
3140 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
3141
c3727d61
LT		 3142 /* Prepare for Rx DMA channel stop */
3143 for (i = 0; i < pdata->rx_q_count; i++)
3144 xgbe_prepare_rx_stop(pdata, i);
3145
c5aa9e3b
LT		 3146 /* Disable each Rx queue */
3147 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
3148
3149 /* Disable each Rx DMA channel */
3150 channel = pdata->channel;
3151 for (i = 0; i < pdata->channel_count; i++, channel++) {
3152 if (!channel->rx_ring)
3153 break;
3154
3155 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
3156 }
3157}
3158
3159static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
3160{
3161 struct xgbe_channel *channel;
3162 unsigned int i;
3163
3164 /* Enable each Tx DMA channel */
3165 channel = pdata->channel;
3166 for (i = 0; i < pdata->channel_count; i++, channel++) {
3167 if (!channel->tx_ring)
3168 break;
3169
3170 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
3171 }
3172
3173 /* Enable MAC Tx */
3174 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
3175}
3176
3177static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
3178{
3179 struct xgbe_channel *channel;
3180 unsigned int i;
3181
16edd34e 3182 /* Prepare for Tx DMA channel stop */
4b8acdf5
LT		 3183 for (i = 0; i < pdata->tx_q_count; i++)
3184 xgbe_prepare_tx_stop(pdata, i);
16edd34e 3185
c5aa9e3b
LT		 3186 /* Disable MAC Tx */
3187 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
3188
3189 /* Disable each Tx DMA channel */
3190 channel = pdata->channel;
3191 for (i = 0; i < pdata->channel_count; i++, channel++) {
3192 if (!channel->tx_ring)
3193 break;
3194
3195 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
3196 }
3197}
3198
3199static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
3200{
3201 struct xgbe_channel *channel;
3202 unsigned int i;
3203
3204 /* Enable each Rx DMA channel */
3205 channel = pdata->channel;
3206 for (i = 0; i < pdata->channel_count; i++, channel++) {
3207 if (!channel->rx_ring)
3208 break;
3209
3210 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
3211 }
3212}
3213
3214static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
3215{
3216 struct xgbe_channel *channel;
3217 unsigned int i;
3218
3219 /* Disable each Rx DMA channel */
3220 channel = pdata->channel;
3221 for (i = 0; i < pdata->channel_count; i++, channel++) {
3222 if (!channel->rx_ring)
3223 break;
3224
3225 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
3226 }
3227}
3228
3229static int xgbe_init(struct xgbe_prv_data *pdata)
3230{
3231 struct xgbe_desc_if *desc_if = &pdata->desc_if;
3232 int ret;
3233
3234 DBGPR("-->xgbe_init\n");
3235
3236 /* Flush Tx queues */
3237 ret = xgbe_flush_tx_queues(pdata);
3238 if (ret)
3239 return ret;
3240
3241 /*
3242 * Initialize DMA related features
3243 */
3244 xgbe_config_dma_bus(pdata);
3245 xgbe_config_dma_cache(pdata);
3246 xgbe_config_osp_mode(pdata);
3247 xgbe_config_pblx8(pdata);
3248 xgbe_config_tx_pbl_val(pdata);
3249 xgbe_config_rx_pbl_val(pdata);
3250 xgbe_config_rx_coalesce(pdata);
3251 xgbe_config_tx_coalesce(pdata);
3252 xgbe_config_rx_buffer_size(pdata);
3253 xgbe_config_tso_mode(pdata);
174fd259 3254 xgbe_config_sph_mode(pdata);
5b9dfe29 3255 xgbe_config_rss(pdata);
c5aa9e3b
LT		 3256 desc_if->wrapper_tx_desc_init(pdata);
3257 desc_if->wrapper_rx_desc_init(pdata);
3258 xgbe_enable_dma_interrupts(pdata);
3259
3260 /*
3261 * Initialize MTL related features
3262 */
3263 xgbe_config_mtl_mode(pdata);
fca2d994 3264 xgbe_config_queue_mapping(pdata);
c5aa9e3b
LT		 3265 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
3266 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
3267 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
3268 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
3269 xgbe_config_tx_fifo_size(pdata);
3270 xgbe_config_rx_fifo_size(pdata);
c5aa9e3b
LT		 3271 /*TODO: Error Packet and undersized good Packet forwarding enable
3272 (FEP and FUP)
3273 */
fca2d994 3274 xgbe_config_dcb_tc(pdata);
c5aa9e3b
LT		 3275 xgbe_enable_mtl_interrupts(pdata);
3276
c5aa9e3b
LT		 3277 /*
3278 * Initialize MAC related features
3279 */
3280 xgbe_config_mac_address(pdata);
b876382b 3281 xgbe_config_rx_mode(pdata);
c5aa9e3b
LT		 3282 xgbe_config_jumbo_enable(pdata);
3283 xgbe_config_flow_control(pdata);
916102c6 3284 xgbe_config_mac_speed(pdata);
c5aa9e3b
LT		 3285 xgbe_config_checksum_offload(pdata);
3286 xgbe_config_vlan_support(pdata);
3287 xgbe_config_mmc(pdata);
3288 xgbe_enable_mac_interrupts(pdata);
3289
3290 DBGPR("<--xgbe_init\n");
3291
3292 return 0;
3293}
3294
3295void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
3296{
3297 DBGPR("-->xgbe_init_function_ptrs\n");
3298
3299 hw_if->tx_complete = xgbe_tx_complete;
3300
c5aa9e3b 3301 hw_if->set_mac_address = xgbe_set_mac_address;
b876382b 3302 hw_if->config_rx_mode = xgbe_config_rx_mode;
c5aa9e3b
LT		 3303
3304 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
3305 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
3306
3307 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
3308 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
801c62d9
LT		 3309 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
3310 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
3311 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
c5aa9e3b
LT		 3312
3313 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
3314 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
3315
e57f7a3f 3316 hw_if->set_speed = xgbe_set_speed;
c5aa9e3b
LT		 3317
3318 hw_if->enable_tx = xgbe_enable_tx;
3319 hw_if->disable_tx = xgbe_disable_tx;
3320 hw_if->enable_rx = xgbe_enable_rx;
3321 hw_if->disable_rx = xgbe_disable_rx;
3322
3323 hw_if->powerup_tx = xgbe_powerup_tx;
3324 hw_if->powerdown_tx = xgbe_powerdown_tx;
3325 hw_if->powerup_rx = xgbe_powerup_rx;
3326 hw_if->powerdown_rx = xgbe_powerdown_rx;
3327
a9d41981 3328 hw_if->dev_xmit = xgbe_dev_xmit;
c5aa9e3b
LT		 3329 hw_if->dev_read = xgbe_dev_read;
3330 hw_if->enable_int = xgbe_enable_int;
3331 hw_if->disable_int = xgbe_disable_int;
3332 hw_if->init = xgbe_init;
3333 hw_if->exit = xgbe_exit;
3334
3335 /* Descriptor related Sequences have to be initialized here */
3336 hw_if->tx_desc_init = xgbe_tx_desc_init;
3337 hw_if->rx_desc_init = xgbe_rx_desc_init;
3338 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
3339 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
3340 hw_if->is_last_desc = xgbe_is_last_desc;
3341 hw_if->is_context_desc = xgbe_is_context_desc;
16958a2b 3342 hw_if->tx_start_xmit = xgbe_tx_start_xmit;
c5aa9e3b
LT		 3343
3344 /* For FLOW ctrl */
3345 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
3346 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
3347
3348 /* For RX coalescing */
3349 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
3350 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
3351 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
3352 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
3353
3354 /* For RX and TX threshold config */
3355 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
3356 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
3357
3358 /* For RX and TX Store and Forward Mode config */
3359 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
3360 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
3361
3362 /* For TX DMA Operating on Second Frame config */
3363 hw_if->config_osp_mode = xgbe_config_osp_mode;
3364
3365 /* For RX and TX PBL config */
3366 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
3367 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
3368 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
3369 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
3370 hw_if->config_pblx8 = xgbe_config_pblx8;
3371
3372 /* For MMC statistics support */
3373 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
3374 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
3375 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
3376
23e4eef7
LT		 3377 /* For PTP config */
3378 hw_if->config_tstamp = xgbe_config_tstamp;
3379 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
3380 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
3381 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
3382 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
3383
fca2d994 3384 /* For Data Center Bridging config */
b3b71597 3385 hw_if->config_tc = xgbe_config_tc;
fca2d994
LT		 3386 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
3387 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
3388
5b9dfe29
LT		 3389 /* For Receive Side Scaling */
3390 hw_if->enable_rss = xgbe_enable_rss;
3391 hw_if->disable_rss = xgbe_disable_rss;
f6ac8628
LT		 3392 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
3393 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
5b9dfe29 3394
c5aa9e3b
LT		 3395 DBGPR("<--xgbe_init_function_ptrs\n");
3396}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git