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Commit | Line | Data |
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c5aa9e3b LT |
1 | /* |
2 | * AMD 10Gb Ethernet driver | |
3 | * | |
4 | * This file is available to you under your choice of the following two | |
5 | * licenses: | |
6 | * | |
7 | * License 1: GPLv2 | |
8 | * | |
491aefb3 | 9 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
10 | * |
11 | * This file is free software; you may copy, redistribute and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation, either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * This file incorporates work covered by the following copyright and | |
25 | * permission notice: | |
26 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
27 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
28 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
29 | * and you. | |
30 | * | |
31 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
32 | * under any End User Software License Agreement or Agreement for Licensed | |
33 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
34 | * granted, free of charge, to any person obtaining a copy of this software | |
35 | * annotated with this license and the Software, to deal in the Software | |
36 | * without restriction, including without limitation the rights to use, | |
37 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
38 | * of the Software, and to permit persons to whom the Software is furnished | |
39 | * to do so, subject to the following conditions: | |
40 | * | |
41 | * The above copyright notice and this permission notice shall be included | |
42 | * in all copies or substantial portions of the Software. | |
43 | * | |
44 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
45 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
46 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
47 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
48 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
49 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
50 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
51 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
52 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
53 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
54 | * THE POSSIBILITY OF SUCH DAMAGE. | |
55 | * | |
56 | * | |
57 | * License 2: Modified BSD | |
58 | * | |
491aefb3 | 59 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
60 | * All rights reserved. |
61 | * | |
62 | * Redistribution and use in source and binary forms, with or without | |
63 | * modification, are permitted provided that the following conditions are met: | |
64 | * * Redistributions of source code must retain the above copyright | |
65 | * notice, this list of conditions and the following disclaimer. | |
66 | * * Redistributions in binary form must reproduce the above copyright | |
67 | * notice, this list of conditions and the following disclaimer in the | |
68 | * documentation and/or other materials provided with the distribution. | |
69 | * * Neither the name of Advanced Micro Devices, Inc. nor the | |
70 | * names of its contributors may be used to endorse or promote products | |
71 | * derived from this software without specific prior written permission. | |
72 | * | |
73 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
74 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
75 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
76 | * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY | |
77 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
78 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
79 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
80 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
81 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
82 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
83 | * | |
84 | * This file incorporates work covered by the following copyright and | |
85 | * permission notice: | |
86 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
87 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
88 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
89 | * and you. | |
90 | * | |
91 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
92 | * under any End User Software License Agreement or Agreement for Licensed | |
93 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
94 | * granted, free of charge, to any person obtaining a copy of this software | |
95 | * annotated with this license and the Software, to deal in the Software | |
96 | * without restriction, including without limitation the rights to use, | |
97 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
98 | * of the Software, and to permit persons to whom the Software is furnished | |
99 | * to do so, subject to the following conditions: | |
100 | * | |
101 | * The above copyright notice and this permission notice shall be included | |
102 | * in all copies or substantial portions of the Software. | |
103 | * | |
104 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
105 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
106 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
107 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
108 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
109 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
110 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
111 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
112 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
113 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
114 | * THE POSSIBILITY OF SUCH DAMAGE. | |
115 | */ | |
116 | ||
e78332b2 | 117 | #include <linux/module.h> |
c5aa9e3b LT |
118 | #include <linux/spinlock.h> |
119 | #include <linux/tcp.h> | |
120 | #include <linux/if_vlan.h> | |
c5aa9e3b LT |
121 | #include <net/busy_poll.h> |
122 | #include <linux/clk.h> | |
123 | #include <linux/if_ether.h> | |
23e4eef7 | 124 | #include <linux/net_tstamp.h> |
88131a81 | 125 | #include <linux/phy.h> |
c5aa9e3b LT |
126 | |
127 | #include "xgbe.h" | |
128 | #include "xgbe-common.h" | |
129 | ||
e78332b2 LT |
130 | static unsigned int ecc_sec_info_threshold = 10; |
131 | static unsigned int ecc_sec_warn_threshold = 10000; | |
132 | static unsigned int ecc_sec_period = 600; | |
133 | static unsigned int ecc_ded_threshold = 2; | |
134 | static unsigned int ecc_ded_period = 600; | |
135 | ||
136 | #ifdef CONFIG_AMD_XGBE_HAVE_ECC | |
137 | /* Only expose the ECC parameters if supported */ | |
138 | module_param(ecc_sec_info_threshold, uint, S_IWUSR | S_IRUGO); | |
139 | MODULE_PARM_DESC(ecc_sec_info_threshold, | |
140 | " ECC corrected error informational threshold setting"); | |
141 | ||
142 | module_param(ecc_sec_warn_threshold, uint, S_IWUSR | S_IRUGO); | |
143 | MODULE_PARM_DESC(ecc_sec_warn_threshold, | |
144 | " ECC corrected error warning threshold setting"); | |
145 | ||
146 | module_param(ecc_sec_period, uint, S_IWUSR | S_IRUGO); | |
147 | MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)"); | |
148 | ||
149 | module_param(ecc_ded_threshold, uint, S_IWUSR | S_IRUGO); | |
150 | MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting"); | |
151 | ||
152 | module_param(ecc_ded_period, uint, S_IWUSR | S_IRUGO); | |
153 | MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)"); | |
154 | #endif | |
155 | ||
9227dc5e LT |
156 | static int xgbe_one_poll(struct napi_struct *, int); |
157 | static int xgbe_all_poll(struct napi_struct *, int); | |
e78332b2 | 158 | static void xgbe_stop(struct xgbe_prv_data *); |
c5aa9e3b | 159 | |
4780b7ca LT |
160 | static int xgbe_alloc_channels(struct xgbe_prv_data *pdata) |
161 | { | |
162 | struct xgbe_channel *channel_mem, *channel; | |
163 | struct xgbe_ring *tx_ring, *rx_ring; | |
164 | unsigned int count, i; | |
9227dc5e | 165 | int ret = -ENOMEM; |
4780b7ca LT |
166 | |
167 | count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); | |
168 | ||
169 | channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL); | |
170 | if (!channel_mem) | |
171 | goto err_channel; | |
172 | ||
173 | tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring), | |
174 | GFP_KERNEL); | |
175 | if (!tx_ring) | |
176 | goto err_tx_ring; | |
177 | ||
178 | rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring), | |
179 | GFP_KERNEL); | |
180 | if (!rx_ring) | |
181 | goto err_rx_ring; | |
182 | ||
183 | for (i = 0, channel = channel_mem; i < count; i++, channel++) { | |
fb160ebd | 184 | snprintf(channel->name, sizeof(channel->name), "channel-%u", i); |
4780b7ca LT |
185 | channel->pdata = pdata; |
186 | channel->queue_index = i; | |
187 | channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + | |
188 | (DMA_CH_INC * i); | |
189 | ||
bd8255d8 LT |
190 | if (pdata->per_channel_irq) |
191 | channel->dma_irq = pdata->channel_irq[i]; | |
9227dc5e | 192 | |
4780b7ca LT |
193 | if (i < pdata->tx_ring_count) { |
194 | spin_lock_init(&tx_ring->lock); | |
195 | channel->tx_ring = tx_ring++; | |
196 | } | |
197 | ||
198 | if (i < pdata->rx_ring_count) { | |
199 | spin_lock_init(&rx_ring->lock); | |
200 | channel->rx_ring = rx_ring++; | |
201 | } | |
202 | ||
34bf65df LT |
203 | netif_dbg(pdata, drv, pdata->netdev, |
204 | "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n", | |
205 | channel->name, channel->dma_regs, channel->dma_irq, | |
206 | channel->tx_ring, channel->rx_ring); | |
4780b7ca LT |
207 | } |
208 | ||
209 | pdata->channel = channel_mem; | |
210 | pdata->channel_count = count; | |
211 | ||
212 | return 0; | |
213 | ||
214 | err_rx_ring: | |
215 | kfree(tx_ring); | |
216 | ||
217 | err_tx_ring: | |
218 | kfree(channel_mem); | |
219 | ||
220 | err_channel: | |
9227dc5e | 221 | return ret; |
4780b7ca LT |
222 | } |
223 | ||
224 | static void xgbe_free_channels(struct xgbe_prv_data *pdata) | |
225 | { | |
226 | if (!pdata->channel) | |
227 | return; | |
228 | ||
229 | kfree(pdata->channel->rx_ring); | |
230 | kfree(pdata->channel->tx_ring); | |
231 | kfree(pdata->channel); | |
232 | ||
233 | pdata->channel = NULL; | |
234 | pdata->channel_count = 0; | |
235 | } | |
236 | ||
c5aa9e3b LT |
237 | static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring) |
238 | { | |
239 | return (ring->rdesc_count - (ring->cur - ring->dirty)); | |
240 | } | |
241 | ||
270894e7 LT |
242 | static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring) |
243 | { | |
244 | return (ring->cur - ring->dirty); | |
245 | } | |
246 | ||
16958a2b LT |
247 | static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel, |
248 | struct xgbe_ring *ring, unsigned int count) | |
249 | { | |
250 | struct xgbe_prv_data *pdata = channel->pdata; | |
251 | ||
252 | if (count > xgbe_tx_avail_desc(ring)) { | |
34bf65df LT |
253 | netif_info(pdata, drv, pdata->netdev, |
254 | "Tx queue stopped, not enough descriptors available\n"); | |
16958a2b LT |
255 | netif_stop_subqueue(pdata->netdev, channel->queue_index); |
256 | ring->tx.queue_stopped = 1; | |
257 | ||
258 | /* If we haven't notified the hardware because of xmit_more | |
259 | * support, tell it now | |
260 | */ | |
261 | if (ring->tx.xmit_more) | |
262 | pdata->hw_if.tx_start_xmit(channel, ring); | |
263 | ||
264 | return NETDEV_TX_BUSY; | |
265 | } | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
c5aa9e3b LT |
270 | static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu) |
271 | { | |
272 | unsigned int rx_buf_size; | |
273 | ||
c5aa9e3b | 274 | rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
08dcc47c LT |
275 | rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); |
276 | ||
d0a8ba6c LT |
277 | rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & |
278 | ~(XGBE_RX_BUF_ALIGN - 1); | |
c5aa9e3b LT |
279 | |
280 | return rx_buf_size; | |
281 | } | |
282 | ||
4c70dd8a LT |
283 | static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, |
284 | struct xgbe_channel *channel) | |
c5aa9e3b LT |
285 | { |
286 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
9867e8fb | 287 | enum xgbe_int int_id; |
4c70dd8a LT |
288 | |
289 | if (channel->tx_ring && channel->rx_ring) | |
290 | int_id = XGMAC_INT_DMA_CH_SR_TI_RI; | |
291 | else if (channel->tx_ring) | |
292 | int_id = XGMAC_INT_DMA_CH_SR_TI; | |
293 | else if (channel->rx_ring) | |
294 | int_id = XGMAC_INT_DMA_CH_SR_RI; | |
295 | else | |
296 | return; | |
297 | ||
298 | hw_if->enable_int(channel, int_id); | |
299 | } | |
300 | ||
301 | static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata) | |
302 | { | |
303 | struct xgbe_channel *channel; | |
c5aa9e3b LT |
304 | unsigned int i; |
305 | ||
306 | channel = pdata->channel; | |
4c70dd8a LT |
307 | for (i = 0; i < pdata->channel_count; i++, channel++) |
308 | xgbe_enable_rx_tx_int(pdata, channel); | |
309 | } | |
9867e8fb | 310 | |
4c70dd8a LT |
311 | static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, |
312 | struct xgbe_channel *channel) | |
313 | { | |
314 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
315 | enum xgbe_int int_id; | |
316 | ||
317 | if (channel->tx_ring && channel->rx_ring) | |
318 | int_id = XGMAC_INT_DMA_CH_SR_TI_RI; | |
319 | else if (channel->tx_ring) | |
320 | int_id = XGMAC_INT_DMA_CH_SR_TI; | |
321 | else if (channel->rx_ring) | |
322 | int_id = XGMAC_INT_DMA_CH_SR_RI; | |
323 | else | |
324 | return; | |
325 | ||
326 | hw_if->disable_int(channel, int_id); | |
c5aa9e3b LT |
327 | } |
328 | ||
329 | static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) | |
330 | { | |
c5aa9e3b LT |
331 | struct xgbe_channel *channel; |
332 | unsigned int i; | |
333 | ||
334 | channel = pdata->channel; | |
4c70dd8a LT |
335 | for (i = 0; i < pdata->channel_count; i++, channel++) |
336 | xgbe_disable_rx_tx_int(pdata, channel); | |
c5aa9e3b LT |
337 | } |
338 | ||
e78332b2 LT |
339 | static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period, |
340 | unsigned int *count, const char *area) | |
341 | { | |
342 | if (time_before(jiffies, *period)) { | |
343 | (*count)++; | |
344 | } else { | |
345 | *period = jiffies + (ecc_sec_period * HZ); | |
346 | *count = 1; | |
347 | } | |
348 | ||
349 | if (*count > ecc_sec_info_threshold) | |
350 | dev_warn_once(pdata->dev, | |
351 | "%s ECC corrected errors exceed informational threshold\n", | |
352 | area); | |
353 | ||
354 | if (*count > ecc_sec_warn_threshold) { | |
355 | dev_warn_once(pdata->dev, | |
356 | "%s ECC corrected errors exceed warning threshold\n", | |
357 | area); | |
358 | return true; | |
359 | } | |
360 | ||
361 | return false; | |
362 | } | |
363 | ||
364 | static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period, | |
365 | unsigned int *count, const char *area) | |
366 | { | |
367 | if (time_before(jiffies, *period)) { | |
368 | (*count)++; | |
369 | } else { | |
370 | *period = jiffies + (ecc_ded_period * HZ); | |
371 | *count = 1; | |
372 | } | |
373 | ||
374 | if (*count > ecc_ded_threshold) { | |
375 | netdev_alert(pdata->netdev, | |
376 | "%s ECC detected errors exceed threshold\n", | |
377 | area); | |
378 | return true; | |
379 | } | |
380 | ||
381 | return false; | |
382 | } | |
383 | ||
384 | static irqreturn_t xgbe_ecc_isr(int irq, void *data) | |
385 | { | |
386 | struct xgbe_prv_data *pdata = data; | |
387 | unsigned int ecc_isr; | |
388 | bool stop = false; | |
389 | ||
390 | /* Mask status with only the interrupts we care about */ | |
391 | ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); | |
392 | ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER); | |
393 | netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr); | |
394 | ||
395 | if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) { | |
396 | stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period, | |
397 | &pdata->tx_ded_count, "TX fifo"); | |
398 | } | |
399 | ||
400 | if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) { | |
401 | stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period, | |
402 | &pdata->rx_ded_count, "RX fifo"); | |
403 | } | |
404 | ||
405 | if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) { | |
406 | stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period, | |
407 | &pdata->desc_ded_count, | |
408 | "descriptor cache"); | |
409 | } | |
410 | ||
411 | if (stop) { | |
412 | pdata->hw_if.disable_ecc_ded(pdata); | |
413 | schedule_work(&pdata->stopdev_work); | |
414 | goto out; | |
415 | } | |
416 | ||
417 | if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) { | |
418 | if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period, | |
419 | &pdata->tx_sec_count, "TX fifo")) | |
420 | pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX); | |
421 | } | |
422 | ||
423 | if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC)) | |
424 | if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period, | |
425 | &pdata->rx_sec_count, "RX fifo")) | |
426 | pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX); | |
427 | ||
428 | if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC)) | |
429 | if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period, | |
430 | &pdata->desc_sec_count, "descriptor cache")) | |
431 | pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC); | |
432 | ||
433 | out: | |
434 | /* Clear all ECC interrupts */ | |
435 | XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); | |
436 | ||
437 | return IRQ_HANDLED; | |
438 | } | |
439 | ||
c5aa9e3b LT |
440 | static irqreturn_t xgbe_isr(int irq, void *data) |
441 | { | |
442 | struct xgbe_prv_data *pdata = data; | |
443 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
444 | struct xgbe_channel *channel; | |
445 | unsigned int dma_isr, dma_ch_isr; | |
732f2ab7 | 446 | unsigned int mac_isr, mac_tssr, mac_mdioisr; |
c5aa9e3b LT |
447 | unsigned int i; |
448 | ||
449 | /* The DMA interrupt status register also reports MAC and MTL | |
450 | * interrupts. So for polling mode, we just need to check for | |
451 | * this register to be non-zero | |
452 | */ | |
453 | dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); | |
454 | if (!dma_isr) | |
455 | goto isr_done; | |
456 | ||
34bf65df | 457 | netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr); |
c5aa9e3b LT |
458 | |
459 | for (i = 0; i < pdata->channel_count; i++) { | |
460 | if (!(dma_isr & (1 << i))) | |
461 | continue; | |
462 | ||
463 | channel = pdata->channel + i; | |
464 | ||
465 | dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); | |
34bf65df LT |
466 | netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n", |
467 | i, dma_ch_isr); | |
c5aa9e3b | 468 | |
fd972b73 LT |
469 | /* The TI or RI interrupt bits may still be set even if using |
470 | * per channel DMA interrupts. Check to be sure those are not | |
471 | * enabled before using the private data napi structure. | |
9227dc5e | 472 | */ |
fd972b73 LT |
473 | if (!pdata->per_channel_irq && |
474 | (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || | |
475 | XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { | |
c5aa9e3b LT |
476 | if (napi_schedule_prep(&pdata->napi)) { |
477 | /* Disable Tx and Rx interrupts */ | |
478 | xgbe_disable_rx_tx_ints(pdata); | |
479 | ||
480 | /* Turn on polling */ | |
79349422 | 481 | __napi_schedule_irqoff(&pdata->napi); |
c5aa9e3b | 482 | } |
4c70dd8a LT |
483 | } else { |
484 | /* Don't clear Rx/Tx status if doing per channel DMA | |
485 | * interrupts, these will be cleared by the ISR for | |
486 | * per channel DMA interrupts. | |
487 | */ | |
488 | XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0); | |
489 | XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0); | |
c5aa9e3b LT |
490 | } |
491 | ||
72c9ac4e LT |
492 | if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU)) |
493 | pdata->ext_stats.rx_buffer_unavailable++; | |
494 | ||
c5aa9e3b LT |
495 | /* Restart the device on a Fatal Bus Error */ |
496 | if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) | |
96aec911 | 497 | schedule_work(&pdata->restart_work); |
c5aa9e3b | 498 | |
4c70dd8a | 499 | /* Clear interrupt signals */ |
c5aa9e3b LT |
500 | XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); |
501 | } | |
502 | ||
503 | if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { | |
504 | mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); | |
505 | ||
732f2ab7 LT |
506 | netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n", |
507 | mac_isr); | |
508 | ||
c5aa9e3b LT |
509 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) |
510 | hw_if->tx_mmc_int(pdata); | |
511 | ||
512 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) | |
513 | hw_if->rx_mmc_int(pdata); | |
23e4eef7 LT |
514 | |
515 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) { | |
516 | mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR); | |
517 | ||
732f2ab7 LT |
518 | netif_dbg(pdata, intr, pdata->netdev, |
519 | "MAC_TSSR=%#010x\n", mac_tssr); | |
520 | ||
23e4eef7 LT |
521 | if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) { |
522 | /* Read Tx Timestamp to clear interrupt */ | |
523 | pdata->tx_tstamp = | |
524 | hw_if->get_tx_tstamp(pdata); | |
afb43e8a LT |
525 | queue_work(pdata->dev_workqueue, |
526 | &pdata->tx_tstamp_work); | |
23e4eef7 LT |
527 | } |
528 | } | |
732f2ab7 LT |
529 | |
530 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) { | |
531 | mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR); | |
532 | ||
533 | netif_dbg(pdata, intr, pdata->netdev, | |
534 | "MAC_MDIOISR=%#010x\n", mac_mdioisr); | |
535 | ||
536 | if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR, | |
537 | SNGLCOMPINT)) | |
538 | complete(&pdata->mdio_complete); | |
539 | } | |
c5aa9e3b LT |
540 | } |
541 | ||
896b4db6 | 542 | isr_done: |
47f164de LT |
543 | /* If there is not a separate AN irq, handle it here */ |
544 | if (pdata->dev_irq == pdata->an_irq) | |
545 | pdata->phy_if.an_isr(irq, pdata); | |
546 | ||
e78332b2 LT |
547 | /* If there is not a separate ECC irq, handle it here */ |
548 | if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq)) | |
549 | xgbe_ecc_isr(irq, pdata); | |
550 | ||
5ab1dcd5 LT |
551 | /* If there is not a separate I2C irq, handle it here */ |
552 | if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq)) | |
553 | pdata->i2c_if.i2c_isr(irq, pdata); | |
554 | ||
c5aa9e3b LT |
555 | return IRQ_HANDLED; |
556 | } | |
557 | ||
9227dc5e LT |
558 | static irqreturn_t xgbe_dma_isr(int irq, void *data) |
559 | { | |
560 | struct xgbe_channel *channel = data; | |
4c70dd8a LT |
561 | struct xgbe_prv_data *pdata = channel->pdata; |
562 | unsigned int dma_status; | |
9227dc5e LT |
563 | |
564 | /* Per channel DMA interrupts are enabled, so we use the per | |
565 | * channel napi structure and not the private data napi structure | |
566 | */ | |
567 | if (napi_schedule_prep(&channel->napi)) { | |
568 | /* Disable Tx and Rx interrupts */ | |
4c70dd8a LT |
569 | if (pdata->channel_irq_mode) |
570 | xgbe_disable_rx_tx_int(pdata, channel); | |
571 | else | |
572 | disable_irq_nosync(channel->dma_irq); | |
9227dc5e LT |
573 | |
574 | /* Turn on polling */ | |
79349422 | 575 | __napi_schedule_irqoff(&channel->napi); |
9227dc5e LT |
576 | } |
577 | ||
4c70dd8a LT |
578 | /* Clear Tx/Rx signals */ |
579 | dma_status = 0; | |
580 | XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1); | |
581 | XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1); | |
582 | XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status); | |
583 | ||
9227dc5e LT |
584 | return IRQ_HANDLED; |
585 | } | |
586 | ||
c635eaac | 587 | static void xgbe_tx_timer(unsigned long data) |
c5aa9e3b | 588 | { |
c635eaac | 589 | struct xgbe_channel *channel = (struct xgbe_channel *)data; |
c5aa9e3b | 590 | struct xgbe_prv_data *pdata = channel->pdata; |
9227dc5e | 591 | struct napi_struct *napi; |
c5aa9e3b LT |
592 | |
593 | DBGPR("-->xgbe_tx_timer\n"); | |
594 | ||
9227dc5e LT |
595 | napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; |
596 | ||
9227dc5e | 597 | if (napi_schedule_prep(napi)) { |
c5aa9e3b | 598 | /* Disable Tx and Rx interrupts */ |
9227dc5e | 599 | if (pdata->per_channel_irq) |
4c70dd8a LT |
600 | if (pdata->channel_irq_mode) |
601 | xgbe_disable_rx_tx_int(pdata, channel); | |
602 | else | |
603 | disable_irq_nosync(channel->dma_irq); | |
9227dc5e LT |
604 | else |
605 | xgbe_disable_rx_tx_ints(pdata); | |
c5aa9e3b LT |
606 | |
607 | /* Turn on polling */ | |
9227dc5e | 608 | __napi_schedule(napi); |
c5aa9e3b LT |
609 | } |
610 | ||
611 | channel->tx_timer_active = 0; | |
612 | ||
c5aa9e3b | 613 | DBGPR("<--xgbe_tx_timer\n"); |
c5aa9e3b LT |
614 | } |
615 | ||
7c12aa08 LT |
616 | static void xgbe_service(struct work_struct *work) |
617 | { | |
618 | struct xgbe_prv_data *pdata = container_of(work, | |
619 | struct xgbe_prv_data, | |
620 | service_work); | |
621 | ||
622 | pdata->phy_if.phy_status(pdata); | |
623 | } | |
624 | ||
625 | static void xgbe_service_timer(unsigned long data) | |
626 | { | |
627 | struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; | |
628 | ||
afb43e8a | 629 | queue_work(pdata->dev_workqueue, &pdata->service_work); |
7c12aa08 LT |
630 | |
631 | mod_timer(&pdata->service_timer, jiffies + HZ); | |
632 | } | |
633 | ||
634 | static void xgbe_init_timers(struct xgbe_prv_data *pdata) | |
c5aa9e3b LT |
635 | { |
636 | struct xgbe_channel *channel; | |
637 | unsigned int i; | |
638 | ||
7c12aa08 LT |
639 | setup_timer(&pdata->service_timer, xgbe_service_timer, |
640 | (unsigned long)pdata); | |
c5aa9e3b LT |
641 | |
642 | channel = pdata->channel; | |
643 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
644 | if (!channel->tx_ring) | |
645 | break; | |
646 | ||
c635eaac LT |
647 | setup_timer(&channel->tx_timer, xgbe_tx_timer, |
648 | (unsigned long)channel); | |
c5aa9e3b | 649 | } |
7c12aa08 | 650 | } |
c5aa9e3b | 651 | |
7c12aa08 LT |
652 | static void xgbe_start_timers(struct xgbe_prv_data *pdata) |
653 | { | |
654 | mod_timer(&pdata->service_timer, jiffies + HZ); | |
c5aa9e3b LT |
655 | } |
656 | ||
7c12aa08 | 657 | static void xgbe_stop_timers(struct xgbe_prv_data *pdata) |
c5aa9e3b LT |
658 | { |
659 | struct xgbe_channel *channel; | |
660 | unsigned int i; | |
661 | ||
7c12aa08 | 662 | del_timer_sync(&pdata->service_timer); |
c5aa9e3b LT |
663 | |
664 | channel = pdata->channel; | |
665 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
666 | if (!channel->tx_ring) | |
667 | break; | |
668 | ||
c635eaac | 669 | del_timer_sync(&channel->tx_timer); |
c5aa9e3b | 670 | } |
c5aa9e3b LT |
671 | } |
672 | ||
673 | void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) | |
674 | { | |
675 | unsigned int mac_hfr0, mac_hfr1, mac_hfr2; | |
676 | struct xgbe_hw_features *hw_feat = &pdata->hw_feat; | |
677 | ||
678 | DBGPR("-->xgbe_get_all_hw_features\n"); | |
679 | ||
680 | mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R); | |
681 | mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R); | |
682 | mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R); | |
683 | ||
684 | memset(hw_feat, 0, sizeof(*hw_feat)); | |
685 | ||
a9a4a2d9 LT |
686 | hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); |
687 | ||
c5aa9e3b LT |
688 | /* Hardware feature register 0 */ |
689 | hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); | |
690 | hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); | |
691 | hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); | |
692 | hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); | |
693 | hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); | |
694 | hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); | |
695 | hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); | |
696 | hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); | |
697 | hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); | |
698 | hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); | |
699 | hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); | |
700 | hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, | |
701 | ADDMACADRSEL); | |
702 | hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); | |
703 | hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); | |
704 | ||
705 | /* Hardware feature register 1 */ | |
706 | hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, | |
707 | RXFIFOSIZE); | |
708 | hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, | |
709 | TXFIFOSIZE); | |
73c25916 | 710 | hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD); |
386d325d | 711 | hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); |
c5aa9e3b LT |
712 | hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); |
713 | hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); | |
714 | hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); | |
715 | hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); | |
cf180b8a | 716 | hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); |
fca2d994 | 717 | hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); |
c5aa9e3b LT |
718 | hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, |
719 | HASHTBLSZ); | |
720 | hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, | |
721 | L3L4FNUM); | |
722 | ||
723 | /* Hardware feature register 2 */ | |
724 | hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); | |
725 | hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); | |
726 | hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); | |
727 | hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); | |
728 | hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); | |
729 | hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM); | |
730 | ||
b85e4d89 LT |
731 | /* Translate the Hash Table size into actual number */ |
732 | switch (hw_feat->hash_table_size) { | |
733 | case 0: | |
734 | break; | |
735 | case 1: | |
736 | hw_feat->hash_table_size = 64; | |
737 | break; | |
738 | case 2: | |
739 | hw_feat->hash_table_size = 128; | |
740 | break; | |
741 | case 3: | |
742 | hw_feat->hash_table_size = 256; | |
743 | break; | |
744 | } | |
745 | ||
386d325d LT |
746 | /* Translate the address width setting into actual number */ |
747 | switch (hw_feat->dma_width) { | |
748 | case 0: | |
749 | hw_feat->dma_width = 32; | |
750 | break; | |
751 | case 1: | |
752 | hw_feat->dma_width = 40; | |
753 | break; | |
754 | case 2: | |
755 | hw_feat->dma_width = 48; | |
756 | break; | |
757 | default: | |
758 | hw_feat->dma_width = 32; | |
759 | } | |
760 | ||
211fcf6d | 761 | /* The Queue, Channel and TC counts are zero based so increment them |
c5aa9e3b LT |
762 | * to get the actual number |
763 | */ | |
764 | hw_feat->rx_q_cnt++; | |
765 | hw_feat->tx_q_cnt++; | |
766 | hw_feat->rx_ch_cnt++; | |
767 | hw_feat->tx_ch_cnt++; | |
211fcf6d | 768 | hw_feat->tc_cnt++; |
c5aa9e3b | 769 | |
bd8255d8 LT |
770 | /* Translate the fifo sizes into actual numbers */ |
771 | hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); | |
772 | hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); | |
773 | ||
c5aa9e3b LT |
774 | DBGPR("<--xgbe_get_all_hw_features\n"); |
775 | } | |
776 | ||
777 | static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add) | |
778 | { | |
9227dc5e LT |
779 | struct xgbe_channel *channel; |
780 | unsigned int i; | |
781 | ||
782 | if (pdata->per_channel_irq) { | |
783 | channel = pdata->channel; | |
784 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
785 | if (add) | |
786 | netif_napi_add(pdata->netdev, &channel->napi, | |
787 | xgbe_one_poll, NAPI_POLL_WEIGHT); | |
788 | ||
789 | napi_enable(&channel->napi); | |
790 | } | |
791 | } else { | |
792 | if (add) | |
793 | netif_napi_add(pdata->netdev, &pdata->napi, | |
794 | xgbe_all_poll, NAPI_POLL_WEIGHT); | |
795 | ||
796 | napi_enable(&pdata->napi); | |
797 | } | |
c5aa9e3b LT |
798 | } |
799 | ||
ff42606e | 800 | static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del) |
c5aa9e3b | 801 | { |
9227dc5e LT |
802 | struct xgbe_channel *channel; |
803 | unsigned int i; | |
804 | ||
805 | if (pdata->per_channel_irq) { | |
806 | channel = pdata->channel; | |
807 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
808 | napi_disable(&channel->napi); | |
ff42606e | 809 | |
9227dc5e LT |
810 | if (del) |
811 | netif_napi_del(&channel->napi); | |
812 | } | |
813 | } else { | |
814 | napi_disable(&pdata->napi); | |
815 | ||
816 | if (del) | |
817 | netif_napi_del(&pdata->napi); | |
818 | } | |
c5aa9e3b LT |
819 | } |
820 | ||
c30e76a7 LT |
821 | static int xgbe_request_irqs(struct xgbe_prv_data *pdata) |
822 | { | |
823 | struct xgbe_channel *channel; | |
824 | struct net_device *netdev = pdata->netdev; | |
825 | unsigned int i; | |
826 | int ret; | |
827 | ||
828 | ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0, | |
829 | netdev->name, pdata); | |
830 | if (ret) { | |
831 | netdev_alert(netdev, "error requesting irq %d\n", | |
832 | pdata->dev_irq); | |
833 | return ret; | |
834 | } | |
835 | ||
e78332b2 LT |
836 | if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) { |
837 | ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr, | |
838 | 0, pdata->ecc_name, pdata); | |
839 | if (ret) { | |
840 | netdev_alert(netdev, "error requesting ecc irq %d\n", | |
841 | pdata->ecc_irq); | |
842 | goto err_dev_irq; | |
843 | } | |
844 | } | |
845 | ||
c30e76a7 LT |
846 | if (!pdata->per_channel_irq) |
847 | return 0; | |
848 | ||
849 | channel = pdata->channel; | |
850 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
851 | snprintf(channel->dma_irq_name, | |
852 | sizeof(channel->dma_irq_name) - 1, | |
853 | "%s-TxRx-%u", netdev_name(netdev), | |
854 | channel->queue_index); | |
855 | ||
856 | ret = devm_request_irq(pdata->dev, channel->dma_irq, | |
857 | xgbe_dma_isr, 0, | |
858 | channel->dma_irq_name, channel); | |
859 | if (ret) { | |
860 | netdev_alert(netdev, "error requesting irq %d\n", | |
861 | channel->dma_irq); | |
e78332b2 | 862 | goto err_dma_irq; |
c30e76a7 LT |
863 | } |
864 | } | |
865 | ||
866 | return 0; | |
867 | ||
e78332b2 | 868 | err_dma_irq: |
c30e76a7 LT |
869 | /* Using an unsigned int, 'i' will go to UINT_MAX and exit */ |
870 | for (i--, channel--; i < pdata->channel_count; i--, channel--) | |
871 | devm_free_irq(pdata->dev, channel->dma_irq, channel); | |
872 | ||
e78332b2 LT |
873 | if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) |
874 | devm_free_irq(pdata->dev, pdata->ecc_irq, pdata); | |
875 | ||
876 | err_dev_irq: | |
c30e76a7 LT |
877 | devm_free_irq(pdata->dev, pdata->dev_irq, pdata); |
878 | ||
879 | return ret; | |
880 | } | |
881 | ||
882 | static void xgbe_free_irqs(struct xgbe_prv_data *pdata) | |
883 | { | |
884 | struct xgbe_channel *channel; | |
885 | unsigned int i; | |
886 | ||
887 | devm_free_irq(pdata->dev, pdata->dev_irq, pdata); | |
888 | ||
e78332b2 LT |
889 | if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) |
890 | devm_free_irq(pdata->dev, pdata->ecc_irq, pdata); | |
891 | ||
c30e76a7 LT |
892 | if (!pdata->per_channel_irq) |
893 | return; | |
894 | ||
895 | channel = pdata->channel; | |
896 | for (i = 0; i < pdata->channel_count; i++, channel++) | |
897 | devm_free_irq(pdata->dev, channel->dma_irq, channel); | |
898 | } | |
899 | ||
c5aa9e3b LT |
900 | void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata) |
901 | { | |
902 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
903 | ||
904 | DBGPR("-->xgbe_init_tx_coalesce\n"); | |
905 | ||
906 | pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS; | |
907 | pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES; | |
908 | ||
909 | hw_if->config_tx_coalesce(pdata); | |
910 | ||
911 | DBGPR("<--xgbe_init_tx_coalesce\n"); | |
912 | } | |
913 | ||
914 | void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata) | |
915 | { | |
916 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
917 | ||
918 | DBGPR("-->xgbe_init_rx_coalesce\n"); | |
919 | ||
920 | pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS); | |
4a57ebcc | 921 | pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS; |
c5aa9e3b LT |
922 | pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES; |
923 | ||
924 | hw_if->config_rx_coalesce(pdata); | |
925 | ||
926 | DBGPR("<--xgbe_init_rx_coalesce\n"); | |
927 | } | |
928 | ||
08dcc47c | 929 | static void xgbe_free_tx_data(struct xgbe_prv_data *pdata) |
c5aa9e3b LT |
930 | { |
931 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
932 | struct xgbe_channel *channel; | |
933 | struct xgbe_ring *ring; | |
934 | struct xgbe_ring_data *rdata; | |
935 | unsigned int i, j; | |
936 | ||
08dcc47c | 937 | DBGPR("-->xgbe_free_tx_data\n"); |
c5aa9e3b LT |
938 | |
939 | channel = pdata->channel; | |
940 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
941 | ring = channel->tx_ring; | |
942 | if (!ring) | |
943 | break; | |
944 | ||
945 | for (j = 0; j < ring->rdesc_count; j++) { | |
d0a8ba6c | 946 | rdata = XGBE_GET_DESC_DATA(ring, j); |
08dcc47c | 947 | desc_if->unmap_rdata(pdata, rdata); |
c5aa9e3b LT |
948 | } |
949 | } | |
950 | ||
08dcc47c | 951 | DBGPR("<--xgbe_free_tx_data\n"); |
c5aa9e3b LT |
952 | } |
953 | ||
08dcc47c | 954 | static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) |
c5aa9e3b LT |
955 | { |
956 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
957 | struct xgbe_channel *channel; | |
958 | struct xgbe_ring *ring; | |
959 | struct xgbe_ring_data *rdata; | |
960 | unsigned int i, j; | |
961 | ||
08dcc47c | 962 | DBGPR("-->xgbe_free_rx_data\n"); |
c5aa9e3b LT |
963 | |
964 | channel = pdata->channel; | |
965 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
966 | ring = channel->rx_ring; | |
967 | if (!ring) | |
968 | break; | |
969 | ||
970 | for (j = 0; j < ring->rdesc_count; j++) { | |
d0a8ba6c | 971 | rdata = XGBE_GET_DESC_DATA(ring, j); |
08dcc47c | 972 | desc_if->unmap_rdata(pdata, rdata); |
c5aa9e3b LT |
973 | } |
974 | } | |
975 | ||
08dcc47c | 976 | DBGPR("<--xgbe_free_rx_data\n"); |
c5aa9e3b LT |
977 | } |
978 | ||
e57f7a3f | 979 | static int xgbe_phy_reset(struct xgbe_prv_data *pdata) |
88131a81 | 980 | { |
88131a81 LT |
981 | pdata->phy_link = -1; |
982 | pdata->phy_speed = SPEED_UNKNOWN; | |
88131a81 | 983 | |
7c12aa08 | 984 | return pdata->phy_if.phy_reset(pdata); |
88131a81 LT |
985 | } |
986 | ||
c5aa9e3b LT |
987 | int xgbe_powerdown(struct net_device *netdev, unsigned int caller) |
988 | { | |
989 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
990 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
991 | unsigned long flags; | |
992 | ||
993 | DBGPR("-->xgbe_powerdown\n"); | |
994 | ||
995 | if (!netif_running(netdev) || | |
996 | (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) { | |
997 | netdev_alert(netdev, "Device is already powered down\n"); | |
998 | DBGPR("<--xgbe_powerdown\n"); | |
999 | return -EINVAL; | |
1000 | } | |
1001 | ||
c5aa9e3b LT |
1002 | spin_lock_irqsave(&pdata->lock, flags); |
1003 | ||
1004 | if (caller == XGMAC_DRIVER_CONTEXT) | |
1005 | netif_device_detach(netdev); | |
1006 | ||
1007 | netif_tx_stop_all_queues(netdev); | |
c5aa9e3b | 1008 | |
7c12aa08 LT |
1009 | xgbe_stop_timers(pdata); |
1010 | flush_workqueue(pdata->dev_workqueue); | |
1011 | ||
c5aa9e3b LT |
1012 | hw_if->powerdown_tx(pdata); |
1013 | hw_if->powerdown_rx(pdata); | |
1014 | ||
c30e76a7 LT |
1015 | xgbe_napi_disable(pdata, 0); |
1016 | ||
c5aa9e3b LT |
1017 | pdata->power_down = 1; |
1018 | ||
1019 | spin_unlock_irqrestore(&pdata->lock, flags); | |
1020 | ||
1021 | DBGPR("<--xgbe_powerdown\n"); | |
1022 | ||
1023 | return 0; | |
1024 | } | |
1025 | ||
1026 | int xgbe_powerup(struct net_device *netdev, unsigned int caller) | |
1027 | { | |
1028 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1029 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1030 | unsigned long flags; | |
1031 | ||
1032 | DBGPR("-->xgbe_powerup\n"); | |
1033 | ||
1034 | if (!netif_running(netdev) || | |
1035 | (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) { | |
1036 | netdev_alert(netdev, "Device is already powered up\n"); | |
1037 | DBGPR("<--xgbe_powerup\n"); | |
1038 | return -EINVAL; | |
1039 | } | |
1040 | ||
1041 | spin_lock_irqsave(&pdata->lock, flags); | |
1042 | ||
1043 | pdata->power_down = 0; | |
1044 | ||
c30e76a7 LT |
1045 | xgbe_napi_enable(pdata, 0); |
1046 | ||
c5aa9e3b LT |
1047 | hw_if->powerup_tx(pdata); |
1048 | hw_if->powerup_rx(pdata); | |
1049 | ||
1050 | if (caller == XGMAC_DRIVER_CONTEXT) | |
1051 | netif_device_attach(netdev); | |
1052 | ||
c5aa9e3b LT |
1053 | netif_tx_start_all_queues(netdev); |
1054 | ||
7c12aa08 LT |
1055 | xgbe_start_timers(pdata); |
1056 | ||
c5aa9e3b LT |
1057 | spin_unlock_irqrestore(&pdata->lock, flags); |
1058 | ||
1059 | DBGPR("<--xgbe_powerup\n"); | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | static int xgbe_start(struct xgbe_prv_data *pdata) | |
1065 | { | |
1066 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
7c12aa08 | 1067 | struct xgbe_phy_if *phy_if = &pdata->phy_if; |
c5aa9e3b | 1068 | struct net_device *netdev = pdata->netdev; |
c30e76a7 | 1069 | int ret; |
c5aa9e3b LT |
1070 | |
1071 | DBGPR("-->xgbe_start\n"); | |
1072 | ||
738f7f64 LT |
1073 | ret = hw_if->init(pdata); |
1074 | if (ret) | |
1075 | return ret; | |
c5aa9e3b | 1076 | |
c30e76a7 LT |
1077 | xgbe_napi_enable(pdata, 1); |
1078 | ||
1079 | ret = xgbe_request_irqs(pdata); | |
1080 | if (ret) | |
1081 | goto err_napi; | |
1082 | ||
47f164de LT |
1083 | ret = phy_if->phy_start(pdata); |
1084 | if (ret) | |
1085 | goto err_irqs; | |
1086 | ||
c5aa9e3b LT |
1087 | hw_if->enable_tx(pdata); |
1088 | hw_if->enable_rx(pdata); | |
1089 | ||
c5aa9e3b LT |
1090 | netif_tx_start_all_queues(netdev); |
1091 | ||
7c12aa08 | 1092 | xgbe_start_timers(pdata); |
afb43e8a | 1093 | queue_work(pdata->dev_workqueue, &pdata->service_work); |
7c12aa08 | 1094 | |
e78332b2 LT |
1095 | clear_bit(XGBE_STOPPED, &pdata->dev_state); |
1096 | ||
c5aa9e3b LT |
1097 | DBGPR("<--xgbe_start\n"); |
1098 | ||
1099 | return 0; | |
c30e76a7 | 1100 | |
47f164de LT |
1101 | err_irqs: |
1102 | xgbe_free_irqs(pdata); | |
1103 | ||
c30e76a7 LT |
1104 | err_napi: |
1105 | xgbe_napi_disable(pdata, 1); | |
1106 | ||
c30e76a7 LT |
1107 | hw_if->exit(pdata); |
1108 | ||
1109 | return ret; | |
c5aa9e3b LT |
1110 | } |
1111 | ||
1112 | static void xgbe_stop(struct xgbe_prv_data *pdata) | |
1113 | { | |
1114 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
7c12aa08 | 1115 | struct xgbe_phy_if *phy_if = &pdata->phy_if; |
5fb4b86a | 1116 | struct xgbe_channel *channel; |
c5aa9e3b | 1117 | struct net_device *netdev = pdata->netdev; |
5fb4b86a LT |
1118 | struct netdev_queue *txq; |
1119 | unsigned int i; | |
c5aa9e3b LT |
1120 | |
1121 | DBGPR("-->xgbe_stop\n"); | |
1122 | ||
e78332b2 LT |
1123 | if (test_bit(XGBE_STOPPED, &pdata->dev_state)) |
1124 | return; | |
1125 | ||
c5aa9e3b | 1126 | netif_tx_stop_all_queues(netdev); |
c5aa9e3b | 1127 | |
7c12aa08 LT |
1128 | xgbe_stop_timers(pdata); |
1129 | flush_workqueue(pdata->dev_workqueue); | |
c5aa9e3b LT |
1130 | |
1131 | hw_if->disable_tx(pdata); | |
1132 | hw_if->disable_rx(pdata); | |
1133 | ||
402168b4 LT |
1134 | phy_if->phy_stop(pdata); |
1135 | ||
c30e76a7 LT |
1136 | xgbe_free_irqs(pdata); |
1137 | ||
1138 | xgbe_napi_disable(pdata, 1); | |
1139 | ||
c30e76a7 LT |
1140 | hw_if->exit(pdata); |
1141 | ||
5fb4b86a LT |
1142 | channel = pdata->channel; |
1143 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
1144 | if (!channel->tx_ring) | |
1145 | continue; | |
1146 | ||
1147 | txq = netdev_get_tx_queue(netdev, channel->queue_index); | |
1148 | netdev_tx_reset_queue(txq); | |
1149 | } | |
1150 | ||
e78332b2 LT |
1151 | set_bit(XGBE_STOPPED, &pdata->dev_state); |
1152 | ||
c5aa9e3b LT |
1153 | DBGPR("<--xgbe_stop\n"); |
1154 | } | |
1155 | ||
e78332b2 LT |
1156 | static void xgbe_stopdev(struct work_struct *work) |
1157 | { | |
1158 | struct xgbe_prv_data *pdata = container_of(work, | |
1159 | struct xgbe_prv_data, | |
1160 | stopdev_work); | |
1161 | ||
1162 | rtnl_lock(); | |
1163 | ||
1164 | xgbe_stop(pdata); | |
1165 | ||
1166 | xgbe_free_tx_data(pdata); | |
1167 | xgbe_free_rx_data(pdata); | |
1168 | ||
1169 | rtnl_unlock(); | |
1170 | ||
1171 | netdev_alert(pdata->netdev, "device stopped\n"); | |
1172 | } | |
1173 | ||
916102c6 | 1174 | static void xgbe_restart_dev(struct xgbe_prv_data *pdata) |
c5aa9e3b | 1175 | { |
c5aa9e3b LT |
1176 | DBGPR("-->xgbe_restart_dev\n"); |
1177 | ||
1178 | /* If not running, "restart" will happen on open */ | |
1179 | if (!netif_running(pdata->netdev)) | |
1180 | return; | |
1181 | ||
1182 | xgbe_stop(pdata); | |
c5aa9e3b | 1183 | |
08dcc47c LT |
1184 | xgbe_free_tx_data(pdata); |
1185 | xgbe_free_rx_data(pdata); | |
c5aa9e3b | 1186 | |
c5aa9e3b LT |
1187 | xgbe_start(pdata); |
1188 | ||
1189 | DBGPR("<--xgbe_restart_dev\n"); | |
1190 | } | |
1191 | ||
1192 | static void xgbe_restart(struct work_struct *work) | |
1193 | { | |
1194 | struct xgbe_prv_data *pdata = container_of(work, | |
1195 | struct xgbe_prv_data, | |
1196 | restart_work); | |
1197 | ||
1198 | rtnl_lock(); | |
1199 | ||
916102c6 | 1200 | xgbe_restart_dev(pdata); |
c5aa9e3b LT |
1201 | |
1202 | rtnl_unlock(); | |
1203 | } | |
1204 | ||
23e4eef7 LT |
1205 | static void xgbe_tx_tstamp(struct work_struct *work) |
1206 | { | |
1207 | struct xgbe_prv_data *pdata = container_of(work, | |
1208 | struct xgbe_prv_data, | |
1209 | tx_tstamp_work); | |
1210 | struct skb_shared_hwtstamps hwtstamps; | |
1211 | u64 nsec; | |
1212 | unsigned long flags; | |
1213 | ||
1214 | if (pdata->tx_tstamp) { | |
1215 | nsec = timecounter_cyc2time(&pdata->tstamp_tc, | |
1216 | pdata->tx_tstamp); | |
1217 | ||
1218 | memset(&hwtstamps, 0, sizeof(hwtstamps)); | |
1219 | hwtstamps.hwtstamp = ns_to_ktime(nsec); | |
1220 | skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); | |
1221 | } | |
1222 | ||
1223 | dev_kfree_skb_any(pdata->tx_tstamp_skb); | |
1224 | ||
1225 | spin_lock_irqsave(&pdata->tstamp_lock, flags); | |
1226 | pdata->tx_tstamp_skb = NULL; | |
1227 | spin_unlock_irqrestore(&pdata->tstamp_lock, flags); | |
1228 | } | |
1229 | ||
1230 | static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, | |
1231 | struct ifreq *ifreq) | |
1232 | { | |
1233 | if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, | |
1234 | sizeof(pdata->tstamp_config))) | |
1235 | return -EFAULT; | |
1236 | ||
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, | |
1241 | struct ifreq *ifreq) | |
1242 | { | |
1243 | struct hwtstamp_config config; | |
1244 | unsigned int mac_tscr; | |
1245 | ||
1246 | if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) | |
1247 | return -EFAULT; | |
1248 | ||
1249 | if (config.flags) | |
1250 | return -EINVAL; | |
1251 | ||
1252 | mac_tscr = 0; | |
1253 | ||
1254 | switch (config.tx_type) { | |
1255 | case HWTSTAMP_TX_OFF: | |
1256 | break; | |
1257 | ||
1258 | case HWTSTAMP_TX_ON: | |
1259 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1260 | break; | |
1261 | ||
1262 | default: | |
1263 | return -ERANGE; | |
1264 | } | |
1265 | ||
1266 | switch (config.rx_filter) { | |
1267 | case HWTSTAMP_FILTER_NONE: | |
1268 | break; | |
1269 | ||
1270 | case HWTSTAMP_FILTER_ALL: | |
1271 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); | |
1272 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1273 | break; | |
1274 | ||
1275 | /* PTP v2, UDP, any kind of event packet */ | |
1276 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1277 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1278 | /* PTP v1, UDP, any kind of event packet */ | |
1279 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
1280 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1281 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1282 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); | |
1283 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1284 | break; | |
1285 | ||
1286 | /* PTP v2, UDP, Sync packet */ | |
1287 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
1288 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1289 | /* PTP v1, UDP, Sync packet */ | |
1290 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
1291 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1292 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1293 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1294 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1295 | break; | |
1296 | ||
1297 | /* PTP v2, UDP, Delay_req packet */ | |
1298 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
1299 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1300 | /* PTP v1, UDP, Delay_req packet */ | |
1301 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1302 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1303 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1304 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1305 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); | |
1306 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1307 | break; | |
1308 | ||
1309 | /* 802.AS1, Ethernet, any kind of event packet */ | |
1310 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1311 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); | |
1312 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); | |
1313 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1314 | break; | |
1315 | ||
1316 | /* 802.AS1, Ethernet, Sync packet */ | |
1317 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
1318 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); | |
1319 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1320 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1321 | break; | |
1322 | ||
1323 | /* 802.AS1, Ethernet, Delay_req packet */ | |
1324 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
1325 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); | |
1326 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); | |
1327 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1328 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1329 | break; | |
1330 | ||
1331 | /* PTP v2/802.AS1, any layer, any kind of event packet */ | |
1332 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
1333 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1334 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); | |
1335 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1336 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1337 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); | |
1338 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1339 | break; | |
1340 | ||
1341 | /* PTP v2/802.AS1, any layer, Sync packet */ | |
1342 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
1343 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1344 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); | |
1345 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1346 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1347 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1348 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1349 | break; | |
1350 | ||
1351 | /* PTP v2/802.AS1, any layer, Delay_req packet */ | |
1352 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
1353 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1354 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); | |
1355 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1356 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1357 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); | |
1358 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1359 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1360 | break; | |
1361 | ||
1362 | default: | |
1363 | return -ERANGE; | |
1364 | } | |
1365 | ||
1366 | pdata->hw_if.config_tstamp(pdata, mac_tscr); | |
1367 | ||
1368 | memcpy(&pdata->tstamp_config, &config, sizeof(config)); | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, | |
1374 | struct sk_buff *skb, | |
1375 | struct xgbe_packet_data *packet) | |
1376 | { | |
1377 | unsigned long flags; | |
1378 | ||
1379 | if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { | |
1380 | spin_lock_irqsave(&pdata->tstamp_lock, flags); | |
1381 | if (pdata->tx_tstamp_skb) { | |
1382 | /* Another timestamp in progress, ignore this one */ | |
1383 | XGMAC_SET_BITS(packet->attributes, | |
1384 | TX_PACKET_ATTRIBUTES, PTP, 0); | |
1385 | } else { | |
1386 | pdata->tx_tstamp_skb = skb_get(skb); | |
1387 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
1388 | } | |
1389 | spin_unlock_irqrestore(&pdata->tstamp_lock, flags); | |
1390 | } | |
1391 | ||
1392 | if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) | |
1393 | skb_tx_timestamp(skb); | |
1394 | } | |
1395 | ||
c5aa9e3b LT |
1396 | static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet) |
1397 | { | |
df8a39de JP |
1398 | if (skb_vlan_tag_present(skb)) |
1399 | packet->vlan_ctag = skb_vlan_tag_get(skb); | |
c5aa9e3b LT |
1400 | } |
1401 | ||
1402 | static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet) | |
1403 | { | |
1404 | int ret; | |
1405 | ||
1406 | if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1407 | TSO_ENABLE)) | |
1408 | return 0; | |
1409 | ||
1410 | ret = skb_cow_head(skb, 0); | |
1411 | if (ret) | |
1412 | return ret; | |
1413 | ||
1414 | packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
1415 | packet->tcp_header_len = tcp_hdrlen(skb); | |
1416 | packet->tcp_payload_len = skb->len - packet->header_len; | |
1417 | packet->mss = skb_shinfo(skb)->gso_size; | |
1418 | DBGPR(" packet->header_len=%u\n", packet->header_len); | |
1419 | DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n", | |
1420 | packet->tcp_header_len, packet->tcp_payload_len); | |
1421 | DBGPR(" packet->mss=%u\n", packet->mss); | |
1422 | ||
5fb4b86a LT |
1423 | /* Update the number of packets that will ultimately be transmitted |
1424 | * along with the extra bytes for each extra packet | |
1425 | */ | |
1426 | packet->tx_packets = skb_shinfo(skb)->gso_segs; | |
1427 | packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len; | |
1428 | ||
c5aa9e3b LT |
1429 | return 0; |
1430 | } | |
1431 | ||
1432 | static int xgbe_is_tso(struct sk_buff *skb) | |
1433 | { | |
1434 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
1435 | return 0; | |
1436 | ||
1437 | if (!skb_is_gso(skb)) | |
1438 | return 0; | |
1439 | ||
1440 | DBGPR(" TSO packet to be processed\n"); | |
1441 | ||
1442 | return 1; | |
1443 | } | |
1444 | ||
23e4eef7 LT |
1445 | static void xgbe_packet_info(struct xgbe_prv_data *pdata, |
1446 | struct xgbe_ring *ring, struct sk_buff *skb, | |
c5aa9e3b LT |
1447 | struct xgbe_packet_data *packet) |
1448 | { | |
1449 | struct skb_frag_struct *frag; | |
1450 | unsigned int context_desc; | |
1451 | unsigned int len; | |
1452 | unsigned int i; | |
1453 | ||
16958a2b LT |
1454 | packet->skb = skb; |
1455 | ||
c5aa9e3b LT |
1456 | context_desc = 0; |
1457 | packet->rdesc_count = 0; | |
1458 | ||
5fb4b86a LT |
1459 | packet->tx_packets = 1; |
1460 | packet->tx_bytes = skb->len; | |
1461 | ||
c5aa9e3b | 1462 | if (xgbe_is_tso(skb)) { |
a7beaf23 | 1463 | /* TSO requires an extra descriptor if mss is different */ |
c5aa9e3b LT |
1464 | if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) { |
1465 | context_desc = 1; | |
1466 | packet->rdesc_count++; | |
1467 | } | |
1468 | ||
a7beaf23 | 1469 | /* TSO requires an extra descriptor for TSO header */ |
c5aa9e3b LT |
1470 | packet->rdesc_count++; |
1471 | ||
1472 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1473 | TSO_ENABLE, 1); | |
1474 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1475 | CSUM_ENABLE, 1); | |
1476 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) | |
1477 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1478 | CSUM_ENABLE, 1); | |
1479 | ||
df8a39de | 1480 | if (skb_vlan_tag_present(skb)) { |
c5aa9e3b | 1481 | /* VLAN requires an extra descriptor if tag is different */ |
df8a39de | 1482 | if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag) |
c5aa9e3b LT |
1483 | /* We can share with the TSO context descriptor */ |
1484 | if (!context_desc) { | |
1485 | context_desc = 1; | |
1486 | packet->rdesc_count++; | |
1487 | } | |
1488 | ||
1489 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1490 | VLAN_CTAG, 1); | |
1491 | } | |
1492 | ||
23e4eef7 LT |
1493 | if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
1494 | (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON)) | |
1495 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1496 | PTP, 1); | |
1497 | ||
c5aa9e3b LT |
1498 | for (len = skb_headlen(skb); len;) { |
1499 | packet->rdesc_count++; | |
d0a8ba6c | 1500 | len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); |
c5aa9e3b LT |
1501 | } |
1502 | ||
1503 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1504 | frag = &skb_shinfo(skb)->frags[i]; | |
1505 | for (len = skb_frag_size(frag); len; ) { | |
1506 | packet->rdesc_count++; | |
d0a8ba6c | 1507 | len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); |
c5aa9e3b LT |
1508 | } |
1509 | } | |
1510 | } | |
1511 | ||
1512 | static int xgbe_open(struct net_device *netdev) | |
1513 | { | |
1514 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
c5aa9e3b LT |
1515 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
1516 | int ret; | |
1517 | ||
1518 | DBGPR("-->xgbe_open\n"); | |
1519 | ||
e57f7a3f LT |
1520 | /* Reset the phy settings */ |
1521 | ret = xgbe_phy_reset(pdata); | |
88131a81 LT |
1522 | if (ret) |
1523 | return ret; | |
1524 | ||
23e4eef7 LT |
1525 | /* Enable the clocks */ |
1526 | ret = clk_prepare_enable(pdata->sysclk); | |
c5aa9e3b | 1527 | if (ret) { |
23e4eef7 | 1528 | netdev_alert(netdev, "dma clk_prepare_enable failed\n"); |
7c12aa08 | 1529 | return ret; |
c5aa9e3b LT |
1530 | } |
1531 | ||
23e4eef7 LT |
1532 | ret = clk_prepare_enable(pdata->ptpclk); |
1533 | if (ret) { | |
1534 | netdev_alert(netdev, "ptp clk_prepare_enable failed\n"); | |
1535 | goto err_sysclk; | |
1536 | } | |
1537 | ||
c5aa9e3b LT |
1538 | /* Calculate the Rx buffer size before allocating rings */ |
1539 | ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu); | |
1540 | if (ret < 0) | |
23e4eef7 | 1541 | goto err_ptpclk; |
c5aa9e3b LT |
1542 | pdata->rx_buf_size = ret; |
1543 | ||
4780b7ca LT |
1544 | /* Allocate the channel and ring structures */ |
1545 | ret = xgbe_alloc_channels(pdata); | |
1546 | if (ret) | |
1547 | goto err_ptpclk; | |
1548 | ||
c5aa9e3b LT |
1549 | /* Allocate the ring descriptors and buffers */ |
1550 | ret = desc_if->alloc_ring_resources(pdata); | |
1551 | if (ret) | |
4780b7ca | 1552 | goto err_channels; |
c5aa9e3b | 1553 | |
7c12aa08 | 1554 | INIT_WORK(&pdata->service_work, xgbe_service); |
c5aa9e3b | 1555 | INIT_WORK(&pdata->restart_work, xgbe_restart); |
e78332b2 | 1556 | INIT_WORK(&pdata->stopdev_work, xgbe_stopdev); |
23e4eef7 | 1557 | INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); |
7c12aa08 | 1558 | xgbe_init_timers(pdata); |
c5aa9e3b | 1559 | |
c5aa9e3b LT |
1560 | ret = xgbe_start(pdata); |
1561 | if (ret) | |
c30e76a7 | 1562 | goto err_rings; |
c5aa9e3b | 1563 | |
7c12aa08 LT |
1564 | clear_bit(XGBE_DOWN, &pdata->dev_state); |
1565 | ||
c5aa9e3b LT |
1566 | DBGPR("<--xgbe_open\n"); |
1567 | ||
1568 | return 0; | |
1569 | ||
4780b7ca | 1570 | err_rings: |
c5aa9e3b LT |
1571 | desc_if->free_ring_resources(pdata); |
1572 | ||
4780b7ca LT |
1573 | err_channels: |
1574 | xgbe_free_channels(pdata); | |
1575 | ||
23e4eef7 LT |
1576 | err_ptpclk: |
1577 | clk_disable_unprepare(pdata->ptpclk); | |
1578 | ||
1579 | err_sysclk: | |
1580 | clk_disable_unprepare(pdata->sysclk); | |
c5aa9e3b LT |
1581 | |
1582 | return ret; | |
1583 | } | |
1584 | ||
1585 | static int xgbe_close(struct net_device *netdev) | |
1586 | { | |
1587 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
c5aa9e3b LT |
1588 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
1589 | ||
1590 | DBGPR("-->xgbe_close\n"); | |
1591 | ||
1592 | /* Stop the device */ | |
1593 | xgbe_stop(pdata); | |
1594 | ||
4780b7ca | 1595 | /* Free the ring descriptors and buffers */ |
c5aa9e3b LT |
1596 | desc_if->free_ring_resources(pdata); |
1597 | ||
e98c72c9 LT |
1598 | /* Free the channel and ring structures */ |
1599 | xgbe_free_channels(pdata); | |
1600 | ||
23e4eef7 LT |
1601 | /* Disable the clocks */ |
1602 | clk_disable_unprepare(pdata->ptpclk); | |
1603 | clk_disable_unprepare(pdata->sysclk); | |
c5aa9e3b | 1604 | |
7c12aa08 | 1605 | set_bit(XGBE_DOWN, &pdata->dev_state); |
88131a81 | 1606 | |
c5aa9e3b LT |
1607 | DBGPR("<--xgbe_close\n"); |
1608 | ||
1609 | return 0; | |
1610 | } | |
1611 | ||
1612 | static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) | |
1613 | { | |
1614 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1615 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1616 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
1617 | struct xgbe_channel *channel; | |
1618 | struct xgbe_ring *ring; | |
1619 | struct xgbe_packet_data *packet; | |
5fb4b86a | 1620 | struct netdev_queue *txq; |
c5aa9e3b LT |
1621 | int ret; |
1622 | ||
1623 | DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); | |
1624 | ||
1625 | channel = pdata->channel + skb->queue_mapping; | |
5fb4b86a | 1626 | txq = netdev_get_tx_queue(netdev, channel->queue_index); |
c5aa9e3b LT |
1627 | ring = channel->tx_ring; |
1628 | packet = &ring->packet_data; | |
1629 | ||
1630 | ret = NETDEV_TX_OK; | |
1631 | ||
c5aa9e3b | 1632 | if (skb->len == 0) { |
34bf65df LT |
1633 | netif_err(pdata, tx_err, netdev, |
1634 | "empty skb received from stack\n"); | |
c5aa9e3b LT |
1635 | dev_kfree_skb_any(skb); |
1636 | goto tx_netdev_return; | |
1637 | } | |
1638 | ||
1639 | /* Calculate preliminary packet info */ | |
1640 | memset(packet, 0, sizeof(*packet)); | |
23e4eef7 | 1641 | xgbe_packet_info(pdata, ring, skb, packet); |
c5aa9e3b LT |
1642 | |
1643 | /* Check that there are enough descriptors available */ | |
16958a2b LT |
1644 | ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count); |
1645 | if (ret) | |
c5aa9e3b | 1646 | goto tx_netdev_return; |
c5aa9e3b LT |
1647 | |
1648 | ret = xgbe_prep_tso(skb, packet); | |
1649 | if (ret) { | |
34bf65df LT |
1650 | netif_err(pdata, tx_err, netdev, |
1651 | "error processing TSO packet\n"); | |
c5aa9e3b LT |
1652 | dev_kfree_skb_any(skb); |
1653 | goto tx_netdev_return; | |
1654 | } | |
1655 | xgbe_prep_vlan(skb, packet); | |
1656 | ||
1657 | if (!desc_if->map_tx_skb(channel, skb)) { | |
1658 | dev_kfree_skb_any(skb); | |
1659 | goto tx_netdev_return; | |
1660 | } | |
1661 | ||
23e4eef7 LT |
1662 | xgbe_prep_tx_tstamp(pdata, skb, packet); |
1663 | ||
5fb4b86a LT |
1664 | /* Report on the actual number of bytes (to be) sent */ |
1665 | netdev_tx_sent_queue(txq, packet->tx_bytes); | |
1666 | ||
c5aa9e3b | 1667 | /* Configure required descriptor fields for transmission */ |
a9d41981 | 1668 | hw_if->dev_xmit(channel); |
c5aa9e3b | 1669 | |
34bf65df LT |
1670 | if (netif_msg_pktdata(pdata)) |
1671 | xgbe_print_pkt(netdev, skb, true); | |
c5aa9e3b | 1672 | |
16958a2b LT |
1673 | /* Stop the queue in advance if there may not be enough descriptors */ |
1674 | xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS); | |
1675 | ||
1676 | ret = NETDEV_TX_OK; | |
1677 | ||
c5aa9e3b | 1678 | tx_netdev_return: |
c5aa9e3b LT |
1679 | return ret; |
1680 | } | |
1681 | ||
1682 | static void xgbe_set_rx_mode(struct net_device *netdev) | |
1683 | { | |
1684 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1685 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
c5aa9e3b LT |
1686 | |
1687 | DBGPR("-->xgbe_set_rx_mode\n"); | |
1688 | ||
b876382b | 1689 | hw_if->config_rx_mode(pdata); |
c5aa9e3b LT |
1690 | |
1691 | DBGPR("<--xgbe_set_rx_mode\n"); | |
1692 | } | |
1693 | ||
1694 | static int xgbe_set_mac_address(struct net_device *netdev, void *addr) | |
1695 | { | |
1696 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1697 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1698 | struct sockaddr *saddr = addr; | |
1699 | ||
1700 | DBGPR("-->xgbe_set_mac_address\n"); | |
1701 | ||
1702 | if (!is_valid_ether_addr(saddr->sa_data)) | |
1703 | return -EADDRNOTAVAIL; | |
1704 | ||
1705 | memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len); | |
1706 | ||
1707 | hw_if->set_mac_address(pdata, netdev->dev_addr); | |
1708 | ||
1709 | DBGPR("<--xgbe_set_mac_address\n"); | |
1710 | ||
1711 | return 0; | |
1712 | } | |
1713 | ||
23e4eef7 LT |
1714 | static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd) |
1715 | { | |
1716 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1717 | int ret; | |
1718 | ||
1719 | switch (cmd) { | |
1720 | case SIOCGHWTSTAMP: | |
1721 | ret = xgbe_get_hwtstamp_settings(pdata, ifreq); | |
1722 | break; | |
1723 | ||
1724 | case SIOCSHWTSTAMP: | |
1725 | ret = xgbe_set_hwtstamp_settings(pdata, ifreq); | |
1726 | break; | |
1727 | ||
1728 | default: | |
1729 | ret = -EOPNOTSUPP; | |
1730 | } | |
1731 | ||
1732 | return ret; | |
1733 | } | |
1734 | ||
c5aa9e3b LT |
1735 | static int xgbe_change_mtu(struct net_device *netdev, int mtu) |
1736 | { | |
1737 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1738 | int ret; | |
1739 | ||
1740 | DBGPR("-->xgbe_change_mtu\n"); | |
1741 | ||
1742 | ret = xgbe_calc_rx_buf_size(netdev, mtu); | |
1743 | if (ret < 0) | |
1744 | return ret; | |
1745 | ||
1746 | pdata->rx_buf_size = ret; | |
1747 | netdev->mtu = mtu; | |
1748 | ||
916102c6 | 1749 | xgbe_restart_dev(pdata); |
c5aa9e3b LT |
1750 | |
1751 | DBGPR("<--xgbe_change_mtu\n"); | |
1752 | ||
1753 | return 0; | |
1754 | } | |
1755 | ||
a8373f1a LT |
1756 | static void xgbe_tx_timeout(struct net_device *netdev) |
1757 | { | |
1758 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1759 | ||
1760 | netdev_warn(netdev, "tx timeout, device restarting\n"); | |
96aec911 | 1761 | schedule_work(&pdata->restart_work); |
a8373f1a LT |
1762 | } |
1763 | ||
bc1f4470 | 1764 | static void xgbe_get_stats64(struct net_device *netdev, |
1765 | struct rtnl_link_stats64 *s) | |
c5aa9e3b LT |
1766 | { |
1767 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1768 | struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; | |
1769 | ||
1770 | DBGPR("-->%s\n", __func__); | |
1771 | ||
1772 | pdata->hw_if.read_mmc_stats(pdata); | |
1773 | ||
1774 | s->rx_packets = pstats->rxframecount_gb; | |
1775 | s->rx_bytes = pstats->rxoctetcount_gb; | |
1776 | s->rx_errors = pstats->rxframecount_gb - | |
1777 | pstats->rxbroadcastframes_g - | |
1778 | pstats->rxmulticastframes_g - | |
1779 | pstats->rxunicastframes_g; | |
1780 | s->multicast = pstats->rxmulticastframes_g; | |
1781 | s->rx_length_errors = pstats->rxlengtherror; | |
1782 | s->rx_crc_errors = pstats->rxcrcerror; | |
1783 | s->rx_fifo_errors = pstats->rxfifooverflow; | |
1784 | ||
1785 | s->tx_packets = pstats->txframecount_gb; | |
1786 | s->tx_bytes = pstats->txoctetcount_gb; | |
1787 | s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; | |
1788 | s->tx_dropped = netdev->stats.tx_dropped; | |
1789 | ||
1790 | DBGPR("<--%s\n", __func__); | |
c5aa9e3b LT |
1791 | } |
1792 | ||
801c62d9 LT |
1793 | static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, |
1794 | u16 vid) | |
1795 | { | |
1796 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1797 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1798 | ||
1799 | DBGPR("-->%s\n", __func__); | |
1800 | ||
1801 | set_bit(vid, pdata->active_vlans); | |
1802 | hw_if->update_vlan_hash_table(pdata); | |
1803 | ||
1804 | DBGPR("<--%s\n", __func__); | |
1805 | ||
1806 | return 0; | |
1807 | } | |
1808 | ||
1809 | static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, | |
1810 | u16 vid) | |
1811 | { | |
1812 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1813 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1814 | ||
1815 | DBGPR("-->%s\n", __func__); | |
1816 | ||
1817 | clear_bit(vid, pdata->active_vlans); | |
1818 | hw_if->update_vlan_hash_table(pdata); | |
1819 | ||
1820 | DBGPR("<--%s\n", __func__); | |
1821 | ||
1822 | return 0; | |
1823 | } | |
1824 | ||
c5aa9e3b LT |
1825 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1826 | static void xgbe_poll_controller(struct net_device *netdev) | |
1827 | { | |
1828 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
9227dc5e LT |
1829 | struct xgbe_channel *channel; |
1830 | unsigned int i; | |
c5aa9e3b LT |
1831 | |
1832 | DBGPR("-->xgbe_poll_controller\n"); | |
1833 | ||
9227dc5e LT |
1834 | if (pdata->per_channel_irq) { |
1835 | channel = pdata->channel; | |
1836 | for (i = 0; i < pdata->channel_count; i++, channel++) | |
1837 | xgbe_dma_isr(channel->dma_irq, channel); | |
1838 | } else { | |
1839 | disable_irq(pdata->dev_irq); | |
1840 | xgbe_isr(pdata->dev_irq, pdata); | |
1841 | enable_irq(pdata->dev_irq); | |
1842 | } | |
c5aa9e3b LT |
1843 | |
1844 | DBGPR("<--xgbe_poll_controller\n"); | |
1845 | } | |
1846 | #endif /* End CONFIG_NET_POLL_CONTROLLER */ | |
1847 | ||
16e5cc64 JF |
1848 | static int xgbe_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, |
1849 | struct tc_to_netdev *tc_to_netdev) | |
fca2d994 LT |
1850 | { |
1851 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
b3b71597 | 1852 | u8 tc; |
fca2d994 | 1853 | |
5eb4dce3 | 1854 | if (tc_to_netdev->type != TC_SETUP_MQPRIO) |
e4c6734e JF |
1855 | return -EINVAL; |
1856 | ||
16e5cc64 JF |
1857 | tc = tc_to_netdev->tc; |
1858 | ||
b3b71597 | 1859 | if (tc > pdata->hw_feat.tc_cnt) |
fca2d994 LT |
1860 | return -EINVAL; |
1861 | ||
b3b71597 LT |
1862 | pdata->num_tcs = tc; |
1863 | pdata->hw_if.config_tc(pdata); | |
fca2d994 LT |
1864 | |
1865 | return 0; | |
1866 | } | |
1867 | ||
c5aa9e3b LT |
1868 | static int xgbe_set_features(struct net_device *netdev, |
1869 | netdev_features_t features) | |
1870 | { | |
1871 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1872 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
5b9dfe29 LT |
1873 | netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter; |
1874 | int ret = 0; | |
c5aa9e3b | 1875 | |
5b9dfe29 | 1876 | rxhash = pdata->netdev_features & NETIF_F_RXHASH; |
801c62d9 LT |
1877 | rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; |
1878 | rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; | |
1879 | rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; | |
c5aa9e3b | 1880 | |
5b9dfe29 LT |
1881 | if ((features & NETIF_F_RXHASH) && !rxhash) |
1882 | ret = hw_if->enable_rss(pdata); | |
1883 | else if (!(features & NETIF_F_RXHASH) && rxhash) | |
1884 | ret = hw_if->disable_rss(pdata); | |
1885 | if (ret) | |
1886 | return ret; | |
1887 | ||
801c62d9 | 1888 | if ((features & NETIF_F_RXCSUM) && !rxcsum) |
c5aa9e3b | 1889 | hw_if->enable_rx_csum(pdata); |
801c62d9 | 1890 | else if (!(features & NETIF_F_RXCSUM) && rxcsum) |
c5aa9e3b | 1891 | hw_if->disable_rx_csum(pdata); |
c5aa9e3b | 1892 | |
801c62d9 | 1893 | if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) |
c5aa9e3b | 1894 | hw_if->enable_rx_vlan_stripping(pdata); |
801c62d9 | 1895 | else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) |
c5aa9e3b | 1896 | hw_if->disable_rx_vlan_stripping(pdata); |
801c62d9 LT |
1897 | |
1898 | if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) | |
1899 | hw_if->enable_rx_vlan_filtering(pdata); | |
1900 | else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) | |
1901 | hw_if->disable_rx_vlan_filtering(pdata); | |
c5aa9e3b LT |
1902 | |
1903 | pdata->netdev_features = features; | |
1904 | ||
1905 | DBGPR("<--xgbe_set_features\n"); | |
1906 | ||
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | static const struct net_device_ops xgbe_netdev_ops = { | |
1911 | .ndo_open = xgbe_open, | |
1912 | .ndo_stop = xgbe_close, | |
1913 | .ndo_start_xmit = xgbe_xmit, | |
1914 | .ndo_set_rx_mode = xgbe_set_rx_mode, | |
1915 | .ndo_set_mac_address = xgbe_set_mac_address, | |
1916 | .ndo_validate_addr = eth_validate_addr, | |
23e4eef7 | 1917 | .ndo_do_ioctl = xgbe_ioctl, |
c5aa9e3b | 1918 | .ndo_change_mtu = xgbe_change_mtu, |
a8373f1a | 1919 | .ndo_tx_timeout = xgbe_tx_timeout, |
c5aa9e3b | 1920 | .ndo_get_stats64 = xgbe_get_stats64, |
801c62d9 LT |
1921 | .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid, |
1922 | .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid, | |
c5aa9e3b LT |
1923 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1924 | .ndo_poll_controller = xgbe_poll_controller, | |
1925 | #endif | |
fca2d994 | 1926 | .ndo_setup_tc = xgbe_setup_tc, |
c5aa9e3b LT |
1927 | .ndo_set_features = xgbe_set_features, |
1928 | }; | |
1929 | ||
ce0b15d1 | 1930 | const struct net_device_ops *xgbe_get_netdev_ops(void) |
c5aa9e3b | 1931 | { |
ce0b15d1 | 1932 | return &xgbe_netdev_ops; |
c5aa9e3b LT |
1933 | } |
1934 | ||
9867e8fb LT |
1935 | static void xgbe_rx_refresh(struct xgbe_channel *channel) |
1936 | { | |
1937 | struct xgbe_prv_data *pdata = channel->pdata; | |
270894e7 | 1938 | struct xgbe_hw_if *hw_if = &pdata->hw_if; |
9867e8fb LT |
1939 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
1940 | struct xgbe_ring *ring = channel->rx_ring; | |
1941 | struct xgbe_ring_data *rdata; | |
1942 | ||
270894e7 LT |
1943 | while (ring->dirty != ring->cur) { |
1944 | rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); | |
1945 | ||
1946 | /* Reset rdata values */ | |
1947 | desc_if->unmap_rdata(pdata, rdata); | |
1948 | ||
1949 | if (desc_if->map_rx_buffer(pdata, ring, rdata)) | |
1950 | break; | |
1951 | ||
8dee19e6 | 1952 | hw_if->rx_desc_reset(pdata, rdata, ring->dirty); |
270894e7 LT |
1953 | |
1954 | ring->dirty++; | |
1955 | } | |
9867e8fb | 1956 | |
ceb8f6be LT |
1957 | /* Make sure everything is written before the register write */ |
1958 | wmb(); | |
1959 | ||
9867e8fb LT |
1960 | /* Update the Rx Tail Pointer Register with address of |
1961 | * the last cleaned entry */ | |
270894e7 | 1962 | rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); |
9867e8fb LT |
1963 | XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, |
1964 | lower_32_bits(rdata->rdesc_dma)); | |
1965 | } | |
1966 | ||
7d9ca345 LT |
1967 | static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata, |
1968 | struct napi_struct *napi, | |
08dcc47c | 1969 | struct xgbe_ring_data *rdata, |
7d9ca345 | 1970 | unsigned int len) |
08dcc47c | 1971 | { |
08dcc47c LT |
1972 | struct sk_buff *skb; |
1973 | u8 *packet; | |
08dcc47c | 1974 | |
385565a1 | 1975 | skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len); |
08dcc47c LT |
1976 | if (!skb) |
1977 | return NULL; | |
1978 | ||
622c36f1 | 1979 | /* Pull in the header buffer which may contain just the header |
7d9ca345 LT |
1980 | * or the header plus data |
1981 | */ | |
cfbfd86b LT |
1982 | dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base, |
1983 | rdata->rx.hdr.dma_off, | |
1984 | rdata->rx.hdr.dma_len, DMA_FROM_DEVICE); | |
7d9ca345 | 1985 | |
c9f140eb LT |
1986 | packet = page_address(rdata->rx.hdr.pa.pages) + |
1987 | rdata->rx.hdr.pa.pages_offset; | |
622c36f1 LT |
1988 | skb_copy_to_linear_data(skb, packet, len); |
1989 | skb_put(skb, len); | |
08dcc47c LT |
1990 | |
1991 | return skb; | |
1992 | } | |
1993 | ||
622c36f1 LT |
1994 | static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata, |
1995 | struct xgbe_packet_data *packet) | |
1996 | { | |
1997 | /* Always zero if not the first descriptor */ | |
1998 | if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST)) | |
1999 | return 0; | |
2000 | ||
2001 | /* First descriptor with split header, return header length */ | |
2002 | if (rdata->rx.hdr_len) | |
2003 | return rdata->rx.hdr_len; | |
2004 | ||
2005 | /* First descriptor but not the last descriptor and no split header, | |
2006 | * so the full buffer was used | |
2007 | */ | |
2008 | if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) | |
2009 | return rdata->rx.hdr.dma_len; | |
2010 | ||
2011 | /* First descriptor and last descriptor and no split header, so | |
2012 | * calculate how much of the buffer was used | |
2013 | */ | |
2014 | return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len); | |
2015 | } | |
2016 | ||
2017 | static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata, | |
2018 | struct xgbe_packet_data *packet, | |
2019 | unsigned int len) | |
2020 | { | |
2021 | /* Always the full buffer if not the last descriptor */ | |
2022 | if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) | |
2023 | return rdata->rx.buf.dma_len; | |
2024 | ||
2025 | /* Last descriptor so calculate how much of the buffer was used | |
2026 | * for the last bit of data | |
2027 | */ | |
2028 | return rdata->rx.len - len; | |
2029 | } | |
2030 | ||
c5aa9e3b LT |
2031 | static int xgbe_tx_poll(struct xgbe_channel *channel) |
2032 | { | |
2033 | struct xgbe_prv_data *pdata = channel->pdata; | |
2034 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
2035 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
2036 | struct xgbe_ring *ring = channel->tx_ring; | |
2037 | struct xgbe_ring_data *rdata; | |
2038 | struct xgbe_ring_desc *rdesc; | |
2039 | struct net_device *netdev = pdata->netdev; | |
5fb4b86a | 2040 | struct netdev_queue *txq; |
c5aa9e3b | 2041 | int processed = 0; |
5fb4b86a | 2042 | unsigned int tx_packets = 0, tx_bytes = 0; |
20a41fba | 2043 | unsigned int cur; |
c5aa9e3b LT |
2044 | |
2045 | DBGPR("-->xgbe_tx_poll\n"); | |
2046 | ||
2047 | /* Nothing to do if there isn't a Tx ring for this channel */ | |
2048 | if (!ring) | |
2049 | return 0; | |
2050 | ||
20a41fba | 2051 | cur = ring->cur; |
20986ed8 LT |
2052 | |
2053 | /* Be sure we get ring->cur before accessing descriptor data */ | |
2054 | smp_rmb(); | |
2055 | ||
5fb4b86a LT |
2056 | txq = netdev_get_tx_queue(netdev, channel->queue_index); |
2057 | ||
d0a8ba6c | 2058 | while ((processed < XGBE_TX_DESC_MAX_PROC) && |
20a41fba | 2059 | (ring->dirty != cur)) { |
d0a8ba6c | 2060 | rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); |
c5aa9e3b LT |
2061 | rdesc = rdata->rdesc; |
2062 | ||
2063 | if (!hw_if->tx_complete(rdesc)) | |
2064 | break; | |
2065 | ||
5449e271 LT |
2066 | /* Make sure descriptor fields are read after reading the OWN |
2067 | * bit */ | |
ceb8f6be | 2068 | dma_rmb(); |
5449e271 | 2069 | |
34bf65df LT |
2070 | if (netif_msg_tx_done(pdata)) |
2071 | xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0); | |
c5aa9e3b | 2072 | |
5fb4b86a LT |
2073 | if (hw_if->is_last_desc(rdesc)) { |
2074 | tx_packets += rdata->tx.packets; | |
2075 | tx_bytes += rdata->tx.bytes; | |
2076 | } | |
2077 | ||
c5aa9e3b | 2078 | /* Free the SKB and reset the descriptor for re-use */ |
08dcc47c | 2079 | desc_if->unmap_rdata(pdata, rdata); |
c5aa9e3b LT |
2080 | hw_if->tx_desc_reset(rdata); |
2081 | ||
2082 | processed++; | |
2083 | ring->dirty++; | |
2084 | } | |
2085 | ||
5fb4b86a | 2086 | if (!processed) |
a83ef427 | 2087 | return 0; |
5fb4b86a LT |
2088 | |
2089 | netdev_tx_completed_queue(txq, tx_packets, tx_bytes); | |
2090 | ||
c5aa9e3b | 2091 | if ((ring->tx.queue_stopped == 1) && |
d0a8ba6c | 2092 | (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) { |
c5aa9e3b | 2093 | ring->tx.queue_stopped = 0; |
5fb4b86a | 2094 | netif_tx_wake_queue(txq); |
c5aa9e3b LT |
2095 | } |
2096 | ||
2097 | DBGPR("<--xgbe_tx_poll: processed=%d\n", processed); | |
2098 | ||
c5aa9e3b LT |
2099 | return processed; |
2100 | } | |
2101 | ||
2102 | static int xgbe_rx_poll(struct xgbe_channel *channel, int budget) | |
2103 | { | |
2104 | struct xgbe_prv_data *pdata = channel->pdata; | |
2105 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
c5aa9e3b LT |
2106 | struct xgbe_ring *ring = channel->rx_ring; |
2107 | struct xgbe_ring_data *rdata; | |
2108 | struct xgbe_packet_data *packet; | |
2109 | struct net_device *netdev = pdata->netdev; | |
9227dc5e | 2110 | struct napi_struct *napi; |
c5aa9e3b | 2111 | struct sk_buff *skb; |
23e4eef7 | 2112 | struct skb_shared_hwtstamps *hwtstamps; |
622c36f1 LT |
2113 | unsigned int last, error, context_next, context; |
2114 | unsigned int len, buf1_len, buf2_len, max_len; | |
55ca6bcd LT |
2115 | unsigned int received = 0; |
2116 | int packet_count = 0; | |
c5aa9e3b LT |
2117 | |
2118 | DBGPR("-->xgbe_rx_poll: budget=%d\n", budget); | |
2119 | ||
2120 | /* Nothing to do if there isn't a Rx ring for this channel */ | |
2121 | if (!ring) | |
2122 | return 0; | |
2123 | ||
622c36f1 | 2124 | last = 0; |
7d9ca345 LT |
2125 | context_next = 0; |
2126 | ||
9227dc5e LT |
2127 | napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; |
2128 | ||
23e4eef7 | 2129 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); |
c5aa9e3b | 2130 | packet = &ring->packet_data; |
55ca6bcd | 2131 | while (packet_count < budget) { |
c5aa9e3b LT |
2132 | DBGPR(" cur = %d\n", ring->cur); |
2133 | ||
23e4eef7 LT |
2134 | /* First time in loop see if we need to restore state */ |
2135 | if (!received && rdata->state_saved) { | |
23e4eef7 LT |
2136 | skb = rdata->state.skb; |
2137 | error = rdata->state.error; | |
2138 | len = rdata->state.len; | |
2139 | } else { | |
2140 | memset(packet, 0, sizeof(*packet)); | |
23e4eef7 LT |
2141 | skb = NULL; |
2142 | error = 0; | |
2143 | len = 0; | |
2144 | } | |
c5aa9e3b LT |
2145 | |
2146 | read_again: | |
23e4eef7 LT |
2147 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); |
2148 | ||
270894e7 | 2149 | if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3)) |
9867e8fb LT |
2150 | xgbe_rx_refresh(channel); |
2151 | ||
c5aa9e3b LT |
2152 | if (hw_if->dev_read(channel)) |
2153 | break; | |
2154 | ||
2155 | received++; | |
2156 | ring->cur++; | |
c5aa9e3b | 2157 | |
622c36f1 LT |
2158 | last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, |
2159 | LAST); | |
23e4eef7 LT |
2160 | context_next = XGMAC_GET_BITS(packet->attributes, |
2161 | RX_PACKET_ATTRIBUTES, | |
2162 | CONTEXT_NEXT); | |
2163 | context = XGMAC_GET_BITS(packet->attributes, | |
2164 | RX_PACKET_ATTRIBUTES, | |
2165 | CONTEXT); | |
c5aa9e3b LT |
2166 | |
2167 | /* Earlier error, just drain the remaining data */ | |
622c36f1 | 2168 | if ((!last || context_next) && error) |
c5aa9e3b LT |
2169 | goto read_again; |
2170 | ||
2171 | if (error || packet->errors) { | |
2172 | if (packet->errors) | |
34bf65df LT |
2173 | netif_err(pdata, rx_err, netdev, |
2174 | "error in received packet\n"); | |
c5aa9e3b | 2175 | dev_kfree_skb(skb); |
55ca6bcd | 2176 | goto next_packet; |
c5aa9e3b LT |
2177 | } |
2178 | ||
23e4eef7 | 2179 | if (!context) { |
622c36f1 LT |
2180 | /* Get the data length in the descriptor buffers */ |
2181 | buf1_len = xgbe_rx_buf1_len(rdata, packet); | |
2182 | len += buf1_len; | |
2183 | buf2_len = xgbe_rx_buf2_len(rdata, packet, len); | |
2184 | len += buf2_len; | |
7d9ca345 | 2185 | |
622c36f1 | 2186 | if (!skb) { |
7d9ca345 | 2187 | skb = xgbe_create_skb(pdata, napi, rdata, |
622c36f1 LT |
2188 | buf1_len); |
2189 | if (!skb) { | |
08dcc47c | 2190 | error = 1; |
622c36f1 LT |
2191 | goto skip_data; |
2192 | } | |
2193 | } | |
2194 | ||
2195 | if (buf2_len) { | |
cfbfd86b LT |
2196 | dma_sync_single_range_for_cpu(pdata->dev, |
2197 | rdata->rx.buf.dma_base, | |
2198 | rdata->rx.buf.dma_off, | |
c9f140eb | 2199 | rdata->rx.buf.dma_len, |
174fd259 LT |
2200 | DMA_FROM_DEVICE); |
2201 | ||
2202 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, | |
c9f140eb LT |
2203 | rdata->rx.buf.pa.pages, |
2204 | rdata->rx.buf.pa.pages_offset, | |
622c36f1 | 2205 | buf2_len, |
7d9ca345 | 2206 | rdata->rx.buf.dma_len); |
c9f140eb | 2207 | rdata->rx.buf.pa.pages = NULL; |
174fd259 | 2208 | } |
c5aa9e3b | 2209 | } |
c5aa9e3b | 2210 | |
622c36f1 LT |
2211 | skip_data: |
2212 | if (!last || context_next) | |
c5aa9e3b LT |
2213 | goto read_again; |
2214 | ||
23e4eef7 | 2215 | if (!skb) |
55ca6bcd | 2216 | goto next_packet; |
23e4eef7 | 2217 | |
c5aa9e3b LT |
2218 | /* Be sure we don't exceed the configured MTU */ |
2219 | max_len = netdev->mtu + ETH_HLEN; | |
2220 | if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && | |
2221 | (skb->protocol == htons(ETH_P_8021Q))) | |
2222 | max_len += VLAN_HLEN; | |
2223 | ||
2224 | if (skb->len > max_len) { | |
34bf65df LT |
2225 | netif_err(pdata, rx_err, netdev, |
2226 | "packet length exceeds configured MTU\n"); | |
c5aa9e3b | 2227 | dev_kfree_skb(skb); |
55ca6bcd | 2228 | goto next_packet; |
c5aa9e3b LT |
2229 | } |
2230 | ||
34bf65df LT |
2231 | if (netif_msg_pktdata(pdata)) |
2232 | xgbe_print_pkt(netdev, skb, false); | |
c5aa9e3b LT |
2233 | |
2234 | skb_checksum_none_assert(skb); | |
2235 | if (XGMAC_GET_BITS(packet->attributes, | |
2236 | RX_PACKET_ATTRIBUTES, CSUM_DONE)) | |
2237 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2238 | ||
2239 | if (XGMAC_GET_BITS(packet->attributes, | |
2240 | RX_PACKET_ATTRIBUTES, VLAN_CTAG)) | |
2241 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
2242 | packet->vlan_ctag); | |
2243 | ||
23e4eef7 LT |
2244 | if (XGMAC_GET_BITS(packet->attributes, |
2245 | RX_PACKET_ATTRIBUTES, RX_TSTAMP)) { | |
2246 | u64 nsec; | |
2247 | ||
2248 | nsec = timecounter_cyc2time(&pdata->tstamp_tc, | |
2249 | packet->rx_tstamp); | |
2250 | hwtstamps = skb_hwtstamps(skb); | |
2251 | hwtstamps->hwtstamp = ns_to_ktime(nsec); | |
2252 | } | |
2253 | ||
5b9dfe29 LT |
2254 | if (XGMAC_GET_BITS(packet->attributes, |
2255 | RX_PACKET_ATTRIBUTES, RSS_HASH)) | |
2256 | skb_set_hash(skb, packet->rss_hash, | |
2257 | packet->rss_hash_type); | |
2258 | ||
c5aa9e3b LT |
2259 | skb->dev = netdev; |
2260 | skb->protocol = eth_type_trans(skb, netdev); | |
2261 | skb_record_rx_queue(skb, channel->queue_index); | |
c5aa9e3b | 2262 | |
9227dc5e | 2263 | napi_gro_receive(napi, skb); |
55ca6bcd LT |
2264 | |
2265 | next_packet: | |
2266 | packet_count++; | |
c5aa9e3b LT |
2267 | } |
2268 | ||
23e4eef7 | 2269 | /* Check if we need to save state before leaving */ |
622c36f1 | 2270 | if (received && (!last || context_next)) { |
23e4eef7 LT |
2271 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); |
2272 | rdata->state_saved = 1; | |
23e4eef7 LT |
2273 | rdata->state.skb = skb; |
2274 | rdata->state.len = len; | |
2275 | rdata->state.error = error; | |
2276 | } | |
2277 | ||
55ca6bcd | 2278 | DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count); |
c5aa9e3b | 2279 | |
55ca6bcd | 2280 | return packet_count; |
c5aa9e3b LT |
2281 | } |
2282 | ||
9227dc5e LT |
2283 | static int xgbe_one_poll(struct napi_struct *napi, int budget) |
2284 | { | |
2285 | struct xgbe_channel *channel = container_of(napi, struct xgbe_channel, | |
2286 | napi); | |
4c70dd8a | 2287 | struct xgbe_prv_data *pdata = channel->pdata; |
9227dc5e LT |
2288 | int processed = 0; |
2289 | ||
2290 | DBGPR("-->xgbe_one_poll: budget=%d\n", budget); | |
2291 | ||
2292 | /* Cleanup Tx ring first */ | |
2293 | xgbe_tx_poll(channel); | |
2294 | ||
2295 | /* Process Rx ring next */ | |
2296 | processed = xgbe_rx_poll(channel, budget); | |
2297 | ||
2298 | /* If we processed everything, we are done */ | |
d7aba644 | 2299 | if ((processed < budget) && napi_complete_done(napi, processed)) { |
9227dc5e | 2300 | /* Enable Tx and Rx interrupts */ |
4c70dd8a LT |
2301 | if (pdata->channel_irq_mode) |
2302 | xgbe_enable_rx_tx_int(pdata, channel); | |
2303 | else | |
2304 | enable_irq(channel->dma_irq); | |
9227dc5e LT |
2305 | } |
2306 | ||
2307 | DBGPR("<--xgbe_one_poll: received = %d\n", processed); | |
2308 | ||
2309 | return processed; | |
2310 | } | |
2311 | ||
2312 | static int xgbe_all_poll(struct napi_struct *napi, int budget) | |
c5aa9e3b LT |
2313 | { |
2314 | struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data, | |
2315 | napi); | |
2316 | struct xgbe_channel *channel; | |
9867e8fb LT |
2317 | int ring_budget; |
2318 | int processed, last_processed; | |
c5aa9e3b LT |
2319 | unsigned int i; |
2320 | ||
9227dc5e | 2321 | DBGPR("-->xgbe_all_poll: budget=%d\n", budget); |
c5aa9e3b | 2322 | |
c5aa9e3b | 2323 | processed = 0; |
9867e8fb LT |
2324 | ring_budget = budget / pdata->rx_ring_count; |
2325 | do { | |
2326 | last_processed = processed; | |
2327 | ||
2328 | channel = pdata->channel; | |
2329 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
2330 | /* Cleanup Tx ring first */ | |
2331 | xgbe_tx_poll(channel); | |
2332 | ||
2333 | /* Process Rx ring next */ | |
2334 | if (ring_budget > (budget - processed)) | |
2335 | ring_budget = budget - processed; | |
2336 | processed += xgbe_rx_poll(channel, ring_budget); | |
2337 | } | |
2338 | } while ((processed < budget) && (processed != last_processed)); | |
c5aa9e3b LT |
2339 | |
2340 | /* If we processed everything, we are done */ | |
d7aba644 | 2341 | if ((processed < budget) && napi_complete_done(napi, processed)) { |
c5aa9e3b LT |
2342 | /* Enable Tx and Rx interrupts */ |
2343 | xgbe_enable_rx_tx_ints(pdata); | |
2344 | } | |
2345 | ||
9227dc5e | 2346 | DBGPR("<--xgbe_all_poll: received = %d\n", processed); |
c5aa9e3b LT |
2347 | |
2348 | return processed; | |
2349 | } | |
2350 | ||
34bf65df LT |
2351 | void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, |
2352 | unsigned int idx, unsigned int count, unsigned int flag) | |
c5aa9e3b LT |
2353 | { |
2354 | struct xgbe_ring_data *rdata; | |
2355 | struct xgbe_ring_desc *rdesc; | |
2356 | ||
2357 | while (count--) { | |
d0a8ba6c | 2358 | rdata = XGBE_GET_DESC_DATA(ring, idx); |
c5aa9e3b | 2359 | rdesc = rdata->rdesc; |
34bf65df LT |
2360 | netdev_dbg(pdata->netdev, |
2361 | "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, | |
2362 | (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", | |
2363 | le32_to_cpu(rdesc->desc0), | |
2364 | le32_to_cpu(rdesc->desc1), | |
2365 | le32_to_cpu(rdesc->desc2), | |
2366 | le32_to_cpu(rdesc->desc3)); | |
c5aa9e3b LT |
2367 | idx++; |
2368 | } | |
2369 | } | |
2370 | ||
34bf65df | 2371 | void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, |
c5aa9e3b LT |
2372 | unsigned int idx) |
2373 | { | |
34bf65df LT |
2374 | struct xgbe_ring_data *rdata; |
2375 | struct xgbe_ring_desc *rdesc; | |
2376 | ||
2377 | rdata = XGBE_GET_DESC_DATA(ring, idx); | |
2378 | rdesc = rdata->rdesc; | |
2379 | netdev_dbg(pdata->netdev, | |
2380 | "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", | |
2381 | idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1), | |
2382 | le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3)); | |
c5aa9e3b LT |
2383 | } |
2384 | ||
2385 | void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) | |
2386 | { | |
2387 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
2388 | unsigned char *buf = skb->data; | |
2389 | unsigned char buffer[128]; | |
2390 | unsigned int i, j; | |
2391 | ||
34bf65df | 2392 | netdev_dbg(netdev, "\n************** SKB dump ****************\n"); |
c5aa9e3b | 2393 | |
34bf65df LT |
2394 | netdev_dbg(netdev, "%s packet of %d bytes\n", |
2395 | (tx_rx ? "TX" : "RX"), skb->len); | |
c5aa9e3b | 2396 | |
34bf65df LT |
2397 | netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest); |
2398 | netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); | |
2399 | netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto)); | |
c5aa9e3b LT |
2400 | |
2401 | for (i = 0, j = 0; i < skb->len;) { | |
2402 | j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", | |
2403 | buf[i++]); | |
2404 | ||
2405 | if ((i % 32) == 0) { | |
34bf65df | 2406 | netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer); |
c5aa9e3b LT |
2407 | j = 0; |
2408 | } else if ((i % 16) == 0) { | |
2409 | buffer[j++] = ' '; | |
2410 | buffer[j++] = ' '; | |
2411 | } else if ((i % 4) == 0) { | |
2412 | buffer[j++] = ' '; | |
2413 | } | |
2414 | } | |
2415 | if (i % 32) | |
34bf65df | 2416 | netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer); |
c5aa9e3b | 2417 | |
34bf65df | 2418 | netdev_dbg(netdev, "\n************** SKB dump ****************\n"); |
c5aa9e3b | 2419 | } |