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amd-xgbe-phy: Use the proper auto-negotiation XNP registers
[thirdparty/kernel/stable.git] / drivers / net / ethernet / amd / xgbe / xgbe.h
CommitLineData
c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#ifndef __XGBE_H__
118#define __XGBE_H__
119
120#include <linux/dma-mapping.h>
121#include <linux/netdevice.h>
122#include <linux/workqueue.h>
123#include <linux/phy.h>
801c62d9
LT		 124#include <linux/if_vlan.h>
125#include <linux/bitops.h>
23e4eef7 126#include <linux/ptp_clock_kernel.h>
74d23cc7 127#include <linux/timecounter.h>
23e4eef7 128#include <linux/net_tstamp.h>
fca2d994 129#include <net/dcbnl.h>
c5aa9e3b 130
c5aa9e3b
LT		 131#define XGBE_DRV_NAME "amd-xgbe"
132#define XGBE_DRV_VERSION "1.0.0-a"
133#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
134
135/* Descriptor related defines */
d0a8ba6c
LT		 136#define XGBE_TX_DESC_CNT 512
137#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139#define XGBE_RX_DESC_CNT 512
c5aa9e3b 140
d0a8ba6c 141#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
c5aa9e3b 142
16958a2b
LT		 143/* Descriptors required for maximum contigous TSO/GSO packet */
144#define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
145
146/* Maximum possible descriptors needed for an SKB:
147 * - Maximum number of SKB frags
148 * - Maximum descriptors for contiguous TSO/GSO packet
149 * - Possible context descriptor
150 * - Possible TSO header descriptor
151 */
152#define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
153
d0a8ba6c
LT		 154#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
155#define XGBE_RX_BUF_ALIGN 64
08dcc47c 156#define XGBE_SKB_ALLOC_SIZE 256
174fd259 157#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
c5aa9e3b 158
d5c48582 159#define XGBE_MAX_DMA_CHANNELS 16
fca2d994 160#define XGBE_MAX_QUEUES 16
16edd34e 161#define XGBE_DMA_STOP_TIMEOUT 5
d0a8ba6c
LT		 162
163/* DMA cache settings - Outer sharable, write-back, write-allocate */
cfa50c78
LT		 164#define XGBE_DMA_OS_AXDOMAIN 0x2
165#define XGBE_DMA_OS_ARCACHE 0xb
166#define XGBE_DMA_OS_AWCACHE 0xf
167
168/* DMA cache settings - System, no caches used */
169#define XGBE_DMA_SYS_AXDOMAIN 0x3
170#define XGBE_DMA_SYS_ARCACHE 0x0
171#define XGBE_DMA_SYS_AWCACHE 0x0
d0a8ba6c
LT		 172
173#define XGBE_DMA_INTERRUPT_MASK 0x31c7
c5aa9e3b
LT		 174
175#define XGMAC_MIN_PACKET 60
176#define XGMAC_STD_PACKET_MTU 1500
177#define XGMAC_MAX_STD_PACKET 1518
178#define XGMAC_JUMBO_PACKET_MTU 9000
179#define XGMAC_MAX_JUMBO_PACKET 9018
180
c5aa9e3b
LT		 181/* MDIO bus phy name */
182#define XGBE_PHY_NAME "amd_xgbe_phy"
183#define XGBE_PRTAD 0
184
23e4eef7
LT		 185/* Device-tree clock names */
186#define XGBE_DMA_CLOCK "dma_clk"
187#define XGBE_PTP_CLOCK "ptp_clk"
9227dc5e 188#define XGBE_DMA_IRQS "amd,per-channel-interrupt"
23e4eef7
LT		 189
190/* Timestamp support - values based on 50MHz PTP clock
191 * 50MHz => 20 nsec
192 */
193#define XGBE_TSTAMP_SSINC 20
194#define XGBE_TSTAMP_SNSINC 0
195
c5aa9e3b
LT		 196/* Driver PMT macros */
197#define XGMAC_DRIVER_CONTEXT 1
198#define XGMAC_IOCTL_CONTEXT 2
199
f076f453 200#define XGBE_FIFO_MAX 81920
d0a8ba6c
LT		 201#define XGBE_FIFO_SIZE_B(x) (x)
202#define XGBE_FIFO_SIZE_KB(x) (x * 1024)
c5aa9e3b 203
fca2d994 204#define XGBE_TC_MIN_QUANTUM 10
c5aa9e3b
LT		 205
206/* Helper macro for descriptor handling
d0a8ba6c 207 * Always use XGBE_GET_DESC_DATA to access the descriptor data
c5aa9e3b
LT		 208 * since the index is free-running and needs to be and-ed
209 * with the descriptor count value of the ring to index to
210 * the proper descriptor data.
211 */
d0a8ba6c 212#define XGBE_GET_DESC_DATA(_ring, _idx) \
c5aa9e3b
LT		 213 ((_ring)->rdata + \
214 ((_idx) & ((_ring)->rdesc_count - 1)))
215
c5aa9e3b 216/* Default coalescing parameters */
9867e8fb
LT		 217#define XGMAC_INIT_DMA_TX_USECS 50
218#define XGMAC_INIT_DMA_TX_FRAMES 25
c5aa9e3b
LT		 219
220#define XGMAC_MAX_DMA_RIWT 0xff
9867e8fb
LT		 221#define XGMAC_INIT_DMA_RX_USECS 30
222#define XGMAC_INIT_DMA_RX_FRAMES 25
c5aa9e3b
LT		 223
224/* Flow control queue count */
225#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
226
b85e4d89
LT		 227/* Maximum MAC address hash table size (256 bits = 8 bytes) */
228#define XGBE_MAC_HASH_TABLE_SIZE 8
c5aa9e3b 229
5b9dfe29
LT		 230/* Receive Side Scaling */
231#define XGBE_RSS_HASH_KEY_SIZE 40
232#define XGBE_RSS_MAX_TABLE_SIZE 256
233#define XGBE_RSS_LOOKUP_TABLE_TYPE 0
234#define XGBE_RSS_HASH_KEY_TYPE 1
235
c5aa9e3b
LT		 236struct xgbe_prv_data;
237
238struct xgbe_packet_data {
16958a2b
LT		 239 struct sk_buff *skb;
240
c5aa9e3b
LT		 241 unsigned int attributes;
242
243 unsigned int errors;
244
245 unsigned int rdesc_count;
246 unsigned int length;
247
248 unsigned int header_len;
249 unsigned int tcp_header_len;
250 unsigned int tcp_payload_len;
251 unsigned short mss;
252
253 unsigned short vlan_ctag;
23e4eef7
LT		 254
255 u64 rx_tstamp;
5b9dfe29
LT		 256
257 u32 rss_hash;
258 enum pkt_hash_types rss_hash_type;
5fb4b86a
LT		 259
260 unsigned int tx_packets;
261 unsigned int tx_bytes;
c5aa9e3b
LT		 262};
263
264/* Common Rx and Tx descriptor mapping */
265struct xgbe_ring_desc {
5226cfc5
LT		 266 __le32 desc0;
267 __le32 desc1;
268 __le32 desc2;
269 __le32 desc3;
c5aa9e3b
LT		 270};
271
08dcc47c
LT		 272/* Page allocation related values */
273struct xgbe_page_alloc {
274 struct page *pages;
275 unsigned int pages_len;
276 unsigned int pages_offset;
277
278 dma_addr_t pages_dma;
279};
280
174fd259
LT		 281/* Ring entry buffer data */
282struct xgbe_buffer_data {
283 struct xgbe_page_alloc pa;
284 struct xgbe_page_alloc pa_unmap;
285
286 dma_addr_t dma;
287 unsigned int dma_len;
288};
289
c9f140eb
LT		 290/* Tx-related ring data */
291struct xgbe_tx_ring_data {
5fb4b86a
LT		 292 unsigned int packets; /* BQL packet count */
293 unsigned int bytes; /* BQL byte count */
c9f140eb
LT		 294};
295
296/* Rx-related ring data */
297struct xgbe_rx_ring_data {
298 struct xgbe_buffer_data hdr; /* Header locations */
299 struct xgbe_buffer_data buf; /* Payload locations */
300
301 unsigned short hdr_len; /* Length of received header */
302 unsigned short len; /* Length of received packet */
303};
304
c5aa9e3b
LT		 305/* Structure used to hold information related to the descriptor
306 * and the packet associated with the descriptor (always use
d0a8ba6c 307 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
c5aa9e3b
LT		 308 */
309struct xgbe_ring_data {
310 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
311 dma_addr_t rdesc_dma; /* DMA address of descriptor */
312
313 struct sk_buff *skb; /* Virtual address of SKB */
314 dma_addr_t skb_dma; /* DMA address of SKB data */
315 unsigned int skb_dma_len; /* Length of SKB DMA area */
c5aa9e3b 316
c9f140eb
LT		 317 struct xgbe_tx_ring_data tx; /* Tx-related data */
318 struct xgbe_rx_ring_data rx; /* Rx-related data */
c5aa9e3b
LT		 319
320 unsigned int interrupt; /* Interrupt indicator */
321
322 unsigned int mapped_as_page;
23e4eef7
LT		 323
324 /* Incomplete receive save location. If the budget is exhausted
325 * or the last descriptor (last normal descriptor or a following
326 * context descriptor) has not been DMA'd yet the current state
327 * of the receive processing needs to be saved.
328 */
329 unsigned int state_saved;
330 struct {
331 unsigned int incomplete;
332 unsigned int context_next;
333 struct sk_buff *skb;
334 unsigned int len;
335 unsigned int error;
336 } state;
c5aa9e3b
LT		 337};
338
339struct xgbe_ring {
340 /* Ring lock - used just for TX rings at the moment */
341 spinlock_t lock;
342
343 /* Per packet related information */
344 struct xgbe_packet_data packet_data;
345
346 /* Virtual/DMA addresses and count of allocated descriptor memory */
347 struct xgbe_ring_desc *rdesc;
348 dma_addr_t rdesc_dma;
349 unsigned int rdesc_count;
350
351 /* Array of descriptor data corresponding the descriptor memory
d0a8ba6c 352 * (always use the XGBE_GET_DESC_DATA macro to access this data)
c5aa9e3b
LT		 353 */
354 struct xgbe_ring_data *rdata;
355
08dcc47c 356 /* Page allocation for RX buffers */
174fd259
LT		 357 struct xgbe_page_alloc rx_hdr_pa;
358 struct xgbe_page_alloc rx_buf_pa;
08dcc47c 359
c5aa9e3b
LT		 360 /* Ring index values
361 * cur - Tx: index of descriptor to be used for current transfer
362 * Rx: index of descriptor to check for packet availability
363 * dirty - Tx: index of descriptor to check for transfer complete
270894e7 364 * Rx: index of descriptor to check for buffer reallocation
c5aa9e3b
LT		 365 */
366 unsigned int cur;
367 unsigned int dirty;
368
369 /* Coalesce frame count used for interrupt bit setting */
370 unsigned int coalesce_count;
371
372 union {
373 struct {
374 unsigned int queue_stopped;
16958a2b 375 unsigned int xmit_more;
c5aa9e3b
LT		 376 unsigned short cur_mss;
377 unsigned short cur_vlan_ctag;
378 } tx;
c5aa9e3b
LT		 379 };
380} ____cacheline_aligned;
381
382/* Structure used to describe the descriptor rings associated with
383 * a DMA channel.
384 */
385struct xgbe_channel {
386 char name[16];
387
388 /* Address of private data area for device */
389 struct xgbe_prv_data *pdata;
390
391 /* Queue index and base address of queue's DMA registers */
392 unsigned int queue_index;
393 void __iomem *dma_regs;
394
9227dc5e
LT		 395 /* Per channel interrupt irq number */
396 int dma_irq;
54ceb9ec 397 char dma_irq_name[IFNAMSIZ + 32];
9227dc5e
LT		 398
399 /* Netdev related settings */
400 struct napi_struct napi;
401
c5aa9e3b
LT		 402 unsigned int saved_ier;
403
404 unsigned int tx_timer_active;
405 struct hrtimer tx_timer;
406
407 struct xgbe_ring *tx_ring;
408 struct xgbe_ring *rx_ring;
409} ____cacheline_aligned;
410
411enum xgbe_int {
c5aa9e3b
LT		 412 XGMAC_INT_DMA_CH_SR_TI,
413 XGMAC_INT_DMA_CH_SR_TPS,
414 XGMAC_INT_DMA_CH_SR_TBU,
415 XGMAC_INT_DMA_CH_SR_RI,
416 XGMAC_INT_DMA_CH_SR_RBU,
417 XGMAC_INT_DMA_CH_SR_RPS,
9867e8fb 418 XGMAC_INT_DMA_CH_SR_TI_RI,
c5aa9e3b
LT		 419 XGMAC_INT_DMA_CH_SR_FBE,
420 XGMAC_INT_DMA_ALL,
421};
422
423enum xgbe_int_state {
424 XGMAC_INT_STATE_SAVE,
425 XGMAC_INT_STATE_RESTORE,
426};
427
428enum xgbe_mtl_fifo_size {
429 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
430 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
431 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
432 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
433 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
434 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
435 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
436 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
437 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
438 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
439 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
440};
441
442struct xgbe_mmc_stats {
443 /* Tx Stats */
444 u64 txoctetcount_gb;
445 u64 txframecount_gb;
446 u64 txbroadcastframes_g;
447 u64 txmulticastframes_g;
448 u64 tx64octets_gb;
449 u64 tx65to127octets_gb;
450 u64 tx128to255octets_gb;
451 u64 tx256to511octets_gb;
452 u64 tx512to1023octets_gb;
453 u64 tx1024tomaxoctets_gb;
454 u64 txunicastframes_gb;
455 u64 txmulticastframes_gb;
456 u64 txbroadcastframes_gb;
457 u64 txunderflowerror;
458 u64 txoctetcount_g;
459 u64 txframecount_g;
460 u64 txpauseframes;
461 u64 txvlanframes_g;
462
463 /* Rx Stats */
464 u64 rxframecount_gb;
465 u64 rxoctetcount_gb;
466 u64 rxoctetcount_g;
467 u64 rxbroadcastframes_g;
468 u64 rxmulticastframes_g;
469 u64 rxcrcerror;
470 u64 rxrunterror;
471 u64 rxjabbererror;
472 u64 rxundersize_g;
473 u64 rxoversize_g;
474 u64 rx64octets_gb;
475 u64 rx65to127octets_gb;
476 u64 rx128to255octets_gb;
477 u64 rx256to511octets_gb;
478 u64 rx512to1023octets_gb;
479 u64 rx1024tomaxoctets_gb;
480 u64 rxunicastframes_g;
481 u64 rxlengtherror;
482 u64 rxoutofrangetype;
483 u64 rxpauseframes;
484 u64 rxfifooverflow;
485 u64 rxvlanframes_gb;
486 u64 rxwatchdogerror;
487};
488
489struct xgbe_hw_if {
490 int (*tx_complete)(struct xgbe_ring_desc *);
491
492 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
493 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
b85e4d89 494 int (*add_mac_addresses)(struct xgbe_prv_data *);
c5aa9e3b
LT		 495 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
496
497 int (*enable_rx_csum)(struct xgbe_prv_data *);
498 int (*disable_rx_csum)(struct xgbe_prv_data *);
499
500 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
501 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
801c62d9
LT		 502 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
503 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
504 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
c5aa9e3b
LT		 505
506 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
507 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
508 int (*set_gmii_speed)(struct xgbe_prv_data *);
509 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
510 int (*set_xgmii_speed)(struct xgbe_prv_data *);
511
512 void (*enable_tx)(struct xgbe_prv_data *);
513 void (*disable_tx)(struct xgbe_prv_data *);
514 void (*enable_rx)(struct xgbe_prv_data *);
515 void (*disable_rx)(struct xgbe_prv_data *);
516
517 void (*powerup_tx)(struct xgbe_prv_data *);
518 void (*powerdown_tx)(struct xgbe_prv_data *);
519 void (*powerup_rx)(struct xgbe_prv_data *);
520 void (*powerdown_rx)(struct xgbe_prv_data *);
521
522 int (*init)(struct xgbe_prv_data *);
523 int (*exit)(struct xgbe_prv_data *);
524
525 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
526 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
a9d41981 527 void (*dev_xmit)(struct xgbe_channel *);
c5aa9e3b
LT		 528 int (*dev_read)(struct xgbe_channel *);
529 void (*tx_desc_init)(struct xgbe_channel *);
530 void (*rx_desc_init)(struct xgbe_channel *);
531 void (*rx_desc_reset)(struct xgbe_ring_data *);
532 void (*tx_desc_reset)(struct xgbe_ring_data *);
533 int (*is_last_desc)(struct xgbe_ring_desc *);
534 int (*is_context_desc)(struct xgbe_ring_desc *);
16958a2b 535 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
c5aa9e3b
LT		 536
537 /* For FLOW ctrl */
538 int (*config_tx_flow_control)(struct xgbe_prv_data *);
539 int (*config_rx_flow_control)(struct xgbe_prv_data *);
540
541 /* For RX coalescing */
542 int (*config_rx_coalesce)(struct xgbe_prv_data *);
543 int (*config_tx_coalesce)(struct xgbe_prv_data *);
544 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
545 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
546
547 /* For RX and TX threshold config */
548 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
549 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
550
551 /* For RX and TX Store and Forward Mode config */
552 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
553 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
554
555 /* For TX DMA Operate on Second Frame config */
556 int (*config_osp_mode)(struct xgbe_prv_data *);
557
558 /* For RX and TX PBL config */
559 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
560 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
561 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
562 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
563 int (*config_pblx8)(struct xgbe_prv_data *);
564
565 /* For MMC statistics */
566 void (*rx_mmc_int)(struct xgbe_prv_data *);
567 void (*tx_mmc_int)(struct xgbe_prv_data *);
568 void (*read_mmc_stats)(struct xgbe_prv_data *);
23e4eef7
LT		 569
570 /* For Timestamp config */
571 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
572 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
573 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
574 unsigned int nsec);
575 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
576 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
fca2d994
LT		 577
578 /* For Data Center Bridging config */
579 void (*config_dcb_tc)(struct xgbe_prv_data *);
580 void (*config_dcb_pfc)(struct xgbe_prv_data *);
5b9dfe29
LT		 581
582 /* For Receive Side Scaling */
583 int (*enable_rss)(struct xgbe_prv_data *);
584 int (*disable_rss)(struct xgbe_prv_data *);
f6ac8628
LT		 585 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
586 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
c5aa9e3b
LT		 587};
588
589struct xgbe_desc_if {
590 int (*alloc_ring_resources)(struct xgbe_prv_data *);
591 void (*free_ring_resources)(struct xgbe_prv_data *);
592 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
270894e7
LT		 593 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
594 struct xgbe_ring_data *);
08dcc47c 595 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
c5aa9e3b
LT		 596 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
597 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
598};
599
600/* This structure contains flags that indicate what hardware features
601 * or configurations are present in the device.
602 */
603struct xgbe_hw_features {
a9a4a2d9
LT		 604 /* HW Version */
605 unsigned int version;
606
c5aa9e3b
LT		 607 /* HW Feature Register0 */
608 unsigned int gmii; /* 1000 Mbps support */
609 unsigned int vlhash; /* VLAN Hash Filter */
610 unsigned int sma; /* SMA(MDIO) Interface */
611 unsigned int rwk; /* PMT remote wake-up packet */
612 unsigned int mgk; /* PMT magic packet */
613 unsigned int mmc; /* RMON module */
614 unsigned int aoe; /* ARP Offload */
615 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
616 unsigned int eee; /* Energy Efficient Ethernet */
617 unsigned int tx_coe; /* Tx Checksum Offload */
618 unsigned int rx_coe; /* Rx Checksum Offload */
619 unsigned int addn_mac; /* Additional MAC Addresses */
620 unsigned int ts_src; /* Timestamp Source */
621 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
622
623 /* HW Feature Register1 */
624 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
625 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
626 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
627 unsigned int dcb; /* DCB Feature */
628 unsigned int sph; /* Split Header Feature */
629 unsigned int tso; /* TCP Segmentation Offload */
630 unsigned int dma_debug; /* DMA Debug Registers */
631 unsigned int rss; /* Receive Side Scaling */
fca2d994 632 unsigned int tc_cnt; /* Number of Traffic Classes */
c5aa9e3b
LT		 633 unsigned int hash_table_size; /* Hash Table Size */
634 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
635
636 /* HW Feature Register2 */
637 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
638 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
639 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
640 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
641 unsigned int pps_out_num; /* Number of PPS outputs */
642 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
643};
644
645struct xgbe_prv_data {
646 struct net_device *netdev;
647 struct platform_device *pdev;
648 struct device *dev;
649
650 /* XGMAC/XPCS related mmio registers */
651 void __iomem *xgmac_regs; /* XGMAC CSRs */
652 void __iomem *xpcs_regs; /* XPCS MMD registers */
653
654 /* Overall device lock */
655 spinlock_t lock;
656
657 /* XPCS indirect addressing mutex */
658 struct mutex xpcs_mutex;
659
5b9dfe29
LT		 660 /* RSS addressing mutex */
661 struct mutex rss_mutex;
662
9227dc5e
LT		 663 int dev_irq;
664 unsigned int per_channel_irq;
c5aa9e3b
LT		 665
666 struct xgbe_hw_if hw_if;
667 struct xgbe_desc_if desc_if;
668
cfa50c78
LT		 669 /* AXI DMA settings */
670 unsigned int axdomain;
671 unsigned int arcache;
672 unsigned int awcache;
673
c5aa9e3b
LT		 674 /* Rings for Tx/Rx on a DMA channel */
675 struct xgbe_channel *channel;
676 unsigned int channel_count;
677 unsigned int tx_ring_count;
678 unsigned int tx_desc_count;
679 unsigned int rx_ring_count;
680 unsigned int rx_desc_count;
681
853eb16b
LT		 682 unsigned int tx_q_count;
683 unsigned int rx_q_count;
684
c5aa9e3b
LT		 685 /* Tx/Rx common settings */
686 unsigned int pblx8;
687
688 /* Tx settings */
689 unsigned int tx_sf_mode;
690 unsigned int tx_threshold;
691 unsigned int tx_pbl;
692 unsigned int tx_osp_mode;
693
694 /* Rx settings */
695 unsigned int rx_sf_mode;
696 unsigned int rx_threshold;
697 unsigned int rx_pbl;
698
699 /* Tx coalescing settings */
700 unsigned int tx_usecs;
701 unsigned int tx_frames;
702
703 /* Rx coalescing settings */
704 unsigned int rx_riwt;
705 unsigned int rx_frames;
706
08dcc47c 707 /* Current Rx buffer size */
c5aa9e3b
LT		 708 unsigned int rx_buf_size;
709
710 /* Flow control settings */
711 unsigned int pause_autoneg;
712 unsigned int tx_pause;
713 unsigned int rx_pause;
714
5b9dfe29
LT		 715 /* Receive Side Scaling settings */
716 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
717 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
718 u32 rss_options;
719
c5aa9e3b
LT		 720 /* MDIO settings */
721 struct module *phy_module;
722 char *mii_bus_id;
723 struct mii_bus *mii;
724 int mdio_mmd;
725 struct phy_device *phydev;
726 int default_autoneg;
727 int default_speed;
728
729 /* Current PHY settings */
730 phy_interface_t phy_mode;
731 int phy_link;
732 int phy_speed;
733 unsigned int phy_tx_pause;
734 unsigned int phy_rx_pause;
735
736 /* Netdev related settings */
737 netdev_features_t netdev_features;
738 struct napi_struct napi;
739 struct xgbe_mmc_stats mmc_stats;
740
801c62d9
LT		 741 /* Filtering support */
742 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
743
23e4eef7
LT		 744 /* Device clocks */
745 struct clk *sysclk;
746 struct clk *ptpclk;
747
748 /* Timestamp support */
749 spinlock_t tstamp_lock;
750 struct ptp_clock_info ptp_clock_info;
751 struct ptp_clock *ptp_clock;
752 struct hwtstamp_config tstamp_config;
753 struct cyclecounter tstamp_cc;
754 struct timecounter tstamp_tc;
755 unsigned int tstamp_addend;
756 struct work_struct tx_tstamp_work;
757 struct sk_buff *tx_tstamp_skb;
758 u64 tx_tstamp;
c5aa9e3b 759
fca2d994
LT		 760 /* DCB support */
761 struct ieee_ets *ets;
762 struct ieee_pfc *pfc;
763 unsigned int q2tc_map[XGBE_MAX_QUEUES];
764 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
765
c5aa9e3b
LT		 766 /* Hardware features of the device */
767 struct xgbe_hw_features hw_feat;
768
769 /* Device restart work structure */
770 struct work_struct restart_work;
771
772 /* Keeps track of power mode */
773 unsigned int power_down;
774
775#ifdef CONFIG_DEBUG_FS
776 struct dentry *xgbe_debugfs;
777
778 unsigned int debugfs_xgmac_reg;
779
780 unsigned int debugfs_xpcs_mmd;
781 unsigned int debugfs_xpcs_reg;
782#endif
783};
784
785/* Function prototypes*/
786
787void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
788void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
789struct net_device_ops *xgbe_get_netdev_ops(void);
790struct ethtool_ops *xgbe_get_ethtool_ops(void);
fca2d994
LT		 791#ifdef CONFIG_AMD_XGBE_DCB
792const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
793#endif
c5aa9e3b
LT		 794
795int xgbe_mdio_register(struct xgbe_prv_data *);
796void xgbe_mdio_unregister(struct xgbe_prv_data *);
797void xgbe_dump_phy_registers(struct xgbe_prv_data *);
23e4eef7
LT		 798void xgbe_ptp_register(struct xgbe_prv_data *);
799void xgbe_ptp_unregister(struct xgbe_prv_data *);
c5aa9e3b
LT		 800void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
801 unsigned int);
802void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
803 unsigned int);
804void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
805void xgbe_get_all_hw_features(struct xgbe_prv_data *);
806int xgbe_powerup(struct net_device *, unsigned int);
807int xgbe_powerdown(struct net_device *, unsigned int);
808void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
809void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
810
811#ifdef CONFIG_DEBUG_FS
812void xgbe_debugfs_init(struct xgbe_prv_data *);
813void xgbe_debugfs_exit(struct xgbe_prv_data *);
814#else
815static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
816static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
817#endif /* CONFIG_DEBUG_FS */
818
819/* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
820#if 0
821#define XGMAC_ENABLE_TX_DESC_DUMP
822#define XGMAC_ENABLE_RX_DESC_DUMP
823#endif
824
825/* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
826#if 0
827#define XGMAC_ENABLE_TX_PKT_DUMP
828#define XGMAC_ENABLE_RX_PKT_DUMP
829#endif
830
831/* NOTE: Uncomment for function trace log messages in KERNEL LOG */
832#if 0
833#define YDEBUG
834#define YDEBUG_MDIO
835#endif
836
837/* For debug prints */
838#ifdef YDEBUG
839#define DBGPR(x...) pr_alert(x)
840#define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
841#else
842#define DBGPR(x...) do { } while (0)
843#define DBGPHY_REGS(x...) do { } while (0)
844#endif
845
846#ifdef YDEBUG_MDIO
847#define DBGPR_MDIO(x...) pr_alert(x)
848#else
849#define DBGPR_MDIO(x...) do { } while (0)
850#endif
851
852#endif
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git