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Commit | Line | Data |
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c5aa9e3b LT |
1 | /* |
2 | * AMD 10Gb Ethernet driver | |
3 | * | |
4 | * This file is available to you under your choice of the following two | |
5 | * licenses: | |
6 | * | |
7 | * License 1: GPLv2 | |
8 | * | |
b3b71597 | 9 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
10 | * |
11 | * This file is free software; you may copy, redistribute and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation, either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * This file incorporates work covered by the following copyright and | |
25 | * permission notice: | |
26 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
27 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
28 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
29 | * and you. | |
30 | * | |
31 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
32 | * under any End User Software License Agreement or Agreement for Licensed | |
33 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
34 | * granted, free of charge, to any person obtaining a copy of this software | |
35 | * annotated with this license and the Software, to deal in the Software | |
36 | * without restriction, including without limitation the rights to use, | |
37 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
38 | * of the Software, and to permit persons to whom the Software is furnished | |
39 | * to do so, subject to the following conditions: | |
40 | * | |
41 | * The above copyright notice and this permission notice shall be included | |
42 | * in all copies or substantial portions of the Software. | |
43 | * | |
44 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
45 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
46 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
47 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
48 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
49 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
50 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
51 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
52 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
53 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
54 | * THE POSSIBILITY OF SUCH DAMAGE. | |
55 | * | |
56 | * | |
57 | * License 2: Modified BSD | |
58 | * | |
b3b71597 | 59 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
60 | * All rights reserved. |
61 | * | |
62 | * Redistribution and use in source and binary forms, with or without | |
63 | * modification, are permitted provided that the following conditions are met: | |
64 | * * Redistributions of source code must retain the above copyright | |
65 | * notice, this list of conditions and the following disclaimer. | |
66 | * * Redistributions in binary form must reproduce the above copyright | |
67 | * notice, this list of conditions and the following disclaimer in the | |
68 | * documentation and/or other materials provided with the distribution. | |
69 | * * Neither the name of Advanced Micro Devices, Inc. nor the | |
70 | * names of its contributors may be used to endorse or promote products | |
71 | * derived from this software without specific prior written permission. | |
72 | * | |
73 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
74 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
75 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
76 | * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY | |
77 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
78 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
79 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
80 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
81 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
82 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
83 | * | |
84 | * This file incorporates work covered by the following copyright and | |
85 | * permission notice: | |
86 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
87 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
88 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
89 | * and you. | |
90 | * | |
91 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
92 | * under any End User Software License Agreement or Agreement for Licensed | |
93 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
94 | * granted, free of charge, to any person obtaining a copy of this software | |
95 | * annotated with this license and the Software, to deal in the Software | |
96 | * without restriction, including without limitation the rights to use, | |
97 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
98 | * of the Software, and to permit persons to whom the Software is furnished | |
99 | * to do so, subject to the following conditions: | |
100 | * | |
101 | * The above copyright notice and this permission notice shall be included | |
102 | * in all copies or substantial portions of the Software. | |
103 | * | |
104 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
105 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
106 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
107 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
108 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
109 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
110 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
111 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
112 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
113 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
114 | * THE POSSIBILITY OF SUCH DAMAGE. | |
115 | */ | |
116 | ||
117 | #ifndef __XGBE_H__ | |
118 | #define __XGBE_H__ | |
119 | ||
120 | #include <linux/dma-mapping.h> | |
121 | #include <linux/netdevice.h> | |
122 | #include <linux/workqueue.h> | |
123 | #include <linux/phy.h> | |
801c62d9 LT |
124 | #include <linux/if_vlan.h> |
125 | #include <linux/bitops.h> | |
23e4eef7 | 126 | #include <linux/ptp_clock_kernel.h> |
74d23cc7 | 127 | #include <linux/timecounter.h> |
23e4eef7 | 128 | #include <linux/net_tstamp.h> |
fca2d994 | 129 | #include <net/dcbnl.h> |
c5aa9e3b | 130 | |
c5aa9e3b | 131 | #define XGBE_DRV_NAME "amd-xgbe" |
e57f7a3f | 132 | #define XGBE_DRV_VERSION "1.0.3" |
c5aa9e3b LT |
133 | #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" |
134 | ||
135 | /* Descriptor related defines */ | |
d0a8ba6c LT |
136 | #define XGBE_TX_DESC_CNT 512 |
137 | #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) | |
138 | #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) | |
139 | #define XGBE_RX_DESC_CNT 512 | |
c5aa9e3b | 140 | |
d0a8ba6c | 141 | #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) |
c5aa9e3b | 142 | |
e1c05067 | 143 | /* Descriptors required for maximum contiguous TSO/GSO packet */ |
16958a2b LT |
144 | #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) |
145 | ||
146 | /* Maximum possible descriptors needed for an SKB: | |
147 | * - Maximum number of SKB frags | |
148 | * - Maximum descriptors for contiguous TSO/GSO packet | |
149 | * - Possible context descriptor | |
150 | * - Possible TSO header descriptor | |
151 | */ | |
152 | #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) | |
153 | ||
d0a8ba6c LT |
154 | #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) |
155 | #define XGBE_RX_BUF_ALIGN 64 | |
08dcc47c | 156 | #define XGBE_SKB_ALLOC_SIZE 256 |
174fd259 | 157 | #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ |
c5aa9e3b | 158 | |
d5c48582 | 159 | #define XGBE_MAX_DMA_CHANNELS 16 |
fca2d994 | 160 | #define XGBE_MAX_QUEUES 16 |
43e0dcf7 | 161 | #define XGBE_PRIORITY_QUEUES 8 |
4b8acdf5 | 162 | #define XGBE_DMA_STOP_TIMEOUT 1 |
d0a8ba6c LT |
163 | |
164 | /* DMA cache settings - Outer sharable, write-back, write-allocate */ | |
cfa50c78 LT |
165 | #define XGBE_DMA_OS_AXDOMAIN 0x2 |
166 | #define XGBE_DMA_OS_ARCACHE 0xb | |
167 | #define XGBE_DMA_OS_AWCACHE 0xf | |
168 | ||
169 | /* DMA cache settings - System, no caches used */ | |
170 | #define XGBE_DMA_SYS_AXDOMAIN 0x3 | |
171 | #define XGBE_DMA_SYS_ARCACHE 0x0 | |
172 | #define XGBE_DMA_SYS_AWCACHE 0x0 | |
d0a8ba6c LT |
173 | |
174 | #define XGBE_DMA_INTERRUPT_MASK 0x31c7 | |
c5aa9e3b LT |
175 | |
176 | #define XGMAC_MIN_PACKET 60 | |
177 | #define XGMAC_STD_PACKET_MTU 1500 | |
178 | #define XGMAC_MAX_STD_PACKET 1518 | |
179 | #define XGMAC_JUMBO_PACKET_MTU 9000 | |
180 | #define XGMAC_MAX_JUMBO_PACKET 9018 | |
43e0dcf7 LT |
181 | #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ |
182 | ||
183 | #define XGMAC_PFC_DATA_LEN 46 | |
184 | #define XGMAC_PFC_DELAYS 14000 | |
185 | ||
186 | #define XGMAC_PRIO_QUEUES(_cnt) \ | |
187 | min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) | |
c5aa9e3b | 188 | |
82a19035 LT |
189 | /* Common property names */ |
190 | #define XGBE_MAC_ADDR_PROPERTY "mac-address" | |
191 | #define XGBE_PHY_MODE_PROPERTY "phy-mode" | |
192 | #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" | |
7c12aa08 | 193 | #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" |
82a19035 | 194 | |
23e4eef7 LT |
195 | /* Device-tree clock names */ |
196 | #define XGBE_DMA_CLOCK "dma_clk" | |
197 | #define XGBE_PTP_CLOCK "ptp_clk" | |
82a19035 LT |
198 | |
199 | /* ACPI property names */ | |
200 | #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" | |
201 | #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" | |
23e4eef7 | 202 | |
47f164de LT |
203 | /* PCI BAR mapping */ |
204 | #define XGBE_XGMAC_BAR 0 | |
205 | #define XGBE_XPCS_BAR 1 | |
206 | #define XGBE_MAC_PROP_OFFSET 0x1d000 | |
207 | #define XGBE_I2C_CTRL_OFFSET 0x1e000 | |
208 | ||
209 | /* PCI MSIx support */ | |
210 | #define XGBE_MSIX_BASE_COUNT 4 | |
211 | #define XGBE_MSIX_MIN_COUNT (XGBE_MSIX_BASE_COUNT + 1) | |
212 | ||
213 | /* PCI clock frequencies */ | |
214 | #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ | |
215 | #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ | |
216 | ||
23e4eef7 LT |
217 | /* Timestamp support - values based on 50MHz PTP clock |
218 | * 50MHz => 20 nsec | |
219 | */ | |
220 | #define XGBE_TSTAMP_SSINC 20 | |
221 | #define XGBE_TSTAMP_SNSINC 0 | |
222 | ||
c5aa9e3b LT |
223 | /* Driver PMT macros */ |
224 | #define XGMAC_DRIVER_CONTEXT 1 | |
225 | #define XGMAC_IOCTL_CONTEXT 2 | |
226 | ||
43e0dcf7 LT |
227 | #define XGMAC_FIFO_MIN_ALLOC 2048 |
228 | #define XGMAC_FIFO_UNIT 256 | |
229 | #define XGMAC_FIFO_ALIGN(_x) \ | |
230 | (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) | |
231 | #define XGMAC_FIFO_FC_OFF 2048 | |
232 | #define XGMAC_FIFO_FC_MIN 4096 | |
c5aa9e3b | 233 | |
fca2d994 | 234 | #define XGBE_TC_MIN_QUANTUM 10 |
c5aa9e3b LT |
235 | |
236 | /* Helper macro for descriptor handling | |
d0a8ba6c | 237 | * Always use XGBE_GET_DESC_DATA to access the descriptor data |
c5aa9e3b LT |
238 | * since the index is free-running and needs to be and-ed |
239 | * with the descriptor count value of the ring to index to | |
240 | * the proper descriptor data. | |
241 | */ | |
d0a8ba6c | 242 | #define XGBE_GET_DESC_DATA(_ring, _idx) \ |
c5aa9e3b LT |
243 | ((_ring)->rdata + \ |
244 | ((_idx) & ((_ring)->rdesc_count - 1))) | |
245 | ||
c5aa9e3b | 246 | /* Default coalescing parameters */ |
c635eaac | 247 | #define XGMAC_INIT_DMA_TX_USECS 1000 |
9867e8fb | 248 | #define XGMAC_INIT_DMA_TX_FRAMES 25 |
c5aa9e3b LT |
249 | |
250 | #define XGMAC_MAX_DMA_RIWT 0xff | |
9867e8fb LT |
251 | #define XGMAC_INIT_DMA_RX_USECS 30 |
252 | #define XGMAC_INIT_DMA_RX_FRAMES 25 | |
c5aa9e3b LT |
253 | |
254 | /* Flow control queue count */ | |
255 | #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 | |
256 | ||
43e0dcf7 LT |
257 | /* Flow control threshold units */ |
258 | #define XGMAC_FLOW_CONTROL_UNIT 512 | |
259 | #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ | |
260 | (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) | |
261 | #define XGMAC_FLOW_CONTROL_VALUE(_x) \ | |
262 | (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) | |
263 | #define XGMAC_FLOW_CONTROL_MAX 33280 | |
264 | ||
b85e4d89 LT |
265 | /* Maximum MAC address hash table size (256 bits = 8 bytes) */ |
266 | #define XGBE_MAC_HASH_TABLE_SIZE 8 | |
c5aa9e3b | 267 | |
5b9dfe29 LT |
268 | /* Receive Side Scaling */ |
269 | #define XGBE_RSS_HASH_KEY_SIZE 40 | |
270 | #define XGBE_RSS_MAX_TABLE_SIZE 256 | |
271 | #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 | |
272 | #define XGBE_RSS_HASH_KEY_TYPE 1 | |
273 | ||
7c12aa08 LT |
274 | /* Auto-negotiation */ |
275 | #define XGBE_AN_MS_TIMEOUT 500 | |
1bf40ada LT |
276 | #define XGBE_LINK_TIMEOUT 5 |
277 | ||
278 | #define XGBE_SGMII_AN_LINK_STATUS BIT(1) | |
279 | #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) | |
280 | #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 | |
281 | #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 | |
282 | #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) | |
7c12aa08 | 283 | |
c5aa9e3b LT |
284 | struct xgbe_prv_data; |
285 | ||
286 | struct xgbe_packet_data { | |
16958a2b LT |
287 | struct sk_buff *skb; |
288 | ||
c5aa9e3b LT |
289 | unsigned int attributes; |
290 | ||
291 | unsigned int errors; | |
292 | ||
293 | unsigned int rdesc_count; | |
294 | unsigned int length; | |
295 | ||
296 | unsigned int header_len; | |
297 | unsigned int tcp_header_len; | |
298 | unsigned int tcp_payload_len; | |
299 | unsigned short mss; | |
300 | ||
301 | unsigned short vlan_ctag; | |
23e4eef7 LT |
302 | |
303 | u64 rx_tstamp; | |
5b9dfe29 LT |
304 | |
305 | u32 rss_hash; | |
306 | enum pkt_hash_types rss_hash_type; | |
5fb4b86a LT |
307 | |
308 | unsigned int tx_packets; | |
309 | unsigned int tx_bytes; | |
c5aa9e3b LT |
310 | }; |
311 | ||
312 | /* Common Rx and Tx descriptor mapping */ | |
313 | struct xgbe_ring_desc { | |
5226cfc5 LT |
314 | __le32 desc0; |
315 | __le32 desc1; | |
316 | __le32 desc2; | |
317 | __le32 desc3; | |
c5aa9e3b LT |
318 | }; |
319 | ||
08dcc47c LT |
320 | /* Page allocation related values */ |
321 | struct xgbe_page_alloc { | |
322 | struct page *pages; | |
323 | unsigned int pages_len; | |
324 | unsigned int pages_offset; | |
325 | ||
326 | dma_addr_t pages_dma; | |
327 | }; | |
328 | ||
174fd259 LT |
329 | /* Ring entry buffer data */ |
330 | struct xgbe_buffer_data { | |
331 | struct xgbe_page_alloc pa; | |
332 | struct xgbe_page_alloc pa_unmap; | |
333 | ||
cfbfd86b LT |
334 | dma_addr_t dma_base; |
335 | unsigned long dma_off; | |
174fd259 LT |
336 | unsigned int dma_len; |
337 | }; | |
338 | ||
c9f140eb LT |
339 | /* Tx-related ring data */ |
340 | struct xgbe_tx_ring_data { | |
5fb4b86a LT |
341 | unsigned int packets; /* BQL packet count */ |
342 | unsigned int bytes; /* BQL byte count */ | |
c9f140eb LT |
343 | }; |
344 | ||
345 | /* Rx-related ring data */ | |
346 | struct xgbe_rx_ring_data { | |
347 | struct xgbe_buffer_data hdr; /* Header locations */ | |
348 | struct xgbe_buffer_data buf; /* Payload locations */ | |
349 | ||
350 | unsigned short hdr_len; /* Length of received header */ | |
351 | unsigned short len; /* Length of received packet */ | |
352 | }; | |
353 | ||
c5aa9e3b LT |
354 | /* Structure used to hold information related to the descriptor |
355 | * and the packet associated with the descriptor (always use | |
d0a8ba6c | 356 | * use the XGBE_GET_DESC_DATA macro to access this data from the ring) |
c5aa9e3b LT |
357 | */ |
358 | struct xgbe_ring_data { | |
359 | struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ | |
360 | dma_addr_t rdesc_dma; /* DMA address of descriptor */ | |
361 | ||
362 | struct sk_buff *skb; /* Virtual address of SKB */ | |
363 | dma_addr_t skb_dma; /* DMA address of SKB data */ | |
364 | unsigned int skb_dma_len; /* Length of SKB DMA area */ | |
c5aa9e3b | 365 | |
c9f140eb LT |
366 | struct xgbe_tx_ring_data tx; /* Tx-related data */ |
367 | struct xgbe_rx_ring_data rx; /* Rx-related data */ | |
c5aa9e3b | 368 | |
c5aa9e3b | 369 | unsigned int mapped_as_page; |
23e4eef7 LT |
370 | |
371 | /* Incomplete receive save location. If the budget is exhausted | |
372 | * or the last descriptor (last normal descriptor or a following | |
373 | * context descriptor) has not been DMA'd yet the current state | |
374 | * of the receive processing needs to be saved. | |
375 | */ | |
376 | unsigned int state_saved; | |
377 | struct { | |
23e4eef7 LT |
378 | struct sk_buff *skb; |
379 | unsigned int len; | |
380 | unsigned int error; | |
381 | } state; | |
c5aa9e3b LT |
382 | }; |
383 | ||
384 | struct xgbe_ring { | |
385 | /* Ring lock - used just for TX rings at the moment */ | |
386 | spinlock_t lock; | |
387 | ||
388 | /* Per packet related information */ | |
389 | struct xgbe_packet_data packet_data; | |
390 | ||
391 | /* Virtual/DMA addresses and count of allocated descriptor memory */ | |
392 | struct xgbe_ring_desc *rdesc; | |
393 | dma_addr_t rdesc_dma; | |
394 | unsigned int rdesc_count; | |
395 | ||
396 | /* Array of descriptor data corresponding the descriptor memory | |
d0a8ba6c | 397 | * (always use the XGBE_GET_DESC_DATA macro to access this data) |
c5aa9e3b LT |
398 | */ |
399 | struct xgbe_ring_data *rdata; | |
400 | ||
08dcc47c | 401 | /* Page allocation for RX buffers */ |
174fd259 LT |
402 | struct xgbe_page_alloc rx_hdr_pa; |
403 | struct xgbe_page_alloc rx_buf_pa; | |
08dcc47c | 404 | |
c5aa9e3b LT |
405 | /* Ring index values |
406 | * cur - Tx: index of descriptor to be used for current transfer | |
407 | * Rx: index of descriptor to check for packet availability | |
408 | * dirty - Tx: index of descriptor to check for transfer complete | |
270894e7 | 409 | * Rx: index of descriptor to check for buffer reallocation |
c5aa9e3b LT |
410 | */ |
411 | unsigned int cur; | |
412 | unsigned int dirty; | |
413 | ||
414 | /* Coalesce frame count used for interrupt bit setting */ | |
415 | unsigned int coalesce_count; | |
416 | ||
417 | union { | |
418 | struct { | |
419 | unsigned int queue_stopped; | |
16958a2b | 420 | unsigned int xmit_more; |
c5aa9e3b LT |
421 | unsigned short cur_mss; |
422 | unsigned short cur_vlan_ctag; | |
423 | } tx; | |
c5aa9e3b LT |
424 | }; |
425 | } ____cacheline_aligned; | |
426 | ||
427 | /* Structure used to describe the descriptor rings associated with | |
428 | * a DMA channel. | |
429 | */ | |
430 | struct xgbe_channel { | |
431 | char name[16]; | |
432 | ||
433 | /* Address of private data area for device */ | |
434 | struct xgbe_prv_data *pdata; | |
435 | ||
436 | /* Queue index and base address of queue's DMA registers */ | |
437 | unsigned int queue_index; | |
438 | void __iomem *dma_regs; | |
439 | ||
9227dc5e LT |
440 | /* Per channel interrupt irq number */ |
441 | int dma_irq; | |
54ceb9ec | 442 | char dma_irq_name[IFNAMSIZ + 32]; |
9227dc5e LT |
443 | |
444 | /* Netdev related settings */ | |
445 | struct napi_struct napi; | |
446 | ||
c5aa9e3b LT |
447 | unsigned int saved_ier; |
448 | ||
449 | unsigned int tx_timer_active; | |
c635eaac | 450 | struct timer_list tx_timer; |
c5aa9e3b LT |
451 | |
452 | struct xgbe_ring *tx_ring; | |
453 | struct xgbe_ring *rx_ring; | |
454 | } ____cacheline_aligned; | |
455 | ||
7c12aa08 LT |
456 | enum xgbe_state { |
457 | XGBE_DOWN, | |
7c12aa08 LT |
458 | XGBE_LINK_INIT, |
459 | XGBE_LINK_ERR, | |
460 | }; | |
461 | ||
c5aa9e3b | 462 | enum xgbe_int { |
c5aa9e3b LT |
463 | XGMAC_INT_DMA_CH_SR_TI, |
464 | XGMAC_INT_DMA_CH_SR_TPS, | |
465 | XGMAC_INT_DMA_CH_SR_TBU, | |
466 | XGMAC_INT_DMA_CH_SR_RI, | |
467 | XGMAC_INT_DMA_CH_SR_RBU, | |
468 | XGMAC_INT_DMA_CH_SR_RPS, | |
9867e8fb | 469 | XGMAC_INT_DMA_CH_SR_TI_RI, |
c5aa9e3b LT |
470 | XGMAC_INT_DMA_CH_SR_FBE, |
471 | XGMAC_INT_DMA_ALL, | |
472 | }; | |
473 | ||
474 | enum xgbe_int_state { | |
475 | XGMAC_INT_STATE_SAVE, | |
476 | XGMAC_INT_STATE_RESTORE, | |
477 | }; | |
478 | ||
7c12aa08 LT |
479 | enum xgbe_speed { |
480 | XGBE_SPEED_1000 = 0, | |
481 | XGBE_SPEED_2500, | |
482 | XGBE_SPEED_10000, | |
483 | XGBE_SPEEDS, | |
484 | }; | |
485 | ||
b03a4a6f LT |
486 | enum xgbe_xpcs_access { |
487 | XGBE_XPCS_ACCESS_V1 = 0, | |
488 | XGBE_XPCS_ACCESS_V2, | |
489 | }; | |
490 | ||
a64def41 LT |
491 | enum xgbe_an_mode { |
492 | XGBE_AN_MODE_CL73 = 0, | |
1bf40ada LT |
493 | XGBE_AN_MODE_CL37, |
494 | XGBE_AN_MODE_CL37_SGMII, | |
a64def41 LT |
495 | XGBE_AN_MODE_NONE, |
496 | }; | |
497 | ||
7c12aa08 LT |
498 | enum xgbe_an { |
499 | XGBE_AN_READY = 0, | |
500 | XGBE_AN_PAGE_RECEIVED, | |
501 | XGBE_AN_INCOMPAT_LINK, | |
502 | XGBE_AN_COMPLETE, | |
503 | XGBE_AN_NO_LINK, | |
504 | XGBE_AN_ERROR, | |
505 | }; | |
506 | ||
507 | enum xgbe_rx { | |
508 | XGBE_RX_BPA = 0, | |
509 | XGBE_RX_XNP, | |
510 | XGBE_RX_COMPLETE, | |
511 | XGBE_RX_ERROR, | |
512 | }; | |
513 | ||
514 | enum xgbe_mode { | |
e57f7a3f LT |
515 | XGBE_MODE_KX_1000 = 0, |
516 | XGBE_MODE_KX_2500, | |
517 | XGBE_MODE_KR, | |
518 | XGBE_MODE_UNKNOWN, | |
7c12aa08 LT |
519 | }; |
520 | ||
521 | enum xgbe_speedset { | |
522 | XGBE_SPEEDSET_1000_10000 = 0, | |
523 | XGBE_SPEEDSET_2500_10000, | |
524 | }; | |
525 | ||
526 | struct xgbe_phy { | |
527 | u32 supported; | |
528 | u32 advertising; | |
529 | u32 lp_advertising; | |
530 | ||
531 | int address; | |
532 | ||
533 | int autoneg; | |
534 | int speed; | |
535 | int duplex; | |
7c12aa08 LT |
536 | |
537 | int link; | |
c1ce2f77 LT |
538 | |
539 | int pause_autoneg; | |
540 | int tx_pause; | |
541 | int rx_pause; | |
7c12aa08 LT |
542 | }; |
543 | ||
c5aa9e3b LT |
544 | struct xgbe_mmc_stats { |
545 | /* Tx Stats */ | |
546 | u64 txoctetcount_gb; | |
547 | u64 txframecount_gb; | |
548 | u64 txbroadcastframes_g; | |
549 | u64 txmulticastframes_g; | |
550 | u64 tx64octets_gb; | |
551 | u64 tx65to127octets_gb; | |
552 | u64 tx128to255octets_gb; | |
553 | u64 tx256to511octets_gb; | |
554 | u64 tx512to1023octets_gb; | |
555 | u64 tx1024tomaxoctets_gb; | |
556 | u64 txunicastframes_gb; | |
557 | u64 txmulticastframes_gb; | |
558 | u64 txbroadcastframes_gb; | |
559 | u64 txunderflowerror; | |
560 | u64 txoctetcount_g; | |
561 | u64 txframecount_g; | |
562 | u64 txpauseframes; | |
563 | u64 txvlanframes_g; | |
564 | ||
565 | /* Rx Stats */ | |
566 | u64 rxframecount_gb; | |
567 | u64 rxoctetcount_gb; | |
568 | u64 rxoctetcount_g; | |
569 | u64 rxbroadcastframes_g; | |
570 | u64 rxmulticastframes_g; | |
571 | u64 rxcrcerror; | |
572 | u64 rxrunterror; | |
573 | u64 rxjabbererror; | |
574 | u64 rxundersize_g; | |
575 | u64 rxoversize_g; | |
576 | u64 rx64octets_gb; | |
577 | u64 rx65to127octets_gb; | |
578 | u64 rx128to255octets_gb; | |
579 | u64 rx256to511octets_gb; | |
580 | u64 rx512to1023octets_gb; | |
581 | u64 rx1024tomaxoctets_gb; | |
582 | u64 rxunicastframes_g; | |
583 | u64 rxlengtherror; | |
584 | u64 rxoutofrangetype; | |
585 | u64 rxpauseframes; | |
586 | u64 rxfifooverflow; | |
587 | u64 rxvlanframes_gb; | |
588 | u64 rxwatchdogerror; | |
589 | }; | |
590 | ||
5452b2df LT |
591 | struct xgbe_ext_stats { |
592 | u64 tx_tso_packets; | |
593 | u64 rx_split_header_packets; | |
72c9ac4e | 594 | u64 rx_buffer_unavailable; |
5452b2df LT |
595 | }; |
596 | ||
c5aa9e3b LT |
597 | struct xgbe_hw_if { |
598 | int (*tx_complete)(struct xgbe_ring_desc *); | |
599 | ||
c5aa9e3b | 600 | int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); |
b876382b | 601 | int (*config_rx_mode)(struct xgbe_prv_data *); |
c5aa9e3b LT |
602 | |
603 | int (*enable_rx_csum)(struct xgbe_prv_data *); | |
604 | int (*disable_rx_csum)(struct xgbe_prv_data *); | |
605 | ||
606 | int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); | |
607 | int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); | |
801c62d9 LT |
608 | int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); |
609 | int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); | |
610 | int (*update_vlan_hash_table)(struct xgbe_prv_data *); | |
c5aa9e3b LT |
611 | |
612 | int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); | |
613 | void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); | |
e57f7a3f | 614 | int (*set_speed)(struct xgbe_prv_data *, int); |
c5aa9e3b LT |
615 | |
616 | void (*enable_tx)(struct xgbe_prv_data *); | |
617 | void (*disable_tx)(struct xgbe_prv_data *); | |
618 | void (*enable_rx)(struct xgbe_prv_data *); | |
619 | void (*disable_rx)(struct xgbe_prv_data *); | |
620 | ||
621 | void (*powerup_tx)(struct xgbe_prv_data *); | |
622 | void (*powerdown_tx)(struct xgbe_prv_data *); | |
623 | void (*powerup_rx)(struct xgbe_prv_data *); | |
624 | void (*powerdown_rx)(struct xgbe_prv_data *); | |
625 | ||
626 | int (*init)(struct xgbe_prv_data *); | |
627 | int (*exit)(struct xgbe_prv_data *); | |
628 | ||
629 | int (*enable_int)(struct xgbe_channel *, enum xgbe_int); | |
630 | int (*disable_int)(struct xgbe_channel *, enum xgbe_int); | |
a9d41981 | 631 | void (*dev_xmit)(struct xgbe_channel *); |
c5aa9e3b LT |
632 | int (*dev_read)(struct xgbe_channel *); |
633 | void (*tx_desc_init)(struct xgbe_channel *); | |
634 | void (*rx_desc_init)(struct xgbe_channel *); | |
c5aa9e3b | 635 | void (*tx_desc_reset)(struct xgbe_ring_data *); |
8dee19e6 LT |
636 | void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, |
637 | unsigned int); | |
c5aa9e3b LT |
638 | int (*is_last_desc)(struct xgbe_ring_desc *); |
639 | int (*is_context_desc)(struct xgbe_ring_desc *); | |
16958a2b | 640 | void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); |
c5aa9e3b LT |
641 | |
642 | /* For FLOW ctrl */ | |
643 | int (*config_tx_flow_control)(struct xgbe_prv_data *); | |
644 | int (*config_rx_flow_control)(struct xgbe_prv_data *); | |
645 | ||
646 | /* For RX coalescing */ | |
647 | int (*config_rx_coalesce)(struct xgbe_prv_data *); | |
648 | int (*config_tx_coalesce)(struct xgbe_prv_data *); | |
649 | unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); | |
650 | unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); | |
651 | ||
652 | /* For RX and TX threshold config */ | |
653 | int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); | |
654 | int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); | |
655 | ||
656 | /* For RX and TX Store and Forward Mode config */ | |
657 | int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); | |
658 | int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); | |
659 | ||
660 | /* For TX DMA Operate on Second Frame config */ | |
661 | int (*config_osp_mode)(struct xgbe_prv_data *); | |
662 | ||
663 | /* For RX and TX PBL config */ | |
664 | int (*config_rx_pbl_val)(struct xgbe_prv_data *); | |
665 | int (*get_rx_pbl_val)(struct xgbe_prv_data *); | |
666 | int (*config_tx_pbl_val)(struct xgbe_prv_data *); | |
667 | int (*get_tx_pbl_val)(struct xgbe_prv_data *); | |
668 | int (*config_pblx8)(struct xgbe_prv_data *); | |
669 | ||
670 | /* For MMC statistics */ | |
671 | void (*rx_mmc_int)(struct xgbe_prv_data *); | |
672 | void (*tx_mmc_int)(struct xgbe_prv_data *); | |
673 | void (*read_mmc_stats)(struct xgbe_prv_data *); | |
23e4eef7 LT |
674 | |
675 | /* For Timestamp config */ | |
676 | int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); | |
677 | void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); | |
678 | void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, | |
679 | unsigned int nsec); | |
680 | u64 (*get_tstamp_time)(struct xgbe_prv_data *); | |
681 | u64 (*get_tx_tstamp)(struct xgbe_prv_data *); | |
fca2d994 LT |
682 | |
683 | /* For Data Center Bridging config */ | |
b3b71597 | 684 | void (*config_tc)(struct xgbe_prv_data *); |
fca2d994 LT |
685 | void (*config_dcb_tc)(struct xgbe_prv_data *); |
686 | void (*config_dcb_pfc)(struct xgbe_prv_data *); | |
5b9dfe29 LT |
687 | |
688 | /* For Receive Side Scaling */ | |
689 | int (*enable_rss)(struct xgbe_prv_data *); | |
690 | int (*disable_rss)(struct xgbe_prv_data *); | |
f6ac8628 LT |
691 | int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); |
692 | int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); | |
c5aa9e3b LT |
693 | }; |
694 | ||
e57f7a3f LT |
695 | /* This structure represents implementation specific routines for an |
696 | * implementation of a PHY. All routines are required unless noted below. | |
697 | * Optional routines: | |
698 | * kr_training_pre, kr_training_post | |
699 | */ | |
700 | struct xgbe_phy_impl_if { | |
701 | /* Perform Setup/teardown actions */ | |
702 | int (*init)(struct xgbe_prv_data *); | |
703 | void (*exit)(struct xgbe_prv_data *); | |
704 | ||
705 | /* Perform start/stop specific actions */ | |
706 | int (*reset)(struct xgbe_prv_data *); | |
707 | int (*start)(struct xgbe_prv_data *); | |
708 | void (*stop)(struct xgbe_prv_data *); | |
709 | ||
710 | /* Return the link status */ | |
711 | int (*link_status)(struct xgbe_prv_data *); | |
712 | ||
713 | /* Indicate if a particular speed is valid */ | |
714 | bool (*valid_speed)(struct xgbe_prv_data *, int); | |
715 | ||
716 | /* Check if the specified mode can/should be used */ | |
717 | bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); | |
718 | /* Switch the PHY into various modes */ | |
719 | void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); | |
720 | /* Retrieve mode needed for a specific speed */ | |
721 | enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); | |
722 | /* Retrieve new/next mode when trying to auto-negotiate */ | |
723 | enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); | |
724 | /* Retrieve current mode */ | |
725 | enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); | |
726 | ||
a64def41 LT |
727 | /* Retrieve current auto-negotiation mode */ |
728 | enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); | |
729 | ||
e57f7a3f LT |
730 | /* Process results of auto-negotiation */ |
731 | enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); | |
732 | ||
733 | /* Pre/Post KR training enablement support */ | |
734 | void (*kr_training_pre)(struct xgbe_prv_data *); | |
735 | void (*kr_training_post)(struct xgbe_prv_data *); | |
736 | }; | |
737 | ||
7c12aa08 | 738 | struct xgbe_phy_if { |
e57f7a3f LT |
739 | /* For PHY setup/teardown */ |
740 | int (*phy_init)(struct xgbe_prv_data *); | |
741 | void (*phy_exit)(struct xgbe_prv_data *); | |
7c12aa08 LT |
742 | |
743 | /* For PHY support when setting device up/down */ | |
744 | int (*phy_reset)(struct xgbe_prv_data *); | |
745 | int (*phy_start)(struct xgbe_prv_data *); | |
746 | void (*phy_stop)(struct xgbe_prv_data *); | |
747 | ||
748 | /* For PHY support while device is up */ | |
749 | void (*phy_status)(struct xgbe_prv_data *); | |
750 | int (*phy_config_aneg)(struct xgbe_prv_data *); | |
e57f7a3f LT |
751 | |
752 | /* For PHY settings validation */ | |
753 | bool (*phy_valid_speed)(struct xgbe_prv_data *, int); | |
754 | ||
47f164de LT |
755 | /* For single interrupt support */ |
756 | irqreturn_t (*an_isr)(int, struct xgbe_prv_data *); | |
757 | ||
e57f7a3f LT |
758 | /* PHY implementation specific services */ |
759 | struct xgbe_phy_impl_if phy_impl; | |
7c12aa08 LT |
760 | }; |
761 | ||
c5aa9e3b LT |
762 | struct xgbe_desc_if { |
763 | int (*alloc_ring_resources)(struct xgbe_prv_data *); | |
764 | void (*free_ring_resources)(struct xgbe_prv_data *); | |
765 | int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); | |
270894e7 LT |
766 | int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, |
767 | struct xgbe_ring_data *); | |
08dcc47c | 768 | void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); |
c5aa9e3b LT |
769 | void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); |
770 | void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); | |
771 | }; | |
772 | ||
773 | /* This structure contains flags that indicate what hardware features | |
774 | * or configurations are present in the device. | |
775 | */ | |
776 | struct xgbe_hw_features { | |
a9a4a2d9 LT |
777 | /* HW Version */ |
778 | unsigned int version; | |
779 | ||
c5aa9e3b LT |
780 | /* HW Feature Register0 */ |
781 | unsigned int gmii; /* 1000 Mbps support */ | |
782 | unsigned int vlhash; /* VLAN Hash Filter */ | |
783 | unsigned int sma; /* SMA(MDIO) Interface */ | |
784 | unsigned int rwk; /* PMT remote wake-up packet */ | |
785 | unsigned int mgk; /* PMT magic packet */ | |
786 | unsigned int mmc; /* RMON module */ | |
787 | unsigned int aoe; /* ARP Offload */ | |
dbedd44e | 788 | unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ |
c5aa9e3b LT |
789 | unsigned int eee; /* Energy Efficient Ethernet */ |
790 | unsigned int tx_coe; /* Tx Checksum Offload */ | |
791 | unsigned int rx_coe; /* Rx Checksum Offload */ | |
792 | unsigned int addn_mac; /* Additional MAC Addresses */ | |
793 | unsigned int ts_src; /* Timestamp Source */ | |
794 | unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ | |
795 | ||
796 | /* HW Feature Register1 */ | |
797 | unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ | |
798 | unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ | |
799 | unsigned int adv_ts_hi; /* Advance Timestamping High Word */ | |
386d325d | 800 | unsigned int dma_width; /* DMA width */ |
c5aa9e3b LT |
801 | unsigned int dcb; /* DCB Feature */ |
802 | unsigned int sph; /* Split Header Feature */ | |
803 | unsigned int tso; /* TCP Segmentation Offload */ | |
804 | unsigned int dma_debug; /* DMA Debug Registers */ | |
805 | unsigned int rss; /* Receive Side Scaling */ | |
fca2d994 | 806 | unsigned int tc_cnt; /* Number of Traffic Classes */ |
c5aa9e3b LT |
807 | unsigned int hash_table_size; /* Hash Table Size */ |
808 | unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ | |
809 | ||
810 | /* HW Feature Register2 */ | |
811 | unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ | |
812 | unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ | |
813 | unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ | |
814 | unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ | |
815 | unsigned int pps_out_num; /* Number of PPS outputs */ | |
816 | unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ | |
817 | }; | |
818 | ||
e57f7a3f LT |
819 | struct xgbe_version_data { |
820 | void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); | |
b03a4a6f | 821 | enum xgbe_xpcs_access xpcs_access; |
e5a20b90 | 822 | unsigned int mmc_64bit; |
bd8255d8 LT |
823 | unsigned int tx_max_fifo_size; |
824 | unsigned int rx_max_fifo_size; | |
aba9777a | 825 | unsigned int tx_tstamp_workaround; |
e57f7a3f LT |
826 | }; |
827 | ||
c5aa9e3b LT |
828 | struct xgbe_prv_data { |
829 | struct net_device *netdev; | |
47f164de | 830 | struct pci_dev *pcidev; |
bd8255d8 | 831 | struct platform_device *platdev; |
82a19035 | 832 | struct acpi_device *adev; |
c5aa9e3b | 833 | struct device *dev; |
bd8255d8 | 834 | struct platform_device *phy_platdev; |
e57f7a3f LT |
835 | struct device *phy_dev; |
836 | ||
837 | /* Version related data */ | |
838 | struct xgbe_version_data *vdata; | |
c5aa9e3b | 839 | |
82a19035 LT |
840 | /* ACPI or DT flag */ |
841 | unsigned int use_acpi; | |
842 | ||
c5aa9e3b LT |
843 | /* XGMAC/XPCS related mmio registers */ |
844 | void __iomem *xgmac_regs; /* XGMAC CSRs */ | |
845 | void __iomem *xpcs_regs; /* XPCS MMD registers */ | |
7c12aa08 LT |
846 | void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ |
847 | void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ | |
848 | void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ | |
47f164de LT |
849 | void __iomem *xprop_regs; /* XGBE property registers */ |
850 | void __iomem *xi2c_regs; /* XGBE I2C CSRs */ | |
c5aa9e3b LT |
851 | |
852 | /* Overall device lock */ | |
853 | spinlock_t lock; | |
854 | ||
ced3fcae LT |
855 | /* XPCS indirect addressing lock */ |
856 | spinlock_t xpcs_lock; | |
b03a4a6f LT |
857 | unsigned int xpcs_window; |
858 | unsigned int xpcs_window_size; | |
859 | unsigned int xpcs_window_mask; | |
c5aa9e3b | 860 | |
5b9dfe29 LT |
861 | /* RSS addressing mutex */ |
862 | struct mutex rss_mutex; | |
863 | ||
7c12aa08 LT |
864 | /* Flags representing xgbe_state */ |
865 | unsigned long dev_state; | |
866 | ||
47f164de | 867 | struct msix_entry *msix_entries; |
9227dc5e | 868 | int dev_irq; |
47f164de LT |
869 | int ecc_irq; |
870 | int i2c_irq; | |
bd8255d8 | 871 | int channel_irq[XGBE_MAX_DMA_CHANNELS]; |
c5aa9e3b | 872 | |
47f164de LT |
873 | unsigned int per_channel_irq; |
874 | unsigned int irq_shared; | |
875 | unsigned int irq_count; | |
876 | unsigned int channel_irq_count; | |
877 | ||
c5aa9e3b | 878 | struct xgbe_hw_if hw_if; |
7c12aa08 | 879 | struct xgbe_phy_if phy_if; |
c5aa9e3b LT |
880 | struct xgbe_desc_if desc_if; |
881 | ||
cfa50c78 | 882 | /* AXI DMA settings */ |
82a19035 | 883 | unsigned int coherent; |
cfa50c78 LT |
884 | unsigned int axdomain; |
885 | unsigned int arcache; | |
886 | unsigned int awcache; | |
887 | ||
7c12aa08 LT |
888 | /* Service routine support */ |
889 | struct workqueue_struct *dev_workqueue; | |
890 | struct work_struct service_work; | |
891 | struct timer_list service_timer; | |
892 | ||
c5aa9e3b LT |
893 | /* Rings for Tx/Rx on a DMA channel */ |
894 | struct xgbe_channel *channel; | |
bd8255d8 LT |
895 | unsigned int tx_max_channel_count; |
896 | unsigned int rx_max_channel_count; | |
c5aa9e3b LT |
897 | unsigned int channel_count; |
898 | unsigned int tx_ring_count; | |
899 | unsigned int tx_desc_count; | |
900 | unsigned int rx_ring_count; | |
901 | unsigned int rx_desc_count; | |
902 | ||
bd8255d8 LT |
903 | unsigned int tx_max_q_count; |
904 | unsigned int rx_max_q_count; | |
853eb16b LT |
905 | unsigned int tx_q_count; |
906 | unsigned int rx_q_count; | |
907 | ||
c5aa9e3b LT |
908 | /* Tx/Rx common settings */ |
909 | unsigned int pblx8; | |
910 | ||
911 | /* Tx settings */ | |
912 | unsigned int tx_sf_mode; | |
913 | unsigned int tx_threshold; | |
914 | unsigned int tx_pbl; | |
915 | unsigned int tx_osp_mode; | |
bd8255d8 | 916 | unsigned int tx_max_fifo_size; |
c5aa9e3b LT |
917 | |
918 | /* Rx settings */ | |
919 | unsigned int rx_sf_mode; | |
920 | unsigned int rx_threshold; | |
921 | unsigned int rx_pbl; | |
bd8255d8 | 922 | unsigned int rx_max_fifo_size; |
c5aa9e3b LT |
923 | |
924 | /* Tx coalescing settings */ | |
925 | unsigned int tx_usecs; | |
926 | unsigned int tx_frames; | |
927 | ||
928 | /* Rx coalescing settings */ | |
929 | unsigned int rx_riwt; | |
4a57ebcc | 930 | unsigned int rx_usecs; |
c5aa9e3b LT |
931 | unsigned int rx_frames; |
932 | ||
08dcc47c | 933 | /* Current Rx buffer size */ |
c5aa9e3b LT |
934 | unsigned int rx_buf_size; |
935 | ||
936 | /* Flow control settings */ | |
937 | unsigned int pause_autoneg; | |
938 | unsigned int tx_pause; | |
939 | unsigned int rx_pause; | |
43e0dcf7 LT |
940 | unsigned int rx_rfa[XGBE_MAX_QUEUES]; |
941 | unsigned int rx_rfd[XGBE_MAX_QUEUES]; | |
c5aa9e3b | 942 | |
5b9dfe29 LT |
943 | /* Receive Side Scaling settings */ |
944 | u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; | |
945 | u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; | |
946 | u32 rss_options; | |
947 | ||
c5aa9e3b | 948 | /* Netdev related settings */ |
82a19035 | 949 | unsigned char mac_addr[ETH_ALEN]; |
c5aa9e3b LT |
950 | netdev_features_t netdev_features; |
951 | struct napi_struct napi; | |
952 | struct xgbe_mmc_stats mmc_stats; | |
5452b2df | 953 | struct xgbe_ext_stats ext_stats; |
c5aa9e3b | 954 | |
801c62d9 LT |
955 | /* Filtering support */ |
956 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
957 | ||
23e4eef7 LT |
958 | /* Device clocks */ |
959 | struct clk *sysclk; | |
82a19035 | 960 | unsigned long sysclk_rate; |
23e4eef7 | 961 | struct clk *ptpclk; |
82a19035 | 962 | unsigned long ptpclk_rate; |
23e4eef7 LT |
963 | |
964 | /* Timestamp support */ | |
965 | spinlock_t tstamp_lock; | |
966 | struct ptp_clock_info ptp_clock_info; | |
967 | struct ptp_clock *ptp_clock; | |
968 | struct hwtstamp_config tstamp_config; | |
969 | struct cyclecounter tstamp_cc; | |
970 | struct timecounter tstamp_tc; | |
971 | unsigned int tstamp_addend; | |
972 | struct work_struct tx_tstamp_work; | |
973 | struct sk_buff *tx_tstamp_skb; | |
974 | u64 tx_tstamp; | |
c5aa9e3b | 975 | |
fca2d994 LT |
976 | /* DCB support */ |
977 | struct ieee_ets *ets; | |
978 | struct ieee_pfc *pfc; | |
979 | unsigned int q2tc_map[XGBE_MAX_QUEUES]; | |
980 | unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; | |
43e0dcf7 LT |
981 | unsigned int pfcq[XGBE_MAX_QUEUES]; |
982 | unsigned int pfc_rfa; | |
b3b71597 | 983 | u8 num_tcs; |
fca2d994 | 984 | |
c5aa9e3b LT |
985 | /* Hardware features of the device */ |
986 | struct xgbe_hw_features hw_feat; | |
987 | ||
988 | /* Device restart work structure */ | |
989 | struct work_struct restart_work; | |
990 | ||
991 | /* Keeps track of power mode */ | |
992 | unsigned int power_down; | |
993 | ||
34bf65df LT |
994 | /* Network interface message level setting */ |
995 | u32 msg_enable; | |
996 | ||
7c12aa08 LT |
997 | /* Current PHY settings */ |
998 | phy_interface_t phy_mode; | |
999 | int phy_link; | |
1000 | int phy_speed; | |
7c12aa08 LT |
1001 | |
1002 | /* MDIO/PHY related settings */ | |
e57f7a3f LT |
1003 | unsigned int phy_started; |
1004 | void *phy_data; | |
7c12aa08 LT |
1005 | struct xgbe_phy phy; |
1006 | int mdio_mmd; | |
1007 | unsigned long link_check; | |
1008 | ||
1009 | char an_name[IFNAMSIZ + 32]; | |
1010 | struct workqueue_struct *an_workqueue; | |
1011 | ||
1012 | int an_irq; | |
1013 | struct work_struct an_irq_work; | |
1014 | ||
7c12aa08 | 1015 | /* Auto-negotiation state machine support */ |
ced3fcae | 1016 | unsigned int an_int; |
1bf40ada | 1017 | unsigned int an_status; |
7c12aa08 LT |
1018 | struct mutex an_mutex; |
1019 | enum xgbe_an an_result; | |
1020 | enum xgbe_an an_state; | |
1021 | enum xgbe_rx kr_state; | |
1022 | enum xgbe_rx kx_state; | |
1023 | struct work_struct an_work; | |
1024 | unsigned int an_supported; | |
1025 | unsigned int parallel_detect; | |
1026 | unsigned int fec_ability; | |
1027 | unsigned long an_start; | |
a64def41 | 1028 | enum xgbe_an_mode an_mode; |
7c12aa08 LT |
1029 | |
1030 | unsigned int lpm_ctrl; /* CTRL1 for resume */ | |
1031 | ||
c5aa9e3b LT |
1032 | #ifdef CONFIG_DEBUG_FS |
1033 | struct dentry *xgbe_debugfs; | |
1034 | ||
1035 | unsigned int debugfs_xgmac_reg; | |
1036 | ||
1037 | unsigned int debugfs_xpcs_mmd; | |
1038 | unsigned int debugfs_xpcs_reg; | |
47f164de LT |
1039 | |
1040 | unsigned int debugfs_xprop_reg; | |
c5aa9e3b LT |
1041 | #endif |
1042 | }; | |
1043 | ||
1044 | /* Function prototypes*/ | |
bd8255d8 LT |
1045 | struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); |
1046 | void xgbe_free_pdata(struct xgbe_prv_data *); | |
1047 | void xgbe_set_counts(struct xgbe_prv_data *); | |
1048 | int xgbe_config_netdev(struct xgbe_prv_data *); | |
1049 | void xgbe_deconfig_netdev(struct xgbe_prv_data *); | |
1050 | ||
1051 | int xgbe_platform_init(void); | |
1052 | void xgbe_platform_exit(void); | |
47f164de LT |
1053 | #ifdef CONFIG_PCI |
1054 | int xgbe_pci_init(void); | |
1055 | void xgbe_pci_exit(void); | |
1056 | #else | |
1057 | static inline int xgbe_pci_init(void) { return 0; } | |
1058 | static inline void xgbe_pci_exit(void) { } | |
1059 | #endif | |
c5aa9e3b LT |
1060 | |
1061 | void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); | |
7c12aa08 | 1062 | void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); |
e57f7a3f | 1063 | void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); |
47f164de | 1064 | void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); |
c5aa9e3b | 1065 | void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); |
ce0b15d1 | 1066 | const struct net_device_ops *xgbe_get_netdev_ops(void); |
1067 | const struct ethtool_ops *xgbe_get_ethtool_ops(void); | |
1068 | ||
fca2d994 LT |
1069 | #ifdef CONFIG_AMD_XGBE_DCB |
1070 | const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); | |
1071 | #endif | |
c5aa9e3b | 1072 | |
23e4eef7 LT |
1073 | void xgbe_ptp_register(struct xgbe_prv_data *); |
1074 | void xgbe_ptp_unregister(struct xgbe_prv_data *); | |
34bf65df LT |
1075 | void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, |
1076 | unsigned int, unsigned int, unsigned int); | |
1077 | void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, | |
c5aa9e3b LT |
1078 | unsigned int); |
1079 | void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); | |
1080 | void xgbe_get_all_hw_features(struct xgbe_prv_data *); | |
1081 | int xgbe_powerup(struct net_device *, unsigned int); | |
1082 | int xgbe_powerdown(struct net_device *, unsigned int); | |
1083 | void xgbe_init_rx_coalesce(struct xgbe_prv_data *); | |
1084 | void xgbe_init_tx_coalesce(struct xgbe_prv_data *); | |
1085 | ||
1086 | #ifdef CONFIG_DEBUG_FS | |
1087 | void xgbe_debugfs_init(struct xgbe_prv_data *); | |
1088 | void xgbe_debugfs_exit(struct xgbe_prv_data *); | |
1089 | #else | |
1090 | static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} | |
1091 | static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} | |
1092 | #endif /* CONFIG_DEBUG_FS */ | |
1093 | ||
c5aa9e3b LT |
1094 | /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ |
1095 | #if 0 | |
1096 | #define YDEBUG | |
1097 | #define YDEBUG_MDIO | |
1098 | #endif | |
1099 | ||
1100 | /* For debug prints */ | |
1101 | #ifdef YDEBUG | |
1102 | #define DBGPR(x...) pr_alert(x) | |
c5aa9e3b LT |
1103 | #else |
1104 | #define DBGPR(x...) do { } while (0) | |
c5aa9e3b LT |
1105 | #endif |
1106 | ||
1107 | #ifdef YDEBUG_MDIO | |
1108 | #define DBGPR_MDIO(x...) pr_alert(x) | |
1109 | #else | |
1110 | #define DBGPR_MDIO(x...) do { } while (0) | |
1111 | #endif | |
1112 | ||
1113 | #endif |