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amd-xgbe: Provide support for receive side scaling
[thirdparty/kernel/stable.git] / drivers / net / ethernet / amd / xgbe / xgbe.h
CommitLineData
c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#ifndef __XGBE_H__
118#define __XGBE_H__
119
120#include <linux/dma-mapping.h>
121#include <linux/netdevice.h>
122#include <linux/workqueue.h>
123#include <linux/phy.h>
801c62d9
LT		 124#include <linux/if_vlan.h>
125#include <linux/bitops.h>
23e4eef7
LT		 126#include <linux/ptp_clock_kernel.h>
127#include <linux/clocksource.h>
128#include <linux/net_tstamp.h>
fca2d994 129#include <net/dcbnl.h>
c5aa9e3b 130
c5aa9e3b
LT		 131#define XGBE_DRV_NAME "amd-xgbe"
132#define XGBE_DRV_VERSION "1.0.0-a"
133#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
134
135/* Descriptor related defines */
d0a8ba6c
LT		 136#define XGBE_TX_DESC_CNT 512
137#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139#define XGBE_RX_DESC_CNT 512
c5aa9e3b 140
d0a8ba6c 141#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
c5aa9e3b 142
d0a8ba6c
LT		 143#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
144#define XGBE_RX_BUF_ALIGN 64
08dcc47c 145#define XGBE_SKB_ALLOC_SIZE 256
174fd259 146#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
c5aa9e3b 147
d5c48582 148#define XGBE_MAX_DMA_CHANNELS 16
fca2d994 149#define XGBE_MAX_QUEUES 16
d0a8ba6c
LT		 150
151/* DMA cache settings - Outer sharable, write-back, write-allocate */
cfa50c78
LT		 152#define XGBE_DMA_OS_AXDOMAIN 0x2
153#define XGBE_DMA_OS_ARCACHE 0xb
154#define XGBE_DMA_OS_AWCACHE 0xf
155
156/* DMA cache settings - System, no caches used */
157#define XGBE_DMA_SYS_AXDOMAIN 0x3
158#define XGBE_DMA_SYS_ARCACHE 0x0
159#define XGBE_DMA_SYS_AWCACHE 0x0
d0a8ba6c
LT		 160
161#define XGBE_DMA_INTERRUPT_MASK 0x31c7
c5aa9e3b
LT		 162
163#define XGMAC_MIN_PACKET 60
164#define XGMAC_STD_PACKET_MTU 1500
165#define XGMAC_MAX_STD_PACKET 1518
166#define XGMAC_JUMBO_PACKET_MTU 9000
167#define XGMAC_MAX_JUMBO_PACKET 9018
168
c5aa9e3b
LT		 169/* MDIO bus phy name */
170#define XGBE_PHY_NAME "amd_xgbe_phy"
171#define XGBE_PRTAD 0
172
23e4eef7
LT		 173/* Device-tree clock names */
174#define XGBE_DMA_CLOCK "dma_clk"
175#define XGBE_PTP_CLOCK "ptp_clk"
9227dc5e 176#define XGBE_DMA_IRQS "amd,per-channel-interrupt"
23e4eef7
LT		 177
178/* Timestamp support - values based on 50MHz PTP clock
179 * 50MHz => 20 nsec
180 */
181#define XGBE_TSTAMP_SSINC 20
182#define XGBE_TSTAMP_SNSINC 0
183
c5aa9e3b
LT		 184/* Driver PMT macros */
185#define XGMAC_DRIVER_CONTEXT 1
186#define XGMAC_IOCTL_CONTEXT 2
187
f076f453 188#define XGBE_FIFO_MAX 81920
d0a8ba6c
LT		 189#define XGBE_FIFO_SIZE_B(x) (x)
190#define XGBE_FIFO_SIZE_KB(x) (x * 1024)
c5aa9e3b 191
fca2d994 192#define XGBE_TC_MIN_QUANTUM 10
c5aa9e3b
LT		 193
194/* Helper macro for descriptor handling
d0a8ba6c 195 * Always use XGBE_GET_DESC_DATA to access the descriptor data
c5aa9e3b
LT		 196 * since the index is free-running and needs to be and-ed
197 * with the descriptor count value of the ring to index to
198 * the proper descriptor data.
199 */
d0a8ba6c 200#define XGBE_GET_DESC_DATA(_ring, _idx) \
c5aa9e3b
LT		 201 ((_ring)->rdata + \
202 ((_idx) & ((_ring)->rdesc_count - 1)))
203
c5aa9e3b 204/* Default coalescing parameters */
9867e8fb
LT		 205#define XGMAC_INIT_DMA_TX_USECS 50
206#define XGMAC_INIT_DMA_TX_FRAMES 25
c5aa9e3b
LT		 207
208#define XGMAC_MAX_DMA_RIWT 0xff
9867e8fb
LT		 209#define XGMAC_INIT_DMA_RX_USECS 30
210#define XGMAC_INIT_DMA_RX_FRAMES 25
c5aa9e3b
LT		 211
212/* Flow control queue count */
213#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
214
b85e4d89
LT		 215/* Maximum MAC address hash table size (256 bits = 8 bytes) */
216#define XGBE_MAC_HASH_TABLE_SIZE 8
c5aa9e3b 217
5b9dfe29
LT		 218/* Receive Side Scaling */
219#define XGBE_RSS_HASH_KEY_SIZE 40
220#define XGBE_RSS_MAX_TABLE_SIZE 256
221#define XGBE_RSS_LOOKUP_TABLE_TYPE 0
222#define XGBE_RSS_HASH_KEY_TYPE 1
223
c5aa9e3b
LT		 224struct xgbe_prv_data;
225
226struct xgbe_packet_data {
227 unsigned int attributes;
228
229 unsigned int errors;
230
231 unsigned int rdesc_count;
232 unsigned int length;
233
234 unsigned int header_len;
235 unsigned int tcp_header_len;
236 unsigned int tcp_payload_len;
237 unsigned short mss;
238
239 unsigned short vlan_ctag;
23e4eef7
LT		 240
241 u64 rx_tstamp;
5b9dfe29
LT		 242
243 u32 rss_hash;
244 enum pkt_hash_types rss_hash_type;
c5aa9e3b
LT		 245};
246
247/* Common Rx and Tx descriptor mapping */
248struct xgbe_ring_desc {
aa96bd3c
LT		 249 u32 desc0;
250 u32 desc1;
251 u32 desc2;
252 u32 desc3;
c5aa9e3b
LT		 253};
254
08dcc47c
LT		 255/* Page allocation related values */
256struct xgbe_page_alloc {
257 struct page *pages;
258 unsigned int pages_len;
259 unsigned int pages_offset;
260
261 dma_addr_t pages_dma;
262};
263
174fd259
LT		 264/* Ring entry buffer data */
265struct xgbe_buffer_data {
266 struct xgbe_page_alloc pa;
267 struct xgbe_page_alloc pa_unmap;
268
269 dma_addr_t dma;
270 unsigned int dma_len;
271};
272
c5aa9e3b
LT		 273/* Structure used to hold information related to the descriptor
274 * and the packet associated with the descriptor (always use
d0a8ba6c 275 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
c5aa9e3b
LT		 276 */
277struct xgbe_ring_data {
278 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
279 dma_addr_t rdesc_dma; /* DMA address of descriptor */
280
281 struct sk_buff *skb; /* Virtual address of SKB */
282 dma_addr_t skb_dma; /* DMA address of SKB data */
283 unsigned int skb_dma_len; /* Length of SKB DMA area */
284 unsigned int tso_header; /* TSO header indicator */
285
174fd259
LT		 286 struct xgbe_buffer_data rx_hdr; /* Header locations */
287 struct xgbe_buffer_data rx_buf; /* Payload locations */
08dcc47c 288
174fd259 289 unsigned short hdr_len; /* Length of received header */
c5aa9e3b
LT		 290 unsigned short len; /* Length of received Rx packet */
291
292 unsigned int interrupt; /* Interrupt indicator */
293
294 unsigned int mapped_as_page;
23e4eef7
LT		 295
296 /* Incomplete receive save location. If the budget is exhausted
297 * or the last descriptor (last normal descriptor or a following
298 * context descriptor) has not been DMA'd yet the current state
299 * of the receive processing needs to be saved.
300 */
301 unsigned int state_saved;
302 struct {
303 unsigned int incomplete;
304 unsigned int context_next;
305 struct sk_buff *skb;
306 unsigned int len;
307 unsigned int error;
308 } state;
c5aa9e3b
LT		 309};
310
311struct xgbe_ring {
312 /* Ring lock - used just for TX rings at the moment */
313 spinlock_t lock;
314
315 /* Per packet related information */
316 struct xgbe_packet_data packet_data;
317
318 /* Virtual/DMA addresses and count of allocated descriptor memory */
319 struct xgbe_ring_desc *rdesc;
320 dma_addr_t rdesc_dma;
321 unsigned int rdesc_count;
322
323 /* Array of descriptor data corresponding the descriptor memory
d0a8ba6c 324 * (always use the XGBE_GET_DESC_DATA macro to access this data)
c5aa9e3b
LT		 325 */
326 struct xgbe_ring_data *rdata;
327
08dcc47c 328 /* Page allocation for RX buffers */
174fd259
LT		 329 struct xgbe_page_alloc rx_hdr_pa;
330 struct xgbe_page_alloc rx_buf_pa;
08dcc47c 331
c5aa9e3b
LT		 332 /* Ring index values
333 * cur - Tx: index of descriptor to be used for current transfer
334 * Rx: index of descriptor to check for packet availability
335 * dirty - Tx: index of descriptor to check for transfer complete
336 * Rx: count of descriptors in which a packet has been received
337 * (used with skb_realloc_index to refresh the ring)
338 */
339 unsigned int cur;
340 unsigned int dirty;
341
342 /* Coalesce frame count used for interrupt bit setting */
343 unsigned int coalesce_count;
344
345 union {
346 struct {
347 unsigned int queue_stopped;
348 unsigned short cur_mss;
349 unsigned short cur_vlan_ctag;
350 } tx;
351
352 struct {
353 unsigned int realloc_index;
354 unsigned int realloc_threshold;
355 } rx;
356 };
357} ____cacheline_aligned;
358
359/* Structure used to describe the descriptor rings associated with
360 * a DMA channel.
361 */
362struct xgbe_channel {
363 char name[16];
364
365 /* Address of private data area for device */
366 struct xgbe_prv_data *pdata;
367
368 /* Queue index and base address of queue's DMA registers */
369 unsigned int queue_index;
370 void __iomem *dma_regs;
371
9227dc5e
LT		 372 /* Per channel interrupt irq number */
373 int dma_irq;
374
375 /* Netdev related settings */
376 struct napi_struct napi;
377
c5aa9e3b
LT		 378 unsigned int saved_ier;
379
380 unsigned int tx_timer_active;
381 struct hrtimer tx_timer;
382
383 struct xgbe_ring *tx_ring;
384 struct xgbe_ring *rx_ring;
385} ____cacheline_aligned;
386
387enum xgbe_int {
c5aa9e3b
LT		 388 XGMAC_INT_DMA_CH_SR_TI,
389 XGMAC_INT_DMA_CH_SR_TPS,
390 XGMAC_INT_DMA_CH_SR_TBU,
391 XGMAC_INT_DMA_CH_SR_RI,
392 XGMAC_INT_DMA_CH_SR_RBU,
393 XGMAC_INT_DMA_CH_SR_RPS,
9867e8fb 394 XGMAC_INT_DMA_CH_SR_TI_RI,
c5aa9e3b
LT		 395 XGMAC_INT_DMA_CH_SR_FBE,
396 XGMAC_INT_DMA_ALL,
397};
398
399enum xgbe_int_state {
400 XGMAC_INT_STATE_SAVE,
401 XGMAC_INT_STATE_RESTORE,
402};
403
404enum xgbe_mtl_fifo_size {
405 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
406 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
407 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
408 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
409 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
410 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
411 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
412 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
413 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
414 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
415 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
416};
417
418struct xgbe_mmc_stats {
419 /* Tx Stats */
420 u64 txoctetcount_gb;
421 u64 txframecount_gb;
422 u64 txbroadcastframes_g;
423 u64 txmulticastframes_g;
424 u64 tx64octets_gb;
425 u64 tx65to127octets_gb;
426 u64 tx128to255octets_gb;
427 u64 tx256to511octets_gb;
428 u64 tx512to1023octets_gb;
429 u64 tx1024tomaxoctets_gb;
430 u64 txunicastframes_gb;
431 u64 txmulticastframes_gb;
432 u64 txbroadcastframes_gb;
433 u64 txunderflowerror;
434 u64 txoctetcount_g;
435 u64 txframecount_g;
436 u64 txpauseframes;
437 u64 txvlanframes_g;
438
439 /* Rx Stats */
440 u64 rxframecount_gb;
441 u64 rxoctetcount_gb;
442 u64 rxoctetcount_g;
443 u64 rxbroadcastframes_g;
444 u64 rxmulticastframes_g;
445 u64 rxcrcerror;
446 u64 rxrunterror;
447 u64 rxjabbererror;
448 u64 rxundersize_g;
449 u64 rxoversize_g;
450 u64 rx64octets_gb;
451 u64 rx65to127octets_gb;
452 u64 rx128to255octets_gb;
453 u64 rx256to511octets_gb;
454 u64 rx512to1023octets_gb;
455 u64 rx1024tomaxoctets_gb;
456 u64 rxunicastframes_g;
457 u64 rxlengtherror;
458 u64 rxoutofrangetype;
459 u64 rxpauseframes;
460 u64 rxfifooverflow;
461 u64 rxvlanframes_gb;
462 u64 rxwatchdogerror;
463};
464
465struct xgbe_hw_if {
466 int (*tx_complete)(struct xgbe_ring_desc *);
467
468 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
469 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
b85e4d89 470 int (*add_mac_addresses)(struct xgbe_prv_data *);
c5aa9e3b
LT		 471 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
472
473 int (*enable_rx_csum)(struct xgbe_prv_data *);
474 int (*disable_rx_csum)(struct xgbe_prv_data *);
475
476 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
477 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
801c62d9
LT		 478 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
479 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
480 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
c5aa9e3b
LT		 481
482 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
483 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
484 int (*set_gmii_speed)(struct xgbe_prv_data *);
485 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
486 int (*set_xgmii_speed)(struct xgbe_prv_data *);
487
488 void (*enable_tx)(struct xgbe_prv_data *);
489 void (*disable_tx)(struct xgbe_prv_data *);
490 void (*enable_rx)(struct xgbe_prv_data *);
491 void (*disable_rx)(struct xgbe_prv_data *);
492
493 void (*powerup_tx)(struct xgbe_prv_data *);
494 void (*powerdown_tx)(struct xgbe_prv_data *);
495 void (*powerup_rx)(struct xgbe_prv_data *);
496 void (*powerdown_rx)(struct xgbe_prv_data *);
497
498 int (*init)(struct xgbe_prv_data *);
499 int (*exit)(struct xgbe_prv_data *);
500
501 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
502 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
a9d41981 503 void (*dev_xmit)(struct xgbe_channel *);
c5aa9e3b
LT		 504 int (*dev_read)(struct xgbe_channel *);
505 void (*tx_desc_init)(struct xgbe_channel *);
506 void (*rx_desc_init)(struct xgbe_channel *);
507 void (*rx_desc_reset)(struct xgbe_ring_data *);
508 void (*tx_desc_reset)(struct xgbe_ring_data *);
509 int (*is_last_desc)(struct xgbe_ring_desc *);
510 int (*is_context_desc)(struct xgbe_ring_desc *);
511
512 /* For FLOW ctrl */
513 int (*config_tx_flow_control)(struct xgbe_prv_data *);
514 int (*config_rx_flow_control)(struct xgbe_prv_data *);
515
516 /* For RX coalescing */
517 int (*config_rx_coalesce)(struct xgbe_prv_data *);
518 int (*config_tx_coalesce)(struct xgbe_prv_data *);
519 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
520 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
521
522 /* For RX and TX threshold config */
523 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
524 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
525
526 /* For RX and TX Store and Forward Mode config */
527 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
528 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
529
530 /* For TX DMA Operate on Second Frame config */
531 int (*config_osp_mode)(struct xgbe_prv_data *);
532
533 /* For RX and TX PBL config */
534 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
535 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
536 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
537 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
538 int (*config_pblx8)(struct xgbe_prv_data *);
539
540 /* For MMC statistics */
541 void (*rx_mmc_int)(struct xgbe_prv_data *);
542 void (*tx_mmc_int)(struct xgbe_prv_data *);
543 void (*read_mmc_stats)(struct xgbe_prv_data *);
23e4eef7
LT		 544
545 /* For Timestamp config */
546 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
547 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
548 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
549 unsigned int nsec);
550 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
551 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
fca2d994
LT		 552
553 /* For Data Center Bridging config */
554 void (*config_dcb_tc)(struct xgbe_prv_data *);
555 void (*config_dcb_pfc)(struct xgbe_prv_data *);
5b9dfe29
LT		 556
557 /* For Receive Side Scaling */
558 int (*enable_rss)(struct xgbe_prv_data *);
559 int (*disable_rss)(struct xgbe_prv_data *);
c5aa9e3b
LT		 560};
561
562struct xgbe_desc_if {
563 int (*alloc_ring_resources)(struct xgbe_prv_data *);
564 void (*free_ring_resources)(struct xgbe_prv_data *);
565 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
08dcc47c
LT		 566 void (*realloc_rx_buffer)(struct xgbe_channel *);
567 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
c5aa9e3b
LT		 568 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
569 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
570};
571
572/* This structure contains flags that indicate what hardware features
573 * or configurations are present in the device.
574 */
575struct xgbe_hw_features {
a9a4a2d9
LT		 576 /* HW Version */
577 unsigned int version;
578
c5aa9e3b
LT		 579 /* HW Feature Register0 */
580 unsigned int gmii; /* 1000 Mbps support */
581 unsigned int vlhash; /* VLAN Hash Filter */
582 unsigned int sma; /* SMA(MDIO) Interface */
583 unsigned int rwk; /* PMT remote wake-up packet */
584 unsigned int mgk; /* PMT magic packet */
585 unsigned int mmc; /* RMON module */
586 unsigned int aoe; /* ARP Offload */
587 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
588 unsigned int eee; /* Energy Efficient Ethernet */
589 unsigned int tx_coe; /* Tx Checksum Offload */
590 unsigned int rx_coe; /* Rx Checksum Offload */
591 unsigned int addn_mac; /* Additional MAC Addresses */
592 unsigned int ts_src; /* Timestamp Source */
593 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
594
595 /* HW Feature Register1 */
596 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
597 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
598 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
599 unsigned int dcb; /* DCB Feature */
600 unsigned int sph; /* Split Header Feature */
601 unsigned int tso; /* TCP Segmentation Offload */
602 unsigned int dma_debug; /* DMA Debug Registers */
603 unsigned int rss; /* Receive Side Scaling */
fca2d994 604 unsigned int tc_cnt; /* Number of Traffic Classes */
c5aa9e3b
LT		 605 unsigned int hash_table_size; /* Hash Table Size */
606 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
607
608 /* HW Feature Register2 */
609 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
610 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
611 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
612 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
613 unsigned int pps_out_num; /* Number of PPS outputs */
614 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
615};
616
617struct xgbe_prv_data {
618 struct net_device *netdev;
619 struct platform_device *pdev;
620 struct device *dev;
621
622 /* XGMAC/XPCS related mmio registers */
623 void __iomem *xgmac_regs; /* XGMAC CSRs */
624 void __iomem *xpcs_regs; /* XPCS MMD registers */
625
626 /* Overall device lock */
627 spinlock_t lock;
628
629 /* XPCS indirect addressing mutex */
630 struct mutex xpcs_mutex;
631
5b9dfe29
LT		 632 /* RSS addressing mutex */
633 struct mutex rss_mutex;
634
9227dc5e
LT		 635 int dev_irq;
636 unsigned int per_channel_irq;
c5aa9e3b
LT		 637
638 struct xgbe_hw_if hw_if;
639 struct xgbe_desc_if desc_if;
640
cfa50c78
LT		 641 /* AXI DMA settings */
642 unsigned int axdomain;
643 unsigned int arcache;
644 unsigned int awcache;
645
c5aa9e3b
LT		 646 /* Rings for Tx/Rx on a DMA channel */
647 struct xgbe_channel *channel;
648 unsigned int channel_count;
649 unsigned int tx_ring_count;
650 unsigned int tx_desc_count;
651 unsigned int rx_ring_count;
652 unsigned int rx_desc_count;
653
853eb16b
LT		 654 unsigned int tx_q_count;
655 unsigned int rx_q_count;
656
c5aa9e3b
LT		 657 /* Tx/Rx common settings */
658 unsigned int pblx8;
659
660 /* Tx settings */
661 unsigned int tx_sf_mode;
662 unsigned int tx_threshold;
663 unsigned int tx_pbl;
664 unsigned int tx_osp_mode;
665
666 /* Rx settings */
667 unsigned int rx_sf_mode;
668 unsigned int rx_threshold;
669 unsigned int rx_pbl;
670
671 /* Tx coalescing settings */
672 unsigned int tx_usecs;
673 unsigned int tx_frames;
674
675 /* Rx coalescing settings */
676 unsigned int rx_riwt;
677 unsigned int rx_frames;
678
08dcc47c 679 /* Current Rx buffer size */
c5aa9e3b
LT		 680 unsigned int rx_buf_size;
681
682 /* Flow control settings */
683 unsigned int pause_autoneg;
684 unsigned int tx_pause;
685 unsigned int rx_pause;
686
5b9dfe29
LT		 687 /* Receive Side Scaling settings */
688 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
689 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
690 u32 rss_options;
691
c5aa9e3b
LT		 692 /* MDIO settings */
693 struct module *phy_module;
694 char *mii_bus_id;
695 struct mii_bus *mii;
696 int mdio_mmd;
697 struct phy_device *phydev;
698 int default_autoneg;
699 int default_speed;
700
701 /* Current PHY settings */
702 phy_interface_t phy_mode;
703 int phy_link;
704 int phy_speed;
705 unsigned int phy_tx_pause;
706 unsigned int phy_rx_pause;
707
708 /* Netdev related settings */
709 netdev_features_t netdev_features;
710 struct napi_struct napi;
711 struct xgbe_mmc_stats mmc_stats;
712
801c62d9
LT		 713 /* Filtering support */
714 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
715
23e4eef7
LT		 716 /* Device clocks */
717 struct clk *sysclk;
718 struct clk *ptpclk;
719
720 /* Timestamp support */
721 spinlock_t tstamp_lock;
722 struct ptp_clock_info ptp_clock_info;
723 struct ptp_clock *ptp_clock;
724 struct hwtstamp_config tstamp_config;
725 struct cyclecounter tstamp_cc;
726 struct timecounter tstamp_tc;
727 unsigned int tstamp_addend;
728 struct work_struct tx_tstamp_work;
729 struct sk_buff *tx_tstamp_skb;
730 u64 tx_tstamp;
c5aa9e3b 731
fca2d994
LT		 732 /* DCB support */
733 struct ieee_ets *ets;
734 struct ieee_pfc *pfc;
735 unsigned int q2tc_map[XGBE_MAX_QUEUES];
736 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
737
c5aa9e3b
LT		 738 /* Hardware features of the device */
739 struct xgbe_hw_features hw_feat;
740
741 /* Device restart work structure */
742 struct work_struct restart_work;
743
744 /* Keeps track of power mode */
745 unsigned int power_down;
746
747#ifdef CONFIG_DEBUG_FS
748 struct dentry *xgbe_debugfs;
749
750 unsigned int debugfs_xgmac_reg;
751
752 unsigned int debugfs_xpcs_mmd;
753 unsigned int debugfs_xpcs_reg;
754#endif
755};
756
757/* Function prototypes*/
758
759void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
760void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
761struct net_device_ops *xgbe_get_netdev_ops(void);
762struct ethtool_ops *xgbe_get_ethtool_ops(void);
fca2d994
LT		 763#ifdef CONFIG_AMD_XGBE_DCB
764const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
765#endif
c5aa9e3b
LT		 766
767int xgbe_mdio_register(struct xgbe_prv_data *);
768void xgbe_mdio_unregister(struct xgbe_prv_data *);
769void xgbe_dump_phy_registers(struct xgbe_prv_data *);
23e4eef7
LT		 770void xgbe_ptp_register(struct xgbe_prv_data *);
771void xgbe_ptp_unregister(struct xgbe_prv_data *);
c5aa9e3b
LT		 772void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
773 unsigned int);
774void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
775 unsigned int);
776void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
777void xgbe_get_all_hw_features(struct xgbe_prv_data *);
778int xgbe_powerup(struct net_device *, unsigned int);
779int xgbe_powerdown(struct net_device *, unsigned int);
780void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
781void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
782
783#ifdef CONFIG_DEBUG_FS
784void xgbe_debugfs_init(struct xgbe_prv_data *);
785void xgbe_debugfs_exit(struct xgbe_prv_data *);
786#else
787static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
788static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
789#endif /* CONFIG_DEBUG_FS */
790
791/* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
792#if 0
793#define XGMAC_ENABLE_TX_DESC_DUMP
794#define XGMAC_ENABLE_RX_DESC_DUMP
795#endif
796
797/* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
798#if 0
799#define XGMAC_ENABLE_TX_PKT_DUMP
800#define XGMAC_ENABLE_RX_PKT_DUMP
801#endif
802
803/* NOTE: Uncomment for function trace log messages in KERNEL LOG */
804#if 0
805#define YDEBUG
806#define YDEBUG_MDIO
807#endif
808
809/* For debug prints */
810#ifdef YDEBUG
811#define DBGPR(x...) pr_alert(x)
812#define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
813#else
814#define DBGPR(x...) do { } while (0)
815#define DBGPHY_REGS(x...) do { } while (0)
816#endif
817
818#ifdef YDEBUG_MDIO
819#define DBGPR_MDIO(x...) pr_alert(x)
820#else
821#define DBGPR_MDIO(x...) do { } while (0)
822#endif
823
824#endif
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git