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amd-xgbe: Use the u32 data type for descriptors
[thirdparty/kernel/stable.git] / drivers / net / ethernet / amd / xgbe / xgbe.h
CommitLineData
c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#ifndef __XGBE_H__
118#define __XGBE_H__
119
120#include <linux/dma-mapping.h>
121#include <linux/netdevice.h>
122#include <linux/workqueue.h>
123#include <linux/phy.h>
801c62d9
LT		 124#include <linux/if_vlan.h>
125#include <linux/bitops.h>
23e4eef7
LT		 126#include <linux/ptp_clock_kernel.h>
127#include <linux/clocksource.h>
128#include <linux/net_tstamp.h>
fca2d994 129#include <net/dcbnl.h>
c5aa9e3b 130
c5aa9e3b
LT		 131#define XGBE_DRV_NAME "amd-xgbe"
132#define XGBE_DRV_VERSION "1.0.0-a"
133#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
134
135/* Descriptor related defines */
d0a8ba6c
LT		 136#define XGBE_TX_DESC_CNT 512
137#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139#define XGBE_RX_DESC_CNT 512
c5aa9e3b 140
d0a8ba6c 141#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
c5aa9e3b 142
d0a8ba6c
LT		 143#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
144#define XGBE_RX_BUF_ALIGN 64
c5aa9e3b 145
d5c48582 146#define XGBE_MAX_DMA_CHANNELS 16
fca2d994 147#define XGBE_MAX_QUEUES 16
d0a8ba6c
LT		 148
149/* DMA cache settings - Outer sharable, write-back, write-allocate */
cfa50c78
LT		 150#define XGBE_DMA_OS_AXDOMAIN 0x2
151#define XGBE_DMA_OS_ARCACHE 0xb
152#define XGBE_DMA_OS_AWCACHE 0xf
153
154/* DMA cache settings - System, no caches used */
155#define XGBE_DMA_SYS_AXDOMAIN 0x3
156#define XGBE_DMA_SYS_ARCACHE 0x0
157#define XGBE_DMA_SYS_AWCACHE 0x0
d0a8ba6c
LT		 158
159#define XGBE_DMA_INTERRUPT_MASK 0x31c7
c5aa9e3b
LT		 160
161#define XGMAC_MIN_PACKET 60
162#define XGMAC_STD_PACKET_MTU 1500
163#define XGMAC_MAX_STD_PACKET 1518
164#define XGMAC_JUMBO_PACKET_MTU 9000
165#define XGMAC_MAX_JUMBO_PACKET 9018
166
c5aa9e3b
LT		 167/* MDIO bus phy name */
168#define XGBE_PHY_NAME "amd_xgbe_phy"
169#define XGBE_PRTAD 0
170
23e4eef7
LT		 171/* Device-tree clock names */
172#define XGBE_DMA_CLOCK "dma_clk"
173#define XGBE_PTP_CLOCK "ptp_clk"
174
175/* Timestamp support - values based on 50MHz PTP clock
176 * 50MHz => 20 nsec
177 */
178#define XGBE_TSTAMP_SSINC 20
179#define XGBE_TSTAMP_SNSINC 0
180
c5aa9e3b
LT		 181/* Driver PMT macros */
182#define XGMAC_DRIVER_CONTEXT 1
183#define XGMAC_IOCTL_CONTEXT 2
184
f076f453 185#define XGBE_FIFO_MAX 81920
d0a8ba6c
LT		 186#define XGBE_FIFO_SIZE_B(x) (x)
187#define XGBE_FIFO_SIZE_KB(x) (x * 1024)
c5aa9e3b 188
fca2d994 189#define XGBE_TC_MIN_QUANTUM 10
c5aa9e3b
LT		 190
191/* Helper macro for descriptor handling
d0a8ba6c 192 * Always use XGBE_GET_DESC_DATA to access the descriptor data
c5aa9e3b
LT		 193 * since the index is free-running and needs to be and-ed
194 * with the descriptor count value of the ring to index to
195 * the proper descriptor data.
196 */
d0a8ba6c 197#define XGBE_GET_DESC_DATA(_ring, _idx) \
c5aa9e3b
LT		 198 ((_ring)->rdata + \
199 ((_idx) & ((_ring)->rdesc_count - 1)))
200
c5aa9e3b 201/* Default coalescing parameters */
9867e8fb
LT		 202#define XGMAC_INIT_DMA_TX_USECS 50
203#define XGMAC_INIT_DMA_TX_FRAMES 25
c5aa9e3b
LT		 204
205#define XGMAC_MAX_DMA_RIWT 0xff
9867e8fb
LT		 206#define XGMAC_INIT_DMA_RX_USECS 30
207#define XGMAC_INIT_DMA_RX_FRAMES 25
c5aa9e3b
LT		 208
209/* Flow control queue count */
210#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
211
b85e4d89
LT		 212/* Maximum MAC address hash table size (256 bits = 8 bytes) */
213#define XGBE_MAC_HASH_TABLE_SIZE 8
c5aa9e3b
LT		 214
215struct xgbe_prv_data;
216
217struct xgbe_packet_data {
218 unsigned int attributes;
219
220 unsigned int errors;
221
222 unsigned int rdesc_count;
223 unsigned int length;
224
225 unsigned int header_len;
226 unsigned int tcp_header_len;
227 unsigned int tcp_payload_len;
228 unsigned short mss;
229
230 unsigned short vlan_ctag;
23e4eef7
LT		 231
232 u64 rx_tstamp;
c5aa9e3b
LT		 233};
234
235/* Common Rx and Tx descriptor mapping */
236struct xgbe_ring_desc {
aa96bd3c
LT		 237 u32 desc0;
238 u32 desc1;
239 u32 desc2;
240 u32 desc3;
c5aa9e3b
LT		 241};
242
243/* Structure used to hold information related to the descriptor
244 * and the packet associated with the descriptor (always use
d0a8ba6c 245 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
c5aa9e3b
LT		 246 */
247struct xgbe_ring_data {
248 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
249 dma_addr_t rdesc_dma; /* DMA address of descriptor */
250
251 struct sk_buff *skb; /* Virtual address of SKB */
252 dma_addr_t skb_dma; /* DMA address of SKB data */
253 unsigned int skb_dma_len; /* Length of SKB DMA area */
254 unsigned int tso_header; /* TSO header indicator */
255
256 unsigned short len; /* Length of received Rx packet */
257
258 unsigned int interrupt; /* Interrupt indicator */
259
260 unsigned int mapped_as_page;
23e4eef7
LT		 261
262 /* Incomplete receive save location. If the budget is exhausted
263 * or the last descriptor (last normal descriptor or a following
264 * context descriptor) has not been DMA'd yet the current state
265 * of the receive processing needs to be saved.
266 */
267 unsigned int state_saved;
268 struct {
269 unsigned int incomplete;
270 unsigned int context_next;
271 struct sk_buff *skb;
272 unsigned int len;
273 unsigned int error;
274 } state;
c5aa9e3b
LT		 275};
276
277struct xgbe_ring {
278 /* Ring lock - used just for TX rings at the moment */
279 spinlock_t lock;
280
281 /* Per packet related information */
282 struct xgbe_packet_data packet_data;
283
284 /* Virtual/DMA addresses and count of allocated descriptor memory */
285 struct xgbe_ring_desc *rdesc;
286 dma_addr_t rdesc_dma;
287 unsigned int rdesc_count;
288
289 /* Array of descriptor data corresponding the descriptor memory
d0a8ba6c 290 * (always use the XGBE_GET_DESC_DATA macro to access this data)
c5aa9e3b
LT		 291 */
292 struct xgbe_ring_data *rdata;
293
294 /* Ring index values
295 * cur - Tx: index of descriptor to be used for current transfer
296 * Rx: index of descriptor to check for packet availability
297 * dirty - Tx: index of descriptor to check for transfer complete
298 * Rx: count of descriptors in which a packet has been received
299 * (used with skb_realloc_index to refresh the ring)
300 */
301 unsigned int cur;
302 unsigned int dirty;
303
304 /* Coalesce frame count used for interrupt bit setting */
305 unsigned int coalesce_count;
306
307 union {
308 struct {
309 unsigned int queue_stopped;
310 unsigned short cur_mss;
311 unsigned short cur_vlan_ctag;
312 } tx;
313
314 struct {
315 unsigned int realloc_index;
316 unsigned int realloc_threshold;
317 } rx;
318 };
319} ____cacheline_aligned;
320
321/* Structure used to describe the descriptor rings associated with
322 * a DMA channel.
323 */
324struct xgbe_channel {
325 char name[16];
326
327 /* Address of private data area for device */
328 struct xgbe_prv_data *pdata;
329
330 /* Queue index and base address of queue's DMA registers */
331 unsigned int queue_index;
332 void __iomem *dma_regs;
333
334 unsigned int saved_ier;
335
336 unsigned int tx_timer_active;
337 struct hrtimer tx_timer;
338
339 struct xgbe_ring *tx_ring;
340 struct xgbe_ring *rx_ring;
341} ____cacheline_aligned;
342
343enum xgbe_int {
c5aa9e3b
LT		 344 XGMAC_INT_DMA_CH_SR_TI,
345 XGMAC_INT_DMA_CH_SR_TPS,
346 XGMAC_INT_DMA_CH_SR_TBU,
347 XGMAC_INT_DMA_CH_SR_RI,
348 XGMAC_INT_DMA_CH_SR_RBU,
349 XGMAC_INT_DMA_CH_SR_RPS,
9867e8fb 350 XGMAC_INT_DMA_CH_SR_TI_RI,
c5aa9e3b
LT		 351 XGMAC_INT_DMA_CH_SR_FBE,
352 XGMAC_INT_DMA_ALL,
353};
354
355enum xgbe_int_state {
356 XGMAC_INT_STATE_SAVE,
357 XGMAC_INT_STATE_RESTORE,
358};
359
360enum xgbe_mtl_fifo_size {
361 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
362 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
363 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
364 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
365 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
366 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
367 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
368 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
369 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
370 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
371 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
372};
373
374struct xgbe_mmc_stats {
375 /* Tx Stats */
376 u64 txoctetcount_gb;
377 u64 txframecount_gb;
378 u64 txbroadcastframes_g;
379 u64 txmulticastframes_g;
380 u64 tx64octets_gb;
381 u64 tx65to127octets_gb;
382 u64 tx128to255octets_gb;
383 u64 tx256to511octets_gb;
384 u64 tx512to1023octets_gb;
385 u64 tx1024tomaxoctets_gb;
386 u64 txunicastframes_gb;
387 u64 txmulticastframes_gb;
388 u64 txbroadcastframes_gb;
389 u64 txunderflowerror;
390 u64 txoctetcount_g;
391 u64 txframecount_g;
392 u64 txpauseframes;
393 u64 txvlanframes_g;
394
395 /* Rx Stats */
396 u64 rxframecount_gb;
397 u64 rxoctetcount_gb;
398 u64 rxoctetcount_g;
399 u64 rxbroadcastframes_g;
400 u64 rxmulticastframes_g;
401 u64 rxcrcerror;
402 u64 rxrunterror;
403 u64 rxjabbererror;
404 u64 rxundersize_g;
405 u64 rxoversize_g;
406 u64 rx64octets_gb;
407 u64 rx65to127octets_gb;
408 u64 rx128to255octets_gb;
409 u64 rx256to511octets_gb;
410 u64 rx512to1023octets_gb;
411 u64 rx1024tomaxoctets_gb;
412 u64 rxunicastframes_g;
413 u64 rxlengtherror;
414 u64 rxoutofrangetype;
415 u64 rxpauseframes;
416 u64 rxfifooverflow;
417 u64 rxvlanframes_gb;
418 u64 rxwatchdogerror;
419};
420
421struct xgbe_hw_if {
422 int (*tx_complete)(struct xgbe_ring_desc *);
423
424 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
425 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
b85e4d89 426 int (*add_mac_addresses)(struct xgbe_prv_data *);
c5aa9e3b
LT		 427 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
428
429 int (*enable_rx_csum)(struct xgbe_prv_data *);
430 int (*disable_rx_csum)(struct xgbe_prv_data *);
431
432 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
433 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
801c62d9
LT		 434 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
435 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
436 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
c5aa9e3b
LT		 437
438 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
439 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
440 int (*set_gmii_speed)(struct xgbe_prv_data *);
441 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
442 int (*set_xgmii_speed)(struct xgbe_prv_data *);
443
444 void (*enable_tx)(struct xgbe_prv_data *);
445 void (*disable_tx)(struct xgbe_prv_data *);
446 void (*enable_rx)(struct xgbe_prv_data *);
447 void (*disable_rx)(struct xgbe_prv_data *);
448
449 void (*powerup_tx)(struct xgbe_prv_data *);
450 void (*powerdown_tx)(struct xgbe_prv_data *);
451 void (*powerup_rx)(struct xgbe_prv_data *);
452 void (*powerdown_rx)(struct xgbe_prv_data *);
453
454 int (*init)(struct xgbe_prv_data *);
455 int (*exit)(struct xgbe_prv_data *);
456
457 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
458 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
a9d41981 459 void (*dev_xmit)(struct xgbe_channel *);
c5aa9e3b
LT		 460 int (*dev_read)(struct xgbe_channel *);
461 void (*tx_desc_init)(struct xgbe_channel *);
462 void (*rx_desc_init)(struct xgbe_channel *);
463 void (*rx_desc_reset)(struct xgbe_ring_data *);
464 void (*tx_desc_reset)(struct xgbe_ring_data *);
465 int (*is_last_desc)(struct xgbe_ring_desc *);
466 int (*is_context_desc)(struct xgbe_ring_desc *);
467
468 /* For FLOW ctrl */
469 int (*config_tx_flow_control)(struct xgbe_prv_data *);
470 int (*config_rx_flow_control)(struct xgbe_prv_data *);
471
472 /* For RX coalescing */
473 int (*config_rx_coalesce)(struct xgbe_prv_data *);
474 int (*config_tx_coalesce)(struct xgbe_prv_data *);
475 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
476 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
477
478 /* For RX and TX threshold config */
479 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
480 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
481
482 /* For RX and TX Store and Forward Mode config */
483 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
484 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
485
486 /* For TX DMA Operate on Second Frame config */
487 int (*config_osp_mode)(struct xgbe_prv_data *);
488
489 /* For RX and TX PBL config */
490 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
491 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
492 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
493 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
494 int (*config_pblx8)(struct xgbe_prv_data *);
495
496 /* For MMC statistics */
497 void (*rx_mmc_int)(struct xgbe_prv_data *);
498 void (*tx_mmc_int)(struct xgbe_prv_data *);
499 void (*read_mmc_stats)(struct xgbe_prv_data *);
23e4eef7
LT		 500
501 /* For Timestamp config */
502 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
503 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
504 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
505 unsigned int nsec);
506 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
507 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
fca2d994
LT		 508
509 /* For Data Center Bridging config */
510 void (*config_dcb_tc)(struct xgbe_prv_data *);
511 void (*config_dcb_pfc)(struct xgbe_prv_data *);
c5aa9e3b
LT		 512};
513
514struct xgbe_desc_if {
515 int (*alloc_ring_resources)(struct xgbe_prv_data *);
516 void (*free_ring_resources)(struct xgbe_prv_data *);
517 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
518 void (*realloc_skb)(struct xgbe_channel *);
519 void (*unmap_skb)(struct xgbe_prv_data *, struct xgbe_ring_data *);
520 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
521 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
522};
523
524/* This structure contains flags that indicate what hardware features
525 * or configurations are present in the device.
526 */
527struct xgbe_hw_features {
a9a4a2d9
LT		 528 /* HW Version */
529 unsigned int version;
530
c5aa9e3b
LT		 531 /* HW Feature Register0 */
532 unsigned int gmii; /* 1000 Mbps support */
533 unsigned int vlhash; /* VLAN Hash Filter */
534 unsigned int sma; /* SMA(MDIO) Interface */
535 unsigned int rwk; /* PMT remote wake-up packet */
536 unsigned int mgk; /* PMT magic packet */
537 unsigned int mmc; /* RMON module */
538 unsigned int aoe; /* ARP Offload */
539 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
540 unsigned int eee; /* Energy Efficient Ethernet */
541 unsigned int tx_coe; /* Tx Checksum Offload */
542 unsigned int rx_coe; /* Rx Checksum Offload */
543 unsigned int addn_mac; /* Additional MAC Addresses */
544 unsigned int ts_src; /* Timestamp Source */
545 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
546
547 /* HW Feature Register1 */
548 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
549 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
550 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
551 unsigned int dcb; /* DCB Feature */
552 unsigned int sph; /* Split Header Feature */
553 unsigned int tso; /* TCP Segmentation Offload */
554 unsigned int dma_debug; /* DMA Debug Registers */
555 unsigned int rss; /* Receive Side Scaling */
fca2d994 556 unsigned int tc_cnt; /* Number of Traffic Classes */
c5aa9e3b
LT		 557 unsigned int hash_table_size; /* Hash Table Size */
558 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
559
560 /* HW Feature Register2 */
561 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
562 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
563 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
564 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
565 unsigned int pps_out_num; /* Number of PPS outputs */
566 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
567};
568
569struct xgbe_prv_data {
570 struct net_device *netdev;
571 struct platform_device *pdev;
572 struct device *dev;
573
574 /* XGMAC/XPCS related mmio registers */
575 void __iomem *xgmac_regs; /* XGMAC CSRs */
576 void __iomem *xpcs_regs; /* XPCS MMD registers */
577
578 /* Overall device lock */
579 spinlock_t lock;
580
581 /* XPCS indirect addressing mutex */
582 struct mutex xpcs_mutex;
583
584 int irq_number;
585
586 struct xgbe_hw_if hw_if;
587 struct xgbe_desc_if desc_if;
588
cfa50c78
LT		 589 /* AXI DMA settings */
590 unsigned int axdomain;
591 unsigned int arcache;
592 unsigned int awcache;
593
c5aa9e3b
LT		 594 /* Rings for Tx/Rx on a DMA channel */
595 struct xgbe_channel *channel;
596 unsigned int channel_count;
597 unsigned int tx_ring_count;
598 unsigned int tx_desc_count;
599 unsigned int rx_ring_count;
600 unsigned int rx_desc_count;
601
853eb16b
LT		 602 unsigned int tx_q_count;
603 unsigned int rx_q_count;
604
c5aa9e3b
LT		 605 /* Tx/Rx common settings */
606 unsigned int pblx8;
607
608 /* Tx settings */
609 unsigned int tx_sf_mode;
610 unsigned int tx_threshold;
611 unsigned int tx_pbl;
612 unsigned int tx_osp_mode;
613
614 /* Rx settings */
615 unsigned int rx_sf_mode;
616 unsigned int rx_threshold;
617 unsigned int rx_pbl;
618
619 /* Tx coalescing settings */
620 unsigned int tx_usecs;
621 unsigned int tx_frames;
622
623 /* Rx coalescing settings */
624 unsigned int rx_riwt;
625 unsigned int rx_frames;
626
627 /* Current MTU */
628 unsigned int rx_buf_size;
629
630 /* Flow control settings */
631 unsigned int pause_autoneg;
632 unsigned int tx_pause;
633 unsigned int rx_pause;
634
635 /* MDIO settings */
636 struct module *phy_module;
637 char *mii_bus_id;
638 struct mii_bus *mii;
639 int mdio_mmd;
640 struct phy_device *phydev;
641 int default_autoneg;
642 int default_speed;
643
644 /* Current PHY settings */
645 phy_interface_t phy_mode;
646 int phy_link;
647 int phy_speed;
648 unsigned int phy_tx_pause;
649 unsigned int phy_rx_pause;
650
651 /* Netdev related settings */
652 netdev_features_t netdev_features;
653 struct napi_struct napi;
654 struct xgbe_mmc_stats mmc_stats;
655
801c62d9
LT		 656 /* Filtering support */
657 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
658
23e4eef7
LT		 659 /* Device clocks */
660 struct clk *sysclk;
661 struct clk *ptpclk;
662
663 /* Timestamp support */
664 spinlock_t tstamp_lock;
665 struct ptp_clock_info ptp_clock_info;
666 struct ptp_clock *ptp_clock;
667 struct hwtstamp_config tstamp_config;
668 struct cyclecounter tstamp_cc;
669 struct timecounter tstamp_tc;
670 unsigned int tstamp_addend;
671 struct work_struct tx_tstamp_work;
672 struct sk_buff *tx_tstamp_skb;
673 u64 tx_tstamp;
c5aa9e3b 674
fca2d994
LT		 675 /* DCB support */
676 struct ieee_ets *ets;
677 struct ieee_pfc *pfc;
678 unsigned int q2tc_map[XGBE_MAX_QUEUES];
679 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
680
c5aa9e3b
LT		 681 /* Hardware features of the device */
682 struct xgbe_hw_features hw_feat;
683
684 /* Device restart work structure */
685 struct work_struct restart_work;
686
687 /* Keeps track of power mode */
688 unsigned int power_down;
689
690#ifdef CONFIG_DEBUG_FS
691 struct dentry *xgbe_debugfs;
692
693 unsigned int debugfs_xgmac_reg;
694
695 unsigned int debugfs_xpcs_mmd;
696 unsigned int debugfs_xpcs_reg;
697#endif
698};
699
700/* Function prototypes*/
701
702void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
703void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
704struct net_device_ops *xgbe_get_netdev_ops(void);
705struct ethtool_ops *xgbe_get_ethtool_ops(void);
fca2d994
LT		 706#ifdef CONFIG_AMD_XGBE_DCB
707const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
708#endif
c5aa9e3b
LT		 709
710int xgbe_mdio_register(struct xgbe_prv_data *);
711void xgbe_mdio_unregister(struct xgbe_prv_data *);
712void xgbe_dump_phy_registers(struct xgbe_prv_data *);
23e4eef7
LT		 713void xgbe_ptp_register(struct xgbe_prv_data *);
714void xgbe_ptp_unregister(struct xgbe_prv_data *);
c5aa9e3b
LT		 715void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
716 unsigned int);
717void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
718 unsigned int);
719void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
720void xgbe_get_all_hw_features(struct xgbe_prv_data *);
721int xgbe_powerup(struct net_device *, unsigned int);
722int xgbe_powerdown(struct net_device *, unsigned int);
723void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
724void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
725
726#ifdef CONFIG_DEBUG_FS
727void xgbe_debugfs_init(struct xgbe_prv_data *);
728void xgbe_debugfs_exit(struct xgbe_prv_data *);
729#else
730static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
731static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
732#endif /* CONFIG_DEBUG_FS */
733
734/* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
735#if 0
736#define XGMAC_ENABLE_TX_DESC_DUMP
737#define XGMAC_ENABLE_RX_DESC_DUMP
738#endif
739
740/* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
741#if 0
742#define XGMAC_ENABLE_TX_PKT_DUMP
743#define XGMAC_ENABLE_RX_PKT_DUMP
744#endif
745
746/* NOTE: Uncomment for function trace log messages in KERNEL LOG */
747#if 0
748#define YDEBUG
749#define YDEBUG_MDIO
750#endif
751
752/* For debug prints */
753#ifdef YDEBUG
754#define DBGPR(x...) pr_alert(x)
755#define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
756#else
757#define DBGPR(x...) do { } while (0)
758#define DBGPHY_REGS(x...) do { } while (0)
759#endif
760
761#ifdef YDEBUG_MDIO
762#define DBGPR_MDIO(x...) pr_alert(x)
763#else
764#define DBGPR_MDIO(x...) do { } while (0)
765#endif
766
767#endif
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git