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amd-xgbe: Update/fix 2.5GbE support
[thirdparty/kernel/stable.git] / drivers / net / ethernet / amd / xgbe / xgbe.h
CommitLineData
c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#ifndef __XGBE_H__
118#define __XGBE_H__
119
120#include <linux/dma-mapping.h>
121#include <linux/netdevice.h>
122#include <linux/workqueue.h>
123#include <linux/phy.h>
801c62d9
LT		 124#include <linux/if_vlan.h>
125#include <linux/bitops.h>
23e4eef7
LT		 126#include <linux/ptp_clock_kernel.h>
127#include <linux/clocksource.h>
128#include <linux/net_tstamp.h>
c5aa9e3b
LT		 129
130
131#define XGBE_DRV_NAME "amd-xgbe"
132#define XGBE_DRV_VERSION "1.0.0-a"
133#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
134
135/* Descriptor related defines */
d0a8ba6c
LT		 136#define XGBE_TX_DESC_CNT 512
137#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139#define XGBE_RX_DESC_CNT 512
c5aa9e3b 140
d0a8ba6c 141#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
c5aa9e3b 142
d0a8ba6c
LT		 143#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
144#define XGBE_RX_BUF_ALIGN 64
c5aa9e3b 145
d5c48582 146#define XGBE_MAX_DMA_CHANNELS 16
d0a8ba6c
LT		 147
148/* DMA cache settings - Outer sharable, write-back, write-allocate */
cfa50c78
LT		 149#define XGBE_DMA_OS_AXDOMAIN 0x2
150#define XGBE_DMA_OS_ARCACHE 0xb
151#define XGBE_DMA_OS_AWCACHE 0xf
152
153/* DMA cache settings - System, no caches used */
154#define XGBE_DMA_SYS_AXDOMAIN 0x3
155#define XGBE_DMA_SYS_ARCACHE 0x0
156#define XGBE_DMA_SYS_AWCACHE 0x0
d0a8ba6c
LT		 157
158#define XGBE_DMA_INTERRUPT_MASK 0x31c7
c5aa9e3b
LT		 159
160#define XGMAC_MIN_PACKET 60
161#define XGMAC_STD_PACKET_MTU 1500
162#define XGMAC_MAX_STD_PACKET 1518
163#define XGMAC_JUMBO_PACKET_MTU 9000
164#define XGMAC_MAX_JUMBO_PACKET 9018
165
c5aa9e3b
LT		 166/* MDIO bus phy name */
167#define XGBE_PHY_NAME "amd_xgbe_phy"
168#define XGBE_PRTAD 0
169
23e4eef7
LT		 170/* Device-tree clock names */
171#define XGBE_DMA_CLOCK "dma_clk"
172#define XGBE_PTP_CLOCK "ptp_clk"
173
174/* Timestamp support - values based on 50MHz PTP clock
175 * 50MHz => 20 nsec
176 */
177#define XGBE_TSTAMP_SSINC 20
178#define XGBE_TSTAMP_SNSINC 0
179
c5aa9e3b
LT		 180/* Driver PMT macros */
181#define XGMAC_DRIVER_CONTEXT 1
182#define XGMAC_IOCTL_CONTEXT 2
183
d0a8ba6c
LT		 184#define XGBE_FIFO_SIZE_B(x) (x)
185#define XGBE_FIFO_SIZE_KB(x) (x * 1024)
c5aa9e3b
LT		 186
187#define XGBE_TC_CNT 2
188
189/* Helper macro for descriptor handling
d0a8ba6c 190 * Always use XGBE_GET_DESC_DATA to access the descriptor data
c5aa9e3b
LT		 191 * since the index is free-running and needs to be and-ed
192 * with the descriptor count value of the ring to index to
193 * the proper descriptor data.
194 */
d0a8ba6c 195#define XGBE_GET_DESC_DATA(_ring, _idx) \
c5aa9e3b
LT		 196 ((_ring)->rdata + \
197 ((_idx) & ((_ring)->rdesc_count - 1)))
198
199
200/* Default coalescing parameters */
9867e8fb
LT		 201#define XGMAC_INIT_DMA_TX_USECS 50
202#define XGMAC_INIT_DMA_TX_FRAMES 25
c5aa9e3b
LT		 203
204#define XGMAC_MAX_DMA_RIWT 0xff
9867e8fb
LT		 205#define XGMAC_INIT_DMA_RX_USECS 30
206#define XGMAC_INIT_DMA_RX_FRAMES 25
c5aa9e3b
LT		 207
208/* Flow control queue count */
209#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
210
b85e4d89
LT		 211/* Maximum MAC address hash table size (256 bits = 8 bytes) */
212#define XGBE_MAC_HASH_TABLE_SIZE 8
c5aa9e3b
LT		 213
214struct xgbe_prv_data;
215
216struct xgbe_packet_data {
217 unsigned int attributes;
218
219 unsigned int errors;
220
221 unsigned int rdesc_count;
222 unsigned int length;
223
224 unsigned int header_len;
225 unsigned int tcp_header_len;
226 unsigned int tcp_payload_len;
227 unsigned short mss;
228
229 unsigned short vlan_ctag;
23e4eef7
LT		 230
231 u64 rx_tstamp;
c5aa9e3b
LT		 232};
233
234/* Common Rx and Tx descriptor mapping */
235struct xgbe_ring_desc {
236 unsigned int desc0;
237 unsigned int desc1;
238 unsigned int desc2;
239 unsigned int desc3;
240};
241
242/* Structure used to hold information related to the descriptor
243 * and the packet associated with the descriptor (always use
d0a8ba6c 244 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
c5aa9e3b
LT		 245 */
246struct xgbe_ring_data {
247 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
248 dma_addr_t rdesc_dma; /* DMA address of descriptor */
249
250 struct sk_buff *skb; /* Virtual address of SKB */
251 dma_addr_t skb_dma; /* DMA address of SKB data */
252 unsigned int skb_dma_len; /* Length of SKB DMA area */
253 unsigned int tso_header; /* TSO header indicator */
254
255 unsigned short len; /* Length of received Rx packet */
256
257 unsigned int interrupt; /* Interrupt indicator */
258
259 unsigned int mapped_as_page;
23e4eef7
LT		 260
261 /* Incomplete receive save location. If the budget is exhausted
262 * or the last descriptor (last normal descriptor or a following
263 * context descriptor) has not been DMA'd yet the current state
264 * of the receive processing needs to be saved.
265 */
266 unsigned int state_saved;
267 struct {
268 unsigned int incomplete;
269 unsigned int context_next;
270 struct sk_buff *skb;
271 unsigned int len;
272 unsigned int error;
273 } state;
c5aa9e3b
LT		 274};
275
276struct xgbe_ring {
277 /* Ring lock - used just for TX rings at the moment */
278 spinlock_t lock;
279
280 /* Per packet related information */
281 struct xgbe_packet_data packet_data;
282
283 /* Virtual/DMA addresses and count of allocated descriptor memory */
284 struct xgbe_ring_desc *rdesc;
285 dma_addr_t rdesc_dma;
286 unsigned int rdesc_count;
287
288 /* Array of descriptor data corresponding the descriptor memory
d0a8ba6c 289 * (always use the XGBE_GET_DESC_DATA macro to access this data)
c5aa9e3b
LT		 290 */
291 struct xgbe_ring_data *rdata;
292
293 /* Ring index values
294 * cur - Tx: index of descriptor to be used for current transfer
295 * Rx: index of descriptor to check for packet availability
296 * dirty - Tx: index of descriptor to check for transfer complete
297 * Rx: count of descriptors in which a packet has been received
298 * (used with skb_realloc_index to refresh the ring)
299 */
300 unsigned int cur;
301 unsigned int dirty;
302
303 /* Coalesce frame count used for interrupt bit setting */
304 unsigned int coalesce_count;
305
306 union {
307 struct {
308 unsigned int queue_stopped;
309 unsigned short cur_mss;
310 unsigned short cur_vlan_ctag;
311 } tx;
312
313 struct {
314 unsigned int realloc_index;
315 unsigned int realloc_threshold;
316 } rx;
317 };
318} ____cacheline_aligned;
319
320/* Structure used to describe the descriptor rings associated with
321 * a DMA channel.
322 */
323struct xgbe_channel {
324 char name[16];
325
326 /* Address of private data area for device */
327 struct xgbe_prv_data *pdata;
328
329 /* Queue index and base address of queue's DMA registers */
330 unsigned int queue_index;
331 void __iomem *dma_regs;
332
333 unsigned int saved_ier;
334
335 unsigned int tx_timer_active;
336 struct hrtimer tx_timer;
337
338 struct xgbe_ring *tx_ring;
339 struct xgbe_ring *rx_ring;
340} ____cacheline_aligned;
341
342enum xgbe_int {
c5aa9e3b
LT		 343 XGMAC_INT_DMA_CH_SR_TI,
344 XGMAC_INT_DMA_CH_SR_TPS,
345 XGMAC_INT_DMA_CH_SR_TBU,
346 XGMAC_INT_DMA_CH_SR_RI,
347 XGMAC_INT_DMA_CH_SR_RBU,
348 XGMAC_INT_DMA_CH_SR_RPS,
9867e8fb 349 XGMAC_INT_DMA_CH_SR_TI_RI,
c5aa9e3b
LT		 350 XGMAC_INT_DMA_CH_SR_FBE,
351 XGMAC_INT_DMA_ALL,
352};
353
354enum xgbe_int_state {
355 XGMAC_INT_STATE_SAVE,
356 XGMAC_INT_STATE_RESTORE,
357};
358
359enum xgbe_mtl_fifo_size {
360 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
361 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
362 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
363 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
364 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
365 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
366 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
367 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
368 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
369 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
370 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
371};
372
373struct xgbe_mmc_stats {
374 /* Tx Stats */
375 u64 txoctetcount_gb;
376 u64 txframecount_gb;
377 u64 txbroadcastframes_g;
378 u64 txmulticastframes_g;
379 u64 tx64octets_gb;
380 u64 tx65to127octets_gb;
381 u64 tx128to255octets_gb;
382 u64 tx256to511octets_gb;
383 u64 tx512to1023octets_gb;
384 u64 tx1024tomaxoctets_gb;
385 u64 txunicastframes_gb;
386 u64 txmulticastframes_gb;
387 u64 txbroadcastframes_gb;
388 u64 txunderflowerror;
389 u64 txoctetcount_g;
390 u64 txframecount_g;
391 u64 txpauseframes;
392 u64 txvlanframes_g;
393
394 /* Rx Stats */
395 u64 rxframecount_gb;
396 u64 rxoctetcount_gb;
397 u64 rxoctetcount_g;
398 u64 rxbroadcastframes_g;
399 u64 rxmulticastframes_g;
400 u64 rxcrcerror;
401 u64 rxrunterror;
402 u64 rxjabbererror;
403 u64 rxundersize_g;
404 u64 rxoversize_g;
405 u64 rx64octets_gb;
406 u64 rx65to127octets_gb;
407 u64 rx128to255octets_gb;
408 u64 rx256to511octets_gb;
409 u64 rx512to1023octets_gb;
410 u64 rx1024tomaxoctets_gb;
411 u64 rxunicastframes_g;
412 u64 rxlengtherror;
413 u64 rxoutofrangetype;
414 u64 rxpauseframes;
415 u64 rxfifooverflow;
416 u64 rxvlanframes_gb;
417 u64 rxwatchdogerror;
418};
419
420struct xgbe_hw_if {
421 int (*tx_complete)(struct xgbe_ring_desc *);
422
423 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
424 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
b85e4d89 425 int (*add_mac_addresses)(struct xgbe_prv_data *);
c5aa9e3b
LT		 426 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
427
428 int (*enable_rx_csum)(struct xgbe_prv_data *);
429 int (*disable_rx_csum)(struct xgbe_prv_data *);
430
431 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
432 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
801c62d9
LT		 433 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
434 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
435 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
c5aa9e3b
LT		 436
437 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
438 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
439 int (*set_gmii_speed)(struct xgbe_prv_data *);
440 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
441 int (*set_xgmii_speed)(struct xgbe_prv_data *);
442
443 void (*enable_tx)(struct xgbe_prv_data *);
444 void (*disable_tx)(struct xgbe_prv_data *);
445 void (*enable_rx)(struct xgbe_prv_data *);
446 void (*disable_rx)(struct xgbe_prv_data *);
447
448 void (*powerup_tx)(struct xgbe_prv_data *);
449 void (*powerdown_tx)(struct xgbe_prv_data *);
450 void (*powerup_rx)(struct xgbe_prv_data *);
451 void (*powerdown_rx)(struct xgbe_prv_data *);
452
453 int (*init)(struct xgbe_prv_data *);
454 int (*exit)(struct xgbe_prv_data *);
455
456 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
457 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
458 void (*pre_xmit)(struct xgbe_channel *);
459 int (*dev_read)(struct xgbe_channel *);
460 void (*tx_desc_init)(struct xgbe_channel *);
461 void (*rx_desc_init)(struct xgbe_channel *);
462 void (*rx_desc_reset)(struct xgbe_ring_data *);
463 void (*tx_desc_reset)(struct xgbe_ring_data *);
464 int (*is_last_desc)(struct xgbe_ring_desc *);
465 int (*is_context_desc)(struct xgbe_ring_desc *);
466
467 /* For FLOW ctrl */
468 int (*config_tx_flow_control)(struct xgbe_prv_data *);
469 int (*config_rx_flow_control)(struct xgbe_prv_data *);
470
471 /* For RX coalescing */
472 int (*config_rx_coalesce)(struct xgbe_prv_data *);
473 int (*config_tx_coalesce)(struct xgbe_prv_data *);
474 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
475 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
476
477 /* For RX and TX threshold config */
478 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
479 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
480
481 /* For RX and TX Store and Forward Mode config */
482 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
483 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
484
485 /* For TX DMA Operate on Second Frame config */
486 int (*config_osp_mode)(struct xgbe_prv_data *);
487
488 /* For RX and TX PBL config */
489 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
490 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
491 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
492 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
493 int (*config_pblx8)(struct xgbe_prv_data *);
494
495 /* For MMC statistics */
496 void (*rx_mmc_int)(struct xgbe_prv_data *);
497 void (*tx_mmc_int)(struct xgbe_prv_data *);
498 void (*read_mmc_stats)(struct xgbe_prv_data *);
23e4eef7
LT		 499
500 /* For Timestamp config */
501 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
502 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
503 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
504 unsigned int nsec);
505 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
506 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
c5aa9e3b
LT		 507};
508
509struct xgbe_desc_if {
510 int (*alloc_ring_resources)(struct xgbe_prv_data *);
511 void (*free_ring_resources)(struct xgbe_prv_data *);
512 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
513 void (*realloc_skb)(struct xgbe_channel *);
514 void (*unmap_skb)(struct xgbe_prv_data *, struct xgbe_ring_data *);
515 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
516 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
517};
518
519/* This structure contains flags that indicate what hardware features
520 * or configurations are present in the device.
521 */
522struct xgbe_hw_features {
523 /* HW Feature Register0 */
524 unsigned int gmii; /* 1000 Mbps support */
525 unsigned int vlhash; /* VLAN Hash Filter */
526 unsigned int sma; /* SMA(MDIO) Interface */
527 unsigned int rwk; /* PMT remote wake-up packet */
528 unsigned int mgk; /* PMT magic packet */
529 unsigned int mmc; /* RMON module */
530 unsigned int aoe; /* ARP Offload */
531 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
532 unsigned int eee; /* Energy Efficient Ethernet */
533 unsigned int tx_coe; /* Tx Checksum Offload */
534 unsigned int rx_coe; /* Rx Checksum Offload */
535 unsigned int addn_mac; /* Additional MAC Addresses */
536 unsigned int ts_src; /* Timestamp Source */
537 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
538
539 /* HW Feature Register1 */
540 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
541 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
542 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
543 unsigned int dcb; /* DCB Feature */
544 unsigned int sph; /* Split Header Feature */
545 unsigned int tso; /* TCP Segmentation Offload */
546 unsigned int dma_debug; /* DMA Debug Registers */
547 unsigned int rss; /* Receive Side Scaling */
548 unsigned int hash_table_size; /* Hash Table Size */
549 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
550
551 /* HW Feature Register2 */
552 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
553 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
554 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
555 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
556 unsigned int pps_out_num; /* Number of PPS outputs */
557 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
558};
559
560struct xgbe_prv_data {
561 struct net_device *netdev;
562 struct platform_device *pdev;
563 struct device *dev;
564
565 /* XGMAC/XPCS related mmio registers */
566 void __iomem *xgmac_regs; /* XGMAC CSRs */
567 void __iomem *xpcs_regs; /* XPCS MMD registers */
568
569 /* Overall device lock */
570 spinlock_t lock;
571
572 /* XPCS indirect addressing mutex */
573 struct mutex xpcs_mutex;
574
575 int irq_number;
576
577 struct xgbe_hw_if hw_if;
578 struct xgbe_desc_if desc_if;
579
cfa50c78
LT		 580 /* AXI DMA settings */
581 unsigned int axdomain;
582 unsigned int arcache;
583 unsigned int awcache;
584
c5aa9e3b
LT		 585 /* Rings for Tx/Rx on a DMA channel */
586 struct xgbe_channel *channel;
587 unsigned int channel_count;
588 unsigned int tx_ring_count;
589 unsigned int tx_desc_count;
590 unsigned int rx_ring_count;
591 unsigned int rx_desc_count;
592
593 /* Tx/Rx common settings */
594 unsigned int pblx8;
595
596 /* Tx settings */
597 unsigned int tx_sf_mode;
598 unsigned int tx_threshold;
599 unsigned int tx_pbl;
600 unsigned int tx_osp_mode;
601
602 /* Rx settings */
603 unsigned int rx_sf_mode;
604 unsigned int rx_threshold;
605 unsigned int rx_pbl;
606
607 /* Tx coalescing settings */
608 unsigned int tx_usecs;
609 unsigned int tx_frames;
610
611 /* Rx coalescing settings */
612 unsigned int rx_riwt;
613 unsigned int rx_frames;
614
615 /* Current MTU */
616 unsigned int rx_buf_size;
617
618 /* Flow control settings */
619 unsigned int pause_autoneg;
620 unsigned int tx_pause;
621 unsigned int rx_pause;
622
623 /* MDIO settings */
624 struct module *phy_module;
625 char *mii_bus_id;
626 struct mii_bus *mii;
627 int mdio_mmd;
628 struct phy_device *phydev;
629 int default_autoneg;
630 int default_speed;
631
632 /* Current PHY settings */
633 phy_interface_t phy_mode;
634 int phy_link;
635 int phy_speed;
636 unsigned int phy_tx_pause;
637 unsigned int phy_rx_pause;
638
639 /* Netdev related settings */
640 netdev_features_t netdev_features;
641 struct napi_struct napi;
642 struct xgbe_mmc_stats mmc_stats;
643
801c62d9
LT		 644 /* Filtering support */
645 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
646
23e4eef7
LT		 647 /* Device clocks */
648 struct clk *sysclk;
649 struct clk *ptpclk;
650
651 /* Timestamp support */
652 spinlock_t tstamp_lock;
653 struct ptp_clock_info ptp_clock_info;
654 struct ptp_clock *ptp_clock;
655 struct hwtstamp_config tstamp_config;
656 struct cyclecounter tstamp_cc;
657 struct timecounter tstamp_tc;
658 unsigned int tstamp_addend;
659 struct work_struct tx_tstamp_work;
660 struct sk_buff *tx_tstamp_skb;
661 u64 tx_tstamp;
c5aa9e3b
LT		 662
663 /* Hardware features of the device */
664 struct xgbe_hw_features hw_feat;
665
666 /* Device restart work structure */
667 struct work_struct restart_work;
668
669 /* Keeps track of power mode */
670 unsigned int power_down;
671
672#ifdef CONFIG_DEBUG_FS
673 struct dentry *xgbe_debugfs;
674
675 unsigned int debugfs_xgmac_reg;
676
677 unsigned int debugfs_xpcs_mmd;
678 unsigned int debugfs_xpcs_reg;
679#endif
680};
681
682/* Function prototypes*/
683
684void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
685void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
686struct net_device_ops *xgbe_get_netdev_ops(void);
687struct ethtool_ops *xgbe_get_ethtool_ops(void);
688
689int xgbe_mdio_register(struct xgbe_prv_data *);
690void xgbe_mdio_unregister(struct xgbe_prv_data *);
691void xgbe_dump_phy_registers(struct xgbe_prv_data *);
23e4eef7
LT		 692void xgbe_ptp_register(struct xgbe_prv_data *);
693void xgbe_ptp_unregister(struct xgbe_prv_data *);
c5aa9e3b
LT		 694void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
695 unsigned int);
696void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
697 unsigned int);
698void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
699void xgbe_get_all_hw_features(struct xgbe_prv_data *);
700int xgbe_powerup(struct net_device *, unsigned int);
701int xgbe_powerdown(struct net_device *, unsigned int);
702void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
703void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
704
705#ifdef CONFIG_DEBUG_FS
706void xgbe_debugfs_init(struct xgbe_prv_data *);
707void xgbe_debugfs_exit(struct xgbe_prv_data *);
708#else
709static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
710static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
711#endif /* CONFIG_DEBUG_FS */
712
713/* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
714#if 0
715#define XGMAC_ENABLE_TX_DESC_DUMP
716#define XGMAC_ENABLE_RX_DESC_DUMP
717#endif
718
719/* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
720#if 0
721#define XGMAC_ENABLE_TX_PKT_DUMP
722#define XGMAC_ENABLE_RX_PKT_DUMP
723#endif
724
725/* NOTE: Uncomment for function trace log messages in KERNEL LOG */
726#if 0
727#define YDEBUG
728#define YDEBUG_MDIO
729#endif
730
731/* For debug prints */
732#ifdef YDEBUG
733#define DBGPR(x...) pr_alert(x)
734#define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
735#else
736#define DBGPR(x...) do { } while (0)
737#define DBGPHY_REGS(x...) do { } while (0)
738#endif
739
740#ifdef YDEBUG_MDIO
741#define DBGPR_MDIO(x...) pr_alert(x)
742#else
743#define DBGPR_MDIO(x...) do { } while (0)
744#endif
745
746#endif
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git