[thirdparty/kernel/stable.git] / drivers / net / ethernet / arc / emac_rockchip.c

// SPDX-License-Identifier: GPL-2.0-or-later
/**
 * emac-rockchip.c - Rockchip EMAC specific glue layer
 *
 * Copyright (C) 2014 Romain Perier <romain.perier@gmail.com>
 */

#include <linux/etherdevice.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_net.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>

#include "emac.h"

#define DRV_NAME        "rockchip_emac"
#define DRV_VERSION     "1.1"

struct emac_rockchip_soc_data {
	unsigned int grf_offset;
	unsigned int grf_mode_offset;
	unsigned int grf_speed_offset;
	bool need_div_macclk;
};

struct rockchip_priv_data {
	struct arc_emac_priv emac;
	struct regmap *grf;
	const struct emac_rockchip_soc_data *soc_data;
	struct regulator *regulator;
	struct clk *refclk;
	struct clk *macclk;
};

static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
{
	struct rockchip_priv_data *emac = priv;
	u32 speed_offset = emac->soc_data->grf_speed_offset;
	u32 data;
	int err = 0;

	switch (speed) {
	case 10:
		data = (1 << (speed_offset + 16)) | (0 << speed_offset);
		break;
	case 100:
		data = (1 << (speed_offset + 16)) | (1 << speed_offset);
		break;
	default:
		pr_err("speed %u not supported\n", speed);
		return;
	}

	err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
	if (err)
		pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
}

static const struct emac_rockchip_soc_data emac_rk3036_emac_data = {
	.grf_offset = 0x140,   .grf_mode_offset = 8,
	.grf_speed_offset = 9, .need_div_macclk = 1,
};

static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
	.grf_offset = 0x154,   .grf_mode_offset = 0,
	.grf_speed_offset = 1, .need_div_macclk = 0,
};

static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
	.grf_offset = 0x0a4,   .grf_mode_offset = 0,
	.grf_speed_offset = 1, .need_div_macclk = 0,
};

static const struct of_device_id emac_rockchip_dt_ids[] = {
	{
		.compatible = "rockchip,rk3036-emac",
		.data = &emac_rk3036_emac_data,
	},
	{
		.compatible = "rockchip,rk3066-emac",
		.data = &emac_rk3066_emac_data,
	},
	{
		.compatible = "rockchip,rk3188-emac",
		.data = &emac_rk3188_emac_data,
	},
	{ /* Sentinel */ }
};

MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);

static int emac_rockchip_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct net_device *ndev;
	struct rockchip_priv_data *priv;
	const struct of_device_id *match;
	u32 data;
	int err, interface;

	if (!pdev->dev.of_node)
		return -ENODEV;

	ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
	if (!ndev)
		return -ENOMEM;
	platform_set_drvdata(pdev, ndev);
	SET_NETDEV_DEV(ndev, dev);

	priv = netdev_priv(ndev);
	priv->emac.drv_name = DRV_NAME;
	priv->emac.drv_version = DRV_VERSION;
	priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;

	interface = of_get_phy_mode(dev->of_node);

	/* RK3036/RK3066/RK3188 SoCs only support RMII */
	if (interface != PHY_INTERFACE_MODE_RMII) {
		dev_err(dev, "unsupported phy interface mode %d\n", interface);
		err = -ENOTSUPP;
		goto out_netdev;
	}

	priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
						    "rockchip,grf");
	if (IS_ERR(priv->grf)) {
		dev_err(dev, "failed to retrieve global register file (%ld)\n",
			PTR_ERR(priv->grf));
		err = PTR_ERR(priv->grf);
		goto out_netdev;
	}

	match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
	priv->soc_data = match->data;

	priv->emac.clk = devm_clk_get(dev, "hclk");
	if (IS_ERR(priv->emac.clk)) {
		dev_err(dev, "failed to retrieve host clock (%ld)\n",
			PTR_ERR(priv->emac.clk));
		err = PTR_ERR(priv->emac.clk);
		goto out_netdev;
	}

	priv->refclk = devm_clk_get(dev, "macref");
	if (IS_ERR(priv->refclk)) {
		dev_err(dev, "failed to retrieve reference clock (%ld)\n",
			PTR_ERR(priv->refclk));
		err = PTR_ERR(priv->refclk);
		goto out_netdev;
	}

	err = clk_prepare_enable(priv->refclk);
	if (err) {
		dev_err(dev, "failed to enable reference clock (%d)\n", err);
		goto out_netdev;
	}

	/* Optional regulator for PHY */
	priv->regulator = devm_regulator_get_optional(dev, "phy");
	if (IS_ERR(priv->regulator)) {
		if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
			err = -EPROBE_DEFER;
			goto out_clk_disable;
		}
		dev_err(dev, "no regulator found\n");
		priv->regulator = NULL;
	}

	if (priv->regulator) {
		err = regulator_enable(priv->regulator);
		if (err) {
			dev_err(dev, "failed to enable phy-supply (%d)\n", err);
			goto out_clk_disable;
		}
	}

	/* Set speed 100M */
	data = (1 << (priv->soc_data->grf_speed_offset + 16)) |
	       (1 << priv->soc_data->grf_speed_offset);
	/* Set RMII mode */
	data |= (1 << (priv->soc_data->grf_mode_offset + 16)) |
		(0 << priv->soc_data->grf_mode_offset);

	err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
	if (err) {
		dev_err(dev, "unable to apply initial settings to grf (%d)\n",
			err);
		goto out_regulator_disable;
	}

	/* RMII interface needs always a rate of 50MHz */
	err = clk_set_rate(priv->refclk, 50000000);
	if (err) {
		dev_err(dev,
			"failed to change reference clock rate (%d)\n", err);
		goto out_regulator_disable;
	}

	if (priv->soc_data->need_div_macclk) {
		priv->macclk = devm_clk_get(dev, "macclk");
		if (IS_ERR(priv->macclk)) {
			dev_err(dev, "failed to retrieve mac clock (%ld)\n",
				PTR_ERR(priv->macclk));
			err = PTR_ERR(priv->macclk);
			goto out_regulator_disable;
		}

		err = clk_prepare_enable(priv->macclk);
		if (err) {
			dev_err(dev, "failed to enable mac clock (%d)\n", err);
			goto out_regulator_disable;
		}

		/* RMII TX/RX needs always a rate of 25MHz */
		err = clk_set_rate(priv->macclk, 25000000);
		if (err) {
			dev_err(dev,
				"failed to change mac clock rate (%d)\n", err);
			goto out_clk_disable_macclk;
		}
	}

	err = arc_emac_probe(ndev, interface);
	if (err) {
		dev_err(dev, "failed to probe arc emac (%d)\n", err);
		goto out_clk_disable_macclk;
	}

	return 0;

out_clk_disable_macclk:
	if (priv->soc_data->need_div_macclk)
		clk_disable_unprepare(priv->macclk);
out_regulator_disable:
	if (priv->regulator)
		regulator_disable(priv->regulator);
out_clk_disable:
	clk_disable_unprepare(priv->refclk);
out_netdev:
	free_netdev(ndev);
	return err;
}

static int emac_rockchip_remove(struct platform_device *pdev)
{
	struct net_device *ndev = platform_get_drvdata(pdev);
	struct rockchip_priv_data *priv = netdev_priv(ndev);
	int err;

	err = arc_emac_remove(ndev);

	clk_disable_unprepare(priv->refclk);

	if (priv->regulator)
		regulator_disable(priv->regulator);

	free_netdev(ndev);
	return err;
}

static struct platform_driver emac_rockchip_driver = {
	.probe = emac_rockchip_probe,
	.remove = emac_rockchip_remove,
	.driver = {
		.name = DRV_NAME,
		.of_match_table  = emac_rockchip_dt_ids,
	},
};

module_platform_driver(emac_rockchip_driver);

MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
MODULE_DESCRIPTION("Rockchip EMAC platform driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
6eacf311 RP	2	/**
	3	* emac-rockchip.c - Rockchip EMAC specific glue layer
	4	*
	5	* Copyright (C) 2014 Romain Perier <romain.perier@gmail.com>
6eacf311 RP	6	*/
	7
	8	#include <linux/etherdevice.h>
	9	#include <linux/mfd/syscon.h>
	10	#include <linux/module.h>
	11	#include <linux/of_net.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/regmap.h>
	14	#include <linux/regulator/consumer.h>
	15
	16	#include "emac.h"
	17
	18	#define DRV_NAME "rockchip_emac"
f4c9d3ee	19	#define DRV_VERSION "1.1"
6eacf311 RP	20
6eacf311 RP	21	struct emac_rockchip_soc_data {
f4c9d3ee XZ	22	unsigned int grf_offset;
	23	unsigned int grf_mode_offset;
	24	unsigned int grf_speed_offset;
	25	bool need_div_macclk;
6eacf311 RP	26	};
	27
	28	struct rockchip_priv_data {
	29	struct arc_emac_priv emac;
	30	struct regmap *grf;
	31	const struct emac_rockchip_soc_data *soc_data;
	32	struct regulator *regulator;
	33	struct clk *refclk;
f4c9d3ee	34	struct clk *macclk;
6eacf311 RP	35	};
	36
	37	static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
	38	{
	39	struct rockchip_priv_data *emac = priv;
f4c9d3ee	40	u32 speed_offset = emac->soc_data->grf_speed_offset;
6eacf311 RP	41	u32 data;
	42	int err = 0;
	43
663713eb	44	switch (speed) {
6eacf311	45	case 10:
f4c9d3ee	46	data = (1 << (speed_offset + 16)) \| (0 << speed_offset);
6eacf311 RP	47	break;
6eacf311 RP	48	case 100:
f4c9d3ee	49	data = (1 << (speed_offset + 16)) \| (1 << speed_offset);
6eacf311 RP	50	break;
	51	default:
	52	pr_err("speed %u not supported\n", speed);
	53	return;
	54	}
	55
	56	err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
	57	if (err)
	58	pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
	59	}
	60
af72261f XZ	61	static const struct emac_rockchip_soc_data emac_rk3036_emac_data = {
	62	.grf_offset = 0x140, .grf_mode_offset = 8,
	63	.grf_speed_offset = 9, .need_div_macclk = 1,
	64	};
	65
f4c9d3ee XZ	66	static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
	67	.grf_offset = 0x154, .grf_mode_offset = 0,
	68	.grf_speed_offset = 1, .need_div_macclk = 0,
	69	};
	70
	71	static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
	72	.grf_offset = 0x0a4, .grf_mode_offset = 0,
	73	.grf_speed_offset = 1, .need_div_macclk = 0,
6eacf311 RP	74	};
	75
	76	static const struct of_device_id emac_rockchip_dt_ids[] = {
663713eb CW	77	{
	78	.compatible = "rockchip,rk3036-emac",
	79	.data = &emac_rk3036_emac_data,
	80	},
	81	{
	82	.compatible = "rockchip,rk3066-emac",
	83	.data = &emac_rk3066_emac_data,
	84	},
	85	{
	86	.compatible = "rockchip,rk3188-emac",
	87	.data = &emac_rk3188_emac_data,
	88	},
6eacf311 RP	89	{ /* Sentinel */ }
	90	};
	91
	92	MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);
	93
	94	static int emac_rockchip_probe(struct platform_device *pdev)
	95	{
	96	struct device *dev = &pdev->dev;
	97	struct net_device *ndev;
	98	struct rockchip_priv_data *priv;
	99	const struct of_device_id *match;
	100	u32 data;
	101	int err, interface;
	102
	103	if (!pdev->dev.of_node)
	104	return -ENODEV;
	105
	106	ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
	107	if (!ndev)
	108	return -ENOMEM;
	109	platform_set_drvdata(pdev, ndev);
	110	SET_NETDEV_DEV(ndev, dev);
	111
	112	priv = netdev_priv(ndev);
	113	priv->emac.drv_name = DRV_NAME;
	114	priv->emac.drv_version = DRV_VERSION;
	115	priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;
	116
	117	interface = of_get_phy_mode(dev->of_node);
	118
af72261f	119	/* RK3036/RK3066/RK3188 SoCs only support RMII */
6eacf311 RP	120	if (interface != PHY_INTERFACE_MODE_RMII) {
	121	dev_err(dev, "unsupported phy interface mode %d\n", interface);
	122	err = -ENOTSUPP;
	123	goto out_netdev;
	124	}
	125
663713eb CW	126	priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
663713eb CW	127	"rockchip,grf");
6eacf311	128	if (IS_ERR(priv->grf)) {
663713eb CW	129	dev_err(dev, "failed to retrieve global register file (%ld)\n",
663713eb CW	130	PTR_ERR(priv->grf));
6eacf311 RP	131	err = PTR_ERR(priv->grf);
	132	goto out_netdev;
	133	}
	134
	135	match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
	136	priv->soc_data = match->data;
	137
	138	priv->emac.clk = devm_clk_get(dev, "hclk");
	139	if (IS_ERR(priv->emac.clk)) {
663713eb CW	140	dev_err(dev, "failed to retrieve host clock (%ld)\n",
663713eb CW	141	PTR_ERR(priv->emac.clk));
6eacf311 RP	142	err = PTR_ERR(priv->emac.clk);
	143	goto out_netdev;
	144	}
	145
	146	priv->refclk = devm_clk_get(dev, "macref");
	147	if (IS_ERR(priv->refclk)) {
663713eb CW	148	dev_err(dev, "failed to retrieve reference clock (%ld)\n",
663713eb CW	149	PTR_ERR(priv->refclk));
6eacf311 RP	150	err = PTR_ERR(priv->refclk);
	151	goto out_netdev;
	152	}
	153
	154	err = clk_prepare_enable(priv->refclk);
	155	if (err) {
	156	dev_err(dev, "failed to enable reference clock (%d)\n", err);
	157	goto out_netdev;
	158	}
	159
	160	/* Optional regulator for PHY */
	161	priv->regulator = devm_regulator_get_optional(dev, "phy");
	162	if (IS_ERR(priv->regulator)) {
00777fac CJ	163	if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
	164	err = -EPROBE_DEFER;
	165	goto out_clk_disable;
	166	}
6eacf311 RP	167	dev_err(dev, "no regulator found\n");
	168	priv->regulator = NULL;
	169	}
	170
	171	if (priv->regulator) {
	172	err = regulator_enable(priv->regulator);
	173	if (err) {
	174	dev_err(dev, "failed to enable phy-supply (%d)\n", err);
	175	goto out_clk_disable;
	176	}
	177	}
	178
f4c9d3ee XZ	179	/* Set speed 100M */
	180	data = (1 << (priv->soc_data->grf_speed_offset + 16)) \|
	181	(1 << priv->soc_data->grf_speed_offset);
	182	/* Set RMII mode */
	183	data \|= (1 << (priv->soc_data->grf_mode_offset + 16)) \|
	184	(0 << priv->soc_data->grf_mode_offset);
6eacf311 RP	185
	186	err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
	187	if (err) {
663713eb CW	188	dev_err(dev, "unable to apply initial settings to grf (%d)\n",
663713eb CW	189	err);
6eacf311 RP	190	goto out_regulator_disable;
	191	}
	192
	193	/* RMII interface needs always a rate of 50MHz */
	194	err = clk_set_rate(priv->refclk, 50000000);
2a9ee696	195	if (err) {
663713eb CW	196	dev_err(dev,
663713eb CW	197	"failed to change reference clock rate (%d)\n", err);
2a9ee696 BR	198	goto out_regulator_disable;
2a9ee696 BR	199	}
c9bca2fe	200
f4c9d3ee XZ	201	if (priv->soc_data->need_div_macclk) {
	202	priv->macclk = devm_clk_get(dev, "macclk");
	203	if (IS_ERR(priv->macclk)) {
663713eb CW	204	dev_err(dev, "failed to retrieve mac clock (%ld)\n",
663713eb CW	205	PTR_ERR(priv->macclk));
f4c9d3ee XZ	206	err = PTR_ERR(priv->macclk);
	207	goto out_regulator_disable;
	208	}
	209
	210	err = clk_prepare_enable(priv->macclk);
	211	if (err) {
	212	dev_err(dev, "failed to enable mac clock (%d)\n", err);
	213	goto out_regulator_disable;
	214	}
	215
	216	/* RMII TX/RX needs always a rate of 25MHz */
	217	err = clk_set_rate(priv->macclk, 25000000);
e46772a6	218	if (err) {
663713eb CW	219	dev_err(dev,
663713eb CW	220	"failed to change mac clock rate (%d)\n", err);
e46772a6 BR	221	goto out_clk_disable_macclk;
e46772a6 BR	222	}
f4c9d3ee XZ	223	}
f4c9d3ee XZ	224
c9bca2fe XZ	225	err = arc_emac_probe(ndev, interface);
	226	if (err) {
	227	dev_err(dev, "failed to probe arc emac (%d)\n", err);
2a9ee696	228	goto out_clk_disable_macclk;
c9bca2fe XZ	229	}
c9bca2fe XZ	230
6eacf311	231	return 0;
2a9ee696	232
e46772a6	233	out_clk_disable_macclk:
2a9ee696 BR	234	if (priv->soc_data->need_div_macclk)
2a9ee696 BR	235	clk_disable_unprepare(priv->macclk);
6eacf311 RP	236	out_regulator_disable:
	237	if (priv->regulator)
	238	regulator_disable(priv->regulator);
	239	out_clk_disable:
	240	clk_disable_unprepare(priv->refclk);
	241	out_netdev:
	242	free_netdev(ndev);
	243	return err;
	244	}
	245
	246	static int emac_rockchip_remove(struct platform_device *pdev)
	247	{
	248	struct net_device *ndev = platform_get_drvdata(pdev);
	249	struct rockchip_priv_data *priv = netdev_priv(ndev);
	250	int err;
	251
cf98192d RP	252	err = arc_emac_remove(ndev);
cf98192d RP	253
6eacf311 RP	254	clk_disable_unprepare(priv->refclk);
	255
	256	if (priv->regulator)
	257	regulator_disable(priv->regulator);
	258
6eacf311 RP	259	free_netdev(ndev);
	260	return err;
	261	}
	262
	263	static struct platform_driver emac_rockchip_driver = {
	264	.probe = emac_rockchip_probe,
	265	.remove = emac_rockchip_remove,
	266	.driver = {
	267	.name = DRV_NAME,
	268	.of_match_table = emac_rockchip_dt_ids,
	269	},
	270	};
	271
	272	module_platform_driver(emac_rockchip_driver);
	273
	274	MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
	275	MODULE_DESCRIPTION("Rockchip EMAC platform driver");
	276	MODULE_LICENSE("GPL");