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[thirdparty/linux.git] / drivers / net / ethernet / atheros / atlx / atl2.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
452c1ce2
CS		 2/*
3 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
4 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
452c1ce2
CS		 8 */
9
60063497 10#include <linux/atomic.h>
452c1ce2
CS		 11#include <linux/crc32.h>
12#include <linux/dma-mapping.h>
13#include <linux/etherdevice.h>
14#include <linux/ethtool.h>
15#include <linux/hardirq.h>
16#include <linux/if_vlan.h>
17#include <linux/in.h>
18#include <linux/interrupt.h>
19#include <linux/ip.h>
20#include <linux/irqflags.h>
21#include <linux/irqreturn.h>
22#include <linux/mii.h>
23#include <linux/net.h>
24#include <linux/netdevice.h>
25#include <linux/pci.h>
26#include <linux/pci_ids.h>
27#include <linux/pm.h>
28#include <linux/skbuff.h>
5a0e3ad6 29#include <linux/slab.h>
452c1ce2
CS		 30#include <linux/spinlock.h>
31#include <linux/string.h>
32#include <linux/tcp.h>
33#include <linux/timer.h>
34#include <linux/types.h>
35#include <linux/workqueue.h>
36
37#include "atl2.h"
38
39#define ATL2_DRV_VERSION "2.2.3"
40
f27e21a8 41static const char atl2_driver_name[] = "atl2";
452c1ce2 42static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
f27e21a8
SH		 43static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
44static const char atl2_driver_version[] = ATL2_DRV_VERSION;
dffe278f 45static const struct ethtool_ops atl2_ethtool_ops;
452c1ce2
CS		 46
47MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
48MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
49MODULE_LICENSE("GPL");
50MODULE_VERSION(ATL2_DRV_VERSION);
51
52/*
53 * atl2_pci_tbl - PCI Device ID Table
54 */
9baa3c34 55static const struct pci_device_id atl2_pci_tbl[] = {
452c1ce2
CS		 56 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
57 /* required last entry */
58 {0,}
59};
60MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
61
452c1ce2
CS		 62static void atl2_check_options(struct atl2_adapter *adapter);
63
49ce9c2c 64/**
452c1ce2
CS		 65 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
66 * @adapter: board private structure to initialize
67 *
68 * atl2_sw_init initializes the Adapter private data structure.
69 * Fields are initialized based on PCI device information and
70 * OS network device settings (MTU size).
71 */
093d369d 72static int atl2_sw_init(struct atl2_adapter *adapter)
452c1ce2
CS		 73{
74 struct atl2_hw *hw = &adapter->hw;
75 struct pci_dev *pdev = adapter->pdev;
76
77 /* PCI config space info */
78 hw->vendor_id = pdev->vendor;
79 hw->device_id = pdev->device;
80 hw->subsystem_vendor_id = pdev->subsystem_vendor;
81 hw->subsystem_id = pdev->subsystem_device;
ff938e43 82 hw->revision_id = pdev->revision;
452c1ce2 83
452c1ce2
CS		 84 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
85
86 adapter->wol = 0;
87 adapter->ict = 50000; /* ~100ms */
88 adapter->link_speed = SPEED_0; /* hardware init */
89 adapter->link_duplex = FULL_DUPLEX;
90
91 hw->phy_configured = false;
92 hw->preamble_len = 7;
93 hw->ipgt = 0x60;
94 hw->min_ifg = 0x50;
95 hw->ipgr1 = 0x40;
96 hw->ipgr2 = 0x60;
97 hw->retry_buf = 2;
98 hw->max_retry = 0xf;
99 hw->lcol = 0x37;
100 hw->jam_ipg = 7;
101 hw->fc_rxd_hi = 0;
102 hw->fc_rxd_lo = 0;
103 hw->max_frame_size = adapter->netdev->mtu;
104
105 spin_lock_init(&adapter->stats_lock);
452c1ce2
CS		 106
107 set_bit(__ATL2_DOWN, &adapter->flags);
108
109 return 0;
110}
111
49ce9c2c 112/**
452c1ce2
CS		 113 * atl2_set_multi - Multicast and Promiscuous mode set
114 * @netdev: network interface device structure
115 *
116 * The set_multi entry point is called whenever the multicast address
117 * list or the network interface flags are updated. This routine is
118 * responsible for configuring the hardware for proper multicast,
119 * promiscuous mode, and all-multi behavior.
120 */
121static void atl2_set_multi(struct net_device *netdev)
122{
123 struct atl2_adapter *adapter = netdev_priv(netdev);
124 struct atl2_hw *hw = &adapter->hw;
22bedad3 125 struct netdev_hw_addr *ha;
452c1ce2
CS		 126 u32 rctl;
127 u32 hash_value;
128
129 /* Check for Promiscuous and All Multicast modes */
130 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
131
132 if (netdev->flags & IFF_PROMISC) {
133 rctl |= MAC_CTRL_PROMIS_EN;
134 } else if (netdev->flags & IFF_ALLMULTI) {
135 rctl |= MAC_CTRL_MC_ALL_EN;
136 rctl &= ~MAC_CTRL_PROMIS_EN;
137 } else
138 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
139
140 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
141
142 /* clear the old settings from the multicast hash table */
143 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
144 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
145
146 /* comoute mc addresses' hash value ,and put it into hash table */
22bedad3
JP		 147 netdev_for_each_mc_addr(ha, netdev) {
148 hash_value = atl2_hash_mc_addr(hw, ha->addr);
452c1ce2
CS		 149 atl2_hash_set(hw, hash_value);
150 }
151}
152
153static void init_ring_ptrs(struct atl2_adapter *adapter)
154{
155 /* Read / Write Ptr Initialize: */
156 adapter->txd_write_ptr = 0;
157 atomic_set(&adapter->txd_read_ptr, 0);
158
159 adapter->rxd_read_ptr = 0;
160 adapter->rxd_write_ptr = 0;
161
162 atomic_set(&adapter->txs_write_ptr, 0);
163 adapter->txs_next_clear = 0;
164}
165
49ce9c2c 166/**
452c1ce2
CS		 167 * atl2_configure - Configure Transmit&Receive Unit after Reset
168 * @adapter: board private structure
169 *
170 * Configure the Tx /Rx unit of the MAC after a reset.
171 */
172static int atl2_configure(struct atl2_adapter *adapter)
173{
174 struct atl2_hw *hw = &adapter->hw;
175 u32 value;
176
177 /* clear interrupt status */
178 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
179
180 /* set MAC Address */
181 value = (((u32)hw->mac_addr[2]) << 24) |
182 (((u32)hw->mac_addr[3]) << 16) |
183 (((u32)hw->mac_addr[4]) << 8) |
184 (((u32)hw->mac_addr[5]));
185 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
186 value = (((u32)hw->mac_addr[0]) << 8) |
187 (((u32)hw->mac_addr[1]));
188 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
189
190 /* HI base address */
191 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
192 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
193
194 /* LO base address */
195 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
196 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
197 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
198 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
199 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
200 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
201
202 /* element count */
203 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
204 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
205 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
206
207 /* config Internal SRAM */
208/*
209 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
210 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
211*/
212
213 /* config IPG/IFG */
214 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
215 MAC_IPG_IFG_IPGT_SHIFT) |
216 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
217 MAC_IPG_IFG_MIFG_SHIFT) |
218 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
219 MAC_IPG_IFG_IPGR1_SHIFT)|
220 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
221 MAC_IPG_IFG_IPGR2_SHIFT);
222 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
223
224 /* config Half-Duplex Control */
225 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
226 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
227 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
228 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
229 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
230 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
231 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
232 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
233
234 /* set Interrupt Moderator Timer */
235 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
236 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
237
238 /* set Interrupt Clear Timer */
239 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
240
241 /* set MTU */
242 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
67bef942 243 ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
452c1ce2
CS		 244
245 /* 1590 */
246 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
247
248 /* flow control */
249 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
250 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
251
252 /* Init mailbox */
253 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
254 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
255
256 /* enable DMA read/write */
257 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
258 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
259
260 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
261 if ((value & ISR_PHY_LINKDOWN) != 0)
262 value = 1; /* config failed */
263 else
264 value = 0;
265
266 /* clear all interrupt status */
267 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
268 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
269 return value;
270}
271
49ce9c2c 272/**
452c1ce2
CS		 273 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
274 * @adapter: board private structure
275 *
276 * Return 0 on success, negative on failure
277 */
278static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
279{
280 struct pci_dev *pdev = adapter->pdev;
281 int size;
282 u8 offset = 0;
283
284 /* real ring DMA buffer */
285 adapter->ring_size = size =
286 adapter->txd_ring_size * 1 + 7 + /* dword align */
287 adapter->txs_ring_size * 4 + 7 + /* dword align */
288 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
289
290 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
291 &adapter->ring_dma);
292 if (!adapter->ring_vir_addr)
293 return -ENOMEM;
294 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
295
296 /* Init TXD Ring */
297 adapter->txd_dma = adapter->ring_dma ;
298 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
299 adapter->txd_dma += offset;
43d620c8 300 adapter->txd_ring = adapter->ring_vir_addr + offset;
452c1ce2
CS		 301
302 /* Init TXS Ring */
303 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
304 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
305 adapter->txs_dma += offset;
306 adapter->txs_ring = (struct tx_pkt_status *)
307 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
308
309 /* Init RXD Ring */
310 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
311 offset = (adapter->rxd_dma & 127) ?
312 (128 - (adapter->rxd_dma & 127)) : 0;
313 if (offset > 7)
314 offset -= 8;
315 else
316 offset += (128 - 8);
317
318 adapter->rxd_dma += offset;
319 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
320 (adapter->txs_ring_size * 4 + offset));
321
322/*
323 * Read / Write Ptr Initialize:
324 * init_ring_ptrs(adapter);
325 */
326 return 0;
327}
328
49ce9c2c 329/**
452c1ce2
CS		 330 * atl2_irq_enable - Enable default interrupt generation settings
331 * @adapter: board private structure
332 */
333static inline void atl2_irq_enable(struct atl2_adapter *adapter)
334{
335 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
336 ATL2_WRITE_FLUSH(&adapter->hw);
337}
338
49ce9c2c 339/**
452c1ce2
CS		 340 * atl2_irq_disable - Mask off interrupt generation on the NIC
341 * @adapter: board private structure
342 */
343static inline void atl2_irq_disable(struct atl2_adapter *adapter)
344{
345 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
346 ATL2_WRITE_FLUSH(&adapter->hw);
347 synchronize_irq(adapter->pdev->irq);
348}
349
c8f44aff 350static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl)
dc437974 351{
f646968f 352 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
dc437974
JP		 353 /* enable VLAN tag insert/strip */
354 *ctrl |= MAC_CTRL_RMV_VLAN;
355 } else {
356 /* disable VLAN tag insert/strip */
357 *ctrl &= ~MAC_CTRL_RMV_VLAN;
358 }
359}
360
c8f44aff
MM		 361static void atl2_vlan_mode(struct net_device *netdev,
362 netdev_features_t features)
452c1ce2
CS		 363{
364 struct atl2_adapter *adapter = netdev_priv(netdev);
365 u32 ctrl;
366
367 atl2_irq_disable(adapter);
452c1ce2 368
dc437974
JP		 369 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
370 __atl2_vlan_mode(features, &ctrl);
371 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
452c1ce2
CS		 372
373 atl2_irq_enable(adapter);
374}
375
376static void atl2_restore_vlan(struct atl2_adapter *adapter)
377{
dc437974
JP		 378 atl2_vlan_mode(adapter->netdev, adapter->netdev->features);
379}
380
c8f44aff
MM		 381static netdev_features_t atl2_fix_features(struct net_device *netdev,
382 netdev_features_t features)
dc437974
JP		 383{
384 /*
385 * Since there is no support for separate rx/tx vlan accel
386 * enable/disable make sure tx flag is always in same state as rx.
387 */
f646968f
PM		 388 if (features & NETIF_F_HW_VLAN_CTAG_RX)
389 features |= NETIF_F_HW_VLAN_CTAG_TX;
dc437974 390 else
f646968f 391 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
dc437974
JP		 392
393 return features;
394}
395
c8f44aff
MM		 396static int atl2_set_features(struct net_device *netdev,
397 netdev_features_t features)
dc437974 398{
c8f44aff 399 netdev_features_t changed = netdev->features ^ features;
dc437974 400
f646968f 401 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
dc437974
JP		 402 atl2_vlan_mode(netdev, features);
403
404 return 0;
452c1ce2 405}
452c1ce2
CS		 406
407static void atl2_intr_rx(struct atl2_adapter *adapter)
408{
409 struct net_device *netdev = adapter->netdev;
410 struct rx_desc *rxd;
411 struct sk_buff *skb;
412
413 do {
414 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
415 if (!rxd->status.update)
416 break; /* end of tx */
417
418 /* clear this flag at once */
419 rxd->status.update = 0;
420
421 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
422 int rx_size = (int)(rxd->status.pkt_size - 4);
423 /* alloc new buffer */
89d71a66 424 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
452c1ce2 425 if (NULL == skb) {
452c1ce2
CS		 426 /*
427 * Check that some rx space is free. If not,
428 * free one and mark stats->rx_dropped++.
429 */
02e71731 430 netdev->stats.rx_dropped++;
452c1ce2
CS		 431 break;
432 }
452c1ce2
CS		 433 memcpy(skb->data, rxd->packet, rx_size);
434 skb_put(skb, rx_size);
435 skb->protocol = eth_type_trans(skb, netdev);
dc437974 436 if (rxd->status.vlan) {
452c1ce2
CS		 437 u16 vlan_tag = (rxd->status.vtag>>4) |
438 ((rxd->status.vtag&7) << 13) |
439 ((rxd->status.vtag&8) << 9);
dc437974 440
86a9bad3 441 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
dc437974 442 }
452c1ce2 443 netif_rx(skb);
02e71731
SH		 444 netdev->stats.rx_bytes += rx_size;
445 netdev->stats.rx_packets++;
452c1ce2 446 } else {
02e71731 447 netdev->stats.rx_errors++;
452c1ce2
CS		 448
449 if (rxd->status.ok && rxd->status.pkt_size <= 60)
02e71731 450 netdev->stats.rx_length_errors++;
452c1ce2 451 if (rxd->status.mcast)
02e71731 452 netdev->stats.multicast++;
452c1ce2 453 if (rxd->status.crc)
02e71731 454 netdev->stats.rx_crc_errors++;
452c1ce2 455 if (rxd->status.align)
02e71731 456 netdev->stats.rx_frame_errors++;
452c1ce2
CS		 457 }
458
459 /* advance write ptr */
460 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
461 adapter->rxd_write_ptr = 0;
462 } while (1);
463
464 /* update mailbox? */
465 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
466 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
467}
468
469static void atl2_intr_tx(struct atl2_adapter *adapter)
470{
02e71731 471 struct net_device *netdev = adapter->netdev;
452c1ce2
CS		 472 u32 txd_read_ptr;
473 u32 txs_write_ptr;
474 struct tx_pkt_status *txs;
475 struct tx_pkt_header *txph;
476 int free_hole = 0;
477
478 do {
479 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
480 txs = adapter->txs_ring + txs_write_ptr;
481 if (!txs->update)
482 break; /* tx stop here */
483
484 free_hole = 1;
485 txs->update = 0;
486
487 if (++txs_write_ptr == adapter->txs_ring_size)
488 txs_write_ptr = 0;
489 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
490
491 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
492 txph = (struct tx_pkt_header *)
493 (((u8 *)adapter->txd_ring) + txd_read_ptr);
494
495 if (txph->pkt_size != txs->pkt_size) {
496 struct tx_pkt_status *old_txs = txs;
497 printk(KERN_WARNING
498 "%s: txs packet size not consistent with txd"
499 " txd_:0x%08x, txs_:0x%08x!\n",
500 adapter->netdev->name,
501 *(u32 *)txph, *(u32 *)txs);
502 printk(KERN_WARNING
503 "txd read ptr: 0x%x\n",
504 txd_read_ptr);
505 txs = adapter->txs_ring + txs_write_ptr;
506 printk(KERN_WARNING
507 "txs-behind:0x%08x\n",
508 *(u32 *)txs);
509 if (txs_write_ptr < 2) {
510 txs = adapter->txs_ring +
511 (adapter->txs_ring_size +
512 txs_write_ptr - 2);
513 } else {
514 txs = adapter->txs_ring + (txs_write_ptr - 2);
515 }
516 printk(KERN_WARNING
517 "txs-before:0x%08x\n",
518 *(u32 *)txs);
519 txs = old_txs;
520 }
521
522 /* 4for TPH */
523 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
524 if (txd_read_ptr >= adapter->txd_ring_size)
525 txd_read_ptr -= adapter->txd_ring_size;
526
527 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
528
529 /* tx statistics: */
e2f092ff 530 if (txs->ok) {
02e71731
SH		 531 netdev->stats.tx_bytes += txs->pkt_size;
532 netdev->stats.tx_packets++;
e2f092ff 533 }
452c1ce2 534 else
02e71731 535 netdev->stats.tx_errors++;
452c1ce2
CS		 536
537 if (txs->defer)
02e71731 538 netdev->stats.collisions++;
452c1ce2 539 if (txs->abort_col)
02e71731 540 netdev->stats.tx_aborted_errors++;
452c1ce2 541 if (txs->late_col)
02e71731 542 netdev->stats.tx_window_errors++;
66c03171 543 if (txs->underrun)
02e71731 544 netdev->stats.tx_fifo_errors++;
452c1ce2
CS		 545 } while (1);
546
547 if (free_hole) {
548 if (netif_queue_stopped(adapter->netdev) &&
549 netif_carrier_ok(adapter->netdev))
550 netif_wake_queue(adapter->netdev);
551 }
552}
553
554static void atl2_check_for_link(struct atl2_adapter *adapter)
555{
556 struct net_device *netdev = adapter->netdev;
557 u16 phy_data = 0;
558
559 spin_lock(&adapter->stats_lock);
560 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
561 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
562 spin_unlock(&adapter->stats_lock);
563
564 /* notify upper layer link down ASAP */
565 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
566 if (netif_carrier_ok(netdev)) { /* old link state: Up */
567 printk(KERN_INFO "%s: %s NIC Link is Down\n",
568 atl2_driver_name, netdev->name);
569 adapter->link_speed = SPEED_0;
570 netif_carrier_off(netdev);
571 netif_stop_queue(netdev);
572 }
573 }
574 schedule_work(&adapter->link_chg_task);
575}
576
577static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
578{
579 u16 phy_data;
580 spin_lock(&adapter->stats_lock);
581 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
582 spin_unlock(&adapter->stats_lock);
583}
584
49ce9c2c 585/**
452c1ce2
CS		 586 * atl2_intr - Interrupt Handler
587 * @irq: interrupt number
588 * @data: pointer to a network interface device structure
452c1ce2
CS		 589 */
590static irqreturn_t atl2_intr(int irq, void *data)
591{
592 struct atl2_adapter *adapter = netdev_priv(data);
593 struct atl2_hw *hw = &adapter->hw;
594 u32 status;
595
596 status = ATL2_READ_REG(hw, REG_ISR);
597 if (0 == status)
598 return IRQ_NONE;
599
600 /* link event */
601 if (status & ISR_PHY)
602 atl2_clear_phy_int(adapter);
603
604 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
605 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
606
607 /* check if PCIE PHY Link down */
608 if (status & ISR_PHY_LINKDOWN) {
609 if (netif_running(adapter->netdev)) { /* reset MAC */
610 ATL2_WRITE_REG(hw, REG_ISR, 0);
611 ATL2_WRITE_REG(hw, REG_IMR, 0);
612 ATL2_WRITE_FLUSH(hw);
613 schedule_work(&adapter->reset_task);
614 return IRQ_HANDLED;
615 }
616 }
617
618 /* check if DMA read/write error? */
619 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
620 ATL2_WRITE_REG(hw, REG_ISR, 0);
621 ATL2_WRITE_REG(hw, REG_IMR, 0);
622 ATL2_WRITE_FLUSH(hw);
623 schedule_work(&adapter->reset_task);
624 return IRQ_HANDLED;
625 }
626
627 /* link event */
628 if (status & (ISR_PHY | ISR_MANUAL)) {
02e71731 629 adapter->netdev->stats.tx_carrier_errors++;
452c1ce2
CS		 630 atl2_check_for_link(adapter);
631 }
632
633 /* transmit event */
634 if (status & ISR_TX_EVENT)
635 atl2_intr_tx(adapter);
636
637 /* rx exception */
638 if (status & ISR_RX_EVENT)
639 atl2_intr_rx(adapter);
640
641 /* re-enable Interrupt */
642 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
643 return IRQ_HANDLED;
644}
645
646static int atl2_request_irq(struct atl2_adapter *adapter)
647{
648 struct net_device *netdev = adapter->netdev;
649 int flags, err = 0;
650
651 flags = IRQF_SHARED;
452c1ce2
CS		 652 adapter->have_msi = true;
653 err = pci_enable_msi(adapter->pdev);
654 if (err)
655 adapter->have_msi = false;
656
657 if (adapter->have_msi)
658 flags &= ~IRQF_SHARED;
452c1ce2 659
a0607fd3 660 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
452c1ce2
CS		 661 netdev);
662}
663
49ce9c2c 664/**
452c1ce2
CS		 665 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
666 * @adapter: board private structure
667 *
668 * Free all transmit software resources
669 */
670static void atl2_free_ring_resources(struct atl2_adapter *adapter)
671{
672 struct pci_dev *pdev = adapter->pdev;
673 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
674 adapter->ring_dma);
675}
676
49ce9c2c 677/**
452c1ce2
CS		 678 * atl2_open - Called when a network interface is made active
679 * @netdev: network interface device structure
680 *
681 * Returns 0 on success, negative value on failure
682 *
683 * The open entry point is called when a network interface is made
684 * active by the system (IFF_UP). At this point all resources needed
685 * for transmit and receive operations are allocated, the interrupt
686 * handler is registered with the OS, the watchdog timer is started,
687 * and the stack is notified that the interface is ready.
688 */
689static int atl2_open(struct net_device *netdev)
690{
691 struct atl2_adapter *adapter = netdev_priv(netdev);
692 int err;
693 u32 val;
694
695 /* disallow open during test */
696 if (test_bit(__ATL2_TESTING, &adapter->flags))
697 return -EBUSY;
698
699 /* allocate transmit descriptors */
700 err = atl2_setup_ring_resources(adapter);
701 if (err)
702 return err;
703
704 err = atl2_init_hw(&adapter->hw);
705 if (err) {
706 err = -EIO;
707 goto err_init_hw;
708 }
709
710 /* hardware has been reset, we need to reload some things */
711 atl2_set_multi(netdev);
712 init_ring_ptrs(adapter);
713
452c1ce2 714 atl2_restore_vlan(adapter);
452c1ce2
CS		 715
716 if (atl2_configure(adapter)) {
717 err = -EIO;
718 goto err_config;
719 }
720
721 err = atl2_request_irq(adapter);
722 if (err)
723 goto err_req_irq;
724
725 clear_bit(__ATL2_DOWN, &adapter->flags);
726
e053b628 727 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
452c1ce2
CS		 728
729 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
730 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
731 val | MASTER_CTRL_MANUAL_INT);
732
733 atl2_irq_enable(adapter);
734
735 return 0;
736
737err_init_hw:
738err_req_irq:
739err_config:
740 atl2_free_ring_resources(adapter);
741 atl2_reset_hw(&adapter->hw);
742
743 return err;
744}
745
746static void atl2_down(struct atl2_adapter *adapter)
747{
748 struct net_device *netdev = adapter->netdev;
749
750 /* signal that we're down so the interrupt handler does not
751 * reschedule our watchdog timer */
752 set_bit(__ATL2_DOWN, &adapter->flags);
753
452c1ce2 754 netif_tx_disable(netdev);
452c1ce2
CS		 755
756 /* reset MAC to disable all RX/TX */
757 atl2_reset_hw(&adapter->hw);
758 msleep(1);
759
760 atl2_irq_disable(adapter);
761
762 del_timer_sync(&adapter->watchdog_timer);
763 del_timer_sync(&adapter->phy_config_timer);
764 clear_bit(0, &adapter->cfg_phy);
765
766 netif_carrier_off(netdev);
767 adapter->link_speed = SPEED_0;
768 adapter->link_duplex = -1;
769}
770
771static void atl2_free_irq(struct atl2_adapter *adapter)
772{
773 struct net_device *netdev = adapter->netdev;
774
775 free_irq(adapter->pdev->irq, netdev);
776
777#ifdef CONFIG_PCI_MSI
778 if (adapter->have_msi)
779 pci_disable_msi(adapter->pdev);
780#endif
781}
782
49ce9c2c 783/**
452c1ce2
CS		 784 * atl2_close - Disables a network interface
785 * @netdev: network interface device structure
786 *
787 * Returns 0, this is not allowed to fail
788 *
789 * The close entry point is called when an interface is de-activated
790 * by the OS. The hardware is still under the drivers control, but
791 * needs to be disabled. A global MAC reset is issued to stop the
792 * hardware, and all transmit and receive resources are freed.
793 */
794static int atl2_close(struct net_device *netdev)
795{
796 struct atl2_adapter *adapter = netdev_priv(netdev);
797
798 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
799
800 atl2_down(adapter);
801 atl2_free_irq(adapter);
802 atl2_free_ring_resources(adapter);
803
804 return 0;
805}
806
807static inline int TxsFreeUnit(struct atl2_adapter *adapter)
808{
809 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
810
811 return (adapter->txs_next_clear >= txs_write_ptr) ?
812 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
813 txs_write_ptr - 1) :
814 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
815}
816
817static inline int TxdFreeBytes(struct atl2_adapter *adapter)
818{
819 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
820
821 return (adapter->txd_write_ptr >= txd_read_ptr) ?
822 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
823 txd_read_ptr - 1) :
824 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
825}
826
61357325
SH		 827static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
828 struct net_device *netdev)
452c1ce2
CS		 829{
830 struct atl2_adapter *adapter = netdev_priv(netdev);
452c1ce2
CS		 831 struct tx_pkt_header *txph;
832 u32 offset, copy_len;
833 int txs_unused;
834 int txbuf_unused;
835
836 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
837 dev_kfree_skb_any(skb);
838 return NETDEV_TX_OK;
839 }
840
841 if (unlikely(skb->len <= 0)) {
842 dev_kfree_skb_any(skb);
843 return NETDEV_TX_OK;
844 }
845
452c1ce2
CS		 846 txs_unused = TxsFreeUnit(adapter);
847 txbuf_unused = TxdFreeBytes(adapter);
848
849 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
850 txs_unused < 1) {
851 /* not enough resources */
852 netif_stop_queue(netdev);
452c1ce2
CS		 853 return NETDEV_TX_BUSY;
854 }
855
856 offset = adapter->txd_write_ptr;
857
858 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
859
860 *(u32 *)txph = 0;
861 txph->pkt_size = skb->len;
862
863 offset += 4;
864 if (offset >= adapter->txd_ring_size)
865 offset -= adapter->txd_ring_size;
866 copy_len = adapter->txd_ring_size - offset;
867 if (copy_len >= skb->len) {
868 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
869 offset += ((u32)(skb->len + 3) & ~3);
870 } else {
871 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
872 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
873 skb->len-copy_len);
874 offset = ((u32)(skb->len-copy_len + 3) & ~3);
875 }
f646968f 876#ifdef NETIF_F_HW_VLAN_CTAG_TX
df8a39de
JP		 877 if (skb_vlan_tag_present(skb)) {
878 u16 vlan_tag = skb_vlan_tag_get(skb);
452c1ce2
CS		 879 vlan_tag = (vlan_tag << 4) |
880 (vlan_tag >> 13) |
881 ((vlan_tag >> 9) & 0x8);
882 txph->ins_vlan = 1;
883 txph->vlan = vlan_tag;
884 }
885#endif
886 if (offset >= adapter->txd_ring_size)
887 offset -= adapter->txd_ring_size;
888 adapter->txd_write_ptr = offset;
889
890 /* clear txs before send */
891 adapter->txs_ring[adapter->txs_next_clear].update = 0;
892 if (++adapter->txs_next_clear == adapter->txs_ring_size)
893 adapter->txs_next_clear = 0;
894
895 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
896 (adapter->txd_write_ptr >> 2));
897
7304720d 898 dev_consume_skb_any(skb);
452c1ce2
CS		 899 return NETDEV_TX_OK;
900}
901
49ce9c2c 902/**
452c1ce2
CS		 903 * atl2_change_mtu - Change the Maximum Transfer Unit
904 * @netdev: network interface device structure
905 * @new_mtu: new value for maximum frame size
906 *
907 * Returns 0 on success, negative on failure
908 */
909static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
910{
911 struct atl2_adapter *adapter = netdev_priv(netdev);
912 struct atl2_hw *hw = &adapter->hw;
913
452c1ce2 914 /* set MTU */
67bef942
JW		 915 netdev->mtu = new_mtu;
916 hw->max_frame_size = new_mtu;
917 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ETH_HLEN +
918 VLAN_HLEN + ETH_FCS_LEN);
452c1ce2
CS		 919
920 return 0;
921}
922
49ce9c2c 923/**
452c1ce2
CS		 924 * atl2_set_mac - Change the Ethernet Address of the NIC
925 * @netdev: network interface device structure
926 * @p: pointer to an address structure
927 *
928 * Returns 0 on success, negative on failure
929 */
930static int atl2_set_mac(struct net_device *netdev, void *p)
931{
932 struct atl2_adapter *adapter = netdev_priv(netdev);
933 struct sockaddr *addr = p;
934
935 if (!is_valid_ether_addr(addr->sa_data))
936 return -EADDRNOTAVAIL;
937
938 if (netif_running(netdev))
939 return -EBUSY;
940
941 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
942 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
943
944 atl2_set_mac_addr(&adapter->hw);
945
946 return 0;
947}
948
452c1ce2
CS		 949static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
950{
951 struct atl2_adapter *adapter = netdev_priv(netdev);
952 struct mii_ioctl_data *data = if_mii(ifr);
953 unsigned long flags;
954
955 switch (cmd) {
956 case SIOCGMIIPHY:
957 data->phy_id = 0;
958 break;
959 case SIOCGMIIREG:
452c1ce2
CS		 960 spin_lock_irqsave(&adapter->stats_lock, flags);
961 if (atl2_read_phy_reg(&adapter->hw,
962 data->reg_num & 0x1F, &data->val_out)) {
963 spin_unlock_irqrestore(&adapter->stats_lock, flags);
964 return -EIO;
965 }
966 spin_unlock_irqrestore(&adapter->stats_lock, flags);
967 break;
968 case SIOCSMIIREG:
452c1ce2
CS		 969 if (data->reg_num & ~(0x1F))
970 return -EFAULT;
971 spin_lock_irqsave(&adapter->stats_lock, flags);
972 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
973 data->val_in)) {
974 spin_unlock_irqrestore(&adapter->stats_lock, flags);
975 return -EIO;
976 }
977 spin_unlock_irqrestore(&adapter->stats_lock, flags);
978 break;
979 default:
980 return -EOPNOTSUPP;
981 }
982 return 0;
983}
984
452c1ce2
CS		 985static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
986{
987 switch (cmd) {
988 case SIOCGMIIPHY:
989 case SIOCGMIIREG:
990 case SIOCSMIIREG:
991 return atl2_mii_ioctl(netdev, ifr, cmd);
992#ifdef ETHTOOL_OPS_COMPAT
993 case SIOCETHTOOL:
994 return ethtool_ioctl(ifr);
995#endif
996 default:
997 return -EOPNOTSUPP;
998 }
999}
1000
49ce9c2c 1001/**
452c1ce2
CS		 1002 * atl2_tx_timeout - Respond to a Tx Hang
1003 * @netdev: network interface device structure
1004 */
1005static void atl2_tx_timeout(struct net_device *netdev)
1006{
1007 struct atl2_adapter *adapter = netdev_priv(netdev);
1008
1009 /* Do the reset outside of interrupt context */
1010 schedule_work(&adapter->reset_task);
1011}
1012
49ce9c2c 1013/**
452c1ce2
CS		 1014 * atl2_watchdog - Timer Call-back
1015 * @data: pointer to netdev cast into an unsigned long
1016 */
e99e88a9 1017static void atl2_watchdog(struct timer_list *t)
452c1ce2 1018{
e99e88a9 1019 struct atl2_adapter *adapter = from_timer(adapter, t, watchdog_timer);
452c1ce2
CS		 1020
1021 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
02e71731
SH		 1022 u32 drop_rxd, drop_rxs;
1023 unsigned long flags;
1024
452c1ce2
CS		 1025 spin_lock_irqsave(&adapter->stats_lock, flags);
1026 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1027 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
452c1ce2
CS		 1028 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1029
02e71731
SH		 1030 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1031
452c1ce2 1032 /* Reset the timer */
e053b628
SH		 1033 mod_timer(&adapter->watchdog_timer,
1034 round_jiffies(jiffies + 4 * HZ));
452c1ce2
CS		 1035 }
1036}
1037
49ce9c2c 1038/**
452c1ce2
CS		 1039 * atl2_phy_config - Timer Call-back
1040 * @data: pointer to netdev cast into an unsigned long
1041 */
e99e88a9 1042static void atl2_phy_config(struct timer_list *t)
452c1ce2 1043{
e99e88a9
KC		 1044 struct atl2_adapter *adapter = from_timer(adapter, t,
1045 phy_config_timer);
452c1ce2
CS		 1046 struct atl2_hw *hw = &adapter->hw;
1047 unsigned long flags;
1048
1049 spin_lock_irqsave(&adapter->stats_lock, flags);
1050 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1051 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1052 MII_CR_RESTART_AUTO_NEG);
1053 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1054 clear_bit(0, &adapter->cfg_phy);
1055}
1056
1057static int atl2_up(struct atl2_adapter *adapter)
1058{
1059 struct net_device *netdev = adapter->netdev;
1060 int err = 0;
1061 u32 val;
1062
1063 /* hardware has been reset, we need to reload some things */
1064
1065 err = atl2_init_hw(&adapter->hw);
1066 if (err) {
1067 err = -EIO;
1068 return err;
1069 }
1070
1071 atl2_set_multi(netdev);
1072 init_ring_ptrs(adapter);
1073
452c1ce2 1074 atl2_restore_vlan(adapter);
452c1ce2
CS		 1075
1076 if (atl2_configure(adapter)) {
1077 err = -EIO;
1078 goto err_up;
1079 }
1080
1081 clear_bit(__ATL2_DOWN, &adapter->flags);
1082
1083 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1084 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1085 MASTER_CTRL_MANUAL_INT);
1086
1087 atl2_irq_enable(adapter);
1088
1089err_up:
1090 return err;
1091}
1092
1093static void atl2_reinit_locked(struct atl2_adapter *adapter)
1094{
1095 WARN_ON(in_interrupt());
1096 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1097 msleep(1);
1098 atl2_down(adapter);
1099 atl2_up(adapter);
1100 clear_bit(__ATL2_RESETTING, &adapter->flags);
1101}
1102
1103static void atl2_reset_task(struct work_struct *work)
1104{
1105 struct atl2_adapter *adapter;
1106 adapter = container_of(work, struct atl2_adapter, reset_task);
1107
1108 atl2_reinit_locked(adapter);
1109}
1110
1111static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1112{
1113 u32 value;
1114 struct atl2_hw *hw = &adapter->hw;
1115 struct net_device *netdev = adapter->netdev;
1116
1117 /* Config MAC CTRL Register */
1118 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1119
1120 /* duplex */
1121 if (FULL_DUPLEX == adapter->link_duplex)
1122 value |= MAC_CTRL_DUPLX;
1123
1124 /* flow control */
1125 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1126
1127 /* PAD & CRC */
1128 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1129
1130 /* preamble length */
1131 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1132 MAC_CTRL_PRMLEN_SHIFT);
1133
1134 /* vlan */
dc437974 1135 __atl2_vlan_mode(netdev->features, &value);
452c1ce2
CS		 1136
1137 /* filter mode */
1138 value |= MAC_CTRL_BC_EN;
1139 if (netdev->flags & IFF_PROMISC)
1140 value |= MAC_CTRL_PROMIS_EN;
1141 else if (netdev->flags & IFF_ALLMULTI)
1142 value |= MAC_CTRL_MC_ALL_EN;
1143
1144 /* half retry buffer */
1145 value |= (((u32)(adapter->hw.retry_buf &
1146 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1147
1148 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1149}
1150
1151static int atl2_check_link(struct atl2_adapter *adapter)
1152{
1153 struct atl2_hw *hw = &adapter->hw;
1154 struct net_device *netdev = adapter->netdev;
1155 int ret_val;
1156 u16 speed, duplex, phy_data;
1157 int reconfig = 0;
1158
1159 /* MII_BMSR must read twise */
1160 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1161 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1162 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1163 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1164 u32 value;
1165 /* disable rx */
1166 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1167 value &= ~MAC_CTRL_RX_EN;
1168 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1169 adapter->link_speed = SPEED_0;
1170 netif_carrier_off(netdev);
1171 netif_stop_queue(netdev);
1172 }
1173 return 0;
1174 }
1175
1176 /* Link Up */
1177 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1178 if (ret_val)
1179 return ret_val;
1180 switch (hw->MediaType) {
1181 case MEDIA_TYPE_100M_FULL:
1182 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1183 reconfig = 1;
1184 break;
1185 case MEDIA_TYPE_100M_HALF:
1186 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1187 reconfig = 1;
1188 break;
1189 case MEDIA_TYPE_10M_FULL:
1190 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1191 reconfig = 1;
1192 break;
1193 case MEDIA_TYPE_10M_HALF:
1194 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1195 reconfig = 1;
1196 break;
1197 }
1198 /* link result is our setting */
1199 if (reconfig == 0) {
1200 if (adapter->link_speed != speed ||
1201 adapter->link_duplex != duplex) {
1202 adapter->link_speed = speed;
1203 adapter->link_duplex = duplex;
1204 atl2_setup_mac_ctrl(adapter);
1205 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1206 atl2_driver_name, netdev->name,
1207 adapter->link_speed,
1208 adapter->link_duplex == FULL_DUPLEX ?
1209 "Full Duplex" : "Half Duplex");
1210 }
1211
1212 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1213 netif_carrier_on(netdev);
1214 netif_wake_queue(netdev);
1215 }
1216 return 0;
1217 }
1218
1219 /* change original link status */
1220 if (netif_carrier_ok(netdev)) {
1221 u32 value;
1222 /* disable rx */
1223 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1224 value &= ~MAC_CTRL_RX_EN;
1225 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1226
1227 adapter->link_speed = SPEED_0;
1228 netif_carrier_off(netdev);
1229 netif_stop_queue(netdev);
1230 }
1231
1232 /* auto-neg, insert timer to re-config phy
1233 * (if interval smaller than 5 seconds, something strange) */
1234 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1235 if (!test_and_set_bit(0, &adapter->cfg_phy))
e053b628
SH		 1236 mod_timer(&adapter->phy_config_timer,
1237 round_jiffies(jiffies + 5 * HZ));
452c1ce2
CS		 1238 }
1239
1240 return 0;
1241}
1242
49ce9c2c 1243/**
452c1ce2 1244 * atl2_link_chg_task - deal with link change event Out of interrupt context
452c1ce2
CS		 1245 */
1246static void atl2_link_chg_task(struct work_struct *work)
1247{
1248 struct atl2_adapter *adapter;
1249 unsigned long flags;
1250
1251 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1252
1253 spin_lock_irqsave(&adapter->stats_lock, flags);
1254 atl2_check_link(adapter);
1255 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1256}
1257
1258static void atl2_setup_pcicmd(struct pci_dev *pdev)
1259{
1260 u16 cmd;
1261
1262 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1263
1264 if (cmd & PCI_COMMAND_INTX_DISABLE)
1265 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1266 if (cmd & PCI_COMMAND_IO)
1267 cmd &= ~PCI_COMMAND_IO;
1268 if (0 == (cmd & PCI_COMMAND_MEMORY))
1269 cmd |= PCI_COMMAND_MEMORY;
1270 if (0 == (cmd & PCI_COMMAND_MASTER))
1271 cmd |= PCI_COMMAND_MASTER;
1272 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1273
1274 /*
1275 * some motherboards BIOS(PXE/EFI) driver may set PME
1276 * while they transfer control to OS (Windows/Linux)
1277 * so we should clear this bit before NIC work normally
1278 */
1279 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1280}
1281
8d1b1fc9
KH		 1282#ifdef CONFIG_NET_POLL_CONTROLLER
1283static void atl2_poll_controller(struct net_device *netdev)
1284{
1285 disable_irq(netdev->irq);
1286 atl2_intr(netdev->irq, netdev);
1287 enable_irq(netdev->irq);
1288}
1289#endif
1290
825a84d1
SH		 1291
1292static const struct net_device_ops atl2_netdev_ops = {
1293 .ndo_open = atl2_open,
1294 .ndo_stop = atl2_close,
00829823 1295 .ndo_start_xmit = atl2_xmit_frame,
afc4b13d 1296 .ndo_set_rx_mode = atl2_set_multi,
825a84d1
SH		 1297 .ndo_validate_addr = eth_validate_addr,
1298 .ndo_set_mac_address = atl2_set_mac,
1299 .ndo_change_mtu = atl2_change_mtu,
dc437974
JP		 1300 .ndo_fix_features = atl2_fix_features,
1301 .ndo_set_features = atl2_set_features,
825a84d1
SH		 1302 .ndo_do_ioctl = atl2_ioctl,
1303 .ndo_tx_timeout = atl2_tx_timeout,
825a84d1
SH		 1304#ifdef CONFIG_NET_POLL_CONTROLLER
1305 .ndo_poll_controller = atl2_poll_controller,
1306#endif
1307};
1308
49ce9c2c 1309/**
452c1ce2
CS		 1310 * atl2_probe - Device Initialization Routine
1311 * @pdev: PCI device information struct
1312 * @ent: entry in atl2_pci_tbl
1313 *
1314 * Returns 0 on success, negative on failure
1315 *
1316 * atl2_probe initializes an adapter identified by a pci_dev structure.
1317 * The OS initialization, configuring of the adapter private structure,
1318 * and a hardware reset occur.
1319 */
1dd06ae8 1320static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
452c1ce2
CS		 1321{
1322 struct net_device *netdev;
1323 struct atl2_adapter *adapter;
4593403f 1324 static int cards_found = 0;
452c1ce2
CS		 1325 unsigned long mmio_start;
1326 int mmio_len;
1327 int err;
1328
452c1ce2
CS		 1329 err = pci_enable_device(pdev);
1330 if (err)
1331 return err;
1332
1333 /*
1334 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1335 * until the kernel has the proper infrastructure to support 64-bit DMA
1336 * on these devices.
1337 */
284901a9
YH		 1338 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1339 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
452c1ce2 1340 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
bd703a15 1341 err = -EIO;
452c1ce2
CS		 1342 goto err_dma;
1343 }
1344
1345 /* Mark all PCI regions associated with PCI device
1346 * pdev as being reserved by owner atl2_driver_name */
1347 err = pci_request_regions(pdev, atl2_driver_name);
1348 if (err)
1349 goto err_pci_reg;
1350
1351 /* Enables bus-mastering on the device and calls
1352 * pcibios_set_master to do the needed arch specific settings */
1353 pci_set_master(pdev);
1354
452c1ce2 1355 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
bd703a15
AK		 1356 if (!netdev) {
1357 err = -ENOMEM;
452c1ce2 1358 goto err_alloc_etherdev;
bd703a15 1359 }
452c1ce2
CS		 1360
1361 SET_NETDEV_DEV(netdev, &pdev->dev);
1362
1363 pci_set_drvdata(pdev, netdev);
1364 adapter = netdev_priv(netdev);
1365 adapter->netdev = netdev;
1366 adapter->pdev = pdev;
1367 adapter->hw.back = adapter;
1368
1369 mmio_start = pci_resource_start(pdev, 0x0);
1370 mmio_len = pci_resource_len(pdev, 0x0);
1371
1372 adapter->hw.mem_rang = (u32)mmio_len;
1373 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1374 if (!adapter->hw.hw_addr) {
1375 err = -EIO;
1376 goto err_ioremap;
1377 }
1378
1379 atl2_setup_pcicmd(pdev);
1380
825a84d1 1381 netdev->netdev_ops = &atl2_netdev_ops;
7ad24ea4 1382 netdev->ethtool_ops = &atl2_ethtool_ops;
452c1ce2 1383 netdev->watchdog_timeo = 5 * HZ;
67bef942
JW		 1384 netdev->min_mtu = 40;
1385 netdev->max_mtu = ETH_DATA_LEN + VLAN_HLEN;
452c1ce2
CS		 1386 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1387
1388 netdev->mem_start = mmio_start;
1389 netdev->mem_end = mmio_start + mmio_len;
1390 adapter->bd_number = cards_found;
1391 adapter->pci_using_64 = false;
1392
1393 /* setup the private structure */
1394 err = atl2_sw_init(adapter);
1395 if (err)
1396 goto err_sw_init;
1397
f43bfaed 1398 netdev->hw_features = NETIF_F_HW_VLAN_CTAG_RX;
f646968f 1399 netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
452c1ce2 1400
452c1ce2
CS		 1401 /* Init PHY as early as possible due to power saving issue */
1402 atl2_phy_init(&adapter->hw);
1403
1404 /* reset the controller to
1405 * put the device in a known good starting state */
1406
1407 if (atl2_reset_hw(&adapter->hw)) {
1408 err = -EIO;
1409 goto err_reset;
1410 }
1411
1412 /* copy the MAC address out of the EEPROM */
1413 atl2_read_mac_addr(&adapter->hw);
1414 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
452c1ce2 1415 if (!is_valid_ether_addr(netdev->dev_addr)) {
452c1ce2
CS		 1416 err = -EIO;
1417 goto err_eeprom;
1418 }
1419
1420 atl2_check_options(adapter);
1421
e99e88a9 1422 timer_setup(&adapter->watchdog_timer, atl2_watchdog, 0);
452c1ce2 1423
e99e88a9 1424 timer_setup(&adapter->phy_config_timer, atl2_phy_config, 0);
452c1ce2
CS		 1425
1426 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1427 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1428
1429 strcpy(netdev->name, "eth%d"); /* ?? */
1430 err = register_netdev(netdev);
1431 if (err)
1432 goto err_register;
1433
1434 /* assume we have no link for now */
1435 netif_carrier_off(netdev);
1436 netif_stop_queue(netdev);
1437
1438 cards_found++;
1439
1440 return 0;
1441
1442err_reset:
1443err_register:
1444err_sw_init:
1445err_eeprom:
1446 iounmap(adapter->hw.hw_addr);
1447err_ioremap:
1448 free_netdev(netdev);
1449err_alloc_etherdev:
1450 pci_release_regions(pdev);
1451err_pci_reg:
1452err_dma:
1453 pci_disable_device(pdev);
1454 return err;
1455}
1456
49ce9c2c 1457/**
452c1ce2
CS		 1458 * atl2_remove - Device Removal Routine
1459 * @pdev: PCI device information struct
1460 *
1461 * atl2_remove is called by the PCI subsystem to alert the driver
1462 * that it should release a PCI device. The could be caused by a
1463 * Hot-Plug event, or because the driver is going to be removed from
1464 * memory.
1465 */
1466/* FIXME: write the original MAC address back in case it was changed from a
1467 * BIOS-set value, as in atl1 -- CHS */
093d369d 1468static void atl2_remove(struct pci_dev *pdev)
452c1ce2
CS		 1469{
1470 struct net_device *netdev = pci_get_drvdata(pdev);
1471 struct atl2_adapter *adapter = netdev_priv(netdev);
1472
1473 /* flush_scheduled work may reschedule our watchdog task, so
1474 * explicitly disable watchdog tasks from being rescheduled */
1475 set_bit(__ATL2_DOWN, &adapter->flags);
1476
1477 del_timer_sync(&adapter->watchdog_timer);
1478 del_timer_sync(&adapter->phy_config_timer);
23f333a2
TH		 1479 cancel_work_sync(&adapter->reset_task);
1480 cancel_work_sync(&adapter->link_chg_task);
452c1ce2
CS		 1481
1482 unregister_netdev(netdev);
1483
1484 atl2_force_ps(&adapter->hw);
1485
1486 iounmap(adapter->hw.hw_addr);
1487 pci_release_regions(pdev);
1488
1489 free_netdev(netdev);
1490
1491 pci_disable_device(pdev);
1492}
1493
1494static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1495{
1496 struct net_device *netdev = pci_get_drvdata(pdev);
1497 struct atl2_adapter *adapter = netdev_priv(netdev);
1498 struct atl2_hw *hw = &adapter->hw;
1499 u16 speed, duplex;
1500 u32 ctrl = 0;
1501 u32 wufc = adapter->wol;
1502
1503#ifdef CONFIG_PM
1504 int retval = 0;
1505#endif
1506
1507 netif_device_detach(netdev);
1508
1509 if (netif_running(netdev)) {
1510 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1511 atl2_down(adapter);
1512 }
1513
1514#ifdef CONFIG_PM
1515 retval = pci_save_state(pdev);
1516 if (retval)
1517 return retval;
1518#endif
1519
1520 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1521 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1522 if (ctrl & BMSR_LSTATUS)
1523 wufc &= ~ATLX_WUFC_LNKC;
1524
1525 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1526 u32 ret_val;
1527 /* get current link speed & duplex */
1528 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1529 if (ret_val) {
1530 printk(KERN_DEBUG
1531 "%s: get speed&duplex error while suspend\n",
1532 atl2_driver_name);
1533 goto wol_dis;
1534 }
1535
1536 ctrl = 0;
1537
1538 /* turn on magic packet wol */
1539 if (wufc & ATLX_WUFC_MAG)
1540 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1541
1542 /* ignore Link Chg event when Link is up */
1543 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1544
1545 /* Config MAC CTRL Register */
1546 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1547 if (FULL_DUPLEX == adapter->link_duplex)
1548 ctrl |= MAC_CTRL_DUPLX;
1549 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1550 ctrl |= (((u32)adapter->hw.preamble_len &
1551 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1552 ctrl |= (((u32)(adapter->hw.retry_buf &
1553 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1554 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1555 if (wufc & ATLX_WUFC_MAG) {
1556 /* magic packet maybe Broadcast&multicast&Unicast */
1557 ctrl |= MAC_CTRL_BC_EN;
1558 }
1559
1560 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1561
1562 /* pcie patch */
1563 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1564 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1565 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1566 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1567 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1568 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1569
1570 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1571 goto suspend_exit;
1572 }
1573
1574 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1575 /* link is down, so only LINK CHG WOL event enable */
1576 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1577 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1578 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1579
1580 /* pcie patch */
1581 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1582 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1583 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1584 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1585 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1586 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1587
1588 hw->phy_configured = false; /* re-init PHY when resume */
1589
1590 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1591
1592 goto suspend_exit;
1593 }
1594
1595wol_dis:
1596 /* WOL disabled */
1597 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1598
1599 /* pcie patch */
1600 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1601 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1602 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1603 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1604 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1605 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1606
1607 atl2_force_ps(hw);
1608 hw->phy_configured = false; /* re-init PHY when resume */
1609
1610 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1611
1612suspend_exit:
1613 if (netif_running(netdev))
1614 atl2_free_irq(adapter);
1615
1616 pci_disable_device(pdev);
1617
1618 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1619
1620 return 0;
1621}
1622
1623#ifdef CONFIG_PM
1624static int atl2_resume(struct pci_dev *pdev)
1625{
1626 struct net_device *netdev = pci_get_drvdata(pdev);
1627 struct atl2_adapter *adapter = netdev_priv(netdev);
1628 u32 err;
1629
1630 pci_set_power_state(pdev, PCI_D0);
1631 pci_restore_state(pdev);
1632
1633 err = pci_enable_device(pdev);
1634 if (err) {
1635 printk(KERN_ERR
1636 "atl2: Cannot enable PCI device from suspend\n");
1637 return err;
1638 }
1639
1640 pci_set_master(pdev);
1641
1642 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1643
1644 pci_enable_wake(pdev, PCI_D3hot, 0);
1645 pci_enable_wake(pdev, PCI_D3cold, 0);
1646
1647 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1648
a849854f
AJ		 1649 if (netif_running(netdev)) {
1650 err = atl2_request_irq(adapter);
1651 if (err)
1652 return err;
1653 }
452c1ce2
CS		 1654
1655 atl2_reset_hw(&adapter->hw);
1656
1657 if (netif_running(netdev))
1658 atl2_up(adapter);
1659
1660 netif_device_attach(netdev);
1661
1662 return 0;
1663}
1664#endif
1665
1666static void atl2_shutdown(struct pci_dev *pdev)
1667{
1668 atl2_suspend(pdev, PMSG_SUSPEND);
1669}
1670
1671static struct pci_driver atl2_driver = {
1672 .name = atl2_driver_name,
1673 .id_table = atl2_pci_tbl,
1674 .probe = atl2_probe,
093d369d 1675 .remove = atl2_remove,
25985edc 1676 /* Power Management Hooks */
452c1ce2
CS		 1677 .suspend = atl2_suspend,
1678#ifdef CONFIG_PM
1679 .resume = atl2_resume,
1680#endif
1681 .shutdown = atl2_shutdown,
1682};
1683
49ce9c2c 1684/**
452c1ce2
CS		 1685 * atl2_init_module - Driver Registration Routine
1686 *
1687 * atl2_init_module is the first routine called when the driver is
1688 * loaded. All it does is register with the PCI subsystem.
1689 */
1690static int __init atl2_init_module(void)
1691{
1692 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1693 atl2_driver_version);
1694 printk(KERN_INFO "%s\n", atl2_copyright);
1695 return pci_register_driver(&atl2_driver);
1696}
1697module_init(atl2_init_module);
1698
49ce9c2c 1699/**
452c1ce2
CS		 1700 * atl2_exit_module - Driver Exit Cleanup Routine
1701 *
1702 * atl2_exit_module is called just before the driver is removed
1703 * from memory.
1704 */
1705static void __exit atl2_exit_module(void)
1706{
1707 pci_unregister_driver(&atl2_driver);
1708}
1709module_exit(atl2_exit_module);
1710
1711static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1712{
1713 struct atl2_adapter *adapter = hw->back;
1714 pci_read_config_word(adapter->pdev, reg, value);
1715}
1716
1717static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1718{
1719 struct atl2_adapter *adapter = hw->back;
1720 pci_write_config_word(adapter->pdev, reg, *value);
1721}
1722
a7888596
PR		 1723static int atl2_get_link_ksettings(struct net_device *netdev,
1724 struct ethtool_link_ksettings *cmd)
452c1ce2
CS		 1725{
1726 struct atl2_adapter *adapter = netdev_priv(netdev);
1727 struct atl2_hw *hw = &adapter->hw;
a7888596 1728 u32 supported, advertising;
452c1ce2 1729
a7888596 1730 supported = (SUPPORTED_10baseT_Half |
452c1ce2
CS		 1731 SUPPORTED_10baseT_Full |
1732 SUPPORTED_100baseT_Half |
1733 SUPPORTED_100baseT_Full |
1734 SUPPORTED_Autoneg |
1735 SUPPORTED_TP);
a7888596 1736 advertising = ADVERTISED_TP;
452c1ce2 1737
a7888596
PR		 1738 advertising |= ADVERTISED_Autoneg;
1739 advertising |= hw->autoneg_advertised;
452c1ce2 1740
a7888596
PR		 1741 cmd->base.port = PORT_TP;
1742 cmd->base.phy_address = 0;
452c1ce2
CS		 1743
1744 if (adapter->link_speed != SPEED_0) {
a7888596 1745 cmd->base.speed = adapter->link_speed;
452c1ce2 1746 if (adapter->link_duplex == FULL_DUPLEX)
a7888596 1747 cmd->base.duplex = DUPLEX_FULL;
452c1ce2 1748 else
a7888596 1749 cmd->base.duplex = DUPLEX_HALF;
452c1ce2 1750 } else {
a7888596
PR		 1751 cmd->base.speed = SPEED_UNKNOWN;
1752 cmd->base.duplex = DUPLEX_UNKNOWN;
452c1ce2
CS		 1753 }
1754
a7888596
PR		 1755 cmd->base.autoneg = AUTONEG_ENABLE;
1756
1757 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1758 supported);
1759 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1760 advertising);
1761
452c1ce2
CS		 1762 return 0;
1763}
1764
a7888596
PR		 1765static int atl2_set_link_ksettings(struct net_device *netdev,
1766 const struct ethtool_link_ksettings *cmd)
452c1ce2
CS		 1767{
1768 struct atl2_adapter *adapter = netdev_priv(netdev);
1769 struct atl2_hw *hw = &adapter->hw;
a7888596
PR		 1770 u32 advertising;
1771
1772 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1773 cmd->link_modes.advertising);
452c1ce2
CS		 1774
1775 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1776 msleep(1);
1777
a7888596 1778 if (cmd->base.autoneg == AUTONEG_ENABLE) {
452c1ce2
CS		 1779#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1780 ADVERTISE_10_FULL | \
1781 ADVERTISE_100_HALF| \
1782 ADVERTISE_100_FULL)
1783
a7888596 1784 if ((advertising & MY_ADV_MASK) == MY_ADV_MASK) {
452c1ce2
CS		 1785 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1786 hw->autoneg_advertised = MY_ADV_MASK;
a7888596 1787 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_FULL) {
452c1ce2
CS		 1788 hw->MediaType = MEDIA_TYPE_100M_FULL;
1789 hw->autoneg_advertised = ADVERTISE_100_FULL;
a7888596 1790 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_100_HALF) {
452c1ce2
CS		 1791 hw->MediaType = MEDIA_TYPE_100M_HALF;
1792 hw->autoneg_advertised = ADVERTISE_100_HALF;
a7888596 1793 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_FULL) {
452c1ce2
CS		 1794 hw->MediaType = MEDIA_TYPE_10M_FULL;
1795 hw->autoneg_advertised = ADVERTISE_10_FULL;
a7888596 1796 } else if ((advertising & MY_ADV_MASK) == ADVERTISE_10_HALF) {
452c1ce2
CS		 1797 hw->MediaType = MEDIA_TYPE_10M_HALF;
1798 hw->autoneg_advertised = ADVERTISE_10_HALF;
1799 } else {
1800 clear_bit(__ATL2_RESETTING, &adapter->flags);
1801 return -EINVAL;
1802 }
a7888596 1803 advertising = hw->autoneg_advertised |
452c1ce2
CS		 1804 ADVERTISED_TP | ADVERTISED_Autoneg;
1805 } else {
1806 clear_bit(__ATL2_RESETTING, &adapter->flags);
1807 return -EINVAL;
1808 }
1809
1810 /* reset the link */
1811 if (netif_running(adapter->netdev)) {
1812 atl2_down(adapter);
1813 atl2_up(adapter);
1814 } else
1815 atl2_reset_hw(&adapter->hw);
1816
1817 clear_bit(__ATL2_RESETTING, &adapter->flags);
1818 return 0;
1819}
1820
452c1ce2
CS		 1821static u32 atl2_get_msglevel(struct net_device *netdev)
1822{
1823 return 0;
1824}
1825
1826/*
1827 * It's sane for this to be empty, but we might want to take advantage of this.
1828 */
1829static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1830{
1831}
1832
1833static int atl2_get_regs_len(struct net_device *netdev)
1834{
1835#define ATL2_REGS_LEN 42
1836 return sizeof(u32) * ATL2_REGS_LEN;
1837}
1838
1839static void atl2_get_regs(struct net_device *netdev,
1840 struct ethtool_regs *regs, void *p)
1841{
1842 struct atl2_adapter *adapter = netdev_priv(netdev);
1843 struct atl2_hw *hw = &adapter->hw;
1844 u32 *regs_buff = p;
1845 u16 phy_data;
1846
1847 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1848
1849 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1850
1851 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1852 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1853 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1854 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1855 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1856 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1857 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1858 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1859 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1860 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1861 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1862 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1863 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1864 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1865 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1866 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1867 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1868 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1869 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1870 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1871 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1872 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1873 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1874 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1875 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1876 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1877 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1878 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1879 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1880 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1881 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1882 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1883 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1884 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1885 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1886 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1887 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1888 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1889 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1890
1891 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1892 regs_buff[40] = (u32)phy_data;
1893 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1894 regs_buff[41] = (u32)phy_data;
1895}
1896
1897static int atl2_get_eeprom_len(struct net_device *netdev)
1898{
1899 struct atl2_adapter *adapter = netdev_priv(netdev);
1900
1901 if (!atl2_check_eeprom_exist(&adapter->hw))
1902 return 512;
1903 else
1904 return 0;
1905}
1906
1907static int atl2_get_eeprom(struct net_device *netdev,
1908 struct ethtool_eeprom *eeprom, u8 *bytes)
1909{
1910 struct atl2_adapter *adapter = netdev_priv(netdev);
1911 struct atl2_hw *hw = &adapter->hw;
1912 u32 *eeprom_buff;
1913 int first_dword, last_dword;
1914 int ret_val = 0;
1915 int i;
1916
1917 if (eeprom->len == 0)
1918 return -EINVAL;
1919
1920 if (atl2_check_eeprom_exist(hw))
1921 return -EINVAL;
1922
1923 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1924
1925 first_dword = eeprom->offset >> 2;
1926 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1927
6da2ec56
KC		 1928 eeprom_buff = kmalloc_array(last_dword - first_dword + 1, sizeof(u32),
1929 GFP_KERNEL);
452c1ce2
CS		 1930 if (!eeprom_buff)
1931 return -ENOMEM;
1932
1933 for (i = first_dword; i < last_dword; i++) {
2467ab95
JS		 1934 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) {
1935 ret_val = -EIO;
1936 goto free;
1937 }
452c1ce2
CS		 1938 }
1939
1940 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1941 eeprom->len);
2467ab95 1942free:
452c1ce2
CS		 1943 kfree(eeprom_buff);
1944
1945 return ret_val;
1946}
1947
1948static int atl2_set_eeprom(struct net_device *netdev,
1949 struct ethtool_eeprom *eeprom, u8 *bytes)
1950{
1951 struct atl2_adapter *adapter = netdev_priv(netdev);
1952 struct atl2_hw *hw = &adapter->hw;
1953 u32 *eeprom_buff;
1954 u32 *ptr;
1955 int max_len, first_dword, last_dword, ret_val = 0;
1956 int i;
1957
1958 if (eeprom->len == 0)
1959 return -EOPNOTSUPP;
1960
1961 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1962 return -EFAULT;
1963
1964 max_len = 512;
1965
1966 first_dword = eeprom->offset >> 2;
1967 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1968 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1969 if (!eeprom_buff)
1970 return -ENOMEM;
1971
ad19031b 1972 ptr = eeprom_buff;
452c1ce2
CS		 1973
1974 if (eeprom->offset & 3) {
1975 /* need read/modify/write of first changed EEPROM word */
1976 /* only the second byte of the word is being modified */
ad19031b
JJ		 1977 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) {
1978 ret_val = -EIO;
1979 goto out;
1980 }
452c1ce2
CS		 1981 ptr++;
1982 }
1983 if (((eeprom->offset + eeprom->len) & 3)) {
1984 /*
1985 * need read/modify/write of last changed EEPROM word
1986 * only the first byte of the word is being modified
1987 */
1988 if (!atl2_read_eeprom(hw, last_dword * 4,
ad19031b
JJ		 1989 &(eeprom_buff[last_dword - first_dword]))) {
1990 ret_val = -EIO;
1991 goto out;
1992 }
452c1ce2
CS		 1993 }
1994
1995 /* Device's eeprom is always little-endian, word addressable */
1996 memcpy(ptr, bytes, eeprom->len);
1997
1998 for (i = 0; i < last_dword - first_dword + 1; i++) {
ad19031b
JJ		 1999 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) {
2000 ret_val = -EIO;
2001 goto out;
2002 }
452c1ce2 2003 }
ad19031b 2004 out:
452c1ce2
CS		 2005 kfree(eeprom_buff);
2006 return ret_val;
2007}
2008
2009static void atl2_get_drvinfo(struct net_device *netdev,
2010 struct ethtool_drvinfo *drvinfo)
2011{
2012 struct atl2_adapter *adapter = netdev_priv(netdev);
2013
68aad78c
RJ		 2014 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver));
2015 strlcpy(drvinfo->version, atl2_driver_version,
2016 sizeof(drvinfo->version));
2017 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version));
2018 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
2019 sizeof(drvinfo->bus_info));
452c1ce2
CS		 2020}
2021
2022static void atl2_get_wol(struct net_device *netdev,
2023 struct ethtool_wolinfo *wol)
2024{
2025 struct atl2_adapter *adapter = netdev_priv(netdev);
2026
2027 wol->supported = WAKE_MAGIC;
2028 wol->wolopts = 0;
2029
2030 if (adapter->wol & ATLX_WUFC_EX)
2031 wol->wolopts |= WAKE_UCAST;
2032 if (adapter->wol & ATLX_WUFC_MC)
2033 wol->wolopts |= WAKE_MCAST;
2034 if (adapter->wol & ATLX_WUFC_BC)
2035 wol->wolopts |= WAKE_BCAST;
2036 if (adapter->wol & ATLX_WUFC_MAG)
2037 wol->wolopts |= WAKE_MAGIC;
2038 if (adapter->wol & ATLX_WUFC_LNKC)
2039 wol->wolopts |= WAKE_PHY;
2040}
2041
2042static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2043{
2044 struct atl2_adapter *adapter = netdev_priv(netdev);
2045
2046 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2047 return -EOPNOTSUPP;
2048
41796e91 2049 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
452c1ce2
CS		 2050 return -EOPNOTSUPP;
2051
2052 /* these settings will always override what we currently have */
2053 adapter->wol = 0;
2054
2055 if (wol->wolopts & WAKE_MAGIC)
2056 adapter->wol |= ATLX_WUFC_MAG;
2057 if (wol->wolopts & WAKE_PHY)
2058 adapter->wol |= ATLX_WUFC_LNKC;
2059
2060 return 0;
2061}
2062
2063static int atl2_nway_reset(struct net_device *netdev)
2064{
2065 struct atl2_adapter *adapter = netdev_priv(netdev);
2066 if (netif_running(netdev))
2067 atl2_reinit_locked(adapter);
2068 return 0;
2069}
2070
0fc0b732 2071static const struct ethtool_ops atl2_ethtool_ops = {
452c1ce2
CS		 2072 .get_drvinfo = atl2_get_drvinfo,
2073 .get_regs_len = atl2_get_regs_len,
2074 .get_regs = atl2_get_regs,
2075 .get_wol = atl2_get_wol,
2076 .set_wol = atl2_set_wol,
2077 .get_msglevel = atl2_get_msglevel,
2078 .set_msglevel = atl2_set_msglevel,
2079 .nway_reset = atl2_nway_reset,
2080 .get_link = ethtool_op_get_link,
2081 .get_eeprom_len = atl2_get_eeprom_len,
2082 .get_eeprom = atl2_get_eeprom,
2083 .set_eeprom = atl2_set_eeprom,
a7888596
PR		 2084 .get_link_ksettings = atl2_get_link_ksettings,
2085 .set_link_ksettings = atl2_set_link_ksettings,
452c1ce2
CS		 2086};
2087
452c1ce2
CS		 2088#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2089 (((a) & 0xff00ff00) >> 8))
2090#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2091#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2092
2093/*
2094 * Reset the transmit and receive units; mask and clear all interrupts.
2095 *
2096 * hw - Struct containing variables accessed by shared code
2097 * return : 0 or idle status (if error)
2098 */
2099static s32 atl2_reset_hw(struct atl2_hw *hw)
2100{
2101 u32 icr;
2102 u16 pci_cfg_cmd_word;
2103 int i;
2104
2105 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2106 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2107 if ((pci_cfg_cmd_word &
2108 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2109 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2110 pci_cfg_cmd_word |=
2111 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2112 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2113 }
2114
2115 /* Clear Interrupt mask to stop board from generating
2116 * interrupts & Clear any pending interrupt events
2117 */
2118 /* FIXME */
2119 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2120 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2121
2122 /* Issue Soft Reset to the MAC. This will reset the chip's
2123 * transmit, receive, DMA. It will not effect
2124 * the current PCI configuration. The global reset bit is self-
2125 * clearing, and should clear within a microsecond.
2126 */
2127 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2128 wmb();
2129 msleep(1); /* delay about 1ms */
2130
2131 /* Wait at least 10ms for All module to be Idle */
2132 for (i = 0; i < 10; i++) {
2133 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2134 if (!icr)
2135 break;
2136 msleep(1); /* delay 1 ms */
2137 cpu_relax();
2138 }
2139
2140 if (icr)
2141 return icr;
2142
2143 return 0;
2144}
2145
2146#define CUSTOM_SPI_CS_SETUP 2
2147#define CUSTOM_SPI_CLK_HI 2
2148#define CUSTOM_SPI_CLK_LO 2
2149#define CUSTOM_SPI_CS_HOLD 2
2150#define CUSTOM_SPI_CS_HI 3
2151
2152static struct atl2_spi_flash_dev flash_table[] =
2153{
2154/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2155{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2156{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2157{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2158};
2159
2160static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2161{
2162 int i;
2163 u32 value;
2164
2165 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2166 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2167
2168 value = SPI_FLASH_CTRL_WAIT_READY |
2169 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2170 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2171 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2172 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2173 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2174 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2175 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2176 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2177 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2178 SPI_FLASH_CTRL_CS_HI_SHIFT |
2179 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2180
2181 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2182
2183 value |= SPI_FLASH_CTRL_START;
2184
2185 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2186
2187 for (i = 0; i < 10; i++) {
2188 msleep(1);
2189 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2190 if (!(value & SPI_FLASH_CTRL_START))
2191 break;
2192 }
2193
2194 if (value & SPI_FLASH_CTRL_START)
2195 return false;
2196
2197 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2198
2199 return true;
2200}
2201
2202/*
2203 * get_permanent_address
2204 * return 0 if get valid mac address,
2205 */
2206static int get_permanent_address(struct atl2_hw *hw)
2207{
2208 u32 Addr[2];
2209 u32 i, Control;
2210 u16 Register;
c81f2124 2211 u8 EthAddr[ETH_ALEN];
452c1ce2
CS		 2212 bool KeyValid;
2213
2214 if (is_valid_ether_addr(hw->perm_mac_addr))
2215 return 0;
2216
2217 Addr[0] = 0;
2218 Addr[1] = 0;
2219
2220 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2221 Register = 0;
2222 KeyValid = false;
2223
2224 /* Read out all EEPROM content */
2225 i = 0;
2226 while (1) {
2227 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2228 if (KeyValid) {
2229 if (Register == REG_MAC_STA_ADDR)
2230 Addr[0] = Control;
2231 else if (Register ==
2232 (REG_MAC_STA_ADDR + 4))
2233 Addr[1] = Control;
2234 KeyValid = false;
2235 } else if ((Control & 0xff) == 0x5A) {
2236 KeyValid = true;
2237 Register = (u16) (Control >> 16);
2238 } else {
2239 /* assume data end while encount an invalid KEYWORD */
2240 break;
2241 }
2242 } else {
2243 break; /* read error */
2244 }
2245 i += 4;
2246 }
2247
2248 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2249 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2250
2251 if (is_valid_ether_addr(EthAddr)) {
c81f2124 2252 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
452c1ce2
CS		 2253 return 0;
2254 }
2255 return 1;
2256 }
2257
2258 /* see if SPI flash exists? */
2259 Addr[0] = 0;
2260 Addr[1] = 0;
2261 Register = 0;
2262 KeyValid = false;
2263 i = 0;
2264 while (1) {
2265 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2266 if (KeyValid) {
2267 if (Register == REG_MAC_STA_ADDR)
2268 Addr[0] = Control;
2269 else if (Register == (REG_MAC_STA_ADDR + 4))
2270 Addr[1] = Control;
2271 KeyValid = false;
2272 } else if ((Control & 0xff) == 0x5A) {
2273 KeyValid = true;
2274 Register = (u16) (Control >> 16);
2275 } else {
2276 break; /* data end */
2277 }
2278 } else {
2279 break; /* read error */
2280 }
2281 i += 4;
2282 }
2283
2284 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2285 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2286 if (is_valid_ether_addr(EthAddr)) {
c81f2124 2287 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
452c1ce2
CS		 2288 return 0;
2289 }
2290 /* maybe MAC-address is from BIOS */
2291 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2292 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2293 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2294 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2295
2296 if (is_valid_ether_addr(EthAddr)) {
c81f2124 2297 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
452c1ce2
CS		 2298 return 0;
2299 }
2300
2301 return 1;
2302}
2303
2304/*
2305 * Reads the adapter's MAC address from the EEPROM
2306 *
2307 * hw - Struct containing variables accessed by shared code
2308 */
2309static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2310{
452c1ce2
CS		 2311 if (get_permanent_address(hw)) {
2312 /* for test */
7efd26d0 2313 /* FIXME: shouldn't we use eth_random_addr() here? */
452c1ce2
CS		 2314 hw->perm_mac_addr[0] = 0x00;
2315 hw->perm_mac_addr[1] = 0x13;
2316 hw->perm_mac_addr[2] = 0x74;
2317 hw->perm_mac_addr[3] = 0x00;
2318 hw->perm_mac_addr[4] = 0x5c;
2319 hw->perm_mac_addr[5] = 0x38;
2320 }
2321
c81f2124 2322 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN);
452c1ce2
CS		 2323
2324 return 0;
2325}
2326
2327/*
2328 * Hashes an address to determine its location in the multicast table
2329 *
2330 * hw - Struct containing variables accessed by shared code
2331 * mc_addr - the multicast address to hash
2332 *
2333 * atl2_hash_mc_addr
2334 * purpose
2335 * set hash value for a multicast address
2336 * hash calcu processing :
2337 * 1. calcu 32bit CRC for multicast address
2338 * 2. reverse crc with MSB to LSB
2339 */
2340static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2341{
2342 u32 crc32, value;
2343 int i;
2344
2345 value = 0;
2346 crc32 = ether_crc_le(6, mc_addr);
2347
2348 for (i = 0; i < 32; i++)
2349 value |= (((crc32 >> i) & 1) << (31 - i));
2350
2351 return value;
2352}
2353
2354/*
2355 * Sets the bit in the multicast table corresponding to the hash value.
2356 *
2357 * hw - Struct containing variables accessed by shared code
2358 * hash_value - Multicast address hash value
2359 */
2360static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2361{
2362 u32 hash_bit, hash_reg;
2363 u32 mta;
2364
2365 /* The HASH Table is a register array of 2 32-bit registers.
2366 * It is treated like an array of 64 bits. We want to set
2367 * bit BitArray[hash_value]. So we figure out what register
2368 * the bit is in, read it, OR in the new bit, then write
2369 * back the new value. The register is determined by the
2370 * upper 7 bits of the hash value and the bit within that
2371 * register are determined by the lower 5 bits of the value.
2372 */
2373 hash_reg = (hash_value >> 31) & 0x1;
2374 hash_bit = (hash_value >> 26) & 0x1F;
2375
2376 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2377
2378 mta |= (1 << hash_bit);
2379
2380 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2381}
2382
2383/*
2384 * atl2_init_pcie - init PCIE module
2385 */
2386static void atl2_init_pcie(struct atl2_hw *hw)
2387{
2388 u32 value;
2389 value = LTSSM_TEST_MODE_DEF;
2390 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2391
2392 value = PCIE_DLL_TX_CTRL1_DEF;
2393 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2394}
2395
2396static void atl2_init_flash_opcode(struct atl2_hw *hw)
2397{
2398 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2399 hw->flash_vendor = 0; /* ATMEL */
2400
2401 /* Init OP table */
2402 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2403 flash_table[hw->flash_vendor].cmdPROGRAM);
2404 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2405 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2406 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2407 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2408 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2409 flash_table[hw->flash_vendor].cmdRDID);
2410 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2411 flash_table[hw->flash_vendor].cmdWREN);
2412 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2413 flash_table[hw->flash_vendor].cmdRDSR);
2414 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2415 flash_table[hw->flash_vendor].cmdWRSR);
2416 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2417 flash_table[hw->flash_vendor].cmdREAD);
2418}
2419
2420/********************************************************************
2421* Performs basic configuration of the adapter.
2422*
2423* hw - Struct containing variables accessed by shared code
2424* Assumes that the controller has previously been reset and is in a
2425* post-reset uninitialized state. Initializes multicast table,
2426* and Calls routines to setup link
2427* Leaves the transmit and receive units disabled and uninitialized.
2428********************************************************************/
2429static s32 atl2_init_hw(struct atl2_hw *hw)
2430{
2431 u32 ret_val = 0;
2432
2433 atl2_init_pcie(hw);
2434
2435 /* Zero out the Multicast HASH table */
2436 /* clear the old settings from the multicast hash table */
2437 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2438 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2439
2440 atl2_init_flash_opcode(hw);
2441
2442 ret_val = atl2_phy_init(hw);
2443
2444 return ret_val;
2445}
2446
2447/*
2448 * Detects the current speed and duplex settings of the hardware.
2449 *
2450 * hw - Struct containing variables accessed by shared code
2451 * speed - Speed of the connection
2452 * duplex - Duplex setting of the connection
2453 */
2454static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2455 u16 *duplex)
2456{
2457 s32 ret_val;
2458 u16 phy_data;
2459
2460 /* Read PHY Specific Status Register (17) */
2461 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2462 if (ret_val)
2463 return ret_val;
2464
2465 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2466 return ATLX_ERR_PHY_RES;
2467
2468 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2469 case MII_ATLX_PSSR_100MBS:
2470 *speed = SPEED_100;
2471 break;
2472 case MII_ATLX_PSSR_10MBS:
2473 *speed = SPEED_10;
2474 break;
2475 default:
2476 return ATLX_ERR_PHY_SPEED;
452c1ce2
CS		 2477 }
2478
2479 if (phy_data & MII_ATLX_PSSR_DPLX)
2480 *duplex = FULL_DUPLEX;
2481 else
2482 *duplex = HALF_DUPLEX;
2483
2484 return 0;
2485}
2486
2487/*
2488 * Reads the value from a PHY register
2489 * hw - Struct containing variables accessed by shared code
2490 * reg_addr - address of the PHY register to read
2491 */
2492static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2493{
2494 u32 val;
2495 int i;
2496
2497 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2498 MDIO_START |
2499 MDIO_SUP_PREAMBLE |
2500 MDIO_RW |
2501 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2502 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2503
2504 wmb();
2505
2506 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2507 udelay(2);
2508 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2509 if (!(val & (MDIO_START | MDIO_BUSY)))
2510 break;
2511 wmb();
2512 }
2513 if (!(val & (MDIO_START | MDIO_BUSY))) {
2514 *phy_data = (u16)val;
2515 return 0;
2516 }
2517
2518 return ATLX_ERR_PHY;
2519}
2520
2521/*
2522 * Writes a value to a PHY register
2523 * hw - Struct containing variables accessed by shared code
2524 * reg_addr - address of the PHY register to write
2525 * data - data to write to the PHY
2526 */
2527static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2528{
2529 int i;
2530 u32 val;
2531
2532 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2533 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2534 MDIO_SUP_PREAMBLE |
2535 MDIO_START |
2536 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2537 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2538
2539 wmb();
2540
2541 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2542 udelay(2);
2543 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2544 if (!(val & (MDIO_START | MDIO_BUSY)))
2545 break;
2546
2547 wmb();
2548 }
2549
2550 if (!(val & (MDIO_START | MDIO_BUSY)))
2551 return 0;
2552
2553 return ATLX_ERR_PHY;
2554}
2555
2556/*
2557 * Configures PHY autoneg and flow control advertisement settings
2558 *
2559 * hw - Struct containing variables accessed by shared code
2560 */
2561static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2562{
2563 s32 ret_val;
2564 s16 mii_autoneg_adv_reg;
2565
2566 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2567 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2568
2569 /* Need to parse autoneg_advertised and set up
2570 * the appropriate PHY registers. First we will parse for
2571 * autoneg_advertised software override. Since we can advertise
2572 * a plethora of combinations, we need to check each bit
2573 * individually.
2574 */
2575
2576 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2577 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2578 * the 1000Base-T Control Register (Address 9). */
2579 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2580
2581 /* Need to parse MediaType and setup the
2582 * appropriate PHY registers. */
2583 switch (hw->MediaType) {
2584 case MEDIA_TYPE_AUTO_SENSOR:
2585 mii_autoneg_adv_reg |=
2586 (MII_AR_10T_HD_CAPS |
2587 MII_AR_10T_FD_CAPS |
2588 MII_AR_100TX_HD_CAPS|
2589 MII_AR_100TX_FD_CAPS);
2590 hw->autoneg_advertised =
2591 ADVERTISE_10_HALF |
2592 ADVERTISE_10_FULL |
2593 ADVERTISE_100_HALF|
2594 ADVERTISE_100_FULL;
2595 break;
2596 case MEDIA_TYPE_100M_FULL:
2597 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2598 hw->autoneg_advertised = ADVERTISE_100_FULL;
2599 break;
2600 case MEDIA_TYPE_100M_HALF:
2601 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2602 hw->autoneg_advertised = ADVERTISE_100_HALF;
2603 break;
2604 case MEDIA_TYPE_10M_FULL:
2605 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2606 hw->autoneg_advertised = ADVERTISE_10_FULL;
2607 break;
2608 default:
2609 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2610 hw->autoneg_advertised = ADVERTISE_10_HALF;
2611 break;
2612 }
2613
2614 /* flow control fixed to enable all */
2615 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2616
2617 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2618
2619 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2620
2621 if (ret_val)
2622 return ret_val;
2623
2624 return 0;
2625}
2626
2627/*
2628 * Resets the PHY and make all config validate
2629 *
2630 * hw - Struct containing variables accessed by shared code
2631 *
2632 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2633 */
2634static s32 atl2_phy_commit(struct atl2_hw *hw)
2635{
2636 s32 ret_val;
2637 u16 phy_data;
2638
2639 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2640 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2641 if (ret_val) {
2642 u32 val;
2643 int i;
2644 /* pcie serdes link may be down ! */
2645 for (i = 0; i < 25; i++) {
2646 msleep(1);
2647 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2648 if (!(val & (MDIO_START | MDIO_BUSY)))
2649 break;
2650 }
2651
2652 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2653 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2654 return ret_val;
2655 }
2656 }
2657 return 0;
2658}
2659
2660static s32 atl2_phy_init(struct atl2_hw *hw)
2661{
2662 s32 ret_val;
2663 u16 phy_val;
2664
2665 if (hw->phy_configured)
2666 return 0;
2667
2668 /* Enable PHY */
2669 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2670 ATL2_WRITE_FLUSH(hw);
2671 msleep(1);
2672
2673 /* check if the PHY is in powersaving mode */
2674 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2675 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2676
2677 /* 024E / 124E 0r 0274 / 1274 ? */
2678 if (phy_val & 0x1000) {
2679 phy_val &= ~0x1000;
2680 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2681 }
2682
2683 msleep(1);
2684
2685 /*Enable PHY LinkChange Interrupt */
2686 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2687 if (ret_val)
2688 return ret_val;
2689
2690 /* setup AutoNeg parameters */
2691 ret_val = atl2_phy_setup_autoneg_adv(hw);
2692 if (ret_val)
2693 return ret_val;
2694
2695 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2696 ret_val = atl2_phy_commit(hw);
2697 if (ret_val)
2698 return ret_val;
2699
2700 hw->phy_configured = true;
2701
2702 return ret_val;
2703}
2704
2705static void atl2_set_mac_addr(struct atl2_hw *hw)
2706{
2707 u32 value;
2708 /* 00-0B-6A-F6-00-DC
2709 * 0: 6AF600DC 1: 000B
2710 * low dword */
2711 value = (((u32)hw->mac_addr[2]) << 24) |
2712 (((u32)hw->mac_addr[3]) << 16) |
2713 (((u32)hw->mac_addr[4]) << 8) |
2714 (((u32)hw->mac_addr[5]));
2715 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2716 /* hight dword */
2717 value = (((u32)hw->mac_addr[0]) << 8) |
2718 (((u32)hw->mac_addr[1]));
2719 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2720}
2721
2722/*
2723 * check_eeprom_exist
2724 * return 0 if eeprom exist
2725 */
2726static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2727{
2728 u32 value;
2729
2730 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2731 if (value & SPI_FLASH_CTRL_EN_VPD) {
2732 value &= ~SPI_FLASH_CTRL_EN_VPD;
2733 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2734 }
2735 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2736 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2737}
2738
2739/* FIXME: This doesn't look right. -- CHS */
2740static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2741{
2742 return true;
2743}
2744
2745static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2746{
2747 int i;
2748 u32 Control;
2749
2750 if (Offset & 0x3)
2751 return false; /* address do not align */
2752
2753 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2754 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2755 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2756
2757 for (i = 0; i < 10; i++) {
2758 msleep(2);
2759 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2760 if (Control & VPD_CAP_VPD_FLAG)
2761 break;
2762 }
2763
2764 if (Control & VPD_CAP_VPD_FLAG) {
2765 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2766 return true;
2767 }
2768 return false; /* timeout */
2769}
2770
2771static void atl2_force_ps(struct atl2_hw *hw)
2772{
2773 u16 phy_val;
2774
2775 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2776 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2777 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2778
2779 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2780 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2781 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2782 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2783}
2784
2785/* This is the only thing that needs to be changed to adjust the
2786 * maximum number of ports that the driver can manage.
2787 */
2788#define ATL2_MAX_NIC 4
2789
2790#define OPTION_UNSET -1
2791#define OPTION_DISABLED 0
2792#define OPTION_ENABLED 1
2793
2794/* All parameters are treated the same, as an integer array of values.
2795 * This macro just reduces the need to repeat the same declaration code
2796 * over and over (plus this helps to avoid typo bugs).
2797 */
2798#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2799#ifndef module_param_array
2800/* Module Parameters are always initialized to -1, so that the driver
2801 * can tell the difference between no user specified value or the
2802 * user asking for the default value.
2803 * The true default values are loaded in when atl2_check_options is called.
2804 *
2805 * This is a GCC extension to ANSI C.
2806 * See the item "Labeled Elements in Initializers" in the section
2807 * "Extensions to the C Language Family" of the GCC documentation.
2808 */
2809
2810#define ATL2_PARAM(X, desc) \
093d369d 2811 static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
452c1ce2
CS		 2812 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2813 MODULE_PARM_DESC(X, desc);
2814#else
2815#define ATL2_PARAM(X, desc) \
093d369d 2816 static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
b79d8fff 2817 static unsigned int num_##X; \
452c1ce2
CS		 2818 module_param_array_named(X, X, int, &num_##X, 0); \
2819 MODULE_PARM_DESC(X, desc);
2820#endif
2821
2822/*
2823 * Transmit Memory Size
2824 * Valid Range: 64-2048
2825 * Default Value: 128
2826 */
2827#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2828#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2829#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2830ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2831
2832/*
2833 * Receive Memory Block Count
2834 * Valid Range: 16-512
2835 * Default Value: 128
2836 */
2837#define ATL2_MIN_RXD_COUNT 16
2838#define ATL2_MAX_RXD_COUNT 512
2839#define ATL2_DEFAULT_RXD_COUNT 64
2840ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2841
2842/*
2843 * User Specified MediaType Override
2844 *
2845 * Valid Range: 0-5
2846 * - 0 - auto-negotiate at all supported speeds
2847 * - 1 - only link at 1000Mbps Full Duplex
2848 * - 2 - only link at 100Mbps Full Duplex
2849 * - 3 - only link at 100Mbps Half Duplex
2850 * - 4 - only link at 10Mbps Full Duplex
2851 * - 5 - only link at 10Mbps Half Duplex
2852 * Default Value: 0
2853 */
2854ATL2_PARAM(MediaType, "MediaType Select");
2855
2856/*
2857 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2858 * Valid Range: 10-65535
2859 * Default Value: 45000(90ms)
2860 */
2861#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2862#define INT_MOD_MAX_CNT 65000
2863#define INT_MOD_MIN_CNT 50
2864ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2865
2866/*
2867 * FlashVendor
2868 * Valid Range: 0-2
2869 * 0 - Atmel
2870 * 1 - SST
2871 * 2 - ST
2872 */
2873ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2874
2875#define AUTONEG_ADV_DEFAULT 0x2F
2876#define AUTONEG_ADV_MASK 0x2F
2877#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2878
2879#define FLASH_VENDOR_DEFAULT 0
2880#define FLASH_VENDOR_MIN 0
2881#define FLASH_VENDOR_MAX 2
2882
2883struct atl2_option {
2884 enum { enable_option, range_option, list_option } type;
2885 char *name;
2886 char *err;
2887 int def;
2888 union {
2889 struct { /* range_option info */
2890 int min;
2891 int max;
2892 } r;
2893 struct { /* list_option info */
2894 int nr;
2895 struct atl2_opt_list { int i; char *str; } *p;
2896 } l;
2897 } arg;
2898};
2899
093d369d 2900static int atl2_validate_option(int *value, struct atl2_option *opt)
452c1ce2
CS		 2901{
2902 int i;
2903 struct atl2_opt_list *ent;
2904
2905 if (*value == OPTION_UNSET) {
2906 *value = opt->def;
2907 return 0;
2908 }
2909
2910 switch (opt->type) {
2911 case enable_option:
2912 switch (*value) {
2913 case OPTION_ENABLED:
2914 printk(KERN_INFO "%s Enabled\n", opt->name);
2915 return 0;
452c1ce2
CS		 2916 case OPTION_DISABLED:
2917 printk(KERN_INFO "%s Disabled\n", opt->name);
2918 return 0;
452c1ce2
CS		 2919 }
2920 break;
2921 case range_option:
2922 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2923 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2924 return 0;
2925 }
2926 break;
2927 case list_option:
2928 for (i = 0; i < opt->arg.l.nr; i++) {
2929 ent = &opt->arg.l.p[i];
2930 if (*value == ent->i) {
2931 if (ent->str[0] != '\0')
2932 printk(KERN_INFO "%s\n", ent->str);
682a7895 2933 return 0;
452c1ce2
CS		 2934 }
2935 }
2936 break;
2937 default:
2938 BUG();
2939 }
2940
2941 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2942 opt->name, *value, opt->err);
2943 *value = opt->def;
2944 return -1;
2945}
2946
49ce9c2c 2947/**
452c1ce2
CS		 2948 * atl2_check_options - Range Checking for Command Line Parameters
2949 * @adapter: board private structure
2950 *
2951 * This routine checks all command line parameters for valid user
2952 * input. If an invalid value is given, or if no user specified
2953 * value exists, a default value is used. The final value is stored
2954 * in a variable in the adapter structure.
2955 */
093d369d 2956static void atl2_check_options(struct atl2_adapter *adapter)
452c1ce2
CS		 2957{
2958 int val;
2959 struct atl2_option opt;
2960 int bd = adapter->bd_number;
2961 if (bd >= ATL2_MAX_NIC) {
2962 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
2963 bd);
2964 printk(KERN_NOTICE "Using defaults for all values\n");
2965#ifndef module_param_array
2966 bd = ATL2_MAX_NIC;
2967#endif
2968 }
2969
2970 /* Bytes of Transmit Memory */
2971 opt.type = range_option;
2972 opt.name = "Bytes of Transmit Memory";
2973 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
2974 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
2975 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
2976 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
2977#ifdef module_param_array
2978 if (num_TxMemSize > bd) {
2979#endif
2980 val = TxMemSize[bd];
2981 atl2_validate_option(&val, &opt);
2982 adapter->txd_ring_size = ((u32) val) * 1024;
2983#ifdef module_param_array
2984 } else
2985 adapter->txd_ring_size = ((u32)opt.def) * 1024;
2986#endif
2987 /* txs ring size: */
2988 adapter->txs_ring_size = adapter->txd_ring_size / 128;
2989 if (adapter->txs_ring_size > 160)
2990 adapter->txs_ring_size = 160;
2991
2992 /* Receive Memory Block Count */
2993 opt.type = range_option;
2994 opt.name = "Number of receive memory block";
2995 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
2996 opt.def = ATL2_DEFAULT_RXD_COUNT;
2997 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
2998 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
2999#ifdef module_param_array
3000 if (num_RxMemBlock > bd) {
3001#endif
3002 val = RxMemBlock[bd];
3003 atl2_validate_option(&val, &opt);
3004 adapter->rxd_ring_size = (u32)val;
3005 /* FIXME */
3006 /* ((u16)val)&~1; */ /* even number */
3007#ifdef module_param_array
3008 } else
3009 adapter->rxd_ring_size = (u32)opt.def;
3010#endif
3011 /* init RXD Flow control value */
3012 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3013 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3014 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3015 (adapter->rxd_ring_size / 12);
3016
3017 /* Interrupt Moderate Timer */
3018 opt.type = range_option;
3019 opt.name = "Interrupt Moderate Timer";
3020 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3021 opt.def = INT_MOD_DEFAULT_CNT;
3022 opt.arg.r.min = INT_MOD_MIN_CNT;
3023 opt.arg.r.max = INT_MOD_MAX_CNT;
3024#ifdef module_param_array
3025 if (num_IntModTimer > bd) {
3026#endif
3027 val = IntModTimer[bd];
3028 atl2_validate_option(&val, &opt);
3029 adapter->imt = (u16) val;
3030#ifdef module_param_array
3031 } else
3032 adapter->imt = (u16)(opt.def);
3033#endif
3034 /* Flash Vendor */
3035 opt.type = range_option;
3036 opt.name = "SPI Flash Vendor";
3037 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3038 opt.def = FLASH_VENDOR_DEFAULT;
3039 opt.arg.r.min = FLASH_VENDOR_MIN;
3040 opt.arg.r.max = FLASH_VENDOR_MAX;
3041#ifdef module_param_array
3042 if (num_FlashVendor > bd) {
3043#endif
3044 val = FlashVendor[bd];
3045 atl2_validate_option(&val, &opt);
3046 adapter->hw.flash_vendor = (u8) val;
3047#ifdef module_param_array
3048 } else
3049 adapter->hw.flash_vendor = (u8)(opt.def);
3050#endif
3051 /* MediaType */
3052 opt.type = range_option;
3053 opt.name = "Speed/Duplex Selection";
3054 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3055 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3056 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3057 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3058#ifdef module_param_array
3059 if (num_MediaType > bd) {
3060#endif
3061 val = MediaType[bd];
3062 atl2_validate_option(&val, &opt);
3063 adapter->hw.MediaType = (u16) val;
3064#ifdef module_param_array
3065 } else
3066 adapter->hw.MediaType = (u16)(opt.def);
3067#endif
3068}
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