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bnx2x: Fix bnx2x_panic_dump for VFs
[thirdparty/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
33d8e6a5 30#include <linux/aer.h>
a2fbb9ea
ET		 31#include <linux/init.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/dma-mapping.h>
36#include <linux/bitops.h>
37#include <linux/irq.h>
38#include <linux/delay.h>
39#include <asm/byteorder.h>
40#include <linux/time.h>
41#include <linux/ethtool.h>
42#include <linux/mii.h>
0c6671b0 43#include <linux/if_vlan.h>
a2fbb9ea 44#include <net/ip.h>
619c5cb6 45#include <net/ipv6.h>
a2fbb9ea
ET		 46#include <net/tcp.h>
47#include <net/checksum.h>
34f80b04 48#include <net/ip6_checksum.h>
a2fbb9ea
ET		 49#include <linux/workqueue.h>
50#include <linux/crc32.h>
34f80b04 51#include <linux/crc32c.h>
a2fbb9ea
ET		 52#include <linux/prefetch.h>
53#include <linux/zlib.h>
a2fbb9ea 54#include <linux/io.h>
452427b0 55#include <linux/semaphore.h>
45229b42 56#include <linux/stringify.h>
7ab24bfd 57#include <linux/vmalloc.h>
a2fbb9ea 58
a2fbb9ea
ET		 59#include "bnx2x.h"
60#include "bnx2x_init.h"
94a78b79 61#include "bnx2x_init_ops.h"
9f6c9258 62#include "bnx2x_cmn.h"
1ab4434c 63#include "bnx2x_vfpf.h"
e4901dde 64#include "bnx2x_dcb.h"
042181f5 65#include "bnx2x_sp.h"
a2fbb9ea 66
94a78b79
VZ		 67#include <linux/firmware.h>
68#include "bnx2x_fw_file_hdr.h"
69/* FW files */
45229b42
BH		 70#define FW_FILE_VERSION \
71 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
72 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
73 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
74 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 75#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
76#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 77#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 78
34f80b04
EG		 79/* Time in jiffies before concluding the transmitter is hung */
80#define TX_TIMEOUT (5*HZ)
a2fbb9ea 81
0329aba1 82static char version[] =
619c5cb6 83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85
24e3fcef 86MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 87MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
a2fbb9ea
ET		 91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 93MODULE_FIRMWARE(FW_FILE_NAME_E1);
94MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 95MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 96
a8f47eb7 97int bnx2x_num_queues;
1c8bb760 98module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
96305234
DK		 99MODULE_PARM_DESC(num_queues,
100 " Set number of queues (default is as a number of CPUs)");
555f6c78 101
19680c48 102static int disable_tpa;
1c8bb760 103module_param(disable_tpa, int, S_IRUGO);
9898f86d 104MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 105
a8f47eb7 106static int int_mode;
1c8bb760 107module_param(int_mode, int, S_IRUGO);
619c5cb6 108MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 109 "(1 INT#x; 2 MSI)");
8badd27a 110
a18f5128 111static int dropless_fc;
1c8bb760 112module_param(dropless_fc, int, S_IRUGO);
a18f5128
EG		 113MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114
8d5726c4 115static int mrrs = -1;
1c8bb760 116module_param(mrrs, int, S_IRUGO);
8d5726c4
EG		 117MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
9898f86d 119static int debug;
1c8bb760 120module_param(debug, int, S_IRUGO);
9898f86d
EG		 121MODULE_PARM_DESC(debug, " Default debug msglevel");
122
619c5cb6 123struct workqueue_struct *bnx2x_wq;
ec6ba945 124
1ef1d45a
BW		 125struct bnx2x_mac_vals {
126 u32 xmac_addr;
127 u32 xmac_val;
128 u32 emac_addr;
129 u32 emac_val;
130 u32 umac_addr;
131 u32 umac_val;
132 u32 bmac_addr;
133 u32 bmac_val[2];
134};
135
a2fbb9ea
ET		 136enum bnx2x_board_type {
137 BCM57710 = 0,
619c5cb6
VZ		 138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
1ab4434c 142 BCM57712_VF,
619c5cb6
VZ		 143 BCM57800,
144 BCM57800_MF,
1ab4434c 145 BCM57800_VF,
619c5cb6
VZ		 146 BCM57810,
147 BCM57810_MF,
1ab4434c 148 BCM57810_VF,
c3def943
YM		 149 BCM57840_4_10,
150 BCM57840_2_20,
7e8e02df 151 BCM57840_MF,
1ab4434c 152 BCM57840_VF,
7e8e02df 153 BCM57811,
1ab4434c
AE		 154 BCM57811_MF,
155 BCM57840_O,
156 BCM57840_MFO,
157 BCM57811_VF
a2fbb9ea
ET		 158};
159
34f80b04 160/* indexed by board_type, above */
53a10565 161static struct {
a2fbb9ea 162 char *name;
0329aba1 163} board_info[] = {
1ab4434c
AE		 164 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
165 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
166 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
167 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
168 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
169 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
170 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
171 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
172 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
173 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
174 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
175 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
176 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
177 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
178 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
179 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
180 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
181 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
182 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
183 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
184 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 185};
186
619c5cb6
VZ		 187#ifndef PCI_DEVICE_ID_NX2_57710
188#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
189#endif
190#ifndef PCI_DEVICE_ID_NX2_57711
191#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
192#endif
193#ifndef PCI_DEVICE_ID_NX2_57711E
194#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
195#endif
196#ifndef PCI_DEVICE_ID_NX2_57712
197#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
198#endif
199#ifndef PCI_DEVICE_ID_NX2_57712_MF
200#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
201#endif
8395be5e
AE		 202#ifndef PCI_DEVICE_ID_NX2_57712_VF
203#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
204#endif
619c5cb6
VZ		 205#ifndef PCI_DEVICE_ID_NX2_57800
206#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
207#endif
208#ifndef PCI_DEVICE_ID_NX2_57800_MF
209#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
210#endif
8395be5e
AE		 211#ifndef PCI_DEVICE_ID_NX2_57800_VF
212#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
213#endif
619c5cb6
VZ		 214#ifndef PCI_DEVICE_ID_NX2_57810
215#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
216#endif
217#ifndef PCI_DEVICE_ID_NX2_57810_MF
218#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
219#endif
c3def943
YM		 220#ifndef PCI_DEVICE_ID_NX2_57840_O
221#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
222#endif
8395be5e
AE		 223#ifndef PCI_DEVICE_ID_NX2_57810_VF
224#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
225#endif
c3def943
YM		 226#ifndef PCI_DEVICE_ID_NX2_57840_4_10
227#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
228#endif
229#ifndef PCI_DEVICE_ID_NX2_57840_2_20
230#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
231#endif
232#ifndef PCI_DEVICE_ID_NX2_57840_MFO
233#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 234#endif
235#ifndef PCI_DEVICE_ID_NX2_57840_MF
236#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
237#endif
8395be5e
AE		 238#ifndef PCI_DEVICE_ID_NX2_57840_VF
239#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
240#endif
7e8e02df
BW		 241#ifndef PCI_DEVICE_ID_NX2_57811
242#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
243#endif
244#ifndef PCI_DEVICE_ID_NX2_57811_MF
245#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
246#endif
8395be5e
AE		 247#ifndef PCI_DEVICE_ID_NX2_57811_VF
248#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
249#endif
250
a3aa1884 251static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 273 { 0 }
274};
275
276MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
277
452427b0
YM		 278/* Global resources for unloading a previously loaded device */
279#define BNX2X_PREV_WAIT_NEEDED 1
280static DEFINE_SEMAPHORE(bnx2x_prev_sem);
281static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 282
283/* Forward declaration */
284static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
285static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
286static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
287
a2fbb9ea
ET		 288/****************************************************************************
289* General service functions
290****************************************************************************/
291
1191cb83 292static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 293 u32 addr, dma_addr_t mapping)
294{
295 REG_WR(bp, addr, U64_LO(mapping));
296 REG_WR(bp, addr + 4, U64_HI(mapping));
297}
298
1191cb83
ED		 299static void storm_memset_spq_addr(struct bnx2x *bp,
300 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 301{
302 u32 addr = XSEM_REG_FAST_MEMORY +
303 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
304
305 __storm_memset_dma_mapping(bp, addr, mapping);
306}
307
1191cb83
ED		 308static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
309 u16 pf_id)
523224a3 310{
619c5cb6
VZ		 311 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
312 pf_id);
313 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
314 pf_id);
315 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
316 pf_id);
317 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
318 pf_id);
523224a3
DK		 319}
320
1191cb83
ED		 321static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
322 u8 enable)
619c5cb6
VZ		 323{
324 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
325 enable);
326 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
327 enable);
328 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
329 enable);
330 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
331 enable);
332}
523224a3 333
1191cb83
ED		 334static void storm_memset_eq_data(struct bnx2x *bp,
335 struct event_ring_data *eq_data,
523224a3
DK		 336 u16 pfid)
337{
338 size_t size = sizeof(struct event_ring_data);
339
340 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
341
342 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
343}
344
1191cb83
ED		 345static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
346 u16 pfid)
523224a3
DK		 347{
348 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
349 REG_WR16(bp, addr, eq_prod);
350}
351
a2fbb9ea
ET		 352/* used only at init
353 * locking is done by mcp
354 */
8d96286a 355static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 356{
357 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
358 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
359 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
360 PCICFG_VENDOR_ID_OFFSET);
361}
362
a2fbb9ea
ET		 363static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
364{
365 u32 val;
366
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
368 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
369 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
370 PCICFG_VENDOR_ID_OFFSET);
371
372 return val;
373}
a2fbb9ea 374
f2e0899f
DK		 375#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
376#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
377#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
378#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
379#define DMAE_DP_DST_NONE "dst_addr [none]"
380
6bf07b8e
YM		 381static void bnx2x_dp_dmae(struct bnx2x *bp,
382 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 383{
384 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 385 int i;
fd1fc79d
AE		 386
387 switch (dmae->opcode & DMAE_COMMAND_DST) {
388 case DMAE_CMD_DST_PCI:
389 if (src_type == DMAE_CMD_SRC_PCI)
390 DP(msglvl, "DMAE: opcode 0x%08x\n"
391 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
392 "comp_addr [%x:%08x], comp_val 0x%08x\n",
393 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
394 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
395 dmae->comp_addr_hi, dmae->comp_addr_lo,
396 dmae->comp_val);
397 else
398 DP(msglvl, "DMAE: opcode 0x%08x\n"
399 "src [%08x], len [%d*4], dst [%x:%08x]\n"
400 "comp_addr [%x:%08x], comp_val 0x%08x\n",
401 dmae->opcode, dmae->src_addr_lo >> 2,
402 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
403 dmae->comp_addr_hi, dmae->comp_addr_lo,
404 dmae->comp_val);
405 break;
406 case DMAE_CMD_DST_GRC:
407 if (src_type == DMAE_CMD_SRC_PCI)
408 DP(msglvl, "DMAE: opcode 0x%08x\n"
409 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
410 "comp_addr [%x:%08x], comp_val 0x%08x\n",
411 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
412 dmae->len, dmae->dst_addr_lo >> 2,
413 dmae->comp_addr_hi, dmae->comp_addr_lo,
414 dmae->comp_val);
415 else
416 DP(msglvl, "DMAE: opcode 0x%08x\n"
417 "src [%08x], len [%d*4], dst [%08x]\n"
418 "comp_addr [%x:%08x], comp_val 0x%08x\n",
419 dmae->opcode, dmae->src_addr_lo >> 2,
420 dmae->len, dmae->dst_addr_lo >> 2,
421 dmae->comp_addr_hi, dmae->comp_addr_lo,
422 dmae->comp_val);
423 break;
424 default:
425 if (src_type == DMAE_CMD_SRC_PCI)
426 DP(msglvl, "DMAE: opcode 0x%08x\n"
427 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
428 "comp_addr [%x:%08x] comp_val 0x%08x\n",
429 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
430 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
431 dmae->comp_val);
432 else
433 DP(msglvl, "DMAE: opcode 0x%08x\n"
434 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
435 "comp_addr [%x:%08x] comp_val 0x%08x\n",
436 dmae->opcode, dmae->src_addr_lo >> 2,
437 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
438 dmae->comp_val);
439 break;
440 }
6bf07b8e
YM		 441
442 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
443 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
444 i, *(((u32 *)dmae) + i));
fd1fc79d 445}
f2e0899f 446
a2fbb9ea 447/* copy command into DMAE command memory and set DMAE command go */
6c719d00 448void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 449{
450 u32 cmd_offset;
451 int i;
452
453 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
454 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
455 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 456 }
457 REG_WR(bp, dmae_reg_go_c[idx], 1);
458}
459
f2e0899f 460u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 461{
f2e0899f
DK		 462 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
463 DMAE_CMD_C_ENABLE);
464}
ad8d3948 465
f2e0899f
DK		 466u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
467{
468 return opcode & ~DMAE_CMD_SRC_RESET;
469}
ad8d3948 470
f2e0899f
DK		 471u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
472 bool with_comp, u8 comp_type)
473{
474 u32 opcode = 0;
475
476 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
477 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 478
f2e0899f
DK		 479 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
480
481 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 482 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
483 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 484 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 485
a2fbb9ea 486#ifdef __BIG_ENDIAN
f2e0899f 487 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 488#else
f2e0899f 489 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 490#endif
f2e0899f
DK		 491 if (with_comp)
492 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
493 return opcode;
494}
495
fd1fc79d 496void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 497 struct dmae_command *dmae,
498 u8 src_type, u8 dst_type)
f2e0899f
DK		 499{
500 memset(dmae, 0, sizeof(struct dmae_command));
501
502 /* set the opcode */
503 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
504 true, DMAE_COMP_PCI);
505
506 /* fill in the completion parameters */
507 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
508 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
509 dmae->comp_val = DMAE_COMP_VAL;
510}
511
fd1fc79d 512/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 513int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
514 u32 *comp)
f2e0899f 515{
5e374b5a 516 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 517 int rc = 0;
518
6bf07b8e
YM		 519 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
520
521 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 522 * as long as this code is called both from syscall context and
523 * from ndo_set_rx_mode() flow that may be called from BH.
524 */
6e30dd4e 525 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 526
f2e0899f 527 /* reset completion */
32316a46 528 *comp = 0;
a2fbb9ea 529
f2e0899f
DK		 530 /* post the command on the channel used for initializations */
531 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 532
f2e0899f 533 /* wait for completion */
a2fbb9ea 534 udelay(5);
32316a46 535 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 536
95c6c616
AE		 537 if (!cnt ||
538 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
539 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 540 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 541 rc = DMAE_TIMEOUT;
542 goto unlock;
a2fbb9ea 543 }
ad8d3948 544 cnt--;
f2e0899f 545 udelay(50);
a2fbb9ea 546 }
32316a46 547 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 548 BNX2X_ERR("DMAE PCI error!\n");
549 rc = DMAE_PCI_ERROR;
550 }
551
f2e0899f 552unlock:
6e30dd4e 553 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 554 return rc;
555}
556
557void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
558 u32 len32)
559{
6bf07b8e 560 int rc;
f2e0899f
DK		 561 struct dmae_command dmae;
562
563 if (!bp->dmae_ready) {
564 u32 *data = bnx2x_sp(bp, wb_data[0]);
565
127a425e
AE		 566 if (CHIP_IS_E1(bp))
567 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
568 else
569 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 570 return;
571 }
572
573 /* set opcode and fixed command fields */
574 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
575
576 /* fill in addresses and len */
577 dmae.src_addr_lo = U64_LO(dma_addr);
578 dmae.src_addr_hi = U64_HI(dma_addr);
579 dmae.dst_addr_lo = dst_addr >> 2;
580 dmae.dst_addr_hi = 0;
581 dmae.len = len32;
582
f2e0899f 583 /* issue the command and wait for completion */
32316a46 584 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 585 if (rc) {
586 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 587#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 588 bnx2x_panic();
9dcd9acd 589#endif
6bf07b8e 590 }
a2fbb9ea
ET		 591}
592
c18487ee 593void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 594{
6bf07b8e 595 int rc;
5ff7b6d4 596 struct dmae_command dmae;
ad8d3948
EG		 597
598 if (!bp->dmae_ready) {
599 u32 *data = bnx2x_sp(bp, wb_data[0]);
600 int i;
601
51c1a580 602 if (CHIP_IS_E1(bp))
127a425e
AE		 603 for (i = 0; i < len32; i++)
604 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 605 else
127a425e
AE		 606 for (i = 0; i < len32; i++)
607 data[i] = REG_RD(bp, src_addr + i*4);
608
ad8d3948
EG		 609 return;
610 }
611
f2e0899f
DK		 612 /* set opcode and fixed command fields */
613 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 614
f2e0899f 615 /* fill in addresses and len */
5ff7b6d4
EG		 616 dmae.src_addr_lo = src_addr >> 2;
617 dmae.src_addr_hi = 0;
618 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
619 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
620 dmae.len = len32;
ad8d3948 621
f2e0899f 622 /* issue the command and wait for completion */
32316a46 623 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 624 if (rc) {
625 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 626#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 627 bnx2x_panic();
9dcd9acd 628#endif
c957d09f 629 }
ad8d3948
EG		 630}
631
8d96286a 632static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
633 u32 addr, u32 len)
573f2035 634{
02e3c6cb 635 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 636 int offset = 0;
637
02e3c6cb 638 while (len > dmae_wr_max) {
573f2035 639 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 640 addr + offset, dmae_wr_max);
641 offset += dmae_wr_max * 4;
642 len -= dmae_wr_max;
573f2035
EG		 643 }
644
645 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
646}
647
a2fbb9ea
ET		 648static int bnx2x_mc_assert(struct bnx2x *bp)
649{
a2fbb9ea 650 char last_idx;
34f80b04
EG		 651 int i, rc = 0;
652 u32 row0, row1, row2, row3;
653
654 /* XSTORM */
655 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
656 XSTORM_ASSERT_LIST_INDEX_OFFSET);
657 if (last_idx)
658 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
659
660 /* print the asserts */
661 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
662
663 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
664 XSTORM_ASSERT_LIST_OFFSET(i));
665 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
666 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
667 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
668 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
669 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
670 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
671
672 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 673 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 674 i, row3, row2, row1, row0);
675 rc++;
676 } else {
677 break;
678 }
679 }
680
681 /* TSTORM */
682 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
683 TSTORM_ASSERT_LIST_INDEX_OFFSET);
684 if (last_idx)
685 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686
687 /* print the asserts */
688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689
690 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
691 TSTORM_ASSERT_LIST_OFFSET(i));
692 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
693 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
694 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
695 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
696 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
697 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
698
699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 700 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
705 }
706 }
707
708 /* CSTORM */
709 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
710 CSTORM_ASSERT_LIST_INDEX_OFFSET);
711 if (last_idx)
712 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
713
714 /* print the asserts */
715 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
716
717 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
718 CSTORM_ASSERT_LIST_OFFSET(i));
719 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
720 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
721 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
722 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
723 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
724 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
725
726 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 727 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 728 i, row3, row2, row1, row0);
729 rc++;
730 } else {
731 break;
732 }
733 }
734
735 /* USTORM */
736 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
737 USTORM_ASSERT_LIST_INDEX_OFFSET);
738 if (last_idx)
739 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
740
741 /* print the asserts */
742 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
743
744 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
745 USTORM_ASSERT_LIST_OFFSET(i));
746 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
747 USTORM_ASSERT_LIST_OFFSET(i) + 4);
748 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
749 USTORM_ASSERT_LIST_OFFSET(i) + 8);
750 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
751 USTORM_ASSERT_LIST_OFFSET(i) + 12);
752
753 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 754 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 755 i, row3, row2, row1, row0);
756 rc++;
757 } else {
758 break;
a2fbb9ea
ET		 759 }
760 }
34f80b04 761
a2fbb9ea
ET		 762 return rc;
763}
c14423fe 764
1a6974b2
YM		 765#define MCPR_TRACE_BUFFER_SIZE (0x800)
766#define SCRATCH_BUFFER_SIZE(bp) \
767 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
768
7a25cc73 769void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 770{
7a25cc73 771 u32 addr, val;
a2fbb9ea 772 u32 mark, offset;
4781bfad 773 __be32 data[9];
a2fbb9ea 774 int word;
f2e0899f 775 u32 trace_shmem_base;
2145a920
VZ		 776 if (BP_NOMCP(bp)) {
777 BNX2X_ERR("NO MCP - can not dump\n");
778 return;
779 }
7a25cc73
DK		 780 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
781 (bp->common.bc_ver & 0xff0000) >> 16,
782 (bp->common.bc_ver & 0xff00) >> 8,
783 (bp->common.bc_ver & 0xff));
784
785 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
786 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 787 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 788
f2e0899f
DK		 789 if (BP_PATH(bp) == 0)
790 trace_shmem_base = bp->common.shmem_base;
791 else
792 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 793
794 /* sanity */
795 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
796 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
797 SCRATCH_BUFFER_SIZE(bp)) {
798 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
799 trace_shmem_base);
800 return;
801 }
802
803 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 804
805 /* validate TRCB signature */
806 mark = REG_RD(bp, addr);
807 if (mark != MFW_TRACE_SIGNATURE) {
808 BNX2X_ERR("Trace buffer signature is missing.");
809 return ;
810 }
811
812 /* read cyclic buffer pointer */
813 addr += 4;
cdaa7cb8 814 mark = REG_RD(bp, addr);
1a6974b2
YM		 815 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
816 if (mark >= trace_shmem_base || mark < addr + 4) {
817 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
818 return;
819 }
7a25cc73 820 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 821
7a25cc73 822 printk("%s", lvl);
2de67439
YM		 823
824 /* dump buffer after the mark */
1a6974b2 825 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 826 for (word = 0; word < 8; word++)
cdaa7cb8 827 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 828 data[8] = 0x0;
7995c64e 829 pr_cont("%s", (char *)data);
a2fbb9ea 830 }
2de67439
YM		 831
832 /* dump buffer before the mark */
cdaa7cb8 833 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 834 for (word = 0; word < 8; word++)
cdaa7cb8 835 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 836 data[8] = 0x0;
7995c64e 837 pr_cont("%s", (char *)data);
a2fbb9ea 838 }
7a25cc73
DK		 839 printk("%s" "end of fw dump\n", lvl);
840}
841
1191cb83 842static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 843{
844 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 845}
846
823e1d90
YM		 847static void bnx2x_hc_int_disable(struct bnx2x *bp)
848{
849 int port = BP_PORT(bp);
850 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
851 u32 val = REG_RD(bp, addr);
852
853 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 854 * MSI/MSIX capability
855 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 856 */
857 if (CHIP_IS_E1(bp)) {
858 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
859 * Use mask register to prevent from HC sending interrupts
860 * after we exit the function
861 */
862 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
863
864 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
865 HC_CONFIG_0_REG_INT_LINE_EN_0 |
866 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
867 } else
868 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
869 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
870 HC_CONFIG_0_REG_INT_LINE_EN_0 |
871 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
872
873 DP(NETIF_MSG_IFDOWN,
874 "write %x to HC %d (addr 0x%x)\n",
875 val, port, addr);
876
877 /* flush all outstanding writes */
878 mmiowb();
879
880 REG_WR(bp, addr, val);
881 if (REG_RD(bp, addr) != val)
6bf07b8e 882 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 883}
884
885static void bnx2x_igu_int_disable(struct bnx2x *bp)
886{
887 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
888
889 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
890 IGU_PF_CONF_INT_LINE_EN |
891 IGU_PF_CONF_ATTN_BIT_EN);
892
893 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
894
895 /* flush all outstanding writes */
896 mmiowb();
897
898 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
899 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 900 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 901}
902
903static void bnx2x_int_disable(struct bnx2x *bp)
904{
905 if (bp->common.int_block == INT_BLOCK_HC)
906 bnx2x_hc_int_disable(bp);
907 else
908 bnx2x_igu_int_disable(bp);
909}
910
911void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 912{
913 int i;
523224a3
DK		 914 u16 j;
915 struct hc_sp_status_block_data sp_sb_data;
916 int func = BP_FUNC(bp);
917#ifdef BNX2X_STOP_ON_ERROR
918 u16 start = 0, end = 0;
6383c0b3 919 u8 cos;
523224a3 920#endif
0155a27c 921 if (IS_PF(bp) && disable_int)
823e1d90 922 bnx2x_int_disable(bp);
a2fbb9ea 923
66e855f3 924 bp->stats_state = STATS_STATE_DISABLED;
7a752993 925 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 926 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
927
a2fbb9ea
ET		 928 BNX2X_ERR("begin crash dump -----------------\n");
929
8440d2b6
EG		 930 /* Indices */
931 /* Common */
0155a27c
YM		 932 if (IS_PF(bp)) {
933 struct host_sp_status_block *def_sb = bp->def_status_blk;
934 int data_size, cstorm_offset;
935
936 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
937 bp->def_idx, bp->def_att_idx, bp->attn_state,
938 bp->spq_prod_idx, bp->stats_counter);
939 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
940 def_sb->atten_status_block.attn_bits,
941 def_sb->atten_status_block.attn_bits_ack,
942 def_sb->atten_status_block.status_block_id,
943 def_sb->atten_status_block.attn_bits_index);
944 BNX2X_ERR(" def (");
945 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
946 pr_cont("0x%x%s",
947 def_sb->sp_sb.index_values[i],
948 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
949
950 data_size = sizeof(struct hc_sp_status_block_data) /
951 sizeof(u32);
952 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
953 for (i = 0; i < data_size; i++)
954 *((u32 *)&sp_sb_data + i) =
955 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
956 i * sizeof(u32));
957
958 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
959 sp_sb_data.igu_sb_id,
960 sp_sb_data.igu_seg_id,
961 sp_sb_data.p_func.pf_id,
962 sp_sb_data.p_func.vnic_id,
963 sp_sb_data.p_func.vf_id,
964 sp_sb_data.p_func.vf_valid,
965 sp_sb_data.state);
966 }
523224a3 967
ec6ba945 968 for_each_eth_queue(bp, i) {
a2fbb9ea 969 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 970 int loop;
f2e0899f 971 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 972 struct hc_status_block_data_e1x sb_data_e1x;
973 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 974 CHIP_IS_E1x(bp) ?
975 sb_data_e1x.common.state_machine :
976 sb_data_e2.common.state_machine;
523224a3 977 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 978 CHIP_IS_E1x(bp) ?
979 sb_data_e1x.index_data :
980 sb_data_e2.index_data;
6383c0b3 981 u8 data_size, cos;
523224a3 982 u32 *sb_data_p;
6383c0b3 983 struct bnx2x_fp_txdata txdata;
523224a3
DK		 984
985 /* Rx */
51c1a580 986 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 987 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 988 fp->rx_comp_prod,
66e855f3 989 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 990 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 991 fp->rx_sge_prod, fp->last_max_sge,
523224a3 992 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 993
523224a3 994 /* Tx */
6383c0b3
AE		 995 for_each_cos_in_tx_queue(fp, cos)
996 {
65565884 997 txdata = *fp->txdata_ptr[cos];
51c1a580 998 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 999 i, txdata.tx_pkt_prod,
1000 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1001 txdata.tx_bd_cons,
1002 le16_to_cpu(*txdata.tx_cons_sb));
1003 }
523224a3 1004
619c5cb6
VZ		 1005 loop = CHIP_IS_E1x(bp) ?
1006 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1007
1008 /* host sb data */
1009
ec6ba945
VZ		 1010 if (IS_FCOE_FP(fp))
1011 continue;
55c11941 1012
523224a3
DK		 1013 BNX2X_ERR(" run indexes (");
1014 for (j = 0; j < HC_SB_MAX_SM; j++)
1015 pr_cont("0x%x%s",
1016 fp->sb_running_index[j],
1017 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1018
1019 BNX2X_ERR(" indexes (");
1020 for (j = 0; j < loop; j++)
1021 pr_cont("0x%x%s",
1022 fp->sb_index_values[j],
1023 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1024
1025 /* VF cannot access FW refelection for status block */
1026 if (IS_VF(bp))
1027 continue;
1028
523224a3 1029 /* fw sb data */
619c5cb6
VZ		 1030 data_size = CHIP_IS_E1x(bp) ?
1031 sizeof(struct hc_status_block_data_e1x) :
1032 sizeof(struct hc_status_block_data_e2);
523224a3 1033 data_size /= sizeof(u32);
619c5cb6
VZ		 1034 sb_data_p = CHIP_IS_E1x(bp) ?
1035 (u32 *)&sb_data_e1x :
1036 (u32 *)&sb_data_e2;
523224a3
DK		 1037 /* copy sb data in here */
1038 for (j = 0; j < data_size; j++)
1039 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1040 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1041 j * sizeof(u32));
1042
619c5cb6 1043 if (!CHIP_IS_E1x(bp)) {
51c1a580 1044 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1045 sb_data_e2.common.p_func.pf_id,
1046 sb_data_e2.common.p_func.vf_id,
1047 sb_data_e2.common.p_func.vf_valid,
1048 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1049 sb_data_e2.common.same_igu_sb_1b,
1050 sb_data_e2.common.state);
f2e0899f 1051 } else {
51c1a580 1052 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1053 sb_data_e1x.common.p_func.pf_id,
1054 sb_data_e1x.common.p_func.vf_id,
1055 sb_data_e1x.common.p_func.vf_valid,
1056 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1057 sb_data_e1x.common.same_igu_sb_1b,
1058 sb_data_e1x.common.state);
f2e0899f 1059 }
523224a3
DK		 1060
1061 /* SB_SMs data */
1062 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1063 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1064 j, hc_sm_p[j].__flags,
1065 hc_sm_p[j].igu_sb_id,
1066 hc_sm_p[j].igu_seg_id,
1067 hc_sm_p[j].time_to_expire,
1068 hc_sm_p[j].timer_value);
523224a3
DK		 1069 }
1070
16a5fd92 1071 /* Indices data */
523224a3 1072 for (j = 0; j < loop; j++) {
51c1a580 1073 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1074 hc_index_p[j].flags,
1075 hc_index_p[j].timeout);
1076 }
8440d2b6 1077 }
a2fbb9ea 1078
523224a3 1079#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1080 if (IS_PF(bp)) {
1081 /* event queue */
1082 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1083 for (i = 0; i < NUM_EQ_DESC; i++) {
1084 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1085
1086 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1087 i, bp->eq_ring[i].message.opcode,
1088 bp->eq_ring[i].message.error);
1089 BNX2X_ERR("data: %x %x %x\n",
1090 data[0], data[1], data[2]);
1091 }
04c46736
YM		 1092 }
1093
8440d2b6
EG		 1094 /* Rings */
1095 /* Rx */
55c11941 1096 for_each_valid_rx_queue(bp, i) {
8440d2b6 1097 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 1098
1099 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1100 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1101 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1102 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1103 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1104
c3eefaf6 1105 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1106 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1107 }
1108
3196a88a
EG		 1109 start = RX_SGE(fp->rx_sge_prod);
1110 end = RX_SGE(fp->last_max_sge);
8440d2b6 1111 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1112 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1113 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1114
c3eefaf6
EG		 1115 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1116 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1117 }
1118
a2fbb9ea
ET		 1119 start = RCQ_BD(fp->rx_comp_cons - 10);
1120 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1121 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1122 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1123
c3eefaf6
EG		 1124 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1125 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1126 }
1127 }
1128
8440d2b6 1129 /* Tx */
55c11941 1130 for_each_valid_tx_queue(bp, i) {
8440d2b6 1131 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3 1132 for_each_cos_in_tx_queue(fp, cos) {
65565884 1133 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3
AE		 1134
1135 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1136 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1137 for (j = start; j != end; j = TX_BD(j + 1)) {
1138 struct sw_tx_bd *sw_bd =
1139 &txdata->tx_buf_ring[j];
1140
51c1a580 1141 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1142 i, cos, j, sw_bd->skb,
1143 sw_bd->first_bd);
1144 }
8440d2b6 1145
6383c0b3
AE		 1146 start = TX_BD(txdata->tx_bd_cons - 10);
1147 end = TX_BD(txdata->tx_bd_cons + 254);
1148 for (j = start; j != end; j = TX_BD(j + 1)) {
1149 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1150
51c1a580 1151 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1152 i, cos, j, tx_bd[0], tx_bd[1],
1153 tx_bd[2], tx_bd[3]);
1154 }
8440d2b6
EG		 1155 }
1156 }
523224a3 1157#endif
0155a27c
YM		 1158 if (IS_PF(bp)) {
1159 bnx2x_fw_dump(bp);
1160 bnx2x_mc_assert(bp);
1161 }
a2fbb9ea 1162 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1163}
1164
619c5cb6
VZ		 1165/*
1166 * FLR Support for E2
1167 *
1168 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1169 * initialization.
1170 */
16a5fd92 1171#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1172#define FLR_WAIT_INTERVAL 50 /* usec */
1173#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1174
1175struct pbf_pN_buf_regs {
1176 int pN;
1177 u32 init_crd;
1178 u32 crd;
1179 u32 crd_freed;
1180};
1181
1182struct pbf_pN_cmd_regs {
1183 int pN;
1184 u32 lines_occup;
1185 u32 lines_freed;
1186};
1187
1188static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1189 struct pbf_pN_buf_regs *regs,
1190 u32 poll_count)
1191{
1192 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1193 u32 cur_cnt = poll_count;
1194
1195 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1196 crd = crd_start = REG_RD(bp, regs->crd);
1197 init_crd = REG_RD(bp, regs->init_crd);
1198
1199 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1200 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1201 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1202
1203 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1204 (init_crd - crd_start))) {
1205 if (cur_cnt--) {
89db4ad8 1206 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1207 crd = REG_RD(bp, regs->crd);
1208 crd_freed = REG_RD(bp, regs->crd_freed);
1209 } else {
1210 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1211 regs->pN);
1212 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1213 regs->pN, crd);
1214 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1215 regs->pN, crd_freed);
1216 break;
1217 }
1218 }
1219 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1220 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1221}
1222
1223static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1224 struct pbf_pN_cmd_regs *regs,
1225 u32 poll_count)
1226{
1227 u32 occup, to_free, freed, freed_start;
1228 u32 cur_cnt = poll_count;
1229
1230 occup = to_free = REG_RD(bp, regs->lines_occup);
1231 freed = freed_start = REG_RD(bp, regs->lines_freed);
1232
1233 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1234 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1235
1236 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1237 if (cur_cnt--) {
89db4ad8 1238 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1239 occup = REG_RD(bp, regs->lines_occup);
1240 freed = REG_RD(bp, regs->lines_freed);
1241 } else {
1242 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1243 regs->pN);
1244 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1245 regs->pN, occup);
1246 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1247 regs->pN, freed);
1248 break;
1249 }
1250 }
1251 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1252 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1253}
1254
1191cb83
ED		 1255static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1256 u32 expected, u32 poll_count)
619c5cb6
VZ		 1257{
1258 u32 cur_cnt = poll_count;
1259 u32 val;
1260
1261 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1262 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1263
1264 return val;
1265}
1266
d16132ce
AE		 1267int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1268 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1269{
1270 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1271 if (val != 0) {
1272 BNX2X_ERR("%s usage count=%d\n", msg, val);
1273 return 1;
1274 }
1275 return 0;
1276}
1277
d16132ce
AE		 1278/* Common routines with VF FLR cleanup */
1279u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1280{
1281 /* adjust polling timeout */
1282 if (CHIP_REV_IS_EMUL(bp))
1283 return FLR_POLL_CNT * 2000;
1284
1285 if (CHIP_REV_IS_FPGA(bp))
1286 return FLR_POLL_CNT * 120;
1287
1288 return FLR_POLL_CNT;
1289}
1290
d16132ce 1291void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1292{
1293 struct pbf_pN_cmd_regs cmd_regs[] = {
1294 {0, (CHIP_IS_E3B0(bp)) ?
1295 PBF_REG_TQ_OCCUPANCY_Q0 :
1296 PBF_REG_P0_TQ_OCCUPANCY,
1297 (CHIP_IS_E3B0(bp)) ?
1298 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1299 PBF_REG_P0_TQ_LINES_FREED_CNT},
1300 {1, (CHIP_IS_E3B0(bp)) ?
1301 PBF_REG_TQ_OCCUPANCY_Q1 :
1302 PBF_REG_P1_TQ_OCCUPANCY,
1303 (CHIP_IS_E3B0(bp)) ?
1304 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1305 PBF_REG_P1_TQ_LINES_FREED_CNT},
1306 {4, (CHIP_IS_E3B0(bp)) ?
1307 PBF_REG_TQ_OCCUPANCY_LB_Q :
1308 PBF_REG_P4_TQ_OCCUPANCY,
1309 (CHIP_IS_E3B0(bp)) ?
1310 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1311 PBF_REG_P4_TQ_LINES_FREED_CNT}
1312 };
1313
1314 struct pbf_pN_buf_regs buf_regs[] = {
1315 {0, (CHIP_IS_E3B0(bp)) ?
1316 PBF_REG_INIT_CRD_Q0 :
1317 PBF_REG_P0_INIT_CRD ,
1318 (CHIP_IS_E3B0(bp)) ?
1319 PBF_REG_CREDIT_Q0 :
1320 PBF_REG_P0_CREDIT,
1321 (CHIP_IS_E3B0(bp)) ?
1322 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1323 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1324 {1, (CHIP_IS_E3B0(bp)) ?
1325 PBF_REG_INIT_CRD_Q1 :
1326 PBF_REG_P1_INIT_CRD,
1327 (CHIP_IS_E3B0(bp)) ?
1328 PBF_REG_CREDIT_Q1 :
1329 PBF_REG_P1_CREDIT,
1330 (CHIP_IS_E3B0(bp)) ?
1331 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1332 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1333 {4, (CHIP_IS_E3B0(bp)) ?
1334 PBF_REG_INIT_CRD_LB_Q :
1335 PBF_REG_P4_INIT_CRD,
1336 (CHIP_IS_E3B0(bp)) ?
1337 PBF_REG_CREDIT_LB_Q :
1338 PBF_REG_P4_CREDIT,
1339 (CHIP_IS_E3B0(bp)) ?
1340 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1341 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1342 };
1343
1344 int i;
1345
1346 /* Verify the command queues are flushed P0, P1, P4 */
1347 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1348 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1349
619c5cb6
VZ		 1350 /* Verify the transmission buffers are flushed P0, P1, P4 */
1351 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1352 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1353}
1354
1355#define OP_GEN_PARAM(param) \
1356 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1357
1358#define OP_GEN_TYPE(type) \
1359 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1360
1361#define OP_GEN_AGG_VECT(index) \
1362 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1363
d16132ce 1364int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1365{
86564c3f 1366 u32 op_gen_command = 0;
619c5cb6
VZ		 1367 u32 comp_addr = BAR_CSTRORM_INTMEM +
1368 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1369 int ret = 0;
1370
1371 if (REG_RD(bp, comp_addr)) {
89db4ad8 1372 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1373 return 1;
1374 }
1375
86564c3f
YM		 1376 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1377 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1378 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1379 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1380
89db4ad8 1381 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1382 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1383
1384 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1385 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1386 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1387 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1388 bnx2x_panic();
1389 return 1;
619c5cb6 1390 }
16a5fd92 1391 /* Zero completion for next FLR */
619c5cb6
VZ		 1392 REG_WR(bp, comp_addr, 0);
1393
1394 return ret;
1395}
1396
b56e9670 1397u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1398{
619c5cb6
VZ		 1399 u16 status;
1400
2a80eebc 1401 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1402 return status & PCI_EXP_DEVSTA_TRPND;
1403}
1404
1405/* PF FLR specific routines
1406*/
1407static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1408{
619c5cb6
VZ		 1409 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1410 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1411 CFC_REG_NUM_LCIDS_INSIDE_PF,
1412 "CFC PF usage counter timed out",
1413 poll_cnt))
1414 return 1;
1415
619c5cb6
VZ		 1416 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1417 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1418 DORQ_REG_PF_USAGE_CNT,
1419 "DQ PF usage counter timed out",
1420 poll_cnt))
1421 return 1;
1422
1423 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1424 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1426 "QM PF usage counter timed out",
1427 poll_cnt))
1428 return 1;
1429
1430 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1431 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1433 "Timers VNIC usage counter timed out",
1434 poll_cnt))
1435 return 1;
1436 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1437 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1438 "Timers NUM_SCANS usage counter timed out",
1439 poll_cnt))
1440 return 1;
1441
1442 /* Wait DMAE PF usage counter to zero */
1443 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1444 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1445 "DMAE command register timed out",
619c5cb6
VZ		 1446 poll_cnt))
1447 return 1;
1448
1449 return 0;
1450}
1451
1452static void bnx2x_hw_enable_status(struct bnx2x *bp)
1453{
1454 u32 val;
1455
1456 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1457 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1458
1459 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1460 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1461
1462 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1463 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1464
1465 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1466 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1467
1468 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1469 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1470
1471 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1472 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1473
1474 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1475 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1476
1477 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1478 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1479 val);
1480}
1481
1482static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1483{
1484 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1485
1486 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1487
1488 /* Re-enable PF target read access */
1489 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1490
1491 /* Poll HW usage counters */
89db4ad8 1492 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1493 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1494 return -EBUSY;
1495
1496 /* Zero the igu 'trailing edge' and 'leading edge' */
1497
1498 /* Send the FW cleanup command */
1499 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1500 return -EBUSY;
1501
1502 /* ATC cleanup */
1503
1504 /* Verify TX hw is flushed */
1505 bnx2x_tx_hw_flushed(bp, poll_cnt);
1506
1507 /* Wait 100ms (not adjusted according to platform) */
1508 msleep(100);
1509
1510 /* Verify no pending pci transactions */
1511 if (bnx2x_is_pcie_pending(bp->pdev))
1512 BNX2X_ERR("PCIE Transactions still pending\n");
1513
1514 /* Debug */
1515 bnx2x_hw_enable_status(bp);
1516
1517 /*
1518 * Master enable - Due to WB DMAE writes performed before this
1519 * register is re-initialized as part of the regular function init
1520 */
1521 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1522
1523 return 0;
1524}
1525
f2e0899f 1526static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1527{
34f80b04 1528 int port = BP_PORT(bp);
a2fbb9ea
ET		 1529 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1530 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1531 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1532 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1533 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1534
1535 if (msix) {
8badd27a
EG		 1536 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1537 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1538 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1539 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1540 if (single_msix)
1541 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1542 } else if (msi) {
1543 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1544 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1545 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1546 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1547 } else {
1548 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1549 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1550 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1551 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1552
a0fd065c 1553 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1554 DP(NETIF_MSG_IFUP,
1555 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1556
a0fd065c 1557 REG_WR(bp, addr, val);
615f8fd9 1558
a0fd065c
DK		 1559 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1560 }
a2fbb9ea
ET		 1561 }
1562
a0fd065c
DK		 1563 if (CHIP_IS_E1(bp))
1564 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1565
51c1a580
MS		 1566 DP(NETIF_MSG_IFUP,
1567 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1568 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1569
1570 REG_WR(bp, addr, val);
37dbbf32
EG		 1571 /*
1572 * Ensure that HC_CONFIG is written before leading/trailing edge config
1573 */
1574 mmiowb();
1575 barrier();
34f80b04 1576
f2e0899f 1577 if (!CHIP_IS_E1(bp)) {
34f80b04 1578 /* init leading/trailing edge */
fb3bff17 1579 if (IS_MF(bp)) {
3395a033 1580 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1581 if (bp->port.pmf)
4acac6a5
EG		 1582 /* enable nig and gpio3 attention */
1583 val |= 0x1100;
34f80b04
EG		 1584 } else
1585 val = 0xffff;
1586
1587 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1588 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1589 }
37dbbf32
EG		 1590
1591 /* Make sure that interrupts are indeed enabled from here on */
1592 mmiowb();
a2fbb9ea
ET		 1593}
1594
f2e0899f
DK		 1595static void bnx2x_igu_int_enable(struct bnx2x *bp)
1596{
1597 u32 val;
30a5de77
DK		 1598 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1599 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1600 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1601
1602 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1603
1604 if (msix) {
1605 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1606 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1607 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1608 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1609
1610 if (single_msix)
1611 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1612 } else if (msi) {
1613 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1614 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1615 IGU_PF_CONF_ATTN_BIT_EN |
1616 IGU_PF_CONF_SINGLE_ISR_EN);
1617 } else {
1618 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1619 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1620 IGU_PF_CONF_ATTN_BIT_EN |
1621 IGU_PF_CONF_SINGLE_ISR_EN);
1622 }
1623
ebe61d80
YM		 1624 /* Clean previous status - need to configure igu prior to ack*/
1625 if ((!msix) || single_msix) {
1626 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1627 bnx2x_ack_int(bp);
1628 }
1629
1630 val |= IGU_PF_CONF_FUNC_EN;
1631
51c1a580 1632 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1633 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1634
1635 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1636
79a8557a
YM		 1637 if (val & IGU_PF_CONF_INT_LINE_EN)
1638 pci_intx(bp->pdev, true);
1639
f2e0899f
DK		 1640 barrier();
1641
1642 /* init leading/trailing edge */
1643 if (IS_MF(bp)) {
3395a033 1644 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1645 if (bp->port.pmf)
1646 /* enable nig and gpio3 attention */
1647 val |= 0x1100;
1648 } else
1649 val = 0xffff;
1650
1651 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1652 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1653
1654 /* Make sure that interrupts are indeed enabled from here on */
1655 mmiowb();
1656}
1657
1658void bnx2x_int_enable(struct bnx2x *bp)
1659{
1660 if (bp->common.int_block == INT_BLOCK_HC)
1661 bnx2x_hc_int_enable(bp);
1662 else
1663 bnx2x_igu_int_enable(bp);
1664}
1665
9f6c9258 1666void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1667{
a2fbb9ea 1668 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1669 int i, offset;
a2fbb9ea 1670
f8ef6e44
YG		 1671 if (disable_hw)
1672 /* prevent the HW from sending interrupts */
1673 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1674
1675 /* make sure all ISRs are done */
1676 if (msix) {
8badd27a
EG		 1677 synchronize_irq(bp->msix_table[0].vector);
1678 offset = 1;
55c11941
MS		 1679 if (CNIC_SUPPORT(bp))
1680 offset++;
ec6ba945 1681 for_each_eth_queue(bp, i)
754a2f52 1682 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1683 } else
1684 synchronize_irq(bp->pdev->irq);
1685
1686 /* make sure sp_task is not running */
1cf167f2 1687 cancel_delayed_work(&bp->sp_task);
3deb8167 1688 cancel_delayed_work(&bp->period_task);
1cf167f2 1689 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1690}
1691
34f80b04 1692/* fast path */
a2fbb9ea
ET		 1693
1694/*
34f80b04 1695 * General service functions
a2fbb9ea
ET		 1696 */
1697
72fd0718
VZ		 1698/* Return true if succeeded to acquire the lock */
1699static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1700{
1701 u32 lock_status;
1702 u32 resource_bit = (1 << resource);
1703 int func = BP_FUNC(bp);
1704 u32 hw_lock_control_reg;
1705
51c1a580
MS		 1706 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1707 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1708
1709 /* Validating that the resource is within range */
1710 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1711 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1712 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1713 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1714 return false;
72fd0718
VZ		 1715 }
1716
1717 if (func <= 5)
1718 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1719 else
1720 hw_lock_control_reg =
1721 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1722
1723 /* Try to acquire the lock */
1724 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1725 lock_status = REG_RD(bp, hw_lock_control_reg);
1726 if (lock_status & resource_bit)
1727 return true;
1728
51c1a580
MS		 1729 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1730 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1731 return false;
1732}
1733
c9ee9206
VZ		 1734/**
1735 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1736 *
1737 * @bp: driver handle
1738 *
1739 * Returns the recovery leader resource id according to the engine this function
1740 * belongs to. Currently only only 2 engines is supported.
1741 */
1191cb83 1742static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1743{
1744 if (BP_PATH(bp))
1745 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1746 else
1747 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1748}
1749
1750/**
2de67439 1751 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1752 *
1753 * @bp: driver handle
1754 *
2de67439 1755 * Tries to acquire a leader lock for current engine.
c9ee9206 1756 */
1191cb83 1757static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1758{
1759 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1760}
1761
619c5cb6 1762static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1763
fd1fc79d
AE		 1764/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1765static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1766{
1767 /* Set the interrupt occurred bit for the sp-task to recognize it
1768 * must ack the interrupt and transition according to the IGU
1769 * state machine.
1770 */
1771 atomic_set(&bp->interrupt_occurred, 1);
1772
1773 /* The sp_task must execute only after this bit
1774 * is set, otherwise we will get out of sync and miss all
1775 * further interrupts. Hence, the barrier.
1776 */
1777 smp_wmb();
1778
1779 /* schedule sp_task to workqueue */
1780 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1781}
3196a88a 1782
619c5cb6 1783void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1784{
1785 struct bnx2x *bp = fp->bp;
1786 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1787 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1788 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1789 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1790
34f80b04 1791 DP(BNX2X_MSG_SP,
a2fbb9ea 1792 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1793 fp->index, cid, command, bp->state,
34f80b04 1794 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1795
fd1fc79d
AE		 1796 /* If cid is within VF range, replace the slowpath object with the
1797 * one corresponding to this VF
1798 */
1799 if (cid >= BNX2X_FIRST_VF_CID &&
1800 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1801 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1802
619c5cb6
VZ		 1803 switch (command) {
1804 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1805 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1806 drv_cmd = BNX2X_Q_CMD_UPDATE;
1807 break;
d6cae238 1808
619c5cb6 1809 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1810 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1811 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1812 break;
1813
6383c0b3 1814 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1815 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1816 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1817 break;
1818
619c5cb6 1819 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1820 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1821 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1822 break;
1823
619c5cb6 1824 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1825 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1826 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1827 break;
1828
619c5cb6 1829 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1830 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1831 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1832 break;
619c5cb6 1833
14a94ebd
MK		 1834 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1835 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1836 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1837 break;
1838
619c5cb6
VZ		 1839 default:
1840 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1841 command, fp->index);
1842 return;
523224a3 1843 }
3196a88a 1844
619c5cb6
VZ		 1845 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1846 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1847 /* q_obj->complete_cmd() failure means that this was
1848 * an unexpected completion.
1849 *
1850 * In this case we don't want to increase the bp->spq_left
1851 * because apparently we haven't sent this command the first
1852 * place.
1853 */
1854#ifdef BNX2X_STOP_ON_ERROR
1855 bnx2x_panic();
1856#else
1857 return;
1858#endif
fd1fc79d
AE		 1859 /* SRIOV: reschedule any 'in_progress' operations */
1860 bnx2x_iov_sp_event(bp, cid, true);
619c5cb6 1861
8fe23fbd 1862 smp_mb__before_atomic_inc();
6e30dd4e 1863 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1864 /* push the change in bp->spq_left and towards the memory */
1865 smp_mb__after_atomic_inc();
49d66772 1866
d6cae238
VZ		 1867 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1868
a3348722
BW		 1869 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1870 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1871 /* if Q update ramrod is completed for last Q in AFEX vif set
1872 * flow, then ACK MCP at the end
1873 *
1874 * mark pending ACK to MCP bit.
1875 * prevent case that both bits are cleared.
1876 * At the end of load/unload driver checks that
2de67439 1877 * sp_state is cleared, and this order prevents
a3348722
BW		 1878 * races
1879 */
1880 smp_mb__before_clear_bit();
1881 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1882 wmb();
1883 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1884 smp_mb__after_clear_bit();
1885
fd1fc79d
AE		 1886 /* schedule the sp task as mcp ack is required */
1887 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1888 }
1889
523224a3 1890 return;
a2fbb9ea
ET		 1891}
1892
9f6c9258 1893irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1894{
555f6c78 1895 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1896 u16 status = bnx2x_ack_int(bp);
34f80b04 1897 u16 mask;
ca00392c 1898 int i;
6383c0b3 1899 u8 cos;
a2fbb9ea 1900
34f80b04 1901 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1902 if (unlikely(status == 0)) {
1903 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1904 return IRQ_NONE;
1905 }
f5372251 1906 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1907
3196a88a
EG		 1908#ifdef BNX2X_STOP_ON_ERROR
1909 if (unlikely(bp->panic))
1910 return IRQ_HANDLED;
1911#endif
1912
ec6ba945 1913 for_each_eth_queue(bp, i) {
ca00392c 1914 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1915
55c11941 1916 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1917 if (status & mask) {
619c5cb6 1918 /* Handle Rx or Tx according to SB id */
6383c0b3 1919 for_each_cos_in_tx_queue(fp, cos)
65565884 1920 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1921 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1922 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1923 status &= ~mask;
1924 }
a2fbb9ea
ET		 1925 }
1926
55c11941
MS		 1927 if (CNIC_SUPPORT(bp)) {
1928 mask = 0x2;
1929 if (status & (mask | 0x1)) {
1930 struct cnic_ops *c_ops = NULL;
993ac7b5 1931
ad9b4359
MC		 1932 rcu_read_lock();
1933 c_ops = rcu_dereference(bp->cnic_ops);
1934 if (c_ops && (bp->cnic_eth_dev.drv_state &
1935 CNIC_DRV_STATE_HANDLES_IRQ))
1936 c_ops->cnic_handler(bp->cnic_data, NULL);
1937 rcu_read_unlock();
993ac7b5 1938
55c11941
MS		 1939 status &= ~mask;
1940 }
993ac7b5 1941 }
a2fbb9ea 1942
34f80b04 1943 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1944
1945 /* schedule sp task to perform default status block work, ack
1946 * attentions and enable interrupts.
1947 */
1948 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1949
1950 status &= ~0x1;
1951 if (!status)
1952 return IRQ_HANDLED;
1953 }
1954
cdaa7cb8
VZ		 1955 if (unlikely(status))
1956 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1957 status);
a2fbb9ea 1958
c18487ee 1959 return IRQ_HANDLED;
a2fbb9ea
ET		 1960}
1961
c18487ee
YR		 1962/* Link */
1963
1964/*
1965 * General service functions
1966 */
a2fbb9ea 1967
9f6c9258 1968int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1969{
1970 u32 lock_status;
1971 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1972 int func = BP_FUNC(bp);
1973 u32 hw_lock_control_reg;
c18487ee 1974 int cnt;
a2fbb9ea 1975
c18487ee
YR		 1976 /* Validating that the resource is within range */
1977 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1978 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1979 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1980 return -EINVAL;
1981 }
a2fbb9ea 1982
4a37fb66
YG		 1983 if (func <= 5) {
1984 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1985 } else {
1986 hw_lock_control_reg =
1987 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1988 }
1989
c18487ee 1990 /* Validating that the resource is not already taken */
4a37fb66 1991 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1992 if (lock_status & resource_bit) {
51c1a580 1993 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 1994 lock_status, resource_bit);
1995 return -EEXIST;
1996 }
a2fbb9ea 1997
46230476
EG		 1998 /* Try for 5 second every 5ms */
1999 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2000 /* Try to acquire the lock */
4a37fb66
YG		 2001 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2002 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2003 if (lock_status & resource_bit)
2004 return 0;
a2fbb9ea 2005
639d65b8 2006 usleep_range(5000, 10000);
a2fbb9ea 2007 }
51c1a580 2008 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2009 return -EAGAIN;
2010}
a2fbb9ea 2011
c9ee9206
VZ		 2012int bnx2x_release_leader_lock(struct bnx2x *bp)
2013{
2014 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2015}
2016
9f6c9258 2017int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2018{
2019 u32 lock_status;
2020 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2021 int func = BP_FUNC(bp);
2022 u32 hw_lock_control_reg;
a2fbb9ea 2023
c18487ee
YR		 2024 /* Validating that the resource is within range */
2025 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2026 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2027 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2028 return -EINVAL;
2029 }
2030
4a37fb66
YG		 2031 if (func <= 5) {
2032 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2033 } else {
2034 hw_lock_control_reg =
2035 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2036 }
2037
c18487ee 2038 /* Validating that the resource is currently taken */
4a37fb66 2039 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2040 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2041 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2042 lock_status, resource_bit);
c18487ee 2043 return -EFAULT;
a2fbb9ea
ET		 2044 }
2045
9f6c9258
DK		 2046 REG_WR(bp, hw_lock_control_reg, resource_bit);
2047 return 0;
c18487ee 2048}
a2fbb9ea 2049
4acac6a5
EG		 2050int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2051{
2052 /* The GPIO should be swapped if swap register is set and active */
2053 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2054 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2055 int gpio_shift = gpio_num +
2056 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2057 u32 gpio_mask = (1 << gpio_shift);
2058 u32 gpio_reg;
2059 int value;
2060
2061 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2062 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2063 return -EINVAL;
2064 }
2065
2066 /* read GPIO value */
2067 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2068
2069 /* get the requested pin value */
2070 if ((gpio_reg & gpio_mask) == gpio_mask)
2071 value = 1;
2072 else
2073 value = 0;
2074
2075 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2076
2077 return value;
2078}
2079
17de50b7 2080int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2081{
2082 /* The GPIO should be swapped if swap register is set and active */
2083 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2084 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2085 int gpio_shift = gpio_num +
2086 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2087 u32 gpio_mask = (1 << gpio_shift);
2088 u32 gpio_reg;
a2fbb9ea 2089
c18487ee
YR		 2090 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2091 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2092 return -EINVAL;
2093 }
a2fbb9ea 2094
4a37fb66 2095 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2096 /* read GPIO and mask except the float bits */
2097 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2098
c18487ee
YR		 2099 switch (mode) {
2100 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2101 DP(NETIF_MSG_LINK,
2102 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2103 gpio_num, gpio_shift);
2104 /* clear FLOAT and set CLR */
2105 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2106 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2107 break;
a2fbb9ea 2108
c18487ee 2109 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2110 DP(NETIF_MSG_LINK,
2111 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2112 gpio_num, gpio_shift);
2113 /* clear FLOAT and set SET */
2114 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2115 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2116 break;
a2fbb9ea 2117
17de50b7 2118 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2119 DP(NETIF_MSG_LINK,
2120 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2121 gpio_num, gpio_shift);
2122 /* set FLOAT */
2123 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2124 break;
a2fbb9ea 2125
c18487ee
YR		 2126 default:
2127 break;
a2fbb9ea
ET		 2128 }
2129
c18487ee 2130 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2131 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2132
c18487ee 2133 return 0;
a2fbb9ea
ET		 2134}
2135
0d40f0d4
YR		 2136int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2137{
2138 u32 gpio_reg = 0;
2139 int rc = 0;
2140
2141 /* Any port swapping should be handled by caller. */
2142
2143 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2144 /* read GPIO and mask except the float bits */
2145 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2146 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2147 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2148 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2149
2150 switch (mode) {
2151 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2152 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2153 /* set CLR */
2154 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2155 break;
2156
2157 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2158 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2159 /* set SET */
2160 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2161 break;
2162
2163 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2164 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2165 /* set FLOAT */
2166 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2167 break;
2168
2169 default:
2170 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2171 rc = -EINVAL;
2172 break;
2173 }
2174
2175 if (rc == 0)
2176 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2177
2178 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2179
2180 return rc;
2181}
2182
4acac6a5
EG		 2183int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2184{
2185 /* The GPIO should be swapped if swap register is set and active */
2186 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2187 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2188 int gpio_shift = gpio_num +
2189 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2190 u32 gpio_mask = (1 << gpio_shift);
2191 u32 gpio_reg;
2192
2193 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2194 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2195 return -EINVAL;
2196 }
2197
2198 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199 /* read GPIO int */
2200 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2201
2202 switch (mode) {
2203 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2204 DP(NETIF_MSG_LINK,
2205 "Clear GPIO INT %d (shift %d) -> output low\n",
2206 gpio_num, gpio_shift);
4acac6a5
EG		 2207 /* clear SET and set CLR */
2208 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2209 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2210 break;
2211
2212 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2213 DP(NETIF_MSG_LINK,
2214 "Set GPIO INT %d (shift %d) -> output high\n",
2215 gpio_num, gpio_shift);
4acac6a5
EG		 2216 /* clear CLR and set SET */
2217 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2218 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219 break;
2220
2221 default:
2222 break;
2223 }
2224
2225 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2226 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2227
2228 return 0;
2229}
2230
d6d99a3f 2231static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2232{
c18487ee 2233 u32 spio_reg;
a2fbb9ea 2234
d6d99a3f
YM		 2235 /* Only 2 SPIOs are configurable */
2236 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2237 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2238 return -EINVAL;
a2fbb9ea
ET		 2239 }
2240
4a37fb66 2241 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2242 /* read SPIO and mask except the float bits */
d6d99a3f 2243 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2244
c18487ee 2245 switch (mode) {
d6d99a3f
YM		 2246 case MISC_SPIO_OUTPUT_LOW:
2247 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2248 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2249 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2250 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2251 break;
a2fbb9ea 2252
d6d99a3f
YM		 2253 case MISC_SPIO_OUTPUT_HIGH:
2254 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2255 /* clear FLOAT and set SET */
d6d99a3f
YM		 2256 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2257 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2258 break;
a2fbb9ea 2259
d6d99a3f
YM		 2260 case MISC_SPIO_INPUT_HI_Z:
2261 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2262 /* set FLOAT */
d6d99a3f 2263 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2264 break;
a2fbb9ea 2265
c18487ee
YR		 2266 default:
2267 break;
a2fbb9ea
ET		 2268 }
2269
c18487ee 2270 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2271 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2272
a2fbb9ea
ET		 2273 return 0;
2274}
2275
9f6c9258 2276void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2277{
a22f0788 2278 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2279 switch (bp->link_vars.ieee_fc &
2280 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2281 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2282 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2283 ADVERTISED_Pause);
c18487ee 2284 break;
356e2385 2285
c18487ee 2286 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2287 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2288 ADVERTISED_Pause);
c18487ee 2289 break;
356e2385 2290
c18487ee 2291 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2292 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2293 break;
356e2385 2294
c18487ee 2295 default:
a22f0788 2296 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2297 ADVERTISED_Pause);
c18487ee
YR		 2298 break;
2299 }
2300}
f1410647 2301
cd1dfce2 2302static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2303{
cd1dfce2
YM		 2304 /* Initialize link parameters structure variables
2305 * It is recommended to turn off RX FC for jumbo frames
2306 * for better performance
2307 */
2308 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2309 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2310 else
2311 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2312}
a2fbb9ea 2313
9156b30b
DK		 2314static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2315{
2316 u32 pause_enabled = 0;
2317
2318 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2319 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2320 pause_enabled = 1;
2321
2322 REG_WR(bp, BAR_USTRORM_INTMEM +
2323 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2324 pause_enabled);
2325 }
2326
2327 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2328 pause_enabled ? "enabled" : "disabled");
2329}
2330
cd1dfce2
YM		 2331int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2332{
2333 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2334 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2335
2336 if (!BP_NOMCP(bp)) {
2337 bnx2x_set_requested_fc(bp);
4a37fb66 2338 bnx2x_acquire_phy_lock(bp);
b5bf9068 2339
a22f0788 2340 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2341 struct link_params *lp = &bp->link_params;
2342 lp->loopback_mode = LOOPBACK_XGXS;
2343 /* do PHY loopback at 10G speed, if possible */
2344 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2345 if (lp->speed_cap_mask[cfx_idx] &
2346 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2347 lp->req_line_speed[cfx_idx] =
2348 SPEED_10000;
2349 else
2350 lp->req_line_speed[cfx_idx] =
2351 SPEED_1000;
2352 }
a22f0788 2353 }
b5bf9068 2354
8970b2e4
MS		 2355 if (load_mode == LOAD_LOOPBACK_EXT) {
2356 struct link_params *lp = &bp->link_params;
2357 lp->loopback_mode = LOOPBACK_EXT;
2358 }
2359
19680c48 2360 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2361
4a37fb66 2362 bnx2x_release_phy_lock(bp);
a2fbb9ea 2363
9156b30b
DK		 2364 bnx2x_init_dropless_fc(bp);
2365
3c96c68b
EG		 2366 bnx2x_calc_fc_adv(bp);
2367
cd1dfce2 2368 if (bp->link_vars.link_up) {
b5bf9068 2369 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2370 bnx2x_link_report(bp);
cd1dfce2
YM		 2371 }
2372 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2373 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2374 return rc;
2375 }
f5372251 2376 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2377 return -EINVAL;
a2fbb9ea
ET		 2378}
2379
9f6c9258 2380void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2381{
19680c48 2382 if (!BP_NOMCP(bp)) {
4a37fb66 2383 bnx2x_acquire_phy_lock(bp);
19680c48 2384 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2385 bnx2x_release_phy_lock(bp);
a2fbb9ea 2386
9156b30b
DK		 2387 bnx2x_init_dropless_fc(bp);
2388
19680c48
EG		 2389 bnx2x_calc_fc_adv(bp);
2390 } else
f5372251 2391 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2392}
a2fbb9ea 2393
c18487ee
YR		 2394static void bnx2x__link_reset(struct bnx2x *bp)
2395{
19680c48 2396 if (!BP_NOMCP(bp)) {
4a37fb66 2397 bnx2x_acquire_phy_lock(bp);
5d07d868 2398 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2399 bnx2x_release_phy_lock(bp);
19680c48 2400 } else
f5372251 2401 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2402}
a2fbb9ea 2403
5d07d868
YM		 2404void bnx2x_force_link_reset(struct bnx2x *bp)
2405{
2406 bnx2x_acquire_phy_lock(bp);
2407 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2408 bnx2x_release_phy_lock(bp);
2409}
2410
a22f0788 2411u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2412{
2145a920 2413 u8 rc = 0;
a2fbb9ea 2414
2145a920
VZ		 2415 if (!BP_NOMCP(bp)) {
2416 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2417 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2418 is_serdes);
2145a920
VZ		 2419 bnx2x_release_phy_lock(bp);
2420 } else
2421 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2422
c18487ee
YR		 2423 return rc;
2424}
a2fbb9ea 2425
2691d51d
EG		 2426/* Calculates the sum of vn_min_rates.
2427 It's needed for further normalizing of the min_rates.
2428 Returns:
2429 sum of vn_min_rates.
2430 or
2431 0 - if all the min_rates are 0.
16a5fd92 2432 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2433 If not all min_rates are zero then those that are zeroes will be set to 1.
2434 */
b475d78f
YM		 2435static void bnx2x_calc_vn_min(struct bnx2x *bp,
2436 struct cmng_init_input *input)
2691d51d
EG		 2437{
2438 int all_zero = 1;
2691d51d
EG		 2439 int vn;
2440
3395a033 2441 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2442 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2443 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2444 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2445
2446 /* Skip hidden vns */
2447 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2448 vn_min_rate = 0;
2691d51d 2449 /* If min rate is zero - set it to 1 */
b475d78f 2450 else if (!vn_min_rate)
2691d51d
EG		 2451 vn_min_rate = DEF_MIN_RATE;
2452 else
2453 all_zero = 0;
2454
b475d78f 2455 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2456 }
2457
30ae438b
DK		 2458 /* if ETS or all min rates are zeros - disable fairness */
2459 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2460 input->flags.cmng_enables &=
30ae438b
DK		 2461 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2462 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2463 } else if (all_zero) {
b475d78f 2464 input->flags.cmng_enables &=
b015e3d1 2465 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2466 DP(NETIF_MSG_IFUP,
2467 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2468 } else
b475d78f 2469 input->flags.cmng_enables |=
b015e3d1 2470 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2471}
2472
b475d78f
YM		 2473static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2474 struct cmng_init_input *input)
34f80b04 2475{
b475d78f 2476 u16 vn_max_rate;
f2e0899f 2477 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2478
b475d78f 2479 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2480 vn_max_rate = 0;
b475d78f 2481 else {
faa6fcbb
DK		 2482 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2483
b475d78f 2484 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2485 /* maxCfg in percents of linkspeed */
2486 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2487 } else /* SD modes */
faa6fcbb
DK		 2488 /* maxCfg is absolute in 100Mb units */
2489 vn_max_rate = maxCfg * 100;
34f80b04 2490 }
f85582f8 2491
b475d78f 2492 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2493
b475d78f 2494 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2495}
f85582f8 2496
523224a3
DK		 2497static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2498{
2499 if (CHIP_REV_IS_SLOW(bp))
2500 return CMNG_FNS_NONE;
fb3bff17 2501 if (IS_MF(bp))
523224a3
DK		 2502 return CMNG_FNS_MINMAX;
2503
2504 return CMNG_FNS_NONE;
2505}
2506
2ae17f66 2507void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2508{
0793f83f 2509 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2510
2511 if (BP_NOMCP(bp))
16a5fd92 2512 return; /* what should be the default value in this case */
523224a3 2513
0793f83f
DK		 2514 /* For 2 port configuration the absolute function number formula
2515 * is:
2516 * abs_func = 2 * vn + BP_PORT + BP_PATH
2517 *
2518 * and there are 4 functions per port
2519 *
2520 * For 4 port configuration it is
2521 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2522 *
2523 * and there are 2 functions per port
2524 */
3395a033 2525 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2526 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2527
2528 if (func >= E1H_FUNC_MAX)
2529 break;
2530
f2e0899f 2531 bp->mf_config[vn] =
523224a3
DK		 2532 MF_CFG_RD(bp, func_mf_config[func].config);
2533 }
a3348722
BW		 2534 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2535 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2536 bp->flags |= MF_FUNC_DIS;
2537 } else {
2538 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2539 bp->flags &= ~MF_FUNC_DIS;
2540 }
523224a3
DK		 2541}
2542
2543static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2544{
b475d78f
YM		 2545 struct cmng_init_input input;
2546 memset(&input, 0, sizeof(struct cmng_init_input));
2547
2548 input.port_rate = bp->link_vars.line_speed;
523224a3 2549
568e2426 2550 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2551 int vn;
2552
523224a3
DK		 2553 /* read mf conf from shmem */
2554 if (read_cfg)
2555 bnx2x_read_mf_cfg(bp);
2556
523224a3 2557 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2558 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2559
2560 /* calculate and set min-max rate for each vn */
c4154f25 2561 if (bp->port.pmf)
3395a033 2562 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2563 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2564
2565 /* always enable rate shaping and fairness */
b475d78f 2566 input.flags.cmng_enables |=
523224a3 2567 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2568
2569 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2570 return;
2571 }
2572
2573 /* rate shaping and fairness are disabled */
2574 DP(NETIF_MSG_IFUP,
2575 "rate shaping and fairness are disabled\n");
2576}
34f80b04 2577
1191cb83
ED		 2578static void storm_memset_cmng(struct bnx2x *bp,
2579 struct cmng_init *cmng,
2580 u8 port)
2581{
2582 int vn;
2583 size_t size = sizeof(struct cmng_struct_per_port);
2584
2585 u32 addr = BAR_XSTRORM_INTMEM +
2586 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2587
2588 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2589
2590 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2591 int func = func_by_vn(bp, vn);
2592
2593 addr = BAR_XSTRORM_INTMEM +
2594 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2595 size = sizeof(struct rate_shaping_vars_per_vn);
2596 __storm_memset_struct(bp, addr, size,
2597 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2598
2599 addr = BAR_XSTRORM_INTMEM +
2600 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2601 size = sizeof(struct fairness_vars_per_vn);
2602 __storm_memset_struct(bp, addr, size,
2603 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2604 }
2605}
2606
568e2426
DK		 2607/* init cmng mode in HW according to local configuration */
2608void bnx2x_set_local_cmng(struct bnx2x *bp)
2609{
2610 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2611
2612 if (cmng_fns != CMNG_FNS_NONE) {
2613 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2614 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2615 } else {
2616 /* rate shaping and fairness are disabled */
2617 DP(NETIF_MSG_IFUP,
2618 "single function mode without fairness\n");
2619 }
2620}
2621
c18487ee
YR		 2622/* This function is called upon link interrupt */
2623static void bnx2x_link_attn(struct bnx2x *bp)
2624{
bb2a0f7a
YG		 2625 /* Make sure that we are synced with the current statistics */
2626 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2627
c18487ee 2628 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2629
9156b30b 2630 bnx2x_init_dropless_fc(bp);
1c06328c 2631
9156b30b 2632 if (bp->link_vars.link_up) {
1c06328c 2633
619c5cb6 2634 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2635 struct host_port_stats *pstats;
2636
2637 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2638 /* reset old mac stats */
bb2a0f7a
YG		 2639 memset(&(pstats->mac_stx[0]), 0,
2640 sizeof(struct mac_stx));
2641 }
f34d28ea 2642 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2643 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2644 }
2645
568e2426
DK		 2646 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2647 bnx2x_set_local_cmng(bp);
9fdc3e95 2648
2ae17f66
VZ		 2649 __bnx2x_link_report(bp);
2650
9fdc3e95
DK		 2651 if (IS_MF(bp))
2652 bnx2x_link_sync_notify(bp);
c18487ee 2653}
a2fbb9ea 2654
9f6c9258 2655void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2656{
2ae17f66 2657 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2658 return;
a2fbb9ea 2659
00253a8c 2660 /* read updated dcb configuration */
ad5afc89
AE		 2661 if (IS_PF(bp)) {
2662 bnx2x_dcbx_pmf_update(bp);
2663 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2664 if (bp->link_vars.link_up)
2665 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2666 else
2667 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2668 /* indicate link status */
2669 bnx2x_link_report(bp);
a2fbb9ea 2670
ad5afc89
AE		 2671 } else { /* VF */
2672 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2673 SUPPORTED_10baseT_Full |
2674 SUPPORTED_100baseT_Half |
2675 SUPPORTED_100baseT_Full |
2676 SUPPORTED_1000baseT_Full |
2677 SUPPORTED_2500baseX_Full |
2678 SUPPORTED_10000baseT_Full |
2679 SUPPORTED_TP |
2680 SUPPORTED_FIBRE |
2681 SUPPORTED_Autoneg |
2682 SUPPORTED_Pause |
2683 SUPPORTED_Asym_Pause);
2684 bp->port.advertising[0] = bp->port.supported[0];
2685
2686 bp->link_params.bp = bp;
2687 bp->link_params.port = BP_PORT(bp);
2688 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2689 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2690 bp->link_params.req_line_speed[0] = SPEED_10000;
2691 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2692 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2693 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2694 bp->link_vars.line_speed = SPEED_10000;
2695 bp->link_vars.link_status =
2696 (LINK_STATUS_LINK_UP |
2697 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2698 bp->link_vars.link_up = 1;
2699 bp->link_vars.duplex = DUPLEX_FULL;
2700 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2701 __bnx2x_link_report(bp);
bb2a0f7a 2702 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2703 }
a2fbb9ea 2704}
a2fbb9ea 2705
a3348722
BW		 2706static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2707 u16 vlan_val, u8 allowed_prio)
2708{
86564c3f 2709 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2710 struct bnx2x_func_afex_update_params *f_update_params =
2711 &func_params.params.afex_update;
2712
2713 func_params.f_obj = &bp->func_obj;
2714 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2715
2716 /* no need to wait for RAMROD completion, so don't
2717 * set RAMROD_COMP_WAIT flag
2718 */
2719
2720 f_update_params->vif_id = vifid;
2721 f_update_params->afex_default_vlan = vlan_val;
2722 f_update_params->allowed_priorities = allowed_prio;
2723
2724 /* if ramrod can not be sent, response to MCP immediately */
2725 if (bnx2x_func_state_change(bp, &func_params) < 0)
2726 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2727
2728 return 0;
2729}
2730
2731static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2732 u16 vif_index, u8 func_bit_map)
2733{
86564c3f 2734 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2735 struct bnx2x_func_afex_viflists_params *update_params =
2736 &func_params.params.afex_viflists;
2737 int rc;
2738 u32 drv_msg_code;
2739
2740 /* validate only LIST_SET and LIST_GET are received from switch */
2741 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2742 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2743 cmd_type);
2744
2745 func_params.f_obj = &bp->func_obj;
2746 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2747
2748 /* set parameters according to cmd_type */
2749 update_params->afex_vif_list_command = cmd_type;
86564c3f 2750 update_params->vif_list_index = vif_index;
a3348722
BW		 2751 update_params->func_bit_map =
2752 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2753 update_params->func_to_clear = 0;
2754 drv_msg_code =
2755 (cmd_type == VIF_LIST_RULE_GET) ?
2756 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2757 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2758
2759 /* if ramrod can not be sent, respond to MCP immediately for
2760 * SET and GET requests (other are not triggered from MCP)
2761 */
2762 rc = bnx2x_func_state_change(bp, &func_params);
2763 if (rc < 0)
2764 bnx2x_fw_command(bp, drv_msg_code, 0);
2765
2766 return 0;
2767}
2768
2769static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2770{
2771 struct afex_stats afex_stats;
2772 u32 func = BP_ABS_FUNC(bp);
2773 u32 mf_config;
2774 u16 vlan_val;
2775 u32 vlan_prio;
2776 u16 vif_id;
2777 u8 allowed_prio;
2778 u8 vlan_mode;
2779 u32 addr_to_write, vifid, addrs, stats_type, i;
2780
2781 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2782 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2783 DP(BNX2X_MSG_MCP,
2784 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2785 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2786 }
2787
2788 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2789 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2790 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2791 DP(BNX2X_MSG_MCP,
2792 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2793 vifid, addrs);
2794 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2795 addrs);
2796 }
2797
2798 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2799 addr_to_write = SHMEM2_RD(bp,
2800 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2801 stats_type = SHMEM2_RD(bp,
2802 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2803
2804 DP(BNX2X_MSG_MCP,
2805 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2806 addr_to_write);
2807
2808 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2809
2810 /* write response to scratchpad, for MCP */
2811 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2812 REG_WR(bp, addr_to_write + i*sizeof(u32),
2813 *(((u32 *)(&afex_stats))+i));
2814
2815 /* send ack message to MCP */
2816 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2817 }
2818
2819 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2820 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2821 bp->mf_config[BP_VN(bp)] = mf_config;
2822 DP(BNX2X_MSG_MCP,
2823 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2824 mf_config);
2825
2826 /* if VIF_SET is "enabled" */
2827 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2828 /* set rate limit directly to internal RAM */
2829 struct cmng_init_input cmng_input;
2830 struct rate_shaping_vars_per_vn m_rs_vn;
2831 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2832 u32 addr = BAR_XSTRORM_INTMEM +
2833 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2834
2835 bp->mf_config[BP_VN(bp)] = mf_config;
2836
2837 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2838 m_rs_vn.vn_counter.rate =
2839 cmng_input.vnic_max_rate[BP_VN(bp)];
2840 m_rs_vn.vn_counter.quota =
2841 (m_rs_vn.vn_counter.rate *
2842 RS_PERIODIC_TIMEOUT_USEC) / 8;
2843
2844 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2845
2846 /* read relevant values from mf_cfg struct in shmem */
2847 vif_id =
2848 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2849 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2850 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2851 vlan_val =
2852 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2853 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2854 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2855 vlan_prio = (mf_config &
2856 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2857 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2858 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2859 vlan_mode =
2860 (MF_CFG_RD(bp,
2861 func_mf_config[func].afex_config) &
2862 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2863 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2864 allowed_prio =
2865 (MF_CFG_RD(bp,
2866 func_mf_config[func].afex_config) &
2867 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2868 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2869
2870 /* send ramrod to FW, return in case of failure */
2871 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2872 allowed_prio))
2873 return;
2874
2875 bp->afex_def_vlan_tag = vlan_val;
2876 bp->afex_vlan_mode = vlan_mode;
2877 } else {
2878 /* notify link down because BP->flags is disabled */
2879 bnx2x_link_report(bp);
2880
2881 /* send INVALID VIF ramrod to FW */
2882 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2883
2884 /* Reset the default afex VLAN */
2885 bp->afex_def_vlan_tag = -1;
2886 }
2887 }
2888}
2889
34f80b04
EG		 2890static void bnx2x_pmf_update(struct bnx2x *bp)
2891{
2892 int port = BP_PORT(bp);
2893 u32 val;
2894
2895 bp->port.pmf = 1;
51c1a580 2896 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2897
3deb8167
YR		 2898 /*
2899 * We need the mb() to ensure the ordering between the writing to
2900 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2901 */
2902 smp_mb();
2903
2904 /* queue a periodic task */
2905 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2906
ef01854e
DK		 2907 bnx2x_dcbx_pmf_update(bp);
2908
34f80b04 2909 /* enable nig attention */
3395a033 2910 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2911 if (bp->common.int_block == INT_BLOCK_HC) {
2912 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2913 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2914 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2915 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2916 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2917 }
bb2a0f7a
YG		 2918
2919 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2920}
2921
c18487ee 2922/* end of Link */
a2fbb9ea
ET		 2923
2924/* slow path */
2925
2926/*
2927 * General service functions
2928 */
2929
2691d51d 2930/* send the MCP a request, block until there is a reply */
a22f0788 2931u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2932{
f2e0899f 2933 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2934 u32 seq;
2691d51d
EG		 2935 u32 rc = 0;
2936 u32 cnt = 1;
2937 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2938
c4ff7cbf 2939 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2940 seq = ++bp->fw_seq;
f2e0899f
DK		 2941 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2942 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2943
754a2f52
DK		 2944 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2945 (command | seq), param);
2691d51d
EG		 2946
2947 do {
2948 /* let the FW do it's magic ... */
2949 msleep(delay);
2950
f2e0899f 2951 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2952
c4ff7cbf
EG		 2953 /* Give the FW up to 5 second (500*10ms) */
2954 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2955
2956 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2957 cnt*delay, rc, seq);
2958
2959 /* is this a reply to our command? */
2960 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2961 rc &= FW_MSG_CODE_MASK;
2962 else {
2963 /* FW BUG! */
2964 BNX2X_ERR("FW failed to respond!\n");
2965 bnx2x_fw_dump(bp);
2966 rc = 0;
2967 }
c4ff7cbf 2968 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2969
2970 return rc;
2971}
2972
1191cb83
ED		 2973static void storm_memset_func_cfg(struct bnx2x *bp,
2974 struct tstorm_eth_function_common_config *tcfg,
2975 u16 abs_fid)
2976{
2977 size_t size = sizeof(struct tstorm_eth_function_common_config);
2978
2979 u32 addr = BAR_TSTRORM_INTMEM +
2980 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2981
2982 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2983}
2984
619c5cb6
VZ		 2985void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2986{
2987 if (CHIP_IS_E1x(bp)) {
2988 struct tstorm_eth_function_common_config tcfg = {0};
2989
2990 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2991 }
2992
2993 /* Enable the function in the FW */
2994 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2995 storm_memset_func_en(bp, p->func_id, 1);
2996
2997 /* spq */
2998 if (p->func_flgs & FUNC_FLG_SPQ) {
2999 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3000 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3001 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3002 }
3003}
3004
6383c0b3 3005/**
16a5fd92 3006 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3007 *
3008 * @bp device handle
3009 * @fp queue handle
3010 * @zero_stats TRUE if statistics zeroing is needed
3011 *
3012 * Return the flags that are common for the Tx-only and not normal connections.
3013 */
1191cb83
ED		 3014static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3015 struct bnx2x_fastpath *fp,
3016 bool zero_stats)
28912902 3017{
619c5cb6
VZ		 3018 unsigned long flags = 0;
3019
3020 /* PF driver will always initialize the Queue to an ACTIVE state */
3021 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3022
6383c0b3 3023 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3024 * parent connection). The statistics are zeroed when the parent
3025 * connection is initialized.
6383c0b3 3026 */
50f0a562
BW		 3027
3028 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3029 if (zero_stats)
3030 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3031
c14db202
YM		 3032 if (bp->flags & TX_SWITCHING)
3033 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3034
91226790 3035 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3036 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3037
823e1d90
YM		 3038#ifdef BNX2X_STOP_ON_ERROR
3039 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3040#endif
3041
6383c0b3
AE		 3042 return flags;
3043}
3044
1191cb83
ED		 3045static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3046 struct bnx2x_fastpath *fp,
3047 bool leading)
6383c0b3
AE		 3048{
3049 unsigned long flags = 0;
3050
619c5cb6
VZ		 3051 /* calculate other queue flags */
3052 if (IS_MF_SD(bp))
3053 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3054
a3348722 3055 if (IS_FCOE_FP(fp)) {
619c5cb6 3056 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3057 /* For FCoE - force usage of default priority (for afex) */
3058 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3059 }
523224a3 3060
f5219d8e 3061 if (!fp->disable_tpa) {
619c5cb6 3062 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3063 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3064 if (fp->mode == TPA_MODE_GRO)
3065 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3066 }
619c5cb6 3067
619c5cb6
VZ		 3068 if (leading) {
3069 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3070 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3071 }
523224a3 3072
619c5cb6
VZ		 3073 /* Always set HW VLAN stripping */
3074 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3075
a3348722
BW		 3076 /* configure silent vlan removal */
3077 if (IS_MF_AFEX(bp))
3078 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3079
6383c0b3 3080 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3081}
3082
619c5cb6 3083static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3084 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3085 u8 cos)
619c5cb6
VZ		 3086{
3087 gen_init->stat_id = bnx2x_stats_id(fp);
3088 gen_init->spcl_id = fp->cl_id;
3089
3090 /* Always use mini-jumbo MTU for FCoE L2 ring */
3091 if (IS_FCOE_FP(fp))
3092 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3093 else
3094 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3095
3096 gen_init->cos = cos;
619c5cb6
VZ		 3097}
3098
3099static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3100 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3101 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3102{
619c5cb6 3103 u8 max_sge = 0;
523224a3
DK		 3104 u16 sge_sz = 0;
3105 u16 tpa_agg_size = 0;
3106
523224a3 3107 if (!fp->disable_tpa) {
dfacf138
DK		 3108 pause->sge_th_lo = SGE_TH_LO(bp);
3109 pause->sge_th_hi = SGE_TH_HI(bp);
3110
3111 /* validate SGE ring has enough to cross high threshold */
3112 WARN_ON(bp->dropless_fc &&
3113 pause->sge_th_hi + FW_PREFETCH_CNT >
3114 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3115
924d75ab 3116 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3117 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3118 SGE_PAGE_SHIFT;
3119 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3120 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3121 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3122 }
3123
3124 /* pause - not for e1 */
3125 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3126 pause->bd_th_lo = BD_TH_LO(bp);
3127 pause->bd_th_hi = BD_TH_HI(bp);
3128
3129 pause->rcq_th_lo = RCQ_TH_LO(bp);
3130 pause->rcq_th_hi = RCQ_TH_HI(bp);
3131 /*
3132 * validate that rings have enough entries to cross
3133 * high thresholds
3134 */
3135 WARN_ON(bp->dropless_fc &&
3136 pause->bd_th_hi + FW_PREFETCH_CNT >
3137 bp->rx_ring_size);
3138 WARN_ON(bp->dropless_fc &&
3139 pause->rcq_th_hi + FW_PREFETCH_CNT >
3140 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3141
523224a3
DK		 3142 pause->pri_map = 1;
3143 }
3144
3145 /* rxq setup */
523224a3
DK		 3146 rxq_init->dscr_map = fp->rx_desc_mapping;
3147 rxq_init->sge_map = fp->rx_sge_mapping;
3148 rxq_init->rcq_map = fp->rx_comp_mapping;
3149 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3150
619c5cb6
VZ		 3151 /* This should be a maximum number of data bytes that may be
3152 * placed on the BD (not including paddings).
3153 */
e52fcb24 3154 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3155 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3156
523224a3 3157 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3158 rxq_init->tpa_agg_sz = tpa_agg_size;
3159 rxq_init->sge_buf_sz = sge_sz;
3160 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3161 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3162 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3163
3164 /* Maximum number or simultaneous TPA aggregation for this Queue.
3165 *
2de67439 3166 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3167 * VF driver(s) may want to define it to a smaller value.
3168 */
dfacf138 3169 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3170
523224a3
DK		 3171 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3172 rxq_init->fw_sb_id = fp->fw_sb_id;
3173
ec6ba945
VZ		 3174 if (IS_FCOE_FP(fp))
3175 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3176 else
6383c0b3 3177 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3178 /* configure silent vlan removal
3179 * if multi function mode is afex, then mask default vlan
3180 */
3181 if (IS_MF_AFEX(bp)) {
3182 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3183 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3184 }
523224a3
DK		 3185}
3186
619c5cb6 3187static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3188 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3189 u8 cos)
523224a3 3190{
65565884 3191 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3192 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3193 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3194 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3195
619c5cb6 3196 /*
16a5fd92 3197 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3198 * leading RSS client id
3199 */
3200 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3201
ec6ba945
VZ		 3202 if (IS_FCOE_FP(fp)) {
3203 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3204 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3205 }
523224a3
DK		 3206}
3207
8d96286a 3208static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3209{
3210 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 3211 struct event_ring_data eq_data = { {0} };
3212 u16 flags;
3213
619c5cb6 3214 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3215 /* reset IGU PF statistics: MSIX + ATTN */
3216 /* PF */
3217 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3218 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3219 (CHIP_MODE_IS_4_PORT(bp) ?
3220 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3221 /* ATTN */
3222 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3223 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3224 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3225 (CHIP_MODE_IS_4_PORT(bp) ?
3226 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3227 }
3228
523224a3
DK		 3229 /* function setup flags */
3230 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3231
619c5cb6
VZ		 3232 /* This flag is relevant for E1x only.
3233 * E2 doesn't have a TPA configuration in a function level.
523224a3 3234 */
619c5cb6 3235 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 3236
3237 func_init.func_flgs = flags;
3238 func_init.pf_id = BP_FUNC(bp);
3239 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3240 func_init.spq_map = bp->spq_mapping;
3241 func_init.spq_prod = bp->spq_prod_idx;
3242
3243 bnx2x_func_init(bp, &func_init);
3244
3245 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3246
3247 /*
619c5cb6
VZ		 3248 * Congestion management values depend on the link rate
3249 * There is no active link so initial link rate is set to 10 Gbps.
3250 * When the link comes up The congestion management values are
3251 * re-calculated according to the actual link rate.
3252 */
523224a3
DK		 3253 bp->link_vars.line_speed = SPEED_10000;
3254 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3255
3256 /* Only the PMF sets the HW */
3257 if (bp->port.pmf)
3258 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3259
86564c3f 3260 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3261 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3262 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3263 eq_data.producer = bp->eq_prod;
3264 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3265 eq_data.sb_id = DEF_SB_ID;
3266 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3267}
3268
523224a3
DK		 3269static void bnx2x_e1h_disable(struct bnx2x *bp)
3270{
3271 int port = BP_PORT(bp);
3272
619c5cb6 3273 bnx2x_tx_disable(bp);
523224a3
DK		 3274
3275 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3276}
3277
3278static void bnx2x_e1h_enable(struct bnx2x *bp)
3279{
3280 int port = BP_PORT(bp);
3281
3282 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3283
16a5fd92 3284 /* Tx queue should be only re-enabled */
523224a3
DK		 3285 netif_tx_wake_all_queues(bp->dev);
3286
3287 /*
3288 * Should not call netif_carrier_on since it will be called if the link
3289 * is up when checking for link state
3290 */
3291}
3292
1d187b34
BW		 3293#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3294
3295static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3296{
3297 struct eth_stats_info *ether_stat =
3298 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3299 struct bnx2x_vlan_mac_obj *mac_obj =
3300 &bp->sp_objs->mac_obj;
3301 int i;
1d187b34 3302
786fdf0b
DC		 3303 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3304 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3305
3ec9f9ca
AE		 3306 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3307 * mac_local field in ether_stat struct. The base address is offset by 2
3308 * bytes to account for the field being 8 bytes but a mac address is
3309 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3310 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3311 * allocated by the ether_stat struct, so the macs will land in their
3312 * proper positions.
3313 */
3314 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3315 memset(ether_stat->mac_local + i, 0,
3316 sizeof(ether_stat->mac_local[0]));
3317 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3318 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3319 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3320 ETH_ALEN);
1d187b34 3321 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3322 if (bp->dev->features & NETIF_F_RXCSUM)
3323 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3324 if (bp->dev->features & NETIF_F_TSO)
3325 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3326 ether_stat->feature_flags |= bp->common.boot_mode;
3327
3328 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3329
3330 ether_stat->txq_size = bp->tx_ring_size;
3331 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3332
fcf93a0a 3333#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3334 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3335#endif
1d187b34
BW		 3336}
3337
3338static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3339{
3340 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3341 struct fcoe_stats_info *fcoe_stat =
3342 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3343
55c11941
MS		 3344 if (!CNIC_LOADED(bp))
3345 return;
3346
3ec9f9ca 3347 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3348
3349 fcoe_stat->qos_priority =
3350 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3351
3352 /* insert FCoE stats from ramrod response */
3353 if (!NO_FCOE(bp)) {
3354 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3355 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3356 tstorm_queue_statistics;
3357
3358 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3359 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3360 xstorm_queue_statistics;
3361
3362 struct fcoe_statistics_params *fw_fcoe_stat =
3363 &bp->fw_stats_data->fcoe;
3364
86564c3f
YM		 3365 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3366 fcoe_stat->rx_bytes_lo,
3367 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3368
86564c3f
YM		 3369 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3370 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3371 fcoe_stat->rx_bytes_lo,
3372 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3373
86564c3f
YM		 3374 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3375 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3376 fcoe_stat->rx_bytes_lo,
3377 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3378
86564c3f
YM		 3379 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3380 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3381 fcoe_stat->rx_bytes_lo,
3382 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3383
86564c3f
YM		 3384 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3385 fcoe_stat->rx_frames_lo,
3386 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3387
86564c3f
YM		 3388 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3389 fcoe_stat->rx_frames_lo,
3390 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3391
86564c3f
YM		 3392 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3393 fcoe_stat->rx_frames_lo,
3394 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3395
86564c3f
YM		 3396 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3397 fcoe_stat->rx_frames_lo,
3398 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3399
86564c3f
YM		 3400 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3401 fcoe_stat->tx_bytes_lo,
3402 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3403
86564c3f
YM		 3404 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3405 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3406 fcoe_stat->tx_bytes_lo,
3407 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3408
86564c3f
YM		 3409 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3410 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3411 fcoe_stat->tx_bytes_lo,
3412 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3413
86564c3f
YM		 3414 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3415 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3416 fcoe_stat->tx_bytes_lo,
3417 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3418
86564c3f
YM		 3419 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3420 fcoe_stat->tx_frames_lo,
3421 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3422
86564c3f
YM		 3423 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3424 fcoe_stat->tx_frames_lo,
3425 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3426
86564c3f
YM		 3427 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3428 fcoe_stat->tx_frames_lo,
3429 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3430
86564c3f
YM		 3431 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3432 fcoe_stat->tx_frames_lo,
3433 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3434 }
3435
1d187b34
BW		 3436 /* ask L5 driver to add data to the struct */
3437 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3438}
3439
3440static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3441{
3442 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3443 struct iscsi_stats_info *iscsi_stat =
3444 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3445
55c11941
MS		 3446 if (!CNIC_LOADED(bp))
3447 return;
3448
3ec9f9ca
AE		 3449 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3450 ETH_ALEN);
1d187b34
BW		 3451
3452 iscsi_stat->qos_priority =
3453 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3454
1d187b34
BW		 3455 /* ask L5 driver to add data to the struct */
3456 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3457}
3458
0793f83f
DK		 3459/* called due to MCP event (on pmf):
3460 * reread new bandwidth configuration
3461 * configure FW
3462 * notify others function about the change
3463 */
1191cb83 3464static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3465{
3466 if (bp->link_vars.link_up) {
3467 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3468 bnx2x_link_sync_notify(bp);
3469 }
3470 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3471}
3472
1191cb83 3473static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3474{
3475 bnx2x_config_mf_bw(bp);
3476 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3477}
3478
c8c60d88
YM		 3479static void bnx2x_handle_eee_event(struct bnx2x *bp)
3480{
3481 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3482 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3483}
3484
1d187b34
BW		 3485static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3486{
3487 enum drv_info_opcode op_code;
3488 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3489
3490 /* if drv_info version supported by MFW doesn't match - send NACK */
3491 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3492 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3493 return;
3494 }
3495
3496 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3497 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3498
3499 memset(&bp->slowpath->drv_info_to_mcp, 0,
3500 sizeof(union drv_info_to_mcp));
3501
3502 switch (op_code) {
3503 case ETH_STATS_OPCODE:
3504 bnx2x_drv_info_ether_stat(bp);
3505 break;
3506 case FCOE_STATS_OPCODE:
3507 bnx2x_drv_info_fcoe_stat(bp);
3508 break;
3509 case ISCSI_STATS_OPCODE:
3510 bnx2x_drv_info_iscsi_stat(bp);
3511 break;
3512 default:
3513 /* if op code isn't supported - send NACK */
3514 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3515 return;
3516 }
3517
3518 /* if we got drv_info attn from MFW then these fields are defined in
3519 * shmem2 for sure
3520 */
3521 SHMEM2_WR(bp, drv_info_host_addr_lo,
3522 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3523 SHMEM2_WR(bp, drv_info_host_addr_hi,
3524 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3525
3526 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3527}
3528
523224a3
DK		 3529static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3530{
3531 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3532
3533 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3534
3535 /*
3536 * This is the only place besides the function initialization
3537 * where the bp->flags can change so it is done without any
3538 * locks
3539 */
f2e0899f 3540 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3541 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3542 bp->flags |= MF_FUNC_DIS;
3543
3544 bnx2x_e1h_disable(bp);
3545 } else {
51c1a580 3546 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3547 bp->flags &= ~MF_FUNC_DIS;
3548
3549 bnx2x_e1h_enable(bp);
3550 }
3551 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3552 }
3553 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3554 bnx2x_config_mf_bw(bp);
523224a3
DK		 3555 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3556 }
3557
3558 /* Report results to MCP */
3559 if (dcc_event)
3560 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3561 else
3562 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3563}
3564
3565/* must be called under the spq lock */
1191cb83 3566static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3567{
3568 struct eth_spe *next_spe = bp->spq_prod_bd;
3569
3570 if (bp->spq_prod_bd == bp->spq_last_bd) {
3571 bp->spq_prod_bd = bp->spq;
3572 bp->spq_prod_idx = 0;
51c1a580 3573 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3574 } else {
3575 bp->spq_prod_bd++;
3576 bp->spq_prod_idx++;
3577 }
3578 return next_spe;
3579}
3580
3581/* must be called under the spq lock */
1191cb83 3582static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3583{
3584 int func = BP_FUNC(bp);
3585
53e51e2f
VZ		 3586 /*
3587 * Make sure that BD data is updated before writing the producer:
3588 * BD data is written to the memory, the producer is read from the
3589 * memory, thus we need a full memory barrier to ensure the ordering.
3590 */
3591 mb();
28912902 3592
523224a3 3593 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3594 bp->spq_prod_idx);
28912902
MC		 3595 mmiowb();
3596}
3597
619c5cb6
VZ		 3598/**
3599 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3600 *
3601 * @cmd: command to check
3602 * @cmd_type: command type
3603 */
1191cb83 3604static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3605{
3606 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3607 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3608 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3609 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3610 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3611 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3612 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3613 return true;
3614 else
3615 return false;
619c5cb6
VZ		 3616}
3617
619c5cb6
VZ		 3618/**
3619 * bnx2x_sp_post - place a single command on an SP ring
3620 *
3621 * @bp: driver handle
3622 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3623 * @cid: SW CID the command is related to
3624 * @data_hi: command private data address (high 32 bits)
3625 * @data_lo: command private data address (low 32 bits)
3626 * @cmd_type: command type (e.g. NONE, ETH)
3627 *
3628 * SP data is handled as if it's always an address pair, thus data fields are
3629 * not swapped to little endian in upper functions. Instead this function swaps
3630 * data as if it's two u32 fields.
3631 */
9f6c9258 3632int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3633 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3634{
28912902 3635 struct eth_spe *spe;
523224a3 3636 u16 type;
619c5cb6 3637 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3638
a2fbb9ea 3639#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3640 if (unlikely(bp->panic)) {
3641 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3642 return -EIO;
51c1a580 3643 }
a2fbb9ea
ET		 3644#endif
3645
34f80b04 3646 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3647
6e30dd4e
VZ		 3648 if (common) {
3649 if (!atomic_read(&bp->eq_spq_left)) {
3650 BNX2X_ERR("BUG! EQ ring full!\n");
3651 spin_unlock_bh(&bp->spq_lock);
3652 bnx2x_panic();
3653 return -EBUSY;
3654 }
3655 } else if (!atomic_read(&bp->cq_spq_left)) {
3656 BNX2X_ERR("BUG! SPQ ring full!\n");
3657 spin_unlock_bh(&bp->spq_lock);
3658 bnx2x_panic();
3659 return -EBUSY;
a2fbb9ea 3660 }
f1410647 3661
28912902
MC		 3662 spe = bnx2x_sp_get_next(bp);
3663
a2fbb9ea 3664 /* CID needs port number to be encoded int it */
28912902 3665 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3666 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3667 HW_CID(bp, cid));
523224a3 3668
14a94ebd
MK		 3669 /* In some cases, type may already contain the func-id
3670 * mainly in SRIOV related use cases, so we add it here only
3671 * if it's not already set.
3672 */
3673 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3674 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3675 SPE_HDR_CONN_TYPE;
3676 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3677 SPE_HDR_FUNCTION_ID);
3678 } else {
3679 type = cmd_type;
3680 }
a2fbb9ea 3681
523224a3
DK		 3682 spe->hdr.type = cpu_to_le16(type);
3683
3684 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3685 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3686
d6cae238
VZ		 3687 /*
3688 * It's ok if the actual decrement is issued towards the memory
3689 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3690 * more explicit memory barrier is needed.
d6cae238
VZ		 3691 */
3692 if (common)
3693 atomic_dec(&bp->eq_spq_left);
3694 else
3695 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3696
51c1a580
MS		 3697 DP(BNX2X_MSG_SP,
3698 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3699 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3700 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3701 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3702 HW_CID(bp, cid), data_hi, data_lo, type,
3703 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3704
28912902 3705 bnx2x_sp_prod_update(bp);
34f80b04 3706 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3707 return 0;
3708}
3709
3710/* acquire split MCP access lock register */
4a37fb66 3711static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3712{
72fd0718 3713 u32 j, val;
34f80b04 3714 int rc = 0;
a2fbb9ea
ET		 3715
3716 might_sleep();
72fd0718 3717 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3718 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3719 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3720 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3721 break;
3722
639d65b8 3723 usleep_range(5000, 10000);
a2fbb9ea 3724 }
3cdeec22 3725 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3726 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3727 rc = -EBUSY;
3728 }
3729
3730 return rc;
3731}
3732
4a37fb66
YG		 3733/* release split MCP access lock register */
3734static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3735{
3cdeec22 3736 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3737}
3738
523224a3
DK		 3739#define BNX2X_DEF_SB_ATT_IDX 0x0001
3740#define BNX2X_DEF_SB_IDX 0x0002
3741
1191cb83 3742static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3743{
523224a3 3744 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3745 u16 rc = 0;
3746
3747 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3748 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3749 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3750 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3751 }
523224a3
DK		 3752
3753 if (bp->def_idx != def_sb->sp_sb.running_index) {
3754 bp->def_idx = def_sb->sp_sb.running_index;
3755 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3756 }
523224a3 3757
16a5fd92 3758 /* Do not reorder: indices reading should complete before handling */
523224a3 3759 barrier();
a2fbb9ea
ET		 3760 return rc;
3761}
3762
3763/*
3764 * slow path service functions
3765 */
3766
3767static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3768{
34f80b04 3769 int port = BP_PORT(bp);
a2fbb9ea
ET		 3770 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3771 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3772 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3773 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3774 u32 aeu_mask;
87942b46 3775 u32 nig_mask = 0;
f2e0899f 3776 u32 reg_addr;
a2fbb9ea 3777
a2fbb9ea
ET		 3778 if (bp->attn_state & asserted)
3779 BNX2X_ERR("IGU ERROR\n");
3780
3fcaf2e5
EG		 3781 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3782 aeu_mask = REG_RD(bp, aeu_addr);
3783
a2fbb9ea 3784 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3785 aeu_mask, asserted);
72fd0718 3786 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3787 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3788
3fcaf2e5
EG		 3789 REG_WR(bp, aeu_addr, aeu_mask);
3790 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3791
3fcaf2e5 3792 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3793 bp->attn_state |= asserted;
3fcaf2e5 3794 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3795
3796 if (asserted & ATTN_HARD_WIRED_MASK) {
3797 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3798
a5e9a7cf
EG		 3799 bnx2x_acquire_phy_lock(bp);
3800
877e9aa4 3801 /* save nig interrupt mask */
87942b46 3802 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3803
361c391e
YR		 3804 /* If nig_mask is not set, no need to call the update
3805 * function.
3806 */
3807 if (nig_mask) {
3808 REG_WR(bp, nig_int_mask_addr, 0);
3809
3810 bnx2x_link_attn(bp);
3811 }
a2fbb9ea
ET		 3812
3813 /* handle unicore attn? */
3814 }
3815 if (asserted & ATTN_SW_TIMER_4_FUNC)
3816 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3817
3818 if (asserted & GPIO_2_FUNC)
3819 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3820
3821 if (asserted & GPIO_3_FUNC)
3822 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3823
3824 if (asserted & GPIO_4_FUNC)
3825 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3826
3827 if (port == 0) {
3828 if (asserted & ATTN_GENERAL_ATTN_1) {
3829 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3830 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3831 }
3832 if (asserted & ATTN_GENERAL_ATTN_2) {
3833 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3834 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3835 }
3836 if (asserted & ATTN_GENERAL_ATTN_3) {
3837 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3838 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3839 }
3840 } else {
3841 if (asserted & ATTN_GENERAL_ATTN_4) {
3842 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3843 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3844 }
3845 if (asserted & ATTN_GENERAL_ATTN_5) {
3846 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3847 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3848 }
3849 if (asserted & ATTN_GENERAL_ATTN_6) {
3850 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3851 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3852 }
3853 }
3854
3855 } /* if hardwired */
3856
f2e0899f
DK		 3857 if (bp->common.int_block == INT_BLOCK_HC)
3858 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3859 COMMAND_REG_ATTN_BITS_SET);
3860 else
3861 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3862
3863 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3864 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3865 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3866
3867 /* now set back the mask */
a5e9a7cf 3868 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 3869 /* Verify that IGU ack through BAR was written before restoring
3870 * NIG mask. This loop should exit after 2-3 iterations max.
3871 */
3872 if (bp->common.int_block != INT_BLOCK_HC) {
3873 u32 cnt = 0, igu_acked;
3874 do {
3875 igu_acked = REG_RD(bp,
3876 IGU_REG_ATTENTION_ACK_BITS);
3877 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3878 (++cnt < MAX_IGU_ATTN_ACK_TO));
3879 if (!igu_acked)
3880 DP(NETIF_MSG_HW,
3881 "Failed to verify IGU ack on time\n");
3882 barrier();
3883 }
87942b46 3884 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3885 bnx2x_release_phy_lock(bp);
3886 }
a2fbb9ea
ET		 3887}
3888
1191cb83 3889static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 3890{
3891 int port = BP_PORT(bp);
b7737c9b 3892 u32 ext_phy_config;
fd4ef40d 3893 /* mark the failure */
b7737c9b
YR		 3894 ext_phy_config =
3895 SHMEM_RD(bp,
3896 dev_info.port_hw_config[port].external_phy_config);
3897
3898 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3899 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3900 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3901 ext_phy_config);
fd4ef40d
EG		 3902
3903 /* log the failure */
51c1a580
MS		 3904 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3905 "Please contact OEM Support for assistance\n");
8304859a 3906
16a5fd92 3907 /* Schedule device reset (unload)
8304859a
AE		 3908 * This is due to some boards consuming sufficient power when driver is
3909 * up to overheat if fan fails.
3910 */
3911 smp_mb__before_clear_bit();
3912 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3913 smp_mb__after_clear_bit();
3914 schedule_delayed_work(&bp->sp_rtnl_task, 0);
fd4ef40d 3915}
ab6ad5a4 3916
1191cb83 3917static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3918{
34f80b04 3919 int port = BP_PORT(bp);
877e9aa4 3920 int reg_offset;
d90d96ba 3921 u32 val;
877e9aa4 3922
34f80b04
EG		 3923 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3924 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3925
34f80b04 3926 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3927
3928 val = REG_RD(bp, reg_offset);
3929 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3930 REG_WR(bp, reg_offset, val);
3931
3932 BNX2X_ERR("SPIO5 hw attention\n");
3933
fd4ef40d 3934 /* Fan failure attention */
d90d96ba 3935 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3936 bnx2x_fan_failure(bp);
877e9aa4 3937 }
34f80b04 3938
3deb8167 3939 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3940 bnx2x_acquire_phy_lock(bp);
3941 bnx2x_handle_module_detect_int(&bp->link_params);
3942 bnx2x_release_phy_lock(bp);
3943 }
3944
34f80b04
EG		 3945 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3946
3947 val = REG_RD(bp, reg_offset);
3948 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3949 REG_WR(bp, reg_offset, val);
3950
3951 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3952 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3953 bnx2x_panic();
3954 }
877e9aa4
ET		 3955}
3956
1191cb83 3957static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 3958{
3959 u32 val;
3960
0626b899 3961 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3962
3963 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3964 BNX2X_ERR("DB hw attention 0x%x\n", val);
3965 /* DORQ discard attention */
3966 if (val & 0x2)
3967 BNX2X_ERR("FATAL error from DORQ\n");
3968 }
34f80b04
EG		 3969
3970 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3971
3972 int port = BP_PORT(bp);
3973 int reg_offset;
3974
3975 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3976 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3977
3978 val = REG_RD(bp, reg_offset);
3979 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3980 REG_WR(bp, reg_offset, val);
3981
3982 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3983 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3984 bnx2x_panic();
3985 }
877e9aa4
ET		 3986}
3987
1191cb83 3988static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 3989{
3990 u32 val;
3991
3992 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3993
3994 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3995 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3996 /* CFC error attention */
3997 if (val & 0x2)
3998 BNX2X_ERR("FATAL error from CFC\n");
3999 }
4000
4001 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4002 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4003 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4004 /* RQ_USDMDP_FIFO_OVERFLOW */
4005 if (val & 0x18000)
4006 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4007
4008 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4009 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4010 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4011 }
877e9aa4 4012 }
34f80b04
EG		 4013
4014 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4015
4016 int port = BP_PORT(bp);
4017 int reg_offset;
4018
4019 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4020 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4021
4022 val = REG_RD(bp, reg_offset);
4023 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4024 REG_WR(bp, reg_offset, val);
4025
4026 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 4027 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 4028 bnx2x_panic();
4029 }
877e9aa4
ET		 4030}
4031
1191cb83 4032static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4033{
34f80b04
EG		 4034 u32 val;
4035
877e9aa4
ET		 4036 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4037
34f80b04
EG		 4038 if (attn & BNX2X_PMF_LINK_ASSERT) {
4039 int func = BP_FUNC(bp);
4040
4041 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4042 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4043 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4044 func_mf_config[BP_ABS_FUNC(bp)].config);
4045 val = SHMEM_RD(bp,
4046 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 4047 if (val & DRV_STATUS_DCC_EVENT_MASK)
4048 bnx2x_dcc_event(bp,
4049 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 4050
4051 if (val & DRV_STATUS_SET_MF_BW)
4052 bnx2x_set_mf_bw(bp);
4053
1d187b34
BW		 4054 if (val & DRV_STATUS_DRV_INFO_REQ)
4055 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4056
4057 if (val & DRV_STATUS_VF_DISABLED)
4058 bnx2x_vf_handle_flr_event(bp);
4059
2691d51d 4060 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4061 bnx2x_pmf_update(bp);
4062
e4901dde 4063 if (bp->port.pmf &&
785b9b1a
SR		 4064 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4065 bp->dcbx_enabled > 0)
e4901dde
VZ		 4066 /* start dcbx state machine */
4067 bnx2x_dcbx_set_params(bp,
4068 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4069 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4070 bnx2x_handle_afex_cmd(bp,
4071 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4072 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4073 bnx2x_handle_eee_event(bp);
3deb8167
YR		 4074 if (bp->link_vars.periodic_flags &
4075 PERIODIC_FLAGS_LINK_EVENT) {
4076 /* sync with link */
4077 bnx2x_acquire_phy_lock(bp);
4078 bp->link_vars.periodic_flags &=
4079 ~PERIODIC_FLAGS_LINK_EVENT;
4080 bnx2x_release_phy_lock(bp);
4081 if (IS_MF(bp))
4082 bnx2x_link_sync_notify(bp);
4083 bnx2x_link_report(bp);
4084 }
4085 /* Always call it here: bnx2x_link_report() will
4086 * prevent the link indication duplication.
4087 */
4088 bnx2x__link_status_update(bp);
34f80b04 4089 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4090
4091 BNX2X_ERR("MC assert!\n");
d6cae238 4092 bnx2x_mc_assert(bp);
877e9aa4
ET		 4093 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4094 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4095 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4096 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4097 bnx2x_panic();
4098
4099 } else if (attn & BNX2X_MCP_ASSERT) {
4100
4101 BNX2X_ERR("MCP assert!\n");
4102 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4103 bnx2x_fw_dump(bp);
877e9aa4
ET		 4104
4105 } else
4106 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4107 }
4108
4109 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4110 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4111 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4112 val = CHIP_IS_E1(bp) ? 0 :
4113 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4114 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4115 }
4116 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4117 val = CHIP_IS_E1(bp) ? 0 :
4118 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4119 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4120 }
877e9aa4 4121 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4122 }
4123}
4124
c9ee9206
VZ		 4125/*
4126 * Bits map:
4127 * 0-7 - Engine0 load counter.
4128 * 8-15 - Engine1 load counter.
4129 * 16 - Engine0 RESET_IN_PROGRESS bit.
4130 * 17 - Engine1 RESET_IN_PROGRESS bit.
4131 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4132 * on the engine
4133 * 19 - Engine1 ONE_IS_LOADED.
4134 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4135 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4136 * just the one belonging to its engine).
4137 *
4138 */
4139#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4140
4141#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4142#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4143#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4144#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4145#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4146#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4147#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4148
4149/*
4150 * Set the GLOBAL_RESET bit.
4151 *
4152 * Should be run under rtnl lock
4153 */
4154void bnx2x_set_reset_global(struct bnx2x *bp)
4155{
f16da43b
AE		 4156 u32 val;
4157 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4158 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4159 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4160 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4161}
4162
4163/*
4164 * Clear the GLOBAL_RESET bit.
4165 *
4166 * Should be run under rtnl lock
4167 */
1191cb83 4168static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4169{
f16da43b
AE		 4170 u32 val;
4171 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4172 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4173 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4174 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4175}
f85582f8 4176
72fd0718 4177/*
c9ee9206
VZ		 4178 * Checks the GLOBAL_RESET bit.
4179 *
72fd0718
VZ		 4180 * should be run under rtnl lock
4181 */
1191cb83 4182static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4183{
3cdeec22 4184 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4185
4186 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4187 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4188}
4189
4190/*
4191 * Clear RESET_IN_PROGRESS bit for the current engine.
4192 *
4193 * Should be run under rtnl lock
4194 */
1191cb83 4195static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4196{
f16da43b 4197 u32 val;
c9ee9206
VZ		 4198 u32 bit = BP_PATH(bp) ?
4199 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4200 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4201 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4202
4203 /* Clear the bit */
4204 val &= ~bit;
4205 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4206
4207 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4208}
4209
4210/*
c9ee9206
VZ		 4211 * Set RESET_IN_PROGRESS for the current engine.
4212 *
72fd0718
VZ		 4213 * should be run under rtnl lock
4214 */
c9ee9206 4215void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4216{
f16da43b 4217 u32 val;
c9ee9206
VZ		 4218 u32 bit = BP_PATH(bp) ?
4219 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4220 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4221 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4222
4223 /* Set the bit */
4224 val |= bit;
4225 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4226 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4227}
4228
4229/*
c9ee9206 4230 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4231 * should be run under rtnl lock
4232 */
c9ee9206 4233bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4234{
3cdeec22 4235 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4236 u32 bit = engine ?
4237 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4238
4239 /* return false if bit is set */
4240 return (val & bit) ? false : true;
72fd0718
VZ		 4241}
4242
4243/*
889b9af3 4244 * set pf load for the current pf.
c9ee9206 4245 *
72fd0718
VZ		 4246 * should be run under rtnl lock
4247 */
889b9af3 4248void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4249{
f16da43b 4250 u32 val1, val;
c9ee9206
VZ		 4251 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4252 BNX2X_PATH0_LOAD_CNT_MASK;
4253 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4254 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4255
f16da43b
AE		 4256 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4257 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4258
51c1a580 4259 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4260
c9ee9206
VZ		 4261 /* get the current counter value */
4262 val1 = (val & mask) >> shift;
4263
889b9af3
AE		 4264 /* set bit of that PF */
4265 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4266
4267 /* clear the old value */
4268 val &= ~mask;
4269
4270 /* set the new one */
4271 val |= ((val1 << shift) & mask);
4272
4273 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4274 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4275}
4276
c9ee9206 4277/**
889b9af3 4278 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4279 *
4280 * @bp: driver handle
4281 *
4282 * Should be run under rtnl lock.
4283 * Decrements the load counter for the current engine. Returns
889b9af3 4284 * whether other functions are still loaded
72fd0718 4285 */
889b9af3 4286bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4287{
f16da43b 4288 u32 val1, val;
c9ee9206
VZ		 4289 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4290 BNX2X_PATH0_LOAD_CNT_MASK;
4291 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4292 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4293
f16da43b
AE		 4294 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4295 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4296 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4297
c9ee9206
VZ		 4298 /* get the current counter value */
4299 val1 = (val & mask) >> shift;
4300
889b9af3
AE		 4301 /* clear bit of that PF */
4302 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4303
4304 /* clear the old value */
4305 val &= ~mask;
4306
4307 /* set the new one */
4308 val |= ((val1 << shift) & mask);
4309
4310 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4311 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4312 return val1 != 0;
72fd0718
VZ		 4313}
4314
4315/*
889b9af3 4316 * Read the load status for the current engine.
c9ee9206 4317 *
72fd0718
VZ		 4318 * should be run under rtnl lock
4319 */
1191cb83 4320static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4321{
c9ee9206
VZ		 4322 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4323 BNX2X_PATH0_LOAD_CNT_MASK);
4324 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4325 BNX2X_PATH0_LOAD_CNT_SHIFT);
4326 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4327
51c1a580 4328 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4329
4330 val = (val & mask) >> shift;
4331
51c1a580
MS		 4332 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4333 engine, val);
c9ee9206 4334
889b9af3 4335 return val != 0;
72fd0718
VZ		 4336}
4337
6bf07b8e
YM		 4338static void _print_parity(struct bnx2x *bp, u32 reg)
4339{
4340 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4341}
4342
1191cb83 4343static void _print_next_block(int idx, const char *blk)
72fd0718 4344{
f1deab50 4345 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4346}
4347
4293b9f5
DK		 4348static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4349 int *par_num, bool print)
72fd0718 4350{
4293b9f5
DK		 4351 u32 cur_bit;
4352 bool res;
4353 int i;
4354
4355 res = false;
4356
72fd0718 4357 for (i = 0; sig; i++) {
4293b9f5 4358 cur_bit = (0x1UL << i);
72fd0718 4359 if (sig & cur_bit) {
4293b9f5
DK		 4360 res |= true; /* Each bit is real error! */
4361
4362 if (print) {
4363 switch (cur_bit) {
4364 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4365 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4366 _print_parity(bp,
4367 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4368 break;
4369 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4370 _print_next_block((*par_num)++,
4371 "PARSER");
6bf07b8e 4372 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4373 break;
4374 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4375 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4376 _print_parity(bp,
4377 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4378 break;
4379 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4380 _print_next_block((*par_num)++,
c9ee9206 4381 "SEARCHER");
6bf07b8e 4382 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4383 break;
4384 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4385 _print_next_block((*par_num)++, "TCM");
4386 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4387 break;
4388 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4389 _print_next_block((*par_num)++,
4390 "TSEMI");
6bf07b8e
YM		 4391 _print_parity(bp,
4392 TSEM_REG_TSEM_PRTY_STS_0);
4393 _print_parity(bp,
4394 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4395 break;
4396 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4397 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4398 _print_parity(bp, GRCBASE_XPB +
4399 PB_REG_PB_PRTY_STS);
4293b9f5 4400 break;
6bf07b8e 4401 }
72fd0718
VZ		 4402 }
4403
4404 /* Clear the bit */
4405 sig &= ~cur_bit;
4406 }
4407 }
4408
4293b9f5 4409 return res;
72fd0718
VZ		 4410}
4411
4293b9f5
DK		 4412static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4413 int *par_num, bool *global,
6bf07b8e 4414 bool print)
72fd0718 4415{
4293b9f5
DK		 4416 u32 cur_bit;
4417 bool res;
4418 int i;
4419
4420 res = false;
4421
72fd0718 4422 for (i = 0; sig; i++) {
4293b9f5 4423 cur_bit = (0x1UL << i);
72fd0718 4424 if (sig & cur_bit) {
4293b9f5 4425 res |= true; /* Each bit is real error! */
72fd0718 4426 switch (cur_bit) {
c9ee9206 4427 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4428 if (print) {
4293b9f5 4429 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4430 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4431 }
72fd0718
VZ		 4432 break;
4433 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4434 if (print) {
4293b9f5 4435 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4436 _print_parity(bp, QM_REG_QM_PRTY_STS);
4437 }
c9ee9206
VZ		 4438 break;
4439 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4440 if (print) {
4293b9f5 4441 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4442 _print_parity(bp, TM_REG_TM_PRTY_STS);
4443 }
72fd0718
VZ		 4444 break;
4445 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4446 if (print) {
4293b9f5 4447 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4448 _print_parity(bp,
4449 XSDM_REG_XSDM_PRTY_STS);
4450 }
c9ee9206
VZ		 4451 break;
4452 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4453 if (print) {
4293b9f5 4454 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4455 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4456 }
72fd0718
VZ		 4457 break;
4458 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4459 if (print) {
4293b9f5
DK		 4460 _print_next_block((*par_num)++,
4461 "XSEMI");
6bf07b8e
YM		 4462 _print_parity(bp,
4463 XSEM_REG_XSEM_PRTY_STS_0);
4464 _print_parity(bp,
4465 XSEM_REG_XSEM_PRTY_STS_1);
4466 }
72fd0718
VZ		 4467 break;
4468 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4469 if (print) {
4293b9f5 4470 _print_next_block((*par_num)++,
c9ee9206 4471 "DOORBELLQ");
6bf07b8e
YM		 4472 _print_parity(bp,
4473 DORQ_REG_DORQ_PRTY_STS);
4474 }
c9ee9206
VZ		 4475 break;
4476 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4477 if (print) {
4293b9f5 4478 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4479 if (CHIP_IS_E1x(bp)) {
4480 _print_parity(bp,
4481 NIG_REG_NIG_PRTY_STS);
4482 } else {
4483 _print_parity(bp,
4484 NIG_REG_NIG_PRTY_STS_0);
4485 _print_parity(bp,
4486 NIG_REG_NIG_PRTY_STS_1);
4487 }
4488 }
72fd0718
VZ		 4489 break;
4490 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4491 if (print)
4293b9f5 4492 _print_next_block((*par_num)++,
c9ee9206
VZ		 4493 "VAUX PCI CORE");
4494 *global = true;
72fd0718
VZ		 4495 break;
4496 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4497 if (print) {
4293b9f5
DK		 4498 _print_next_block((*par_num)++,
4499 "DEBUG");
6bf07b8e
YM		 4500 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4501 }
72fd0718
VZ		 4502 break;
4503 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4504 if (print) {
4293b9f5 4505 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4506 _print_parity(bp,
4507 USDM_REG_USDM_PRTY_STS);
4508 }
72fd0718 4509 break;
8736c826 4510 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4511 if (print) {
4293b9f5 4512 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4513 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4514 }
8736c826 4515 break;
72fd0718 4516 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4517 if (print) {
4293b9f5
DK		 4518 _print_next_block((*par_num)++,
4519 "USEMI");
6bf07b8e
YM		 4520 _print_parity(bp,
4521 USEM_REG_USEM_PRTY_STS_0);
4522 _print_parity(bp,
4523 USEM_REG_USEM_PRTY_STS_1);
4524 }
72fd0718
VZ		 4525 break;
4526 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4527 if (print) {
4293b9f5 4528 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4529 _print_parity(bp, GRCBASE_UPB +
4530 PB_REG_PB_PRTY_STS);
4531 }
72fd0718
VZ		 4532 break;
4533 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4534 if (print) {
4293b9f5 4535 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4536 _print_parity(bp,
4537 CSDM_REG_CSDM_PRTY_STS);
4538 }
72fd0718 4539 break;
8736c826 4540 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4541 if (print) {
4293b9f5 4542 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4543 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4544 }
8736c826 4545 break;
72fd0718
VZ		 4546 }
4547
4548 /* Clear the bit */
4549 sig &= ~cur_bit;
4550 }
4551 }
4552
4293b9f5 4553 return res;
72fd0718
VZ		 4554}
4555
4293b9f5
DK		 4556static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4557 int *par_num, bool print)
72fd0718 4558{
4293b9f5
DK		 4559 u32 cur_bit;
4560 bool res;
4561 int i;
4562
4563 res = false;
4564
72fd0718 4565 for (i = 0; sig; i++) {
4293b9f5 4566 cur_bit = (0x1UL << i);
72fd0718 4567 if (sig & cur_bit) {
4293b9f5
DK		 4568 res |= true; /* Each bit is real error! */
4569 if (print) {
4570 switch (cur_bit) {
4571 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4572 _print_next_block((*par_num)++,
4573 "CSEMI");
6bf07b8e
YM		 4574 _print_parity(bp,
4575 CSEM_REG_CSEM_PRTY_STS_0);
4576 _print_parity(bp,
4577 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4578 break;
4579 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4580 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4581 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4582 _print_parity(bp,
4583 PXP2_REG_PXP2_PRTY_STS_0);
4584 _print_parity(bp,
4585 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4586 break;
4587 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4588 _print_next_block((*par_num)++,
4589 "PXPPCICLOCKCLIENT");
4590 break;
4591 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4592 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4593 _print_parity(bp,
4594 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4595 break;
4596 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4597 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4598 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4599 break;
4600 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4601 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4602 _print_parity(bp,
4603 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4604 break;
4605 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4606 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4607 if (CHIP_IS_E1x(bp))
4608 _print_parity(bp,
4609 HC_REG_HC_PRTY_STS);
4610 else
4611 _print_parity(bp,
4612 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4613 break;
4614 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4615 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4616 _print_parity(bp,
4617 MISC_REG_MISC_PRTY_STS);
4293b9f5 4618 break;
6bf07b8e 4619 }
72fd0718
VZ		 4620 }
4621
4622 /* Clear the bit */
4623 sig &= ~cur_bit;
4624 }
4625 }
4626
4293b9f5 4627 return res;
72fd0718
VZ		 4628}
4629
4293b9f5
DK		 4630static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4631 int *par_num, bool *global,
4632 bool print)
72fd0718 4633{
4293b9f5
DK		 4634 bool res = false;
4635 u32 cur_bit;
4636 int i;
4637
72fd0718 4638 for (i = 0; sig; i++) {
4293b9f5 4639 cur_bit = (0x1UL << i);
72fd0718
VZ		 4640 if (sig & cur_bit) {
4641 switch (cur_bit) {
4642 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4643 if (print)
4293b9f5
DK		 4644 _print_next_block((*par_num)++,
4645 "MCP ROM");
c9ee9206 4646 *global = true;
4293b9f5 4647 res |= true;
72fd0718
VZ		 4648 break;
4649 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4650 if (print)
4293b9f5 4651 _print_next_block((*par_num)++,
c9ee9206
VZ		 4652 "MCP UMP RX");
4653 *global = true;
4293b9f5 4654 res |= true;
72fd0718
VZ		 4655 break;
4656 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4657 if (print)
4293b9f5 4658 _print_next_block((*par_num)++,
c9ee9206
VZ		 4659 "MCP UMP TX");
4660 *global = true;
4293b9f5 4661 res |= true;
72fd0718
VZ		 4662 break;
4663 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206 4664 if (print)
4293b9f5 4665 _print_next_block((*par_num)++,
c9ee9206 4666 "MCP SCPAD");
4293b9f5
DK		 4667 /* clear latched SCPAD PATIRY from MCP */
4668 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4669 1UL << 10);
72fd0718
VZ		 4670 break;
4671 }
4672
4673 /* Clear the bit */
4674 sig &= ~cur_bit;
4675 }
4676 }
4677
4293b9f5 4678 return res;
72fd0718
VZ		 4679}
4680
4293b9f5
DK		 4681static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4682 int *par_num, bool print)
8736c826 4683{
4293b9f5
DK		 4684 u32 cur_bit;
4685 bool res;
4686 int i;
4687
4688 res = false;
4689
8736c826 4690 for (i = 0; sig; i++) {
4293b9f5 4691 cur_bit = (0x1UL << i);
8736c826 4692 if (sig & cur_bit) {
4293b9f5
DK		 4693 res |= true; /* Each bit is real error! */
4694 if (print) {
4695 switch (cur_bit) {
4696 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4697 _print_next_block((*par_num)++,
4698 "PGLUE_B");
6bf07b8e 4699 _print_parity(bp,
4293b9f5
DK		 4700 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4701 break;
4702 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4703 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4704 _print_parity(bp,
4705 ATC_REG_ATC_PRTY_STS);
4293b9f5 4706 break;
6bf07b8e 4707 }
8736c826 4708 }
8736c826
VZ		 4709 /* Clear the bit */
4710 sig &= ~cur_bit;
4711 }
4712 }
4713
4293b9f5 4714 return res;
8736c826
VZ		 4715}
4716
1191cb83
ED		 4717static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4718 u32 *sig)
72fd0718 4719{
4293b9f5
DK		 4720 bool res = false;
4721
8736c826
VZ		 4722 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4723 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4724 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4725 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4726 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4727 int par_num = 0;
51c1a580
MS		 4728 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4729 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4730 sig[0] & HW_PRTY_ASSERT_SET_0,
4731 sig[1] & HW_PRTY_ASSERT_SET_1,
4732 sig[2] & HW_PRTY_ASSERT_SET_2,
4733 sig[3] & HW_PRTY_ASSERT_SET_3,
4734 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4735 if (print)
4736 netdev_err(bp->dev,
4737 "Parity errors detected in blocks: ");
4293b9f5
DK		 4738 res |= bnx2x_check_blocks_with_parity0(bp,
4739 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4740 res |= bnx2x_check_blocks_with_parity1(bp,
4741 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4742 res |= bnx2x_check_blocks_with_parity2(bp,
4743 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4744 res |= bnx2x_check_blocks_with_parity3(bp,
4745 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4746 res |= bnx2x_check_blocks_with_parity4(bp,
4747 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4748
c9ee9206
VZ		 4749 if (print)
4750 pr_cont("\n");
4293b9f5 4751 }
8736c826 4752
4293b9f5 4753 return res;
72fd0718
VZ		 4754}
4755
c9ee9206
VZ		 4756/**
4757 * bnx2x_chk_parity_attn - checks for parity attentions.
4758 *
4759 * @bp: driver handle
4760 * @global: true if there was a global attention
4761 * @print: show parity attention in syslog
4762 */
4763bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4764{
8736c826 4765 struct attn_route attn = { {0} };
72fd0718
VZ		 4766 int port = BP_PORT(bp);
4767
4768 attn.sig[0] = REG_RD(bp,
4769 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4770 port*4);
4771 attn.sig[1] = REG_RD(bp,
4772 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4773 port*4);
4774 attn.sig[2] = REG_RD(bp,
4775 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4776 port*4);
4777 attn.sig[3] = REG_RD(bp,
4778 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4779 port*4);
0a5ccb75
YM		 4780 /* Since MCP attentions can't be disabled inside the block, we need to
4781 * read AEU registers to see whether they're currently disabled
4782 */
4783 attn.sig[3] &= ((REG_RD(bp,
4784 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4785 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4786 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4787 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 4788
8736c826
VZ		 4789 if (!CHIP_IS_E1x(bp))
4790 attn.sig[4] = REG_RD(bp,
4791 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4792 port*4);
4793
4794 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4795}
4796
1191cb83 4797static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 4798{
4799 u32 val;
4800 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4801
4802 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4803 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4804 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4805 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4806 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4807 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4808 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4809 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4810 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4811 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4812 if (val &
4813 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4814 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4815 if (val &
4816 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4817 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4818 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4819 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4820 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4821 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4822 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4823 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4824 }
4825 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4826 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4827 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4828 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4829 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4830 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4831 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4832 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4833 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4834 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4835 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4836 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4837 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4838 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4839 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4840 }
4841
4842 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4843 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4844 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4845 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4846 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4847 }
f2e0899f
DK		 4848}
4849
72fd0718
VZ		 4850static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4851{
4852 struct attn_route attn, *group_mask;
34f80b04 4853 int port = BP_PORT(bp);
877e9aa4 4854 int index;
a2fbb9ea
ET		 4855 u32 reg_addr;
4856 u32 val;
3fcaf2e5 4857 u32 aeu_mask;
c9ee9206 4858 bool global = false;
a2fbb9ea
ET		 4859
4860 /* need to take HW lock because MCP or other port might also
4861 try to handle this event */
4a37fb66 4862 bnx2x_acquire_alr(bp);
a2fbb9ea 4863
c9ee9206
VZ		 4864 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4865#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4866 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4867 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4868 /* Disable HW interrupts */
4869 bnx2x_int_disable(bp);
72fd0718
VZ		 4870 /* In case of parity errors don't handle attentions so that
4871 * other function would "see" parity errors.
4872 */
c9ee9206
VZ		 4873#else
4874 bnx2x_panic();
4875#endif
4876 bnx2x_release_alr(bp);
72fd0718
VZ		 4877 return;
4878 }
4879
a2fbb9ea
ET		 4880 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4881 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4882 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4883 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4884 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4885 attn.sig[4] =
4886 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4887 else
4888 attn.sig[4] = 0;
4889
4890 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4891 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4892
4893 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4894 if (deasserted & (1 << index)) {
72fd0718 4895 group_mask = &bp->attn_group[index];
a2fbb9ea 4896
51c1a580 4897 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 4898 index,
4899 group_mask->sig[0], group_mask->sig[1],
4900 group_mask->sig[2], group_mask->sig[3],
4901 group_mask->sig[4]);
a2fbb9ea 4902
f2e0899f
DK		 4903 bnx2x_attn_int_deasserted4(bp,
4904 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4905 bnx2x_attn_int_deasserted3(bp,
72fd0718 4906 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4907 bnx2x_attn_int_deasserted1(bp,
72fd0718 4908 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4909 bnx2x_attn_int_deasserted2(bp,
72fd0718 4910 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4911 bnx2x_attn_int_deasserted0(bp,
72fd0718 4912 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4913 }
4914 }
4915
4a37fb66 4916 bnx2x_release_alr(bp);
a2fbb9ea 4917
f2e0899f
DK		 4918 if (bp->common.int_block == INT_BLOCK_HC)
4919 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4920 COMMAND_REG_ATTN_BITS_CLR);
4921 else
4922 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4923
4924 val = ~deasserted;
f2e0899f
DK		 4925 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4926 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4927 REG_WR(bp, reg_addr, val);
a2fbb9ea 4928
a2fbb9ea 4929 if (~bp->attn_state & deasserted)
3fcaf2e5 4930 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4931
4932 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4933 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4934
3fcaf2e5
EG		 4935 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4936 aeu_mask = REG_RD(bp, reg_addr);
4937
4938 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4939 aeu_mask, deasserted);
72fd0718 4940 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4941 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4942
3fcaf2e5
EG		 4943 REG_WR(bp, reg_addr, aeu_mask);
4944 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4945
4946 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4947 bp->attn_state &= ~deasserted;
4948 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4949}
4950
4951static void bnx2x_attn_int(struct bnx2x *bp)
4952{
4953 /* read local copy of bits */
68d59484
EG		 4954 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4955 attn_bits);
4956 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4957 attn_bits_ack);
a2fbb9ea
ET		 4958 u32 attn_state = bp->attn_state;
4959
4960 /* look for changed bits */
4961 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4962 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4963
4964 DP(NETIF_MSG_HW,
4965 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4966 attn_bits, attn_ack, asserted, deasserted);
4967
4968 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4969 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4970
4971 /* handle bits that were raised */
4972 if (asserted)
4973 bnx2x_attn_int_asserted(bp, asserted);
4974
4975 if (deasserted)
4976 bnx2x_attn_int_deasserted(bp, deasserted);
4977}
4978
619c5cb6
VZ		 4979void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4980 u16 index, u8 op, u8 update)
4981{
dc1ba591
AE		 4982 u32 igu_addr = bp->igu_base_addr;
4983 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 4984 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4985 igu_addr);
4986}
4987
1191cb83 4988static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 4989{
4990 /* No memory barriers */
4991 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4992 mmiowb(); /* keep prod updates ordered */
4993}
4994
523224a3
DK		 4995static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4996 union event_ring_elem *elem)
4997{
619c5cb6
VZ		 4998 u8 err = elem->message.error;
4999
523224a3 5000 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5001 (cid < bp->cnic_eth_dev.starting_cid &&
5002 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5003 return 1;
5004
5005 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5006
619c5cb6
VZ		 5007 if (unlikely(err)) {
5008
523224a3
DK		 5009 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5010 cid);
823e1d90 5011 bnx2x_panic_dump(bp, false);
523224a3 5012 }
619c5cb6 5013 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5014 return 0;
5015}
523224a3 5016
1191cb83 5017static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5018{
5019 struct bnx2x_mcast_ramrod_params rparam;
5020 int rc;
5021
5022 memset(&rparam, 0, sizeof(rparam));
5023
5024 rparam.mcast_obj = &bp->mcast_obj;
5025
5026 netif_addr_lock_bh(bp->dev);
5027
5028 /* Clear pending state for the last command */
5029 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5030
5031 /* If there are pending mcast commands - send them */
5032 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5033 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5034 if (rc < 0)
5035 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5036 rc);
5037 }
5038
5039 netif_addr_unlock_bh(bp->dev);
5040}
5041
1191cb83
ED		 5042static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5043 union event_ring_elem *elem)
619c5cb6
VZ		 5044{
5045 unsigned long ramrod_flags = 0;
5046 int rc = 0;
5047 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5048 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5049
5050 /* Always push next commands out, don't wait here */
5051 __set_bit(RAMROD_CONT, &ramrod_flags);
5052
86564c3f
YM		 5053 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5054 >> BNX2X_SWCID_SHIFT) {
619c5cb6 5055 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5056 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5057 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5058 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5059 else
15192a8c 5060 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6
VZ		 5061
5062 break;
619c5cb6 5063 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5064 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5065 /* This is only relevant for 57710 where multicast MACs are
5066 * configured as unicast MACs using the same ramrod.
5067 */
5068 bnx2x_handle_mcast_eqe(bp);
5069 return;
5070 default:
5071 BNX2X_ERR("Unsupported classification command: %d\n",
5072 elem->message.data.eth_event.echo);
5073 return;
5074 }
5075
5076 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5077
5078 if (rc < 0)
5079 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5080 else if (rc > 0)
5081 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5082}
5083
619c5cb6 5084static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5085
1191cb83 5086static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5087{
5088 netif_addr_lock_bh(bp->dev);
5089
5090 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5091
5092 /* Send rx_mode command again if was requested */
5093 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5094 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5095 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5096 &bp->sp_state))
5097 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5098 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5099 &bp->sp_state))
5100 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5101
5102 netif_addr_unlock_bh(bp->dev);
5103}
5104
1191cb83 5105static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5106 union event_ring_elem *elem)
5107{
5108 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5109 DP(BNX2X_MSG_SP,
5110 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5111 elem->message.data.vif_list_event.func_bit_map);
5112 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5113 elem->message.data.vif_list_event.func_bit_map);
5114 } else if (elem->message.data.vif_list_event.echo ==
5115 VIF_LIST_RULE_SET) {
5116 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5117 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5118 }
5119}
5120
5121/* called with rtnl_lock */
1191cb83 5122static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5123{
5124 int q, rc;
5125 struct bnx2x_fastpath *fp;
5126 struct bnx2x_queue_state_params queue_params = {NULL};
5127 struct bnx2x_queue_update_params *q_update_params =
5128 &queue_params.params.update;
5129
2de67439 5130 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5131 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5132
5133 /* set silent vlan removal values according to vlan mode */
5134 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5135 &q_update_params->update_flags);
5136 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5137 &q_update_params->update_flags);
5138 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5139
5140 /* in access mode mark mask and value are 0 to strip all vlans */
5141 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5142 q_update_params->silent_removal_value = 0;
5143 q_update_params->silent_removal_mask = 0;
5144 } else {
5145 q_update_params->silent_removal_value =
5146 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5147 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5148 }
5149
5150 for_each_eth_queue(bp, q) {
5151 /* Set the appropriate Queue object */
5152 fp = &bp->fp[q];
15192a8c 5153 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5154
5155 /* send the ramrod */
5156 rc = bnx2x_queue_state_change(bp, &queue_params);
5157 if (rc < 0)
5158 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5159 q);
5160 }
5161
fea75645 5162 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5163 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5164 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5165
5166 /* clear pending completion bit */
5167 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5168
5169 /* mark latest Q bit */
5170 smp_mb__before_clear_bit();
5171 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5172 smp_mb__after_clear_bit();
5173
5174 /* send Q update ramrod for FCoE Q */
5175 rc = bnx2x_queue_state_change(bp, &queue_params);
5176 if (rc < 0)
5177 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5178 q);
5179 } else {
5180 /* If no FCoE ring - ACK MCP now */
5181 bnx2x_link_report(bp);
5182 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5183 }
a3348722
BW		 5184}
5185
1191cb83 5186static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5187 struct bnx2x *bp, u32 cid)
5188{
94f05b0f 5189 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5190
5191 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5192 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5193 else
15192a8c 5194 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5195}
5196
523224a3
DK		 5197static void bnx2x_eq_int(struct bnx2x *bp)
5198{
5199 u16 hw_cons, sw_cons, sw_prod;
5200 union event_ring_elem *elem;
55c11941 5201 u8 echo;
523224a3
DK		 5202 u32 cid;
5203 u8 opcode;
fd1fc79d 5204 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5205 struct bnx2x_queue_sp_obj *q_obj;
5206 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5207 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5208
5209 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5210
5211 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5212 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5213 * condition below will be met. The next element is the size of a
5214 * regular element and hence incrementing by 1
5215 */
5216 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5217 hw_cons++;
5218
25985edc 5219 /* This function may never run in parallel with itself for a
523224a3
DK		 5220 * specific bp, thus there is no need in "paired" read memory
5221 * barrier here.
5222 */
5223 sw_cons = bp->eq_cons;
5224 sw_prod = bp->eq_prod;
5225
d6cae238 5226 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5227 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5228
5229 for (; sw_cons != hw_cons;
5230 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5231
523224a3
DK		 5232 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5233
fd1fc79d
AE		 5234 rc = bnx2x_iov_eq_sp_event(bp, elem);
5235 if (!rc) {
5236 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5237 rc);
5238 goto next_spqe;
5239 }
523224a3 5240
86564c3f
YM		 5241 /* elem CID originates from FW; actually LE */
5242 cid = SW_CID((__force __le32)
5243 elem->message.data.cfc_del_event.cid);
5244 opcode = elem->message.opcode;
523224a3
DK		 5245
5246 /* handle eq element */
5247 switch (opcode) {
fd1fc79d
AE		 5248 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5249 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5250 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5251 continue;
5252
523224a3 5253 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5254 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5255 "got statistics comp event %d\n",
5256 bp->stats_comp++);
523224a3 5257 /* nothing to do with stats comp */
d6cae238 5258 goto next_spqe;
523224a3
DK		 5259
5260 case EVENT_RING_OPCODE_CFC_DEL:
5261 /* handle according to cid range */
5262 /*
5263 * we may want to verify here that the bp state is
5264 * HALTING
5265 */
d6cae238 5266 DP(BNX2X_MSG_SP,
523224a3 5267 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5268
5269 if (CNIC_LOADED(bp) &&
5270 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5271 goto next_spqe;
55c11941 5272
619c5cb6
VZ		 5273 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5274
5275 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5276 break;
5277
523224a3 5278 goto next_spqe;
e4901dde
VZ		 5279
5280 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5281 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5282 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5283 if (f_obj->complete_cmd(bp, f_obj,
5284 BNX2X_F_CMD_TX_STOP))
5285 break;
e4901dde 5286 goto next_spqe;
619c5cb6 5287
e4901dde 5288 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5289 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5290 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5291 if (f_obj->complete_cmd(bp, f_obj,
5292 BNX2X_F_CMD_TX_START))
5293 break;
e4901dde 5294 goto next_spqe;
55c11941 5295
a3348722 5296 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5297 echo = elem->message.data.function_update_event.echo;
5298 if (echo == SWITCH_UPDATE) {
5299 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5300 "got FUNC_SWITCH_UPDATE ramrod\n");
5301 if (f_obj->complete_cmd(
5302 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5303 break;
a3348722 5304
55c11941
MS		 5305 } else {
5306 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5307 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5308 f_obj->complete_cmd(bp, f_obj,
5309 BNX2X_F_CMD_AFEX_UPDATE);
5310
5311 /* We will perform the Queues update from
5312 * sp_rtnl task as all Queue SP operations
5313 * should run under rtnl_lock.
5314 */
5315 smp_mb__before_clear_bit();
5316 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5317 &bp->sp_rtnl_state);
5318 smp_mb__after_clear_bit();
5319
5320 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5321 }
a3348722 5322
a3348722
BW		 5323 goto next_spqe;
5324
5325 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5326 f_obj->complete_cmd(bp, f_obj,
5327 BNX2X_F_CMD_AFEX_VIFLISTS);
5328 bnx2x_after_afex_vif_lists(bp, elem);
5329 goto next_spqe;
619c5cb6 5330 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5331 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5332 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5333 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5334 break;
5335
5336 goto next_spqe;
5337
5338 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5339 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5340 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5341 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5342 break;
5343
5344 goto next_spqe;
523224a3
DK		 5345 }
5346
5347 switch (opcode | bp->state) {
619c5cb6
VZ		 5348 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5349 BNX2X_STATE_OPEN):
5350 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5351 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 5352 cid = elem->message.data.eth_event.echo &
5353 BNX2X_SWCID_MASK;
d6cae238 5354 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5355 cid);
5356 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5357 break;
5358
619c5cb6
VZ		 5359 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5360 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5361 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5362 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5363 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5364 BNX2X_STATE_OPEN):
5365 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5366 BNX2X_STATE_DIAG):
5367 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5368 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5369 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 5370 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5371 break;
5372
619c5cb6
VZ		 5373 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5374 BNX2X_STATE_OPEN):
5375 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5376 BNX2X_STATE_DIAG):
5377 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5378 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5379 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5380 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5381 break;
5382
619c5cb6
VZ		 5383 case (EVENT_RING_OPCODE_FILTERS_RULES |
5384 BNX2X_STATE_OPEN):
5385 case (EVENT_RING_OPCODE_FILTERS_RULES |
5386 BNX2X_STATE_DIAG):
5387 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5388 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5389 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5390 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5391 break;
5392 default:
5393 /* unknown event log error and continue */
619c5cb6
VZ		 5394 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5395 elem->message.opcode, bp->state);
523224a3
DK		 5396 }
5397next_spqe:
5398 spqe_cnt++;
5399 } /* for */
5400
8fe23fbd 5401 smp_mb__before_atomic_inc();
6e30dd4e 5402 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5403
5404 bp->eq_cons = sw_cons;
5405 bp->eq_prod = sw_prod;
5406 /* Make sure that above mem writes were issued towards the memory */
5407 smp_wmb();
5408
5409 /* update producer */
5410 bnx2x_update_eq_prod(bp, bp->eq_prod);
5411}
5412
a2fbb9ea
ET		 5413static void bnx2x_sp_task(struct work_struct *work)
5414{
1cf167f2 5415 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5416
fd1fc79d 5417 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5418
16a5fd92 5419 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5420 smp_rmb();
5421 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5422
fd1fc79d
AE		 5423 /* what work needs to be performed? */
5424 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5425
fd1fc79d
AE		 5426 DP(BNX2X_MSG_SP, "status %x\n", status);
5427 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5428 atomic_set(&bp->interrupt_occurred, 0);
5429
5430 /* HW attentions */
5431 if (status & BNX2X_DEF_SB_ATT_IDX) {
5432 bnx2x_attn_int(bp);
5433 status &= ~BNX2X_DEF_SB_ATT_IDX;
5434 }
5435
5436 /* SP events: STAT_QUERY and others */
5437 if (status & BNX2X_DEF_SB_IDX) {
5438 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5439
55c11941 5440 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5441 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5442 /* Prevent local bottom-halves from running as
5443 * we are going to change the local NAPI list.
5444 */
5445 local_bh_disable();
5446 napi_schedule(&bnx2x_fcoe(bp, napi));
5447 local_bh_enable();
5448 }
5449
5450 /* Handle EQ completions */
5451 bnx2x_eq_int(bp);
5452 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5453 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5454
5455 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5456 }
55c11941 5457
fd1fc79d
AE		 5458 /* if status is non zero then perhaps something went wrong */
5459 if (unlikely(status))
5460 DP(BNX2X_MSG_SP,
5461 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5462
fd1fc79d
AE		 5463 /* ack status block only if something was actually handled */
5464 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5465 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5466 }
5467
fd1fc79d
AE		 5468 /* must be called after the EQ processing (since eq leads to sriov
5469 * ramrod completion flows).
5470 * This flow may have been scheduled by the arrival of a ramrod
5471 * completion, or by the sriov code rescheduling itself.
5472 */
5473 bnx2x_iov_sp_task(bp);
a3348722
BW		 5474
5475 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5476 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5477 &bp->sp_state)) {
5478 bnx2x_link_report(bp);
5479 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5480 }
a2fbb9ea
ET		 5481}
5482
9f6c9258 5483irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5484{
5485 struct net_device *dev = dev_instance;
5486 struct bnx2x *bp = netdev_priv(dev);
5487
523224a3
DK		 5488 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5489 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5490
5491#ifdef BNX2X_STOP_ON_ERROR
5492 if (unlikely(bp->panic))
5493 return IRQ_HANDLED;
5494#endif
5495
55c11941 5496 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5497 struct cnic_ops *c_ops;
5498
5499 rcu_read_lock();
5500 c_ops = rcu_dereference(bp->cnic_ops);
5501 if (c_ops)
5502 c_ops->cnic_handler(bp->cnic_data, NULL);
5503 rcu_read_unlock();
5504 }
55c11941 5505
fd1fc79d
AE		 5506 /* schedule sp task to perform default status block work, ack
5507 * attentions and enable interrupts.
5508 */
5509 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5510
5511 return IRQ_HANDLED;
5512}
5513
5514/* end of slow path */
5515
619c5cb6
VZ		 5516void bnx2x_drv_pulse(struct bnx2x *bp)
5517{
5518 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5519 bp->fw_drv_pulse_wr_seq);
5520}
5521
a2fbb9ea
ET		 5522static void bnx2x_timer(unsigned long data)
5523{
5524 struct bnx2x *bp = (struct bnx2x *) data;
5525
5526 if (!netif_running(bp->dev))
5527 return;
5528
67c431a5
AE		 5529 if (IS_PF(bp) &&
5530 !BP_NOMCP(bp)) {
f2e0899f 5531 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5532 u16 drv_pulse;
5533 u16 mcp_pulse;
a2fbb9ea
ET		 5534
5535 ++bp->fw_drv_pulse_wr_seq;
5536 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5537 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5538 bnx2x_drv_pulse(bp);
a2fbb9ea 5539
f2e0899f 5540 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5541 MCP_PULSE_SEQ_MASK);
5542 /* The delta between driver pulse and mcp response
4c868664
EG		 5543 * should not get too big. If the MFW is more than 5 pulses
5544 * behind, we should worry about it enough to generate an error
5545 * log.
a2fbb9ea 5546 */
4c868664
EG		 5547 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5548 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5549 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5550 }
5551
f34d28ea 5552 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5553 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5554
abc5a021 5555 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5556 if (IS_VF(bp))
5557 bnx2x_timer_sriov(bp);
78c3bcc5 5558
a2fbb9ea
ET		 5559 mod_timer(&bp->timer, jiffies + bp->current_interval);
5560}
5561
5562/* end of Statistics */
5563
5564/* nic init */
5565
5566/*
5567 * nic init service functions
5568 */
5569
1191cb83 5570static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5571{
523224a3
DK		 5572 u32 i;
5573 if (!(len%4) && !(addr%4))
5574 for (i = 0; i < len; i += 4)
5575 REG_WR(bp, addr + i, fill);
5576 else
5577 for (i = 0; i < len; i++)
5578 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5579}
5580
523224a3 5581/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5582static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5583 int fw_sb_id,
5584 u32 *sb_data_p,
5585 u32 data_size)
34f80b04 5586{
a2fbb9ea 5587 int index;
523224a3
DK		 5588 for (index = 0; index < data_size; index++)
5589 REG_WR(bp, BAR_CSTRORM_INTMEM +
5590 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5591 sizeof(u32)*index,
5592 *(sb_data_p + index));
5593}
a2fbb9ea 5594
1191cb83 5595static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5596{
5597 u32 *sb_data_p;
5598 u32 data_size = 0;
f2e0899f 5599 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5600 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5601
523224a3 5602 /* disable the function first */
619c5cb6 5603 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5604 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5605 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5606 sb_data_e2.common.p_func.vf_valid = false;
5607 sb_data_p = (u32 *)&sb_data_e2;
5608 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5609 } else {
5610 memset(&sb_data_e1x, 0,
5611 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5612 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5613 sb_data_e1x.common.p_func.vf_valid = false;
5614 sb_data_p = (u32 *)&sb_data_e1x;
5615 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5616 }
523224a3 5617 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5618
523224a3
DK		 5619 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5620 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5621 CSTORM_STATUS_BLOCK_SIZE);
5622 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5623 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5624 CSTORM_SYNC_BLOCK_SIZE);
5625}
34f80b04 5626
523224a3 5627/* helper: writes SP SB data to FW */
1191cb83 5628static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5629 struct hc_sp_status_block_data *sp_sb_data)
5630{
5631 int func = BP_FUNC(bp);
5632 int i;
5633 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5634 REG_WR(bp, BAR_CSTRORM_INTMEM +
5635 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5636 i*sizeof(u32),
5637 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5638}
5639
1191cb83 5640static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5641{
5642 int func = BP_FUNC(bp);
523224a3
DK		 5643 struct hc_sp_status_block_data sp_sb_data;
5644 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5645
619c5cb6 5646 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5647 sp_sb_data.p_func.vf_valid = false;
5648
5649 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5650
5651 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5652 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5653 CSTORM_SP_STATUS_BLOCK_SIZE);
5654 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5655 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5656 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5657}
5658
1191cb83 5659static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5660 int igu_sb_id, int igu_seg_id)
5661{
5662 hc_sm->igu_sb_id = igu_sb_id;
5663 hc_sm->igu_seg_id = igu_seg_id;
5664 hc_sm->timer_value = 0xFF;
5665 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5666}
5667
150966ad 5668/* allocates state machine ids. */
1191cb83 5669static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5670{
5671 /* zero out state machine indices */
5672 /* rx indices */
5673 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5674
5675 /* tx indices */
5676 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5677 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5678 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5679 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5680
5681 /* map indices */
5682 /* rx indices */
5683 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5684 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5685
5686 /* tx indices */
5687 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5688 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5689 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5690 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5691 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5692 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5693 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5694 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5695}
5696
b93288d5 5697void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5698 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5699{
523224a3
DK		 5700 int igu_seg_id;
5701
f2e0899f 5702 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5703 struct hc_status_block_data_e1x sb_data_e1x;
5704 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5705 int data_size;
5706 u32 *sb_data_p;
5707
f2e0899f
DK		 5708 if (CHIP_INT_MODE_IS_BC(bp))
5709 igu_seg_id = HC_SEG_ACCESS_NORM;
5710 else
5711 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5712
5713 bnx2x_zero_fp_sb(bp, fw_sb_id);
5714
619c5cb6 5715 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5716 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5717 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5718 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5719 sb_data_e2.common.p_func.vf_id = vfid;
5720 sb_data_e2.common.p_func.vf_valid = vf_valid;
5721 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5722 sb_data_e2.common.same_igu_sb_1b = true;
5723 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5724 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5725 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5726 sb_data_p = (u32 *)&sb_data_e2;
5727 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5728 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5729 } else {
5730 memset(&sb_data_e1x, 0,
5731 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5732 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5733 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5734 sb_data_e1x.common.p_func.vf_id = 0xff;
5735 sb_data_e1x.common.p_func.vf_valid = false;
5736 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5737 sb_data_e1x.common.same_igu_sb_1b = true;
5738 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5739 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5740 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5741 sb_data_p = (u32 *)&sb_data_e1x;
5742 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5743 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5744 }
523224a3
DK		 5745
5746 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5747 igu_sb_id, igu_seg_id);
5748 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5749 igu_sb_id, igu_seg_id);
5750
51c1a580 5751 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 5752
86564c3f 5753 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 5754 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5755}
5756
619c5cb6 5757static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5758 u16 tx_usec, u16 rx_usec)
5759{
6383c0b3 5760 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5761 false, rx_usec);
6383c0b3
AE		 5762 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5763 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5764 tx_usec);
5765 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5766 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5767 tx_usec);
5768 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5769 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5770 tx_usec);
523224a3 5771}
f2e0899f 5772
523224a3
DK		 5773static void bnx2x_init_def_sb(struct bnx2x *bp)
5774{
5775 struct host_sp_status_block *def_sb = bp->def_status_blk;
5776 dma_addr_t mapping = bp->def_status_blk_mapping;
5777 int igu_sp_sb_index;
5778 int igu_seg_id;
34f80b04
EG		 5779 int port = BP_PORT(bp);
5780 int func = BP_FUNC(bp);
f2eaeb58 5781 int reg_offset, reg_offset_en5;
a2fbb9ea 5782 u64 section;
523224a3
DK		 5783 int index;
5784 struct hc_sp_status_block_data sp_sb_data;
5785 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5786
f2e0899f
DK		 5787 if (CHIP_INT_MODE_IS_BC(bp)) {
5788 igu_sp_sb_index = DEF_SB_IGU_ID;
5789 igu_seg_id = HC_SEG_ACCESS_DEF;
5790 } else {
5791 igu_sp_sb_index = bp->igu_dsb_id;
5792 igu_seg_id = IGU_SEG_ACCESS_DEF;
5793 }
a2fbb9ea
ET		 5794
5795 /* ATTN */
523224a3 5796 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5797 atten_status_block);
523224a3 5798 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5799
49d66772
ET		 5800 bp->attn_state = 0;
5801
a2fbb9ea
ET		 5802 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5803 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5804 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5805 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5806 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5807 int sindex;
5808 /* take care of sig[0]..sig[4] */
5809 for (sindex = 0; sindex < 4; sindex++)
5810 bp->attn_group[index].sig[sindex] =
5811 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5812
619c5cb6 5813 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5814 /*
5815 * enable5 is separate from the rest of the registers,
5816 * and therefore the address skip is 4
5817 * and not 16 between the different groups
5818 */
5819 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5820 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5821 else
5822 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5823 }
5824
f2e0899f
DK		 5825 if (bp->common.int_block == INT_BLOCK_HC) {
5826 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5827 HC_REG_ATTN_MSG0_ADDR_L);
5828
5829 REG_WR(bp, reg_offset, U64_LO(section));
5830 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5831 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5832 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5833 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5834 }
a2fbb9ea 5835
523224a3
DK		 5836 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5837 sp_sb);
a2fbb9ea 5838
523224a3 5839 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5840
86564c3f 5841 /* PCI guarantees endianity of regpairs */
619c5cb6 5842 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5843 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5844 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5845 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5846 sp_sb_data.igu_seg_id = igu_seg_id;
5847 sp_sb_data.p_func.pf_id = func;
f2e0899f 5848 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5849 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5850
523224a3 5851 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5852
523224a3 5853 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5854}
5855
9f6c9258 5856void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5857{
a2fbb9ea
ET		 5858 int i;
5859
ec6ba945 5860 for_each_eth_queue(bp, i)
523224a3 5861 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5862 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5863}
5864
a2fbb9ea
ET		 5865static void bnx2x_init_sp_ring(struct bnx2x *bp)
5866{
a2fbb9ea 5867 spin_lock_init(&bp->spq_lock);
6e30dd4e 5868 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5869
a2fbb9ea 5870 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5871 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5872 bp->spq_prod_bd = bp->spq;
5873 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5874}
5875
523224a3 5876static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5877{
5878 int i;
523224a3
DK		 5879 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5880 union event_ring_elem *elem =
5881 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5882
523224a3
DK		 5883 elem->next_page.addr.hi =
5884 cpu_to_le32(U64_HI(bp->eq_mapping +
5885 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5886 elem->next_page.addr.lo =
5887 cpu_to_le32(U64_LO(bp->eq_mapping +
5888 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5889 }
523224a3
DK		 5890 bp->eq_cons = 0;
5891 bp->eq_prod = NUM_EQ_DESC;
5892 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 5893 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 5894 atomic_set(&bp->eq_spq_left,
5895 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5896}
5897
619c5cb6 5898/* called with netif_addr_lock_bh() */
a8f47eb7 5899static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5900 unsigned long rx_mode_flags,
5901 unsigned long rx_accept_flags,
5902 unsigned long tx_accept_flags,
5903 unsigned long ramrod_flags)
ab532cf3 5904{
619c5cb6
VZ		 5905 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5906 int rc;
5907
5908 memset(&ramrod_param, 0, sizeof(ramrod_param));
5909
5910 /* Prepare ramrod parameters */
5911 ramrod_param.cid = 0;
5912 ramrod_param.cl_id = cl_id;
5913 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5914 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5915
619c5cb6
VZ		 5916 ramrod_param.pstate = &bp->sp_state;
5917 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5918
619c5cb6
VZ		 5919 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5920 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5921
5922 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5923
5924 ramrod_param.ramrod_flags = ramrod_flags;
5925 ramrod_param.rx_mode_flags = rx_mode_flags;
5926
5927 ramrod_param.rx_accept_flags = rx_accept_flags;
5928 ramrod_param.tx_accept_flags = tx_accept_flags;
5929
5930 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5931 if (rc < 0) {
5932 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 5933 return rc;
619c5cb6 5934 }
924d75ab
YM		 5935
5936 return 0;
a2fbb9ea
ET		 5937}
5938
86564c3f
YM		 5939static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5940 unsigned long *rx_accept_flags,
5941 unsigned long *tx_accept_flags)
471de716 5942{
924d75ab
YM		 5943 /* Clear the flags first */
5944 *rx_accept_flags = 0;
5945 *tx_accept_flags = 0;
619c5cb6 5946
924d75ab 5947 switch (rx_mode) {
619c5cb6
VZ		 5948 case BNX2X_RX_MODE_NONE:
5949 /*
5950 * 'drop all' supersedes any accept flags that may have been
5951 * passed to the function.
5952 */
5953 break;
5954 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 5955 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5956 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5957 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 5958
5959 /* internal switching mode */
924d75ab
YM		 5960 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5961 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5962 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 5963
5964 break;
5965 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 5966 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5967 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5968 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 5969
5970 /* internal switching mode */
924d75ab
YM		 5971 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5972 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5973 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 5974
5975 break;
5976 case BNX2X_RX_MODE_PROMISC:
16a5fd92 5977 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 5978 * should receive matched and unmatched (in resolution of port)
5979 * unicast packets.
5980 */
924d75ab
YM		 5981 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5982 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5983 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5984 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 5985
5986 /* internal switching mode */
924d75ab
YM		 5987 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5988 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 5989
5990 if (IS_MF_SI(bp))
924d75ab 5991 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 5992 else
924d75ab 5993 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6
VZ		 5994
5995 break;
5996 default:
924d75ab
YM		 5997 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5998 return -EINVAL;
619c5cb6 5999 }
de832a55 6000
924d75ab 6001 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
619c5cb6 6002 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
924d75ab
YM		 6003 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6004 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
34f80b04
EG		 6005 }
6006
924d75ab
YM		 6007 return 0;
6008}
6009
6010/* called with netif_addr_lock_bh() */
a8f47eb7 6011static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6012{
6013 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6014 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6015 int rc;
6016
6017 if (!NO_FCOE(bp))
6018 /* Configure rx_mode of FCoE Queue */
6019 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6020
6021 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6022 &tx_accept_flags);
6023 if (rc)
6024 return rc;
6025
619c5cb6
VZ		 6026 __set_bit(RAMROD_RX, &ramrod_flags);
6027 __set_bit(RAMROD_TX, &ramrod_flags);
6028
924d75ab
YM		 6029 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6030 rx_accept_flags, tx_accept_flags,
6031 ramrod_flags);
619c5cb6
VZ		 6032}
6033
6034static void bnx2x_init_internal_common(struct bnx2x *bp)
6035{
6036 int i;
6037
523224a3
DK		 6038 /* Zero this manually as its initialization is
6039 currently missing in the initTool */
6040 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6041 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6042 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6043 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6044 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6045 CHIP_INT_MODE_IS_BC(bp) ?
6046 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6047 }
523224a3 6048}
8a1c38d1 6049
471de716
EG		 6050static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6051{
6052 switch (load_code) {
6053 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6054 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6055 bnx2x_init_internal_common(bp);
6056 /* no break */
6057
6058 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6059 /* nothing to do */
471de716
EG		 6060 /* no break */
6061
6062 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6063 /* internal memory per function is
6064 initialized inside bnx2x_pf_init */
471de716
EG		 6065 break;
6066
6067 default:
6068 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6069 break;
6070 }
6071}
6072
619c5cb6 6073static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6074{
55c11941 6075 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6076}
523224a3 6077
619c5cb6
VZ		 6078static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6079{
55c11941 6080 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6081}
6082
1191cb83 6083static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6084{
6085 if (CHIP_IS_E1x(fp->bp))
6086 return BP_L_ID(fp->bp) + fp->index;
6087 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6088 return bnx2x_fp_igu_sb_id(fp);
6089}
6090
6383c0b3 6091static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6092{
6093 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6094 u8 cos;
619c5cb6 6095 unsigned long q_type = 0;
6383c0b3 6096 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6097 fp->rx_queue = fp_idx;
b3b83c3f 6098 fp->cid = fp_idx;
619c5cb6
VZ		 6099 fp->cl_id = bnx2x_fp_cl_id(fp);
6100 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6101 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6102 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6103 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6104
523224a3 6105 /* init shortcut */
619c5cb6 6106 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6107
16a5fd92 6108 /* Setup SB indices */
523224a3 6109 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6110
619c5cb6
VZ		 6111 /* Configure Queue State object */
6112 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6113 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6114
6115 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6116
6117 /* init tx data */
6118 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6119 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6120 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6121 FP_COS_TO_TXQ(fp, cos, bp),
6122 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6123 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6124 }
6125
ad5afc89
AE		 6126 /* nothing more for vf to do here */
6127 if (IS_VF(bp))
6128 return;
6129
6130 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6131 fp->fw_sb_id, fp->igu_sb_id);
6132 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6133 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6134 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6135 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6136
6137 /**
6138 * Configure classification DBs: Always enable Tx switching
6139 */
6140 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6141
ad5afc89
AE		 6142 DP(NETIF_MSG_IFUP,
6143 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6144 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6145 fp->igu_sb_id);
523224a3
DK		 6146}
6147
1191cb83
ED		 6148static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6149{
6150 int i;
6151
6152 for (i = 1; i <= NUM_TX_RINGS; i++) {
6153 struct eth_tx_next_bd *tx_next_bd =
6154 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6155
6156 tx_next_bd->addr_hi =
6157 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6158 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6159 tx_next_bd->addr_lo =
6160 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6161 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6162 }
6163
639d65b8
YM		 6164 *txdata->tx_cons_sb = cpu_to_le16(0);
6165
1191cb83
ED		 6166 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6167 txdata->tx_db.data.zero_fill1 = 0;
6168 txdata->tx_db.data.prod = 0;
6169
6170 txdata->tx_pkt_prod = 0;
6171 txdata->tx_pkt_cons = 0;
6172 txdata->tx_bd_prod = 0;
6173 txdata->tx_bd_cons = 0;
6174 txdata->tx_pkt = 0;
6175}
6176
55c11941
MS		 6177static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6178{
6179 int i;
6180
6181 for_each_tx_queue_cnic(bp, i)
6182 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6183}
d76a6111 6184
1191cb83
ED		 6185static void bnx2x_init_tx_rings(struct bnx2x *bp)
6186{
6187 int i;
6188 u8 cos;
6189
55c11941 6190 for_each_eth_queue(bp, i)
1191cb83 6191 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6192 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6193}
6194
a8f47eb7 6195static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6196{
6197 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6198 unsigned long q_type = 0;
6199
6200 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6201 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6202 BNX2X_FCOE_ETH_CL_ID_IDX);
6203 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6204 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6205 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6206 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6207 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6208 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6209 fp);
6210
6211 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6212
6213 /* qZone id equals to FW (per path) client id */
6214 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6215 /* init shortcut */
6216 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6217 bnx2x_rx_ustorm_prods_offset(fp);
6218
6219 /* Configure Queue State object */
6220 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6221 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6222
6223 /* No multi-CoS for FCoE L2 client */
6224 BUG_ON(fp->max_cos != 1);
6225
6226 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6227 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6228 bnx2x_sp_mapping(bp, q_rdata), q_type);
6229
6230 DP(NETIF_MSG_IFUP,
6231 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6232 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6233 fp->igu_sb_id);
6234}
6235
55c11941 6236void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6237{
ec6ba945
VZ		 6238 if (!NO_FCOE(bp))
6239 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6240
6241 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6242 BNX2X_VF_ID_INVALID, false,
619c5cb6 6243 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6244
55c11941
MS		 6245 /* ensure status block indices were read */
6246 rmb();
6247 bnx2x_init_rx_rings_cnic(bp);
6248 bnx2x_init_tx_rings_cnic(bp);
6249
6250 /* flush all */
6251 mb();
6252 mmiowb();
6253}
a2fbb9ea 6254
ecf01c22 6255void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6256{
6257 int i;
6258
ecf01c22 6259 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6260 for_each_eth_queue(bp, i)
6261 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6262
6263 /* ensure status block indices were read */
6264 rmb();
6265 bnx2x_init_rx_rings(bp);
6266 bnx2x_init_tx_rings(bp);
6267
ecf01c22
YM		 6268 if (IS_PF(bp)) {
6269 /* Initialize MOD_ABS interrupts */
6270 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6271 bp->common.shmem_base,
6272 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6273
ecf01c22
YM		 6274 /* initialize the default status block and sp ring */
6275 bnx2x_init_def_sb(bp);
6276 bnx2x_update_dsb_idx(bp);
6277 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6278 } else {
6279 bnx2x_memset_stats(bp);
ecf01c22
YM		 6280 }
6281}
16119785 6282
ecf01c22
YM		 6283void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6284{
523224a3 6285 bnx2x_init_eq_ring(bp);
471de716 6286 bnx2x_init_internal(bp, load_code);
523224a3 6287 bnx2x_pf_init(bp);
0ef00459
EG		 6288 bnx2x_stats_init(bp);
6289
0ef00459
EG		 6290 /* flush all before enabling interrupts */
6291 mb();
6292 mmiowb();
6293
615f8fd9 6294 bnx2x_int_enable(bp);
eb8da205
EG		 6295
6296 /* Check for SPIO5 */
6297 bnx2x_attn_int_deasserted0(bp,
6298 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6299 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6300}
6301
ecf01c22 6302/* gzip service functions */
a2fbb9ea
ET		 6303static int bnx2x_gunzip_init(struct bnx2x *bp)
6304{
1a983142
FT		 6305 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6306 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6307 if (bp->gunzip_buf == NULL)
6308 goto gunzip_nomem1;
6309
6310 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6311 if (bp->strm == NULL)
6312 goto gunzip_nomem2;
6313
7ab24bfd 6314 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6315 if (bp->strm->workspace == NULL)
6316 goto gunzip_nomem3;
6317
6318 return 0;
6319
6320gunzip_nomem3:
6321 kfree(bp->strm);
6322 bp->strm = NULL;
6323
6324gunzip_nomem2:
1a983142
FT		 6325 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6326 bp->gunzip_mapping);
a2fbb9ea
ET		 6327 bp->gunzip_buf = NULL;
6328
6329gunzip_nomem1:
51c1a580 6330 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6331 return -ENOMEM;
6332}
6333
6334static void bnx2x_gunzip_end(struct bnx2x *bp)
6335{
b3b83c3f 6336 if (bp->strm) {
7ab24bfd 6337 vfree(bp->strm->workspace);
b3b83c3f
DK		 6338 kfree(bp->strm);
6339 bp->strm = NULL;
6340 }
a2fbb9ea
ET		 6341
6342 if (bp->gunzip_buf) {
1a983142
FT		 6343 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6344 bp->gunzip_mapping);
a2fbb9ea
ET		 6345 bp->gunzip_buf = NULL;
6346 }
6347}
6348
94a78b79 6349static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6350{
6351 int n, rc;
6352
6353 /* check gzip header */
94a78b79
VZ		 6354 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6355 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6356 return -EINVAL;
94a78b79 6357 }
a2fbb9ea
ET		 6358
6359 n = 10;
6360
34f80b04 6361#define FNAME 0x8
a2fbb9ea
ET		 6362
6363 if (zbuf[3] & FNAME)
6364 while ((zbuf[n++] != 0) && (n < len));
6365
94a78b79 6366 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6367 bp->strm->avail_in = len - n;
6368 bp->strm->next_out = bp->gunzip_buf;
6369 bp->strm->avail_out = FW_BUF_SIZE;
6370
6371 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6372 if (rc != Z_OK)
6373 return rc;
6374
6375 rc = zlib_inflate(bp->strm, Z_FINISH);
6376 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6377 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6378 bp->strm->msg);
a2fbb9ea
ET		 6379
6380 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6381 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6382 netdev_err(bp->dev,
6383 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6384 bp->gunzip_outlen);
a2fbb9ea
ET		 6385 bp->gunzip_outlen >>= 2;
6386
6387 zlib_inflateEnd(bp->strm);
6388
6389 if (rc == Z_STREAM_END)
6390 return 0;
6391
6392 return rc;
6393}
6394
6395/* nic load/unload */
6396
6397/*
34f80b04 6398 * General service functions
a2fbb9ea
ET		 6399 */
6400
6401/* send a NIG loopback debug packet */
6402static void bnx2x_lb_pckt(struct bnx2x *bp)
6403{
a2fbb9ea 6404 u32 wb_write[3];
a2fbb9ea
ET		 6405
6406 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6407 wb_write[0] = 0x55555555;
6408 wb_write[1] = 0x55555555;
34f80b04 6409 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6410 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6411
6412 /* NON-IP protocol */
a2fbb9ea
ET		 6413 wb_write[0] = 0x09000000;
6414 wb_write[1] = 0x55555555;
34f80b04 6415 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6416 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6417}
6418
6419/* some of the internal memories
6420 * are not directly readable from the driver
6421 * to test them we send debug packets
6422 */
6423static int bnx2x_int_mem_test(struct bnx2x *bp)
6424{
6425 int factor;
6426 int count, i;
6427 u32 val = 0;
6428
ad8d3948 6429 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6430 factor = 120;
ad8d3948
EG		 6431 else if (CHIP_REV_IS_EMUL(bp))
6432 factor = 200;
6433 else
a2fbb9ea 6434 factor = 1;
a2fbb9ea 6435
a2fbb9ea
ET		 6436 /* Disable inputs of parser neighbor blocks */
6437 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6438 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6439 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6440 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6441
6442 /* Write 0 to parser credits for CFC search request */
6443 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6444
6445 /* send Ethernet packet */
6446 bnx2x_lb_pckt(bp);
6447
6448 /* TODO do i reset NIG statistic? */
6449 /* Wait until NIG register shows 1 packet of size 0x10 */
6450 count = 1000 * factor;
6451 while (count) {
34f80b04 6452
a2fbb9ea
ET		 6453 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6454 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6455 if (val == 0x10)
6456 break;
6457
639d65b8 6458 usleep_range(10000, 20000);
a2fbb9ea
ET		 6459 count--;
6460 }
6461 if (val != 0x10) {
6462 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6463 return -1;
6464 }
6465
6466 /* Wait until PRS register shows 1 packet */
6467 count = 1000 * factor;
6468 while (count) {
6469 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6470 if (val == 1)
6471 break;
6472
639d65b8 6473 usleep_range(10000, 20000);
a2fbb9ea
ET		 6474 count--;
6475 }
6476 if (val != 0x1) {
6477 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6478 return -2;
6479 }
6480
6481 /* Reset and init BRB, PRS */
34f80b04 6482 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6483 msleep(50);
34f80b04 6484 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6485 msleep(50);
619c5cb6
VZ		 6486 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6487 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6488
6489 DP(NETIF_MSG_HW, "part2\n");
6490
6491 /* Disable inputs of parser neighbor blocks */
6492 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6493 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6494 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6495 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6496
6497 /* Write 0 to parser credits for CFC search request */
6498 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6499
6500 /* send 10 Ethernet packets */
6501 for (i = 0; i < 10; i++)
6502 bnx2x_lb_pckt(bp);
6503
6504 /* Wait until NIG register shows 10 + 1
6505 packets of size 11*0x10 = 0xb0 */
6506 count = 1000 * factor;
6507 while (count) {
34f80b04 6508
a2fbb9ea
ET		 6509 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6510 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6511 if (val == 0xb0)
6512 break;
6513
639d65b8 6514 usleep_range(10000, 20000);
a2fbb9ea
ET		 6515 count--;
6516 }
6517 if (val != 0xb0) {
6518 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6519 return -3;
6520 }
6521
6522 /* Wait until PRS register shows 2 packets */
6523 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6524 if (val != 2)
6525 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6526
6527 /* Write 1 to parser credits for CFC search request */
6528 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6529
6530 /* Wait until PRS register shows 3 packets */
6531 msleep(10 * factor);
6532 /* Wait until NIG register shows 1 packet of size 0x10 */
6533 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6534 if (val != 3)
6535 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6536
6537 /* clear NIG EOP FIFO */
6538 for (i = 0; i < 11; i++)
6539 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6540 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6541 if (val != 1) {
6542 BNX2X_ERR("clear of NIG failed\n");
6543 return -4;
6544 }
6545
6546 /* Reset and init BRB, PRS, NIG */
6547 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6548 msleep(50);
6549 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6550 msleep(50);
619c5cb6
VZ		 6551 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6552 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6553 if (!CNIC_SUPPORT(bp))
6554 /* set NIC mode */
6555 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6556
6557 /* Enable inputs of parser neighbor blocks */
6558 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6559 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6560 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6561 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6562
6563 DP(NETIF_MSG_HW, "done\n");
6564
6565 return 0; /* OK */
6566}
6567
4a33bc03 6568static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6569{
b343d002
YM		 6570 u32 val;
6571
a2fbb9ea 6572 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6573 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6574 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6575 else
6576 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6577 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6578 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6579 /*
6580 * mask read length error interrupts in brb for parser
6581 * (parsing unit and 'checksum and crc' unit)
6582 * these errors are legal (PU reads fixed length and CAC can cause
6583 * read length error on truncated packets)
6584 */
6585 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6586 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6587 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6588 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6589 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6590 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6591/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6592/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6593 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6594 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6595 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6596/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6597/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6598 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6599 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6600 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6601 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6602/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6603/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6604
b343d002
YM		 6605 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6606 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6607 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6608 if (!CHIP_IS_E1x(bp))
6609 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6610 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6611 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6612
a2fbb9ea
ET		 6613 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6614 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6615 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6616/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6617
6618 if (!CHIP_IS_E1x(bp))
6619 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6620 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6621
a2fbb9ea
ET		 6622 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6623 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6624/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6625 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6626}
6627
81f75bbf
EG		 6628static void bnx2x_reset_common(struct bnx2x *bp)
6629{
619c5cb6
VZ		 6630 u32 val = 0x1400;
6631
81f75bbf
EG		 6632 /* reset_common */
6633 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6634 0xd3ffff7f);
619c5cb6
VZ		 6635
6636 if (CHIP_IS_E3(bp)) {
6637 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6638 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6639 }
6640
6641 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6642}
6643
6644static void bnx2x_setup_dmae(struct bnx2x *bp)
6645{
6646 bp->dmae_ready = 0;
6647 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6648}
6649
573f2035
EG		 6650static void bnx2x_init_pxp(struct bnx2x *bp)
6651{
6652 u16 devctl;
6653 int r_order, w_order;
6654
2a80eebc 6655 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6656 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6657 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6658 if (bp->mrrs == -1)
6659 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6660 else {
6661 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6662 r_order = bp->mrrs;
6663 }
6664
6665 bnx2x_init_pxp_arb(bp, r_order, w_order);
6666}
fd4ef40d
EG		 6667
6668static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6669{
2145a920 6670 int is_required;
fd4ef40d 6671 u32 val;
2145a920 6672 int port;
fd4ef40d 6673
2145a920
VZ		 6674 if (BP_NOMCP(bp))
6675 return;
6676
6677 is_required = 0;
fd4ef40d
EG		 6678 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6679 SHARED_HW_CFG_FAN_FAILURE_MASK;
6680
6681 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6682 is_required = 1;
6683
6684 /*
6685 * The fan failure mechanism is usually related to the PHY type since
6686 * the power consumption of the board is affected by the PHY. Currently,
6687 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6688 */
6689 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6690 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6691 is_required |=
d90d96ba
YR		 6692 bnx2x_fan_failure_det_req(
6693 bp,
6694 bp->common.shmem_base,
a22f0788 6695 bp->common.shmem2_base,
d90d96ba 6696 port);
fd4ef40d
EG		 6697 }
6698
6699 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6700
6701 if (is_required == 0)
6702 return;
6703
6704 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6705 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6706
6707 /* set to active low mode */
6708 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6709 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6710 REG_WR(bp, MISC_REG_SPIO_INT, val);
6711
6712 /* enable interrupt to signal the IGU */
6713 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6714 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6715 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6716}
6717
c9ee9206 6718void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6719{
6720 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6721 val &= ~IGU_PF_CONF_FUNC_EN;
6722
6723 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6724 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6725 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6726}
6727
1191cb83 6728static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6729{
6730 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6731 /* Avoid common init in case MFW supports LFA */
6732 if (SHMEM2_RD(bp, size) >
6733 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6734 return;
619c5cb6
VZ		 6735 shmem_base[0] = bp->common.shmem_base;
6736 shmem2_base[0] = bp->common.shmem2_base;
6737 if (!CHIP_IS_E1x(bp)) {
6738 shmem_base[1] =
6739 SHMEM2_RD(bp, other_shmem_base_addr);
6740 shmem2_base[1] =
6741 SHMEM2_RD(bp, other_shmem2_base_addr);
6742 }
6743 bnx2x_acquire_phy_lock(bp);
6744 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6745 bp->common.chip_id);
6746 bnx2x_release_phy_lock(bp);
6747}
6748
6749/**
6750 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6751 *
6752 * @bp: driver handle
6753 */
6754static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6755{
619c5cb6 6756 u32 val;
a2fbb9ea 6757
51c1a580 6758 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6759
2031bd3a 6760 /*
2de67439 6761 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 6762 * registers while we're resetting the chip
6763 */
7a06a122 6764 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6765
81f75bbf 6766 bnx2x_reset_common(bp);
34f80b04 6767 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6768
619c5cb6
VZ		 6769 val = 0xfffc;
6770 if (CHIP_IS_E3(bp)) {
6771 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6772 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6773 }
6774 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6775
7a06a122 6776 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6777
619c5cb6 6778 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6779
619c5cb6
VZ		 6780 if (!CHIP_IS_E1x(bp)) {
6781 u8 abs_func_id;
f2e0899f
DK		 6782
6783 /**
6784 * 4-port mode or 2-port mode we need to turn of master-enable
6785 * for everyone, after that, turn it back on for self.
6786 * so, we disregard multi-function or not, and always disable
6787 * for all functions on the given path, this means 0,2,4,6 for
6788 * path 0 and 1,3,5,7 for path 1
6789 */
619c5cb6
VZ		 6790 for (abs_func_id = BP_PATH(bp);
6791 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6792 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6793 REG_WR(bp,
6794 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6795 1);
6796 continue;
6797 }
6798
619c5cb6 6799 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6800 /* clear pf enable */
6801 bnx2x_pf_disable(bp);
6802 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6803 }
6804 }
a2fbb9ea 6805
619c5cb6 6806 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6807 if (CHIP_IS_E1(bp)) {
6808 /* enable HW interrupt from PXP on USDM overflow
6809 bit 16 on INT_MASK_0 */
6810 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6811 }
a2fbb9ea 6812
619c5cb6 6813 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6814 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6815
6816#ifdef __BIG_ENDIAN
34f80b04
EG		 6817 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6818 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6819 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6820 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6821 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6822 /* make sure this value is 0 */
6823 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6824
6825/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6826 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6827 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6828 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6829 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6830#endif
6831
523224a3
DK		 6832 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6833
34f80b04
EG		 6834 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6835 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6836
34f80b04
EG		 6837 /* let the HW do it's magic ... */
6838 msleep(100);
6839 /* finish PXP init */
6840 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6841 if (val != 1) {
6842 BNX2X_ERR("PXP2 CFG failed\n");
6843 return -EBUSY;
6844 }
6845 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6846 if (val != 1) {
6847 BNX2X_ERR("PXP2 RD_INIT failed\n");
6848 return -EBUSY;
6849 }
a2fbb9ea 6850
f2e0899f
DK		 6851 /* Timers bug workaround E2 only. We need to set the entire ILT to
6852 * have entries with value "0" and valid bit on.
6853 * This needs to be done by the first PF that is loaded in a path
6854 * (i.e. common phase)
6855 */
619c5cb6
VZ		 6856 if (!CHIP_IS_E1x(bp)) {
6857/* In E2 there is a bug in the timers block that can cause function 6 / 7
6858 * (i.e. vnic3) to start even if it is marked as "scan-off".
6859 * This occurs when a different function (func2,3) is being marked
6860 * as "scan-off". Real-life scenario for example: if a driver is being
6861 * load-unloaded while func6,7 are down. This will cause the timer to access
6862 * the ilt, translate to a logical address and send a request to read/write.
6863 * Since the ilt for the function that is down is not valid, this will cause
6864 * a translation error which is unrecoverable.
6865 * The Workaround is intended to make sure that when this happens nothing fatal
6866 * will occur. The workaround:
6867 * 1. First PF driver which loads on a path will:
6868 * a. After taking the chip out of reset, by using pretend,
6869 * it will write "0" to the following registers of
6870 * the other vnics.
6871 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6872 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6873 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6874 * And for itself it will write '1' to
6875 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6876 * dmae-operations (writing to pram for example.)
6877 * note: can be done for only function 6,7 but cleaner this
6878 * way.
6879 * b. Write zero+valid to the entire ILT.
6880 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6881 * VNIC3 (of that port). The range allocated will be the
6882 * entire ILT. This is needed to prevent ILT range error.
6883 * 2. Any PF driver load flow:
6884 * a. ILT update with the physical addresses of the allocated
6885 * logical pages.
6886 * b. Wait 20msec. - note that this timeout is needed to make
6887 * sure there are no requests in one of the PXP internal
6888 * queues with "old" ILT addresses.
6889 * c. PF enable in the PGLC.
6890 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 6891 * occurred while driver was down)
619c5cb6
VZ		 6892 * e. PF enable in the CFC (WEAK + STRONG)
6893 * f. Timers scan enable
6894 * 3. PF driver unload flow:
6895 * a. Clear the Timers scan_en.
6896 * b. Polling for scan_on=0 for that PF.
6897 * c. Clear the PF enable bit in the PXP.
6898 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6899 * e. Write zero+valid to all ILT entries (The valid bit must
6900 * stay set)
6901 * f. If this is VNIC 3 of a port then also init
6902 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 6903 * to the last entry in the ILT.
619c5cb6
VZ		 6904 *
6905 * Notes:
6906 * Currently the PF error in the PGLC is non recoverable.
6907 * In the future the there will be a recovery routine for this error.
6908 * Currently attention is masked.
6909 * Having an MCP lock on the load/unload process does not guarantee that
6910 * there is no Timer disable during Func6/7 enable. This is because the
6911 * Timers scan is currently being cleared by the MCP on FLR.
6912 * Step 2.d can be done only for PF6/7 and the driver can also check if
6913 * there is error before clearing it. But the flow above is simpler and
6914 * more general.
6915 * All ILT entries are written by zero+valid and not just PF6/7
6916 * ILT entries since in the future the ILT entries allocation for
6917 * PF-s might be dynamic.
6918 */
f2e0899f
DK		 6919 struct ilt_client_info ilt_cli;
6920 struct bnx2x_ilt ilt;
6921 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6922 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6923
b595076a 6924 /* initialize dummy TM client */
f2e0899f
DK		 6925 ilt_cli.start = 0;
6926 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6927 ilt_cli.client_num = ILT_CLIENT_TM;
6928
6929 /* Step 1: set zeroes to all ilt page entries with valid bit on
6930 * Step 2: set the timers first/last ilt entry to point
6931 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 6932 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 6933 *
6934 * both steps performed by call to bnx2x_ilt_client_init_op()
6935 * with dummy TM client
6936 *
6937 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6938 * and his brother are split registers
6939 */
6940 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6941 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6942 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6943
6944 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6945 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6946 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6947 }
6948
34f80b04
EG		 6949 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6950 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 6951
619c5cb6 6952 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6953 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6954 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 6955 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 6956
619c5cb6 6957 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6958
6959 /* let the HW do it's magic ... */
6960 do {
6961 msleep(200);
6962 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6963 } while (factor-- && (val != 1));
6964
6965 if (val != 1) {
6966 BNX2X_ERR("ATC_INIT failed\n");
6967 return -EBUSY;
6968 }
6969 }
6970
619c5cb6 6971 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6972
b56e9670
AE		 6973 bnx2x_iov_init_dmae(bp);
6974
34f80b04
EG		 6975 /* clean the DMAE memory */
6976 bp->dmae_ready = 1;
619c5cb6
VZ		 6977 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6978
6979 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6980
6981 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6982
6983 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6984
619c5cb6 6985 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6986
34f80b04
EG		 6987 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6988 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6989 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6990 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6991
619c5cb6 6992 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6993
523224a3
DK		 6994 /* QM queues pointers table */
6995 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6996
34f80b04
EG		 6997 /* soft reset pulse */
6998 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6999 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7000
55c11941
MS		 7001 if (CNIC_SUPPORT(bp))
7002 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7003
619c5cb6 7004 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7005
619c5cb6 7006 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7007 /* enable hw interrupt from doorbell Q */
7008 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7009
619c5cb6 7010 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7011
619c5cb6 7012 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7013 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7014
f2e0899f 7015 if (!CHIP_IS_E1(bp))
619c5cb6 7016 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7017
a3348722
BW		 7018 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7019 if (IS_MF_AFEX(bp)) {
7020 /* configure that VNTag and VLAN headers must be
7021 * received in afex mode
7022 */
7023 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7024 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7025 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7026 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7027 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7028 } else {
7029 /* Bit-map indicating which L2 hdrs may appear
7030 * after the basic Ethernet header
7031 */
7032 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7033 bp->path_has_ovlan ? 7 : 6);
7034 }
7035 }
a2fbb9ea 7036
619c5cb6
VZ		 7037 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7038 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7039 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7040 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7041
619c5cb6
VZ		 7042 if (!CHIP_IS_E1x(bp)) {
7043 /* reset VFC memories */
7044 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7045 VFC_MEMORIES_RST_REG_CAM_RST |
7046 VFC_MEMORIES_RST_REG_RAM_RST);
7047 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7048 VFC_MEMORIES_RST_REG_CAM_RST |
7049 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7050
619c5cb6
VZ		 7051 msleep(20);
7052 }
a2fbb9ea 7053
619c5cb6
VZ		 7054 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7055 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7056 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7057 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7058
34f80b04
EG		 7059 /* sync semi rtc */
7060 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7061 0x80000000);
7062 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7063 0x80000000);
a2fbb9ea 7064
619c5cb6
VZ		 7065 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7066 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7067 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7068
a3348722
BW		 7069 if (!CHIP_IS_E1x(bp)) {
7070 if (IS_MF_AFEX(bp)) {
7071 /* configure that VNTag and VLAN headers must be
7072 * sent in afex mode
7073 */
7074 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7075 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7076 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7077 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7078 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7079 } else {
7080 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7081 bp->path_has_ovlan ? 7 : 6);
7082 }
7083 }
f2e0899f 7084
34f80b04 7085 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7086
619c5cb6
VZ		 7087 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7088
55c11941
MS		 7089 if (CNIC_SUPPORT(bp)) {
7090 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7091 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7092 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7093 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7094 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7095 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7096 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7097 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7098 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7099 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7100 }
34f80b04 7101 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7102
34f80b04
EG		 7103 if (sizeof(union cdu_context) != 1024)
7104 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7105 dev_alert(&bp->pdev->dev,
7106 "please adjust the size of cdu_context(%ld)\n",
7107 (long)sizeof(union cdu_context));
a2fbb9ea 7108
619c5cb6 7109 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7110 val = (4 << 24) + (0 << 12) + 1024;
7111 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7112
619c5cb6 7113 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7114 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7115 /* enable context validation interrupt from CFC */
7116 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7117
7118 /* set the thresholds to prevent CFC/CDU race */
7119 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7120
619c5cb6 7121 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7122
619c5cb6 7123 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7124 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7125
619c5cb6
VZ		 7126 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7127 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7128
34f80b04
EG		 7129 /* Reset PCIE errors for debug */
7130 REG_WR(bp, 0x2814, 0xffffffff);
7131 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7132
619c5cb6 7133 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7134 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7135 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7136 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7137 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7138 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7139 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7140 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7141 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7142 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7143 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7144 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7145 }
7146
619c5cb6 7147 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7148 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7149 /* in E3 this done in per-port section */
7150 if (!CHIP_IS_E3(bp))
7151 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7152 }
619c5cb6
VZ		 7153 if (CHIP_IS_E1H(bp))
7154 /* not applicable for E2 (and above ...) */
7155 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7156
7157 if (CHIP_REV_IS_SLOW(bp))
7158 msleep(200);
7159
7160 /* finish CFC init */
7161 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7162 if (val != 1) {
7163 BNX2X_ERR("CFC LL_INIT failed\n");
7164 return -EBUSY;
7165 }
7166 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7167 if (val != 1) {
7168 BNX2X_ERR("CFC AC_INIT failed\n");
7169 return -EBUSY;
7170 }
7171 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7172 if (val != 1) {
7173 BNX2X_ERR("CFC CAM_INIT failed\n");
7174 return -EBUSY;
7175 }
7176 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7177
f2e0899f
DK		 7178 if (CHIP_IS_E1(bp)) {
7179 /* read NIG statistic
7180 to see if this is our first up since powerup */
7181 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7182 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7183
f2e0899f
DK		 7184 /* do internal memory self test */
7185 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7186 BNX2X_ERR("internal mem self test failed\n");
7187 return -EBUSY;
7188 }
34f80b04
EG		 7189 }
7190
fd4ef40d
EG		 7191 bnx2x_setup_fan_failure_detection(bp);
7192
34f80b04
EG		 7193 /* clear PXP2 attentions */
7194 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7195
4a33bc03 7196 bnx2x_enable_blocks_attention(bp);
c9ee9206 7197 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7198
6bbca910 7199 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7200 if (CHIP_IS_E1x(bp))
7201 bnx2x__common_init_phy(bp);
6bbca910
YR		 7202 } else
7203 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7204
34f80b04
EG		 7205 return 0;
7206}
a2fbb9ea 7207
619c5cb6
VZ		 7208/**
7209 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7210 *
7211 * @bp: driver handle
7212 */
7213static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7214{
7215 int rc = bnx2x_init_hw_common(bp);
7216
7217 if (rc)
7218 return rc;
7219
7220 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7221 if (!BP_NOMCP(bp))
7222 bnx2x__common_init_phy(bp);
7223
7224 return 0;
7225}
7226
523224a3 7227static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7228{
7229 int port = BP_PORT(bp);
619c5cb6 7230 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7231 u32 low, high;
4293b9f5 7232 u32 val, reg;
a2fbb9ea 7233
51c1a580 7234 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7235
7236 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7237
619c5cb6
VZ		 7238 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7239 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7240 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7241
f2e0899f
DK		 7242 /* Timers bug workaround: disables the pf_master bit in pglue at
7243 * common phase, we need to enable it here before any dmae access are
7244 * attempted. Therefore we manually added the enable-master to the
7245 * port phase (it also happens in the function phase)
7246 */
619c5cb6 7247 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7248 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7249
619c5cb6
VZ		 7250 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7251 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7252 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7253 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7254
7255 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7256 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7257 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7258 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7259
523224a3
DK		 7260 /* QM cid (connection) count */
7261 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7262
55c11941
MS		 7263 if (CNIC_SUPPORT(bp)) {
7264 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7265 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7266 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7267 }
cdaa7cb8 7268
619c5cb6 7269 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7270
2b674047
DK		 7271 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7272
f2e0899f 7273 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7274
7275 if (IS_MF(bp))
7276 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7277 else if (bp->dev->mtu > 4096) {
7278 if (bp->flags & ONE_PORT_FLAG)
7279 low = 160;
7280 else {
7281 val = bp->dev->mtu;
7282 /* (24*1024 + val*4)/256 */
7283 low = 96 + (val/64) +
7284 ((val % 64) ? 1 : 0);
7285 }
7286 } else
7287 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7288 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7289 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7290 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7291 }
1c06328c 7292
619c5cb6
VZ		 7293 if (CHIP_MODE_IS_4_PORT(bp))
7294 REG_WR(bp, (BP_PORT(bp) ?
7295 BRB1_REG_MAC_GUARANTIED_1 :
7296 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7297
619c5cb6 7298 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7299 if (CHIP_IS_E3B0(bp)) {
7300 if (IS_MF_AFEX(bp)) {
7301 /* configure headers for AFEX mode */
7302 REG_WR(bp, BP_PORT(bp) ?
7303 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7304 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7305 REG_WR(bp, BP_PORT(bp) ?
7306 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7307 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7308 REG_WR(bp, BP_PORT(bp) ?
7309 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7310 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7311 } else {
7312 /* Ovlan exists only if we are in multi-function +
7313 * switch-dependent mode, in switch-independent there
7314 * is no ovlan headers
7315 */
7316 REG_WR(bp, BP_PORT(bp) ?
7317 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7318 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7319 (bp->path_has_ovlan ? 7 : 6));
7320 }
7321 }
356e2385 7322
619c5cb6
VZ		 7323 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7324 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7325 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7326 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7327
619c5cb6
VZ		 7328 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7329 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7330 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7331 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7332
619c5cb6
VZ		 7333 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7334 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7335
619c5cb6
VZ		 7336 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7337
7338 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7339 /* configure PBF to work without PAUSE mtu 9000 */
7340 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7341
f2e0899f
DK		 7342 /* update threshold */
7343 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7344 /* update init credit */
7345 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7346
f2e0899f
DK		 7347 /* probe changes */
7348 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7349 udelay(50);
7350 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7351 }
a2fbb9ea 7352
55c11941
MS		 7353 if (CNIC_SUPPORT(bp))
7354 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7355
619c5cb6
VZ		 7356 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7357 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7358
7359 if (CHIP_IS_E1(bp)) {
7360 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7361 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7362 }
619c5cb6 7363 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7364
619c5cb6 7365 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7366
619c5cb6 7367 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7368 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7369 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7370 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7371 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7372 val = IS_MF(bp) ? 0xF7 : 0x7;
7373 /* Enable DCBX attention for all but E1 */
7374 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7375 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7376
4293b9f5
DK		 7377 /* SCPAD_PARITY should NOT trigger close the gates */
7378 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7379 REG_WR(bp, reg,
7380 REG_RD(bp, reg) &
7381 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7382
7383 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7384 REG_WR(bp, reg,
7385 REG_RD(bp, reg) &
7386 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7387
619c5cb6
VZ		 7388 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7389
7390 if (!CHIP_IS_E1x(bp)) {
7391 /* Bit-map indicating which L2 hdrs may appear after the
7392 * basic Ethernet header
7393 */
a3348722
BW		 7394 if (IS_MF_AFEX(bp))
7395 REG_WR(bp, BP_PORT(bp) ?
7396 NIG_REG_P1_HDRS_AFTER_BASIC :
7397 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7398 else
7399 REG_WR(bp, BP_PORT(bp) ?
7400 NIG_REG_P1_HDRS_AFTER_BASIC :
7401 NIG_REG_P0_HDRS_AFTER_BASIC,
7402 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7403
7404 if (CHIP_IS_E3(bp))
7405 REG_WR(bp, BP_PORT(bp) ?
7406 NIG_REG_LLH1_MF_MODE :
7407 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7408 }
7409 if (!CHIP_IS_E3(bp))
7410 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7411
f2e0899f 7412 if (!CHIP_IS_E1(bp)) {
fb3bff17 7413 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7414 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7415 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7416
619c5cb6 7417 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7418 val = 0;
7419 switch (bp->mf_mode) {
7420 case MULTI_FUNCTION_SD:
7421 val = 1;
7422 break;
7423 case MULTI_FUNCTION_SI:
a3348722 7424 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7425 val = 2;
7426 break;
7427 }
7428
7429 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7430 NIG_REG_LLH0_CLS_TYPE), val);
7431 }
1c06328c
EG		 7432 {
7433 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7434 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7435 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7436 }
34f80b04
EG		 7437 }
7438
619c5cb6
VZ		 7439 /* If SPIO5 is set to generate interrupts, enable it for this port */
7440 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7441 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7442 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7443 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7444 val = REG_RD(bp, reg_addr);
f1410647 7445 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7446 REG_WR(bp, reg_addr, val);
f1410647 7447 }
a2fbb9ea 7448
34f80b04
EG		 7449 return 0;
7450}
7451
34f80b04
EG		 7452static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7453{
7454 int reg;
32d68de1 7455 u32 wb_write[2];
34f80b04 7456
f2e0899f 7457 if (CHIP_IS_E1(bp))
34f80b04 7458 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7459 else
7460 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7461
32d68de1
YM		 7462 wb_write[0] = ONCHIP_ADDR1(addr);
7463 wb_write[1] = ONCHIP_ADDR2(addr);
7464 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7465}
7466
b56e9670 7467void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7468{
7469 u32 data, ctl, cnt = 100;
7470 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7471 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7472 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7473 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7474 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7475 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7476
7477 /* Not supported in BC mode */
7478 if (CHIP_INT_MODE_IS_BC(bp))
7479 return;
7480
7481 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7482 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7483 IGU_REGULAR_CLEANUP_SET |
7484 IGU_REGULAR_BCLEANUP;
7485
7486 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7487 func_encode << IGU_CTRL_REG_FID_SHIFT |
7488 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7489
7490 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7491 data, igu_addr_data);
7492 REG_WR(bp, igu_addr_data, data);
7493 mmiowb();
7494 barrier();
7495 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7496 ctl, igu_addr_ctl);
7497 REG_WR(bp, igu_addr_ctl, ctl);
7498 mmiowb();
7499 barrier();
7500
7501 /* wait for clean up to finish */
7502 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7503 msleep(20);
7504
1191cb83
ED		 7505 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7506 DP(NETIF_MSG_HW,
7507 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7508 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7509 }
7510}
7511
7512static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7513{
619c5cb6 7514 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7515}
7516
1191cb83 7517static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7518{
7519 u32 i, base = FUNC_ILT_BASE(func);
7520 for (i = base; i < base + ILT_PER_FUNC; i++)
7521 bnx2x_ilt_wr(bp, i, 0);
7522}
7523
910cc727 7524static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7525{
7526 int port = BP_PORT(bp);
7527 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7528 /* T1 hash bits value determines the T1 number of entries */
7529 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7530}
7531
7532static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7533{
7534 int rc;
7535 struct bnx2x_func_state_params func_params = {NULL};
7536 struct bnx2x_func_switch_update_params *switch_update_params =
7537 &func_params.params.switch_update;
7538
7539 /* Prepare parameters for function state transitions */
7540 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7541 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7542
7543 func_params.f_obj = &bp->func_obj;
7544 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7545
7546 /* Function parameters */
7547 switch_update_params->suspend = suspend;
7548
7549 rc = bnx2x_func_state_change(bp, &func_params);
7550
7551 return rc;
7552}
7553
910cc727 7554static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7555{
7556 int rc, i, port = BP_PORT(bp);
7557 int vlan_en = 0, mac_en[NUM_MACS];
7558
55c11941
MS		 7559 /* Close input from network */
7560 if (bp->mf_mode == SINGLE_FUNCTION) {
7561 bnx2x_set_rx_filter(&bp->link_params, 0);
7562 } else {
7563 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7564 NIG_REG_LLH0_FUNC_EN);
7565 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7566 NIG_REG_LLH0_FUNC_EN, 0);
7567 for (i = 0; i < NUM_MACS; i++) {
7568 mac_en[i] = REG_RD(bp, port ?
7569 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7570 4 * i) :
7571 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7572 4 * i));
7573 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7574 4 * i) :
7575 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7576 }
7577 }
7578
7579 /* Close BMC to host */
7580 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7581 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7582
7583 /* Suspend Tx switching to the PF. Completion of this ramrod
7584 * further guarantees that all the packets of that PF / child
7585 * VFs in BRB were processed by the Parser, so it is safe to
7586 * change the NIC_MODE register.
7587 */
7588 rc = bnx2x_func_switch_update(bp, 1);
7589 if (rc) {
7590 BNX2X_ERR("Can't suspend tx-switching!\n");
7591 return rc;
7592 }
7593
7594 /* Change NIC_MODE register */
7595 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7596
7597 /* Open input from network */
7598 if (bp->mf_mode == SINGLE_FUNCTION) {
7599 bnx2x_set_rx_filter(&bp->link_params, 1);
7600 } else {
7601 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7602 NIG_REG_LLH0_FUNC_EN, vlan_en);
7603 for (i = 0; i < NUM_MACS; i++) {
7604 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7605 4 * i) :
7606 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7607 mac_en[i]);
7608 }
7609 }
7610
7611 /* Enable BMC to host */
7612 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7613 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7614
7615 /* Resume Tx switching to the PF */
7616 rc = bnx2x_func_switch_update(bp, 0);
7617 if (rc) {
7618 BNX2X_ERR("Can't resume tx-switching!\n");
7619 return rc;
7620 }
7621
7622 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7623 return 0;
7624}
7625
7626int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7627{
7628 int rc;
7629
7630 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7631
7632 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7633 /* Configure searcher as part of function hw init */
55c11941
MS		 7634 bnx2x_init_searcher(bp);
7635
7636 /* Reset NIC mode */
7637 rc = bnx2x_reset_nic_mode(bp);
7638 if (rc)
7639 BNX2X_ERR("Can't change NIC mode!\n");
7640 return rc;
7641 }
7642
7643 return 0;
7644}
7645
523224a3 7646static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7647{
7648 int port = BP_PORT(bp);
7649 int func = BP_FUNC(bp);
619c5cb6 7650 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7651 struct bnx2x_ilt *ilt = BP_ILT(bp);
7652 u16 cdu_ilt_start;
8badd27a 7653 u32 addr, val;
f4a66897 7654 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7655 int i, main_mem_width, rc;
34f80b04 7656
51c1a580 7657 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7658
619c5cb6 7659 /* FLR cleanup - hmmm */
89db4ad8
AE		 7660 if (!CHIP_IS_E1x(bp)) {
7661 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7662 if (rc) {
7663 bnx2x_fw_dump(bp);
89db4ad8 7664 return rc;
04c46736 7665 }
89db4ad8 7666 }
619c5cb6 7667
8badd27a 7668 /* set MSI reconfigure capability */
f2e0899f
DK		 7669 if (bp->common.int_block == INT_BLOCK_HC) {
7670 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7671 val = REG_RD(bp, addr);
7672 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7673 REG_WR(bp, addr, val);
7674 }
8badd27a 7675
619c5cb6
VZ		 7676 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7677 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7678
523224a3
DK		 7679 ilt = BP_ILT(bp);
7680 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7681
290ca2bb
AE		 7682 if (IS_SRIOV(bp))
7683 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7684 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7685
7686 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7687 * those of the VFs, so start line should be reset
7688 */
7689 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7690 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7691 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7692 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7693 bp->context[i].cxt_mapping;
7694 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7695 }
290ca2bb 7696
523224a3 7697 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7698
55c11941
MS		 7699 if (!CONFIGURE_NIC_MODE(bp)) {
7700 bnx2x_init_searcher(bp);
7701 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7702 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7703 } else {
7704 /* Set NIC mode */
7705 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 7706 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 7707 }
37b091ba 7708
619c5cb6 7709 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7710 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7711
7712 /* Turn on a single ISR mode in IGU if driver is going to use
7713 * INT#x or MSI
7714 */
7715 if (!(bp->flags & USING_MSIX_FLAG))
7716 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7717 /*
7718 * Timers workaround bug: function init part.
7719 * Need to wait 20msec after initializing ILT,
7720 * needed to make sure there are no requests in
7721 * one of the PXP internal queues with "old" ILT addresses
7722 */
7723 msleep(20);
7724 /*
7725 * Master enable - Due to WB DMAE writes performed before this
7726 * register is re-initialized as part of the regular function
7727 * init
7728 */
7729 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7730 /* Enable the function in IGU */
7731 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7732 }
7733
523224a3 7734 bp->dmae_ready = 1;
34f80b04 7735
619c5cb6 7736 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 7737
619c5cb6 7738 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7739 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7740
619c5cb6
VZ		 7741 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7742 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7743 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7744 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7745 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7746 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7747 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7748 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7749 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7750 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7751 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7752 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7753 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7754
7755 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7756 REG_WR(bp, QM_REG_PF_EN, 1);
7757
619c5cb6
VZ		 7758 if (!CHIP_IS_E1x(bp)) {
7759 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7760 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7761 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7762 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7763 }
7764 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7765
7766 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7767 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 7768 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 7769
7770 bnx2x_iov_init_dq(bp);
7771
619c5cb6
VZ		 7772 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7773 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7774 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7775 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7776 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7777 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7778 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7779 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7780 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7781 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7782 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7783
619c5cb6 7784 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 7785
619c5cb6 7786 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 7787
619c5cb6 7788 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7789 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7790
fb3bff17 7791 if (IS_MF(bp)) {
34f80b04 7792 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 7793 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 7794 }
7795
619c5cb6 7796 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 7797
34f80b04 7798 /* HC init per function */
f2e0899f
DK		 7799 if (bp->common.int_block == INT_BLOCK_HC) {
7800 if (CHIP_IS_E1H(bp)) {
7801 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7802
7803 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7804 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7805 }
619c5cb6 7806 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 7807
7808 } else {
7809 int num_segs, sb_idx, prod_offset;
7810
34f80b04
EG		 7811 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7812
619c5cb6 7813 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7814 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7815 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7816 }
7817
619c5cb6 7818 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7819
619c5cb6 7820 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7821 int dsb_idx = 0;
7822 /**
7823 * Producer memory:
7824 * E2 mode: address 0-135 match to the mapping memory;
7825 * 136 - PF0 default prod; 137 - PF1 default prod;
7826 * 138 - PF2 default prod; 139 - PF3 default prod;
7827 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7828 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7829 * 144-147 reserved.
7830 *
7831 * E1.5 mode - In backward compatible mode;
7832 * for non default SB; each even line in the memory
7833 * holds the U producer and each odd line hold
7834 * the C producer. The first 128 producers are for
7835 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7836 * producers are for the DSB for each PF.
7837 * Each PF has five segments: (the order inside each
7838 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7839 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7840 * 144-147 attn prods;
7841 */
7842 /* non-default-status-blocks */
7843 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7844 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7845 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7846 prod_offset = (bp->igu_base_sb + sb_idx) *
7847 num_segs;
7848
7849 for (i = 0; i < num_segs; i++) {
7850 addr = IGU_REG_PROD_CONS_MEMORY +
7851 (prod_offset + i) * 4;
7852 REG_WR(bp, addr, 0);
7853 }
7854 /* send consumer update with value 0 */
7855 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7856 USTORM_ID, 0, IGU_INT_NOP, 1);
7857 bnx2x_igu_clear_sb(bp,
7858 bp->igu_base_sb + sb_idx);
7859 }
7860
7861 /* default-status-blocks */
7862 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7863 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7864
7865 if (CHIP_MODE_IS_4_PORT(bp))
7866 dsb_idx = BP_FUNC(bp);
7867 else
3395a033 7868 dsb_idx = BP_VN(bp);
f2e0899f
DK		 7869
7870 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7871 IGU_BC_BASE_DSB_PROD + dsb_idx :
7872 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7873
3395a033
DK		 7874 /*
7875 * igu prods come in chunks of E1HVN_MAX (4) -
7876 * does not matters what is the current chip mode
7877 */
f2e0899f
DK		 7878 for (i = 0; i < (num_segs * E1HVN_MAX);
7879 i += E1HVN_MAX) {
7880 addr = IGU_REG_PROD_CONS_MEMORY +
7881 (prod_offset + i)*4;
7882 REG_WR(bp, addr, 0);
7883 }
7884 /* send consumer update with 0 */
7885 if (CHIP_INT_MODE_IS_BC(bp)) {
7886 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7887 USTORM_ID, 0, IGU_INT_NOP, 1);
7888 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7889 CSTORM_ID, 0, IGU_INT_NOP, 1);
7890 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7891 XSTORM_ID, 0, IGU_INT_NOP, 1);
7892 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7893 TSTORM_ID, 0, IGU_INT_NOP, 1);
7894 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7895 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7896 } else {
7897 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7898 USTORM_ID, 0, IGU_INT_NOP, 1);
7899 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7900 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7901 }
7902 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7903
16a5fd92 7904 /* !!! These should become driver const once
f2e0899f
DK		 7905 rf-tool supports split-68 const */
7906 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7907 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7908 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7909 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7910 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7911 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7912 }
34f80b04 7913 }
34f80b04 7914
c14423fe 7915 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 7916 REG_WR(bp, 0x2114, 0xffffffff);
7917 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 7918
f4a66897
VZ		 7919 if (CHIP_IS_E1x(bp)) {
7920 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7921 main_mem_base = HC_REG_MAIN_MEMORY +
7922 BP_PORT(bp) * (main_mem_size * 4);
7923 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7924 main_mem_width = 8;
7925
7926 val = REG_RD(bp, main_mem_prty_clr);
7927 if (val)
51c1a580
MS		 7928 DP(NETIF_MSG_HW,
7929 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7930 val);
f4a66897
VZ		 7931
7932 /* Clear "false" parity errors in MSI-X table */
7933 for (i = main_mem_base;
7934 i < main_mem_base + main_mem_size * 4;
7935 i += main_mem_width) {
7936 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7937 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7938 i, main_mem_width / 4);
7939 }
7940 /* Clear HC parity attention */
7941 REG_RD(bp, main_mem_prty_clr);
7942 }
7943
619c5cb6
VZ		 7944#ifdef BNX2X_STOP_ON_ERROR
7945 /* Enable STORMs SP logging */
7946 REG_WR8(bp, BAR_USTRORM_INTMEM +
7947 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7948 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7949 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7950 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7951 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7952 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7953 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7954#endif
7955
b7737c9b 7956 bnx2x_phy_probe(&bp->link_params);
f85582f8 7957
34f80b04
EG		 7958 return 0;
7959}
7960
55c11941
MS		 7961void bnx2x_free_mem_cnic(struct bnx2x *bp)
7962{
7963 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7964
7965 if (!CHIP_IS_E1x(bp))
7966 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7967 sizeof(struct host_hc_status_block_e2));
7968 else
7969 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7970 sizeof(struct host_hc_status_block_e1x));
7971
7972 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7973}
7974
9f6c9258 7975void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 7976{
a052997e
MS		 7977 int i;
7978
619c5cb6
VZ		 7979 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7980 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7981
b4cddbd6
AE		 7982 if (IS_VF(bp))
7983 return;
7984
7985 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7986 sizeof(struct host_sp_status_block));
7987
a2fbb9ea 7988 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 7989 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7990
a052997e
MS		 7991 for (i = 0; i < L2_ILT_LINES(bp); i++)
7992 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7993 bp->context[i].size);
523224a3
DK		 7994 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7995
7996 BNX2X_FREE(bp->ilt->lines);
f85582f8 7997
7a9b2557 7998 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 7999
523224a3
DK		 8000 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8001 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8002
05952246
YM		 8003 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8004
580d9d08 8005 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8006}
8007
55c11941 8008int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8009{
619c5cb6
VZ		 8010 if (!CHIP_IS_E1x(bp))
8011 /* size = the status block + ramrod buffers */
f2e0899f
DK		 8012 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
8013 sizeof(struct host_hc_status_block_e2));
8014 else
55c11941
MS		 8015 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
8016 &bp->cnic_sb_mapping,
8017 sizeof(struct
8018 host_hc_status_block_e1x));
8badd27a 8019
2f7a3122 8020 if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
16a5fd92 8021 /* allocate searcher T2 table, as it wasn't allocated before */
55c11941
MS		 8022 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
8023
8024 /* write address to which L5 should insert its values */
8025 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8026 &bp->slowpath->drv_info_to_mcp;
8027
8028 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8029 goto alloc_mem_err;
8030
8031 return 0;
8032
8033alloc_mem_err:
8034 bnx2x_free_mem_cnic(bp);
8035 BNX2X_ERR("Can't allocate memory\n");
8036 return -ENOMEM;
8037}
8038
8039int bnx2x_alloc_mem(struct bnx2x *bp)
8040{
8041 int i, allocated, context_size;
a2fbb9ea 8042
2f7a3122 8043 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
55c11941
MS		 8044 /* allocate searcher T2 table */
8045 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
8badd27a 8046
523224a3
DK		 8047 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
8048 sizeof(struct host_sp_status_block));
a2fbb9ea 8049
523224a3
DK		 8050 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
8051 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8052
a052997e
MS		 8053 /* Allocate memory for CDU context:
8054 * This memory is allocated separately and not in the generic ILT
8055 * functions because CDU differs in few aspects:
8056 * 1. There are multiple entities allocating memory for context -
8057 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8058 * its own ILT lines.
8059 * 2. Since CDU page-size is not a single 4KB page (which is the case
8060 * for the other ILT clients), to be efficient we want to support
8061 * allocation of sub-page-size in the last entry.
8062 * 3. Context pointers are used by the driver to pass to FW / update
8063 * the context (for the other ILT clients the pointers are used just to
8064 * free the memory during unload).
8065 */
8066 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8067
a052997e
MS		 8068 for (i = 0, allocated = 0; allocated < context_size; i++) {
8069 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8070 (context_size - allocated));
8071 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
8072 &bp->context[i].cxt_mapping,
8073 bp->context[i].size);
8074 allocated += bp->context[i].size;
8075 }
523224a3 8076 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 8077
523224a3
DK		 8078 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8079 goto alloc_mem_err;
65abd74d 8080
67c431a5
AE		 8081 if (bnx2x_iov_alloc_mem(bp))
8082 goto alloc_mem_err;
8083
9f6c9258
DK		 8084 /* Slow path ring */
8085 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 8086
523224a3
DK		 8087 /* EQ */
8088 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
8089 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 8090
9f6c9258 8091 return 0;
e1510706 8092
9f6c9258
DK		 8093alloc_mem_err:
8094 bnx2x_free_mem(bp);
51c1a580 8095 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8096 return -ENOMEM;
65abd74d
YG		 8097}
8098
a2fbb9ea
ET		 8099/*
8100 * Init service functions
8101 */
a2fbb9ea 8102
619c5cb6
VZ		 8103int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8104 struct bnx2x_vlan_mac_obj *obj, bool set,
8105 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8106{
619c5cb6
VZ		 8107 int rc;
8108 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8109
619c5cb6 8110 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8111
619c5cb6
VZ		 8112 /* Fill general parameters */
8113 ramrod_param.vlan_mac_obj = obj;
8114 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8115
619c5cb6
VZ		 8116 /* Fill a user request section if needed */
8117 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8118 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8119
619c5cb6 8120 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8121
619c5cb6
VZ		 8122 /* Set the command: ADD or DEL */
8123 if (set)
8124 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8125 else
8126 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8127 }
8128
619c5cb6 8129 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8130
8131 if (rc == -EEXIST) {
8132 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8133 /* do not treat adding same MAC as error */
8134 rc = 0;
8135 } else if (rc < 0)
619c5cb6 8136 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8137
619c5cb6 8138 return rc;
a2fbb9ea
ET		 8139}
8140
619c5cb6
VZ		 8141int bnx2x_del_all_macs(struct bnx2x *bp,
8142 struct bnx2x_vlan_mac_obj *mac_obj,
8143 int mac_type, bool wait_for_comp)
e665bfda 8144{
619c5cb6
VZ		 8145 int rc;
8146 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8147
619c5cb6
VZ		 8148 /* Wait for completion of requested */
8149 if (wait_for_comp)
8150 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8151
619c5cb6
VZ		 8152 /* Set the mac type of addresses we want to clear */
8153 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8154
619c5cb6
VZ		 8155 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8156 if (rc < 0)
8157 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8158
619c5cb6 8159 return rc;
0793f83f
DK		 8160}
8161
619c5cb6 8162int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8163{
a3348722
BW		 8164 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8165 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
51c1a580
MS		 8166 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8167 "Ignoring Zero MAC for STORAGE SD mode\n");
614c76df
DK		 8168 return 0;
8169 }
614c76df 8170
f8f4f61a
DK		 8171 if (IS_PF(bp)) {
8172 unsigned long ramrod_flags = 0;
0793f83f 8173
f8f4f61a
DK		 8174 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8175 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8176 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8177 &bp->sp_objs->mac_obj, set,
8178 BNX2X_ETH_MAC, &ramrod_flags);
8179 } else { /* vf */
8180 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8181 bp->fp->index, true);
8182 }
e665bfda 8183}
6e30dd4e 8184
619c5cb6 8185int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8186{
60cad4e6
AE		 8187 if (IS_PF(bp))
8188 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8189 else /* VF */
8190 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8191}
a2fbb9ea 8192
d6214d7a 8193/**
e8920674 8194 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8195 *
e8920674 8196 * @bp: driver handle
d6214d7a 8197 *
e8920674 8198 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8199 */
1ab4434c 8200int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8201{
1ab4434c
AE		 8202 int rc = 0;
8203
60cad4e6
AE		 8204 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8205 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8206 return -EINVAL;
60cad4e6 8207 }
1ab4434c 8208
9ee3d37b 8209 switch (int_mode) {
1ab4434c
AE		 8210 case BNX2X_INT_MODE_MSIX:
8211 /* attempt to enable msix */
8212 rc = bnx2x_enable_msix(bp);
8213
8214 /* msix attained */
8215 if (!rc)
8216 return 0;
8217
8218 /* vfs use only msix */
8219 if (rc && IS_VF(bp))
8220 return rc;
8221
8222 /* failed to enable multiple MSI-X */
8223 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8224 bp->num_queues,
8225 1 + bp->num_cnic_queues);
8226
8227 /* falling through... */
8228 case BNX2X_INT_MODE_MSI:
d6214d7a 8229 bnx2x_enable_msi(bp);
1ab4434c 8230
d6214d7a 8231 /* falling through... */
1ab4434c 8232 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8233 bp->num_ethernet_queues = 1;
8234 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8235 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8236 break;
d6214d7a 8237 default:
1ab4434c
AE		 8238 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8239 return -EINVAL;
9f6c9258 8240 }
1ab4434c 8241 return 0;
a2fbb9ea
ET		 8242}
8243
1ab4434c 8244/* must be called prior to any HW initializations */
c2bff63f
DK		 8245static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8246{
290ca2bb
AE		 8247 if (IS_SRIOV(bp))
8248 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8249 return L2_ILT_LINES(bp);
8250}
8251
523224a3
DK		 8252void bnx2x_ilt_set_info(struct bnx2x *bp)
8253{
8254 struct ilt_client_info *ilt_client;
8255 struct bnx2x_ilt *ilt = BP_ILT(bp);
8256 u16 line = 0;
8257
8258 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8259 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8260
8261 /* CDU */
8262 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8263 ilt_client->client_num = ILT_CLIENT_CDU;
8264 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8265 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8266 ilt_client->start = line;
619c5cb6 8267 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8268
8269 if (CNIC_SUPPORT(bp))
8270 line += CNIC_ILT_LINES;
523224a3
DK		 8271 ilt_client->end = line - 1;
8272
51c1a580 8273 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8274 ilt_client->start,
8275 ilt_client->end,
8276 ilt_client->page_size,
8277 ilt_client->flags,
8278 ilog2(ilt_client->page_size >> 12));
8279
8280 /* QM */
8281 if (QM_INIT(bp->qm_cid_count)) {
8282 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8283 ilt_client->client_num = ILT_CLIENT_QM;
8284 ilt_client->page_size = QM_ILT_PAGE_SZ;
8285 ilt_client->flags = 0;
8286 ilt_client->start = line;
8287
8288 /* 4 bytes for each cid */
8289 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8290 QM_ILT_PAGE_SZ);
8291
8292 ilt_client->end = line - 1;
8293
51c1a580
MS		 8294 DP(NETIF_MSG_IFUP,
8295 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8296 ilt_client->start,
8297 ilt_client->end,
8298 ilt_client->page_size,
8299 ilt_client->flags,
8300 ilog2(ilt_client->page_size >> 12));
523224a3 8301 }
523224a3 8302
55c11941
MS		 8303 if (CNIC_SUPPORT(bp)) {
8304 /* SRC */
8305 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8306 ilt_client->client_num = ILT_CLIENT_SRC;
8307 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8308 ilt_client->flags = 0;
8309 ilt_client->start = line;
8310 line += SRC_ILT_LINES;
8311 ilt_client->end = line - 1;
523224a3 8312
55c11941
MS		 8313 DP(NETIF_MSG_IFUP,
8314 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8315 ilt_client->start,
8316 ilt_client->end,
8317 ilt_client->page_size,
8318 ilt_client->flags,
8319 ilog2(ilt_client->page_size >> 12));
9f6c9258 8320
55c11941
MS		 8321 /* TM */
8322 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8323 ilt_client->client_num = ILT_CLIENT_TM;
8324 ilt_client->page_size = TM_ILT_PAGE_SZ;
8325 ilt_client->flags = 0;
8326 ilt_client->start = line;
8327 line += TM_ILT_LINES;
8328 ilt_client->end = line - 1;
523224a3 8329
55c11941
MS		 8330 DP(NETIF_MSG_IFUP,
8331 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8332 ilt_client->start,
8333 ilt_client->end,
8334 ilt_client->page_size,
8335 ilt_client->flags,
8336 ilog2(ilt_client->page_size >> 12));
8337 }
9f6c9258 8338
619c5cb6 8339 BUG_ON(line > ILT_MAX_LINES);
523224a3 8340}
f85582f8 8341
619c5cb6
VZ		 8342/**
8343 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8344 *
8345 * @bp: driver handle
8346 * @fp: pointer to fastpath
8347 * @init_params: pointer to parameters structure
8348 *
8349 * parameters configured:
8350 * - HC configuration
8351 * - Queue's CDU context
8352 */
1191cb83 8353static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8354 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8355{
6383c0b3 8356 u8 cos;
a052997e
MS		 8357 int cxt_index, cxt_offset;
8358
619c5cb6
VZ		 8359 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8360 if (!IS_FCOE_FP(fp)) {
8361 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8362 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8363
16a5fd92 8364 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8365 * to INIT state.
8366 */
8367 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8368 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8369
8370 /* HC rate */
8371 init_params->rx.hc_rate = bp->rx_ticks ?
8372 (1000000 / bp->rx_ticks) : 0;
8373 init_params->tx.hc_rate = bp->tx_ticks ?
8374 (1000000 / bp->tx_ticks) : 0;
8375
8376 /* FW SB ID */
8377 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8378 fp->fw_sb_id;
8379
8380 /*
8381 * CQ index among the SB indices: FCoE clients uses the default
8382 * SB, therefore it's different.
8383 */
6383c0b3
AE		 8384 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8385 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8386 }
8387
6383c0b3
AE		 8388 /* set maximum number of COSs supported by this queue */
8389 init_params->max_cos = fp->max_cos;
8390
51c1a580 8391 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8392 fp->index, init_params->max_cos);
8393
8394 /* set the context pointers queue object */
a052997e 8395 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8396 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8397 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8398 ILT_PAGE_CIDS);
6383c0b3 8399 init_params->cxts[cos] =
a052997e
MS		 8400 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8401 }
619c5cb6
VZ		 8402}
8403
910cc727 8404static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8405 struct bnx2x_queue_state_params *q_params,
8406 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8407 int tx_index, bool leading)
8408{
8409 memset(tx_only_params, 0, sizeof(*tx_only_params));
8410
8411 /* Set the command */
8412 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8413
8414 /* Set tx-only QUEUE flags: don't zero statistics */
8415 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8416
8417 /* choose the index of the cid to send the slow path on */
8418 tx_only_params->cid_index = tx_index;
8419
8420 /* Set general TX_ONLY_SETUP parameters */
8421 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8422
8423 /* Set Tx TX_ONLY_SETUP parameters */
8424 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8425
51c1a580
MS		 8426 DP(NETIF_MSG_IFUP,
8427 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8428 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8429 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8430 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8431
8432 /* send the ramrod */
8433 return bnx2x_queue_state_change(bp, q_params);
8434}
8435
619c5cb6
VZ		 8436/**
8437 * bnx2x_setup_queue - setup queue
8438 *
8439 * @bp: driver handle
8440 * @fp: pointer to fastpath
8441 * @leading: is leading
8442 *
8443 * This function performs 2 steps in a Queue state machine
8444 * actually: 1) RESET->INIT 2) INIT->SETUP
8445 */
8446
8447int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8448 bool leading)
8449{
3b603066 8450 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8451 struct bnx2x_queue_setup_params *setup_params =
8452 &q_params.params.setup;
6383c0b3
AE		 8453 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8454 &q_params.params.tx_only;
a2fbb9ea 8455 int rc;
6383c0b3
AE		 8456 u8 tx_index;
8457
51c1a580 8458 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8459
ec6ba945
VZ		 8460 /* reset IGU state skip FCoE L2 queue */
8461 if (!IS_FCOE_FP(fp))
8462 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8463 IGU_INT_ENABLE, 0);
a2fbb9ea 8464
15192a8c 8465 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8466 /* We want to wait for completion in this context */
8467 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8468
619c5cb6
VZ		 8469 /* Prepare the INIT parameters */
8470 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8471
619c5cb6
VZ		 8472 /* Set the command */
8473 q_params.cmd = BNX2X_Q_CMD_INIT;
8474
8475 /* Change the state to INIT */
8476 rc = bnx2x_queue_state_change(bp, &q_params);
8477 if (rc) {
6383c0b3 8478 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8479 return rc;
8480 }
ec6ba945 8481
51c1a580 8482 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8483
619c5cb6
VZ		 8484 /* Now move the Queue to the SETUP state... */
8485 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8486
619c5cb6
VZ		 8487 /* Set QUEUE flags */
8488 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8489
619c5cb6 8490 /* Set general SETUP parameters */
6383c0b3
AE		 8491 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8492 FIRST_TX_COS_INDEX);
619c5cb6 8493
6383c0b3 8494 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8495 &setup_params->rxq_params);
8496
6383c0b3
AE		 8497 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8498 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8499
8500 /* Set the command */
8501 q_params.cmd = BNX2X_Q_CMD_SETUP;
8502
55c11941
MS		 8503 if (IS_FCOE_FP(fp))
8504 bp->fcoe_init = true;
8505
619c5cb6
VZ		 8506 /* Change the state to SETUP */
8507 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8508 if (rc) {
8509 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8510 return rc;
8511 }
8512
8513 /* loop through the relevant tx-only indices */
8514 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8515 tx_index < fp->max_cos;
8516 tx_index++) {
8517
8518 /* prepare and send tx-only ramrod*/
8519 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8520 tx_only_params, tx_index, leading);
8521 if (rc) {
8522 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8523 fp->index, tx_index);
8524 return rc;
8525 }
8526 }
523224a3 8527
34f80b04 8528 return rc;
a2fbb9ea
ET		 8529}
8530
619c5cb6 8531static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8532{
619c5cb6 8533 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8534 struct bnx2x_fp_txdata *txdata;
3b603066 8535 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8536 int rc, tx_index;
8537
51c1a580 8538 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8539
15192a8c 8540 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8541 /* We want to wait for completion in this context */
8542 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8543
6383c0b3
AE		 8544 /* close tx-only connections */
8545 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8546 tx_index < fp->max_cos;
8547 tx_index++){
8548
8549 /* ascertain this is a normal queue*/
65565884 8550 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8551
51c1a580 8552 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8553 txdata->txq_index);
8554
8555 /* send halt terminate on tx-only connection */
8556 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8557 memset(&q_params.params.terminate, 0,
8558 sizeof(q_params.params.terminate));
8559 q_params.params.terminate.cid_index = tx_index;
8560
8561 rc = bnx2x_queue_state_change(bp, &q_params);
8562 if (rc)
8563 return rc;
8564
8565 /* send halt terminate on tx-only connection */
8566 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8567 memset(&q_params.params.cfc_del, 0,
8568 sizeof(q_params.params.cfc_del));
8569 q_params.params.cfc_del.cid_index = tx_index;
8570 rc = bnx2x_queue_state_change(bp, &q_params);
8571 if (rc)
8572 return rc;
8573 }
8574 /* Stop the primary connection: */
8575 /* ...halt the connection */
619c5cb6
VZ		 8576 q_params.cmd = BNX2X_Q_CMD_HALT;
8577 rc = bnx2x_queue_state_change(bp, &q_params);
8578 if (rc)
da5a662a 8579 return rc;
a2fbb9ea 8580
6383c0b3 8581 /* ...terminate the connection */
619c5cb6 8582 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8583 memset(&q_params.params.terminate, 0,
8584 sizeof(q_params.params.terminate));
8585 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8586 rc = bnx2x_queue_state_change(bp, &q_params);
8587 if (rc)
523224a3 8588 return rc;
6383c0b3 8589 /* ...delete cfc entry */
619c5cb6 8590 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8591 memset(&q_params.params.cfc_del, 0,
8592 sizeof(q_params.params.cfc_del));
8593 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8594 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8595}
8596
34f80b04
EG		 8597static void bnx2x_reset_func(struct bnx2x *bp)
8598{
8599 int port = BP_PORT(bp);
8600 int func = BP_FUNC(bp);
f2e0899f 8601 int i;
523224a3
DK		 8602
8603 /* Disable the function in the FW */
8604 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8605 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8606 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8607 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8608
8609 /* FP SBs */
ec6ba945 8610 for_each_eth_queue(bp, i) {
523224a3 8611 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8612 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8613 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8614 SB_DISABLED);
523224a3
DK		 8615 }
8616
55c11941
MS		 8617 if (CNIC_LOADED(bp))
8618 /* CNIC SB */
8619 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8620 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8621 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8622
523224a3 8623 /* SP SB */
619c5cb6 8624 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8625 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8626 SB_DISABLED);
523224a3
DK		 8627
8628 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8629 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8630 0);
34f80b04
EG		 8631
8632 /* Configure IGU */
f2e0899f
DK		 8633 if (bp->common.int_block == INT_BLOCK_HC) {
8634 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8635 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8636 } else {
8637 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8638 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8639 }
34f80b04 8640
55c11941
MS		 8641 if (CNIC_LOADED(bp)) {
8642 /* Disable Timer scan */
8643 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8644 /*
8645 * Wait for at least 10ms and up to 2 second for the timers
8646 * scan to complete
8647 */
8648 for (i = 0; i < 200; i++) {
639d65b8 8649 usleep_range(10000, 20000);
55c11941
MS		 8650 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8651 break;
8652 }
37b091ba 8653 }
34f80b04 8654 /* Clear ILT */
f2e0899f
DK		 8655 bnx2x_clear_func_ilt(bp, func);
8656
8657 /* Timers workaround bug for E2: if this is vnic-3,
8658 * we need to set the entire ilt range for this timers.
8659 */
619c5cb6 8660 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8661 struct ilt_client_info ilt_cli;
8662 /* use dummy TM client */
8663 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8664 ilt_cli.start = 0;
8665 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8666 ilt_cli.client_num = ILT_CLIENT_TM;
8667
8668 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8669 }
8670
8671 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 8672 if (!CHIP_IS_E1x(bp))
f2e0899f 8673 bnx2x_pf_disable(bp);
523224a3
DK		 8674
8675 bp->dmae_ready = 0;
34f80b04
EG		 8676}
8677
8678static void bnx2x_reset_port(struct bnx2x *bp)
8679{
8680 int port = BP_PORT(bp);
8681 u32 val;
8682
619c5cb6
VZ		 8683 /* Reset physical Link */
8684 bnx2x__link_reset(bp);
8685
34f80b04
EG		 8686 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8687
8688 /* Do not rcv packets to BRB */
8689 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8690 /* Do not direct rcv packets that are not for MCP to the BRB */
8691 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8692 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8693
8694 /* Configure AEU */
8695 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8696
8697 msleep(100);
8698 /* Check for BRB port occupancy */
8699 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8700 if (val)
8701 DP(NETIF_MSG_IFDOWN,
33471629 8702 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 8703
8704 /* TODO: Close Doorbell port? */
8705}
8706
1191cb83 8707static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 8708{
3b603066 8709 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 8710
619c5cb6
VZ		 8711 /* Prepare parameters for function state transitions */
8712 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 8713
619c5cb6
VZ		 8714 func_params.f_obj = &bp->func_obj;
8715 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 8716
619c5cb6 8717 func_params.params.hw_init.load_phase = load_code;
49d66772 8718
619c5cb6 8719 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 8720}
8721
1191cb83 8722static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 8723{
3b603066 8724 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 8725 int rc;
228241eb 8726
619c5cb6
VZ		 8727 /* Prepare parameters for function state transitions */
8728 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8729 func_params.f_obj = &bp->func_obj;
8730 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 8731
619c5cb6
VZ		 8732 /*
8733 * Try to stop the function the 'good way'. If fails (in case
8734 * of a parity error during bnx2x_chip_cleanup()) and we are
8735 * not in a debug mode, perform a state transaction in order to
8736 * enable further HW_RESET transaction.
8737 */
8738 rc = bnx2x_func_state_change(bp, &func_params);
8739 if (rc) {
34f80b04 8740#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 8741 return rc;
34f80b04 8742#else
51c1a580 8743 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 8744 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8745 return bnx2x_func_state_change(bp, &func_params);
34f80b04 8746#endif
228241eb 8747 }
a2fbb9ea 8748
619c5cb6
VZ		 8749 return 0;
8750}
523224a3 8751
619c5cb6
VZ		 8752/**
8753 * bnx2x_send_unload_req - request unload mode from the MCP.
8754 *
8755 * @bp: driver handle
8756 * @unload_mode: requested function's unload mode
8757 *
8758 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8759 */
8760u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8761{
8762 u32 reset_code = 0;
8763 int port = BP_PORT(bp);
3101c2bc 8764
619c5cb6 8765 /* Select the UNLOAD request mode */
65abd74d
YG		 8766 if (unload_mode == UNLOAD_NORMAL)
8767 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8768
7d0446c2 8769 else if (bp->flags & NO_WOL_FLAG)
65abd74d 8770 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 8771
7d0446c2 8772 else if (bp->wol) {
65abd74d
YG		 8773 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8774 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 8775 struct pci_dev *pdev = bp->pdev;
65abd74d 8776 u32 val;
f9977903
DK		 8777 u16 pmc;
8778
65abd74d 8779 /* The mac address is written to entries 1-4 to
f9977903
DK		 8780 * preserve entry 0 which is used by the PMF
8781 */
3395a033 8782 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 8783
8784 val = (mac_addr[0] << 8) | mac_addr[1];
8785 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8786
8787 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8788 (mac_addr[4] << 8) | mac_addr[5];
8789 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8790
f9977903 8791 /* Enable the PME and clear the status */
29ed74c3 8792 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 8793 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 8794 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 8795
65abd74d
YG		 8796 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8797
8798 } else
8799 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 8800
619c5cb6
VZ		 8801 /* Send the request to the MCP */
8802 if (!BP_NOMCP(bp))
8803 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8804 else {
8805 int path = BP_PATH(bp);
8806
51c1a580 8807 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 8808 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8809 bnx2x_load_count[path][2]);
8810 bnx2x_load_count[path][0]--;
8811 bnx2x_load_count[path][1 + port]--;
51c1a580 8812 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 8813 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8814 bnx2x_load_count[path][2]);
8815 if (bnx2x_load_count[path][0] == 0)
619c5cb6 8816 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 8817 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 8818 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8819 else
8820 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8821 }
8822
8823 return reset_code;
8824}
8825
8826/**
8827 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8828 *
8829 * @bp: driver handle
5d07d868 8830 * @keep_link: true iff link should be kept up
619c5cb6 8831 */
5d07d868 8832void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 8833{
5d07d868
YM		 8834 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8835
619c5cb6
VZ		 8836 /* Report UNLOAD_DONE to MCP */
8837 if (!BP_NOMCP(bp))
5d07d868 8838 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 8839}
8840
1191cb83 8841static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 8842{
8843 int tout = 50;
8844 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8845
8846 if (!bp->port.pmf)
8847 return 0;
8848
8849 /*
8850 * (assumption: No Attention from MCP at this stage)
16a5fd92 8851 * PMF probably in the middle of TX disable/enable transaction
6debea87 8852 * 1. Sync IRS for default SB
16a5fd92
YM		 8853 * 2. Sync SP queue - this guarantees us that attention handling started
8854 * 3. Wait, that TX disable/enable transaction completes
6debea87 8855 *
16a5fd92
YM		 8856 * 1+2 guarantee that if DCBx attention was scheduled it already changed
8857 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8858 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 8859 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8860 * transaction.
8861 */
8862
8863 /* make sure default SB ISR is done */
8864 if (msix)
8865 synchronize_irq(bp->msix_table[0].vector);
8866 else
8867 synchronize_irq(bp->pdev->irq);
8868
8869 flush_workqueue(bnx2x_wq);
8870
8871 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8872 BNX2X_F_STATE_STARTED && tout--)
8873 msleep(20);
8874
8875 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8876 BNX2X_F_STATE_STARTED) {
8877#ifdef BNX2X_STOP_ON_ERROR
51c1a580 8878 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 8879 return -EBUSY;
8880#else
8881 /*
8882 * Failed to complete the transaction in a "good way"
8883 * Force both transactions with CLR bit
8884 */
3b603066 8885 struct bnx2x_func_state_params func_params = {NULL};
6debea87 8886
51c1a580 8887 DP(NETIF_MSG_IFDOWN,
6bf07b8e 8888 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
6debea87
DK		 8889
8890 func_params.f_obj = &bp->func_obj;
8891 __set_bit(RAMROD_DRV_CLR_ONLY,
8892 &func_params.ramrod_flags);
8893
8894 /* STARTED-->TX_ST0PPED */
8895 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8896 bnx2x_func_state_change(bp, &func_params);
8897
8898 /* TX_ST0PPED-->STARTED */
8899 func_params.cmd = BNX2X_F_CMD_TX_START;
8900 return bnx2x_func_state_change(bp, &func_params);
8901#endif
8902 }
8903
8904 return 0;
8905}
8906
5d07d868 8907void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 8908{
8909 int port = BP_PORT(bp);
6383c0b3
AE		 8910 int i, rc = 0;
8911 u8 cos;
3b603066 8912 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 8913 u32 reset_code;
8914
8915 /* Wait until tx fastpath tasks complete */
8916 for_each_tx_queue(bp, i) {
8917 struct bnx2x_fastpath *fp = &bp->fp[i];
8918
6383c0b3 8919 for_each_cos_in_tx_queue(fp, cos)
65565884 8920 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 8921#ifdef BNX2X_STOP_ON_ERROR
8922 if (rc)
8923 return;
8924#endif
8925 }
8926
8927 /* Give HW time to discard old tx messages */
0926d499 8928 usleep_range(1000, 2000);
619c5cb6
VZ		 8929
8930 /* Clean all ETH MACs */
15192a8c
BW		 8931 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8932 false);
619c5cb6
VZ		 8933 if (rc < 0)
8934 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8935
8936 /* Clean up UC list */
15192a8c 8937 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 8938 true);
8939 if (rc < 0)
51c1a580
MS		 8940 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8941 rc);
619c5cb6
VZ		 8942
8943 /* Disable LLH */
8944 if (!CHIP_IS_E1(bp))
8945 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8946
8947 /* Set "drop all" (stop Rx).
8948 * We need to take a netif_addr_lock() here in order to prevent
8949 * a race between the completion code and this code.
8950 */
8951 netif_addr_lock_bh(bp->dev);
8952 /* Schedule the rx_mode command */
8953 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8954 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8955 else
8956 bnx2x_set_storm_rx_mode(bp);
8957
8958 /* Cleanup multicast configuration */
8959 rparam.mcast_obj = &bp->mcast_obj;
8960 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8961 if (rc < 0)
8962 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8963
8964 netif_addr_unlock_bh(bp->dev);
8965
f1929b01 8966 bnx2x_iov_chip_cleanup(bp);
619c5cb6 8967
6debea87
DK		 8968 /*
8969 * Send the UNLOAD_REQUEST to the MCP. This will return if
8970 * this function should perform FUNC, PORT or COMMON HW
8971 * reset.
8972 */
8973 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8974
8975 /*
8976 * (assumption: No Attention from MCP at this stage)
16a5fd92 8977 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 8978 */
8979 rc = bnx2x_func_wait_started(bp);
8980 if (rc) {
8981 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8982#ifdef BNX2X_STOP_ON_ERROR
8983 return;
8984#endif
8985 }
8986
34f80b04 8987 /* Close multi and leading connections
619c5cb6
VZ		 8988 * Completions for ramrods are collected in a synchronous way
8989 */
55c11941 8990 for_each_eth_queue(bp, i)
619c5cb6 8991 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 8992#ifdef BNX2X_STOP_ON_ERROR
8993 return;
8994#else
228241eb 8995 goto unload_error;
523224a3 8996#endif
55c11941
MS		 8997
8998 if (CNIC_LOADED(bp)) {
8999 for_each_cnic_queue(bp, i)
9000 if (bnx2x_stop_queue(bp, i))
9001#ifdef BNX2X_STOP_ON_ERROR
9002 return;
9003#else
9004 goto unload_error;
9005#endif
9006 }
9007
619c5cb6
VZ		 9008 /* If SP settings didn't get completed so far - something
9009 * very wrong has happen.
9010 */
9011 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9012 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9013
619c5cb6
VZ		 9014#ifndef BNX2X_STOP_ON_ERROR
9015unload_error:
9016#endif
523224a3 9017 rc = bnx2x_func_stop(bp);
da5a662a 9018 if (rc) {
523224a3 9019 BNX2X_ERR("Function stop failed!\n");
da5a662a 9020#ifdef BNX2X_STOP_ON_ERROR
523224a3 9021 return;
523224a3 9022#endif
34f80b04 9023 }
a2fbb9ea 9024
523224a3
DK		 9025 /* Disable HW interrupts, NAPI */
9026 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9027 /* Delete all NAPI objects */
9028 bnx2x_del_all_napi(bp);
55c11941
MS		 9029 if (CNIC_LOADED(bp))
9030 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9031
9032 /* Release IRQs */
d6214d7a 9033 bnx2x_free_irq(bp);
523224a3 9034
a2fbb9ea 9035 /* Reset the chip */
619c5cb6
VZ		 9036 rc = bnx2x_reset_hw(bp, reset_code);
9037 if (rc)
9038 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 9039
619c5cb6 9040 /* Report UNLOAD_DONE to MCP */
5d07d868 9041 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9042}
9043
9f6c9258 9044void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9045{
9046 u32 val;
9047
51c1a580 9048 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9049
9050 if (CHIP_IS_E1(bp)) {
9051 int port = BP_PORT(bp);
9052 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9053 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9054
9055 val = REG_RD(bp, addr);
9056 val &= ~(0x300);
9057 REG_WR(bp, addr, val);
619c5cb6 9058 } else {
72fd0718
VZ		 9059 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9060 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9061 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9062 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9063 }
9064}
9065
72fd0718
VZ		 9066/* Close gates #2, #3 and #4: */
9067static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9068{
c9ee9206 9069 u32 val;
72fd0718
VZ		 9070
9071 /* Gates #2 and #4a are closed/opened for "not E1" only */
9072 if (!CHIP_IS_E1(bp)) {
9073 /* #4 */
c9ee9206 9074 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9075 /* #2 */
c9ee9206 9076 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9077 }
9078
9079 /* #3 */
c9ee9206
VZ		 9080 if (CHIP_IS_E1x(bp)) {
9081 /* Prevent interrupts from HC on both ports */
9082 val = REG_RD(bp, HC_REG_CONFIG_1);
9083 REG_WR(bp, HC_REG_CONFIG_1,
9084 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9085 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9086
9087 val = REG_RD(bp, HC_REG_CONFIG_0);
9088 REG_WR(bp, HC_REG_CONFIG_0,
9089 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9090 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9091 } else {
d82603c6 9092 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9093 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9094
9095 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9096 (!close) ?
9097 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9098 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9099 }
72fd0718 9100
51c1a580 9101 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9102 close ? "closing" : "opening");
9103 mmiowb();
9104}
9105
9106#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9107
9108static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9109{
9110 /* Do some magic... */
9111 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9112 *magic_val = val & SHARED_MF_CLP_MAGIC;
9113 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9114}
9115
e8920674
DK		 9116/**
9117 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9118 *
e8920674
DK		 9119 * @bp: driver handle
9120 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9121 */
9122static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9123{
9124 /* Restore the `magic' bit value... */
72fd0718
VZ		 9125 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9126 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9127 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9128}
9129
f85582f8 9130/**
e8920674 9131 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9132 *
e8920674
DK		 9133 * @bp: driver handle
9134 * @magic_val: old value of 'magic' bit.
9135 *
9136 * Takes care of CLP configurations.
72fd0718
VZ		 9137 */
9138static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9139{
9140 u32 shmem;
9141 u32 validity_offset;
9142
51c1a580 9143 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9144
9145 /* Set `magic' bit in order to save MF config */
9146 if (!CHIP_IS_E1(bp))
9147 bnx2x_clp_reset_prep(bp, magic_val);
9148
9149 /* Get shmem offset */
9150 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9151 validity_offset =
9152 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9153
9154 /* Clear validity map flags */
9155 if (shmem > 0)
9156 REG_WR(bp, shmem + validity_offset, 0);
9157}
9158
9159#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9160#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9161
e8920674
DK		 9162/**
9163 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9164 *
e8920674 9165 * @bp: driver handle
72fd0718 9166 */
1191cb83 9167static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9168{
9169 /* special handling for emulation and FPGA,
9170 wait 10 times longer */
9171 if (CHIP_REV_IS_SLOW(bp))
9172 msleep(MCP_ONE_TIMEOUT*10);
9173 else
9174 msleep(MCP_ONE_TIMEOUT);
9175}
9176
1b6e2ceb
DK		 9177/*
9178 * initializes bp->common.shmem_base and waits for validity signature to appear
9179 */
9180static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9181{
1b6e2ceb
DK		 9182 int cnt = 0;
9183 u32 val = 0;
72fd0718 9184
1b6e2ceb
DK		 9185 do {
9186 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9187 if (bp->common.shmem_base) {
9188 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9189 if (val & SHR_MEM_VALIDITY_MB)
9190 return 0;
9191 }
72fd0718 9192
1b6e2ceb 9193 bnx2x_mcp_wait_one(bp);
72fd0718 9194
1b6e2ceb 9195 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9196
1b6e2ceb 9197 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9198
1b6e2ceb
DK		 9199 return -ENODEV;
9200}
72fd0718 9201
1b6e2ceb
DK		 9202static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9203{
9204 int rc = bnx2x_init_shmem(bp);
72fd0718 9205
72fd0718
VZ		 9206 /* Restore the `magic' bit value */
9207 if (!CHIP_IS_E1(bp))
9208 bnx2x_clp_reset_done(bp, magic_val);
9209
9210 return rc;
9211}
9212
9213static void bnx2x_pxp_prep(struct bnx2x *bp)
9214{
9215 if (!CHIP_IS_E1(bp)) {
9216 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9217 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9218 mmiowb();
9219 }
9220}
9221
9222/*
9223 * Reset the whole chip except for:
9224 * - PCIE core
9225 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9226 * one reset bit)
9227 * - IGU
9228 * - MISC (including AEU)
9229 * - GRC
9230 * - RBCN, RBCP
9231 */
c9ee9206 9232static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9233{
9234 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9235 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9236
9237 /*
9238 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9239 * (per chip) blocks.
9240 */
9241 global_bits2 =
9242 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9243 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9244
c55e771b
BW		 9245 /* Don't reset the following blocks.
9246 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9247 * reset, as in 4 port device they might still be owned
9248 * by the MCP (there is only one leader per path).
9249 */
72fd0718
VZ		 9250 not_reset_mask1 =
9251 MISC_REGISTERS_RESET_REG_1_RST_HC |
9252 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9253 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9254
9255 not_reset_mask2 =
c9ee9206 9256 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9257 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9258 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9259 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9260 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9261 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9262 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9263 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9264 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9265 MISC_REGISTERS_RESET_REG_2_PGLC |
9266 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9267 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9268 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9269 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9270 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9271 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9272
8736c826
VZ		 9273 /*
9274 * Keep the following blocks in reset:
9275 * - all xxMACs are handled by the bnx2x_link code.
9276 */
9277 stay_reset2 =
8736c826
VZ		 9278 MISC_REGISTERS_RESET_REG_2_XMAC |
9279 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9280
9281 /* Full reset masks according to the chip */
72fd0718
VZ		 9282 reset_mask1 = 0xffffffff;
9283
9284 if (CHIP_IS_E1(bp))
9285 reset_mask2 = 0xffff;
8736c826 9286 else if (CHIP_IS_E1H(bp))
72fd0718 9287 reset_mask2 = 0x1ffff;
8736c826
VZ		 9288 else if (CHIP_IS_E2(bp))
9289 reset_mask2 = 0xfffff;
9290 else /* CHIP_IS_E3 */
9291 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9292
9293 /* Don't reset global blocks unless we need to */
9294 if (!global)
9295 reset_mask2 &= ~global_bits2;
9296
9297 /*
9298 * In case of attention in the QM, we need to reset PXP
9299 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9300 * because otherwise QM reset would release 'close the gates' shortly
9301 * before resetting the PXP, then the PSWRQ would send a write
9302 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9303 * read the payload data from PSWWR, but PSWWR would not
9304 * respond. The write queue in PGLUE would stuck, dmae commands
9305 * would not return. Therefore it's important to reset the second
9306 * reset register (containing the
9307 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9308 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9309 * bit).
9310 */
72fd0718
VZ		 9311 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9312 reset_mask2 & (~not_reset_mask2));
9313
c9ee9206
VZ		 9314 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9315 reset_mask1 & (~not_reset_mask1));
9316
72fd0718
VZ		 9317 barrier();
9318 mmiowb();
9319
8736c826
VZ		 9320 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9321 reset_mask2 & (~stay_reset2));
9322
9323 barrier();
9324 mmiowb();
9325
c9ee9206 9326 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9327 mmiowb();
9328}
9329
c9ee9206
VZ		 9330/**
9331 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9332 * It should get cleared in no more than 1s.
9333 *
9334 * @bp: driver handle
9335 *
9336 * It should get cleared in no more than 1s. Returns 0 if
9337 * pending writes bit gets cleared.
9338 */
9339static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9340{
9341 u32 cnt = 1000;
9342 u32 pend_bits = 0;
9343
9344 do {
9345 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9346
9347 if (pend_bits == 0)
9348 break;
9349
0926d499 9350 usleep_range(1000, 2000);
c9ee9206
VZ		 9351 } while (cnt-- > 0);
9352
9353 if (cnt <= 0) {
9354 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9355 pend_bits);
9356 return -EBUSY;
9357 }
9358
9359 return 0;
9360}
9361
9362static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9363{
9364 int cnt = 1000;
9365 u32 val = 0;
9366 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9367 u32 tags_63_32 = 0;
72fd0718
VZ		 9368
9369 /* Empty the Tetris buffer, wait for 1s */
9370 do {
9371 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9372 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9373 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9374 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9375 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9376 if (CHIP_IS_E3(bp))
9377 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9378
72fd0718
VZ		 9379 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9380 ((port_is_idle_0 & 0x1) == 0x1) &&
9381 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9382 (pgl_exp_rom2 == 0xffffffff) &&
9383 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9384 break;
0926d499 9385 usleep_range(1000, 2000);
72fd0718
VZ		 9386 } while (cnt-- > 0);
9387
9388 if (cnt <= 0) {
51c1a580
MS		 9389 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9390 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9391 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9392 pgl_exp_rom2);
9393 return -EAGAIN;
9394 }
9395
9396 barrier();
9397
9398 /* Close gates #2, #3 and #4 */
9399 bnx2x_set_234_gates(bp, true);
9400
c9ee9206
VZ		 9401 /* Poll for IGU VQs for 57712 and newer chips */
9402 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9403 return -EAGAIN;
9404
72fd0718
VZ		 9405 /* TBD: Indicate that "process kill" is in progress to MCP */
9406
9407 /* Clear "unprepared" bit */
9408 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9409 barrier();
9410
9411 /* Make sure all is written to the chip before the reset */
9412 mmiowb();
9413
9414 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9415 * PSWHST, GRC and PSWRD Tetris buffer.
9416 */
0926d499 9417 usleep_range(1000, 2000);
72fd0718
VZ		 9418
9419 /* Prepare to chip reset: */
9420 /* MCP */
c9ee9206
VZ		 9421 if (global)
9422 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9423
9424 /* PXP */
9425 bnx2x_pxp_prep(bp);
9426 barrier();
9427
9428 /* reset the chip */
c9ee9206 9429 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9430 barrier();
9431
9dcd9acd
DK		 9432 /* clear errors in PGB */
9433 if (!CHIP_IS_E1x(bp))
9434 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9435
72fd0718
VZ		 9436 /* Recover after reset: */
9437 /* MCP */
c9ee9206 9438 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9439 return -EAGAIN;
9440
c9ee9206
VZ		 9441 /* TBD: Add resetting the NO_MCP mode DB here */
9442
72fd0718
VZ		 9443 /* Open the gates #2, #3 and #4 */
9444 bnx2x_set_234_gates(bp, false);
9445
9446 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9447 * reset state, re-enable attentions. */
9448
a2fbb9ea
ET		 9449 return 0;
9450}
9451
910cc727 9452static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9453{
9454 int rc = 0;
c9ee9206 9455 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9456 u32 load_code;
9457
9458 /* if not going to reset MCP - load "fake" driver to reset HW while
9459 * driver is owner of the HW
9460 */
9461 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9462 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9463 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9464 if (!load_code) {
9465 BNX2X_ERR("MCP response failure, aborting\n");
9466 rc = -EAGAIN;
9467 goto exit_leader_reset;
9468 }
9469 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9470 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9471 BNX2X_ERR("MCP unexpected resp, aborting\n");
9472 rc = -EAGAIN;
9473 goto exit_leader_reset2;
9474 }
9475 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9476 if (!load_code) {
9477 BNX2X_ERR("MCP response failure, aborting\n");
9478 rc = -EAGAIN;
9479 goto exit_leader_reset2;
9480 }
9481 }
c9ee9206 9482
72fd0718 9483 /* Try to recover after the failure */
c9ee9206 9484 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9485 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9486 BP_PATH(bp));
72fd0718 9487 rc = -EAGAIN;
95c6c616 9488 goto exit_leader_reset2;
72fd0718
VZ		 9489 }
9490
c9ee9206
VZ		 9491 /*
9492 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9493 * state.
9494 */
72fd0718 9495 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9496 if (global)
9497 bnx2x_clear_reset_global(bp);
72fd0718 9498
95c6c616
AE		 9499exit_leader_reset2:
9500 /* unload "fake driver" if it was loaded */
9501 if (!global && !BP_NOMCP(bp)) {
9502 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9503 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9504 }
72fd0718
VZ		 9505exit_leader_reset:
9506 bp->is_leader = 0;
c9ee9206
VZ		 9507 bnx2x_release_leader_lock(bp);
9508 smp_mb();
72fd0718
VZ		 9509 return rc;
9510}
9511
1191cb83 9512static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9513{
9514 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9515
9516 /* Disconnect this device */
9517 netif_device_detach(bp->dev);
9518
9519 /*
9520 * Block ifup for all function on this engine until "process kill"
9521 * or power cycle.
9522 */
9523 bnx2x_set_reset_in_progress(bp);
9524
9525 /* Shut down the power */
9526 bnx2x_set_power_state(bp, PCI_D3hot);
9527
9528 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9529
9530 smp_mb();
9531}
9532
9533/*
9534 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9535 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9536 * will never be called when netif_running(bp->dev) is false.
9537 */
9538static void bnx2x_parity_recover(struct bnx2x *bp)
9539{
c9ee9206 9540 bool global = false;
7a752993 9541 u32 error_recovered, error_unrecovered;
95c6c616 9542 bool is_parity;
c9ee9206 9543
72fd0718
VZ		 9544 DP(NETIF_MSG_HW, "Handling parity\n");
9545 while (1) {
9546 switch (bp->recovery_state) {
9547 case BNX2X_RECOVERY_INIT:
9548 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9549 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9550 WARN_ON(!is_parity);
c9ee9206 9551
72fd0718 9552 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9553 if (bnx2x_trylock_leader_lock(bp)) {
9554 bnx2x_set_reset_in_progress(bp);
9555 /*
9556 * Check if there is a global attention and if
9557 * there was a global attention, set the global
9558 * reset bit.
9559 */
9560
9561 if (global)
9562 bnx2x_set_reset_global(bp);
9563
72fd0718 9564 bp->is_leader = 1;
c9ee9206 9565 }
72fd0718
VZ		 9566
9567 /* Stop the driver */
9568 /* If interface has been removed - break */
5d07d868 9569 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9570 return;
9571
9572 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9573
c9ee9206
VZ		 9574 /* Ensure "is_leader", MCP command sequence and
9575 * "recovery_state" update values are seen on other
9576 * CPUs.
72fd0718 9577 */
c9ee9206 9578 smp_mb();
72fd0718
VZ		 9579 break;
9580
9581 case BNX2X_RECOVERY_WAIT:
9582 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9583 if (bp->is_leader) {
c9ee9206 9584 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9585 bool other_load_status =
9586 bnx2x_get_load_status(bp, other_engine);
9587 bool load_status =
9588 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9589 global = bnx2x_reset_is_global(bp);
9590
9591 /*
9592 * In case of a parity in a global block, let
9593 * the first leader that performs a
9594 * leader_reset() reset the global blocks in
9595 * order to clear global attentions. Otherwise
16a5fd92 9596 * the gates will remain closed for that
c9ee9206
VZ		 9597 * engine.
9598 */
889b9af3
AE		 9599 if (load_status ||
9600 (global && other_load_status)) {
72fd0718
VZ		 9601 /* Wait until all other functions get
9602 * down.
9603 */
7be08a72 9604 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9605 HZ/10);
9606 return;
9607 } else {
9608 /* If all other functions got down -
9609 * try to bring the chip back to
9610 * normal. In any case it's an exit
9611 * point for a leader.
9612 */
c9ee9206
VZ		 9613 if (bnx2x_leader_reset(bp)) {
9614 bnx2x_recovery_failed(bp);
72fd0718
VZ		 9615 return;
9616 }
9617
c9ee9206
VZ		 9618 /* If we are here, means that the
9619 * leader has succeeded and doesn't
9620 * want to be a leader any more. Try
9621 * to continue as a none-leader.
9622 */
9623 break;
72fd0718
VZ		 9624 }
9625 } else { /* non-leader */
c9ee9206 9626 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 9627 /* Try to get a LEADER_LOCK HW lock as
9628 * long as a former leader may have
9629 * been unloaded by the user or
9630 * released a leadership by another
9631 * reason.
9632 */
c9ee9206 9633 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 9634 /* I'm a leader now! Restart a
9635 * switch case.
9636 */
9637 bp->is_leader = 1;
9638 break;
9639 }
9640
7be08a72 9641 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9642 HZ/10);
9643 return;
9644
c9ee9206
VZ		 9645 } else {
9646 /*
9647 * If there was a global attention, wait
9648 * for it to be cleared.
9649 */
9650 if (bnx2x_reset_is_global(bp)) {
9651 schedule_delayed_work(
7be08a72
AE		 9652 &bp->sp_rtnl_task,
9653 HZ/10);
c9ee9206
VZ		 9654 return;
9655 }
9656
7a752993
AE		 9657 error_recovered =
9658 bp->eth_stats.recoverable_error;
9659 error_unrecovered =
9660 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 9661 bp->recovery_state =
9662 BNX2X_RECOVERY_NIC_LOADING;
9663 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 9664 error_unrecovered++;
95c6c616 9665 netdev_err(bp->dev,
51c1a580 9666 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 9667 /* Disconnect this device */
9668 netif_device_detach(bp->dev);
9669 /* Shut down the power */
9670 bnx2x_set_power_state(
9671 bp, PCI_D3hot);
9672 smp_mb();
9673 } else {
c9ee9206
VZ		 9674 bp->recovery_state =
9675 BNX2X_RECOVERY_DONE;
7a752993 9676 error_recovered++;
c9ee9206
VZ		 9677 smp_mb();
9678 }
7a752993
AE		 9679 bp->eth_stats.recoverable_error =
9680 error_recovered;
9681 bp->eth_stats.unrecoverable_error =
9682 error_unrecovered;
c9ee9206 9683
72fd0718
VZ		 9684 return;
9685 }
9686 }
9687 default:
9688 return;
9689 }
9690 }
9691}
9692
56ad3152
MS		 9693static int bnx2x_close(struct net_device *dev);
9694
72fd0718
VZ		 9695/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9696 * scheduled on a general queue in order to prevent a dead lock.
9697 */
7be08a72 9698static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 9699{
7be08a72 9700 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 9701
9702 rtnl_lock();
9703
8395be5e
AE		 9704 if (!netif_running(bp->dev)) {
9705 rtnl_unlock();
9706 return;
9707 }
7be08a72 9708
6bf07b8e 9709 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 9710#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 9711 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9712 "you will need to reboot when done\n");
9713 goto sp_rtnl_not_reset;
7be08a72 9714#endif
7be08a72 9715 /*
b1fb8740
VZ		 9716 * Clear all pending SP commands as we are going to reset the
9717 * function anyway.
7be08a72 9718 */
b1fb8740
VZ		 9719 bp->sp_rtnl_state = 0;
9720 smp_mb();
9721
72fd0718 9722 bnx2x_parity_recover(bp);
b1fb8740 9723
8395be5e
AE		 9724 rtnl_unlock();
9725 return;
b1fb8740
VZ		 9726 }
9727
9728 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 9729#ifdef BNX2X_STOP_ON_ERROR
9730 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9731 "you will need to reboot when done\n");
9732 goto sp_rtnl_not_reset;
9733#endif
9734
b1fb8740
VZ		 9735 /*
9736 * Clear all pending SP commands as we are going to reset the
9737 * function anyway.
9738 */
9739 bp->sp_rtnl_state = 0;
9740 smp_mb();
9741
5d07d868 9742 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 9743 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740 9744
8395be5e
AE		 9745 rtnl_unlock();
9746 return;
72fd0718 9747 }
b1fb8740
VZ		 9748#ifdef BNX2X_STOP_ON_ERROR
9749sp_rtnl_not_reset:
9750#endif
9751 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9752 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 9753 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9754 bnx2x_after_function_update(bp);
8304859a
AE		 9755 /*
9756 * in case of fan failure we need to reset id if the "stop on error"
9757 * debug flag is set, since we trying to prevent permanent overheating
9758 * damage
9759 */
9760 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 9761 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 9762 netif_device_detach(bp->dev);
9763 bnx2x_close(bp->dev);
8395be5e
AE		 9764 rtnl_unlock();
9765 return;
8304859a
AE		 9766 }
9767
381ac16b
AE		 9768 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9769 DP(BNX2X_MSG_SP,
9770 "sending set mcast vf pf channel message from rtnl sp-task\n");
9771 bnx2x_vfpf_set_mcast(bp->dev);
9772 }
78c3bcc5
AE		 9773 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9774 &bp->sp_rtnl_state)){
9775 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9776 bnx2x_tx_disable(bp);
9777 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9778 }
9779 }
381ac16b 9780
8b09be5f
YM		 9781 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9782 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9783 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 9784 }
9785
3ec9f9ca
AE		 9786 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9787 &bp->sp_rtnl_state))
9788 bnx2x_pf_set_vfs_vlan(bp);
9789
6ffa39f2 9790 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 9791 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 9792 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 9793 }
07b4eb3b 9794
8395be5e
AE		 9795 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9796 * can be called from other contexts as well)
9797 */
34f80b04 9798 rtnl_unlock();
8395be5e 9799
6411280a 9800 /* enable SR-IOV if applicable */
8395be5e 9801 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 9802 &bp->sp_rtnl_state)) {
9803 bnx2x_disable_sriov(bp);
6411280a 9804 bnx2x_enable_sriov(bp);
3c76feff 9805 }
34f80b04
EG		 9806}
9807
3deb8167
YR		 9808static void bnx2x_period_task(struct work_struct *work)
9809{
9810 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9811
9812 if (!netif_running(bp->dev))
9813 goto period_task_exit;
9814
9815 if (CHIP_REV_IS_SLOW(bp)) {
9816 BNX2X_ERR("period task called on emulation, ignoring\n");
9817 goto period_task_exit;
9818 }
9819
9820 bnx2x_acquire_phy_lock(bp);
9821 /*
9822 * The barrier is needed to ensure the ordering between the writing to
9823 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9824 * the reading here.
9825 */
9826 smp_mb();
9827 if (bp->port.pmf) {
9828 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9829
9830 /* Re-queue task in 1 sec */
9831 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9832 }
9833
9834 bnx2x_release_phy_lock(bp);
9835period_task_exit:
9836 return;
9837}
9838
a2fbb9ea
ET		 9839/*
9840 * Init service functions
9841 */
9842
a8f47eb7 9843static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 9844{
9845 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9846 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9847 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 9848}
9849
1ef1d45a
BW		 9850static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9851 struct bnx2x_mac_vals *vals)
34f80b04 9852{
452427b0
YM		 9853 u32 val, base_addr, offset, mask, reset_reg;
9854 bool mac_stopped = false;
9855 u8 port = BP_PORT(bp);
34f80b04 9856
1ef1d45a
BW		 9857 /* reset addresses as they also mark which values were changed */
9858 vals->bmac_addr = 0;
9859 vals->umac_addr = 0;
9860 vals->xmac_addr = 0;
9861 vals->emac_addr = 0;
9862
452427b0 9863 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 9864
452427b0
YM		 9865 if (!CHIP_IS_E3(bp)) {
9866 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9867 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9868 if ((mask & reset_reg) && val) {
9869 u32 wb_data[2];
9870 BNX2X_DEV_INFO("Disable bmac Rx\n");
9871 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9872 : NIG_REG_INGRESS_BMAC0_MEM;
9873 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9874 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 9875
452427b0
YM		 9876 /*
9877 * use rd/wr since we cannot use dmae. This is safe
9878 * since MCP won't access the bus due to the request
9879 * to unload, and no function on the path can be
9880 * loaded at this time.
9881 */
9882 wb_data[0] = REG_RD(bp, base_addr + offset);
9883 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 9884 vals->bmac_addr = base_addr + offset;
9885 vals->bmac_val[0] = wb_data[0];
9886 vals->bmac_val[1] = wb_data[1];
452427b0 9887 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 9888 REG_WR(bp, vals->bmac_addr, wb_data[0]);
9889 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 9890 }
9891 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 9892 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9893 vals->emac_val = REG_RD(bp, vals->emac_addr);
9894 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 9895 mac_stopped = true;
9896 } else {
9897 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9898 BNX2X_DEV_INFO("Disable xmac Rx\n");
9899 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9900 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9901 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9902 val & ~(1 << 1));
9903 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9904 val | (1 << 1));
1ef1d45a
BW		 9905 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9906 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9907 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 9908 mac_stopped = true;
9909 }
9910 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9911 if (mask & reset_reg) {
9912 BNX2X_DEV_INFO("Disable umac Rx\n");
9913 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1ef1d45a
BW		 9914 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9915 vals->umac_val = REG_RD(bp, vals->umac_addr);
9916 REG_WR(bp, vals->umac_addr, 0);
452427b0
YM		 9917 mac_stopped = true;
9918 }
9919 }
9920
9921 if (mac_stopped)
9922 msleep(20);
452427b0
YM		 9923}
9924
9925#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9926#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9927#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9928#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9929
91ebb929
YM		 9930#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
9931#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
9932#define BCM_5710_UNDI_FW_MF_VERS (0x05)
9933#define BNX2X_PREV_UNDI_MF_PORT(p) (0x1a150c + ((p) << 4))
9934#define BNX2X_PREV_UNDI_MF_FUNC(f) (0x1a184c + ((f) << 4))
9935static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
9936{
9937 u8 major, minor, version;
9938 u32 fw;
9939
9940 /* Must check that FW is loaded */
9941 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
9942 MISC_REGISTERS_RESET_REG_1_RST_XSEM)) {
9943 BNX2X_DEV_INFO("XSEM is reset - UNDI MF FW is not loaded\n");
9944 return false;
9945 }
9946
9947 /* Read Currently loaded FW version */
9948 fw = REG_RD(bp, XSEM_REG_PRAM);
9949 major = fw & 0xff;
9950 minor = (fw >> 0x8) & 0xff;
9951 version = (fw >> 0x10) & 0xff;
9952 BNX2X_DEV_INFO("Loaded FW: 0x%08x: Major 0x%02x Minor 0x%02x Version 0x%02x\n",
9953 fw, major, minor, version);
9954
9955 if (major > BCM_5710_UNDI_FW_MF_MAJOR)
9956 return true;
9957
9958 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
9959 (minor > BCM_5710_UNDI_FW_MF_MINOR))
9960 return true;
9961
9962 if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
9963 (minor == BCM_5710_UNDI_FW_MF_MINOR) &&
9964 (version >= BCM_5710_UNDI_FW_MF_VERS))
9965 return true;
9966
9967 return false;
9968}
9969
9970static void bnx2x_prev_unload_undi_mf(struct bnx2x *bp)
9971{
9972 int i;
9973
9974 /* Due to legacy (FW) code, the first function on each engine has a
9975 * different offset macro from the rest of the functions.
9976 * Setting this for all 8 functions is harmless regardless of whether
9977 * this is actually a multi-function device.
9978 */
9979 for (i = 0; i < 2; i++)
9980 REG_WR(bp, BNX2X_PREV_UNDI_MF_PORT(i), 1);
9981
9982 for (i = 2; i < 8; i++)
9983 REG_WR(bp, BNX2X_PREV_UNDI_MF_FUNC(i - 2), 1);
9984
9985 BNX2X_DEV_INFO("UNDI FW (MF) set to discard\n");
9986}
9987
1dd06ae8 9988static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
452427b0
YM		 9989{
9990 u16 rcq, bd;
9991 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9992
9993 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9994 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9995
9996 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9997 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9998
9999 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10000 port, bd, rcq);
10001}
10002
0329aba1 10003static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10004{
5d07d868
YM		 10005 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10006 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10007 if (!rc) {
10008 BNX2X_ERR("MCP response failure, aborting\n");
10009 return -EBUSY;
10010 }
10011
10012 return 0;
10013}
10014
c63da990
BW		 10015static struct bnx2x_prev_path_list *
10016 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10017{
10018 struct bnx2x_prev_path_list *tmp_list;
10019
10020 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10021 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10022 bp->pdev->bus->number == tmp_list->bus &&
10023 BP_PATH(bp) == tmp_list->path)
10024 return tmp_list;
10025
10026 return NULL;
10027}
10028
7fa6f340
YM		 10029static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10030{
10031 struct bnx2x_prev_path_list *tmp_list;
10032 int rc;
10033
10034 rc = down_interruptible(&bnx2x_prev_sem);
10035 if (rc) {
10036 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10037 return rc;
10038 }
10039
10040 tmp_list = bnx2x_prev_path_get_entry(bp);
10041 if (tmp_list) {
10042 tmp_list->aer = 1;
10043 rc = 0;
10044 } else {
10045 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10046 BP_PATH(bp));
10047 }
10048
10049 up(&bnx2x_prev_sem);
10050
10051 return rc;
10052}
10053
0329aba1 10054static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10055{
10056 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10057 bool rc = false;
452427b0
YM		 10058
10059 if (down_trylock(&bnx2x_prev_sem))
10060 return false;
10061
7fa6f340
YM		 10062 tmp_list = bnx2x_prev_path_get_entry(bp);
10063 if (tmp_list) {
10064 if (tmp_list->aer) {
10065 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10066 BP_PATH(bp));
10067 } else {
452427b0
YM		 10068 rc = true;
10069 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10070 BP_PATH(bp));
452427b0
YM		 10071 }
10072 }
10073
10074 up(&bnx2x_prev_sem);
10075
10076 return rc;
10077}
10078
178135c1
DK		 10079bool bnx2x_port_after_undi(struct bnx2x *bp)
10080{
10081 struct bnx2x_prev_path_list *entry;
10082 bool val;
10083
10084 down(&bnx2x_prev_sem);
10085
10086 entry = bnx2x_prev_path_get_entry(bp);
10087 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10088
10089 up(&bnx2x_prev_sem);
10090
10091 return val;
10092}
10093
c63da990 10094static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10095{
10096 struct bnx2x_prev_path_list *tmp_list;
10097 int rc;
10098
7fa6f340
YM		 10099 rc = down_interruptible(&bnx2x_prev_sem);
10100 if (rc) {
10101 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10102 return rc;
10103 }
10104
10105 /* Check whether the entry for this path already exists */
10106 tmp_list = bnx2x_prev_path_get_entry(bp);
10107 if (tmp_list) {
10108 if (!tmp_list->aer) {
10109 BNX2X_ERR("Re-Marking the path.\n");
10110 } else {
10111 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10112 BP_PATH(bp));
10113 tmp_list->aer = 0;
10114 }
10115 up(&bnx2x_prev_sem);
10116 return 0;
10117 }
10118 up(&bnx2x_prev_sem);
10119
10120 /* Create an entry for this path and add it */
ea4b3857 10121 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10122 if (!tmp_list) {
10123 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10124 return -ENOMEM;
10125 }
10126
10127 tmp_list->bus = bp->pdev->bus->number;
10128 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10129 tmp_list->path = BP_PATH(bp);
7fa6f340 10130 tmp_list->aer = 0;
c63da990 10131 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10132
10133 rc = down_interruptible(&bnx2x_prev_sem);
10134 if (rc) {
10135 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10136 kfree(tmp_list);
10137 } else {
7fa6f340
YM		 10138 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10139 BP_PATH(bp));
452427b0
YM		 10140 list_add(&tmp_list->list, &bnx2x_prev_list);
10141 up(&bnx2x_prev_sem);
10142 }
10143
10144 return rc;
10145}
10146
0329aba1 10147static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10148{
452427b0
YM		 10149 struct pci_dev *dev = bp->pdev;
10150
8eee694c
YM		 10151 if (CHIP_IS_E1x(bp)) {
10152 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10153 return -EINVAL;
10154 }
10155
10156 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10157 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10158 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10159 bp->common.bc_ver);
10160 return -EINVAL;
10161 }
452427b0 10162
8903b9eb
CL		 10163 if (!pci_wait_for_pending_transaction(dev))
10164 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10165
8eee694c 10166 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10167 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10168
10169 return 0;
10170}
10171
0329aba1 10172static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10173{
10174 int rc;
10175
10176 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10177
10178 /* Test if previous unload process was already finished for this path */
10179 if (bnx2x_prev_is_path_marked(bp))
10180 return bnx2x_prev_mcp_done(bp);
10181
04c46736
YM		 10182 BNX2X_DEV_INFO("Path is unmarked\n");
10183
452427b0
YM		 10184 /* If function has FLR capabilities, and existing FW version matches
10185 * the one required, then FLR will be sufficient to clean any residue
10186 * left by previous driver
10187 */
91ebb929 10188 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10189
10190 if (!rc) {
10191 /* fw version is good */
10192 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10193 rc = bnx2x_do_flr(bp);
10194 }
10195
10196 if (!rc) {
10197 /* FLR was performed */
10198 BNX2X_DEV_INFO("FLR successful\n");
10199 return 0;
10200 }
10201
10202 BNX2X_DEV_INFO("Could not FLR\n");
452427b0
YM		 10203
10204 /* Close the MCP request, return failure*/
10205 rc = bnx2x_prev_mcp_done(bp);
10206 if (!rc)
10207 rc = BNX2X_PREV_WAIT_NEEDED;
10208
10209 return rc;
10210}
10211
0329aba1 10212static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10213{
10214 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10215 bool prev_undi = false;
1ef1d45a
BW		 10216 struct bnx2x_mac_vals mac_vals;
10217
452427b0
YM		 10218 /* It is possible a previous function received 'common' answer,
10219 * but hasn't loaded yet, therefore creating a scenario of
10220 * multiple functions receiving 'common' on the same path.
10221 */
10222 BNX2X_DEV_INFO("Common unload Flow\n");
10223
1ef1d45a
BW		 10224 memset(&mac_vals, 0, sizeof(mac_vals));
10225
452427b0
YM		 10226 if (bnx2x_prev_is_path_marked(bp))
10227 return bnx2x_prev_mcp_done(bp);
10228
10229 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10230
10231 /* Reset should be performed after BRB is emptied */
10232 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10233 u32 timer_count = 1000;
452427b0
YM		 10234
10235 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10236 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10237
10238 /* close LLH filters towards the BRB */
10239 bnx2x_set_rx_filter(&bp->link_params, 0);
452427b0
YM		 10240
10241 /* Check if the UNDI driver was previously loaded
34f80b04
EG		 10242 * UNDI driver initializes CID offset for normal bell to 0x7
10243 */
452427b0
YM		 10244 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10245 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10246 if (tmp_reg == 0x7) {
10247 BNX2X_DEV_INFO("UNDI previously loaded\n");
10248 prev_undi = true;
10249 /* clear the UNDI indication */
10250 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
a74801c5
YM		 10251 /* clear possible idle check errors */
10252 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
34f80b04 10253 }
452427b0 10254 }
d46f7c4d
DK		 10255 if (!CHIP_IS_E1x(bp))
10256 /* block FW from writing to host */
10257 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10258
452427b0
YM		 10259 /* wait until BRB is empty */
10260 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10261 while (timer_count) {
10262 u32 prev_brb = tmp_reg;
34f80b04 10263
452427b0
YM		 10264 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10265 if (!tmp_reg)
10266 break;
619c5cb6 10267
452427b0 10268 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10269
452427b0
YM		 10270 /* reset timer as long as BRB actually gets emptied */
10271 if (prev_brb > tmp_reg)
10272 timer_count = 1000;
10273 else
10274 timer_count--;
da5a662a 10275
91ebb929
YM		 10276 /* New UNDI FW supports MF and contains better
10277 * cleaning methods - might be redundant but harmless.
10278 */
10279 if (bnx2x_prev_unload_undi_fw_supports_mf(bp)) {
10280 bnx2x_prev_unload_undi_mf(bp);
10281 } else if (prev_undi) {
10282 /* If UNDI resides in memory,
10283 * manually increment it
10284 */
452427b0 10285 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
91ebb929 10286 }
452427b0 10287 udelay(10);
7a06a122 10288 }
452427b0
YM		 10289
10290 if (!timer_count)
10291 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10292 }
f16da43b 10293
452427b0
YM		 10294 /* No packets are in the pipeline, path is ready for reset */
10295 bnx2x_reset_common(bp);
10296
1ef1d45a
BW		 10297 if (mac_vals.xmac_addr)
10298 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10299 if (mac_vals.umac_addr)
10300 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10301 if (mac_vals.emac_addr)
10302 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10303 if (mac_vals.bmac_addr) {
10304 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10305 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10306 }
10307
c63da990 10308 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10309 if (rc) {
10310 bnx2x_prev_mcp_done(bp);
10311 return rc;
10312 }
10313
10314 return bnx2x_prev_mcp_done(bp);
10315}
10316
24f06716
AE		 10317/* previous driver DMAE transaction may have occurred when pre-boot stage ended
10318 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10319 * the addresses of the transaction, resulting in was-error bit set in the pci
10320 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10321 * to clear the interrupt which detected this from the pglueb and the was done
10322 * bit
10323 */
0329aba1 10324static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
24f06716 10325{
4a25417c
AE		 10326 if (!CHIP_IS_E1x(bp)) {
10327 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10328 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
04c46736
YM		 10329 DP(BNX2X_MSG_SP,
10330 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
4a25417c
AE		 10331 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10332 1 << BP_FUNC(bp));
10333 }
24f06716
AE		 10334 }
10335}
10336
0329aba1 10337static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10338{
10339 int time_counter = 10;
10340 u32 rc, fw, hw_lock_reg, hw_lock_val;
10341 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10342
24f06716
AE		 10343 /* clear hw from errors which may have resulted from an interrupted
10344 * dmae transaction.
10345 */
10346 bnx2x_prev_interrupted_dmae(bp);
10347
10348 /* Release previously held locks */
452427b0
YM		 10349 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10350 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10351 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10352
3cdeec22 10353 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10354 if (hw_lock_val) {
10355 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10356 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10357 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10358 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10359 }
10360
10361 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10362 REG_WR(bp, hw_lock_reg, 0xffffffff);
10363 } else
10364 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10365
10366 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10367 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10368 bnx2x_release_alr(bp);
452427b0
YM		 10369 }
10370
452427b0 10371 do {
7fa6f340 10372 int aer = 0;
452427b0
YM		 10373 /* Lock MCP using an unload request */
10374 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10375 if (!fw) {
10376 BNX2X_ERR("MCP response failure, aborting\n");
10377 rc = -EBUSY;
10378 break;
10379 }
10380
7fa6f340
YM		 10381 rc = down_interruptible(&bnx2x_prev_sem);
10382 if (rc) {
10383 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10384 rc);
10385 } else {
10386 /* If Path is marked by EEH, ignore unload status */
10387 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10388 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10389 up(&bnx2x_prev_sem);
7fa6f340 10390 }
7fa6f340
YM		 10391
10392 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10393 rc = bnx2x_prev_unload_common(bp);
10394 break;
10395 }
10396
16a5fd92 10397 /* non-common reply from MCP might require looping */
452427b0
YM		 10398 rc = bnx2x_prev_unload_uncommon(bp);
10399 if (rc != BNX2X_PREV_WAIT_NEEDED)
10400 break;
10401
10402 msleep(20);
10403 } while (--time_counter);
10404
10405 if (!time_counter || rc) {
91ebb929
YM		 10406 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10407 rc = -EPROBE_DEFER;
452427b0
YM		 10408 }
10409
c63da990 10410 /* Mark function if its port was used to boot from SAN */
178135c1 10411 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10412 bp->link_params.feature_config_flags |=
10413 FEATURE_CONFIG_BOOT_FROM_SAN;
10414
452427b0
YM		 10415 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10416
10417 return rc;
34f80b04
EG		 10418}
10419
0329aba1 10420static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10421{
1d187b34 10422 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10423 u16 pmc;
34f80b04
EG		 10424
10425 /* Get the chip revision id and number. */
10426 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10427 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10428 id = ((val & 0xffff) << 16);
10429 val = REG_RD(bp, MISC_REG_CHIP_REV);
10430 id |= ((val & 0xf) << 12);
f22fdf25
YM		 10431
10432 /* Metal is read from PCI regs, but we can't access >=0x400 from
10433 * the configuration space (so we need to reg_rd)
10434 */
10435 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10436 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 10437 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 10438 id |= (val & 0xf);
10439 bp->common.chip_id = id;
523224a3 10440
7e8e02df
BW		 10441 /* force 57811 according to MISC register */
10442 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10443 if (CHIP_IS_57810(bp))
10444 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10445 (bp->common.chip_id & 0x0000FFFF);
10446 else if (CHIP_IS_57810_MF(bp))
10447 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10448 (bp->common.chip_id & 0x0000FFFF);
10449 bp->common.chip_id |= 0x1;
10450 }
10451
523224a3
DK		 10452 /* Set doorbell size */
10453 bp->db_size = (1 << BNX2X_DB_SHIFT);
10454
619c5cb6 10455 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 10456 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10457 if ((val & 1) == 0)
10458 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10459 else
10460 val = (val >> 1) & 1;
10461 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10462 "2_PORT_MODE");
10463 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10464 CHIP_2_PORT_MODE;
10465
10466 if (CHIP_MODE_IS_4_PORT(bp))
10467 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10468 else
10469 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10470 } else {
10471 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10472 bp->pfid = bp->pf_num; /* 0..7 */
10473 }
10474
51c1a580
MS		 10475 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10476
f2e0899f
DK		 10477 bp->link_params.chip_id = bp->common.chip_id;
10478 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 10479
1c06328c
EG		 10480 val = (REG_RD(bp, 0x2874) & 0x55);
10481 if ((bp->common.chip_id & 0x1) ||
10482 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10483 bp->flags |= ONE_PORT_FLAG;
10484 BNX2X_DEV_INFO("single port device\n");
10485 }
10486
34f80b04 10487 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 10488 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 10489 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10490 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10491 bp->common.flash_size, bp->common.flash_size);
10492
1b6e2ceb
DK		 10493 bnx2x_init_shmem(bp);
10494
f2e0899f
DK		 10495 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10496 MISC_REG_GENERIC_CR_1 :
10497 MISC_REG_GENERIC_CR_0));
1b6e2ceb 10498
34f80b04 10499 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 10500 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 10501 if (SHMEM2_RD(bp, size) >
10502 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10503 bp->link_params.lfa_base =
10504 REG_RD(bp, bp->common.shmem2_base +
10505 (u32)offsetof(struct shmem2_region,
10506 lfa_host_addr[BP_PORT(bp)]));
10507 else
10508 bp->link_params.lfa_base = 0;
2691d51d
EG		 10509 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10510 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10511
f2e0899f 10512 if (!bp->common.shmem_base) {
34f80b04
EG		 10513 BNX2X_DEV_INFO("MCP not active\n");
10514 bp->flags |= NO_MCP_FLAG;
10515 return;
10516 }
10517
34f80b04 10518 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10519 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10520
10521 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10522 SHARED_HW_CFG_LED_MODE_MASK) >>
10523 SHARED_HW_CFG_LED_MODE_SHIFT);
10524
c2c8b03e
EG		 10525 bp->link_params.feature_config_flags = 0;
10526 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10527 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10528 bp->link_params.feature_config_flags |=
10529 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10530 else
10531 bp->link_params.feature_config_flags &=
10532 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10533
34f80b04
EG		 10534 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10535 bp->common.bc_ver = val;
10536 BNX2X_DEV_INFO("bc_ver %X\n", val);
10537 if (val < BNX2X_BC_VER) {
10538 /* for now only warn
10539 * later we might need to enforce this */
51c1a580
MS		 10540 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10541 BNX2X_BC_VER, val);
34f80b04 10542 }
4d295db0 10543 bp->link_params.feature_config_flags |=
a22f0788 10544 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10545 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10546
a22f0788
YR		 10547 bp->link_params.feature_config_flags |=
10548 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10549 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10550 bp->link_params.feature_config_flags |=
10551 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10552 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 10553 bp->link_params.feature_config_flags |=
10554 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10555 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 10556
10557 bp->link_params.feature_config_flags |=
10558 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10559 FEATURE_CONFIG_MT_SUPPORT : 0;
10560
0e898dd7
BW		 10561 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10562 BC_SUPPORTS_PFC_STATS : 0;
85242eea 10563
2e499d3c
BW		 10564 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10565 BC_SUPPORTS_FCOE_FEATURES : 0;
10566
9876879f
BW		 10567 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10568 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 10569
10570 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10571 BC_SUPPORTS_RMMOD_CMD : 0;
10572
1d187b34
BW		 10573 boot_mode = SHMEM_RD(bp,
10574 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10575 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10576 switch (boot_mode) {
10577 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10578 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10579 break;
10580 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10581 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10582 break;
10583 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10584 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10585 break;
10586 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10587 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10588 break;
10589 }
10590
29ed74c3 10591 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 10592 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10593
72ce58c3 10594 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 10595 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 10596
10597 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10598 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10599 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10600 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10601
cdaa7cb8
VZ		 10602 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10603 val, val2, val3, val4);
34f80b04
EG		 10604}
10605
f2e0899f
DK		 10606#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10607#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10608
0329aba1 10609static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 10610{
10611 int pfid = BP_FUNC(bp);
f2e0899f
DK		 10612 int igu_sb_id;
10613 u32 val;
6383c0b3 10614 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 10615
10616 bp->igu_base_sb = 0xff;
f2e0899f 10617 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 10618 int vn = BP_VN(bp);
6383c0b3 10619 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 10620 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10621 FP_SB_MAX_E1x;
10622
10623 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10624 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10625
9b341bb1 10626 return 0;
f2e0899f
DK		 10627 }
10628
10629 /* IGU in normal mode - read CAM */
10630 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10631 igu_sb_id++) {
10632 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10633 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10634 continue;
10635 fid = IGU_FID(val);
10636 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10637 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10638 continue;
10639 if (IGU_VEC(val) == 0)
10640 /* default status block */
10641 bp->igu_dsb_id = igu_sb_id;
10642 else {
10643 if (bp->igu_base_sb == 0xff)
10644 bp->igu_base_sb = igu_sb_id;
6383c0b3 10645 igu_sb_cnt++;
f2e0899f
DK		 10646 }
10647 }
10648 }
619c5cb6 10649
6383c0b3 10650#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 10651 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10652 * optional that number of CAM entries will not be equal to the value
10653 * advertised in PCI.
10654 * Driver should use the minimal value of both as the actual status
10655 * block count
619c5cb6 10656 */
185d4c8b 10657 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 10658#endif
619c5cb6 10659
9b341bb1 10660 if (igu_sb_cnt == 0) {
f2e0899f 10661 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 10662 return -EINVAL;
10663 }
10664
10665 return 0;
f2e0899f
DK		 10666}
10667
1dd06ae8 10668static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 10669{
a22f0788
YR		 10670 int cfg_size = 0, idx, port = BP_PORT(bp);
10671
10672 /* Aggregation of supported attributes of all external phys */
10673 bp->port.supported[0] = 0;
10674 bp->port.supported[1] = 0;
b7737c9b
YR		 10675 switch (bp->link_params.num_phys) {
10676 case 1:
a22f0788
YR		 10677 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10678 cfg_size = 1;
10679 break;
b7737c9b 10680 case 2:
a22f0788
YR		 10681 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10682 cfg_size = 1;
10683 break;
10684 case 3:
10685 if (bp->link_params.multi_phy_config &
10686 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10687 bp->port.supported[1] =
10688 bp->link_params.phy[EXT_PHY1].supported;
10689 bp->port.supported[0] =
10690 bp->link_params.phy[EXT_PHY2].supported;
10691 } else {
10692 bp->port.supported[0] =
10693 bp->link_params.phy[EXT_PHY1].supported;
10694 bp->port.supported[1] =
10695 bp->link_params.phy[EXT_PHY2].supported;
10696 }
10697 cfg_size = 2;
10698 break;
b7737c9b 10699 }
a2fbb9ea 10700
a22f0788 10701 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 10702 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 10703 SHMEM_RD(bp,
a22f0788
YR		 10704 dev_info.port_hw_config[port].external_phy_config),
10705 SHMEM_RD(bp,
10706 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 10707 return;
f85582f8 10708 }
a2fbb9ea 10709
619c5cb6
VZ		 10710 if (CHIP_IS_E3(bp))
10711 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10712 else {
10713 switch (switch_cfg) {
10714 case SWITCH_CFG_1G:
10715 bp->port.phy_addr = REG_RD(
10716 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10717 break;
10718 case SWITCH_CFG_10G:
10719 bp->port.phy_addr = REG_RD(
10720 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10721 break;
10722 default:
10723 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10724 bp->port.link_config[0]);
10725 return;
10726 }
a2fbb9ea 10727 }
619c5cb6 10728 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 10729 /* mask what we support according to speed_cap_mask per configuration */
10730 for (idx = 0; idx < cfg_size; idx++) {
10731 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10732 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 10733 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 10734
a22f0788 10735 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10736 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 10737 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 10738
a22f0788 10739 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10740 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 10741 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 10742
a22f0788 10743 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10744 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 10745 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 10746
a22f0788 10747 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10748 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 10749 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 10750 SUPPORTED_1000baseT_Full);
a2fbb9ea 10751
a22f0788 10752 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10753 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 10754 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 10755
a22f0788 10756 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10757 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 10758 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 10759
10760 if (!(bp->link_params.speed_cap_mask[idx] &
10761 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10762 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 10763 }
a2fbb9ea 10764
a22f0788
YR		 10765 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10766 bp->port.supported[1]);
a2fbb9ea
ET		 10767}
10768
0329aba1 10769static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 10770{
a22f0788
YR		 10771 u32 link_config, idx, cfg_size = 0;
10772 bp->port.advertising[0] = 0;
10773 bp->port.advertising[1] = 0;
10774 switch (bp->link_params.num_phys) {
10775 case 1:
10776 case 2:
10777 cfg_size = 1;
10778 break;
10779 case 3:
10780 cfg_size = 2;
10781 break;
10782 }
10783 for (idx = 0; idx < cfg_size; idx++) {
10784 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10785 link_config = bp->port.link_config[idx];
10786 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 10787 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 10788 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10789 bp->link_params.req_line_speed[idx] =
10790 SPEED_AUTO_NEG;
10791 bp->port.advertising[idx] |=
10792 bp->port.supported[idx];
10bd1f24
MY		 10793 if (bp->link_params.phy[EXT_PHY1].type ==
10794 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10795 bp->port.advertising[idx] |=
10796 (SUPPORTED_100baseT_Half |
10797 SUPPORTED_100baseT_Full);
f85582f8
DK		 10798 } else {
10799 /* force 10G, no AN */
a22f0788
YR		 10800 bp->link_params.req_line_speed[idx] =
10801 SPEED_10000;
10802 bp->port.advertising[idx] |=
10803 (ADVERTISED_10000baseT_Full |
f85582f8 10804 ADVERTISED_FIBRE);
a22f0788 10805 continue;
f85582f8
DK		 10806 }
10807 break;
a2fbb9ea 10808
f85582f8 10809 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 10810 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10811 bp->link_params.req_line_speed[idx] =
10812 SPEED_10;
10813 bp->port.advertising[idx] |=
10814 (ADVERTISED_10baseT_Full |
f85582f8
DK		 10815 ADVERTISED_TP);
10816 } else {
51c1a580 10817 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 10818 link_config,
a22f0788 10819 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10820 return;
10821 }
10822 break;
a2fbb9ea 10823
f85582f8 10824 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 10825 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10826 bp->link_params.req_line_speed[idx] =
10827 SPEED_10;
10828 bp->link_params.req_duplex[idx] =
10829 DUPLEX_HALF;
10830 bp->port.advertising[idx] |=
10831 (ADVERTISED_10baseT_Half |
f85582f8
DK		 10832 ADVERTISED_TP);
10833 } else {
51c1a580 10834 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10835 link_config,
10836 bp->link_params.speed_cap_mask[idx]);
10837 return;
10838 }
10839 break;
a2fbb9ea 10840
f85582f8
DK		 10841 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10842 if (bp->port.supported[idx] &
10843 SUPPORTED_100baseT_Full) {
a22f0788
YR		 10844 bp->link_params.req_line_speed[idx] =
10845 SPEED_100;
10846 bp->port.advertising[idx] |=
10847 (ADVERTISED_100baseT_Full |
f85582f8
DK		 10848 ADVERTISED_TP);
10849 } else {
51c1a580 10850 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10851 link_config,
10852 bp->link_params.speed_cap_mask[idx]);
10853 return;
10854 }
10855 break;
a2fbb9ea 10856
f85582f8
DK		 10857 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10858 if (bp->port.supported[idx] &
10859 SUPPORTED_100baseT_Half) {
10860 bp->link_params.req_line_speed[idx] =
10861 SPEED_100;
10862 bp->link_params.req_duplex[idx] =
10863 DUPLEX_HALF;
a22f0788
YR		 10864 bp->port.advertising[idx] |=
10865 (ADVERTISED_100baseT_Half |
f85582f8
DK		 10866 ADVERTISED_TP);
10867 } else {
51c1a580 10868 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 10869 link_config,
10870 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10871 return;
10872 }
10873 break;
a2fbb9ea 10874
f85582f8 10875 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 10876 if (bp->port.supported[idx] &
10877 SUPPORTED_1000baseT_Full) {
10878 bp->link_params.req_line_speed[idx] =
10879 SPEED_1000;
10880 bp->port.advertising[idx] |=
10881 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 10882 ADVERTISED_TP);
10883 } else {
51c1a580 10884 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 10885 link_config,
10886 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10887 return;
10888 }
10889 break;
a2fbb9ea 10890
f85582f8 10891 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 10892 if (bp->port.supported[idx] &
10893 SUPPORTED_2500baseX_Full) {
10894 bp->link_params.req_line_speed[idx] =
10895 SPEED_2500;
10896 bp->port.advertising[idx] |=
10897 (ADVERTISED_2500baseX_Full |
34f80b04 10898 ADVERTISED_TP);
f85582f8 10899 } else {
51c1a580 10900 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 10901 link_config,
f85582f8
DK		 10902 bp->link_params.speed_cap_mask[idx]);
10903 return;
10904 }
10905 break;
a2fbb9ea 10906
f85582f8 10907 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 10908 if (bp->port.supported[idx] &
10909 SUPPORTED_10000baseT_Full) {
10910 bp->link_params.req_line_speed[idx] =
10911 SPEED_10000;
10912 bp->port.advertising[idx] |=
10913 (ADVERTISED_10000baseT_Full |
34f80b04 10914 ADVERTISED_FIBRE);
f85582f8 10915 } else {
51c1a580 10916 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 10917 link_config,
f85582f8
DK		 10918 bp->link_params.speed_cap_mask[idx]);
10919 return;
10920 }
10921 break;
3c9ada22
YR		 10922 case PORT_FEATURE_LINK_SPEED_20G:
10923 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 10924
3c9ada22 10925 break;
f85582f8 10926 default:
51c1a580 10927 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 10928 link_config);
f85582f8
DK		 10929 bp->link_params.req_line_speed[idx] =
10930 SPEED_AUTO_NEG;
10931 bp->port.advertising[idx] =
10932 bp->port.supported[idx];
10933 break;
10934 }
a2fbb9ea 10935
a22f0788 10936 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 10937 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 10938 if (bp->link_params.req_flow_ctrl[idx] ==
10939 BNX2X_FLOW_CTRL_AUTO) {
10940 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10941 bp->link_params.req_flow_ctrl[idx] =
10942 BNX2X_FLOW_CTRL_NONE;
10943 else
10944 bnx2x_set_requested_fc(bp);
a22f0788 10945 }
a2fbb9ea 10946
51c1a580 10947 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 10948 bp->link_params.req_line_speed[idx],
10949 bp->link_params.req_duplex[idx],
10950 bp->link_params.req_flow_ctrl[idx],
10951 bp->port.advertising[idx]);
10952 }
a2fbb9ea
ET		 10953}
10954
0329aba1 10955static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 10956{
86564c3f
YM		 10957 __be16 mac_hi_be = cpu_to_be16(mac_hi);
10958 __be32 mac_lo_be = cpu_to_be32(mac_lo);
10959 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10960 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 10961}
10962
0329aba1 10963static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 10964{
34f80b04 10965 int port = BP_PORT(bp);
589abe3a 10966 u32 config;
c8c60d88 10967 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 10968
c18487ee 10969 bp->link_params.bp = bp;
34f80b04 10970 bp->link_params.port = port;
c18487ee 10971
c18487ee 10972 bp->link_params.lane_config =
a2fbb9ea 10973 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 10974
a22f0788 10975 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 10976 SHMEM_RD(bp,
b0261926
YR		 10977 dev_info.port_hw_config[port].speed_capability_mask) &
10978 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 10979 bp->link_params.speed_cap_mask[1] =
10980 SHMEM_RD(bp,
b0261926
YR		 10981 dev_info.port_hw_config[port].speed_capability_mask2) &
10982 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 10983 bp->port.link_config[0] =
a2fbb9ea
ET		 10984 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10985
a22f0788
YR		 10986 bp->port.link_config[1] =
10987 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 10988
a22f0788
YR		 10989 bp->link_params.multi_phy_config =
10990 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 10991 /* If the device is capable of WoL, set the default state according
10992 * to the HW
10993 */
4d295db0 10994 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 10995 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10996 (config & PORT_FEATURE_WOL_ENABLED));
10997
4ba7699b
YM		 10998 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10999 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11000 bp->flags |= NO_ISCSI_FLAG;
11001 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11002 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11003 bp->flags |= NO_FCOE_FLAG;
11004
51c1a580 11005 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11006 bp->link_params.lane_config,
a22f0788
YR		 11007 bp->link_params.speed_cap_mask[0],
11008 bp->port.link_config[0]);
a2fbb9ea 11009
a22f0788 11010 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11011 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11012 bnx2x_phy_probe(&bp->link_params);
c18487ee 11013 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11014
11015 bnx2x_link_settings_requested(bp);
11016
01cd4528
EG		 11017 /*
11018 * If connected directly, work with the internal PHY, otherwise, work
11019 * with the external PHY
11020 */
b7737c9b
YR		 11021 ext_phy_config =
11022 SHMEM_RD(bp,
11023 dev_info.port_hw_config[port].external_phy_config);
11024 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11025 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11026 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11027
11028 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11029 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11030 bp->mdio.prtad =
b7737c9b 11031 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11032
c8c60d88
YM		 11033 /* Configure link feature according to nvram value */
11034 eee_mode = (((SHMEM_RD(bp, dev_info.
11035 port_feature_config[port].eee_power_mode)) &
11036 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11037 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11038 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11039 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11040 EEE_MODE_ENABLE_LPI |
11041 EEE_MODE_OUTPUT_TIME;
11042 } else {
11043 bp->link_params.eee_mode = 0;
11044 }
0793f83f 11045}
01cd4528 11046
b306f5ed 11047void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11048{
9e62e912 11049 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11050 int port = BP_PORT(bp);
2ba45142 11051 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11052 drv_lic_key[port].max_iscsi_conn);
2ba45142 11053
55c11941
MS		 11054 if (!CNIC_SUPPORT(bp)) {
11055 bp->flags |= no_flags;
11056 return;
11057 }
11058
b306f5ed 11059 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11060 bp->cnic_eth_dev.max_iscsi_conn =
11061 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11062 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11063
b306f5ed
DK		 11064 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11065 bp->cnic_eth_dev.max_iscsi_conn);
11066
11067 /*
11068 * If maximum allowed number of connections is zero -
11069 * disable the feature.
11070 */
11071 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11072 bp->flags |= no_flags;
b306f5ed
DK		 11073}
11074
0329aba1 11075static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11076{
11077 /* Port info */
11078 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11079 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11080 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11081 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11082
11083 /* Node info */
11084 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11085 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11086 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11087 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11088}
86800194
DK		 11089
11090static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11091{
11092 u8 count = 0;
11093
11094 if (IS_MF(bp)) {
11095 u8 fid;
11096
11097 /* iterate over absolute function ids for this path: */
11098 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11099 if (IS_MF_SD(bp)) {
11100 u32 cfg = MF_CFG_RD(bp,
11101 func_mf_config[fid].config);
11102
11103 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11104 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11105 FUNC_MF_CFG_PROTOCOL_FCOE))
11106 count++;
11107 } else {
11108 u32 cfg = MF_CFG_RD(bp,
11109 func_ext_config[fid].
11110 func_cfg);
11111
11112 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11113 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11114 count++;
11115 }
11116 }
11117 } else { /* SF */
11118 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11119
11120 for (port = 0; port < port_cnt; port++) {
11121 u32 lic = SHMEM_RD(bp,
11122 drv_lic_key[port].max_fcoe_conn) ^
11123 FW_ENCODE_32BIT_PATTERN;
11124 if (lic)
11125 count++;
11126 }
11127 }
11128
11129 return count;
11130}
11131
0329aba1 11132static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11133{
11134 int port = BP_PORT(bp);
11135 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11136 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11137 drv_lic_key[port].max_fcoe_conn);
86800194 11138 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11139
55c11941
MS		 11140 if (!CNIC_SUPPORT(bp)) {
11141 bp->flags |= NO_FCOE_FLAG;
11142 return;
11143 }
11144
b306f5ed 11145 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11146 bp->cnic_eth_dev.max_fcoe_conn =
11147 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11148 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11149
0eb43b4b
BPG		 11150 /* Calculate the number of maximum allowed FCoE tasks */
11151 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11152
11153 /* check if FCoE resources must be shared between different functions */
11154 if (num_fcoe_func)
11155 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11156
bf61ee14
VZ		 11157 /* Read the WWN: */
11158 if (!IS_MF(bp)) {
11159 /* Port info */
11160 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11161 SHMEM_RD(bp,
2de67439 11162 dev_info.port_hw_config[port].
bf61ee14
VZ		 11163 fcoe_wwn_port_name_upper);
11164 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11165 SHMEM_RD(bp,
2de67439 11166 dev_info.port_hw_config[port].
bf61ee14
VZ		 11167 fcoe_wwn_port_name_lower);
11168
11169 /* Node info */
11170 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11171 SHMEM_RD(bp,
2de67439 11172 dev_info.port_hw_config[port].
bf61ee14
VZ		 11173 fcoe_wwn_node_name_upper);
11174 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11175 SHMEM_RD(bp,
2de67439 11176 dev_info.port_hw_config[port].
bf61ee14
VZ		 11177 fcoe_wwn_node_name_lower);
11178 } else if (!IS_MF_SD(bp)) {
bf61ee14
VZ		 11179 /*
11180 * Read the WWN info only if the FCoE feature is enabled for
11181 * this function.
11182 */
7b5342d9 11183 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912
DK		 11184 bnx2x_get_ext_wwn_info(bp, func);
11185
382e513a 11186 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
9e62e912 11187 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11188 }
bf61ee14 11189
b306f5ed 11190 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11191
bf61ee14
VZ		 11192 /*
11193 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11194 * disable the feature.
11195 */
2ba45142
VZ		 11196 if (!bp->cnic_eth_dev.max_fcoe_conn)
11197 bp->flags |= NO_FCOE_FLAG;
11198}
b306f5ed 11199
0329aba1 11200static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11201{
11202 /*
11203 * iSCSI may be dynamically disabled but reading
11204 * info here we will decrease memory usage by driver
11205 * if the feature is disabled for good
11206 */
11207 bnx2x_get_iscsi_info(bp);
11208 bnx2x_get_fcoe_info(bp);
11209}
2ba45142 11210
0329aba1 11211static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11212{
11213 u32 val, val2;
11214 int func = BP_ABS_FUNC(bp);
11215 int port = BP_PORT(bp);
2ba45142
VZ		 11216 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11217 u8 *fip_mac = bp->fip_mac;
0793f83f 11218
55c11941
MS		 11219 if (IS_MF(bp)) {
11220 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11221 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11222 * In non SD mode features configuration comes from struct
11223 * func_ext_config.
2ba45142 11224 */
55c11941 11225 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
0793f83f
DK		 11226 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11227 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11228 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11229 iscsi_mac_addr_upper);
0793f83f 11230 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11231 iscsi_mac_addr_lower);
2ba45142 11232 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11233 BNX2X_DEV_INFO
11234 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11235 } else {
2ba45142 11236 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11237 }
2ba45142
VZ		 11238
11239 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11240 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11241 fcoe_mac_addr_upper);
2ba45142 11242 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11243 fcoe_mac_addr_lower);
2ba45142 11244 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11245 BNX2X_DEV_INFO
11246 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11247 } else {
2ba45142 11248 bp->flags |= NO_FCOE_FLAG;
55c11941 11249 }
a3348722
BW		 11250
11251 bp->mf_ext_config = cfg;
11252
9e62e912 11253 } else { /* SD MODE */
55c11941
MS		 11254 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11255 /* use primary mac as iscsi mac */
11256 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11257
11258 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11259 BNX2X_DEV_INFO
11260 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11261 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11262 /* use primary mac as fip mac */
11263 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11264 BNX2X_DEV_INFO("SD FCoE MODE\n");
11265 BNX2X_DEV_INFO
11266 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11267 }
0793f83f 11268 }
a3348722 11269
82594f8f
YM		 11270 /* If this is a storage-only interface, use SAN mac as
11271 * primary MAC. Notice that for SD this is already the case,
11272 * as the SAN mac was copied from the primary MAC.
11273 */
11274 if (IS_MF_FCOE_AFEX(bp))
a3348722 11275 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11276 } else {
0793f83f 11277 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11278 iscsi_mac_upper);
0793f83f 11279 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11280 iscsi_mac_lower);
2ba45142 11281 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11282
11283 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11284 fcoe_fip_mac_upper);
c03bd39c 11285 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11286 fcoe_fip_mac_lower);
c03bd39c 11287 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11288 }
11289
55c11941 11290 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11291 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11292 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
426b9241
DK		 11293 memset(iscsi_mac, 0, ETH_ALEN);
11294 }
11295
55c11941 11296 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11297 if (!is_valid_ether_addr(fip_mac)) {
11298 bp->flags |= NO_FCOE_FLAG;
11299 memset(bp->fip_mac, 0, ETH_ALEN);
11300 }
55c11941
MS		 11301}
11302
0329aba1 11303static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11304{
11305 u32 val, val2;
11306 int func = BP_ABS_FUNC(bp);
11307 int port = BP_PORT(bp);
11308
11309 /* Zero primary MAC configuration */
11310 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11311
11312 if (BP_NOMCP(bp)) {
11313 BNX2X_ERROR("warning: random MAC workaround active\n");
11314 eth_hw_addr_random(bp->dev);
11315 } else if (IS_MF(bp)) {
11316 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11317 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11318 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11319 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11320 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11321
11322 if (CNIC_SUPPORT(bp))
11323 bnx2x_get_cnic_mac_hwinfo(bp);
11324 } else {
11325 /* in SF read MACs from port configuration */
11326 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11327 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11328 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11329
11330 if (CNIC_SUPPORT(bp))
11331 bnx2x_get_cnic_mac_hwinfo(bp);
11332 }
11333
3d7d562c
YM		 11334 if (!BP_NOMCP(bp)) {
11335 /* Read physical port identifier from shmem */
11336 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11337 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11338 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11339 bp->flags |= HAS_PHYS_PORT_ID;
11340 }
11341
55c11941 11342 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11343
614c76df 11344 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6 11345 dev_err(&bp->pdev->dev,
51c1a580
MS		 11346 "bad Ethernet MAC address configuration: %pM\n"
11347 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11348 bp->dev->dev_addr);
7964211d 11349}
51c1a580 11350
0329aba1 11351static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11352{
11353 int tmp;
11354 u32 cfg;
51c1a580 11355
aeeddb8b
YM		 11356 if (IS_VF(bp))
11357 return 0;
11358
7964211d
YM		 11359 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11360 /* Take function: tmp = func */
11361 tmp = BP_ABS_FUNC(bp);
11362 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11363 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11364 } else {
11365 /* Take port: tmp = port */
11366 tmp = BP_PORT(bp);
11367 cfg = SHMEM_RD(bp,
11368 dev_info.port_hw_config[tmp].generic_features);
11369 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11370 }
11371 return cfg;
34f80b04
EG		 11372}
11373
0329aba1 11374static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11375{
0793f83f 11376 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 11377 int vn;
0793f83f 11378 u32 val = 0;
34f80b04 11379 int rc = 0;
a2fbb9ea 11380
34f80b04 11381 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11382
6383c0b3
AE		 11383 /*
11384 * initialize IGU parameters
11385 */
f2e0899f
DK		 11386 if (CHIP_IS_E1x(bp)) {
11387 bp->common.int_block = INT_BLOCK_HC;
11388
11389 bp->igu_dsb_id = DEF_SB_IGU_ID;
11390 bp->igu_base_sb = 0;
f2e0899f
DK		 11391 } else {
11392 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 11393
16a5fd92 11394 /* do not allow device reset during IGU info processing */
7a06a122
DK		 11395 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11396
f2e0899f 11397 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 11398
11399 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11400 int tout = 5000;
11401
11402 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11403
11404 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11405 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11406 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11407
11408 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11409 tout--;
0926d499 11410 usleep_range(1000, 2000);
619c5cb6
VZ		 11411 }
11412
11413 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11414 dev_err(&bp->pdev->dev,
11415 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 11416 bnx2x_release_hw_lock(bp,
11417 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 11418 return -EPERM;
11419 }
11420 }
11421
f2e0899f 11422 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 11423 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 11424 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11425 } else
619c5cb6 11426 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 11427
9b341bb1 11428 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 11429 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 11430 if (rc)
11431 return rc;
f2e0899f 11432 }
619c5cb6
VZ		 11433
11434 /*
11435 * set base FW non-default (fast path) status block id, this value is
11436 * used to initialize the fw_sb_id saved on the fp/queue structure to
11437 * determine the id used by the FW.
11438 */
11439 if (CHIP_IS_E1x(bp))
11440 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11441 else /*
11442 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11443 * the same queue are indicated on the same IGU SB). So we prefer
11444 * FW and IGU SBs to be the same value.
11445 */
11446 bp->base_fw_ndsb = bp->igu_base_sb;
11447
11448 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11449 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11450 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 11451
11452 /*
11453 * Initialize MF configuration
11454 */
523224a3 11455
fb3bff17
DK		 11456 bp->mf_ov = 0;
11457 bp->mf_mode = 0;
3395a033 11458 vn = BP_VN(bp);
0793f83f 11459
f2e0899f 11460 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 11461 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11462 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11463 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11464
f2e0899f
DK		 11465 if (SHMEM2_HAS(bp, mf_cfg_addr))
11466 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11467 else
11468 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 11469 offsetof(struct shmem_region, func_mb) +
11470 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 11471 /*
11472 * get mf configuration:
16a5fd92 11473 * 1. Existence of MF configuration
0793f83f
DK		 11474 * 2. MAC address must be legal (check only upper bytes)
11475 * for Switch-Independent mode;
11476 * OVLAN must be legal for Switch-Dependent mode
11477 * 3. SF_MODE configures specific MF mode
11478 */
11479 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11480 /* get mf configuration */
11481 val = SHMEM_RD(bp,
11482 dev_info.shared_feature_config.config);
11483 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11484
11485 switch (val) {
11486 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11487 val = MF_CFG_RD(bp, func_mf_config[func].
11488 mac_upper);
11489 /* check for legal mac (upper bytes)*/
11490 if (val != 0xffff) {
11491 bp->mf_mode = MULTI_FUNCTION_SI;
11492 bp->mf_config[vn] = MF_CFG_RD(bp,
11493 func_mf_config[func].config);
11494 } else
51c1a580 11495 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f 11496 break;
a3348722
BW		 11497 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11498 if ((!CHIP_IS_E1x(bp)) &&
11499 (MF_CFG_RD(bp, func_mf_config[func].
11500 mac_upper) != 0xffff) &&
11501 (SHMEM2_HAS(bp,
11502 afex_driver_support))) {
11503 bp->mf_mode = MULTI_FUNCTION_AFEX;
11504 bp->mf_config[vn] = MF_CFG_RD(bp,
11505 func_mf_config[func].config);
11506 } else {
11507 BNX2X_DEV_INFO("can not configure afex mode\n");
11508 }
11509 break;
0793f83f
DK		 11510 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11511 /* get OV configuration */
11512 val = MF_CFG_RD(bp,
11513 func_mf_config[FUNC_0].e1hov_tag);
11514 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11515
11516 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11517 bp->mf_mode = MULTI_FUNCTION_SD;
11518 bp->mf_config[vn] = MF_CFG_RD(bp,
11519 func_mf_config[func].config);
11520 } else
754a2f52 11521 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 11522 break;
3786b942
AE		 11523 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11524 bp->mf_config[vn] = 0;
11525 break;
0793f83f
DK		 11526 default:
11527 /* Unknown configuration: reset mf_config */
11528 bp->mf_config[vn] = 0;
51c1a580 11529 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 11530 }
11531 }
a2fbb9ea 11532
2691d51d 11533 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 11534 IS_MF(bp) ? "multi" : "single");
2691d51d 11535
0793f83f
DK		 11536 switch (bp->mf_mode) {
11537 case MULTI_FUNCTION_SD:
11538 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11539 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 11540 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 11541 bp->mf_ov = val;
619c5cb6
VZ		 11542 bp->path_has_ovlan = true;
11543
51c1a580
MS		 11544 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11545 func, bp->mf_ov, bp->mf_ov);
2691d51d 11546 } else {
619c5cb6 11547 dev_err(&bp->pdev->dev,
51c1a580
MS		 11548 "No valid MF OV for func %d, aborting\n",
11549 func);
619c5cb6 11550 return -EPERM;
34f80b04 11551 }
0793f83f 11552 break;
a3348722
BW		 11553 case MULTI_FUNCTION_AFEX:
11554 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11555 break;
0793f83f 11556 case MULTI_FUNCTION_SI:
51c1a580
MS		 11557 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11558 func);
0793f83f
DK		 11559 break;
11560 default:
11561 if (vn) {
619c5cb6 11562 dev_err(&bp->pdev->dev,
51c1a580
MS		 11563 "VN %d is in a single function mode, aborting\n",
11564 vn);
619c5cb6 11565 return -EPERM;
2691d51d 11566 }
0793f83f 11567 break;
34f80b04 11568 }
0793f83f 11569
619c5cb6
VZ		 11570 /* check if other port on the path needs ovlan:
11571 * Since MF configuration is shared between ports
11572 * Possible mixed modes are only
11573 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11574 */
11575 if (CHIP_MODE_IS_4_PORT(bp) &&
11576 !bp->path_has_ovlan &&
11577 !IS_MF(bp) &&
11578 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11579 u8 other_port = !BP_PORT(bp);
11580 u8 other_func = BP_PATH(bp) + 2*other_port;
11581 val = MF_CFG_RD(bp,
11582 func_mf_config[other_func].e1hov_tag);
11583 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11584 bp->path_has_ovlan = true;
11585 }
34f80b04 11586 }
a2fbb9ea 11587
e848582c
DK		 11588 /* adjust igu_sb_cnt to MF for E1H */
11589 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11590 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 11591
619c5cb6
VZ		 11592 /* port info */
11593 bnx2x_get_port_hwinfo(bp);
f2e0899f 11594
0793f83f
DK		 11595 /* Get MAC addresses */
11596 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 11597
2ba45142 11598 bnx2x_get_cnic_info(bp);
2ba45142 11599
34f80b04
EG		 11600 return rc;
11601}
11602
0329aba1 11603static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 11604{
11605 int cnt, i, block_end, rodi;
fcdf95cb 11606 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 11607 char str_id_reg[VENDOR_ID_LEN+1];
11608 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 11609 char *vpd_data;
11610 char *vpd_extended_data = NULL;
34f24c7f
VZ		 11611 u8 len;
11612
fcdf95cb 11613 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 11614 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11615
11616 if (cnt < BNX2X_VPD_LEN)
11617 goto out_not_found;
11618
fcdf95cb
BW		 11619 /* VPD RO tag should be first tag after identifier string, hence
11620 * we should be able to find it in first BNX2X_VPD_LEN chars
11621 */
11622 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 11623 PCI_VPD_LRDT_RO_DATA);
11624 if (i < 0)
11625 goto out_not_found;
11626
34f24c7f 11627 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 11628 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 11629
11630 i += PCI_VPD_LRDT_TAG_SIZE;
11631
fcdf95cb
BW		 11632 if (block_end > BNX2X_VPD_LEN) {
11633 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11634 if (vpd_extended_data == NULL)
11635 goto out_not_found;
11636
11637 /* read rest of vpd image into vpd_extended_data */
11638 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11639 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11640 block_end - BNX2X_VPD_LEN,
11641 vpd_extended_data + BNX2X_VPD_LEN);
11642 if (cnt < (block_end - BNX2X_VPD_LEN))
11643 goto out_not_found;
11644 vpd_data = vpd_extended_data;
11645 } else
11646 vpd_data = vpd_start;
11647
11648 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 11649
11650 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11651 PCI_VPD_RO_KEYWORD_MFR_ID);
11652 if (rodi < 0)
11653 goto out_not_found;
11654
11655 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11656
11657 if (len != VENDOR_ID_LEN)
11658 goto out_not_found;
11659
11660 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11661
11662 /* vendor specific info */
11663 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11664 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11665 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11666 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11667
11668 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11669 PCI_VPD_RO_KEYWORD_VENDOR0);
11670 if (rodi >= 0) {
11671 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11672
11673 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11674
11675 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11676 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11677 bp->fw_ver[len] = ' ';
11678 }
11679 }
fcdf95cb 11680 kfree(vpd_extended_data);
34f24c7f
VZ		 11681 return;
11682 }
11683out_not_found:
fcdf95cb 11684 kfree(vpd_extended_data);
34f24c7f
VZ		 11685 return;
11686}
11687
0329aba1 11688static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 11689{
11690 u32 flags = 0;
11691
11692 if (CHIP_REV_IS_FPGA(bp))
11693 SET_FLAGS(flags, MODE_FPGA);
11694 else if (CHIP_REV_IS_EMUL(bp))
11695 SET_FLAGS(flags, MODE_EMUL);
11696 else
11697 SET_FLAGS(flags, MODE_ASIC);
11698
11699 if (CHIP_MODE_IS_4_PORT(bp))
11700 SET_FLAGS(flags, MODE_PORT4);
11701 else
11702 SET_FLAGS(flags, MODE_PORT2);
11703
11704 if (CHIP_IS_E2(bp))
11705 SET_FLAGS(flags, MODE_E2);
11706 else if (CHIP_IS_E3(bp)) {
11707 SET_FLAGS(flags, MODE_E3);
11708 if (CHIP_REV(bp) == CHIP_REV_Ax)
11709 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 11710 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11711 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 11712 }
11713
11714 if (IS_MF(bp)) {
11715 SET_FLAGS(flags, MODE_MF);
11716 switch (bp->mf_mode) {
11717 case MULTI_FUNCTION_SD:
11718 SET_FLAGS(flags, MODE_MF_SD);
11719 break;
11720 case MULTI_FUNCTION_SI:
11721 SET_FLAGS(flags, MODE_MF_SI);
11722 break;
a3348722
BW		 11723 case MULTI_FUNCTION_AFEX:
11724 SET_FLAGS(flags, MODE_MF_AFEX);
11725 break;
619c5cb6
VZ		 11726 }
11727 } else
11728 SET_FLAGS(flags, MODE_SF);
11729
11730#if defined(__LITTLE_ENDIAN)
11731 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11732#else /*(__BIG_ENDIAN)*/
11733 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11734#endif
11735 INIT_MODE_FLAGS(bp) = flags;
11736}
11737
0329aba1 11738static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 11739{
f2e0899f 11740 int func;
34f80b04
EG		 11741 int rc;
11742
34f80b04 11743 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 11744 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 11745 spin_lock_init(&bp->stats_lock);
507393eb 11746 sema_init(&bp->stats_sema, 1);
55c11941 11747
1cf167f2 11748 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 11749 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 11750 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
1ab4434c
AE		 11751 if (IS_PF(bp)) {
11752 rc = bnx2x_get_hwinfo(bp);
11753 if (rc)
11754 return rc;
11755 } else {
e09b74d0 11756 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 11757 }
34f80b04 11758
619c5cb6
VZ		 11759 bnx2x_set_modes_bitmap(bp);
11760
11761 rc = bnx2x_alloc_mem_bp(bp);
11762 if (rc)
11763 return rc;
523224a3 11764
34f24c7f 11765 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 11766
11767 func = BP_FUNC(bp);
11768
34f80b04 11769 /* need to reset chip if undi was active */
1ab4434c 11770 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 11771 /* init fw_seq */
11772 bp->fw_seq =
11773 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11774 DRV_MSG_SEQ_NUMBER_MASK;
11775 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11776
91ebb929
YM		 11777 rc = bnx2x_prev_unload(bp);
11778 if (rc) {
11779 bnx2x_free_mem_bp(bp);
11780 return rc;
11781 }
452427b0
YM		 11782 }
11783
34f80b04 11784 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 11785 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 11786
11787 if (BP_NOMCP(bp) && (func == 0))
51c1a580 11788 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 11789
614c76df 11790 bp->disable_tpa = disable_tpa;
a3348722 11791 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
614c76df 11792
7a9b2557 11793 /* Set TPA flags */
614c76df 11794 if (bp->disable_tpa) {
621b4d66 11795 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11796 bp->dev->features &= ~NETIF_F_LRO;
11797 } else {
621b4d66 11798 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11799 bp->dev->features |= NETIF_F_LRO;
11800 }
11801
a18f5128
EG		 11802 if (CHIP_IS_E1(bp))
11803 bp->dropless_fc = 0;
11804 else
7964211d 11805 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 11806
8d5726c4 11807 bp->mrrs = mrrs;
7a9b2557 11808
a3348722 11809 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 11810 if (IS_VF(bp))
11811 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 11812
7d323bfd 11813 /* make sure that the numbers are in the right granularity */
523224a3
DK		 11814 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11815 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 11816
fc543637 11817 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 11818
11819 init_timer(&bp->timer);
11820 bp->timer.expires = jiffies + bp->current_interval;
11821 bp->timer.data = (unsigned long) bp;
11822 bp->timer.function = bnx2x_timer;
11823
0370cf90
BW		 11824 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11825 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11826 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11827 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11828 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11829 bnx2x_dcbx_init_params(bp);
11830 } else {
11831 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11832 }
e4901dde 11833
619c5cb6
VZ		 11834 if (CHIP_IS_E1x(bp))
11835 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11836 else
11837 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 11838
6383c0b3 11839 /* multiple tx priority */
1ab4434c
AE		 11840 if (IS_VF(bp))
11841 bp->max_cos = 1;
11842 else if (CHIP_IS_E1x(bp))
6383c0b3 11843 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 11844 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 11845 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 11846 else if (CHIP_IS_E3B0(bp))
6383c0b3 11847 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 11848 else
11849 BNX2X_ERR("unknown chip %x revision %x\n",
11850 CHIP_NUM(bp), CHIP_REV(bp));
11851 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 11852
55c11941
MS		 11853 /* We need at least one default status block for slow-path events,
11854 * second status block for the L2 queue, and a third status block for
16a5fd92 11855 * CNIC if supported.
55c11941 11856 */
60cad4e6
AE		 11857 if (IS_VF(bp))
11858 bp->min_msix_vec_cnt = 1;
11859 else if (CNIC_SUPPORT(bp))
55c11941 11860 bp->min_msix_vec_cnt = 3;
60cad4e6 11861 else /* PF w/o cnic */
55c11941
MS		 11862 bp->min_msix_vec_cnt = 2;
11863 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11864
5bb680d6
MS		 11865 bp->dump_preset_idx = 1;
11866
34f80b04 11867 return rc;
a2fbb9ea
ET		 11868}
11869
de0c62db
DK		 11870/****************************************************************************
11871* General service functions
11872****************************************************************************/
a2fbb9ea 11873
619c5cb6
VZ		 11874/*
11875 * net_device service functions
11876 */
11877
bb2a0f7a 11878/* called with rtnl_lock */
a2fbb9ea
ET		 11879static int bnx2x_open(struct net_device *dev)
11880{
11881 struct bnx2x *bp = netdev_priv(dev);
8395be5e 11882 int rc;
a2fbb9ea 11883
1355b704
MY		 11884 bp->stats_init = true;
11885
6eccabb3
EG		 11886 netif_carrier_off(dev);
11887
a2fbb9ea
ET		 11888 bnx2x_set_power_state(bp, PCI_D0);
11889
ad5afc89 11890 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 11891 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11892 * want the first function loaded on the current engine to
11893 * complete the recovery.
ad5afc89 11894 * Parity recovery is only relevant for PF driver.
c9ee9206 11895 */
ad5afc89 11896 if (IS_PF(bp)) {
1a6974b2
YM		 11897 int other_engine = BP_PATH(bp) ? 0 : 1;
11898 bool other_load_status, load_status;
11899 bool global = false;
11900
ad5afc89
AE		 11901 other_load_status = bnx2x_get_load_status(bp, other_engine);
11902 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11903 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11904 bnx2x_chk_parity_attn(bp, &global, true)) {
11905 do {
11906 /* If there are attentions and they are in a
11907 * global blocks, set the GLOBAL_RESET bit
11908 * regardless whether it will be this function
11909 * that will complete the recovery or not.
11910 */
11911 if (global)
11912 bnx2x_set_reset_global(bp);
72fd0718 11913
ad5afc89
AE		 11914 /* Only the first function on the current
11915 * engine should try to recover in open. In case
11916 * of attentions in global blocks only the first
11917 * in the chip should try to recover.
11918 */
11919 if ((!load_status &&
11920 (!global || !other_load_status)) &&
11921 bnx2x_trylock_leader_lock(bp) &&
11922 !bnx2x_leader_reset(bp)) {
11923 netdev_info(bp->dev,
11924 "Recovered in open\n");
11925 break;
11926 }
72fd0718 11927
ad5afc89
AE		 11928 /* recovery has failed... */
11929 bnx2x_set_power_state(bp, PCI_D3hot);
11930 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 11931
ad5afc89
AE		 11932 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11933 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 11934
ad5afc89
AE		 11935 return -EAGAIN;
11936 } while (0);
11937 }
11938 }
72fd0718
VZ		 11939
11940 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 11941 rc = bnx2x_nic_load(bp, LOAD_OPEN);
11942 if (rc)
11943 return rc;
9a8130bc 11944 return 0;
a2fbb9ea
ET		 11945}
11946
bb2a0f7a 11947/* called with rtnl_lock */
56ad3152 11948static int bnx2x_close(struct net_device *dev)
a2fbb9ea 11949{
a2fbb9ea
ET		 11950 struct bnx2x *bp = netdev_priv(dev);
11951
11952 /* Unload the driver, release IRQs */
5d07d868 11953 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 11954
a2fbb9ea
ET		 11955 return 0;
11956}
11957
1191cb83
ED		 11958static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11959 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 11960{
619c5cb6
VZ		 11961 int mc_count = netdev_mc_count(bp->dev);
11962 struct bnx2x_mcast_list_elem *mc_mac =
11963 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11964 struct netdev_hw_addr *ha;
6e30dd4e 11965
619c5cb6
VZ		 11966 if (!mc_mac)
11967 return -ENOMEM;
6e30dd4e 11968
619c5cb6 11969 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 11970
619c5cb6
VZ		 11971 netdev_for_each_mc_addr(ha, bp->dev) {
11972 mc_mac->mac = bnx2x_mc_addr(ha);
11973 list_add_tail(&mc_mac->link, &p->mcast_list);
11974 mc_mac++;
6e30dd4e 11975 }
619c5cb6
VZ		 11976
11977 p->mcast_list_len = mc_count;
11978
11979 return 0;
6e30dd4e
VZ		 11980}
11981
1191cb83 11982static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 11983 struct bnx2x_mcast_ramrod_params *p)
11984{
11985 struct bnx2x_mcast_list_elem *mc_mac =
11986 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11987 link);
11988
11989 WARN_ON(!mc_mac);
11990 kfree(mc_mac);
11991}
11992
11993/**
11994 * bnx2x_set_uc_list - configure a new unicast MACs list.
11995 *
11996 * @bp: driver handle
6e30dd4e 11997 *
619c5cb6 11998 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 11999 */
1191cb83 12000static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12001{
619c5cb6 12002 int rc;
6e30dd4e 12003 struct net_device *dev = bp->dev;
6e30dd4e 12004 struct netdev_hw_addr *ha;
15192a8c 12005 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12006 unsigned long ramrod_flags = 0;
6e30dd4e 12007
619c5cb6
VZ		 12008 /* First schedule a cleanup up of old configuration */
12009 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12010 if (rc < 0) {
12011 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12012 return rc;
12013 }
6e30dd4e
VZ		 12014
12015 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12016 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12017 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12018 if (rc == -EEXIST) {
12019 DP(BNX2X_MSG_SP,
12020 "Failed to schedule ADD operations: %d\n", rc);
12021 /* do not treat adding same MAC as error */
12022 rc = 0;
12023
12024 } else if (rc < 0) {
12025
619c5cb6
VZ		 12026 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12027 rc);
12028 return rc;
6e30dd4e
VZ		 12029 }
12030 }
12031
619c5cb6
VZ		 12032 /* Execute the pending commands */
12033 __set_bit(RAMROD_CONT, &ramrod_flags);
12034 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12035 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12036}
12037
1191cb83 12038static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 12039{
619c5cb6 12040 struct net_device *dev = bp->dev;
3b603066 12041 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12042 int rc = 0;
6e30dd4e 12043
619c5cb6 12044 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12045
619c5cb6
VZ		 12046 /* first, clear all configured multicast MACs */
12047 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12048 if (rc < 0) {
51c1a580 12049 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12050 return rc;
12051 }
6e30dd4e 12052
619c5cb6
VZ		 12053 /* then, configure a new MACs list */
12054 if (netdev_mc_count(dev)) {
12055 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12056 if (rc) {
51c1a580
MS		 12057 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12058 rc);
619c5cb6
VZ		 12059 return rc;
12060 }
6e30dd4e 12061
619c5cb6
VZ		 12062 /* Now add the new MACs */
12063 rc = bnx2x_config_mcast(bp, &rparam,
12064 BNX2X_MCAST_CMD_ADD);
12065 if (rc < 0)
51c1a580
MS		 12066 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12067 rc);
6e30dd4e 12068
619c5cb6
VZ		 12069 bnx2x_free_mcast_macs_list(&rparam);
12070 }
6e30dd4e 12071
619c5cb6 12072 return rc;
6e30dd4e
VZ		 12073}
12074
619c5cb6 12075/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12076static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12077{
12078 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12079
12080 if (bp->state != BNX2X_STATE_OPEN) {
12081 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12082 return;
8b09be5f
YM		 12083 } else {
12084 /* Schedule an SP task to handle rest of change */
12085 DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n");
12086 smp_mb__before_clear_bit();
12087 set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state);
12088 smp_mb__after_clear_bit();
12089 schedule_delayed_work(&bp->sp_rtnl_task, 0);
34f80b04 12090 }
8b09be5f
YM		 12091}
12092
12093void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12094{
12095 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12096
619c5cb6 12097 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12098
8b09be5f
YM		 12099 netif_addr_lock_bh(bp->dev);
12100
12101 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12102 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12103 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12104 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12105 CHIP_IS_E1(bp))) {
34f80b04 12106 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12107 } else {
381ac16b
AE		 12108 if (IS_PF(bp)) {
12109 /* some multicasts */
12110 if (bnx2x_set_mc_list(bp) < 0)
12111 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12112
8b09be5f
YM		 12113 /* release bh lock, as bnx2x_set_uc_list might sleep */
12114 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12115 if (bnx2x_set_uc_list(bp) < 0)
12116 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12117 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12118 } else {
12119 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12120 * wait for the pf's response).
381ac16b
AE		 12121 */
12122 smp_mb__before_clear_bit();
12123 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
12124 &bp->sp_rtnl_state);
12125 smp_mb__after_clear_bit();
12126 schedule_delayed_work(&bp->sp_rtnl_task, 0);
12127 }
34f80b04
EG		 12128 }
12129
12130 bp->rx_mode = rx_mode;
614c76df
DK		 12131 /* handle ISCSI SD mode */
12132 if (IS_MF_ISCSI_SD(bp))
12133 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12134
12135 /* Schedule the rx_mode command */
12136 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12137 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12138 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12139 return;
12140 }
12141
381ac16b
AE		 12142 if (IS_PF(bp)) {
12143 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12144 netif_addr_unlock_bh(bp->dev);
381ac16b 12145 } else {
8b09be5f
YM		 12146 /* VF will need to request the PF to make this change, and so
12147 * the VF needs to release the bottom-half lock prior to the
12148 * request (as it will likely require sleep on the VF side)
381ac16b 12149 */
8b09be5f
YM		 12150 netif_addr_unlock_bh(bp->dev);
12151 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12152 }
34f80b04
EG		 12153}
12154
c18487ee 12155/* called with rtnl_lock */
01cd4528
EG		 12156static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12157 int devad, u16 addr)
a2fbb9ea 12158{
01cd4528
EG		 12159 struct bnx2x *bp = netdev_priv(netdev);
12160 u16 value;
12161 int rc;
a2fbb9ea 12162
01cd4528
EG		 12163 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12164 prtad, devad, addr);
a2fbb9ea 12165
01cd4528
EG		 12166 /* The HW expects different devad if CL22 is used */
12167 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12168
01cd4528 12169 bnx2x_acquire_phy_lock(bp);
e10bc84d 12170 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12171 bnx2x_release_phy_lock(bp);
12172 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12173
01cd4528
EG		 12174 if (!rc)
12175 rc = value;
12176 return rc;
12177}
a2fbb9ea 12178
01cd4528
EG		 12179/* called with rtnl_lock */
12180static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12181 u16 addr, u16 value)
12182{
12183 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12184 int rc;
12185
51c1a580
MS		 12186 DP(NETIF_MSG_LINK,
12187 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12188 prtad, devad, addr, value);
01cd4528 12189
01cd4528
EG		 12190 /* The HW expects different devad if CL22 is used */
12191 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12192
01cd4528 12193 bnx2x_acquire_phy_lock(bp);
e10bc84d 12194 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12195 bnx2x_release_phy_lock(bp);
12196 return rc;
12197}
c18487ee 12198
01cd4528
EG		 12199/* called with rtnl_lock */
12200static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12201{
12202 struct bnx2x *bp = netdev_priv(dev);
12203 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12204
01cd4528
EG		 12205 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12206 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 12207
01cd4528
EG		 12208 if (!netif_running(dev))
12209 return -EAGAIN;
12210
12211 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 12212}
12213
257ddbda 12214#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 12215static void poll_bnx2x(struct net_device *dev)
12216{
12217 struct bnx2x *bp = netdev_priv(dev);
14a15d61 12218 int i;
a2fbb9ea 12219
14a15d61
MS		 12220 for_each_eth_queue(bp, i) {
12221 struct bnx2x_fastpath *fp = &bp->fp[i];
12222 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12223 }
a2fbb9ea
ET		 12224}
12225#endif
12226
614c76df
DK		 12227static int bnx2x_validate_addr(struct net_device *dev)
12228{
12229 struct bnx2x *bp = netdev_priv(dev);
12230
e09b74d0
AE		 12231 /* query the bulletin board for mac address configured by the PF */
12232 if (IS_VF(bp))
12233 bnx2x_sample_bulletin(bp);
12234
51c1a580
MS		 12235 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12236 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12237 return -EADDRNOTAVAIL;
51c1a580 12238 }
614c76df
DK		 12239 return 0;
12240}
12241
3d7d562c
YM		 12242static int bnx2x_get_phys_port_id(struct net_device *netdev,
12243 struct netdev_phys_port_id *ppid)
12244{
12245 struct bnx2x *bp = netdev_priv(netdev);
12246
12247 if (!(bp->flags & HAS_PHYS_PORT_ID))
12248 return -EOPNOTSUPP;
12249
12250 ppid->id_len = sizeof(bp->phys_port_id);
12251 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12252
12253 return 0;
12254}
12255
c64213cd
SH		 12256static const struct net_device_ops bnx2x_netdev_ops = {
12257 .ndo_open = bnx2x_open,
12258 .ndo_stop = bnx2x_close,
12259 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 12260 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 12261 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 12262 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 12263 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 12264 .ndo_do_ioctl = bnx2x_ioctl,
12265 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 12266 .ndo_fix_features = bnx2x_fix_features,
12267 .ndo_set_features = bnx2x_set_features,
c64213cd 12268 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 12269#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 12270 .ndo_poll_controller = poll_bnx2x,
12271#endif
6383c0b3 12272 .ndo_setup_tc = bnx2x_setup_tc,
6411280a 12273#ifdef CONFIG_BNX2X_SRIOV
abc5a021 12274 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 12275 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 12276 .ndo_get_vf_config = bnx2x_get_vf_config,
6411280a 12277#endif
55c11941 12278#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 12279 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12280#endif
8f20aa57 12281
e0d1095a 12282#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 12283 .ndo_busy_poll = bnx2x_low_latency_recv,
8f20aa57 12284#endif
3d7d562c 12285 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
c64213cd
SH		 12286};
12287
1191cb83 12288static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 12289{
12290 struct device *dev = &bp->pdev->dev;
12291
8ceafbfa
LT		 12292 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12293 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 12294 dev_err(dev, "System does not support DMA, aborting\n");
12295 return -EIO;
12296 }
12297
12298 return 0;
12299}
12300
33d8e6a5
YM		 12301static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12302{
12303 if (bp->flags & AER_ENABLED) {
12304 pci_disable_pcie_error_reporting(bp->pdev);
12305 bp->flags &= ~AER_ENABLED;
12306 }
12307}
12308
1ab4434c
AE		 12309static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12310 struct net_device *dev, unsigned long board_type)
a2fbb9ea 12311{
a2fbb9ea 12312 int rc;
c22610d0 12313 u32 pci_cfg_dword;
65087cfe
AE		 12314 bool chip_is_e1x = (board_type == BCM57710 ||
12315 board_type == BCM57711 ||
12316 board_type == BCM57711E);
a2fbb9ea
ET		 12317
12318 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 12319
34f80b04
EG		 12320 bp->dev = dev;
12321 bp->pdev = pdev;
a2fbb9ea
ET		 12322
12323 rc = pci_enable_device(pdev);
12324 if (rc) {
cdaa7cb8
VZ		 12325 dev_err(&bp->pdev->dev,
12326 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 12327 goto err_out;
12328 }
12329
12330 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 12331 dev_err(&bp->pdev->dev,
12332 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 12333 rc = -ENODEV;
12334 goto err_out_disable;
12335 }
12336
1ab4434c
AE		 12337 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12338 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 12339 rc = -ENODEV;
12340 goto err_out_disable;
12341 }
12342
092a5fc9
YR		 12343 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12344 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12345 PCICFG_REVESION_ID_ERROR_VAL) {
12346 pr_err("PCI device error, probably due to fan failure, aborting\n");
12347 rc = -ENODEV;
12348 goto err_out_disable;
12349 }
12350
34f80b04
EG		 12351 if (atomic_read(&pdev->enable_cnt) == 1) {
12352 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12353 if (rc) {
cdaa7cb8
VZ		 12354 dev_err(&bp->pdev->dev,
12355 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 12356 goto err_out_disable;
12357 }
a2fbb9ea 12358
34f80b04
EG		 12359 pci_set_master(pdev);
12360 pci_save_state(pdev);
12361 }
a2fbb9ea 12362
1ab4434c 12363 if (IS_PF(bp)) {
29ed74c3 12364 if (!pdev->pm_cap) {
1ab4434c
AE		 12365 dev_err(&bp->pdev->dev,
12366 "Cannot find power management capability, aborting\n");
12367 rc = -EIO;
12368 goto err_out_release;
12369 }
a2fbb9ea
ET		 12370 }
12371
77c98e6a 12372 if (!pci_is_pcie(pdev)) {
51c1a580 12373 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 12374 rc = -EIO;
12375 goto err_out_release;
12376 }
12377
619c5cb6
VZ		 12378 rc = bnx2x_set_coherency_mask(bp);
12379 if (rc)
a2fbb9ea 12380 goto err_out_release;
a2fbb9ea 12381
34f80b04
EG		 12382 dev->mem_start = pci_resource_start(pdev, 0);
12383 dev->base_addr = dev->mem_start;
12384 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 12385
12386 dev->irq = pdev->irq;
12387
275f165f 12388 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 12389 if (!bp->regview) {
cdaa7cb8
VZ		 12390 dev_err(&bp->pdev->dev,
12391 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 12392 rc = -ENOMEM;
12393 goto err_out_release;
12394 }
12395
c22610d0
AE		 12396 /* In E1/E1H use pci device function given by kernel.
12397 * In E2/E3 read physical function from ME register since these chips
12398 * support Physical Device Assignment where kernel BDF maybe arbitrary
12399 * (depending on hypervisor).
12400 */
2de67439 12401 if (chip_is_e1x) {
c22610d0 12402 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 12403 } else {
12404 /* chip is E2/3*/
c22610d0
AE		 12405 pci_read_config_dword(bp->pdev,
12406 PCICFG_ME_REGISTER, &pci_cfg_dword);
12407 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 12408 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 12409 }
51c1a580 12410 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 12411
34f80b04
EG		 12412 /* clean indirect addresses */
12413 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12414 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5
YM		 12415
12416 /* AER (Advanced Error reporting) configuration */
12417 rc = pci_enable_pcie_error_reporting(pdev);
12418 if (!rc)
12419 bp->flags |= AER_ENABLED;
12420 else
12421 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12422
a5c53dbc
DK		 12423 /*
12424 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 12425 * is not used by the driver.
12426 */
1ab4434c
AE		 12427 if (IS_PF(bp)) {
12428 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12429 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12430 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12431 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12432
12433 if (chip_is_e1x) {
12434 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12435 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12436 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12437 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12438 }
a5c53dbc 12439
1ab4434c
AE		 12440 /* Enable internal target-read (in case we are probed after PF
12441 * FLR). Must be done prior to any BAR read access. Only for
12442 * 57712 and up
12443 */
12444 if (!chip_is_e1x)
12445 REG_WR(bp,
12446 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 12447 }
a2fbb9ea 12448
34f80b04 12449 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 12450
c64213cd 12451 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 12452 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 12453
01789349
JP		 12454 dev->priv_flags |= IFF_UNICAST_FLT;
12455
66371c44 12456 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 12457 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12458 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
f646968f 12459 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a848ade4 12460 if (!CHIP_IS_E1x(bp)) {
117401ee 12461 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
2e3bd6a4 12462 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
a848ade4
DK		 12463 dev->hw_enc_features =
12464 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12465 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
117401ee 12466 NETIF_F_GSO_IPIP |
2e3bd6a4 12467 NETIF_F_GSO_SIT |
65bc0cfe 12468 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
a848ade4 12469 }
66371c44
MM		 12470
12471 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12472 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12473
f646968f 12474 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 12475 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 12476
538dd2e3
MB		 12477 /* Add Loopback capability to the device */
12478 dev->hw_features |= NETIF_F_LOOPBACK;
12479
98507672 12480#ifdef BCM_DCBNL
785b9b1a
SR		 12481 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12482#endif
12483
01cd4528
EG		 12484 /* get_port_hwinfo() will set prtad and mmds properly */
12485 bp->mdio.prtad = MDIO_PRTAD_NONE;
12486 bp->mdio.mmds = 0;
12487 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12488 bp->mdio.dev = dev;
12489 bp->mdio.mdio_read = bnx2x_mdio_read;
12490 bp->mdio.mdio_write = bnx2x_mdio_write;
12491
a2fbb9ea
ET		 12492 return 0;
12493
a2fbb9ea 12494err_out_release:
34f80b04
EG		 12495 if (atomic_read(&pdev->enable_cnt) == 1)
12496 pci_release_regions(pdev);
a2fbb9ea
ET		 12497
12498err_out_disable:
12499 pci_disable_device(pdev);
a2fbb9ea
ET		 12500
12501err_out:
12502 return rc;
12503}
12504
6891dd25 12505static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 12506{
37f9ce62 12507 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 12508 struct bnx2x_fw_file_hdr *fw_hdr;
12509 struct bnx2x_fw_file_section *sections;
94a78b79 12510 u32 offset, len, num_ops;
86564c3f 12511 __be16 *ops_offsets;
94a78b79 12512 int i;
37f9ce62 12513 const u8 *fw_ver;
94a78b79 12514
51c1a580
MS		 12515 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12516 BNX2X_ERR("Wrong FW size\n");
94a78b79 12517 return -EINVAL;
51c1a580 12518 }
94a78b79
VZ		 12519
12520 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12521 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12522
12523 /* Make sure none of the offsets and sizes make us read beyond
12524 * the end of the firmware data */
12525 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12526 offset = be32_to_cpu(sections[i].offset);
12527 len = be32_to_cpu(sections[i].len);
12528 if (offset + len > firmware->size) {
51c1a580 12529 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 12530 return -EINVAL;
12531 }
12532 }
12533
12534 /* Likewise for the init_ops offsets */
12535 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 12536 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 12537 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12538
12539 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12540 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 12541 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 12542 return -EINVAL;
12543 }
12544 }
12545
12546 /* Check FW version */
12547 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12548 fw_ver = firmware->data + offset;
12549 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12550 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12551 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12552 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 12553 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12554 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12555 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 12556 BCM_5710_FW_MINOR_VERSION,
12557 BCM_5710_FW_REVISION_VERSION,
12558 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 12559 return -EINVAL;
94a78b79
VZ		 12560 }
12561
12562 return 0;
12563}
12564
1191cb83 12565static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12566{
ab6ad5a4
EG		 12567 const __be32 *source = (const __be32 *)_source;
12568 u32 *target = (u32 *)_target;
94a78b79 12569 u32 i;
94a78b79
VZ		 12570
12571 for (i = 0; i < n/4; i++)
12572 target[i] = be32_to_cpu(source[i]);
12573}
12574
12575/*
12576 Ops array is stored in the following format:
12577 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12578 */
1191cb83 12579static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 12580{
ab6ad5a4
EG		 12581 const __be32 *source = (const __be32 *)_source;
12582 struct raw_op *target = (struct raw_op *)_target;
94a78b79 12583 u32 i, j, tmp;
94a78b79 12584
ab6ad5a4 12585 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 12586 tmp = be32_to_cpu(source[j]);
12587 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 12588 target[i].offset = tmp & 0xffffff;
12589 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 12590 }
12591}
ab6ad5a4 12592
1aa8b471 12593/* IRO array is stored in the following format:
523224a3
DK		 12594 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12595 */
1191cb83 12596static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 12597{
12598 const __be32 *source = (const __be32 *)_source;
12599 struct iro *target = (struct iro *)_target;
12600 u32 i, j, tmp;
12601
12602 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12603 target[i].base = be32_to_cpu(source[j]);
12604 j++;
12605 tmp = be32_to_cpu(source[j]);
12606 target[i].m1 = (tmp >> 16) & 0xffff;
12607 target[i].m2 = tmp & 0xffff;
12608 j++;
12609 tmp = be32_to_cpu(source[j]);
12610 target[i].m3 = (tmp >> 16) & 0xffff;
12611 target[i].size = tmp & 0xffff;
12612 j++;
12613 }
12614}
12615
1191cb83 12616static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 12617{
ab6ad5a4
EG		 12618 const __be16 *source = (const __be16 *)_source;
12619 u16 *target = (u16 *)_target;
94a78b79 12620 u32 i;
94a78b79
VZ		 12621
12622 for (i = 0; i < n/2; i++)
12623 target[i] = be16_to_cpu(source[i]);
12624}
12625
7995c64e
JP		 12626#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12627do { \
12628 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12629 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 12630 if (!bp->arr) \
7995c64e 12631 goto lbl; \
7995c64e
JP		 12632 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12633 (u8 *)bp->arr, len); \
12634} while (0)
94a78b79 12635
3b603066 12636static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 12637{
c0ea452e 12638 const char *fw_file_name;
94a78b79 12639 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 12640 int rc;
94a78b79 12641
c0ea452e
MS		 12642 if (bp->firmware)
12643 return 0;
94a78b79 12644
c0ea452e
MS		 12645 if (CHIP_IS_E1(bp))
12646 fw_file_name = FW_FILE_NAME_E1;
12647 else if (CHIP_IS_E1H(bp))
12648 fw_file_name = FW_FILE_NAME_E1H;
12649 else if (!CHIP_IS_E1x(bp))
12650 fw_file_name = FW_FILE_NAME_E2;
12651 else {
12652 BNX2X_ERR("Unsupported chip revision\n");
12653 return -EINVAL;
12654 }
12655 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 12656
c0ea452e
MS		 12657 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12658 if (rc) {
12659 BNX2X_ERR("Can't load firmware file %s\n",
12660 fw_file_name);
12661 goto request_firmware_exit;
12662 }
eb2afd4a 12663
c0ea452e
MS		 12664 rc = bnx2x_check_firmware(bp);
12665 if (rc) {
12666 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12667 goto request_firmware_exit;
94a78b79
VZ		 12668 }
12669
12670 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12671
12672 /* Initialize the pointers to the init arrays */
12673 /* Blob */
12674 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12675
12676 /* Opcodes */
12677 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12678
12679 /* Offsets */
ab6ad5a4
EG		 12680 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12681 be16_to_cpu_n);
94a78b79
VZ		 12682
12683 /* STORMs firmware */
573f2035
EG		 12684 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12685 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12686 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12687 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12688 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12689 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12690 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12691 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12692 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12693 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12694 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12695 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12696 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12697 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12698 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12699 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 12700 /* IRO */
12701 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 12702
12703 return 0;
ab6ad5a4 12704
523224a3
DK		 12705iro_alloc_err:
12706 kfree(bp->init_ops_offsets);
94a78b79
VZ		 12707init_offsets_alloc_err:
12708 kfree(bp->init_ops);
12709init_ops_alloc_err:
12710 kfree(bp->init_data);
12711request_firmware_exit:
12712 release_firmware(bp->firmware);
127d0a19 12713 bp->firmware = NULL;
94a78b79
VZ		 12714
12715 return rc;
12716}
12717
619c5cb6
VZ		 12718static void bnx2x_release_firmware(struct bnx2x *bp)
12719{
12720 kfree(bp->init_ops_offsets);
12721 kfree(bp->init_ops);
12722 kfree(bp->init_data);
12723 release_firmware(bp->firmware);
eb2afd4a 12724 bp->firmware = NULL;
619c5cb6
VZ		 12725}
12726
619c5cb6
VZ		 12727static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12728 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12729 .init_hw_cmn = bnx2x_init_hw_common,
12730 .init_hw_port = bnx2x_init_hw_port,
12731 .init_hw_func = bnx2x_init_hw_func,
12732
12733 .reset_hw_cmn = bnx2x_reset_common,
12734 .reset_hw_port = bnx2x_reset_port,
12735 .reset_hw_func = bnx2x_reset_func,
12736
12737 .gunzip_init = bnx2x_gunzip_init,
12738 .gunzip_end = bnx2x_gunzip_end,
12739
12740 .init_fw = bnx2x_init_firmware,
12741 .release_fw = bnx2x_release_firmware,
12742};
12743
12744void bnx2x__init_func_obj(struct bnx2x *bp)
12745{
12746 /* Prepare DMAE related driver resources */
12747 bnx2x_setup_dmae(bp);
12748
12749 bnx2x_init_func_obj(bp, &bp->func_obj,
12750 bnx2x_sp(bp, func_rdata),
12751 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 12752 bnx2x_sp(bp, func_afex_rdata),
12753 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 12754 &bnx2x_func_sp_drv);
12755}
12756
12757/* must be called after sriov-enable */
1191cb83 12758static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 12759{
37ae41a9 12760 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 12761
290ca2bb
AE		 12762 if (IS_SRIOV(bp))
12763 cid_count += BNX2X_VF_CIDS;
12764
55c11941
MS		 12765 if (CNIC_SUPPORT(bp))
12766 cid_count += CNIC_CID_MAX;
290ca2bb 12767
523224a3
DK		 12768 return roundup(cid_count, QM_CID_ROUND);
12769}
f85582f8 12770
619c5cb6 12771/**
6383c0b3 12772 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 12773 *
12774 * @dev: pci device
12775 *
12776 */
60cad4e6 12777static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 12778{
ae2104be 12779 int index;
1ab4434c 12780 u16 control = 0;
619c5cb6 12781
6383c0b3
AE		 12782 /*
12783 * If MSI-X is not supported - return number of SBs needed to support
12784 * one fast path queue: one FP queue + SB for CNIC
12785 */
ae2104be 12786 if (!pdev->msix_cap) {
1ab4434c 12787 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 12788 return 1 + cnic_cnt;
1ab4434c
AE		 12789 }
12790 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 12791
6383c0b3
AE		 12792 /*
12793 * The value in the PCI configuration space is the index of the last
12794 * entry, namely one less than the actual size of the table, which is
12795 * exactly what we want to return from this function: number of all SBs
12796 * without the default SB.
1ab4434c 12797 * For VFs there is no default SB, then we return (index+1).
6383c0b3 12798 */
ae2104be 12799 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
619c5cb6 12800
1ab4434c 12801 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 12802
60cad4e6 12803 return index;
1ab4434c 12804}
523224a3 12805
1ab4434c
AE		 12806static int set_max_cos_est(int chip_id)
12807{
12808 switch (chip_id) {
f2e0899f
DK		 12809 case BCM57710:
12810 case BCM57711:
12811 case BCM57711E:
1ab4434c 12812 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 12813 case BCM57712:
619c5cb6 12814 case BCM57712_MF:
1ab4434c 12815 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 12816 case BCM57800:
12817 case BCM57800_MF:
12818 case BCM57810:
12819 case BCM57810_MF:
c3def943
YM		 12820 case BCM57840_4_10:
12821 case BCM57840_2_20:
1ab4434c 12822 case BCM57840_O:
c3def943 12823 case BCM57840_MFO:
619c5cb6 12824 case BCM57840_MF:
7e8e02df
BW		 12825 case BCM57811:
12826 case BCM57811_MF:
1ab4434c 12827 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 12828 case BCM57712_VF:
12829 case BCM57800_VF:
12830 case BCM57810_VF:
12831 case BCM57840_VF:
12832 case BCM57811_VF:
1ab4434c 12833 return 1;
f2e0899f 12834 default:
1ab4434c 12835 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 12836 return -ENODEV;
f2e0899f 12837 }
1ab4434c 12838}
f2e0899f 12839
1ab4434c
AE		 12840static int set_is_vf(int chip_id)
12841{
12842 switch (chip_id) {
12843 case BCM57712_VF:
12844 case BCM57800_VF:
12845 case BCM57810_VF:
12846 case BCM57840_VF:
12847 case BCM57811_VF:
12848 return true;
12849 default:
12850 return false;
12851 }
12852}
6383c0b3 12853
1ab4434c
AE		 12854static int bnx2x_init_one(struct pci_dev *pdev,
12855 const struct pci_device_id *ent)
12856{
12857 struct net_device *dev = NULL;
12858 struct bnx2x *bp;
b91e1a1a
YM		 12859 enum pcie_link_width pcie_width;
12860 enum pci_bus_speed pcie_speed;
1ab4434c
AE		 12861 int rc, max_non_def_sbs;
12862 int rx_count, tx_count, rss_count, doorbell_size;
12863 int max_cos_est;
12864 bool is_vf;
12865 int cnic_cnt;
12866
12867 /* An estimated maximum supported CoS number according to the chip
12868 * version.
12869 * We will try to roughly estimate the maximum number of CoSes this chip
12870 * may support in order to minimize the memory allocated for Tx
12871 * netdev_queue's. This number will be accurately calculated during the
12872 * initialization of bp->max_cos based on the chip versions AND chip
12873 * revision in the bnx2x_init_bp().
12874 */
12875 max_cos_est = set_max_cos_est(ent->driver_data);
12876 if (max_cos_est < 0)
12877 return max_cos_est;
12878 is_vf = set_is_vf(ent->driver_data);
12879 cnic_cnt = is_vf ? 0 : 1;
12880
60cad4e6
AE		 12881 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12882
12883 /* add another SB for VF as it has no default SB */
12884 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 12885
12886 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 12887 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 12888
12889 if (rss_count < 1)
12890 return -EINVAL;
6383c0b3
AE		 12891
12892 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 12893 rx_count = rss_count + cnic_cnt;
6383c0b3 12894
1ab4434c 12895 /* Maximum number of netdev Tx queues:
37ae41a9 12896 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 12897 */
55c11941 12898 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 12899
a2fbb9ea 12900 /* dev zeroed in init_etherdev */
6383c0b3 12901 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 12902 if (!dev)
a2fbb9ea
ET		 12903 return -ENOMEM;
12904
a2fbb9ea 12905 bp = netdev_priv(dev);
a2fbb9ea 12906
1ab4434c
AE		 12907 bp->flags = 0;
12908 if (is_vf)
12909 bp->flags |= IS_VF_FLAG;
12910
6383c0b3 12911 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 12912 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 12913 bp->msg_enable = debug;
55c11941 12914 bp->cnic_support = cnic_cnt;
4bd9b0ff 12915 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 12916
6383c0b3 12917 pci_set_drvdata(pdev, dev);
523224a3 12918
1ab4434c 12919 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 12920 if (rc < 0) {
12921 free_netdev(dev);
12922 return rc;
12923 }
12924
1ab4434c
AE		 12925 BNX2X_DEV_INFO("This is a %s function\n",
12926 IS_PF(bp) ? "physical" : "virtual");
55c11941 12927 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 12928 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 12929 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 12930 tx_count, rx_count);
60aa0509 12931
34f80b04 12932 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 12933 if (rc)
12934 goto init_one_exit;
12935
1ab4434c
AE		 12936 /* Map doorbells here as we need the real value of bp->max_cos which
12937 * is initialized in bnx2x_init_bp() to determine the number of
12938 * l2 connections.
6383c0b3 12939 */
1ab4434c 12940 if (IS_VF(bp)) {
1d6f3cd8 12941 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 12942 rc = bnx2x_vf_pci_alloc(bp);
12943 if (rc)
12944 goto init_one_exit;
1ab4434c
AE		 12945 } else {
12946 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12947 if (doorbell_size > pci_resource_len(pdev, 2)) {
12948 dev_err(&bp->pdev->dev,
12949 "Cannot map doorbells, bar size too small, aborting\n");
12950 rc = -ENOMEM;
12951 goto init_one_exit;
12952 }
12953 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12954 doorbell_size);
37ae41a9 12955 }
6383c0b3
AE		 12956 if (!bp->doorbells) {
12957 dev_err(&bp->pdev->dev,
12958 "Cannot map doorbell space, aborting\n");
12959 rc = -ENOMEM;
12960 goto init_one_exit;
12961 }
12962
be1f1ffa
AE		 12963 if (IS_VF(bp)) {
12964 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12965 if (rc)
12966 goto init_one_exit;
12967 }
12968
3c76feff
AE		 12969 /* Enable SRIOV if capability found in configuration space */
12970 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb
AE		 12971 if (rc)
12972 goto init_one_exit;
12973
523224a3 12974 /* calc qm_cid_count */
6383c0b3 12975 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 12976 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 12977
55c11941 12978 /* disable FCOE L2 queue for E1x*/
62ac0dc9 12979 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 12980 bp->flags |= NO_FCOE_FLAG;
12981
0e8d2ec5
MS		 12982 /* Set bp->num_queues for MSI-X mode*/
12983 bnx2x_set_num_queues(bp);
12984
25985edc 12985 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 12986 * needed.
d6214d7a 12987 */
1ab4434c
AE		 12988 rc = bnx2x_set_int_mode(bp);
12989 if (rc) {
12990 dev_err(&pdev->dev, "Cannot set interrupts\n");
12991 goto init_one_exit;
12992 }
04c46736 12993 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 12994
1ab4434c 12995 /* register the net device */
b340007f
VZ		 12996 rc = register_netdev(dev);
12997 if (rc) {
12998 dev_err(&pdev->dev, "Cannot register net device\n");
12999 goto init_one_exit;
13000 }
1ab4434c 13001 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 13002
ec6ba945
VZ		 13003 if (!NO_FCOE(bp)) {
13004 /* Add storage MAC address */
13005 rtnl_lock();
13006 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13007 rtnl_unlock();
13008 }
b91e1a1a
YM		 13009 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13010 pcie_speed == PCI_SPEED_UNKNOWN ||
13011 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13012 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13013 else
13014 BNX2X_DEV_INFO(
13015 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
ca1ee4b2
DK		 13016 board_info[ent->driver_data].name,
13017 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13018 pcie_width,
b91e1a1a
YM		 13019 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13020 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13021 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
ca1ee4b2
DK		 13022 "Unknown",
13023 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 13024
a2fbb9ea 13025 return 0;
34f80b04
EG		 13026
13027init_one_exit:
33d8e6a5
YM		 13028 bnx2x_disable_pcie_error_reporting(bp);
13029
34f80b04
EG		 13030 if (bp->regview)
13031 iounmap(bp->regview);
13032
1ab4434c 13033 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 13034 iounmap(bp->doorbells);
13035
13036 free_netdev(dev);
13037
13038 if (atomic_read(&pdev->enable_cnt) == 1)
13039 pci_release_regions(pdev);
13040
13041 pci_disable_device(pdev);
34f80b04
EG		 13042
13043 return rc;
a2fbb9ea
ET		 13044}
13045
b030ed2f
YM		 13046static void __bnx2x_remove(struct pci_dev *pdev,
13047 struct net_device *dev,
13048 struct bnx2x *bp,
13049 bool remove_netdev)
a2fbb9ea 13050{
ec6ba945
VZ		 13051 /* Delete storage MAC address */
13052 if (!NO_FCOE(bp)) {
13053 rtnl_lock();
13054 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13055 rtnl_unlock();
13056 }
ec6ba945 13057
98507672
SR		 13058#ifdef BCM_DCBNL
13059 /* Delete app tlvs from dcbnl */
13060 bnx2x_dcbnl_update_applist(bp, true);
13061#endif
13062
a6d3a5ba
BW		 13063 if (IS_PF(bp) &&
13064 !BP_NOMCP(bp) &&
13065 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13066 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13067
b030ed2f
YM		 13068 /* Close the interface - either directly or implicitly */
13069 if (remove_netdev) {
13070 unregister_netdev(dev);
13071 } else {
13072 rtnl_lock();
6ef5a92c 13073 dev_close(dev);
b030ed2f
YM		 13074 rtnl_unlock();
13075 }
a2fbb9ea 13076
78c3bcc5
AE		 13077 bnx2x_iov_remove_one(bp);
13078
084d6cbb 13079 /* Power on: we can't let PCI layer write to us while we are in D3 */
1ab4434c
AE		 13080 if (IS_PF(bp))
13081 bnx2x_set_power_state(bp, PCI_D0);
084d6cbb 13082
d6214d7a
DK		 13083 /* Disable MSI/MSI-X */
13084 bnx2x_disable_msi(bp);
f85582f8 13085
084d6cbb 13086 /* Power off */
1ab4434c
AE		 13087 if (IS_PF(bp))
13088 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 13089
72fd0718 13090 /* Make sure RESET task is not scheduled before continuing */
7be08a72 13091 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 13092
4513f925
AE		 13093 /* send message via vfpf channel to release the resources of this vf */
13094 if (IS_VF(bp))
13095 bnx2x_vfpf_release(bp);
72fd0718 13096
b030ed2f
YM		 13097 /* Assumes no further PCIe PM changes will occur */
13098 if (system_state == SYSTEM_POWER_OFF) {
13099 pci_wake_from_d3(pdev, bp->wol);
13100 pci_set_power_state(pdev, PCI_D3hot);
13101 }
13102
33d8e6a5 13103 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 13104 if (remove_netdev) {
13105 if (bp->regview)
13106 iounmap(bp->regview);
33d8e6a5 13107
d9aee591
YM		 13108 /* For vfs, doorbells are part of the regview and were unmapped
13109 * along with it. FW is only loaded by PF.
13110 */
13111 if (IS_PF(bp)) {
13112 if (bp->doorbells)
13113 iounmap(bp->doorbells);
eb2afd4a 13114
d9aee591
YM		 13115 bnx2x_release_firmware(bp);
13116 }
13117 bnx2x_free_mem_bp(bp);
523224a3 13118
b030ed2f 13119 free_netdev(dev);
34f80b04 13120
d9aee591
YM		 13121 if (atomic_read(&pdev->enable_cnt) == 1)
13122 pci_release_regions(pdev);
34f80b04 13123
5f6db130
YM		 13124 pci_disable_device(pdev);
13125 }
a2fbb9ea
ET		 13126}
13127
b030ed2f
YM		 13128static void bnx2x_remove_one(struct pci_dev *pdev)
13129{
13130 struct net_device *dev = pci_get_drvdata(pdev);
13131 struct bnx2x *bp;
13132
13133 if (!dev) {
13134 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13135 return;
13136 }
13137 bp = netdev_priv(dev);
13138
13139 __bnx2x_remove(pdev, dev, bp, true);
13140}
13141
f8ef6e44
YG		 13142static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13143{
7fa6f340 13144 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 13145
13146 bp->rx_mode = BNX2X_RX_MODE_NONE;
13147
55c11941
MS		 13148 if (CNIC_LOADED(bp))
13149 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13150
619c5cb6
VZ		 13151 /* Stop Tx */
13152 bnx2x_tx_disable(bp);
26614ba5
MS		 13153 /* Delete all NAPI objects */
13154 bnx2x_del_all_napi(bp);
55c11941
MS		 13155 if (CNIC_LOADED(bp))
13156 bnx2x_del_all_napi_cnic(bp);
7fa6f340 13157 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 13158
13159 del_timer_sync(&bp->timer);
7fa6f340
YM		 13160 cancel_delayed_work(&bp->sp_task);
13161 cancel_delayed_work(&bp->period_task);
619c5cb6 13162
7fa6f340
YM		 13163 spin_lock_bh(&bp->stats_lock);
13164 bp->stats_state = STATS_STATE_DISABLED;
13165 spin_unlock_bh(&bp->stats_lock);
f8ef6e44 13166
7fa6f340 13167 bnx2x_save_statistics(bp);
f8ef6e44 13168
619c5cb6
VZ		 13169 netif_carrier_off(bp->dev);
13170
f8ef6e44
YG		 13171 return 0;
13172}
13173
493adb1f
WX		 13174/**
13175 * bnx2x_io_error_detected - called when PCI error is detected
13176 * @pdev: Pointer to PCI device
13177 * @state: The current pci connection state
13178 *
13179 * This function is called after a PCI bus error affecting
13180 * this device has been detected.
13181 */
13182static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13183 pci_channel_state_t state)
13184{
13185 struct net_device *dev = pci_get_drvdata(pdev);
13186 struct bnx2x *bp = netdev_priv(dev);
13187
13188 rtnl_lock();
13189
7fa6f340
YM		 13190 BNX2X_ERR("IO error detected\n");
13191
493adb1f
WX		 13192 netif_device_detach(dev);
13193
07ce50e4
DN		 13194 if (state == pci_channel_io_perm_failure) {
13195 rtnl_unlock();
13196 return PCI_ERS_RESULT_DISCONNECT;
13197 }
13198
493adb1f 13199 if (netif_running(dev))
f8ef6e44 13200 bnx2x_eeh_nic_unload(bp);
493adb1f 13201
7fa6f340
YM		 13202 bnx2x_prev_path_mark_eeh(bp);
13203
493adb1f
WX		 13204 pci_disable_device(pdev);
13205
13206 rtnl_unlock();
13207
13208 /* Request a slot reset */
13209 return PCI_ERS_RESULT_NEED_RESET;
13210}
13211
13212/**
13213 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13214 * @pdev: Pointer to PCI device
13215 *
13216 * Restart the card from scratch, as if from a cold-boot.
13217 */
13218static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13219{
13220 struct net_device *dev = pci_get_drvdata(pdev);
13221 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 13222 int i;
493adb1f
WX		 13223
13224 rtnl_lock();
7fa6f340 13225 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 13226 if (pci_enable_device(pdev)) {
13227 dev_err(&pdev->dev,
13228 "Cannot re-enable PCI device after reset\n");
13229 rtnl_unlock();
13230 return PCI_ERS_RESULT_DISCONNECT;
13231 }
13232
13233 pci_set_master(pdev);
13234 pci_restore_state(pdev);
70632d0a 13235 pci_save_state(pdev);
493adb1f
WX		 13236
13237 if (netif_running(dev))
13238 bnx2x_set_power_state(bp, PCI_D0);
13239
7fa6f340
YM		 13240 if (netif_running(dev)) {
13241 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 13242
13243 /* MCP should have been reset; Need to wait for validity */
13244 bnx2x_init_shmem(bp);
13245
7fa6f340
YM		 13246 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13247 u32 v;
13248
13249 v = SHMEM2_RD(bp,
13250 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13251 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13252 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13253 }
13254 bnx2x_drain_tx_queues(bp);
13255 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13256 bnx2x_netif_stop(bp, 1);
13257 bnx2x_free_irq(bp);
13258
13259 /* Report UNLOAD_DONE to MCP */
13260 bnx2x_send_unload_done(bp, true);
13261
13262 bp->sp_state = 0;
13263 bp->port.pmf = 0;
13264
13265 bnx2x_prev_unload(bp);
13266
16a5fd92 13267 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 13268 * assume the FW will no longer write to the bnx2x driver.
13269 */
13270 bnx2x_squeeze_objects(bp);
13271 bnx2x_free_skbs(bp);
13272 for_each_rx_queue(bp, i)
13273 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13274 bnx2x_free_fp_mem(bp);
13275 bnx2x_free_mem(bp);
13276
13277 bp->state = BNX2X_STATE_CLOSED;
13278 }
13279
493adb1f
WX		 13280 rtnl_unlock();
13281
33d8e6a5
YM		 13282 /* If AER, perform cleanup of the PCIe registers */
13283 if (bp->flags & AER_ENABLED) {
13284 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13285 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13286 else
13287 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13288 }
13289
493adb1f
WX		 13290 return PCI_ERS_RESULT_RECOVERED;
13291}
13292
13293/**
13294 * bnx2x_io_resume - called when traffic can start flowing again
13295 * @pdev: Pointer to PCI device
13296 *
13297 * This callback is called when the error recovery driver tells us that
13298 * its OK to resume normal operation.
13299 */
13300static void bnx2x_io_resume(struct pci_dev *pdev)
13301{
13302 struct net_device *dev = pci_get_drvdata(pdev);
13303 struct bnx2x *bp = netdev_priv(dev);
13304
72fd0718 13305 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 13306 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 13307 return;
13308 }
13309
493adb1f
WX		 13310 rtnl_lock();
13311
7fa6f340
YM		 13312 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13313 DRV_MSG_SEQ_NUMBER_MASK;
13314
493adb1f 13315 if (netif_running(dev))
f8ef6e44 13316 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 13317
13318 netif_device_attach(dev);
13319
13320 rtnl_unlock();
13321}
13322
3646f0e5 13323static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 13324 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 13325 .slot_reset = bnx2x_io_slot_reset,
13326 .resume = bnx2x_io_resume,
493adb1f
WX		 13327};
13328
b030ed2f
YM		 13329static void bnx2x_shutdown(struct pci_dev *pdev)
13330{
13331 struct net_device *dev = pci_get_drvdata(pdev);
13332 struct bnx2x *bp;
13333
13334 if (!dev)
13335 return;
13336
13337 bp = netdev_priv(dev);
13338 if (!bp)
13339 return;
13340
13341 rtnl_lock();
13342 netif_device_detach(dev);
13343 rtnl_unlock();
13344
13345 /* Don't remove the netdevice, as there are scenarios which will cause
13346 * the kernel to hang, e.g., when trying to remove bnx2i while the
13347 * rootfs is mounted from SAN.
13348 */
13349 __bnx2x_remove(pdev, dev, bp, false);
13350}
13351
a2fbb9ea 13352static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 13353 .name = DRV_MODULE_NAME,
13354 .id_table = bnx2x_pci_tbl,
13355 .probe = bnx2x_init_one,
0329aba1 13356 .remove = bnx2x_remove_one,
493adb1f
WX		 13357 .suspend = bnx2x_suspend,
13358 .resume = bnx2x_resume,
13359 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 13360#ifdef CONFIG_BNX2X_SRIOV
13361 .sriov_configure = bnx2x_sriov_configure,
13362#endif
b030ed2f 13363 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 13364};
13365
13366static int __init bnx2x_init(void)
13367{
dd21ca6d
SG		 13368 int ret;
13369
7995c64e 13370 pr_info("%s", version);
938cf541 13371
1cf167f2
EG		 13372 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13373 if (bnx2x_wq == NULL) {
7995c64e 13374 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 13375 return -ENOMEM;
13376 }
13377
dd21ca6d
SG		 13378 ret = pci_register_driver(&bnx2x_pci_driver);
13379 if (ret) {
7995c64e 13380 pr_err("Cannot register driver\n");
dd21ca6d
SG		 13381 destroy_workqueue(bnx2x_wq);
13382 }
13383 return ret;
a2fbb9ea
ET		 13384}
13385
13386static void __exit bnx2x_cleanup(void)
13387{
452427b0 13388 struct list_head *pos, *q;
d76a6111 13389
a2fbb9ea 13390 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 13391
13392 destroy_workqueue(bnx2x_wq);
452427b0 13393
16a5fd92 13394 /* Free globally allocated resources */
452427b0
YM		 13395 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13396 struct bnx2x_prev_path_list *tmp =
13397 list_entry(pos, struct bnx2x_prev_path_list, list);
13398 list_del(pos);
13399 kfree(tmp);
13400 }
a2fbb9ea
ET		 13401}
13402
3deb8167
YR		 13403void bnx2x_notify_link_changed(struct bnx2x *bp)
13404{
13405 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13406}
13407
a2fbb9ea
ET		 13408module_init(bnx2x_init);
13409module_exit(bnx2x_cleanup);
13410
619c5cb6
VZ		 13411/**
13412 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13413 *
13414 * @bp: driver handle
13415 * @set: set or clear the CAM entry
13416 *
16a5fd92 13417 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 13418 * Return 0 if success, -ENODEV if ramrod doesn't return.
13419 */
1191cb83 13420static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 13421{
13422 unsigned long ramrod_flags = 0;
13423
13424 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13425 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13426 &bp->iscsi_l2_mac_obj, true,
13427 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13428}
993ac7b5
MC		 13429
13430/* count denotes the number of new completions we have seen */
13431static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13432{
13433 struct eth_spe *spe;
a052997e 13434 int cxt_index, cxt_offset;
993ac7b5
MC		 13435
13436#ifdef BNX2X_STOP_ON_ERROR
13437 if (unlikely(bp->panic))
13438 return;
13439#endif
13440
13441 spin_lock_bh(&bp->spq_lock);
c2bff63f 13442 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 13443 bp->cnic_spq_pending -= count;
13444
c2bff63f
DK		 13445 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13446 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13447 & SPE_HDR_CONN_TYPE) >>
13448 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 13449 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13450 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 13451
13452 /* Set validation for iSCSI L2 client before sending SETUP
13453 * ramrod
13454 */
13455 if (type == ETH_CONNECTION_TYPE) {
a052997e 13456 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 13457 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 13458 ILT_PAGE_CIDS;
37ae41a9 13459 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 13460 (cxt_index * ILT_PAGE_CIDS);
13461 bnx2x_set_ctx_validation(bp,
13462 &bp->context[cxt_index].
13463 vcxt[cxt_offset].eth,
37ae41a9 13464 BNX2X_ISCSI_ETH_CID(bp));
a052997e 13465 }
c2bff63f
DK		 13466 }
13467
619c5cb6
VZ		 13468 /*
13469 * There may be not more than 8 L2, not more than 8 L5 SPEs
13470 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 13471 * COMMON ramrods is not more than the EQ and SPQ can
13472 * accommodate.
c2bff63f 13473 */
6e30dd4e
VZ		 13474 if (type == ETH_CONNECTION_TYPE) {
13475 if (!atomic_read(&bp->cq_spq_left))
13476 break;
13477 else
13478 atomic_dec(&bp->cq_spq_left);
13479 } else if (type == NONE_CONNECTION_TYPE) {
13480 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 13481 break;
13482 else
6e30dd4e 13483 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 13484 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13485 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 13486 if (bp->cnic_spq_pending >=
13487 bp->cnic_eth_dev.max_kwqe_pending)
13488 break;
13489 else
13490 bp->cnic_spq_pending++;
13491 } else {
13492 BNX2X_ERR("Unknown SPE type: %d\n", type);
13493 bnx2x_panic();
993ac7b5 13494 break;
c2bff63f 13495 }
993ac7b5
MC		 13496
13497 spe = bnx2x_sp_get_next(bp);
13498 *spe = *bp->cnic_kwq_cons;
13499
51c1a580 13500 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 13501 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13502
13503 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13504 bp->cnic_kwq_cons = bp->cnic_kwq;
13505 else
13506 bp->cnic_kwq_cons++;
13507 }
13508 bnx2x_sp_prod_update(bp);
13509 spin_unlock_bh(&bp->spq_lock);
13510}
13511
13512static int bnx2x_cnic_sp_queue(struct net_device *dev,
13513 struct kwqe_16 *kwqes[], u32 count)
13514{
13515 struct bnx2x *bp = netdev_priv(dev);
13516 int i;
13517
13518#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 13519 if (unlikely(bp->panic)) {
13520 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 13521 return -EIO;
51c1a580 13522 }
993ac7b5
MC		 13523#endif
13524
95c6c616
AE		 13525 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13526 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 13527 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 13528 return -EAGAIN;
13529 }
13530
993ac7b5
MC		 13531 spin_lock_bh(&bp->spq_lock);
13532
13533 for (i = 0; i < count; i++) {
13534 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13535
13536 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13537 break;
13538
13539 *bp->cnic_kwq_prod = *spe;
13540
13541 bp->cnic_kwq_pending++;
13542
51c1a580 13543 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 13544 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 13545 spe->data.update_data_addr.hi,
13546 spe->data.update_data_addr.lo,
993ac7b5
MC		 13547 bp->cnic_kwq_pending);
13548
13549 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13550 bp->cnic_kwq_prod = bp->cnic_kwq;
13551 else
13552 bp->cnic_kwq_prod++;
13553 }
13554
13555 spin_unlock_bh(&bp->spq_lock);
13556
13557 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13558 bnx2x_cnic_sp_post(bp, 0);
13559
13560 return i;
13561}
13562
13563static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13564{
13565 struct cnic_ops *c_ops;
13566 int rc = 0;
13567
13568 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 13569 c_ops = rcu_dereference_protected(bp->cnic_ops,
13570 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 13571 if (c_ops)
13572 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13573 mutex_unlock(&bp->cnic_mutex);
13574
13575 return rc;
13576}
13577
13578static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13579{
13580 struct cnic_ops *c_ops;
13581 int rc = 0;
13582
13583 rcu_read_lock();
13584 c_ops = rcu_dereference(bp->cnic_ops);
13585 if (c_ops)
13586 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13587 rcu_read_unlock();
13588
13589 return rc;
13590}
13591
13592/*
13593 * for commands that have no data
13594 */
9f6c9258 13595int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 13596{
13597 struct cnic_ctl_info ctl = {0};
13598
13599 ctl.cmd = cmd;
13600
13601 return bnx2x_cnic_ctl_send(bp, &ctl);
13602}
13603
619c5cb6 13604static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 13605{
619c5cb6 13606 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 13607
13608 /* first we tell CNIC and only then we count this as a completion */
13609 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13610 ctl.data.comp.cid = cid;
619c5cb6 13611 ctl.data.comp.error = err;
993ac7b5
MC		 13612
13613 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 13614 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 13615}
13616
619c5cb6
VZ		 13617/* Called with netif_addr_lock_bh() taken.
13618 * Sets an rx_mode config for an iSCSI ETH client.
13619 * Doesn't block.
13620 * Completion should be checked outside.
13621 */
13622static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13623{
13624 unsigned long accept_flags = 0, ramrod_flags = 0;
13625 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13626 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13627
13628 if (start) {
13629 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13630 * because it's the only way for UIO Queue to accept
13631 * multicasts (in non-promiscuous mode only one Queue per
13632 * function will receive multicast packets (leading in our
13633 * case).
13634 */
13635 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13636 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13637 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13638 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13639
13640 /* Clear STOP_PENDING bit if START is requested */
13641 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13642
13643 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13644 } else
13645 /* Clear START_PENDING bit if STOP is requested */
13646 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13647
13648 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13649 set_bit(sched_state, &bp->sp_state);
13650 else {
13651 __set_bit(RAMROD_RX, &ramrod_flags);
13652 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13653 ramrod_flags);
13654 }
13655}
13656
993ac7b5
MC		 13657static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13658{
13659 struct bnx2x *bp = netdev_priv(dev);
13660 int rc = 0;
13661
13662 switch (ctl->cmd) {
13663 case DRV_CTL_CTXTBL_WR_CMD: {
13664 u32 index = ctl->data.io.offset;
13665 dma_addr_t addr = ctl->data.io.dma_addr;
13666
13667 bnx2x_ilt_wr(bp, index, addr);
13668 break;
13669 }
13670
c2bff63f
DK		 13671 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13672 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 13673
13674 bnx2x_cnic_sp_post(bp, count);
13675 break;
13676 }
13677
13678 /* rtnl_lock is held. */
13679 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 13680 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13681 unsigned long sp_bits = 0;
13682
13683 /* Configure the iSCSI classification object */
13684 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13685 cp->iscsi_l2_client_id,
13686 cp->iscsi_l2_cid, BP_FUNC(bp),
13687 bnx2x_sp(bp, mac_rdata),
13688 bnx2x_sp_mapping(bp, mac_rdata),
13689 BNX2X_FILTER_MAC_PENDING,
13690 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13691 &bp->macs_pool);
ec6ba945 13692
523224a3 13693 /* Set iSCSI MAC address */
619c5cb6
VZ		 13694 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13695 if (rc)
13696 break;
523224a3
DK		 13697
13698 mmiowb();
13699 barrier();
13700
619c5cb6
VZ		 13701 /* Start accepting on iSCSI L2 ring */
13702
13703 netif_addr_lock_bh(dev);
13704 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13705 netif_addr_unlock_bh(dev);
13706
13707 /* bits to wait on */
13708 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13709 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13710
13711 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13712 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 13713
993ac7b5
MC		 13714 break;
13715 }
13716
13717 /* rtnl_lock is held. */
13718 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 13719 unsigned long sp_bits = 0;
993ac7b5 13720
523224a3 13721 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 13722 netif_addr_lock_bh(dev);
13723 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13724 netif_addr_unlock_bh(dev);
13725
13726 /* bits to wait on */
13727 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13728 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13729
13730 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13731 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 13732
13733 mmiowb();
13734 barrier();
13735
13736 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 13737 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13738 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 13739 break;
13740 }
c2bff63f
DK		 13741 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13742 int count = ctl->data.credit.credit_count;
13743
13744 smp_mb__before_atomic_inc();
6e30dd4e 13745 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 13746 smp_mb__after_atomic_inc();
13747 break;
13748 }
1d187b34 13749 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 13750 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 13751
13752 if (CHIP_IS_E3(bp)) {
13753 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 13754 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13755 int path = BP_PATH(bp);
13756 int port = BP_PORT(bp);
13757 int i;
13758 u32 scratch_offset;
13759 u32 *host_addr;
1d187b34 13760
2e499d3c 13761 /* first write capability to shmem2 */
1d187b34
BW		 13762 if (ulp_type == CNIC_ULP_ISCSI)
13763 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13764 else if (ulp_type == CNIC_ULP_FCOE)
13765 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13766 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 13767
13768 if ((ulp_type != CNIC_ULP_FCOE) ||
13769 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13770 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13771 break;
13772
13773 /* if reached here - should write fcoe capabilities */
13774 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13775 if (!scratch_offset)
13776 break;
13777 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13778 fcoe_features[path][port]);
13779 host_addr = (u32 *) &(ctl->data.register_data.
13780 fcoe_features);
13781 for (i = 0; i < sizeof(struct fcoe_capabilities);
13782 i += 4)
13783 REG_WR(bp, scratch_offset + i,
13784 *(host_addr + i/4));
1d187b34
BW		 13785 }
13786 break;
13787 }
2e499d3c 13788
1d187b34
BW		 13789 case DRV_CTL_ULP_UNREGISTER_CMD: {
13790 int ulp_type = ctl->data.ulp_type;
13791
13792 if (CHIP_IS_E3(bp)) {
13793 int idx = BP_FW_MB_IDX(bp);
13794 u32 cap;
13795
13796 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13797 if (ulp_type == CNIC_ULP_ISCSI)
13798 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13799 else if (ulp_type == CNIC_ULP_FCOE)
13800 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13801 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13802 }
13803 break;
13804 }
993ac7b5
MC		 13805
13806 default:
13807 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13808 rc = -EINVAL;
13809 }
13810
13811 return rc;
13812}
13813
9f6c9258 13814void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 13815{
13816 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13817
13818 if (bp->flags & USING_MSIX_FLAG) {
13819 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13820 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13821 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13822 } else {
13823 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13824 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13825 }
619c5cb6 13826 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 13827 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13828 else
13829 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13830
619c5cb6
VZ		 13831 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13832 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 13833 cp->irq_arr[1].status_blk = bp->def_status_blk;
13834 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 13835 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 13836
13837 cp->num_irq = 2;
13838}
13839
37ae41a9
MS		 13840void bnx2x_setup_cnic_info(struct bnx2x *bp)
13841{
13842 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13843
37ae41a9
MS		 13844 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13845 bnx2x_cid_ilt_lines(bp);
13846 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13847 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13848 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13849
f78afb35
MC		 13850 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
13851 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
13852 cp->iscsi_l2_cid);
13853
37ae41a9
MS		 13854 if (NO_ISCSI_OOO(bp))
13855 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13856}
13857
993ac7b5
MC		 13858static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13859 void *data)
13860{
13861 struct bnx2x *bp = netdev_priv(dev);
13862 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 13863 int rc;
13864
13865 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 13866
51c1a580
MS		 13867 if (ops == NULL) {
13868 BNX2X_ERR("NULL ops received\n");
993ac7b5 13869 return -EINVAL;
51c1a580 13870 }
993ac7b5 13871
55c11941
MS		 13872 if (!CNIC_SUPPORT(bp)) {
13873 BNX2X_ERR("Can't register CNIC when not supported\n");
13874 return -EOPNOTSUPP;
13875 }
13876
13877 if (!CNIC_LOADED(bp)) {
13878 rc = bnx2x_load_cnic(bp);
13879 if (rc) {
13880 BNX2X_ERR("CNIC-related load failed\n");
13881 return rc;
13882 }
55c11941
MS		 13883 }
13884
13885 bp->cnic_enabled = true;
13886
993ac7b5
MC		 13887 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13888 if (!bp->cnic_kwq)
13889 return -ENOMEM;
13890
13891 bp->cnic_kwq_cons = bp->cnic_kwq;
13892 bp->cnic_kwq_prod = bp->cnic_kwq;
13893 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13894
13895 bp->cnic_spq_pending = 0;
13896 bp->cnic_kwq_pending = 0;
13897
13898 bp->cnic_data = data;
13899
13900 cp->num_irq = 0;
619c5cb6 13901 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 13902 cp->iro_arr = bp->iro_arr;
993ac7b5 13903
993ac7b5 13904 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 13905
993ac7b5
MC		 13906 rcu_assign_pointer(bp->cnic_ops, ops);
13907
13908 return 0;
13909}
13910
13911static int bnx2x_unregister_cnic(struct net_device *dev)
13912{
13913 struct bnx2x *bp = netdev_priv(dev);
13914 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13915
13916 mutex_lock(&bp->cnic_mutex);
993ac7b5 13917 cp->drv_state = 0;
2cfa5a04 13918 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 13919 mutex_unlock(&bp->cnic_mutex);
13920 synchronize_rcu();
fea75645 13921 bp->cnic_enabled = false;
993ac7b5
MC		 13922 kfree(bp->cnic_kwq);
13923 bp->cnic_kwq = NULL;
13924
13925 return 0;
13926}
13927
a8f47eb7 13928static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 13929{
13930 struct bnx2x *bp = netdev_priv(dev);
13931 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13932
2ba45142
VZ		 13933 /* If both iSCSI and FCoE are disabled - return NULL in
13934 * order to indicate CNIC that it should not try to work
13935 * with this device.
13936 */
13937 if (NO_ISCSI(bp) && NO_FCOE(bp))
13938 return NULL;
13939
993ac7b5
MC		 13940 cp->drv_owner = THIS_MODULE;
13941 cp->chip_id = CHIP_ID(bp);
13942 cp->pdev = bp->pdev;
13943 cp->io_base = bp->regview;
13944 cp->io_base2 = bp->doorbells;
13945 cp->max_kwqe_pending = 8;
523224a3 13946 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 13947 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13948 bnx2x_cid_ilt_lines(bp);
993ac7b5 13949 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 13950 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 13951 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13952 cp->drv_ctl = bnx2x_drv_ctl;
13953 cp->drv_register_cnic = bnx2x_register_cnic;
13954 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 13955 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 13956 cp->iscsi_l2_client_id =
13957 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 13958 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 13959
2ba45142
VZ		 13960 if (NO_ISCSI_OOO(bp))
13961 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13962
13963 if (NO_ISCSI(bp))
13964 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13965
13966 if (NO_FCOE(bp))
13967 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13968
51c1a580
MS		 13969 BNX2X_DEV_INFO(
13970 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 13971 cp->ctx_blk_size,
13972 cp->ctx_tbl_offset,
13973 cp->ctx_tbl_len,
13974 cp->starting_cid);
993ac7b5
MC		 13975 return cp;
13976}
993ac7b5 13977
a8f47eb7 13978static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 13979{
6411280a
AE		 13980 struct bnx2x *bp = fp->bp;
13981 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 13982
6411280a
AE		 13983 if (IS_VF(bp))
13984 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13985 else if (!CHIP_IS_E1x(bp))
13986 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13987 else
13988 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 13989
6411280a 13990 return offset;
8d9ac297 13991}
381ac16b 13992
6411280a
AE		 13993/* called only on E1H or E2.
13994 * When pretending to be PF, the pretend value is the function number 0...7
13995 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13996 * combination
13997 */
13998int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 13999{
6411280a 14000 u32 pretend_reg;
381ac16b 14001
23826850 14002 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 14003 return -1;
381ac16b 14004
6411280a
AE		 14005 /* get my own pretend register */
14006 pretend_reg = bnx2x_get_pretend_reg(bp);
14007 REG_WR(bp, pretend_reg, pretend_func_val);
14008 REG_RD(bp, pretend_reg);
381ac16b
AE		 14009 return 0;
14010}
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