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bnx2x: Recovery flow bug fixes
[thirdparty/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/dma-mapping.h>
35#include <linux/bitops.h>
36#include <linux/irq.h>
37#include <linux/delay.h>
38#include <asm/byteorder.h>
39#include <linux/time.h>
40#include <linux/ethtool.h>
41#include <linux/mii.h>
01789349 42#include <linux/if.h>
0c6671b0 43#include <linux/if_vlan.h>
a2fbb9ea 44#include <net/ip.h>
619c5cb6 45#include <net/ipv6.h>
a2fbb9ea
ET		 46#include <net/tcp.h>
47#include <net/checksum.h>
34f80b04 48#include <net/ip6_checksum.h>
a2fbb9ea
ET		 49#include <linux/workqueue.h>
50#include <linux/crc32.h>
34f80b04 51#include <linux/crc32c.h>
a2fbb9ea
ET		 52#include <linux/prefetch.h>
53#include <linux/zlib.h>
a2fbb9ea 54#include <linux/io.h>
45229b42 55#include <linux/stringify.h>
7ab24bfd 56#include <linux/vmalloc.h>
a2fbb9ea 57
a2fbb9ea
ET		 58#include "bnx2x.h"
59#include "bnx2x_init.h"
94a78b79 60#include "bnx2x_init_ops.h"
9f6c9258 61#include "bnx2x_cmn.h"
e4901dde 62#include "bnx2x_dcb.h"
042181f5 63#include "bnx2x_sp.h"
a2fbb9ea 64
94a78b79
VZ		 65#include <linux/firmware.h>
66#include "bnx2x_fw_file_hdr.h"
67/* FW files */
45229b42
BH		 68#define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 76
34f80b04
EG		 77/* Time in jiffies before concluding the transmitter is hung */
78#define TX_TIMEOUT (5*HZ)
a2fbb9ea 79
53a10565 80static char version[] __devinitdata =
619c5cb6 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
83
24e3fcef 84MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 85MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
a2fbb9ea
ET		 89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 91MODULE_FIRMWARE(FW_FILE_NAME_E1);
92MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 93MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 94
555f6c78
EG		 95static int multi_mode = 1;
96module_param(multi_mode, int, 0);
ca00392c
EG		 97MODULE_PARM_DESC(multi_mode, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
99
d6214d7a 100int num_queues;
54b9ddaa
VZ		 101module_param(num_queues, int, 0);
102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
555f6c78 104
19680c48 105static int disable_tpa;
19680c48 106module_param(disable_tpa, int, 0);
9898f86d 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 108
9ee3d37b
DK		 109#define INT_MODE_INTx 1
110#define INT_MODE_MSI 2
8badd27a
EG		 111static int int_mode;
112module_param(int_mode, int, 0);
619c5cb6 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 114 "(1 INT#x; 2 MSI)");
8badd27a 115
a18f5128
EG		 116static int dropless_fc;
117module_param(dropless_fc, int, 0);
118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
9898f86d 120static int poll;
a2fbb9ea 121module_param(poll, int, 0);
9898f86d 122MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 123
124static int mrrs = -1;
125module_param(mrrs, int, 0);
126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
127
9898f86d 128static int debug;
a2fbb9ea 129module_param(debug, int, 0);
9898f86d
EG		 130MODULE_PARM_DESC(debug, " Default debug msglevel");
131
a2fbb9ea 132
619c5cb6
VZ		 133
134struct workqueue_struct *bnx2x_wq;
ec6ba945 135
a2fbb9ea
ET		 136enum bnx2x_board_type {
137 BCM57710 = 0,
619c5cb6
VZ		 138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
142 BCM57800,
143 BCM57800_MF,
144 BCM57810,
145 BCM57810_MF,
146 BCM57840,
147 BCM57840_MF
a2fbb9ea
ET		 148};
149
34f80b04 150/* indexed by board_type, above */
53a10565 151static struct {
a2fbb9ea
ET		 152 char *name;
153} board_info[] __devinitdata = {
619c5cb6
VZ		 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
165 "Ethernet Multi Function"}
a2fbb9ea
ET		 166};
167
619c5cb6
VZ		 168#ifndef PCI_DEVICE_ID_NX2_57710
169#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
170#endif
171#ifndef PCI_DEVICE_ID_NX2_57711
172#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
173#endif
174#ifndef PCI_DEVICE_ID_NX2_57711E
175#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
176#endif
177#ifndef PCI_DEVICE_ID_NX2_57712
178#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
179#endif
180#ifndef PCI_DEVICE_ID_NX2_57712_MF
181#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
182#endif
183#ifndef PCI_DEVICE_ID_NX2_57800
184#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
185#endif
186#ifndef PCI_DEVICE_ID_NX2_57800_MF
187#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
188#endif
189#ifndef PCI_DEVICE_ID_NX2_57810
190#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
191#endif
192#ifndef PCI_DEVICE_ID_NX2_57810_MF
193#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
194#endif
195#ifndef PCI_DEVICE_ID_NX2_57840
196#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
197#endif
198#ifndef PCI_DEVICE_ID_NX2_57840_MF
199#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
200#endif
a3aa1884 201static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
a2fbb9ea
ET		 213 { 0 }
214};
215
216MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
217
218/****************************************************************************
219* General service functions
220****************************************************************************/
221
619c5cb6
VZ		 222static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
223 u32 addr, dma_addr_t mapping)
224{
225 REG_WR(bp, addr, U64_LO(mapping));
226 REG_WR(bp, addr + 4, U64_HI(mapping));
227}
228
229static inline void storm_memset_spq_addr(struct bnx2x *bp,
230 dma_addr_t mapping, u16 abs_fid)
231{
232 u32 addr = XSEM_REG_FAST_MEMORY +
233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
234
235 __storm_memset_dma_mapping(bp, addr, mapping);
236}
237
238static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
239 u16 pf_id)
523224a3 240{
619c5cb6
VZ		 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id);
243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id);
245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
246 pf_id);
247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
248 pf_id);
523224a3
DK		 249}
250
619c5cb6
VZ		 251static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
252 u8 enable)
253{
254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable);
256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
257 enable);
258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
259 enable);
260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
261 enable);
262}
523224a3
DK		 263
264static inline void storm_memset_eq_data(struct bnx2x *bp,
265 struct event_ring_data *eq_data,
266 u16 pfid)
267{
268 size_t size = sizeof(struct event_ring_data);
269
270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
271
272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
273}
274
275static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
276 u16 pfid)
277{
278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
279 REG_WR16(bp, addr, eq_prod);
280}
281
a2fbb9ea
ET		 282/* used only at init
283 * locking is done by mcp
284 */
8d96286a 285static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 286{
287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
290 PCICFG_VENDOR_ID_OFFSET);
291}
292
a2fbb9ea
ET		 293static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
294{
295 u32 val;
296
297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
300 PCICFG_VENDOR_ID_OFFSET);
301
302 return val;
303}
a2fbb9ea 304
f2e0899f
DK		 305#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
306#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
307#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
308#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
309#define DMAE_DP_DST_NONE "dst_addr [none]"
310
8d96286a 311static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
312 int msglvl)
f2e0899f
DK		 313{
314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
315
316 switch (dmae->opcode & DMAE_COMMAND_DST) {
317 case DMAE_CMD_DST_PCI:
318 if (src_type == DMAE_CMD_SRC_PCI)
319 DP(msglvl, "DMAE: opcode 0x%08x\n"
320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
321 "comp_addr [%x:%08x], comp_val 0x%08x\n",
322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
324 dmae->comp_addr_hi, dmae->comp_addr_lo,
325 dmae->comp_val);
326 else
327 DP(msglvl, "DMAE: opcode 0x%08x\n"
328 "src [%08x], len [%d*4], dst [%x:%08x]\n"
329 "comp_addr [%x:%08x], comp_val 0x%08x\n",
330 dmae->opcode, dmae->src_addr_lo >> 2,
331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
332 dmae->comp_addr_hi, dmae->comp_addr_lo,
333 dmae->comp_val);
334 break;
335 case DMAE_CMD_DST_GRC:
336 if (src_type == DMAE_CMD_SRC_PCI)
337 DP(msglvl, "DMAE: opcode 0x%08x\n"
338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
339 "comp_addr [%x:%08x], comp_val 0x%08x\n",
340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
341 dmae->len, dmae->dst_addr_lo >> 2,
342 dmae->comp_addr_hi, dmae->comp_addr_lo,
343 dmae->comp_val);
344 else
345 DP(msglvl, "DMAE: opcode 0x%08x\n"
346 "src [%08x], len [%d*4], dst [%08x]\n"
347 "comp_addr [%x:%08x], comp_val 0x%08x\n",
348 dmae->opcode, dmae->src_addr_lo >> 2,
349 dmae->len, dmae->dst_addr_lo >> 2,
350 dmae->comp_addr_hi, dmae->comp_addr_lo,
351 dmae->comp_val);
352 break;
353 default:
354 if (src_type == DMAE_CMD_SRC_PCI)
355 DP(msglvl, "DMAE: opcode 0x%08x\n"
f1deab50
JP		 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
357 "comp_addr [%x:%08x] comp_val 0x%08x\n",
f2e0899f
DK		 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
360 dmae->comp_val);
361 else
362 DP(msglvl, "DMAE: opcode 0x%08x\n"
f1deab50
JP		 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
364 "comp_addr [%x:%08x] comp_val 0x%08x\n",
f2e0899f
DK		 365 dmae->opcode, dmae->src_addr_lo >> 2,
366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
367 dmae->comp_val);
368 break;
369 }
370
371}
372
a2fbb9ea 373/* copy command into DMAE command memory and set DMAE command go */
6c719d00 374void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 375{
376 u32 cmd_offset;
377 int i;
378
379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
382
ad8d3948
EG		 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 385 }
386 REG_WR(bp, dmae_reg_go_c[idx], 1);
387}
388
f2e0899f 389u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 390{
f2e0899f
DK		 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
392 DMAE_CMD_C_ENABLE);
393}
ad8d3948 394
f2e0899f
DK		 395u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
396{
397 return opcode & ~DMAE_CMD_SRC_RESET;
398}
ad8d3948 399
f2e0899f
DK		 400u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
401 bool with_comp, u8 comp_type)
402{
403 u32 opcode = 0;
404
405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
406 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 407
f2e0899f
DK		 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
409
410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 414
a2fbb9ea 415#ifdef __BIG_ENDIAN
f2e0899f 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 417#else
f2e0899f 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 419#endif
f2e0899f
DK		 420 if (with_comp)
421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
422 return opcode;
423}
424
8d96286a 425static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
426 struct dmae_command *dmae,
427 u8 src_type, u8 dst_type)
f2e0899f
DK		 428{
429 memset(dmae, 0, sizeof(struct dmae_command));
430
431 /* set the opcode */
432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
433 true, DMAE_COMP_PCI);
434
435 /* fill in the completion parameters */
436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
438 dmae->comp_val = DMAE_COMP_VAL;
439}
440
441/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 442static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
443 struct dmae_command *dmae)
f2e0899f
DK		 444{
445 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 447 int rc = 0;
448
449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 452
619c5cb6
VZ		 453 /*
454 * Lock the dmae channel. Disable BHs to prevent a dead-lock
455 * as long as this code is called both from syscall context and
456 * from ndo_set_rx_mode() flow that may be called from BH.
457 */
6e30dd4e 458 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 459
f2e0899f 460 /* reset completion */
a2fbb9ea
ET		 461 *wb_comp = 0;
462
f2e0899f
DK		 463 /* post the command on the channel used for initializations */
464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 465
f2e0899f 466 /* wait for completion */
a2fbb9ea 467 udelay(5);
f2e0899f 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
470
95c6c616
AE		 471 if (!cnt ||
472 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
473 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 474 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 475 rc = DMAE_TIMEOUT;
476 goto unlock;
a2fbb9ea 477 }
ad8d3948 478 cnt--;
f2e0899f 479 udelay(50);
a2fbb9ea 480 }
f2e0899f
DK		 481 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
482 BNX2X_ERR("DMAE PCI error!\n");
483 rc = DMAE_PCI_ERROR;
484 }
485
486 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
487 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
488 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 489
f2e0899f 490unlock:
6e30dd4e 491 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 492 return rc;
493}
494
495void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
496 u32 len32)
497{
498 struct dmae_command dmae;
499
500 if (!bp->dmae_ready) {
501 u32 *data = bnx2x_sp(bp, wb_data[0]);
502
127a425e
AE		 503 DP(BNX2X_MSG_OFF,
504 "DMAE is not ready (dst_addr %08x len32 %d) using indirect\n",
505 dst_addr, len32);
506 if (CHIP_IS_E1(bp))
507 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
508 else
509 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 510 return;
511 }
512
513 /* set opcode and fixed command fields */
514 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
515
516 /* fill in addresses and len */
517 dmae.src_addr_lo = U64_LO(dma_addr);
518 dmae.src_addr_hi = U64_HI(dma_addr);
519 dmae.dst_addr_lo = dst_addr >> 2;
520 dmae.dst_addr_hi = 0;
521 dmae.len = len32;
522
523 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
524
525 /* issue the command and wait for completion */
526 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 527}
528
c18487ee 529void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 530{
5ff7b6d4 531 struct dmae_command dmae;
ad8d3948
EG		 532
533 if (!bp->dmae_ready) {
534 u32 *data = bnx2x_sp(bp, wb_data[0]);
535 int i;
536
127a425e
AE		 537 if (CHIP_IS_E1(bp)) {
538 DP(BNX2X_MSG_OFF,
539 "DMAE is not ready (src_addr %08x len32 %d) using indirect\n",
540 src_addr, len32);
541 for (i = 0; i < len32; i++)
542 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
543 } else
544 for (i = 0; i < len32; i++)
545 data[i] = REG_RD(bp, src_addr + i*4);
546
ad8d3948
EG		 547 return;
548 }
549
f2e0899f
DK		 550 /* set opcode and fixed command fields */
551 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 552
f2e0899f 553 /* fill in addresses and len */
5ff7b6d4
EG		 554 dmae.src_addr_lo = src_addr >> 2;
555 dmae.src_addr_hi = 0;
556 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
557 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
558 dmae.len = len32;
ad8d3948 559
f2e0899f 560 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 561
f2e0899f
DK		 562 /* issue the command and wait for completion */
563 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 564}
565
8d96286a 566static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
567 u32 addr, u32 len)
573f2035 568{
02e3c6cb 569 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 570 int offset = 0;
571
02e3c6cb 572 while (len > dmae_wr_max) {
573f2035 573 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 574 addr + offset, dmae_wr_max);
575 offset += dmae_wr_max * 4;
576 len -= dmae_wr_max;
573f2035
EG		 577 }
578
579 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
580}
581
ad8d3948
EG		 582/* used only for slowpath so not inlined */
583static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
584{
585 u32 wb_write[2];
586
587 wb_write[0] = val_hi;
588 wb_write[1] = val_lo;
589 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 590}
a2fbb9ea 591
ad8d3948
EG		 592#ifdef USE_WB_RD
593static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
594{
595 u32 wb_data[2];
596
597 REG_RD_DMAE(bp, reg, wb_data, 2);
598
599 return HILO_U64(wb_data[0], wb_data[1]);
600}
601#endif
602
a2fbb9ea
ET		 603static int bnx2x_mc_assert(struct bnx2x *bp)
604{
a2fbb9ea 605 char last_idx;
34f80b04
EG		 606 int i, rc = 0;
607 u32 row0, row1, row2, row3;
608
609 /* XSTORM */
610 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
611 XSTORM_ASSERT_LIST_INDEX_OFFSET);
612 if (last_idx)
613 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
614
615 /* print the asserts */
616 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
617
618 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
619 XSTORM_ASSERT_LIST_OFFSET(i));
620 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
621 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
622 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
623 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
624 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
625 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
626
627 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
628 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
629 " 0x%08x 0x%08x 0x%08x\n",
630 i, row3, row2, row1, row0);
631 rc++;
632 } else {
633 break;
634 }
635 }
636
637 /* TSTORM */
638 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_INDEX_OFFSET);
640 if (last_idx)
641 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
642
643 /* print the asserts */
644 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
645
646 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
647 TSTORM_ASSERT_LIST_OFFSET(i));
648 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
649 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
650 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
651 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
652 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
653 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
654
655 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
656 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
657 " 0x%08x 0x%08x 0x%08x\n",
658 i, row3, row2, row1, row0);
659 rc++;
660 } else {
661 break;
662 }
663 }
664
665 /* CSTORM */
666 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
667 CSTORM_ASSERT_LIST_INDEX_OFFSET);
668 if (last_idx)
669 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
670
671 /* print the asserts */
672 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
673
674 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
675 CSTORM_ASSERT_LIST_OFFSET(i));
676 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
677 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
678 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
679 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
680 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
681 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
682
683 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
684 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
685 " 0x%08x 0x%08x 0x%08x\n",
686 i, row3, row2, row1, row0);
687 rc++;
688 } else {
689 break;
690 }
691 }
692
693 /* USTORM */
694 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_INDEX_OFFSET);
696 if (last_idx)
697 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
698
699 /* print the asserts */
700 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
701
702 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
703 USTORM_ASSERT_LIST_OFFSET(i));
704 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
705 USTORM_ASSERT_LIST_OFFSET(i) + 4);
706 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
707 USTORM_ASSERT_LIST_OFFSET(i) + 8);
708 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
709 USTORM_ASSERT_LIST_OFFSET(i) + 12);
710
711 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
712 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
713 " 0x%08x 0x%08x 0x%08x\n",
714 i, row3, row2, row1, row0);
715 rc++;
716 } else {
717 break;
a2fbb9ea
ET		 718 }
719 }
34f80b04 720
a2fbb9ea
ET		 721 return rc;
722}
c14423fe 723
7a25cc73 724void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 725{
7a25cc73 726 u32 addr, val;
a2fbb9ea 727 u32 mark, offset;
4781bfad 728 __be32 data[9];
a2fbb9ea 729 int word;
f2e0899f 730 u32 trace_shmem_base;
2145a920
VZ		 731 if (BP_NOMCP(bp)) {
732 BNX2X_ERR("NO MCP - can not dump\n");
733 return;
734 }
7a25cc73
DK		 735 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
736 (bp->common.bc_ver & 0xff0000) >> 16,
737 (bp->common.bc_ver & 0xff00) >> 8,
738 (bp->common.bc_ver & 0xff));
739
740 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
741 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
742 printk("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 743
f2e0899f
DK		 744 if (BP_PATH(bp) == 0)
745 trace_shmem_base = bp->common.shmem_base;
746 else
747 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
748 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 749 mark = REG_RD(bp, addr);
f2e0899f
DK		 750 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
751 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 752 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 753
7a25cc73 754 printk("%s", lvl);
f2e0899f 755 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 756 for (word = 0; word < 8; word++)
cdaa7cb8 757 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 758 data[8] = 0x0;
7995c64e 759 pr_cont("%s", (char *)data);
a2fbb9ea 760 }
cdaa7cb8 761 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 762 for (word = 0; word < 8; word++)
cdaa7cb8 763 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 764 data[8] = 0x0;
7995c64e 765 pr_cont("%s", (char *)data);
a2fbb9ea 766 }
7a25cc73
DK		 767 printk("%s" "end of fw dump\n", lvl);
768}
769
770static inline void bnx2x_fw_dump(struct bnx2x *bp)
771{
772 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 773}
774
6c719d00 775void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 776{
777 int i;
523224a3
DK		 778 u16 j;
779 struct hc_sp_status_block_data sp_sb_data;
780 int func = BP_FUNC(bp);
781#ifdef BNX2X_STOP_ON_ERROR
782 u16 start = 0, end = 0;
6383c0b3 783 u8 cos;
523224a3 784#endif
a2fbb9ea 785
66e855f3
YG		 786 bp->stats_state = STATS_STATE_DISABLED;
787 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
788
a2fbb9ea
ET		 789 BNX2X_ERR("begin crash dump -----------------\n");
790
8440d2b6
EG		 791 /* Indices */
792 /* Common */
523224a3 793 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
619c5cb6
VZ		 794 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
795 bp->def_idx, bp->def_att_idx, bp->attn_state,
796 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 797 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
798 bp->def_status_blk->atten_status_block.attn_bits,
799 bp->def_status_blk->atten_status_block.attn_bits_ack,
800 bp->def_status_blk->atten_status_block.status_block_id,
801 bp->def_status_blk->atten_status_block.attn_bits_index);
802 BNX2X_ERR(" def (");
803 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
804 pr_cont("0x%x%s",
f1deab50
JP		 805 bp->def_status_blk->sp_sb.index_values[i],
806 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
523224a3
DK		 807
808 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
809 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
810 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
811 i*sizeof(u32));
812
f1deab50 813 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
523224a3
DK		 814 sp_sb_data.igu_sb_id,
815 sp_sb_data.igu_seg_id,
816 sp_sb_data.p_func.pf_id,
817 sp_sb_data.p_func.vnic_id,
818 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 819 sp_sb_data.p_func.vf_valid,
820 sp_sb_data.state);
523224a3 821
8440d2b6 822
ec6ba945 823 for_each_eth_queue(bp, i) {
a2fbb9ea 824 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 825 int loop;
f2e0899f 826 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 827 struct hc_status_block_data_e1x sb_data_e1x;
828 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 829 CHIP_IS_E1x(bp) ?
830 sb_data_e1x.common.state_machine :
831 sb_data_e2.common.state_machine;
523224a3 832 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 833 CHIP_IS_E1x(bp) ?
834 sb_data_e1x.index_data :
835 sb_data_e2.index_data;
6383c0b3 836 u8 data_size, cos;
523224a3 837 u32 *sb_data_p;
6383c0b3 838 struct bnx2x_fp_txdata txdata;
523224a3
DK		 839
840 /* Rx */
cdaa7cb8 841 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 842 " rx_comp_prod(0x%x)"
cdaa7cb8 843 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 844 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 845 fp->rx_comp_prod,
66e855f3 846 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 847 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 848 " fp_hc_idx(0x%x)\n",
8440d2b6 849 fp->rx_sge_prod, fp->last_max_sge,
523224a3 850 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 851
523224a3 852 /* Tx */
6383c0b3
AE		 853 for_each_cos_in_tx_queue(fp, cos)
854 {
855 txdata = fp->txdata[cos];
856 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
857 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
858 " *tx_cons_sb(0x%x)\n",
859 i, txdata.tx_pkt_prod,
860 txdata.tx_pkt_cons, txdata.tx_bd_prod,
861 txdata.tx_bd_cons,
862 le16_to_cpu(*txdata.tx_cons_sb));
863 }
523224a3 864
619c5cb6
VZ		 865 loop = CHIP_IS_E1x(bp) ?
866 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 867
868 /* host sb data */
869
ec6ba945
VZ		 870#ifdef BCM_CNIC
871 if (IS_FCOE_FP(fp))
872 continue;
873#endif
523224a3
DK		 874 BNX2X_ERR(" run indexes (");
875 for (j = 0; j < HC_SB_MAX_SM; j++)
876 pr_cont("0x%x%s",
877 fp->sb_running_index[j],
878 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
879
880 BNX2X_ERR(" indexes (");
881 for (j = 0; j < loop; j++)
882 pr_cont("0x%x%s",
883 fp->sb_index_values[j],
884 (j == loop - 1) ? ")" : " ");
885 /* fw sb data */
619c5cb6
VZ		 886 data_size = CHIP_IS_E1x(bp) ?
887 sizeof(struct hc_status_block_data_e1x) :
888 sizeof(struct hc_status_block_data_e2);
523224a3 889 data_size /= sizeof(u32);
619c5cb6
VZ		 890 sb_data_p = CHIP_IS_E1x(bp) ?
891 (u32 *)&sb_data_e1x :
892 (u32 *)&sb_data_e2;
523224a3
DK		 893 /* copy sb data in here */
894 for (j = 0; j < data_size; j++)
895 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
896 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
897 j * sizeof(u32));
898
619c5cb6
VZ		 899 if (!CHIP_IS_E1x(bp)) {
900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
902 "state(0x%x)\n",
f2e0899f
DK		 903 sb_data_e2.common.p_func.pf_id,
904 sb_data_e2.common.p_func.vf_id,
905 sb_data_e2.common.p_func.vf_valid,
906 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 907 sb_data_e2.common.same_igu_sb_1b,
908 sb_data_e2.common.state);
f2e0899f 909 } else {
619c5cb6
VZ		 910 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
911 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
912 "state(0x%x)\n",
f2e0899f
DK		 913 sb_data_e1x.common.p_func.pf_id,
914 sb_data_e1x.common.p_func.vf_id,
915 sb_data_e1x.common.p_func.vf_valid,
916 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 917 sb_data_e1x.common.same_igu_sb_1b,
918 sb_data_e1x.common.state);
f2e0899f 919 }
523224a3
DK		 920
921 /* SB_SMs data */
922 for (j = 0; j < HC_SB_MAX_SM; j++) {
923 pr_cont("SM[%d] __flags (0x%x) "
924 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
925 "time_to_expire (0x%x) "
926 "timer_value(0x%x)\n", j,
927 hc_sm_p[j].__flags,
928 hc_sm_p[j].igu_sb_id,
929 hc_sm_p[j].igu_seg_id,
930 hc_sm_p[j].time_to_expire,
931 hc_sm_p[j].timer_value);
932 }
933
934 /* Indecies data */
935 for (j = 0; j < loop; j++) {
936 pr_cont("INDEX[%d] flags (0x%x) "
937 "timeout (0x%x)\n", j,
938 hc_index_p[j].flags,
939 hc_index_p[j].timeout);
940 }
8440d2b6 941 }
a2fbb9ea 942
523224a3 943#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 944 /* Rings */
945 /* Rx */
ec6ba945 946 for_each_rx_queue(bp, i) {
8440d2b6 947 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 948
949 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
950 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 951 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 952 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
953 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
954
c3eefaf6 955 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 956 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 957 }
958
3196a88a
EG		 959 start = RX_SGE(fp->rx_sge_prod);
960 end = RX_SGE(fp->last_max_sge);
8440d2b6 961 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 962 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
963 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
964
c3eefaf6
EG		 965 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
966 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 967 }
968
a2fbb9ea
ET		 969 start = RCQ_BD(fp->rx_comp_cons - 10);
970 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 971 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 972 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
973
c3eefaf6
EG		 974 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
975 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 976 }
977 }
978
8440d2b6 979 /* Tx */
ec6ba945 980 for_each_tx_queue(bp, i) {
8440d2b6 981 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3
AE		 982 for_each_cos_in_tx_queue(fp, cos) {
983 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
984
985 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
986 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
987 for (j = start; j != end; j = TX_BD(j + 1)) {
988 struct sw_tx_bd *sw_bd =
989 &txdata->tx_buf_ring[j];
990
991 BNX2X_ERR("fp%d: txdata %d, "
992 "packet[%x]=[%p,%x]\n",
993 i, cos, j, sw_bd->skb,
994 sw_bd->first_bd);
995 }
8440d2b6 996
6383c0b3
AE		 997 start = TX_BD(txdata->tx_bd_cons - 10);
998 end = TX_BD(txdata->tx_bd_cons + 254);
999 for (j = start; j != end; j = TX_BD(j + 1)) {
1000 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1001
6383c0b3
AE		 1002 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
1003 "[%x:%x:%x:%x]\n",
1004 i, cos, j, tx_bd[0], tx_bd[1],
1005 tx_bd[2], tx_bd[3]);
1006 }
8440d2b6
EG		 1007 }
1008 }
523224a3 1009#endif
34f80b04 1010 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 1011 bnx2x_mc_assert(bp);
1012 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1013}
1014
619c5cb6
VZ		 1015/*
1016 * FLR Support for E2
1017 *
1018 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1019 * initialization.
1020 */
1021#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
89db4ad8
AE		 1022#define FLR_WAIT_INTERVAL 50 /* usec */
1023#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1024
1025struct pbf_pN_buf_regs {
1026 int pN;
1027 u32 init_crd;
1028 u32 crd;
1029 u32 crd_freed;
1030};
1031
1032struct pbf_pN_cmd_regs {
1033 int pN;
1034 u32 lines_occup;
1035 u32 lines_freed;
1036};
1037
1038static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1039 struct pbf_pN_buf_regs *regs,
1040 u32 poll_count)
1041{
1042 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1043 u32 cur_cnt = poll_count;
1044
1045 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1046 crd = crd_start = REG_RD(bp, regs->crd);
1047 init_crd = REG_RD(bp, regs->init_crd);
1048
1049 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1050 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1051 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1052
1053 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1054 (init_crd - crd_start))) {
1055 if (cur_cnt--) {
89db4ad8 1056 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1057 crd = REG_RD(bp, regs->crd);
1058 crd_freed = REG_RD(bp, regs->crd_freed);
1059 } else {
1060 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1061 regs->pN);
1062 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1063 regs->pN, crd);
1064 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1065 regs->pN, crd_freed);
1066 break;
1067 }
1068 }
1069 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1070 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1071}
1072
1073static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1074 struct pbf_pN_cmd_regs *regs,
1075 u32 poll_count)
1076{
1077 u32 occup, to_free, freed, freed_start;
1078 u32 cur_cnt = poll_count;
1079
1080 occup = to_free = REG_RD(bp, regs->lines_occup);
1081 freed = freed_start = REG_RD(bp, regs->lines_freed);
1082
1083 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1084 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1085
1086 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1087 if (cur_cnt--) {
89db4ad8 1088 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1089 occup = REG_RD(bp, regs->lines_occup);
1090 freed = REG_RD(bp, regs->lines_freed);
1091 } else {
1092 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1093 regs->pN);
1094 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1095 regs->pN, occup);
1096 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1097 regs->pN, freed);
1098 break;
1099 }
1100 }
1101 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1102 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1103}
1104
1105static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1106 u32 expected, u32 poll_count)
1107{
1108 u32 cur_cnt = poll_count;
1109 u32 val;
1110
1111 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1112 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1113
1114 return val;
1115}
1116
1117static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1118 char *msg, u32 poll_cnt)
1119{
1120 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1121 if (val != 0) {
1122 BNX2X_ERR("%s usage count=%d\n", msg, val);
1123 return 1;
1124 }
1125 return 0;
1126}
1127
1128static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1129{
1130 /* adjust polling timeout */
1131 if (CHIP_REV_IS_EMUL(bp))
1132 return FLR_POLL_CNT * 2000;
1133
1134 if (CHIP_REV_IS_FPGA(bp))
1135 return FLR_POLL_CNT * 120;
1136
1137 return FLR_POLL_CNT;
1138}
1139
1140static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1141{
1142 struct pbf_pN_cmd_regs cmd_regs[] = {
1143 {0, (CHIP_IS_E3B0(bp)) ?
1144 PBF_REG_TQ_OCCUPANCY_Q0 :
1145 PBF_REG_P0_TQ_OCCUPANCY,
1146 (CHIP_IS_E3B0(bp)) ?
1147 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1148 PBF_REG_P0_TQ_LINES_FREED_CNT},
1149 {1, (CHIP_IS_E3B0(bp)) ?
1150 PBF_REG_TQ_OCCUPANCY_Q1 :
1151 PBF_REG_P1_TQ_OCCUPANCY,
1152 (CHIP_IS_E3B0(bp)) ?
1153 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1154 PBF_REG_P1_TQ_LINES_FREED_CNT},
1155 {4, (CHIP_IS_E3B0(bp)) ?
1156 PBF_REG_TQ_OCCUPANCY_LB_Q :
1157 PBF_REG_P4_TQ_OCCUPANCY,
1158 (CHIP_IS_E3B0(bp)) ?
1159 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1160 PBF_REG_P4_TQ_LINES_FREED_CNT}
1161 };
1162
1163 struct pbf_pN_buf_regs buf_regs[] = {
1164 {0, (CHIP_IS_E3B0(bp)) ?
1165 PBF_REG_INIT_CRD_Q0 :
1166 PBF_REG_P0_INIT_CRD ,
1167 (CHIP_IS_E3B0(bp)) ?
1168 PBF_REG_CREDIT_Q0 :
1169 PBF_REG_P0_CREDIT,
1170 (CHIP_IS_E3B0(bp)) ?
1171 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1172 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1173 {1, (CHIP_IS_E3B0(bp)) ?
1174 PBF_REG_INIT_CRD_Q1 :
1175 PBF_REG_P1_INIT_CRD,
1176 (CHIP_IS_E3B0(bp)) ?
1177 PBF_REG_CREDIT_Q1 :
1178 PBF_REG_P1_CREDIT,
1179 (CHIP_IS_E3B0(bp)) ?
1180 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1181 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1182 {4, (CHIP_IS_E3B0(bp)) ?
1183 PBF_REG_INIT_CRD_LB_Q :
1184 PBF_REG_P4_INIT_CRD,
1185 (CHIP_IS_E3B0(bp)) ?
1186 PBF_REG_CREDIT_LB_Q :
1187 PBF_REG_P4_CREDIT,
1188 (CHIP_IS_E3B0(bp)) ?
1189 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1190 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1191 };
1192
1193 int i;
1194
1195 /* Verify the command queues are flushed P0, P1, P4 */
1196 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1197 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1198
1199
1200 /* Verify the transmission buffers are flushed P0, P1, P4 */
1201 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1202 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1203}
1204
1205#define OP_GEN_PARAM(param) \
1206 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1207
1208#define OP_GEN_TYPE(type) \
1209 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1210
1211#define OP_GEN_AGG_VECT(index) \
1212 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1213
1214
1215static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1216 u32 poll_cnt)
1217{
1218 struct sdm_op_gen op_gen = {0};
1219
1220 u32 comp_addr = BAR_CSTRORM_INTMEM +
1221 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1222 int ret = 0;
1223
1224 if (REG_RD(bp, comp_addr)) {
89db4ad8 1225 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1226 return 1;
1227 }
1228
1229 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1230 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1231 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1232 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1233
89db4ad8 1234 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
619c5cb6
VZ		 1235 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1236
1237 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1238 BNX2X_ERR("FW final cleanup did not succeed\n");
1239 ret = 1;
1240 }
1241 /* Zero completion for nxt FLR */
1242 REG_WR(bp, comp_addr, 0);
1243
1244 return ret;
1245}
1246
1247static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1248{
1249 int pos;
1250 u16 status;
1251
77c98e6a 1252 pos = pci_pcie_cap(dev);
619c5cb6
VZ		 1253 if (!pos)
1254 return false;
1255
1256 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1257 return status & PCI_EXP_DEVSTA_TRPND;
1258}
1259
1260/* PF FLR specific routines
1261*/
1262static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1263{
1264
1265 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1266 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1267 CFC_REG_NUM_LCIDS_INSIDE_PF,
1268 "CFC PF usage counter timed out",
1269 poll_cnt))
1270 return 1;
1271
1272
1273 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1274 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1275 DORQ_REG_PF_USAGE_CNT,
1276 "DQ PF usage counter timed out",
1277 poll_cnt))
1278 return 1;
1279
1280 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1281 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1282 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1283 "QM PF usage counter timed out",
1284 poll_cnt))
1285 return 1;
1286
1287 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1288 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1289 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1290 "Timers VNIC usage counter timed out",
1291 poll_cnt))
1292 return 1;
1293 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1294 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1295 "Timers NUM_SCANS usage counter timed out",
1296 poll_cnt))
1297 return 1;
1298
1299 /* Wait DMAE PF usage counter to zero */
1300 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1301 dmae_reg_go_c[INIT_DMAE_C(bp)],
1302 "DMAE dommand register timed out",
1303 poll_cnt))
1304 return 1;
1305
1306 return 0;
1307}
1308
1309static void bnx2x_hw_enable_status(struct bnx2x *bp)
1310{
1311 u32 val;
1312
1313 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1314 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1315
1316 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1317 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1318
1319 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1320 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1321
1322 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1323 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1324
1325 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1326 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1327
1328 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1329 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1330
1331 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1332 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1333
1334 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1335 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1336 val);
1337}
1338
1339static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1340{
1341 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1342
1343 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1344
1345 /* Re-enable PF target read access */
1346 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1347
1348 /* Poll HW usage counters */
89db4ad8 1349 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1350 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1351 return -EBUSY;
1352
1353 /* Zero the igu 'trailing edge' and 'leading edge' */
1354
1355 /* Send the FW cleanup command */
1356 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1357 return -EBUSY;
1358
1359 /* ATC cleanup */
1360
1361 /* Verify TX hw is flushed */
1362 bnx2x_tx_hw_flushed(bp, poll_cnt);
1363
1364 /* Wait 100ms (not adjusted according to platform) */
1365 msleep(100);
1366
1367 /* Verify no pending pci transactions */
1368 if (bnx2x_is_pcie_pending(bp->pdev))
1369 BNX2X_ERR("PCIE Transactions still pending\n");
1370
1371 /* Debug */
1372 bnx2x_hw_enable_status(bp);
1373
1374 /*
1375 * Master enable - Due to WB DMAE writes performed before this
1376 * register is re-initialized as part of the regular function init
1377 */
1378 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1379
1380 return 0;
1381}
1382
f2e0899f 1383static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1384{
34f80b04 1385 int port = BP_PORT(bp);
a2fbb9ea
ET		 1386 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1387 u32 val = REG_RD(bp, addr);
1388 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1389 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1390
1391 if (msix) {
8badd27a
EG		 1392 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1393 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1394 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1395 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1396 } else if (msi) {
1397 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1398 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1399 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1400 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1401 } else {
1402 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1403 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1404 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1405 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1406
a0fd065c
DK		 1407 if (!CHIP_IS_E1(bp)) {
1408 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1409 val, port, addr);
615f8fd9 1410
a0fd065c 1411 REG_WR(bp, addr, val);
615f8fd9 1412
a0fd065c
DK		 1413 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1414 }
a2fbb9ea
ET		 1415 }
1416
a0fd065c
DK		 1417 if (CHIP_IS_E1(bp))
1418 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1419
8badd27a
EG		 1420 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1421 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1422
1423 REG_WR(bp, addr, val);
37dbbf32
EG		 1424 /*
1425 * Ensure that HC_CONFIG is written before leading/trailing edge config
1426 */
1427 mmiowb();
1428 barrier();
34f80b04 1429
f2e0899f 1430 if (!CHIP_IS_E1(bp)) {
34f80b04 1431 /* init leading/trailing edge */
fb3bff17 1432 if (IS_MF(bp)) {
3395a033 1433 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1434 if (bp->port.pmf)
4acac6a5
EG		 1435 /* enable nig and gpio3 attention */
1436 val |= 0x1100;
34f80b04
EG		 1437 } else
1438 val = 0xffff;
1439
1440 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1441 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1442 }
37dbbf32
EG		 1443
1444 /* Make sure that interrupts are indeed enabled from here on */
1445 mmiowb();
a2fbb9ea
ET		 1446}
1447
f2e0899f
DK		 1448static void bnx2x_igu_int_enable(struct bnx2x *bp)
1449{
1450 u32 val;
1451 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1452 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1453
1454 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1455
1456 if (msix) {
1457 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1458 IGU_PF_CONF_SINGLE_ISR_EN);
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_MSI_MSIX_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN);
1462 } else if (msi) {
1463 val &= ~IGU_PF_CONF_INT_LINE_EN;
1464 val |= (IGU_PF_CONF_FUNC_EN |
1465 IGU_PF_CONF_MSI_MSIX_EN |
1466 IGU_PF_CONF_ATTN_BIT_EN |
1467 IGU_PF_CONF_SINGLE_ISR_EN);
1468 } else {
1469 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1470 val |= (IGU_PF_CONF_FUNC_EN |
1471 IGU_PF_CONF_INT_LINE_EN |
1472 IGU_PF_CONF_ATTN_BIT_EN |
1473 IGU_PF_CONF_SINGLE_ISR_EN);
1474 }
1475
1476 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1477 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1478
1479 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1480
1481 barrier();
1482
1483 /* init leading/trailing edge */
1484 if (IS_MF(bp)) {
3395a033 1485 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1486 if (bp->port.pmf)
1487 /* enable nig and gpio3 attention */
1488 val |= 0x1100;
1489 } else
1490 val = 0xffff;
1491
1492 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1493 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1494
1495 /* Make sure that interrupts are indeed enabled from here on */
1496 mmiowb();
1497}
1498
1499void bnx2x_int_enable(struct bnx2x *bp)
1500{
1501 if (bp->common.int_block == INT_BLOCK_HC)
1502 bnx2x_hc_int_enable(bp);
1503 else
1504 bnx2x_igu_int_enable(bp);
1505}
1506
1507static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1508{
34f80b04 1509 int port = BP_PORT(bp);
a2fbb9ea
ET		 1510 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1511 u32 val = REG_RD(bp, addr);
1512
a0fd065c
DK		 1513 /*
1514 * in E1 we must use only PCI configuration space to disable
1515 * MSI/MSIX capablility
1516 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1517 */
1518 if (CHIP_IS_E1(bp)) {
1519 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1520 * Use mask register to prevent from HC sending interrupts
1521 * after we exit the function
1522 */
1523 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1524
1525 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1526 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1527 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1528 } else
1529 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1530 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1531 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1532 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1533
1534 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1535 val, port, addr);
1536
8badd27a
EG		 1537 /* flush all outstanding writes */
1538 mmiowb();
1539
a2fbb9ea
ET		 1540 REG_WR(bp, addr, val);
1541 if (REG_RD(bp, addr) != val)
1542 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1543}
1544
f2e0899f
DK		 1545static void bnx2x_igu_int_disable(struct bnx2x *bp)
1546{
1547 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1548
1549 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1550 IGU_PF_CONF_INT_LINE_EN |
1551 IGU_PF_CONF_ATTN_BIT_EN);
1552
1553 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1554
1555 /* flush all outstanding writes */
1556 mmiowb();
1557
1558 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1559 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1560 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1561}
1562
6383c0b3 1563void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1564{
1565 if (bp->common.int_block == INT_BLOCK_HC)
1566 bnx2x_hc_int_disable(bp);
1567 else
1568 bnx2x_igu_int_disable(bp);
1569}
1570
9f6c9258 1571void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1572{
a2fbb9ea 1573 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1574 int i, offset;
a2fbb9ea 1575
f8ef6e44
YG		 1576 if (disable_hw)
1577 /* prevent the HW from sending interrupts */
1578 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1579
1580 /* make sure all ISRs are done */
1581 if (msix) {
8badd27a
EG		 1582 synchronize_irq(bp->msix_table[0].vector);
1583 offset = 1;
37b091ba
MC		 1584#ifdef BCM_CNIC
1585 offset++;
1586#endif
ec6ba945 1587 for_each_eth_queue(bp, i)
754a2f52 1588 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1589 } else
1590 synchronize_irq(bp->pdev->irq);
1591
1592 /* make sure sp_task is not running */
1cf167f2 1593 cancel_delayed_work(&bp->sp_task);
3deb8167 1594 cancel_delayed_work(&bp->period_task);
1cf167f2 1595 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1596}
1597
34f80b04 1598/* fast path */
a2fbb9ea
ET		 1599
1600/*
34f80b04 1601 * General service functions
a2fbb9ea
ET		 1602 */
1603
72fd0718
VZ		 1604/* Return true if succeeded to acquire the lock */
1605static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1606{
1607 u32 lock_status;
1608 u32 resource_bit = (1 << resource);
1609 int func = BP_FUNC(bp);
1610 u32 hw_lock_control_reg;
1611
1612 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1613
1614 /* Validating that the resource is within range */
1615 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1616 DP(NETIF_MSG_HW,
1617 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1618 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1619 return false;
72fd0718
VZ		 1620 }
1621
1622 if (func <= 5)
1623 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1624 else
1625 hw_lock_control_reg =
1626 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1627
1628 /* Try to acquire the lock */
1629 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1630 lock_status = REG_RD(bp, hw_lock_control_reg);
1631 if (lock_status & resource_bit)
1632 return true;
1633
1634 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1635 return false;
1636}
1637
c9ee9206
VZ		 1638/**
1639 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1640 *
1641 * @bp: driver handle
1642 *
1643 * Returns the recovery leader resource id according to the engine this function
1644 * belongs to. Currently only only 2 engines is supported.
1645 */
1646static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1647{
1648 if (BP_PATH(bp))
1649 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1650 else
1651 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1652}
1653
1654/**
1655 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1656 *
1657 * @bp: driver handle
1658 *
1659 * Tries to aquire a leader lock for cuurent engine.
1660 */
1661static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1662{
1663 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1664}
1665
993ac7b5 1666#ifdef BCM_CNIC
619c5cb6 1667static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
993ac7b5 1668#endif
3196a88a 1669
619c5cb6 1670void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1671{
1672 struct bnx2x *bp = fp->bp;
1673 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1674 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6
VZ		 1675 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1676 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
a2fbb9ea 1677
34f80b04 1678 DP(BNX2X_MSG_SP,
a2fbb9ea 1679 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1680 fp->index, cid, command, bp->state,
34f80b04 1681 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1682
619c5cb6
VZ		 1683 switch (command) {
1684 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1685 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1686 drv_cmd = BNX2X_Q_CMD_UPDATE;
1687 break;
d6cae238 1688
619c5cb6 1689 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1690 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1691 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1692 break;
1693
6383c0b3
AE		 1694 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1695 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1696 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1697 break;
1698
619c5cb6 1699 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1700 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1701 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1702 break;
1703
619c5cb6 1704 case (RAMROD_CMD_ID_ETH_TERMINATE):
d6cae238 1705 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1706 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1707 break;
1708
619c5cb6 1709 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1710 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1711 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1712 break;
619c5cb6
VZ		 1713
1714 default:
1715 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1716 command, fp->index);
1717 return;
523224a3 1718 }
3196a88a 1719
619c5cb6
VZ		 1720 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1721 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1722 /* q_obj->complete_cmd() failure means that this was
1723 * an unexpected completion.
1724 *
1725 * In this case we don't want to increase the bp->spq_left
1726 * because apparently we haven't sent this command the first
1727 * place.
1728 */
1729#ifdef BNX2X_STOP_ON_ERROR
1730 bnx2x_panic();
1731#else
1732 return;
1733#endif
1734
8fe23fbd 1735 smp_mb__before_atomic_inc();
6e30dd4e 1736 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1737 /* push the change in bp->spq_left and towards the memory */
1738 smp_mb__after_atomic_inc();
49d66772 1739
d6cae238
VZ		 1740 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1741
523224a3 1742 return;
a2fbb9ea
ET		 1743}
1744
619c5cb6
VZ		 1745void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1746 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1747{
1748 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1749
1750 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1751 start);
1752}
1753
9f6c9258 1754irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1755{
555f6c78 1756 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1757 u16 status = bnx2x_ack_int(bp);
34f80b04 1758 u16 mask;
ca00392c 1759 int i;
6383c0b3 1760 u8 cos;
a2fbb9ea 1761
34f80b04 1762 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1763 if (unlikely(status == 0)) {
1764 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1765 return IRQ_NONE;
1766 }
f5372251 1767 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1768
3196a88a
EG		 1769#ifdef BNX2X_STOP_ON_ERROR
1770 if (unlikely(bp->panic))
1771 return IRQ_HANDLED;
1772#endif
1773
ec6ba945 1774 for_each_eth_queue(bp, i) {
ca00392c 1775 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1776
6383c0b3 1777 mask = 0x2 << (fp->index + CNIC_PRESENT);
ca00392c 1778 if (status & mask) {
619c5cb6 1779 /* Handle Rx or Tx according to SB id */
54b9ddaa 1780 prefetch(fp->rx_cons_sb);
6383c0b3
AE		 1781 for_each_cos_in_tx_queue(fp, cos)
1782 prefetch(fp->txdata[cos].tx_cons_sb);
523224a3 1783 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1784 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1785 status &= ~mask;
1786 }
a2fbb9ea
ET		 1787 }
1788
993ac7b5 1789#ifdef BCM_CNIC
523224a3 1790 mask = 0x2;
993ac7b5
MC		 1791 if (status & (mask | 0x1)) {
1792 struct cnic_ops *c_ops = NULL;
1793
619c5cb6
VZ		 1794 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1795 rcu_read_lock();
1796 c_ops = rcu_dereference(bp->cnic_ops);
1797 if (c_ops)
1798 c_ops->cnic_handler(bp->cnic_data, NULL);
1799 rcu_read_unlock();
1800 }
993ac7b5
MC		 1801
1802 status &= ~mask;
1803 }
1804#endif
a2fbb9ea 1805
34f80b04 1806 if (unlikely(status & 0x1)) {
1cf167f2 1807 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1808
1809 status &= ~0x1;
1810 if (!status)
1811 return IRQ_HANDLED;
1812 }
1813
cdaa7cb8
VZ		 1814 if (unlikely(status))
1815 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1816 status);
a2fbb9ea 1817
c18487ee 1818 return IRQ_HANDLED;
a2fbb9ea
ET		 1819}
1820
c18487ee
YR		 1821/* Link */
1822
1823/*
1824 * General service functions
1825 */
a2fbb9ea 1826
9f6c9258 1827int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1828{
1829 u32 lock_status;
1830 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1831 int func = BP_FUNC(bp);
1832 u32 hw_lock_control_reg;
c18487ee 1833 int cnt;
a2fbb9ea 1834
c18487ee
YR		 1835 /* Validating that the resource is within range */
1836 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1837 DP(NETIF_MSG_HW,
1838 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1839 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1840 return -EINVAL;
1841 }
a2fbb9ea 1842
4a37fb66
YG		 1843 if (func <= 5) {
1844 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1845 } else {
1846 hw_lock_control_reg =
1847 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1848 }
1849
c18487ee 1850 /* Validating that the resource is not already taken */
4a37fb66 1851 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1852 if (lock_status & resource_bit) {
1853 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1854 lock_status, resource_bit);
1855 return -EEXIST;
1856 }
a2fbb9ea 1857
46230476
EG		 1858 /* Try for 5 second every 5ms */
1859 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1860 /* Try to acquire the lock */
4a37fb66
YG		 1861 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1862 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1863 if (lock_status & resource_bit)
1864 return 0;
a2fbb9ea 1865
c18487ee 1866 msleep(5);
a2fbb9ea 1867 }
c18487ee
YR		 1868 DP(NETIF_MSG_HW, "Timeout\n");
1869 return -EAGAIN;
1870}
a2fbb9ea 1871
c9ee9206
VZ		 1872int bnx2x_release_leader_lock(struct bnx2x *bp)
1873{
1874 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1875}
1876
9f6c9258 1877int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1878{
1879 u32 lock_status;
1880 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1881 int func = BP_FUNC(bp);
1882 u32 hw_lock_control_reg;
a2fbb9ea 1883
72fd0718
VZ		 1884 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1885
c18487ee
YR		 1886 /* Validating that the resource is within range */
1887 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1888 DP(NETIF_MSG_HW,
1889 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1890 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1891 return -EINVAL;
1892 }
1893
4a37fb66
YG		 1894 if (func <= 5) {
1895 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1896 } else {
1897 hw_lock_control_reg =
1898 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1899 }
1900
c18487ee 1901 /* Validating that the resource is currently taken */
4a37fb66 1902 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1903 if (!(lock_status & resource_bit)) {
1904 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1905 lock_status, resource_bit);
1906 return -EFAULT;
a2fbb9ea
ET		 1907 }
1908
9f6c9258
DK		 1909 REG_WR(bp, hw_lock_control_reg, resource_bit);
1910 return 0;
c18487ee 1911}
a2fbb9ea 1912
9f6c9258 1913
4acac6a5
EG		 1914int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1915{
1916 /* The GPIO should be swapped if swap register is set and active */
1917 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1918 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1919 int gpio_shift = gpio_num +
1920 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1921 u32 gpio_mask = (1 << gpio_shift);
1922 u32 gpio_reg;
1923 int value;
1924
1925 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1926 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1927 return -EINVAL;
1928 }
1929
1930 /* read GPIO value */
1931 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1932
1933 /* get the requested pin value */
1934 if ((gpio_reg & gpio_mask) == gpio_mask)
1935 value = 1;
1936 else
1937 value = 0;
1938
1939 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1940
1941 return value;
1942}
1943
17de50b7 1944int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1945{
1946 /* The GPIO should be swapped if swap register is set and active */
1947 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1948 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1949 int gpio_shift = gpio_num +
1950 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1951 u32 gpio_mask = (1 << gpio_shift);
1952 u32 gpio_reg;
a2fbb9ea 1953
c18487ee
YR		 1954 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1955 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1956 return -EINVAL;
1957 }
a2fbb9ea 1958
4a37fb66 1959 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1960 /* read GPIO and mask except the float bits */
1961 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1962
c18487ee
YR		 1963 switch (mode) {
1964 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1965 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1966 gpio_num, gpio_shift);
1967 /* clear FLOAT and set CLR */
1968 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1969 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1970 break;
a2fbb9ea 1971
c18487ee
YR		 1972 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1973 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1974 gpio_num, gpio_shift);
1975 /* clear FLOAT and set SET */
1976 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1977 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1978 break;
a2fbb9ea 1979
17de50b7 1980 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1981 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1982 gpio_num, gpio_shift);
1983 /* set FLOAT */
1984 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1985 break;
a2fbb9ea 1986
c18487ee
YR		 1987 default:
1988 break;
a2fbb9ea
ET		 1989 }
1990
c18487ee 1991 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1992 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1993
c18487ee 1994 return 0;
a2fbb9ea
ET		 1995}
1996
0d40f0d4
YR		 1997int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1998{
1999 u32 gpio_reg = 0;
2000 int rc = 0;
2001
2002 /* Any port swapping should be handled by caller. */
2003
2004 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2005 /* read GPIO and mask except the float bits */
2006 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2007 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2008 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2009 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2010
2011 switch (mode) {
2012 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2013 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2014 /* set CLR */
2015 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2016 break;
2017
2018 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2019 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2020 /* set SET */
2021 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2022 break;
2023
2024 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2025 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2026 /* set FLOAT */
2027 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2028 break;
2029
2030 default:
2031 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2032 rc = -EINVAL;
2033 break;
2034 }
2035
2036 if (rc == 0)
2037 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2038
2039 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2040
2041 return rc;
2042}
2043
4acac6a5
EG		 2044int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2045{
2046 /* The GPIO should be swapped if swap register is set and active */
2047 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2048 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2049 int gpio_shift = gpio_num +
2050 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2051 u32 gpio_mask = (1 << gpio_shift);
2052 u32 gpio_reg;
2053
2054 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2055 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2056 return -EINVAL;
2057 }
2058
2059 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2060 /* read GPIO int */
2061 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2062
2063 switch (mode) {
2064 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2065 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2066 "output low\n", gpio_num, gpio_shift);
2067 /* clear SET and set CLR */
2068 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2069 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2070 break;
2071
2072 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2073 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2074 "output high\n", gpio_num, gpio_shift);
2075 /* clear CLR and set SET */
2076 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2077 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2078 break;
2079
2080 default:
2081 break;
2082 }
2083
2084 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2085 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2086
2087 return 0;
2088}
2089
c18487ee 2090static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 2091{
c18487ee
YR		 2092 u32 spio_mask = (1 << spio_num);
2093 u32 spio_reg;
a2fbb9ea 2094
c18487ee
YR		 2095 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2096 (spio_num > MISC_REGISTERS_SPIO_7)) {
2097 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2098 return -EINVAL;
a2fbb9ea
ET		 2099 }
2100
4a37fb66 2101 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 2102 /* read SPIO and mask except the float bits */
2103 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 2104
c18487ee 2105 switch (mode) {
6378c025 2106 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 2107 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2108 /* clear FLOAT and set CLR */
2109 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2111 break;
a2fbb9ea 2112
6378c025 2113 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 2114 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2115 /* clear FLOAT and set SET */
2116 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2117 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2118 break;
a2fbb9ea 2119
c18487ee
YR		 2120 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2121 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2122 /* set FLOAT */
2123 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2124 break;
a2fbb9ea 2125
c18487ee
YR		 2126 default:
2127 break;
a2fbb9ea
ET		 2128 }
2129
c18487ee 2130 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2131 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2132
a2fbb9ea
ET		 2133 return 0;
2134}
2135
9f6c9258 2136void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2137{
a22f0788 2138 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2139 switch (bp->link_vars.ieee_fc &
2140 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2141 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2142 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2143 ADVERTISED_Pause);
c18487ee 2144 break;
356e2385 2145
c18487ee 2146 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2147 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2148 ADVERTISED_Pause);
c18487ee 2149 break;
356e2385 2150
c18487ee 2151 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2152 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2153 break;
356e2385 2154
c18487ee 2155 default:
a22f0788 2156 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2157 ADVERTISED_Pause);
c18487ee
YR		 2158 break;
2159 }
2160}
f1410647 2161
9f6c9258 2162u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 2163{
19680c48
EG		 2164 if (!BP_NOMCP(bp)) {
2165 u8 rc;
a22f0788
YR		 2166 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2167 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1cb0c788
YR		 2168 /*
2169 * Initialize link parameters structure variables
2170 * It is recommended to turn off RX FC for jumbo frames
2171 * for better performance
2172 */
2173 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
c0700f90 2174 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 2175 else
c0700f90 2176 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 2177
4a37fb66 2178 bnx2x_acquire_phy_lock(bp);
b5bf9068 2179
a22f0788 2180 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2181 struct link_params *lp = &bp->link_params;
2182 lp->loopback_mode = LOOPBACK_XGXS;
2183 /* do PHY loopback at 10G speed, if possible */
2184 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2185 if (lp->speed_cap_mask[cfx_idx] &
2186 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2187 lp->req_line_speed[cfx_idx] =
2188 SPEED_10000;
2189 else
2190 lp->req_line_speed[cfx_idx] =
2191 SPEED_1000;
2192 }
a22f0788 2193 }
b5bf9068 2194
19680c48 2195 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2196
4a37fb66 2197 bnx2x_release_phy_lock(bp);
a2fbb9ea 2198
3c96c68b
EG		 2199 bnx2x_calc_fc_adv(bp);
2200
b5bf9068
EG		 2201 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2202 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2203 bnx2x_link_report(bp);
3deb8167
YR		 2204 } else
2205 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2206 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2207 return rc;
2208 }
f5372251 2209 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2210 return -EINVAL;
a2fbb9ea
ET		 2211}
2212
9f6c9258 2213void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2214{
19680c48 2215 if (!BP_NOMCP(bp)) {
4a37fb66 2216 bnx2x_acquire_phy_lock(bp);
54c2fb78 2217 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 2218 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2219 bnx2x_release_phy_lock(bp);
a2fbb9ea 2220
19680c48
EG		 2221 bnx2x_calc_fc_adv(bp);
2222 } else
f5372251 2223 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2224}
a2fbb9ea 2225
c18487ee
YR		 2226static void bnx2x__link_reset(struct bnx2x *bp)
2227{
19680c48 2228 if (!BP_NOMCP(bp)) {
4a37fb66 2229 bnx2x_acquire_phy_lock(bp);
589abe3a 2230 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 2231 bnx2x_release_phy_lock(bp);
19680c48 2232 } else
f5372251 2233 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2234}
a2fbb9ea 2235
a22f0788 2236u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2237{
2145a920 2238 u8 rc = 0;
a2fbb9ea 2239
2145a920
VZ		 2240 if (!BP_NOMCP(bp)) {
2241 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2242 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2243 is_serdes);
2145a920
VZ		 2244 bnx2x_release_phy_lock(bp);
2245 } else
2246 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2247
c18487ee
YR		 2248 return rc;
2249}
a2fbb9ea 2250
8a1c38d1 2251static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 2252{
8a1c38d1
EG		 2253 u32 r_param = bp->link_vars.line_speed / 8;
2254 u32 fair_periodic_timeout_usec;
2255 u32 t_fair;
34f80b04 2256
8a1c38d1
EG		 2257 memset(&(bp->cmng.rs_vars), 0,
2258 sizeof(struct rate_shaping_vars_per_port));
2259 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 2260
8a1c38d1
EG		 2261 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2262 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 2263
8a1c38d1
EG		 2264 /* this is the threshold below which no timer arming will occur
2265 1.25 coefficient is for the threshold to be a little bigger
2266 than the real time, to compensate for timer in-accuracy */
2267 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 2268 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2269
8a1c38d1
EG		 2270 /* resolution of fairness timer */
2271 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2272 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2273 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 2274
8a1c38d1
EG		 2275 /* this is the threshold below which we won't arm the timer anymore */
2276 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 2277
8a1c38d1
EG		 2278 /* we multiply by 1e3/8 to get bytes/msec.
2279 We don't want the credits to pass a credit
2280 of the t_fair*FAIR_MEM (algorithm resolution) */
2281 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2282 /* since each tick is 4 usec */
2283 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 2284}
2285
2691d51d
EG		 2286/* Calculates the sum of vn_min_rates.
2287 It's needed for further normalizing of the min_rates.
2288 Returns:
2289 sum of vn_min_rates.
2290 or
2291 0 - if all the min_rates are 0.
2292 In the later case fainess algorithm should be deactivated.
2293 If not all min_rates are zero then those that are zeroes will be set to 1.
2294 */
2295static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2296{
2297 int all_zero = 1;
2691d51d
EG		 2298 int vn;
2299
2300 bp->vn_weight_sum = 0;
3395a033 2301 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2302 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2303 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2304 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2305
2306 /* Skip hidden vns */
2307 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2308 continue;
2309
2310 /* If min rate is zero - set it to 1 */
2311 if (!vn_min_rate)
2312 vn_min_rate = DEF_MIN_RATE;
2313 else
2314 all_zero = 0;
2315
2316 bp->vn_weight_sum += vn_min_rate;
2317 }
2318
30ae438b
DK		 2319 /* if ETS or all min rates are zeros - disable fairness */
2320 if (BNX2X_IS_ETS_ENABLED(bp)) {
2321 bp->cmng.flags.cmng_enables &=
2322 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2323 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2324 } else if (all_zero) {
b015e3d1
EG		 2325 bp->cmng.flags.cmng_enables &=
2326 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2327 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2328 " fairness will be disabled\n");
2329 } else
2330 bp->cmng.flags.cmng_enables |=
2331 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2332}
2333
f2e0899f 2334static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 2335{
2336 struct rate_shaping_vars_per_vn m_rs_vn;
2337 struct fairness_vars_per_vn m_fair_vn;
f2e0899f 2338 u32 vn_cfg = bp->mf_config[vn];
3395a033 2339 int func = func_by_vn(bp, vn);
34f80b04
EG		 2340 u16 vn_min_rate, vn_max_rate;
2341 int i;
2342
2343 /* If function is hidden - set min and max to zeroes */
2344 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2345 vn_min_rate = 0;
2346 vn_max_rate = 0;
2347
2348 } else {
faa6fcbb
DK		 2349 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2350
34f80b04
EG		 2351 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2352 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 2353 /* If fairness is enabled (not all min rates are zeroes) and
2354 if current min rate is zero - set it to 1.
2355 This is a requirement of the algorithm. */
f2e0899f 2356 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 2357 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 2358
2359 if (IS_MF_SI(bp))
2360 /* maxCfg in percents of linkspeed */
2361 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2362 else
2363 /* maxCfg is absolute in 100Mb units */
2364 vn_max_rate = maxCfg * 100;
34f80b04 2365 }
f85582f8 2366
8a1c38d1 2367 DP(NETIF_MSG_IFUP,
b015e3d1 2368 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 2369 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 2370
2371 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2372 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2373
2374 /* global vn counter - maximal Mbps for this vn */
2375 m_rs_vn.vn_counter.rate = vn_max_rate;
2376
2377 /* quota - number of bytes transmitted in this period */
2378 m_rs_vn.vn_counter.quota =
2379 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2380
8a1c38d1 2381 if (bp->vn_weight_sum) {
34f80b04
EG		 2382 /* credit for each period of the fairness algorithm:
2383 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2384 vn_weight_sum should not be larger than 10000, thus
2385 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2386 than zero */
34f80b04 2387 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2388 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2389 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2390 (bp->cmng.fair_vars.fair_threshold +
2391 MIN_ABOVE_THRESH));
cdaa7cb8 2392 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2393 m_fair_vn.vn_credit_delta);
2394 }
2395
34f80b04
EG		 2396 /* Store it to internal memory */
2397 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2398 REG_WR(bp, BAR_XSTRORM_INTMEM +
2399 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2400 ((u32 *)(&m_rs_vn))[i]);
2401
2402 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2403 REG_WR(bp, BAR_XSTRORM_INTMEM +
2404 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2405 ((u32 *)(&m_fair_vn))[i]);
2406}
f85582f8 2407
523224a3
DK		 2408static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2409{
2410 if (CHIP_REV_IS_SLOW(bp))
2411 return CMNG_FNS_NONE;
fb3bff17 2412 if (IS_MF(bp))
523224a3
DK		 2413 return CMNG_FNS_MINMAX;
2414
2415 return CMNG_FNS_NONE;
2416}
2417
2ae17f66 2418void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2419{
0793f83f 2420 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2421
2422 if (BP_NOMCP(bp))
2423 return; /* what should be the default bvalue in this case */
2424
0793f83f
DK		 2425 /* For 2 port configuration the absolute function number formula
2426 * is:
2427 * abs_func = 2 * vn + BP_PORT + BP_PATH
2428 *
2429 * and there are 4 functions per port
2430 *
2431 * For 4 port configuration it is
2432 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2433 *
2434 * and there are 2 functions per port
2435 */
3395a033 2436 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2437 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2438
2439 if (func >= E1H_FUNC_MAX)
2440 break;
2441
f2e0899f 2442 bp->mf_config[vn] =
523224a3
DK		 2443 MF_CFG_RD(bp, func_mf_config[func].config);
2444 }
2445}
2446
2447static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2448{
2449
2450 if (cmng_type == CMNG_FNS_MINMAX) {
2451 int vn;
2452
2453 /* clear cmng_enables */
2454 bp->cmng.flags.cmng_enables = 0;
2455
2456 /* read mf conf from shmem */
2457 if (read_cfg)
2458 bnx2x_read_mf_cfg(bp);
2459
2460 /* Init rate shaping and fairness contexts */
2461 bnx2x_init_port_minmax(bp);
2462
2463 /* vn_weight_sum and enable fairness if not 0 */
2464 bnx2x_calc_vn_weight_sum(bp);
2465
2466 /* calculate and set min-max rate for each vn */
c4154f25 2467 if (bp->port.pmf)
3395a033 2468 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
c4154f25 2469 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2470
2471 /* always enable rate shaping and fairness */
2472 bp->cmng.flags.cmng_enables |=
2473 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2474 if (!bp->vn_weight_sum)
2475 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2476 " fairness will be disabled\n");
2477 return;
2478 }
2479
2480 /* rate shaping and fairness are disabled */
2481 DP(NETIF_MSG_IFUP,
2482 "rate shaping and fairness are disabled\n");
2483}
34f80b04 2484
c18487ee
YR		 2485/* This function is called upon link interrupt */
2486static void bnx2x_link_attn(struct bnx2x *bp)
2487{
bb2a0f7a
YG		 2488 /* Make sure that we are synced with the current statistics */
2489 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2490
c18487ee 2491 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2492
bb2a0f7a
YG		 2493 if (bp->link_vars.link_up) {
2494
1c06328c 2495 /* dropless flow control */
f2e0899f 2496 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2497 int port = BP_PORT(bp);
2498 u32 pause_enabled = 0;
2499
2500 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2501 pause_enabled = 1;
2502
2503 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2504 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2505 pause_enabled);
2506 }
2507
619c5cb6 2508 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2509 struct host_port_stats *pstats;
2510
2511 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2512 /* reset old mac stats */
bb2a0f7a
YG		 2513 memset(&(pstats->mac_stx[0]), 0,
2514 sizeof(struct mac_stx));
2515 }
f34d28ea 2516 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2517 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2518 }
2519
f2e0899f
DK		 2520 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2521 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2522
f2e0899f
DK		 2523 if (cmng_fns != CMNG_FNS_NONE) {
2524 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2525 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2526 } else
2527 /* rate shaping and fairness are disabled */
2528 DP(NETIF_MSG_IFUP,
2529 "single function mode without fairness\n");
34f80b04 2530 }
9fdc3e95 2531
2ae17f66
VZ		 2532 __bnx2x_link_report(bp);
2533
9fdc3e95
DK		 2534 if (IS_MF(bp))
2535 bnx2x_link_sync_notify(bp);
c18487ee 2536}
a2fbb9ea 2537
9f6c9258 2538void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2539{
2ae17f66 2540 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2541 return;
a2fbb9ea 2542
00253a8c
DK		 2543 /* read updated dcb configuration */
2544 bnx2x_dcbx_pmf_update(bp);
2545
c18487ee 2546 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2547
bb2a0f7a
YG		 2548 if (bp->link_vars.link_up)
2549 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2550 else
2551 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2552
c18487ee
YR		 2553 /* indicate link status */
2554 bnx2x_link_report(bp);
a2fbb9ea 2555}
a2fbb9ea 2556
34f80b04
EG		 2557static void bnx2x_pmf_update(struct bnx2x *bp)
2558{
2559 int port = BP_PORT(bp);
2560 u32 val;
2561
2562 bp->port.pmf = 1;
2563 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2564
3deb8167
YR		 2565 /*
2566 * We need the mb() to ensure the ordering between the writing to
2567 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2568 */
2569 smp_mb();
2570
2571 /* queue a periodic task */
2572 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2573
ef01854e
DK		 2574 bnx2x_dcbx_pmf_update(bp);
2575
34f80b04 2576 /* enable nig attention */
3395a033 2577 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2578 if (bp->common.int_block == INT_BLOCK_HC) {
2579 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2580 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2581 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2582 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2583 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2584 }
bb2a0f7a
YG		 2585
2586 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2587}
2588
c18487ee 2589/* end of Link */
a2fbb9ea
ET		 2590
2591/* slow path */
2592
2593/*
2594 * General service functions
2595 */
2596
2691d51d 2597/* send the MCP a request, block until there is a reply */
a22f0788 2598u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2599{
f2e0899f 2600 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2601 u32 seq;
2691d51d
EG		 2602 u32 rc = 0;
2603 u32 cnt = 1;
2604 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2605
c4ff7cbf 2606 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2607 seq = ++bp->fw_seq;
f2e0899f
DK		 2608 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2609 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2610
754a2f52
DK		 2611 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2612 (command | seq), param);
2691d51d
EG		 2613
2614 do {
2615 /* let the FW do it's magic ... */
2616 msleep(delay);
2617
f2e0899f 2618 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2619
c4ff7cbf
EG		 2620 /* Give the FW up to 5 second (500*10ms) */
2621 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2622
2623 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2624 cnt*delay, rc, seq);
2625
2626 /* is this a reply to our command? */
2627 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2628 rc &= FW_MSG_CODE_MASK;
2629 else {
2630 /* FW BUG! */
2631 BNX2X_ERR("FW failed to respond!\n");
2632 bnx2x_fw_dump(bp);
2633 rc = 0;
2634 }
c4ff7cbf 2635 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2636
2637 return rc;
2638}
2639
ec6ba945 2640
619c5cb6
VZ		 2641void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2642{
2643 if (CHIP_IS_E1x(bp)) {
2644 struct tstorm_eth_function_common_config tcfg = {0};
2645
2646 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2647 }
2648
2649 /* Enable the function in the FW */
2650 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2651 storm_memset_func_en(bp, p->func_id, 1);
2652
2653 /* spq */
2654 if (p->func_flgs & FUNC_FLG_SPQ) {
2655 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2656 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2657 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2658 }
2659}
2660
6383c0b3
AE		 2661/**
2662 * bnx2x_get_tx_only_flags - Return common flags
2663 *
2664 * @bp device handle
2665 * @fp queue handle
2666 * @zero_stats TRUE if statistics zeroing is needed
2667 *
2668 * Return the flags that are common for the Tx-only and not normal connections.
2669 */
2670static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2671 struct bnx2x_fastpath *fp,
2672 bool zero_stats)
28912902 2673{
619c5cb6
VZ		 2674 unsigned long flags = 0;
2675
2676 /* PF driver will always initialize the Queue to an ACTIVE state */
2677 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2678
6383c0b3
AE		 2679 /* tx only connections collect statistics (on the same index as the
2680 * parent connection). The statistics are zeroed when the parent
2681 * connection is initialized.
2682 */
50f0a562
BW		 2683
2684 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2685 if (zero_stats)
2686 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2687
6383c0b3
AE		 2688
2689 return flags;
2690}
2691
2692static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2693 struct bnx2x_fastpath *fp,
2694 bool leading)
2695{
2696 unsigned long flags = 0;
2697
619c5cb6
VZ		 2698 /* calculate other queue flags */
2699 if (IS_MF_SD(bp))
2700 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2701
619c5cb6
VZ		 2702 if (IS_FCOE_FP(fp))
2703 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
523224a3 2704
f5219d8e 2705 if (!fp->disable_tpa) {
619c5cb6 2706 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e
VZ		 2707 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2708 }
619c5cb6 2709
619c5cb6
VZ		 2710 if (leading) {
2711 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2712 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2713 }
523224a3 2714
619c5cb6
VZ		 2715 /* Always set HW VLAN stripping */
2716 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2717
6383c0b3
AE		 2718
2719 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2720}
2721
619c5cb6 2722static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2723 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2724 u8 cos)
619c5cb6
VZ		 2725{
2726 gen_init->stat_id = bnx2x_stats_id(fp);
2727 gen_init->spcl_id = fp->cl_id;
2728
2729 /* Always use mini-jumbo MTU for FCoE L2 ring */
2730 if (IS_FCOE_FP(fp))
2731 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2732 else
2733 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2734
2735 gen_init->cos = cos;
619c5cb6
VZ		 2736}
2737
2738static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2739 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2740 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2741{
619c5cb6 2742 u8 max_sge = 0;
523224a3
DK		 2743 u16 sge_sz = 0;
2744 u16 tpa_agg_size = 0;
2745
523224a3 2746 if (!fp->disable_tpa) {
dfacf138
DK		 2747 pause->sge_th_lo = SGE_TH_LO(bp);
2748 pause->sge_th_hi = SGE_TH_HI(bp);
2749
2750 /* validate SGE ring has enough to cross high threshold */
2751 WARN_ON(bp->dropless_fc &&
2752 pause->sge_th_hi + FW_PREFETCH_CNT >
2753 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2754
523224a3
DK		 2755 tpa_agg_size = min_t(u32,
2756 (min_t(u32, 8, MAX_SKB_FRAGS) *
2757 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2758 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2759 SGE_PAGE_SHIFT;
2760 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2761 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2762 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2763 0xffff);
2764 }
2765
2766 /* pause - not for e1 */
2767 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 2768 pause->bd_th_lo = BD_TH_LO(bp);
2769 pause->bd_th_hi = BD_TH_HI(bp);
2770
2771 pause->rcq_th_lo = RCQ_TH_LO(bp);
2772 pause->rcq_th_hi = RCQ_TH_HI(bp);
2773 /*
2774 * validate that rings have enough entries to cross
2775 * high thresholds
2776 */
2777 WARN_ON(bp->dropless_fc &&
2778 pause->bd_th_hi + FW_PREFETCH_CNT >
2779 bp->rx_ring_size);
2780 WARN_ON(bp->dropless_fc &&
2781 pause->rcq_th_hi + FW_PREFETCH_CNT >
2782 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 2783
523224a3
DK		 2784 pause->pri_map = 1;
2785 }
2786
2787 /* rxq setup */
523224a3
DK		 2788 rxq_init->dscr_map = fp->rx_desc_mapping;
2789 rxq_init->sge_map = fp->rx_sge_mapping;
2790 rxq_init->rcq_map = fp->rx_comp_mapping;
2791 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 2792
619c5cb6
VZ		 2793 /* This should be a maximum number of data bytes that may be
2794 * placed on the BD (not including paddings).
2795 */
e52fcb24
ED		 2796 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2797 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 2798
523224a3 2799 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 2800 rxq_init->tpa_agg_sz = tpa_agg_size;
2801 rxq_init->sge_buf_sz = sge_sz;
2802 rxq_init->max_sges_pkt = max_sge;
619c5cb6
VZ		 2803 rxq_init->rss_engine_id = BP_FUNC(bp);
2804
2805 /* Maximum number or simultaneous TPA aggregation for this Queue.
2806 *
2807 * For PF Clients it should be the maximum avaliable number.
2808 * VF driver(s) may want to define it to a smaller value.
2809 */
dfacf138 2810 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 2811
523224a3
DK		 2812 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2813 rxq_init->fw_sb_id = fp->fw_sb_id;
2814
ec6ba945
VZ		 2815 if (IS_FCOE_FP(fp))
2816 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2817 else
6383c0b3 2818 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
523224a3
DK		 2819}
2820
619c5cb6 2821static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 2822 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2823 u8 cos)
523224a3 2824{
6383c0b3
AE		 2825 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2826 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 2827 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2828 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 2829
619c5cb6
VZ		 2830 /*
2831 * set the tss leading client id for TX classfication ==
2832 * leading RSS client id
2833 */
2834 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2835
ec6ba945
VZ		 2836 if (IS_FCOE_FP(fp)) {
2837 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2838 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2839 }
523224a3
DK		 2840}
2841
8d96286a 2842static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2843{
2844 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 2845 struct event_ring_data eq_data = { {0} };
2846 u16 flags;
2847
619c5cb6 2848 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2849 /* reset IGU PF statistics: MSIX + ATTN */
2850 /* PF */
2851 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2852 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2853 (CHIP_MODE_IS_4_PORT(bp) ?
2854 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2855 /* ATTN */
2856 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2857 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2858 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2859 (CHIP_MODE_IS_4_PORT(bp) ?
2860 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2861 }
2862
523224a3
DK		 2863 /* function setup flags */
2864 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2865
619c5cb6
VZ		 2866 /* This flag is relevant for E1x only.
2867 * E2 doesn't have a TPA configuration in a function level.
523224a3 2868 */
619c5cb6 2869 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 2870
2871 func_init.func_flgs = flags;
2872 func_init.pf_id = BP_FUNC(bp);
2873 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 2874 func_init.spq_map = bp->spq_mapping;
2875 func_init.spq_prod = bp->spq_prod_idx;
2876
2877 bnx2x_func_init(bp, &func_init);
2878
2879 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2880
2881 /*
619c5cb6
VZ		 2882 * Congestion management values depend on the link rate
2883 * There is no active link so initial link rate is set to 10 Gbps.
2884 * When the link comes up The congestion management values are
2885 * re-calculated according to the actual link rate.
2886 */
523224a3
DK		 2887 bp->link_vars.line_speed = SPEED_10000;
2888 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2889
2890 /* Only the PMF sets the HW */
2891 if (bp->port.pmf)
2892 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2893
523224a3
DK		 2894 /* init Event Queue */
2895 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2896 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2897 eq_data.producer = bp->eq_prod;
2898 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2899 eq_data.sb_id = DEF_SB_ID;
2900 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2901}
2902
2903
2904static void bnx2x_e1h_disable(struct bnx2x *bp)
2905{
2906 int port = BP_PORT(bp);
2907
619c5cb6 2908 bnx2x_tx_disable(bp);
523224a3
DK		 2909
2910 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 2911}
2912
2913static void bnx2x_e1h_enable(struct bnx2x *bp)
2914{
2915 int port = BP_PORT(bp);
2916
2917 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2918
2919 /* Tx queue should be only reenabled */
2920 netif_tx_wake_all_queues(bp->dev);
2921
2922 /*
2923 * Should not call netif_carrier_on since it will be called if the link
2924 * is up when checking for link state
2925 */
2926}
2927
1d187b34
BW		 2928#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
2929
2930static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
2931{
2932 struct eth_stats_info *ether_stat =
2933 &bp->slowpath->drv_info_to_mcp.ether_stat;
2934
2935 /* leave last char as NULL */
2936 memcpy(ether_stat->version, DRV_MODULE_VERSION,
2937 ETH_STAT_INFO_VERSION_LEN - 1);
2938
2939 bp->fp[0].mac_obj.get_n_elements(bp, &bp->fp[0].mac_obj,
2940 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
2941 ether_stat->mac_local);
2942
2943 ether_stat->mtu_size = bp->dev->mtu;
2944
2945 if (bp->dev->features & NETIF_F_RXCSUM)
2946 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
2947 if (bp->dev->features & NETIF_F_TSO)
2948 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
2949 ether_stat->feature_flags |= bp->common.boot_mode;
2950
2951 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
2952
2953 ether_stat->txq_size = bp->tx_ring_size;
2954 ether_stat->rxq_size = bp->rx_ring_size;
2955}
2956
2957static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
2958{
f2fd5c34 2959#ifdef BCM_CNIC
1d187b34
BW		 2960 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
2961 struct fcoe_stats_info *fcoe_stat =
2962 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
2963
2964 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN);
2965
2966 fcoe_stat->qos_priority =
2967 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
2968
2969 /* insert FCoE stats from ramrod response */
2970 if (!NO_FCOE(bp)) {
2971 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
2972 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2973 tstorm_queue_statistics;
2974
2975 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
2976 &bp->fw_stats_data->queue_stats[FCOE_IDX].
2977 xstorm_queue_statistics;
2978
2979 struct fcoe_statistics_params *fw_fcoe_stat =
2980 &bp->fw_stats_data->fcoe;
2981
2982 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
2983 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
2984
2985 ADD_64(fcoe_stat->rx_bytes_hi,
2986 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
2987 fcoe_stat->rx_bytes_lo,
2988 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
2989
2990 ADD_64(fcoe_stat->rx_bytes_hi,
2991 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
2992 fcoe_stat->rx_bytes_lo,
2993 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
2994
2995 ADD_64(fcoe_stat->rx_bytes_hi,
2996 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
2997 fcoe_stat->rx_bytes_lo,
2998 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
2999
3000 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3001 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3002
3003 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3004 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3005
3006 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3007 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3008
3009 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
f33f1fcc 3010 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34
BW		 3011
3012 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3013 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3014
3015 ADD_64(fcoe_stat->tx_bytes_hi,
3016 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3017 fcoe_stat->tx_bytes_lo,
3018 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3019
3020 ADD_64(fcoe_stat->tx_bytes_hi,
3021 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3022 fcoe_stat->tx_bytes_lo,
3023 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3024
3025 ADD_64(fcoe_stat->tx_bytes_hi,
3026 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3027 fcoe_stat->tx_bytes_lo,
3028 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3029
3030 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3031 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3032
3033 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3034 fcoe_q_xstorm_stats->ucast_pkts_sent);
3035
3036 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3037 fcoe_q_xstorm_stats->bcast_pkts_sent);
3038
3039 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3040 fcoe_q_xstorm_stats->mcast_pkts_sent);
3041 }
3042
1d187b34
BW		 3043 /* ask L5 driver to add data to the struct */
3044 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3045#endif
3046}
3047
3048static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3049{
f2fd5c34 3050#ifdef BCM_CNIC
1d187b34
BW		 3051 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3052 struct iscsi_stats_info *iscsi_stat =
3053 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3054
3055 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3056
3057 iscsi_stat->qos_priority =
3058 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3059
1d187b34
BW		 3060 /* ask L5 driver to add data to the struct */
3061 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3062#endif
3063}
3064
0793f83f
DK		 3065/* called due to MCP event (on pmf):
3066 * reread new bandwidth configuration
3067 * configure FW
3068 * notify others function about the change
3069 */
3070static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
3071{
3072 if (bp->link_vars.link_up) {
3073 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3074 bnx2x_link_sync_notify(bp);
3075 }
3076 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3077}
3078
3079static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
3080{
3081 bnx2x_config_mf_bw(bp);
3082 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3083}
3084
1d187b34
BW		 3085static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3086{
3087 enum drv_info_opcode op_code;
3088 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3089
3090 /* if drv_info version supported by MFW doesn't match - send NACK */
3091 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3092 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3093 return;
3094 }
3095
3096 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3097 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3098
3099 memset(&bp->slowpath->drv_info_to_mcp, 0,
3100 sizeof(union drv_info_to_mcp));
3101
3102 switch (op_code) {
3103 case ETH_STATS_OPCODE:
3104 bnx2x_drv_info_ether_stat(bp);
3105 break;
3106 case FCOE_STATS_OPCODE:
3107 bnx2x_drv_info_fcoe_stat(bp);
3108 break;
3109 case ISCSI_STATS_OPCODE:
3110 bnx2x_drv_info_iscsi_stat(bp);
3111 break;
3112 default:
3113 /* if op code isn't supported - send NACK */
3114 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3115 return;
3116 }
3117
3118 /* if we got drv_info attn from MFW then these fields are defined in
3119 * shmem2 for sure
3120 */
3121 SHMEM2_WR(bp, drv_info_host_addr_lo,
3122 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3123 SHMEM2_WR(bp, drv_info_host_addr_hi,
3124 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3125
3126 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3127}
3128
523224a3
DK		 3129static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3130{
3131 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3132
3133 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3134
3135 /*
3136 * This is the only place besides the function initialization
3137 * where the bp->flags can change so it is done without any
3138 * locks
3139 */
f2e0899f 3140 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 3141 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
3142 bp->flags |= MF_FUNC_DIS;
3143
3144 bnx2x_e1h_disable(bp);
3145 } else {
3146 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
3147 bp->flags &= ~MF_FUNC_DIS;
3148
3149 bnx2x_e1h_enable(bp);
3150 }
3151 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3152 }
3153 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3154 bnx2x_config_mf_bw(bp);
523224a3
DK		 3155 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3156 }
3157
3158 /* Report results to MCP */
3159 if (dcc_event)
3160 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3161 else
3162 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3163}
3164
3165/* must be called under the spq lock */
3166static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3167{
3168 struct eth_spe *next_spe = bp->spq_prod_bd;
3169
3170 if (bp->spq_prod_bd == bp->spq_last_bd) {
3171 bp->spq_prod_bd = bp->spq;
3172 bp->spq_prod_idx = 0;
3173 DP(NETIF_MSG_TIMER, "end of spq\n");
3174 } else {
3175 bp->spq_prod_bd++;
3176 bp->spq_prod_idx++;
3177 }
3178 return next_spe;
3179}
3180
3181/* must be called under the spq lock */
28912902
MC		 3182static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3183{
3184 int func = BP_FUNC(bp);
3185
53e51e2f
VZ		 3186 /*
3187 * Make sure that BD data is updated before writing the producer:
3188 * BD data is written to the memory, the producer is read from the
3189 * memory, thus we need a full memory barrier to ensure the ordering.
3190 */
3191 mb();
28912902 3192
523224a3 3193 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3194 bp->spq_prod_idx);
28912902
MC		 3195 mmiowb();
3196}
3197
619c5cb6
VZ		 3198/**
3199 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3200 *
3201 * @cmd: command to check
3202 * @cmd_type: command type
3203 */
3204static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3205{
3206 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3207 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3208 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3209 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3210 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3211 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3212 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3213 return true;
3214 else
3215 return false;
3216
3217}
3218
3219
3220/**
3221 * bnx2x_sp_post - place a single command on an SP ring
3222 *
3223 * @bp: driver handle
3224 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3225 * @cid: SW CID the command is related to
3226 * @data_hi: command private data address (high 32 bits)
3227 * @data_lo: command private data address (low 32 bits)
3228 * @cmd_type: command type (e.g. NONE, ETH)
3229 *
3230 * SP data is handled as if it's always an address pair, thus data fields are
3231 * not swapped to little endian in upper functions. Instead this function swaps
3232 * data as if it's two u32 fields.
3233 */
9f6c9258 3234int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3235 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3236{
28912902 3237 struct eth_spe *spe;
523224a3 3238 u16 type;
619c5cb6 3239 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3240
a2fbb9ea
ET		 3241#ifdef BNX2X_STOP_ON_ERROR
3242 if (unlikely(bp->panic))
3243 return -EIO;
3244#endif
3245
34f80b04 3246 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3247
6e30dd4e
VZ		 3248 if (common) {
3249 if (!atomic_read(&bp->eq_spq_left)) {
3250 BNX2X_ERR("BUG! EQ ring full!\n");
3251 spin_unlock_bh(&bp->spq_lock);
3252 bnx2x_panic();
3253 return -EBUSY;
3254 }
3255 } else if (!atomic_read(&bp->cq_spq_left)) {
3256 BNX2X_ERR("BUG! SPQ ring full!\n");
3257 spin_unlock_bh(&bp->spq_lock);
3258 bnx2x_panic();
3259 return -EBUSY;
a2fbb9ea 3260 }
f1410647 3261
28912902
MC		 3262 spe = bnx2x_sp_get_next(bp);
3263
a2fbb9ea 3264 /* CID needs port number to be encoded int it */
28912902 3265 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3266 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3267 HW_CID(bp, cid));
523224a3 3268
619c5cb6 3269 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3270
523224a3
DK		 3271 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3272 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3273
523224a3
DK		 3274 spe->hdr.type = cpu_to_le16(type);
3275
3276 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3277 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3278
d6cae238
VZ		 3279 /*
3280 * It's ok if the actual decrement is issued towards the memory
3281 * somewhere between the spin_lock and spin_unlock. Thus no
3282 * more explict memory barrier is needed.
3283 */
3284 if (common)
3285 atomic_dec(&bp->eq_spq_left);
3286 else
3287 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3288
a2fbb9ea 3289
cdaa7cb8 3290 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
d6cae238
VZ		 3291 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3292 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3293 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3294 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3295 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3296 HW_CID(bp, cid), data_hi, data_lo, type,
3297 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3298
28912902 3299 bnx2x_sp_prod_update(bp);
34f80b04 3300 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3301 return 0;
3302}
3303
3304/* acquire split MCP access lock register */
4a37fb66 3305static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3306{
72fd0718 3307 u32 j, val;
34f80b04 3308 int rc = 0;
a2fbb9ea
ET		 3309
3310 might_sleep();
72fd0718 3311 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3312 val = (1UL << 31);
3313 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3314 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3315 if (val & (1L << 31))
3316 break;
3317
3318 msleep(5);
3319 }
a2fbb9ea 3320 if (!(val & (1L << 31))) {
19680c48 3321 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3322 rc = -EBUSY;
3323 }
3324
3325 return rc;
3326}
3327
4a37fb66
YG		 3328/* release split MCP access lock register */
3329static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3330{
72fd0718 3331 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3332}
3333
523224a3
DK		 3334#define BNX2X_DEF_SB_ATT_IDX 0x0001
3335#define BNX2X_DEF_SB_IDX 0x0002
3336
a2fbb9ea
ET		 3337static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3338{
523224a3 3339 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3340 u16 rc = 0;
3341
3342 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3343 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3344 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3345 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3346 }
523224a3
DK		 3347
3348 if (bp->def_idx != def_sb->sp_sb.running_index) {
3349 bp->def_idx = def_sb->sp_sb.running_index;
3350 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3351 }
523224a3
DK		 3352
3353 /* Do not reorder: indecies reading should complete before handling */
3354 barrier();
a2fbb9ea
ET		 3355 return rc;
3356}
3357
3358/*
3359 * slow path service functions
3360 */
3361
3362static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3363{
34f80b04 3364 int port = BP_PORT(bp);
a2fbb9ea
ET		 3365 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3366 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3367 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3368 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3369 u32 aeu_mask;
87942b46 3370 u32 nig_mask = 0;
f2e0899f 3371 u32 reg_addr;
a2fbb9ea 3372
a2fbb9ea
ET		 3373 if (bp->attn_state & asserted)
3374 BNX2X_ERR("IGU ERROR\n");
3375
3fcaf2e5
EG		 3376 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3377 aeu_mask = REG_RD(bp, aeu_addr);
3378
a2fbb9ea 3379 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3380 aeu_mask, asserted);
72fd0718 3381 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3382 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3383
3fcaf2e5
EG		 3384 REG_WR(bp, aeu_addr, aeu_mask);
3385 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3386
3fcaf2e5 3387 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3388 bp->attn_state |= asserted;
3fcaf2e5 3389 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3390
3391 if (asserted & ATTN_HARD_WIRED_MASK) {
3392 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3393
a5e9a7cf
EG		 3394 bnx2x_acquire_phy_lock(bp);
3395
877e9aa4 3396 /* save nig interrupt mask */
87942b46 3397 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3398
361c391e
YR		 3399 /* If nig_mask is not set, no need to call the update
3400 * function.
3401 */
3402 if (nig_mask) {
3403 REG_WR(bp, nig_int_mask_addr, 0);
3404
3405 bnx2x_link_attn(bp);
3406 }
a2fbb9ea
ET		 3407
3408 /* handle unicore attn? */
3409 }
3410 if (asserted & ATTN_SW_TIMER_4_FUNC)
3411 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3412
3413 if (asserted & GPIO_2_FUNC)
3414 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3415
3416 if (asserted & GPIO_3_FUNC)
3417 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3418
3419 if (asserted & GPIO_4_FUNC)
3420 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3421
3422 if (port == 0) {
3423 if (asserted & ATTN_GENERAL_ATTN_1) {
3424 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3425 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3426 }
3427 if (asserted & ATTN_GENERAL_ATTN_2) {
3428 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3429 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3430 }
3431 if (asserted & ATTN_GENERAL_ATTN_3) {
3432 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3433 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3434 }
3435 } else {
3436 if (asserted & ATTN_GENERAL_ATTN_4) {
3437 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3438 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3439 }
3440 if (asserted & ATTN_GENERAL_ATTN_5) {
3441 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3442 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3443 }
3444 if (asserted & ATTN_GENERAL_ATTN_6) {
3445 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3446 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3447 }
3448 }
3449
3450 } /* if hardwired */
3451
f2e0899f
DK		 3452 if (bp->common.int_block == INT_BLOCK_HC)
3453 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3454 COMMAND_REG_ATTN_BITS_SET);
3455 else
3456 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3457
3458 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3459 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3460 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3461
3462 /* now set back the mask */
a5e9a7cf 3463 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 3464 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3465 bnx2x_release_phy_lock(bp);
3466 }
a2fbb9ea
ET		 3467}
3468
fd4ef40d
EG		 3469static inline void bnx2x_fan_failure(struct bnx2x *bp)
3470{
3471 int port = BP_PORT(bp);
b7737c9b 3472 u32 ext_phy_config;
fd4ef40d 3473 /* mark the failure */
b7737c9b
YR		 3474 ext_phy_config =
3475 SHMEM_RD(bp,
3476 dev_info.port_hw_config[port].external_phy_config);
3477
3478 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3479 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3480 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3481 ext_phy_config);
fd4ef40d
EG		 3482
3483 /* log the failure */
cdaa7cb8
VZ		 3484 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3485 " the driver to shutdown the card to prevent permanent"
3486 " damage. Please contact OEM Support for assistance\n");
8304859a
AE		 3487
3488 /*
3489 * Scheudle device reset (unload)
3490 * This is due to some boards consuming sufficient power when driver is
3491 * up to overheat if fan fails.
3492 */
3493 smp_mb__before_clear_bit();
3494 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3495 smp_mb__after_clear_bit();
3496 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3497
fd4ef40d 3498}
ab6ad5a4 3499
877e9aa4 3500static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3501{
34f80b04 3502 int port = BP_PORT(bp);
877e9aa4 3503 int reg_offset;
d90d96ba 3504 u32 val;
877e9aa4 3505
34f80b04
EG		 3506 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3507 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3508
34f80b04 3509 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3510
3511 val = REG_RD(bp, reg_offset);
3512 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3513 REG_WR(bp, reg_offset, val);
3514
3515 BNX2X_ERR("SPIO5 hw attention\n");
3516
fd4ef40d 3517 /* Fan failure attention */
d90d96ba 3518 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3519 bnx2x_fan_failure(bp);
877e9aa4 3520 }
34f80b04 3521
3deb8167 3522 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3523 bnx2x_acquire_phy_lock(bp);
3524 bnx2x_handle_module_detect_int(&bp->link_params);
3525 bnx2x_release_phy_lock(bp);
3526 }
3527
34f80b04
EG		 3528 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3529
3530 val = REG_RD(bp, reg_offset);
3531 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3532 REG_WR(bp, reg_offset, val);
3533
3534 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3535 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3536 bnx2x_panic();
3537 }
877e9aa4
ET		 3538}
3539
3540static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3541{
3542 u32 val;
3543
0626b899 3544 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3545
3546 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3547 BNX2X_ERR("DB hw attention 0x%x\n", val);
3548 /* DORQ discard attention */
3549 if (val & 0x2)
3550 BNX2X_ERR("FATAL error from DORQ\n");
3551 }
34f80b04
EG		 3552
3553 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3554
3555 int port = BP_PORT(bp);
3556 int reg_offset;
3557
3558 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3559 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3560
3561 val = REG_RD(bp, reg_offset);
3562 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3563 REG_WR(bp, reg_offset, val);
3564
3565 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3566 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3567 bnx2x_panic();
3568 }
877e9aa4
ET		 3569}
3570
3571static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3572{
3573 u32 val;
3574
3575 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3576
3577 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3578 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3579 /* CFC error attention */
3580 if (val & 0x2)
3581 BNX2X_ERR("FATAL error from CFC\n");
3582 }
3583
3584 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3585 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3586 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3587 /* RQ_USDMDP_FIFO_OVERFLOW */
3588 if (val & 0x18000)
3589 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3590
3591 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3592 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3593 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3594 }
877e9aa4 3595 }
34f80b04
EG		 3596
3597 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3598
3599 int port = BP_PORT(bp);
3600 int reg_offset;
3601
3602 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3603 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3604
3605 val = REG_RD(bp, reg_offset);
3606 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3607 REG_WR(bp, reg_offset, val);
3608
3609 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3610 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3611 bnx2x_panic();
3612 }
877e9aa4
ET		 3613}
3614
3615static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3616{
34f80b04
EG		 3617 u32 val;
3618
877e9aa4
ET		 3619 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3620
34f80b04
EG		 3621 if (attn & BNX2X_PMF_LINK_ASSERT) {
3622 int func = BP_FUNC(bp);
3623
3624 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3625 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3626 func_mf_config[BP_ABS_FUNC(bp)].config);
3627 val = SHMEM_RD(bp,
3628 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3629 if (val & DRV_STATUS_DCC_EVENT_MASK)
3630 bnx2x_dcc_event(bp,
3631 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3632
3633 if (val & DRV_STATUS_SET_MF_BW)
3634 bnx2x_set_mf_bw(bp);
3635
1d187b34
BW		 3636 if (val & DRV_STATUS_DRV_INFO_REQ)
3637 bnx2x_handle_drv_info_req(bp);
2691d51d 3638 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3639 bnx2x_pmf_update(bp);
3640
e4901dde 3641 if (bp->port.pmf &&
785b9b1a
SR		 3642 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3643 bp->dcbx_enabled > 0)
e4901dde
VZ		 3644 /* start dcbx state machine */
3645 bnx2x_dcbx_set_params(bp,
3646 BNX2X_DCBX_STATE_NEG_RECEIVED);
3deb8167
YR		 3647 if (bp->link_vars.periodic_flags &
3648 PERIODIC_FLAGS_LINK_EVENT) {
3649 /* sync with link */
3650 bnx2x_acquire_phy_lock(bp);
3651 bp->link_vars.periodic_flags &=
3652 ~PERIODIC_FLAGS_LINK_EVENT;
3653 bnx2x_release_phy_lock(bp);
3654 if (IS_MF(bp))
3655 bnx2x_link_sync_notify(bp);
3656 bnx2x_link_report(bp);
3657 }
3658 /* Always call it here: bnx2x_link_report() will
3659 * prevent the link indication duplication.
3660 */
3661 bnx2x__link_status_update(bp);
34f80b04 3662 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3663
3664 BNX2X_ERR("MC assert!\n");
d6cae238 3665 bnx2x_mc_assert(bp);
877e9aa4
ET		 3666 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3667 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3668 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3669 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3670 bnx2x_panic();
3671
3672 } else if (attn & BNX2X_MCP_ASSERT) {
3673
3674 BNX2X_ERR("MCP assert!\n");
3675 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3676 bnx2x_fw_dump(bp);
877e9aa4
ET		 3677
3678 } else
3679 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3680 }
3681
3682 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3683 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3684 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3685 val = CHIP_IS_E1(bp) ? 0 :
3686 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3687 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3688 }
3689 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3690 val = CHIP_IS_E1(bp) ? 0 :
3691 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3692 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3693 }
877e9aa4 3694 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3695 }
3696}
3697
c9ee9206
VZ		 3698/*
3699 * Bits map:
3700 * 0-7 - Engine0 load counter.
3701 * 8-15 - Engine1 load counter.
3702 * 16 - Engine0 RESET_IN_PROGRESS bit.
3703 * 17 - Engine1 RESET_IN_PROGRESS bit.
3704 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3705 * on the engine
3706 * 19 - Engine1 ONE_IS_LOADED.
3707 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3708 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3709 * just the one belonging to its engine).
3710 *
3711 */
3712#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3713
3714#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3715#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3716#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3717#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3718#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3719#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3720#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3721
3722/*
3723 * Set the GLOBAL_RESET bit.
3724 *
3725 * Should be run under rtnl lock
3726 */
3727void bnx2x_set_reset_global(struct bnx2x *bp)
3728{
f16da43b
AE		 3729 u32 val;
3730 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3731 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 3732 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 3733 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 3734}
3735
3736/*
3737 * Clear the GLOBAL_RESET bit.
3738 *
3739 * Should be run under rtnl lock
3740 */
3741static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3742{
f16da43b
AE		 3743 u32 val;
3744 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3745 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 3746 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 3747 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 3748}
f85582f8 3749
72fd0718 3750/*
c9ee9206
VZ		 3751 * Checks the GLOBAL_RESET bit.
3752 *
72fd0718
VZ		 3753 * should be run under rtnl lock
3754 */
c9ee9206
VZ		 3755static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3756{
3757 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3758
3759 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3760 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3761}
3762
3763/*
3764 * Clear RESET_IN_PROGRESS bit for the current engine.
3765 *
3766 * Should be run under rtnl lock
3767 */
72fd0718
VZ		 3768static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3769{
f16da43b 3770 u32 val;
c9ee9206
VZ		 3771 u32 bit = BP_PATH(bp) ?
3772 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 3773 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3774 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 3775
3776 /* Clear the bit */
3777 val &= ~bit;
3778 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 3779
3780 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 3781}
3782
3783/*
c9ee9206
VZ		 3784 * Set RESET_IN_PROGRESS for the current engine.
3785 *
72fd0718
VZ		 3786 * should be run under rtnl lock
3787 */
c9ee9206 3788void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 3789{
f16da43b 3790 u32 val;
c9ee9206
VZ		 3791 u32 bit = BP_PATH(bp) ?
3792 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 3793 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3794 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 3795
3796 /* Set the bit */
3797 val |= bit;
3798 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 3799 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 3800}
3801
3802/*
c9ee9206 3803 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 3804 * should be run under rtnl lock
3805 */
c9ee9206 3806bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 3807{
c9ee9206
VZ		 3808 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3809 u32 bit = engine ?
3810 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3811
3812 /* return false if bit is set */
3813 return (val & bit) ? false : true;
72fd0718
VZ		 3814}
3815
3816/*
889b9af3 3817 * set pf load for the current pf.
c9ee9206 3818 *
72fd0718
VZ		 3819 * should be run under rtnl lock
3820 */
889b9af3 3821void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 3822{
f16da43b 3823 u32 val1, val;
c9ee9206
VZ		 3824 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3825 BNX2X_PATH0_LOAD_CNT_MASK;
3826 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3827 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 3828
f16da43b
AE		 3829 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3830 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3831
72fd0718
VZ		 3832 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3833
c9ee9206
VZ		 3834 /* get the current counter value */
3835 val1 = (val & mask) >> shift;
3836
889b9af3
AE		 3837 /* set bit of that PF */
3838 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 3839
3840 /* clear the old value */
3841 val &= ~mask;
3842
3843 /* set the new one */
3844 val |= ((val1 << shift) & mask);
3845
3846 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 3847 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 3848}
3849
c9ee9206 3850/**
889b9af3 3851 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 3852 *
3853 * @bp: driver handle
3854 *
3855 * Should be run under rtnl lock.
3856 * Decrements the load counter for the current engine. Returns
889b9af3 3857 * whether other functions are still loaded
72fd0718 3858 */
889b9af3 3859bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 3860{
f16da43b 3861 u32 val1, val;
c9ee9206
VZ		 3862 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3863 BNX2X_PATH0_LOAD_CNT_MASK;
3864 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3865 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 3866
f16da43b
AE		 3867 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3868 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
72fd0718
VZ		 3869 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3870
c9ee9206
VZ		 3871 /* get the current counter value */
3872 val1 = (val & mask) >> shift;
3873
889b9af3
AE		 3874 /* clear bit of that PF */
3875 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 3876
3877 /* clear the old value */
3878 val &= ~mask;
3879
3880 /* set the new one */
3881 val |= ((val1 << shift) & mask);
3882
3883 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 3884 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3885 return val1 != 0;
72fd0718
VZ		 3886}
3887
3888/*
889b9af3 3889 * Read the load status for the current engine.
c9ee9206 3890 *
72fd0718
VZ		 3891 * should be run under rtnl lock
3892 */
889b9af3 3893static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 3894{
c9ee9206
VZ		 3895 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3896 BNX2X_PATH0_LOAD_CNT_MASK);
3897 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3898 BNX2X_PATH0_LOAD_CNT_SHIFT);
3899 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3900
3901 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3902
3903 val = (val & mask) >> shift;
3904
889b9af3 3905 DP(NETIF_MSG_HW, "load mask for engine %d = 0x%x\n", engine, val);
c9ee9206 3906
889b9af3 3907 return val != 0;
72fd0718
VZ		 3908}
3909
c9ee9206 3910/*
889b9af3 3911 * Reset the load status for the current engine.
c9ee9206 3912 */
889b9af3 3913static inline void bnx2x_clear_load_status(struct bnx2x *bp)
72fd0718 3914{
f16da43b 3915 u32 val;
c9ee9206 3916 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
f16da43b
AE		 3917 BNX2X_PATH0_LOAD_CNT_MASK);
3918 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3919 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 3920 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
f16da43b 3921 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 3922}
3923
3924static inline void _print_next_block(int idx, const char *blk)
3925{
f1deab50 3926 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 3927}
3928
c9ee9206
VZ		 3929static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3930 bool print)
72fd0718
VZ		 3931{
3932 int i = 0;
3933 u32 cur_bit = 0;
3934 for (i = 0; sig; i++) {
3935 cur_bit = ((u32)0x1 << i);
3936 if (sig & cur_bit) {
3937 switch (cur_bit) {
3938 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 3939 if (print)
3940 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 3941 break;
3942 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 3943 if (print)
3944 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 3945 break;
3946 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 3947 if (print)
3948 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 3949 break;
3950 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 3951 if (print)
3952 _print_next_block(par_num++,
3953 "SEARCHER");
3954 break;
3955 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3956 if (print)
3957 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 3958 break;
3959 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 3960 if (print)
3961 _print_next_block(par_num++, "TSEMI");
3962 break;
3963 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3964 if (print)
3965 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 3966 break;
3967 }
3968
3969 /* Clear the bit */
3970 sig &= ~cur_bit;
3971 }
3972 }
3973
3974 return par_num;
3975}
3976
c9ee9206
VZ		 3977static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3978 bool *global, bool print)
72fd0718
VZ		 3979{
3980 int i = 0;
3981 u32 cur_bit = 0;
3982 for (i = 0; sig; i++) {
3983 cur_bit = ((u32)0x1 << i);
3984 if (sig & cur_bit) {
3985 switch (cur_bit) {
c9ee9206
VZ		 3986 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3987 if (print)
3988 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 3989 break;
3990 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 3991 if (print)
3992 _print_next_block(par_num++, "QM");
3993 break;
3994 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3995 if (print)
3996 _print_next_block(par_num++, "TM");
72fd0718
VZ		 3997 break;
3998 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 3999 if (print)
4000 _print_next_block(par_num++, "XSDM");
4001 break;
4002 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4003 if (print)
4004 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 4005 break;
4006 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 4007 if (print)
4008 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 4009 break;
4010 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 4011 if (print)
4012 _print_next_block(par_num++,
4013 "DOORBELLQ");
4014 break;
4015 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4016 if (print)
4017 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 4018 break;
4019 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 4020 if (print)
4021 _print_next_block(par_num++,
4022 "VAUX PCI CORE");
4023 *global = true;
72fd0718
VZ		 4024 break;
4025 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 4026 if (print)
4027 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 4028 break;
4029 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 4030 if (print)
4031 _print_next_block(par_num++, "USDM");
72fd0718 4032 break;
8736c826
VZ		 4033 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4034 if (print)
4035 _print_next_block(par_num++, "UCM");
4036 break;
72fd0718 4037 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 4038 if (print)
4039 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 4040 break;
4041 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 4042 if (print)
4043 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 4044 break;
4045 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 4046 if (print)
4047 _print_next_block(par_num++, "CSDM");
72fd0718 4048 break;
8736c826
VZ		 4049 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4050 if (print)
4051 _print_next_block(par_num++, "CCM");
4052 break;
72fd0718
VZ		 4053 }
4054
4055 /* Clear the bit */
4056 sig &= ~cur_bit;
4057 }
4058 }
4059
4060 return par_num;
4061}
4062
c9ee9206
VZ		 4063static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4064 bool print)
72fd0718
VZ		 4065{
4066 int i = 0;
4067 u32 cur_bit = 0;
4068 for (i = 0; sig; i++) {
4069 cur_bit = ((u32)0x1 << i);
4070 if (sig & cur_bit) {
4071 switch (cur_bit) {
4072 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 4073 if (print)
4074 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 4075 break;
4076 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 4077 if (print)
4078 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 4079 break;
4080 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 4081 if (print)
4082 _print_next_block(par_num++,
72fd0718
VZ		 4083 "PXPPCICLOCKCLIENT");
4084 break;
4085 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 4086 if (print)
4087 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 4088 break;
4089 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 4090 if (print)
4091 _print_next_block(par_num++, "CDU");
4092 break;
4093 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4094 if (print)
4095 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 4096 break;
4097 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 4098 if (print)
4099 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 4100 break;
4101 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 4102 if (print)
4103 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 4104 break;
4105 }
4106
4107 /* Clear the bit */
4108 sig &= ~cur_bit;
4109 }
4110 }
4111
4112 return par_num;
4113}
4114
c9ee9206
VZ		 4115static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4116 bool *global, bool print)
72fd0718
VZ		 4117{
4118 int i = 0;
4119 u32 cur_bit = 0;
4120 for (i = 0; sig; i++) {
4121 cur_bit = ((u32)0x1 << i);
4122 if (sig & cur_bit) {
4123 switch (cur_bit) {
4124 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 4125 if (print)
4126 _print_next_block(par_num++, "MCP ROM");
4127 *global = true;
72fd0718
VZ		 4128 break;
4129 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 4130 if (print)
4131 _print_next_block(par_num++,
4132 "MCP UMP RX");
4133 *global = true;
72fd0718
VZ		 4134 break;
4135 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 4136 if (print)
4137 _print_next_block(par_num++,
4138 "MCP UMP TX");
4139 *global = true;
72fd0718
VZ		 4140 break;
4141 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 4142 if (print)
4143 _print_next_block(par_num++,
4144 "MCP SCPAD");
4145 *global = true;
72fd0718
VZ		 4146 break;
4147 }
4148
4149 /* Clear the bit */
4150 sig &= ~cur_bit;
4151 }
4152 }
4153
4154 return par_num;
4155}
4156
8736c826
VZ		 4157static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4158 bool print)
4159{
4160 int i = 0;
4161 u32 cur_bit = 0;
4162 for (i = 0; sig; i++) {
4163 cur_bit = ((u32)0x1 << i);
4164 if (sig & cur_bit) {
4165 switch (cur_bit) {
4166 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4167 if (print)
4168 _print_next_block(par_num++, "PGLUE_B");
4169 break;
4170 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4171 if (print)
4172 _print_next_block(par_num++, "ATC");
4173 break;
4174 }
4175
4176 /* Clear the bit */
4177 sig &= ~cur_bit;
4178 }
4179 }
4180
4181 return par_num;
4182}
4183
c9ee9206 4184static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
8736c826 4185 u32 *sig)
72fd0718 4186{
8736c826
VZ		 4187 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4188 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4189 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4190 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4191 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718
VZ		 4192 int par_num = 0;
4193 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
8736c826
VZ		 4194 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4195 "[4]:0x%08x\n",
4196 sig[0] & HW_PRTY_ASSERT_SET_0,
4197 sig[1] & HW_PRTY_ASSERT_SET_1,
4198 sig[2] & HW_PRTY_ASSERT_SET_2,
4199 sig[3] & HW_PRTY_ASSERT_SET_3,
4200 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4201 if (print)
4202 netdev_err(bp->dev,
4203 "Parity errors detected in blocks: ");
4204 par_num = bnx2x_check_blocks_with_parity0(
8736c826 4205 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
c9ee9206 4206 par_num = bnx2x_check_blocks_with_parity1(
8736c826 4207 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
c9ee9206 4208 par_num = bnx2x_check_blocks_with_parity2(
8736c826 4209 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
c9ee9206 4210 par_num = bnx2x_check_blocks_with_parity3(
8736c826
VZ		 4211 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4212 par_num = bnx2x_check_blocks_with_parity4(
4213 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4214
c9ee9206
VZ		 4215 if (print)
4216 pr_cont("\n");
8736c826 4217
72fd0718
VZ		 4218 return true;
4219 } else
4220 return false;
4221}
4222
c9ee9206
VZ		 4223/**
4224 * bnx2x_chk_parity_attn - checks for parity attentions.
4225 *
4226 * @bp: driver handle
4227 * @global: true if there was a global attention
4228 * @print: show parity attention in syslog
4229 */
4230bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4231{
8736c826 4232 struct attn_route attn = { {0} };
72fd0718
VZ		 4233 int port = BP_PORT(bp);
4234
4235 attn.sig[0] = REG_RD(bp,
4236 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4237 port*4);
4238 attn.sig[1] = REG_RD(bp,
4239 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4240 port*4);
4241 attn.sig[2] = REG_RD(bp,
4242 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4243 port*4);
4244 attn.sig[3] = REG_RD(bp,
4245 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4246 port*4);
4247
8736c826
VZ		 4248 if (!CHIP_IS_E1x(bp))
4249 attn.sig[4] = REG_RD(bp,
4250 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4251 port*4);
4252
4253 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4254}
4255
f2e0899f
DK		 4256
4257static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4258{
4259 u32 val;
4260 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4261
4262 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4263 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4264 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4265 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4266 "ADDRESS_ERROR\n");
4267 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4268 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4269 "INCORRECT_RCV_BEHAVIOR\n");
4270 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4271 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4272 "WAS_ERROR_ATTN\n");
4273 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4274 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4275 "VF_LENGTH_VIOLATION_ATTN\n");
4276 if (val &
4277 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4278 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4279 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4280 if (val &
4281 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4282 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4283 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4284 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4285 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4286 "TCPL_ERROR_ATTN\n");
4287 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4288 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4289 "TCPL_IN_TWO_RCBS_ATTN\n");
4290 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4291 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4292 "CSSNOOP_FIFO_OVERFLOW\n");
4293 }
4294 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4295 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4296 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4297 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4298 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4299 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4300 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4301 "_ATC_TCPL_TO_NOT_PEND\n");
4302 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4303 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4304 "ATC_GPA_MULTIPLE_HITS\n");
4305 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4306 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4307 "ATC_RCPL_TO_EMPTY_CNT\n");
4308 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4309 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4310 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4311 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4312 "ATC_IREQ_LESS_THAN_STU\n");
4313 }
4314
4315 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4316 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4317 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4318 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4319 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4320 }
4321
4322}
4323
72fd0718
VZ		 4324static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4325{
4326 struct attn_route attn, *group_mask;
34f80b04 4327 int port = BP_PORT(bp);
877e9aa4 4328 int index;
a2fbb9ea
ET		 4329 u32 reg_addr;
4330 u32 val;
3fcaf2e5 4331 u32 aeu_mask;
c9ee9206 4332 bool global = false;
a2fbb9ea
ET		 4333
4334 /* need to take HW lock because MCP or other port might also
4335 try to handle this event */
4a37fb66 4336 bnx2x_acquire_alr(bp);
a2fbb9ea 4337
c9ee9206
VZ		 4338 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4339#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4340 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4341 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4342 /* Disable HW interrupts */
4343 bnx2x_int_disable(bp);
72fd0718
VZ		 4344 /* In case of parity errors don't handle attentions so that
4345 * other function would "see" parity errors.
4346 */
c9ee9206
VZ		 4347#else
4348 bnx2x_panic();
4349#endif
4350 bnx2x_release_alr(bp);
72fd0718
VZ		 4351 return;
4352 }
4353
a2fbb9ea
ET		 4354 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4355 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4356 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4357 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4358 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4359 attn.sig[4] =
4360 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4361 else
4362 attn.sig[4] = 0;
4363
4364 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4365 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4366
4367 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4368 if (deasserted & (1 << index)) {
72fd0718 4369 group_mask = &bp->attn_group[index];
a2fbb9ea 4370
f2e0899f
DK		 4371 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4372 "%08x %08x %08x\n",
4373 index,
4374 group_mask->sig[0], group_mask->sig[1],
4375 group_mask->sig[2], group_mask->sig[3],
4376 group_mask->sig[4]);
a2fbb9ea 4377
f2e0899f
DK		 4378 bnx2x_attn_int_deasserted4(bp,
4379 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4380 bnx2x_attn_int_deasserted3(bp,
72fd0718 4381 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4382 bnx2x_attn_int_deasserted1(bp,
72fd0718 4383 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4384 bnx2x_attn_int_deasserted2(bp,
72fd0718 4385 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4386 bnx2x_attn_int_deasserted0(bp,
72fd0718 4387 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4388 }
4389 }
4390
4a37fb66 4391 bnx2x_release_alr(bp);
a2fbb9ea 4392
f2e0899f
DK		 4393 if (bp->common.int_block == INT_BLOCK_HC)
4394 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4395 COMMAND_REG_ATTN_BITS_CLR);
4396 else
4397 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4398
4399 val = ~deasserted;
f2e0899f
DK		 4400 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4401 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4402 REG_WR(bp, reg_addr, val);
a2fbb9ea 4403
a2fbb9ea 4404 if (~bp->attn_state & deasserted)
3fcaf2e5 4405 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4406
4407 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4408 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4409
3fcaf2e5
EG		 4410 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4411 aeu_mask = REG_RD(bp, reg_addr);
4412
4413 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4414 aeu_mask, deasserted);
72fd0718 4415 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4416 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4417
3fcaf2e5
EG		 4418 REG_WR(bp, reg_addr, aeu_mask);
4419 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4420
4421 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4422 bp->attn_state &= ~deasserted;
4423 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4424}
4425
4426static void bnx2x_attn_int(struct bnx2x *bp)
4427{
4428 /* read local copy of bits */
68d59484
EG		 4429 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4430 attn_bits);
4431 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4432 attn_bits_ack);
a2fbb9ea
ET		 4433 u32 attn_state = bp->attn_state;
4434
4435 /* look for changed bits */
4436 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4437 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4438
4439 DP(NETIF_MSG_HW,
4440 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4441 attn_bits, attn_ack, asserted, deasserted);
4442
4443 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4444 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4445
4446 /* handle bits that were raised */
4447 if (asserted)
4448 bnx2x_attn_int_asserted(bp, asserted);
4449
4450 if (deasserted)
4451 bnx2x_attn_int_deasserted(bp, deasserted);
4452}
4453
619c5cb6
VZ		 4454void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4455 u16 index, u8 op, u8 update)
4456{
4457 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4458
4459 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4460 igu_addr);
4461}
4462
523224a3
DK		 4463static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4464{
4465 /* No memory barriers */
4466 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4467 mmiowb(); /* keep prod updates ordered */
4468}
4469
4470#ifdef BCM_CNIC
4471static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4472 union event_ring_elem *elem)
4473{
619c5cb6
VZ		 4474 u8 err = elem->message.error;
4475
523224a3 4476 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4477 (cid < bp->cnic_eth_dev.starting_cid &&
4478 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4479 return 1;
4480
4481 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4482
619c5cb6
VZ		 4483 if (unlikely(err)) {
4484
523224a3
DK		 4485 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4486 cid);
4487 bnx2x_panic_dump(bp);
4488 }
619c5cb6 4489 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4490 return 0;
4491}
4492#endif
4493
619c5cb6
VZ		 4494static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4495{
4496 struct bnx2x_mcast_ramrod_params rparam;
4497 int rc;
4498
4499 memset(&rparam, 0, sizeof(rparam));
4500
4501 rparam.mcast_obj = &bp->mcast_obj;
4502
4503 netif_addr_lock_bh(bp->dev);
4504
4505 /* Clear pending state for the last command */
4506 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4507
4508 /* If there are pending mcast commands - send them */
4509 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4510 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4511 if (rc < 0)
4512 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4513 rc);
4514 }
4515
4516 netif_addr_unlock_bh(bp->dev);
4517}
4518
4519static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4520 union event_ring_elem *elem)
4521{
4522 unsigned long ramrod_flags = 0;
4523 int rc = 0;
4524 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4525 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4526
4527 /* Always push next commands out, don't wait here */
4528 __set_bit(RAMROD_CONT, &ramrod_flags);
4529
4530 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4531 case BNX2X_FILTER_MAC_PENDING:
4532#ifdef BCM_CNIC
4533 if (cid == BNX2X_ISCSI_ETH_CID)
4534 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4535 else
4536#endif
4537 vlan_mac_obj = &bp->fp[cid].mac_obj;
4538
4539 break;
619c5cb6
VZ		 4540 case BNX2X_FILTER_MCAST_PENDING:
4541 /* This is only relevant for 57710 where multicast MACs are
4542 * configured as unicast MACs using the same ramrod.
4543 */
4544 bnx2x_handle_mcast_eqe(bp);
4545 return;
4546 default:
4547 BNX2X_ERR("Unsupported classification command: %d\n",
4548 elem->message.data.eth_event.echo);
4549 return;
4550 }
4551
4552 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4553
4554 if (rc < 0)
4555 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4556 else if (rc > 0)
4557 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4558
4559}
4560
4561#ifdef BCM_CNIC
4562static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4563#endif
4564
4565static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4566{
4567 netif_addr_lock_bh(bp->dev);
4568
4569 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4570
4571 /* Send rx_mode command again if was requested */
4572 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4573 bnx2x_set_storm_rx_mode(bp);
4574#ifdef BCM_CNIC
4575 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4576 &bp->sp_state))
4577 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4578 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4579 &bp->sp_state))
4580 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4581#endif
4582
4583 netif_addr_unlock_bh(bp->dev);
4584}
4585
4586static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4587 struct bnx2x *bp, u32 cid)
4588{
94f05b0f 4589 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
619c5cb6
VZ		 4590#ifdef BCM_CNIC
4591 if (cid == BNX2X_FCOE_ETH_CID)
4592 return &bnx2x_fcoe(bp, q_obj);
4593 else
4594#endif
6383c0b3 4595 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
619c5cb6
VZ		 4596}
4597
523224a3
DK		 4598static void bnx2x_eq_int(struct bnx2x *bp)
4599{
4600 u16 hw_cons, sw_cons, sw_prod;
4601 union event_ring_elem *elem;
4602 u32 cid;
4603 u8 opcode;
4604 int spqe_cnt = 0;
619c5cb6
VZ		 4605 struct bnx2x_queue_sp_obj *q_obj;
4606 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4607 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4608
4609 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4610
4611 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4612 * when we get the the next-page we nned to adjust so the loop
4613 * condition below will be met. The next element is the size of a
4614 * regular element and hence incrementing by 1
4615 */
4616 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4617 hw_cons++;
4618
25985edc 4619 /* This function may never run in parallel with itself for a
523224a3
DK		 4620 * specific bp, thus there is no need in "paired" read memory
4621 * barrier here.
4622 */
4623 sw_cons = bp->eq_cons;
4624 sw_prod = bp->eq_prod;
4625
d6cae238 4626 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 4627 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4628
4629 for (; sw_cons != hw_cons;
4630 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4631
4632
4633 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4634
4635 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4636 opcode = elem->message.opcode;
4637
4638
4639 /* handle eq element */
4640 switch (opcode) {
4641 case EVENT_RING_OPCODE_STAT_QUERY:
619c5cb6
VZ		 4642 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4643 bp->stats_comp++);
523224a3 4644 /* nothing to do with stats comp */
d6cae238 4645 goto next_spqe;
523224a3
DK		 4646
4647 case EVENT_RING_OPCODE_CFC_DEL:
4648 /* handle according to cid range */
4649 /*
4650 * we may want to verify here that the bp state is
4651 * HALTING
4652 */
d6cae238 4653 DP(BNX2X_MSG_SP,
523224a3
DK		 4654 "got delete ramrod for MULTI[%d]\n", cid);
4655#ifdef BCM_CNIC
4656 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4657 goto next_spqe;
4658#endif
619c5cb6
VZ		 4659 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4660
4661 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4662 break;
4663
4664
523224a3
DK		 4665
4666 goto next_spqe;
e4901dde
VZ		 4667
4668 case EVENT_RING_OPCODE_STOP_TRAFFIC:
d6cae238 4669 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
6debea87
DK		 4670 if (f_obj->complete_cmd(bp, f_obj,
4671 BNX2X_F_CMD_TX_STOP))
4672 break;
e4901dde
VZ		 4673 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4674 goto next_spqe;
619c5cb6 4675
e4901dde 4676 case EVENT_RING_OPCODE_START_TRAFFIC:
d6cae238 4677 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
6debea87
DK		 4678 if (f_obj->complete_cmd(bp, f_obj,
4679 BNX2X_F_CMD_TX_START))
4680 break;
e4901dde
VZ		 4681 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4682 goto next_spqe;
619c5cb6 4683 case EVENT_RING_OPCODE_FUNCTION_START:
d6cae238 4684 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
619c5cb6
VZ		 4685 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4686 break;
4687
4688 goto next_spqe;
4689
4690 case EVENT_RING_OPCODE_FUNCTION_STOP:
d6cae238 4691 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 4692 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4693 break;
4694
4695 goto next_spqe;
523224a3
DK		 4696 }
4697
4698 switch (opcode | bp->state) {
619c5cb6
VZ		 4699 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4700 BNX2X_STATE_OPEN):
4701 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 4702 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 4703 cid = elem->message.data.eth_event.echo &
4704 BNX2X_SWCID_MASK;
d6cae238 4705 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 4706 cid);
4707 rss_raw->clear_pending(rss_raw);
523224a3
DK		 4708 break;
4709
619c5cb6
VZ		 4710 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4711 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4712 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 4713 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4714 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4715 BNX2X_STATE_OPEN):
4716 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4717 BNX2X_STATE_DIAG):
4718 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4719 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4720 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 4721 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 4722 break;
4723
619c5cb6
VZ		 4724 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4725 BNX2X_STATE_OPEN):
4726 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4727 BNX2X_STATE_DIAG):
4728 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4729 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4730 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 4731 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 4732 break;
4733
619c5cb6
VZ		 4734 case (EVENT_RING_OPCODE_FILTERS_RULES |
4735 BNX2X_STATE_OPEN):
4736 case (EVENT_RING_OPCODE_FILTERS_RULES |
4737 BNX2X_STATE_DIAG):
4738 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 4739 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4740 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 4741 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 4742 break;
4743 default:
4744 /* unknown event log error and continue */
619c5cb6
VZ		 4745 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4746 elem->message.opcode, bp->state);
523224a3
DK		 4747 }
4748next_spqe:
4749 spqe_cnt++;
4750 } /* for */
4751
8fe23fbd 4752 smp_mb__before_atomic_inc();
6e30dd4e 4753 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 4754
4755 bp->eq_cons = sw_cons;
4756 bp->eq_prod = sw_prod;
4757 /* Make sure that above mem writes were issued towards the memory */
4758 smp_wmb();
4759
4760 /* update producer */
4761 bnx2x_update_eq_prod(bp, bp->eq_prod);
4762}
4763
a2fbb9ea
ET		 4764static void bnx2x_sp_task(struct work_struct *work)
4765{
1cf167f2 4766 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 4767 u16 status;
4768
a2fbb9ea 4769 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 4770/* if (status == 0) */
4771/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 4772
cdaa7cb8 4773 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 4774
877e9aa4 4775 /* HW attentions */
523224a3 4776 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 4777 bnx2x_attn_int(bp);
523224a3 4778 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 4779 }
4780
523224a3
DK		 4781 /* SP events: STAT_QUERY and others */
4782 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 4783#ifdef BCM_CNIC
4784 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 4785
ec6ba945 4786 if ((!NO_FCOE(bp)) &&
019dbb4c
VZ		 4787 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4788 /*
4789 * Prevent local bottom-halves from running as
4790 * we are going to change the local NAPI list.
4791 */
4792 local_bh_disable();
ec6ba945 4793 napi_schedule(&bnx2x_fcoe(bp, napi));
019dbb4c
VZ		 4794 local_bh_enable();
4795 }
ec6ba945 4796#endif
523224a3
DK		 4797 /* Handle EQ completions */
4798 bnx2x_eq_int(bp);
4799
4800 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4801 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4802
4803 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 4804 }
4805
4806 if (unlikely(status))
4807 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4808 status);
a2fbb9ea 4809
523224a3
DK		 4810 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4811 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 4812}
4813
9f6c9258 4814irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 4815{
4816 struct net_device *dev = dev_instance;
4817 struct bnx2x *bp = netdev_priv(dev);
4818
523224a3
DK		 4819 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4820 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 4821
4822#ifdef BNX2X_STOP_ON_ERROR
4823 if (unlikely(bp->panic))
4824 return IRQ_HANDLED;
4825#endif
4826
993ac7b5
MC		 4827#ifdef BCM_CNIC
4828 {
4829 struct cnic_ops *c_ops;
4830
4831 rcu_read_lock();
4832 c_ops = rcu_dereference(bp->cnic_ops);
4833 if (c_ops)
4834 c_ops->cnic_handler(bp->cnic_data, NULL);
4835 rcu_read_unlock();
4836 }
4837#endif
1cf167f2 4838 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 4839
4840 return IRQ_HANDLED;
4841}
4842
4843/* end of slow path */
4844
619c5cb6
VZ		 4845
4846void bnx2x_drv_pulse(struct bnx2x *bp)
4847{
4848 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4849 bp->fw_drv_pulse_wr_seq);
4850}
4851
4852
a2fbb9ea
ET		 4853static void bnx2x_timer(unsigned long data)
4854{
6383c0b3 4855 u8 cos;
a2fbb9ea
ET		 4856 struct bnx2x *bp = (struct bnx2x *) data;
4857
4858 if (!netif_running(bp->dev))
4859 return;
4860
a2fbb9ea
ET		 4861 if (poll) {
4862 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 4863
6383c0b3
AE		 4864 for_each_cos_in_tx_queue(fp, cos)
4865 bnx2x_tx_int(bp, &fp->txdata[cos]);
b8ee8328 4866 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 4867 }
4868
34f80b04 4869 if (!BP_NOMCP(bp)) {
f2e0899f 4870 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 4871 u32 drv_pulse;
4872 u32 mcp_pulse;
4873
4874 ++bp->fw_drv_pulse_wr_seq;
4875 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4876 /* TBD - add SYSTEM_TIME */
4877 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 4878 bnx2x_drv_pulse(bp);
a2fbb9ea 4879
f2e0899f 4880 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 4881 MCP_PULSE_SEQ_MASK);
4882 /* The delta between driver pulse and mcp response
4883 * should be 1 (before mcp response) or 0 (after mcp response)
4884 */
4885 if ((drv_pulse != mcp_pulse) &&
4886 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4887 /* someone lost a heartbeat... */
4888 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4889 drv_pulse, mcp_pulse);
4890 }
4891 }
4892
f34d28ea 4893 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 4894 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 4895
a2fbb9ea
ET		 4896 mod_timer(&bp->timer, jiffies + bp->current_interval);
4897}
4898
4899/* end of Statistics */
4900
4901/* nic init */
4902
4903/*
4904 * nic init service functions
4905 */
4906
523224a3 4907static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 4908{
523224a3
DK		 4909 u32 i;
4910 if (!(len%4) && !(addr%4))
4911 for (i = 0; i < len; i += 4)
4912 REG_WR(bp, addr + i, fill);
4913 else
4914 for (i = 0; i < len; i++)
4915 REG_WR8(bp, addr + i, fill);
34f80b04 4916
34f80b04
EG		 4917}
4918
523224a3
DK		 4919/* helper: writes FP SP data to FW - data_size in dwords */
4920static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4921 int fw_sb_id,
4922 u32 *sb_data_p,
4923 u32 data_size)
34f80b04 4924{
a2fbb9ea 4925 int index;
523224a3
DK		 4926 for (index = 0; index < data_size; index++)
4927 REG_WR(bp, BAR_CSTRORM_INTMEM +
4928 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4929 sizeof(u32)*index,
4930 *(sb_data_p + index));
4931}
a2fbb9ea 4932
523224a3
DK		 4933static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4934{
4935 u32 *sb_data_p;
4936 u32 data_size = 0;
f2e0899f 4937 struct hc_status_block_data_e2 sb_data_e2;
523224a3 4938 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 4939
523224a3 4940 /* disable the function first */
619c5cb6 4941 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4942 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4943 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 4944 sb_data_e2.common.p_func.vf_valid = false;
4945 sb_data_p = (u32 *)&sb_data_e2;
4946 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4947 } else {
4948 memset(&sb_data_e1x, 0,
4949 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4950 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 4951 sb_data_e1x.common.p_func.vf_valid = false;
4952 sb_data_p = (u32 *)&sb_data_e1x;
4953 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4954 }
523224a3 4955 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4956
523224a3
DK		 4957 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4958 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4959 CSTORM_STATUS_BLOCK_SIZE);
4960 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4961 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4962 CSTORM_SYNC_BLOCK_SIZE);
4963}
34f80b04 4964
523224a3
DK		 4965/* helper: writes SP SB data to FW */
4966static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4967 struct hc_sp_status_block_data *sp_sb_data)
4968{
4969 int func = BP_FUNC(bp);
4970 int i;
4971 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4972 REG_WR(bp, BAR_CSTRORM_INTMEM +
4973 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4974 i*sizeof(u32),
4975 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4976}
4977
523224a3 4978static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4979{
4980 int func = BP_FUNC(bp);
523224a3
DK		 4981 struct hc_sp_status_block_data sp_sb_data;
4982 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4983
619c5cb6 4984 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 4985 sp_sb_data.p_func.vf_valid = false;
4986
4987 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4988
4989 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4990 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4991 CSTORM_SP_STATUS_BLOCK_SIZE);
4992 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4993 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4994 CSTORM_SP_SYNC_BLOCK_SIZE);
4995
4996}
4997
4998
4999static inline
5000void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5001 int igu_sb_id, int igu_seg_id)
5002{
5003 hc_sm->igu_sb_id = igu_sb_id;
5004 hc_sm->igu_seg_id = igu_seg_id;
5005 hc_sm->timer_value = 0xFF;
5006 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5007}
5008
150966ad
AE		 5009
5010/* allocates state machine ids. */
5011static inline
5012void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5013{
5014 /* zero out state machine indices */
5015 /* rx indices */
5016 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5017
5018 /* tx indices */
5019 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5020 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5021 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5022 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5023
5024 /* map indices */
5025 /* rx indices */
5026 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5027 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5028
5029 /* tx indices */
5030 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5031 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5032 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5033 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5034 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5035 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5036 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5037 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5038}
5039
8d96286a 5040static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5041 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5042{
523224a3
DK		 5043 int igu_seg_id;
5044
f2e0899f 5045 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5046 struct hc_status_block_data_e1x sb_data_e1x;
5047 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5048 int data_size;
5049 u32 *sb_data_p;
5050
f2e0899f
DK		 5051 if (CHIP_INT_MODE_IS_BC(bp))
5052 igu_seg_id = HC_SEG_ACCESS_NORM;
5053 else
5054 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5055
5056 bnx2x_zero_fp_sb(bp, fw_sb_id);
5057
619c5cb6 5058 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5059 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5060 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5061 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5062 sb_data_e2.common.p_func.vf_id = vfid;
5063 sb_data_e2.common.p_func.vf_valid = vf_valid;
5064 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5065 sb_data_e2.common.same_igu_sb_1b = true;
5066 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5067 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5068 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5069 sb_data_p = (u32 *)&sb_data_e2;
5070 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5071 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5072 } else {
5073 memset(&sb_data_e1x, 0,
5074 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5075 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5076 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5077 sb_data_e1x.common.p_func.vf_id = 0xff;
5078 sb_data_e1x.common.p_func.vf_valid = false;
5079 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5080 sb_data_e1x.common.same_igu_sb_1b = true;
5081 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5082 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5083 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5084 sb_data_p = (u32 *)&sb_data_e1x;
5085 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5086 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5087 }
523224a3
DK		 5088
5089 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5090 igu_sb_id, igu_seg_id);
5091 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5092 igu_sb_id, igu_seg_id);
5093
5094 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
5095
5096 /* write indecies to HW */
5097 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5098}
5099
619c5cb6 5100static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5101 u16 tx_usec, u16 rx_usec)
5102{
6383c0b3 5103 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5104 false, rx_usec);
6383c0b3
AE		 5105 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5106 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5107 tx_usec);
5108 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5109 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5110 tx_usec);
5111 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5112 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5113 tx_usec);
523224a3 5114}
f2e0899f 5115
523224a3
DK		 5116static void bnx2x_init_def_sb(struct bnx2x *bp)
5117{
5118 struct host_sp_status_block *def_sb = bp->def_status_blk;
5119 dma_addr_t mapping = bp->def_status_blk_mapping;
5120 int igu_sp_sb_index;
5121 int igu_seg_id;
34f80b04
EG		 5122 int port = BP_PORT(bp);
5123 int func = BP_FUNC(bp);
f2eaeb58 5124 int reg_offset, reg_offset_en5;
a2fbb9ea 5125 u64 section;
523224a3
DK		 5126 int index;
5127 struct hc_sp_status_block_data sp_sb_data;
5128 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5129
f2e0899f
DK		 5130 if (CHIP_INT_MODE_IS_BC(bp)) {
5131 igu_sp_sb_index = DEF_SB_IGU_ID;
5132 igu_seg_id = HC_SEG_ACCESS_DEF;
5133 } else {
5134 igu_sp_sb_index = bp->igu_dsb_id;
5135 igu_seg_id = IGU_SEG_ACCESS_DEF;
5136 }
a2fbb9ea
ET		 5137
5138 /* ATTN */
523224a3 5139 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5140 atten_status_block);
523224a3 5141 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5142
49d66772
ET		 5143 bp->attn_state = 0;
5144
a2fbb9ea
ET		 5145 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5146 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5147 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5148 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5149 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5150 int sindex;
5151 /* take care of sig[0]..sig[4] */
5152 for (sindex = 0; sindex < 4; sindex++)
5153 bp->attn_group[index].sig[sindex] =
5154 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5155
619c5cb6 5156 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5157 /*
5158 * enable5 is separate from the rest of the registers,
5159 * and therefore the address skip is 4
5160 * and not 16 between the different groups
5161 */
5162 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5163 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5164 else
5165 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5166 }
5167
f2e0899f
DK		 5168 if (bp->common.int_block == INT_BLOCK_HC) {
5169 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5170 HC_REG_ATTN_MSG0_ADDR_L);
5171
5172 REG_WR(bp, reg_offset, U64_LO(section));
5173 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5174 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5175 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5176 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5177 }
a2fbb9ea 5178
523224a3
DK		 5179 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5180 sp_sb);
a2fbb9ea 5181
523224a3 5182 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5183
619c5cb6 5184 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5185 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5186 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5187 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5188 sp_sb_data.igu_seg_id = igu_seg_id;
5189 sp_sb_data.p_func.pf_id = func;
f2e0899f 5190 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5191 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5192
523224a3 5193 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5194
523224a3 5195 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5196}
5197
9f6c9258 5198void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5199{
a2fbb9ea
ET		 5200 int i;
5201
ec6ba945 5202 for_each_eth_queue(bp, i)
523224a3 5203 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5204 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5205}
5206
a2fbb9ea
ET		 5207static void bnx2x_init_sp_ring(struct bnx2x *bp)
5208{
a2fbb9ea 5209 spin_lock_init(&bp->spq_lock);
6e30dd4e 5210 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5211
a2fbb9ea 5212 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5213 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5214 bp->spq_prod_bd = bp->spq;
5215 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5216}
5217
523224a3 5218static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5219{
5220 int i;
523224a3
DK		 5221 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5222 union event_ring_elem *elem =
5223 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5224
523224a3
DK		 5225 elem->next_page.addr.hi =
5226 cpu_to_le32(U64_HI(bp->eq_mapping +
5227 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5228 elem->next_page.addr.lo =
5229 cpu_to_le32(U64_LO(bp->eq_mapping +
5230 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5231 }
523224a3
DK		 5232 bp->eq_cons = 0;
5233 bp->eq_prod = NUM_EQ_DESC;
5234 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 5235 /* we want a warning message before it gets rought... */
5236 atomic_set(&bp->eq_spq_left,
5237 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5238}
5239
619c5cb6
VZ		 5240
5241/* called with netif_addr_lock_bh() */
5242void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5243 unsigned long rx_mode_flags,
5244 unsigned long rx_accept_flags,
5245 unsigned long tx_accept_flags,
5246 unsigned long ramrod_flags)
ab532cf3 5247{
619c5cb6
VZ		 5248 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5249 int rc;
5250
5251 memset(&ramrod_param, 0, sizeof(ramrod_param));
5252
5253 /* Prepare ramrod parameters */
5254 ramrod_param.cid = 0;
5255 ramrod_param.cl_id = cl_id;
5256 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5257 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5258
619c5cb6
VZ		 5259 ramrod_param.pstate = &bp->sp_state;
5260 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5261
619c5cb6
VZ		 5262 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5263 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5264
5265 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5266
5267 ramrod_param.ramrod_flags = ramrod_flags;
5268 ramrod_param.rx_mode_flags = rx_mode_flags;
5269
5270 ramrod_param.rx_accept_flags = rx_accept_flags;
5271 ramrod_param.tx_accept_flags = tx_accept_flags;
5272
5273 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5274 if (rc < 0) {
5275 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5276 return;
5277 }
a2fbb9ea
ET		 5278}
5279
619c5cb6
VZ		 5280/* called with netif_addr_lock_bh() */
5281void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 5282{
619c5cb6
VZ		 5283 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5284 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 5285
619c5cb6
VZ		 5286#ifdef BCM_CNIC
5287 if (!NO_FCOE(bp))
5288
5289 /* Configure rx_mode of FCoE Queue */
5290 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5291#endif
5292
5293 switch (bp->rx_mode) {
5294 case BNX2X_RX_MODE_NONE:
5295 /*
5296 * 'drop all' supersedes any accept flags that may have been
5297 * passed to the function.
5298 */
5299 break;
5300 case BNX2X_RX_MODE_NORMAL:
5301 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5302 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5303 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5304
5305 /* internal switching mode */
5306 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5307 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5308 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5309
5310 break;
5311 case BNX2X_RX_MODE_ALLMULTI:
5312 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5313 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5314 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5315
5316 /* internal switching mode */
5317 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5318 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5319 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5320
5321 break;
5322 case BNX2X_RX_MODE_PROMISC:
5323 /* According to deffinition of SI mode, iface in promisc mode
5324 * should receive matched and unmatched (in resolution of port)
5325 * unicast packets.
5326 */
5327 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5328 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5329 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5330 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5331
5332 /* internal switching mode */
5333 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5334 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5335
5336 if (IS_MF_SI(bp))
5337 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5338 else
5339 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5340
5341 break;
5342 default:
5343 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5344 return;
5345 }
de832a55 5346
619c5cb6
VZ		 5347 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5348 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5349 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5350 }
5351
619c5cb6
VZ		 5352 __set_bit(RAMROD_RX, &ramrod_flags);
5353 __set_bit(RAMROD_TX, &ramrod_flags);
5354
5355 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5356 tx_accept_flags, ramrod_flags);
5357}
5358
5359static void bnx2x_init_internal_common(struct bnx2x *bp)
5360{
5361 int i;
5362
0793f83f
DK		 5363 if (IS_MF_SI(bp))
5364 /*
5365 * In switch independent mode, the TSTORM needs to accept
5366 * packets that failed classification, since approximate match
5367 * mac addresses aren't written to NIG LLH
5368 */
5369 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5370 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5371 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5372 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5373 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5374
523224a3
DK		 5375 /* Zero this manually as its initialization is
5376 currently missing in the initTool */
5377 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5378 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5379 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5380 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5381 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5382 CHIP_INT_MODE_IS_BC(bp) ?
5383 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5384 }
523224a3 5385}
8a1c38d1 5386
471de716
EG		 5387static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5388{
5389 switch (load_code) {
5390 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5391 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5392 bnx2x_init_internal_common(bp);
5393 /* no break */
5394
5395 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5396 /* nothing to do */
471de716
EG		 5397 /* no break */
5398
5399 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5400 /* internal memory per function is
5401 initialized inside bnx2x_pf_init */
471de716
EG		 5402 break;
5403
5404 default:
5405 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5406 break;
5407 }
5408}
5409
619c5cb6 5410static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5411{
6383c0b3 5412 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
619c5cb6 5413}
523224a3 5414
619c5cb6
VZ		 5415static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5416{
6383c0b3 5417 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
619c5cb6
VZ		 5418}
5419
5420static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5421{
5422 if (CHIP_IS_E1x(fp->bp))
5423 return BP_L_ID(fp->bp) + fp->index;
5424 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5425 return bnx2x_fp_igu_sb_id(fp);
5426}
5427
6383c0b3 5428static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5429{
5430 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5431 u8 cos;
619c5cb6 5432 unsigned long q_type = 0;
6383c0b3 5433 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 5434 fp->rx_queue = fp_idx;
b3b83c3f 5435 fp->cid = fp_idx;
619c5cb6
VZ		 5436 fp->cl_id = bnx2x_fp_cl_id(fp);
5437 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5438 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5439 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5440 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5441
523224a3 5442 /* init shortcut */
619c5cb6 5443 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
523224a3
DK		 5444 /* Setup SB indicies */
5445 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5446
619c5cb6
VZ		 5447 /* Configure Queue State object */
5448 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5449 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5450
5451 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5452
5453 /* init tx data */
5454 for_each_cos_in_tx_queue(fp, cos) {
5455 bnx2x_init_txdata(bp, &fp->txdata[cos],
5456 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5457 FP_COS_TO_TXQ(fp, cos),
5458 BNX2X_TX_SB_INDEX_BASE + cos);
5459 cids[cos] = fp->txdata[cos].cid;
5460 }
5461
5462 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5463 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5464 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5465
5466 /**
5467 * Configure classification DBs: Always enable Tx switching
5468 */
5469 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5470
523224a3
DK		 5471 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5472 "cl_id %d fw_sb %d igu_sb %d\n",
619c5cb6 5473 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
523224a3
DK		 5474 fp->igu_sb_id);
5475 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5476 fp->fw_sb_id, fp->igu_sb_id);
5477
5478 bnx2x_update_fpsb_idx(fp);
5479}
5480
9f6c9258 5481void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 5482{
5483 int i;
5484
ec6ba945 5485 for_each_eth_queue(bp, i)
6383c0b3 5486 bnx2x_init_eth_fp(bp, i);
37b091ba 5487#ifdef BCM_CNIC
ec6ba945
VZ		 5488 if (!NO_FCOE(bp))
5489 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5490
5491 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5492 BNX2X_VF_ID_INVALID, false,
619c5cb6 5493 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5494
37b091ba 5495#endif
a2fbb9ea 5496
020c7e3f
YR		 5497 /* Initialize MOD_ABS interrupts */
5498 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5499 bp->common.shmem_base, bp->common.shmem2_base,
5500 BP_PORT(bp));
16119785
EG		 5501 /* ensure status block indices were read */
5502 rmb();
5503
523224a3 5504 bnx2x_init_def_sb(bp);
5c862848 5505 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5506 bnx2x_init_rx_rings(bp);
523224a3 5507 bnx2x_init_tx_rings(bp);
a2fbb9ea 5508 bnx2x_init_sp_ring(bp);
523224a3 5509 bnx2x_init_eq_ring(bp);
471de716 5510 bnx2x_init_internal(bp, load_code);
523224a3 5511 bnx2x_pf_init(bp);
0ef00459
EG		 5512 bnx2x_stats_init(bp);
5513
0ef00459
EG		 5514 /* flush all before enabling interrupts */
5515 mb();
5516 mmiowb();
5517
615f8fd9 5518 bnx2x_int_enable(bp);
eb8da205
EG		 5519
5520 /* Check for SPIO5 */
5521 bnx2x_attn_int_deasserted0(bp,
5522 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5523 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5524}
5525
5526/* end of nic init */
5527
5528/*
5529 * gzip service functions
5530 */
5531
5532static int bnx2x_gunzip_init(struct bnx2x *bp)
5533{
1a983142
FT		 5534 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5535 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5536 if (bp->gunzip_buf == NULL)
5537 goto gunzip_nomem1;
5538
5539 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5540 if (bp->strm == NULL)
5541 goto gunzip_nomem2;
5542
7ab24bfd 5543 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5544 if (bp->strm->workspace == NULL)
5545 goto gunzip_nomem3;
5546
5547 return 0;
5548
5549gunzip_nomem3:
5550 kfree(bp->strm);
5551 bp->strm = NULL;
5552
5553gunzip_nomem2:
1a983142
FT		 5554 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5555 bp->gunzip_mapping);
a2fbb9ea
ET		 5556 bp->gunzip_buf = NULL;
5557
5558gunzip_nomem1:
cdaa7cb8
VZ		 5559 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5560 " un-compression\n");
a2fbb9ea
ET		 5561 return -ENOMEM;
5562}
5563
5564static void bnx2x_gunzip_end(struct bnx2x *bp)
5565{
b3b83c3f 5566 if (bp->strm) {
7ab24bfd 5567 vfree(bp->strm->workspace);
b3b83c3f
DK		 5568 kfree(bp->strm);
5569 bp->strm = NULL;
5570 }
a2fbb9ea
ET		 5571
5572 if (bp->gunzip_buf) {
1a983142
FT		 5573 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5574 bp->gunzip_mapping);
a2fbb9ea
ET		 5575 bp->gunzip_buf = NULL;
5576 }
5577}
5578
94a78b79 5579static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 5580{
5581 int n, rc;
5582
5583 /* check gzip header */
94a78b79
VZ		 5584 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5585 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 5586 return -EINVAL;
94a78b79 5587 }
a2fbb9ea
ET		 5588
5589 n = 10;
5590
34f80b04 5591#define FNAME 0x8
a2fbb9ea
ET		 5592
5593 if (zbuf[3] & FNAME)
5594 while ((zbuf[n++] != 0) && (n < len));
5595
94a78b79 5596 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 5597 bp->strm->avail_in = len - n;
5598 bp->strm->next_out = bp->gunzip_buf;
5599 bp->strm->avail_out = FW_BUF_SIZE;
5600
5601 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5602 if (rc != Z_OK)
5603 return rc;
5604
5605 rc = zlib_inflate(bp->strm, Z_FINISH);
5606 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 5607 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5608 bp->strm->msg);
a2fbb9ea
ET		 5609
5610 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5611 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 5612 netdev_err(bp->dev, "Firmware decompression error:"
5613 " gunzip_outlen (%d) not aligned\n",
5614 bp->gunzip_outlen);
a2fbb9ea
ET		 5615 bp->gunzip_outlen >>= 2;
5616
5617 zlib_inflateEnd(bp->strm);
5618
5619 if (rc == Z_STREAM_END)
5620 return 0;
5621
5622 return rc;
5623}
5624
5625/* nic load/unload */
5626
5627/*
34f80b04 5628 * General service functions
a2fbb9ea
ET		 5629 */
5630
5631/* send a NIG loopback debug packet */
5632static void bnx2x_lb_pckt(struct bnx2x *bp)
5633{
a2fbb9ea 5634 u32 wb_write[3];
a2fbb9ea
ET		 5635
5636 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 5637 wb_write[0] = 0x55555555;
5638 wb_write[1] = 0x55555555;
34f80b04 5639 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 5640 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5641
5642 /* NON-IP protocol */
a2fbb9ea
ET		 5643 wb_write[0] = 0x09000000;
5644 wb_write[1] = 0x55555555;
34f80b04 5645 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 5646 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5647}
5648
5649/* some of the internal memories
5650 * are not directly readable from the driver
5651 * to test them we send debug packets
5652 */
5653static int bnx2x_int_mem_test(struct bnx2x *bp)
5654{
5655 int factor;
5656 int count, i;
5657 u32 val = 0;
5658
ad8d3948 5659 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 5660 factor = 120;
ad8d3948
EG		 5661 else if (CHIP_REV_IS_EMUL(bp))
5662 factor = 200;
5663 else
a2fbb9ea 5664 factor = 1;
a2fbb9ea 5665
a2fbb9ea
ET		 5666 /* Disable inputs of parser neighbor blocks */
5667 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5668 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5669 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5670 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5671
5672 /* Write 0 to parser credits for CFC search request */
5673 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5674
5675 /* send Ethernet packet */
5676 bnx2x_lb_pckt(bp);
5677
5678 /* TODO do i reset NIG statistic? */
5679 /* Wait until NIG register shows 1 packet of size 0x10 */
5680 count = 1000 * factor;
5681 while (count) {
34f80b04 5682
a2fbb9ea
ET		 5683 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5684 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5685 if (val == 0x10)
5686 break;
5687
5688 msleep(10);
5689 count--;
5690 }
5691 if (val != 0x10) {
5692 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5693 return -1;
5694 }
5695
5696 /* Wait until PRS register shows 1 packet */
5697 count = 1000 * factor;
5698 while (count) {
5699 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 5700 if (val == 1)
5701 break;
5702
5703 msleep(10);
5704 count--;
5705 }
5706 if (val != 0x1) {
5707 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5708 return -2;
5709 }
5710
5711 /* Reset and init BRB, PRS */
34f80b04 5712 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 5713 msleep(50);
34f80b04 5714 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 5715 msleep(50);
619c5cb6
VZ		 5716 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5717 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 5718
5719 DP(NETIF_MSG_HW, "part2\n");
5720
5721 /* Disable inputs of parser neighbor blocks */
5722 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5723 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5724 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5725 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5726
5727 /* Write 0 to parser credits for CFC search request */
5728 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5729
5730 /* send 10 Ethernet packets */
5731 for (i = 0; i < 10; i++)
5732 bnx2x_lb_pckt(bp);
5733
5734 /* Wait until NIG register shows 10 + 1
5735 packets of size 11*0x10 = 0xb0 */
5736 count = 1000 * factor;
5737 while (count) {
34f80b04 5738
a2fbb9ea
ET		 5739 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5740 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5741 if (val == 0xb0)
5742 break;
5743
5744 msleep(10);
5745 count--;
5746 }
5747 if (val != 0xb0) {
5748 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5749 return -3;
5750 }
5751
5752 /* Wait until PRS register shows 2 packets */
5753 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5754 if (val != 2)
5755 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5756
5757 /* Write 1 to parser credits for CFC search request */
5758 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5759
5760 /* Wait until PRS register shows 3 packets */
5761 msleep(10 * factor);
5762 /* Wait until NIG register shows 1 packet of size 0x10 */
5763 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5764 if (val != 3)
5765 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5766
5767 /* clear NIG EOP FIFO */
5768 for (i = 0; i < 11; i++)
5769 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5770 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5771 if (val != 1) {
5772 BNX2X_ERR("clear of NIG failed\n");
5773 return -4;
5774 }
5775
5776 /* Reset and init BRB, PRS, NIG */
5777 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5778 msleep(50);
5779 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5780 msleep(50);
619c5cb6
VZ		 5781 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5782 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
37b091ba 5783#ifndef BCM_CNIC
a2fbb9ea
ET		 5784 /* set NIC mode */
5785 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5786#endif
5787
5788 /* Enable inputs of parser neighbor blocks */
5789 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5790 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5791 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 5792 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 5793
5794 DP(NETIF_MSG_HW, "done\n");
5795
5796 return 0; /* OK */
5797}
5798
4a33bc03 5799static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 5800{
5801 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 5802 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5803 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5804 else
5805 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 5806 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5807 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 5808 /*
5809 * mask read length error interrupts in brb for parser
5810 * (parsing unit and 'checksum and crc' unit)
5811 * these errors are legal (PU reads fixed length and CAC can cause
5812 * read length error on truncated packets)
5813 */
5814 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 5815 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5816 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5817 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5818 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5819 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 5820/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5821/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5822 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5823 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5824 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 5825/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5826/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5827 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5828 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5829 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5830 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 5831/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5832/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 5833
34f80b04
EG		 5834 if (CHIP_REV_IS_FPGA(bp))
5835 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
619c5cb6 5836 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5837 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5838 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5839 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5840 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5841 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5842 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 5843 else
5844 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 5845 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5846 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5847 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 5848/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 5849
5850 if (!CHIP_IS_E1x(bp))
5851 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5852 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5853
a2fbb9ea
ET		 5854 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5855 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 5856/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 5857 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 5858}
5859
81f75bbf
EG		 5860static void bnx2x_reset_common(struct bnx2x *bp)
5861{
619c5cb6
VZ		 5862 u32 val = 0x1400;
5863
81f75bbf
EG		 5864 /* reset_common */
5865 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5866 0xd3ffff7f);
619c5cb6
VZ		 5867
5868 if (CHIP_IS_E3(bp)) {
5869 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5870 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5871 }
5872
5873 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5874}
5875
5876static void bnx2x_setup_dmae(struct bnx2x *bp)
5877{
5878 bp->dmae_ready = 0;
5879 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 5880}
5881
573f2035
EG		 5882static void bnx2x_init_pxp(struct bnx2x *bp)
5883{
5884 u16 devctl;
5885 int r_order, w_order;
5886
5887 pci_read_config_word(bp->pdev,
b6c2f86e 5888 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 5889 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5890 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5891 if (bp->mrrs == -1)
5892 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5893 else {
5894 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5895 r_order = bp->mrrs;
5896 }
5897
5898 bnx2x_init_pxp_arb(bp, r_order, w_order);
5899}
fd4ef40d
EG		 5900
5901static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5902{
2145a920 5903 int is_required;
fd4ef40d 5904 u32 val;
2145a920 5905 int port;
fd4ef40d 5906
2145a920
VZ		 5907 if (BP_NOMCP(bp))
5908 return;
5909
5910 is_required = 0;
fd4ef40d
EG		 5911 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5912 SHARED_HW_CFG_FAN_FAILURE_MASK;
5913
5914 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5915 is_required = 1;
5916
5917 /*
5918 * The fan failure mechanism is usually related to the PHY type since
5919 * the power consumption of the board is affected by the PHY. Currently,
5920 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5921 */
5922 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5923 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 5924 is_required |=
d90d96ba
YR		 5925 bnx2x_fan_failure_det_req(
5926 bp,
5927 bp->common.shmem_base,
a22f0788 5928 bp->common.shmem2_base,
d90d96ba 5929 port);
fd4ef40d
EG		 5930 }
5931
5932 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5933
5934 if (is_required == 0)
5935 return;
5936
5937 /* Fan failure is indicated by SPIO 5 */
5938 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5939 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5940
5941 /* set to active low mode */
5942 val = REG_RD(bp, MISC_REG_SPIO_INT);
5943 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 5944 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 5945 REG_WR(bp, MISC_REG_SPIO_INT, val);
5946
5947 /* enable interrupt to signal the IGU */
5948 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5949 val |= (1 << MISC_REGISTERS_SPIO_5);
5950 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5951}
5952
f2e0899f
DK		 5953static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5954{
5955 u32 offset = 0;
5956
5957 if (CHIP_IS_E1(bp))
5958 return;
5959 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5960 return;
5961
5962 switch (BP_ABS_FUNC(bp)) {
5963 case 0:
5964 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5965 break;
5966 case 1:
5967 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5968 break;
5969 case 2:
5970 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5971 break;
5972 case 3:
5973 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5974 break;
5975 case 4:
5976 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5977 break;
5978 case 5:
5979 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5980 break;
5981 case 6:
5982 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5983 break;
5984 case 7:
5985 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5986 break;
5987 default:
5988 return;
5989 }
5990
5991 REG_WR(bp, offset, pretend_func_num);
5992 REG_RD(bp, offset);
5993 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5994}
5995
c9ee9206 5996void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 5997{
5998 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5999 val &= ~IGU_PF_CONF_FUNC_EN;
6000
6001 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6002 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6003 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6004}
6005
619c5cb6
VZ		 6006static inline void bnx2x__common_init_phy(struct bnx2x *bp)
6007{
6008 u32 shmem_base[2], shmem2_base[2];
6009 shmem_base[0] = bp->common.shmem_base;
6010 shmem2_base[0] = bp->common.shmem2_base;
6011 if (!CHIP_IS_E1x(bp)) {
6012 shmem_base[1] =
6013 SHMEM2_RD(bp, other_shmem_base_addr);
6014 shmem2_base[1] =
6015 SHMEM2_RD(bp, other_shmem2_base_addr);
6016 }
6017 bnx2x_acquire_phy_lock(bp);
6018 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6019 bp->common.chip_id);
6020 bnx2x_release_phy_lock(bp);
6021}
6022
6023/**
6024 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6025 *
6026 * @bp: driver handle
6027 */
6028static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6029{
619c5cb6 6030 u32 val;
a2fbb9ea 6031
f2e0899f 6032 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6033
2031bd3a
DK		 6034 /*
6035 * take the UNDI lock to protect undi_unload flow from accessing
6036 * registers while we're resetting the chip
6037 */
7a06a122 6038 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6039
81f75bbf 6040 bnx2x_reset_common(bp);
34f80b04 6041 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6042
619c5cb6
VZ		 6043 val = 0xfffc;
6044 if (CHIP_IS_E3(bp)) {
6045 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6046 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6047 }
6048 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6049
7a06a122 6050 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6051
619c5cb6 6052 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6053
619c5cb6
VZ		 6054 if (!CHIP_IS_E1x(bp)) {
6055 u8 abs_func_id;
f2e0899f
DK		 6056
6057 /**
6058 * 4-port mode or 2-port mode we need to turn of master-enable
6059 * for everyone, after that, turn it back on for self.
6060 * so, we disregard multi-function or not, and always disable
6061 * for all functions on the given path, this means 0,2,4,6 for
6062 * path 0 and 1,3,5,7 for path 1
6063 */
619c5cb6
VZ		 6064 for (abs_func_id = BP_PATH(bp);
6065 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6066 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6067 REG_WR(bp,
6068 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6069 1);
6070 continue;
6071 }
6072
619c5cb6 6073 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6074 /* clear pf enable */
6075 bnx2x_pf_disable(bp);
6076 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6077 }
6078 }
a2fbb9ea 6079
619c5cb6 6080 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6081 if (CHIP_IS_E1(bp)) {
6082 /* enable HW interrupt from PXP on USDM overflow
6083 bit 16 on INT_MASK_0 */
6084 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6085 }
a2fbb9ea 6086
619c5cb6 6087 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6088 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6089
6090#ifdef __BIG_ENDIAN
34f80b04
EG		 6091 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6092 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6093 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6094 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6095 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6096 /* make sure this value is 0 */
6097 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6098
6099/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6100 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6101 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6102 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6103 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6104#endif
6105
523224a3
DK		 6106 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6107
34f80b04
EG		 6108 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6109 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6110
34f80b04
EG		 6111 /* let the HW do it's magic ... */
6112 msleep(100);
6113 /* finish PXP init */
6114 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6115 if (val != 1) {
6116 BNX2X_ERR("PXP2 CFG failed\n");
6117 return -EBUSY;
6118 }
6119 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6120 if (val != 1) {
6121 BNX2X_ERR("PXP2 RD_INIT failed\n");
6122 return -EBUSY;
6123 }
a2fbb9ea 6124
f2e0899f
DK		 6125 /* Timers bug workaround E2 only. We need to set the entire ILT to
6126 * have entries with value "0" and valid bit on.
6127 * This needs to be done by the first PF that is loaded in a path
6128 * (i.e. common phase)
6129 */
619c5cb6
VZ		 6130 if (!CHIP_IS_E1x(bp)) {
6131/* In E2 there is a bug in the timers block that can cause function 6 / 7
6132 * (i.e. vnic3) to start even if it is marked as "scan-off".
6133 * This occurs when a different function (func2,3) is being marked
6134 * as "scan-off". Real-life scenario for example: if a driver is being
6135 * load-unloaded while func6,7 are down. This will cause the timer to access
6136 * the ilt, translate to a logical address and send a request to read/write.
6137 * Since the ilt for the function that is down is not valid, this will cause
6138 * a translation error which is unrecoverable.
6139 * The Workaround is intended to make sure that when this happens nothing fatal
6140 * will occur. The workaround:
6141 * 1. First PF driver which loads on a path will:
6142 * a. After taking the chip out of reset, by using pretend,
6143 * it will write "0" to the following registers of
6144 * the other vnics.
6145 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6146 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6147 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6148 * And for itself it will write '1' to
6149 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6150 * dmae-operations (writing to pram for example.)
6151 * note: can be done for only function 6,7 but cleaner this
6152 * way.
6153 * b. Write zero+valid to the entire ILT.
6154 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6155 * VNIC3 (of that port). The range allocated will be the
6156 * entire ILT. This is needed to prevent ILT range error.
6157 * 2. Any PF driver load flow:
6158 * a. ILT update with the physical addresses of the allocated
6159 * logical pages.
6160 * b. Wait 20msec. - note that this timeout is needed to make
6161 * sure there are no requests in one of the PXP internal
6162 * queues with "old" ILT addresses.
6163 * c. PF enable in the PGLC.
6164 * d. Clear the was_error of the PF in the PGLC. (could have
6165 * occured while driver was down)
6166 * e. PF enable in the CFC (WEAK + STRONG)
6167 * f. Timers scan enable
6168 * 3. PF driver unload flow:
6169 * a. Clear the Timers scan_en.
6170 * b. Polling for scan_on=0 for that PF.
6171 * c. Clear the PF enable bit in the PXP.
6172 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6173 * e. Write zero+valid to all ILT entries (The valid bit must
6174 * stay set)
6175 * f. If this is VNIC 3 of a port then also init
6176 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6177 * to the last enrty in the ILT.
6178 *
6179 * Notes:
6180 * Currently the PF error in the PGLC is non recoverable.
6181 * In the future the there will be a recovery routine for this error.
6182 * Currently attention is masked.
6183 * Having an MCP lock on the load/unload process does not guarantee that
6184 * there is no Timer disable during Func6/7 enable. This is because the
6185 * Timers scan is currently being cleared by the MCP on FLR.
6186 * Step 2.d can be done only for PF6/7 and the driver can also check if
6187 * there is error before clearing it. But the flow above is simpler and
6188 * more general.
6189 * All ILT entries are written by zero+valid and not just PF6/7
6190 * ILT entries since in the future the ILT entries allocation for
6191 * PF-s might be dynamic.
6192 */
f2e0899f
DK		 6193 struct ilt_client_info ilt_cli;
6194 struct bnx2x_ilt ilt;
6195 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6196 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6197
b595076a 6198 /* initialize dummy TM client */
f2e0899f
DK		 6199 ilt_cli.start = 0;
6200 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6201 ilt_cli.client_num = ILT_CLIENT_TM;
6202
6203 /* Step 1: set zeroes to all ilt page entries with valid bit on
6204 * Step 2: set the timers first/last ilt entry to point
6205 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 6206 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 6207 *
6208 * both steps performed by call to bnx2x_ilt_client_init_op()
6209 * with dummy TM client
6210 *
6211 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6212 * and his brother are split registers
6213 */
6214 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6215 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6216 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6217
6218 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6219 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6220 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6221 }
6222
6223
34f80b04
EG		 6224 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6225 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 6226
619c5cb6 6227 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6228 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6229 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 6230 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 6231
619c5cb6 6232 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6233
6234 /* let the HW do it's magic ... */
6235 do {
6236 msleep(200);
6237 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6238 } while (factor-- && (val != 1));
6239
6240 if (val != 1) {
6241 BNX2X_ERR("ATC_INIT failed\n");
6242 return -EBUSY;
6243 }
6244 }
6245
619c5cb6 6246 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6247
34f80b04
EG		 6248 /* clean the DMAE memory */
6249 bp->dmae_ready = 1;
619c5cb6
VZ		 6250 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6251
6252 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6253
6254 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6255
6256 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6257
619c5cb6 6258 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6259
34f80b04
EG		 6260 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6261 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6262 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6263 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6264
619c5cb6 6265 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6266
f85582f8 6267
523224a3
DK		 6268 /* QM queues pointers table */
6269 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6270
34f80b04
EG		 6271 /* soft reset pulse */
6272 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6273 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6274
37b091ba 6275#ifdef BCM_CNIC
619c5cb6 6276 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6277#endif
a2fbb9ea 6278
619c5cb6 6279 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 6280 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 6281 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 6282 /* enable hw interrupt from doorbell Q */
6283 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 6284
619c5cb6 6285 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 6286
619c5cb6 6287 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 6288 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 6289
f2e0899f 6290 if (!CHIP_IS_E1(bp))
619c5cb6 6291 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 6292
619c5cb6
VZ		 6293 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6294 /* Bit-map indicating which L2 hdrs may appear
6295 * after the basic Ethernet header
6296 */
6297 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6298 bp->path_has_ovlan ? 7 : 6);
a2fbb9ea 6299
619c5cb6
VZ		 6300 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6301 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6302 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6303 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 6304
619c5cb6
VZ		 6305 if (!CHIP_IS_E1x(bp)) {
6306 /* reset VFC memories */
6307 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6308 VFC_MEMORIES_RST_REG_CAM_RST |
6309 VFC_MEMORIES_RST_REG_RAM_RST);
6310 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6311 VFC_MEMORIES_RST_REG_CAM_RST |
6312 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 6313
619c5cb6
VZ		 6314 msleep(20);
6315 }
a2fbb9ea 6316
619c5cb6
VZ		 6317 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6318 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6319 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6320 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6321
34f80b04
EG		 6322 /* sync semi rtc */
6323 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6324 0x80000000);
6325 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6326 0x80000000);
a2fbb9ea 6327
619c5cb6
VZ		 6328 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6329 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6330 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6331
619c5cb6
VZ		 6332 if (!CHIP_IS_E1x(bp))
6333 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6334 bp->path_has_ovlan ? 7 : 6);
f2e0899f 6335
34f80b04 6336 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6337
619c5cb6
VZ		 6338 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6339
37b091ba
MC		 6340#ifdef BCM_CNIC
6341 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6342 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6343 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6344 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6345 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6346 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6347 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6348 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6349 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6350 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6351#endif
34f80b04 6352 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6353
34f80b04
EG		 6354 if (sizeof(union cdu_context) != 1024)
6355 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 6356 dev_alert(&bp->pdev->dev, "please adjust the size "
6357 "of cdu_context(%ld)\n",
7995c64e 6358 (long)sizeof(union cdu_context));
a2fbb9ea 6359
619c5cb6 6360 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6361 val = (4 << 24) + (0 << 12) + 1024;
6362 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6363
619c5cb6 6364 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6365 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6366 /* enable context validation interrupt from CFC */
6367 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6368
6369 /* set the thresholds to prevent CFC/CDU race */
6370 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6371
619c5cb6 6372 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6373
619c5cb6 6374 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6375 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6376
619c5cb6
VZ		 6377 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6378 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6379
34f80b04
EG		 6380 /* Reset PCIE errors for debug */
6381 REG_WR(bp, 0x2814, 0xffffffff);
6382 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6383
619c5cb6 6384 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6385 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6386 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6387 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6388 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6389 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6390 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6391 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6392 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6393 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6394 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6395 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6396 }
6397
619c5cb6 6398 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6399 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6400 /* in E3 this done in per-port section */
6401 if (!CHIP_IS_E3(bp))
6402 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6403 }
619c5cb6
VZ		 6404 if (CHIP_IS_E1H(bp))
6405 /* not applicable for E2 (and above ...) */
6406 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6407
6408 if (CHIP_REV_IS_SLOW(bp))
6409 msleep(200);
6410
6411 /* finish CFC init */
6412 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6413 if (val != 1) {
6414 BNX2X_ERR("CFC LL_INIT failed\n");
6415 return -EBUSY;
6416 }
6417 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6418 if (val != 1) {
6419 BNX2X_ERR("CFC AC_INIT failed\n");
6420 return -EBUSY;
6421 }
6422 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6423 if (val != 1) {
6424 BNX2X_ERR("CFC CAM_INIT failed\n");
6425 return -EBUSY;
6426 }
6427 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6428
f2e0899f
DK		 6429 if (CHIP_IS_E1(bp)) {
6430 /* read NIG statistic
6431 to see if this is our first up since powerup */
6432 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6433 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6434
f2e0899f
DK		 6435 /* do internal memory self test */
6436 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6437 BNX2X_ERR("internal mem self test failed\n");
6438 return -EBUSY;
6439 }
34f80b04
EG		 6440 }
6441
fd4ef40d
EG		 6442 bnx2x_setup_fan_failure_detection(bp);
6443
34f80b04
EG		 6444 /* clear PXP2 attentions */
6445 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6446
4a33bc03 6447 bnx2x_enable_blocks_attention(bp);
c9ee9206 6448 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6449
6bbca910 6450 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6451 if (CHIP_IS_E1x(bp))
6452 bnx2x__common_init_phy(bp);
6bbca910
YR		 6453 } else
6454 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6455
34f80b04
EG		 6456 return 0;
6457}
a2fbb9ea 6458
619c5cb6
VZ		 6459/**
6460 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6461 *
6462 * @bp: driver handle
6463 */
6464static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6465{
6466 int rc = bnx2x_init_hw_common(bp);
6467
6468 if (rc)
6469 return rc;
6470
6471 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6472 if (!BP_NOMCP(bp))
6473 bnx2x__common_init_phy(bp);
6474
6475 return 0;
6476}
6477
523224a3 6478static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6479{
6480 int port = BP_PORT(bp);
619c5cb6 6481 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6482 u32 low, high;
34f80b04 6483 u32 val;
a2fbb9ea 6484
619c5cb6
VZ		 6485 bnx2x__link_reset(bp);
6486
cdaa7cb8 6487 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 6488
6489 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6490
619c5cb6
VZ		 6491 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6492 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6493 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6494
f2e0899f
DK		 6495 /* Timers bug workaround: disables the pf_master bit in pglue at
6496 * common phase, we need to enable it here before any dmae access are
6497 * attempted. Therefore we manually added the enable-master to the
6498 * port phase (it also happens in the function phase)
6499 */
619c5cb6 6500 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6501 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6502
619c5cb6
VZ		 6503 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6504 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6505 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6506 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6507
6508 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6509 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6510 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6511 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6512
523224a3
DK		 6513 /* QM cid (connection) count */
6514 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6515
523224a3 6516#ifdef BCM_CNIC
619c5cb6 6517 bnx2x_init_block(bp, BLOCK_TM, init_phase);
37b091ba
MC		 6518 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6519 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 6520#endif
cdaa7cb8 6521
619c5cb6 6522 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f
DK		 6523
6524 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6525 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6526
6527 if (IS_MF(bp))
6528 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6529 else if (bp->dev->mtu > 4096) {
6530 if (bp->flags & ONE_PORT_FLAG)
6531 low = 160;
6532 else {
6533 val = bp->dev->mtu;
6534 /* (24*1024 + val*4)/256 */
6535 low = 96 + (val/64) +
6536 ((val % 64) ? 1 : 0);
6537 }
6538 } else
6539 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6540 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6541 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6542 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6543 }
1c06328c 6544
619c5cb6
VZ		 6545 if (CHIP_MODE_IS_4_PORT(bp))
6546 REG_WR(bp, (BP_PORT(bp) ?
6547 BRB1_REG_MAC_GUARANTIED_1 :
6548 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6549
ca00392c 6550
619c5cb6
VZ		 6551 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6552 if (CHIP_IS_E3B0(bp))
6553 /* Ovlan exists only if we are in multi-function +
6554 * switch-dependent mode, in switch-independent there
6555 * is no ovlan headers
6556 */
6557 REG_WR(bp, BP_PORT(bp) ?
6558 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6559 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6560 (bp->path_has_ovlan ? 7 : 6));
356e2385 6561
619c5cb6
VZ		 6562 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6563 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6564 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6565 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 6566
619c5cb6
VZ		 6567 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6568 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6569 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6570 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 6571
619c5cb6
VZ		 6572 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6573 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 6574
619c5cb6
VZ		 6575 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6576
6577 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6578 /* configure PBF to work without PAUSE mtu 9000 */
6579 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 6580
f2e0899f
DK		 6581 /* update threshold */
6582 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6583 /* update init credit */
6584 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 6585
f2e0899f
DK		 6586 /* probe changes */
6587 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6588 udelay(50);
6589 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6590 }
a2fbb9ea 6591
37b091ba 6592#ifdef BCM_CNIC
619c5cb6 6593 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
a2fbb9ea 6594#endif
619c5cb6
VZ		 6595 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6596 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 6597
6598 if (CHIP_IS_E1(bp)) {
6599 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6600 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6601 }
619c5cb6 6602 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 6603
619c5cb6 6604 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6605
619c5cb6 6606 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 6607 /* init aeu_mask_attn_func_0/1:
6608 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6609 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6610 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 6611 val = IS_MF(bp) ? 0xF7 : 0x7;
6612 /* Enable DCBX attention for all but E1 */
6613 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6614 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 6615
619c5cb6
VZ		 6616 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6617
6618 if (!CHIP_IS_E1x(bp)) {
6619 /* Bit-map indicating which L2 hdrs may appear after the
6620 * basic Ethernet header
6621 */
6622 REG_WR(bp, BP_PORT(bp) ?
6623 NIG_REG_P1_HDRS_AFTER_BASIC :
6624 NIG_REG_P0_HDRS_AFTER_BASIC,
6625 IS_MF_SD(bp) ? 7 : 6);
6626
6627 if (CHIP_IS_E3(bp))
6628 REG_WR(bp, BP_PORT(bp) ?
6629 NIG_REG_LLH1_MF_MODE :
6630 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6631 }
6632 if (!CHIP_IS_E3(bp))
6633 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 6634
f2e0899f 6635 if (!CHIP_IS_E1(bp)) {
fb3bff17 6636 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 6637 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 6638 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 6639
619c5cb6 6640 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6641 val = 0;
6642 switch (bp->mf_mode) {
6643 case MULTI_FUNCTION_SD:
6644 val = 1;
6645 break;
6646 case MULTI_FUNCTION_SI:
6647 val = 2;
6648 break;
6649 }
6650
6651 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6652 NIG_REG_LLH0_CLS_TYPE), val);
6653 }
1c06328c
EG		 6654 {
6655 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6656 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6657 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6658 }
34f80b04
EG		 6659 }
6660
619c5cb6
VZ		 6661
6662 /* If SPIO5 is set to generate interrupts, enable it for this port */
6663 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6664 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
4d295db0
EG		 6665 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6666 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6667 val = REG_RD(bp, reg_addr);
f1410647 6668 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 6669 REG_WR(bp, reg_addr, val);
f1410647 6670 }
a2fbb9ea 6671
34f80b04
EG		 6672 return 0;
6673}
6674
34f80b04
EG		 6675static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6676{
6677 int reg;
6678
f2e0899f 6679 if (CHIP_IS_E1(bp))
34f80b04 6680 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 6681 else
6682 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 6683
6684 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6685}
6686
f2e0899f
DK		 6687static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6688{
619c5cb6 6689 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 6690}
6691
6692static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6693{
6694 u32 i, base = FUNC_ILT_BASE(func);
6695 for (i = base; i < base + ILT_PER_FUNC; i++)
6696 bnx2x_ilt_wr(bp, i, 0);
6697}
6698
523224a3 6699static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 6700{
6701 int port = BP_PORT(bp);
6702 int func = BP_FUNC(bp);
619c5cb6 6703 int init_phase = PHASE_PF0 + func;
523224a3
DK		 6704 struct bnx2x_ilt *ilt = BP_ILT(bp);
6705 u16 cdu_ilt_start;
8badd27a 6706 u32 addr, val;
f4a66897 6707 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 6708 int i, main_mem_width, rc;
34f80b04 6709
cdaa7cb8 6710 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 6711
619c5cb6 6712 /* FLR cleanup - hmmm */
89db4ad8
AE		 6713 if (!CHIP_IS_E1x(bp)) {
6714 rc = bnx2x_pf_flr_clnup(bp);
6715 if (rc)
6716 return rc;
6717 }
619c5cb6 6718
8badd27a 6719 /* set MSI reconfigure capability */
f2e0899f
DK		 6720 if (bp->common.int_block == INT_BLOCK_HC) {
6721 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6722 val = REG_RD(bp, addr);
6723 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6724 REG_WR(bp, addr, val);
6725 }
8badd27a 6726
619c5cb6
VZ		 6727 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6728 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6729
523224a3
DK		 6730 ilt = BP_ILT(bp);
6731 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 6732
523224a3
DK		 6733 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6734 ilt->lines[cdu_ilt_start + i].page =
6735 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6736 ilt->lines[cdu_ilt_start + i].page_mapping =
6737 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6738 /* cdu ilt pages are allocated manually so there's no need to
6739 set the size */
37b091ba 6740 }
523224a3 6741 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 6742
523224a3
DK		 6743#ifdef BCM_CNIC
6744 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 6745
523224a3
DK		 6746 /* T1 hash bits value determines the T1 number of entries */
6747 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6748#endif
37b091ba 6749
523224a3
DK		 6750#ifndef BCM_CNIC
6751 /* set NIC mode */
6752 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6753#endif /* BCM_CNIC */
37b091ba 6754
619c5cb6 6755 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6756 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6757
6758 /* Turn on a single ISR mode in IGU if driver is going to use
6759 * INT#x or MSI
6760 */
6761 if (!(bp->flags & USING_MSIX_FLAG))
6762 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6763 /*
6764 * Timers workaround bug: function init part.
6765 * Need to wait 20msec after initializing ILT,
6766 * needed to make sure there are no requests in
6767 * one of the PXP internal queues with "old" ILT addresses
6768 */
6769 msleep(20);
6770 /*
6771 * Master enable - Due to WB DMAE writes performed before this
6772 * register is re-initialized as part of the regular function
6773 * init
6774 */
6775 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6776 /* Enable the function in IGU */
6777 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6778 }
6779
523224a3 6780 bp->dmae_ready = 1;
34f80b04 6781
619c5cb6 6782 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 6783
619c5cb6 6784 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6785 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6786
619c5cb6
VZ		 6787 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6788 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6789 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6790 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6791 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6792 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6793 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6794 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6795 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6796 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6797 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6798 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6799 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6800
6801 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6802 REG_WR(bp, QM_REG_PF_EN, 1);
6803
619c5cb6
VZ		 6804 if (!CHIP_IS_E1x(bp)) {
6805 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6806 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6807 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6808 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6809 }
6810 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6811
6812 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6813 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6814 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6815 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6816 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6817 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6818 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6819 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6820 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6821 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6822 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6823 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6824 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6825
619c5cb6 6826 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 6827
619c5cb6 6828 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 6829
619c5cb6 6830 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6831 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6832
fb3bff17 6833 if (IS_MF(bp)) {
34f80b04 6834 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 6835 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 6836 }
6837
619c5cb6 6838 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 6839
34f80b04 6840 /* HC init per function */
f2e0899f
DK		 6841 if (bp->common.int_block == INT_BLOCK_HC) {
6842 if (CHIP_IS_E1H(bp)) {
6843 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6844
6845 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6846 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6847 }
619c5cb6 6848 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 6849
6850 } else {
6851 int num_segs, sb_idx, prod_offset;
6852
34f80b04
EG		 6853 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6854
619c5cb6 6855 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6856 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6857 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6858 }
6859
619c5cb6 6860 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6861
619c5cb6 6862 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6863 int dsb_idx = 0;
6864 /**
6865 * Producer memory:
6866 * E2 mode: address 0-135 match to the mapping memory;
6867 * 136 - PF0 default prod; 137 - PF1 default prod;
6868 * 138 - PF2 default prod; 139 - PF3 default prod;
6869 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6870 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6871 * 144-147 reserved.
6872 *
6873 * E1.5 mode - In backward compatible mode;
6874 * for non default SB; each even line in the memory
6875 * holds the U producer and each odd line hold
6876 * the C producer. The first 128 producers are for
6877 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6878 * producers are for the DSB for each PF.
6879 * Each PF has five segments: (the order inside each
6880 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6881 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6882 * 144-147 attn prods;
6883 */
6884 /* non-default-status-blocks */
6885 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6886 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6887 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6888 prod_offset = (bp->igu_base_sb + sb_idx) *
6889 num_segs;
6890
6891 for (i = 0; i < num_segs; i++) {
6892 addr = IGU_REG_PROD_CONS_MEMORY +
6893 (prod_offset + i) * 4;
6894 REG_WR(bp, addr, 0);
6895 }
6896 /* send consumer update with value 0 */
6897 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6898 USTORM_ID, 0, IGU_INT_NOP, 1);
6899 bnx2x_igu_clear_sb(bp,
6900 bp->igu_base_sb + sb_idx);
6901 }
6902
6903 /* default-status-blocks */
6904 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6905 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6906
6907 if (CHIP_MODE_IS_4_PORT(bp))
6908 dsb_idx = BP_FUNC(bp);
6909 else
3395a033 6910 dsb_idx = BP_VN(bp);
f2e0899f
DK		 6911
6912 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6913 IGU_BC_BASE_DSB_PROD + dsb_idx :
6914 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6915
3395a033
DK		 6916 /*
6917 * igu prods come in chunks of E1HVN_MAX (4) -
6918 * does not matters what is the current chip mode
6919 */
f2e0899f
DK		 6920 for (i = 0; i < (num_segs * E1HVN_MAX);
6921 i += E1HVN_MAX) {
6922 addr = IGU_REG_PROD_CONS_MEMORY +
6923 (prod_offset + i)*4;
6924 REG_WR(bp, addr, 0);
6925 }
6926 /* send consumer update with 0 */
6927 if (CHIP_INT_MODE_IS_BC(bp)) {
6928 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6929 USTORM_ID, 0, IGU_INT_NOP, 1);
6930 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6931 CSTORM_ID, 0, IGU_INT_NOP, 1);
6932 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6933 XSTORM_ID, 0, IGU_INT_NOP, 1);
6934 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6935 TSTORM_ID, 0, IGU_INT_NOP, 1);
6936 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6937 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6938 } else {
6939 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6940 USTORM_ID, 0, IGU_INT_NOP, 1);
6941 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6942 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6943 }
6944 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6945
6946 /* !!! these should become driver const once
6947 rf-tool supports split-68 const */
6948 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6949 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6950 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6951 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6952 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6953 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6954 }
34f80b04 6955 }
34f80b04 6956
c14423fe 6957 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 6958 REG_WR(bp, 0x2114, 0xffffffff);
6959 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 6960
f4a66897
VZ		 6961 if (CHIP_IS_E1x(bp)) {
6962 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6963 main_mem_base = HC_REG_MAIN_MEMORY +
6964 BP_PORT(bp) * (main_mem_size * 4);
6965 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6966 main_mem_width = 8;
6967
6968 val = REG_RD(bp, main_mem_prty_clr);
6969 if (val)
6970 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6971 "block during "
6972 "function init (0x%x)!\n", val);
6973
6974 /* Clear "false" parity errors in MSI-X table */
6975 for (i = main_mem_base;
6976 i < main_mem_base + main_mem_size * 4;
6977 i += main_mem_width) {
6978 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6979 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6980 i, main_mem_width / 4);
6981 }
6982 /* Clear HC parity attention */
6983 REG_RD(bp, main_mem_prty_clr);
6984 }
6985
619c5cb6
VZ		 6986#ifdef BNX2X_STOP_ON_ERROR
6987 /* Enable STORMs SP logging */
6988 REG_WR8(bp, BAR_USTRORM_INTMEM +
6989 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6990 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6991 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6992 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6993 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6994 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6995 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6996#endif
6997
b7737c9b 6998 bnx2x_phy_probe(&bp->link_params);
f85582f8 6999
34f80b04
EG		 7000 return 0;
7001}
7002
a2fbb9ea 7003
9f6c9258 7004void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 7005{
a2fbb9ea 7006 /* fastpath */
b3b83c3f 7007 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 7008 /* end of fastpath */
7009
7010 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 7011 sizeof(struct host_sp_status_block));
a2fbb9ea 7012
619c5cb6
VZ		 7013 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7014 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7015
a2fbb9ea 7016 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 7017 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7018
523224a3
DK		 7019 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
7020 bp->context.size);
7021
7022 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7023
7024 BNX2X_FREE(bp->ilt->lines);
f85582f8 7025
37b091ba 7026#ifdef BCM_CNIC
619c5cb6 7027 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7028 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7029 sizeof(struct host_hc_status_block_e2));
7030 else
7031 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7032 sizeof(struct host_hc_status_block_e1x));
f85582f8 7033
523224a3 7034 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 7035#endif
f85582f8 7036
7a9b2557 7037 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 7038
523224a3
DK		 7039 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7040 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 7041}
7042
7043static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7044{
7045 int num_groups;
50f0a562 7046 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
619c5cb6 7047
50f0a562
BW		 7048 /* number of queues for statistics is number of eth queues + FCoE */
7049 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
619c5cb6
VZ		 7050
7051 /* Total number of FW statistics requests =
50f0a562
BW		 7052 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7053 * num of queues
7054 */
7055 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
523224a3 7056
619c5cb6
VZ		 7057
7058 /* Request is built from stats_query_header and an array of
7059 * stats_query_cmd_group each of which contains
7060 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7061 * configured in the stats_query_header.
7062 */
50f0a562
BW		 7063 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7064 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
619c5cb6
VZ		 7065
7066 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7067 num_groups * sizeof(struct stats_query_cmd_group);
7068
7069 /* Data for statistics requests + stats_conter
7070 *
7071 * stats_counter holds per-STORM counters that are incremented
7072 * when STORM has finished with the current request.
50f0a562
BW		 7073 *
7074 * memory for FCoE offloaded statistics are counted anyway,
7075 * even if they will not be sent.
619c5cb6
VZ		 7076 */
7077 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7078 sizeof(struct per_pf_stats) +
50f0a562 7079 sizeof(struct fcoe_statistics_params) +
619c5cb6
VZ		 7080 sizeof(struct per_queue_stats) * num_queue_stats +
7081 sizeof(struct stats_counter);
7082
7083 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7084 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7085
7086 /* Set shortcuts */
7087 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7088 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7089
7090 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7091 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7092
7093 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7094 bp->fw_stats_req_sz;
7095 return 0;
7096
7097alloc_mem_err:
7098 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7099 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7100 return -ENOMEM;
a2fbb9ea
ET		 7101}
7102
f2e0899f 7103
9f6c9258 7104int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 7105{
523224a3 7106#ifdef BCM_CNIC
619c5cb6
VZ		 7107 if (!CHIP_IS_E1x(bp))
7108 /* size = the status block + ramrod buffers */
f2e0899f
DK		 7109 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7110 sizeof(struct host_hc_status_block_e2));
7111 else
7112 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7113 sizeof(struct host_hc_status_block_e1x));
8badd27a 7114
523224a3
DK		 7115 /* allocate searcher T2 table */
7116 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7117#endif
a2fbb9ea 7118
8badd27a 7119
523224a3
DK		 7120 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7121 sizeof(struct host_sp_status_block));
a2fbb9ea 7122
523224a3
DK		 7123 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7124 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7125
619c5cb6
VZ		 7126 /* Allocated memory for FW statistics */
7127 if (bnx2x_alloc_fw_stats_mem(bp))
7128 goto alloc_mem_err;
7129
6383c0b3 7130 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
f85582f8 7131
523224a3
DK		 7132 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
7133 bp->context.size);
65abd74d 7134
523224a3 7135 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 7136
523224a3
DK		 7137 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7138 goto alloc_mem_err;
65abd74d 7139
9f6c9258
DK		 7140 /* Slow path ring */
7141 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 7142
523224a3
DK		 7143 /* EQ */
7144 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7145 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 7146
b3b83c3f
DK		 7147
7148 /* fastpath */
7149 /* need to be done at the end, since it's self adjusting to amount
7150 * of memory available for RSS queues
7151 */
7152 if (bnx2x_alloc_fp_mem(bp))
7153 goto alloc_mem_err;
9f6c9258 7154 return 0;
e1510706 7155
9f6c9258
DK		 7156alloc_mem_err:
7157 bnx2x_free_mem(bp);
7158 return -ENOMEM;
65abd74d
YG		 7159}
7160
a2fbb9ea
ET		 7161/*
7162 * Init service functions
7163 */
a2fbb9ea 7164
619c5cb6
VZ		 7165int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7166 struct bnx2x_vlan_mac_obj *obj, bool set,
7167 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 7168{
619c5cb6
VZ		 7169 int rc;
7170 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 7171
619c5cb6 7172 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 7173
619c5cb6
VZ		 7174 /* Fill general parameters */
7175 ramrod_param.vlan_mac_obj = obj;
7176 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 7177
619c5cb6
VZ		 7178 /* Fill a user request section if needed */
7179 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7180 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 7181
619c5cb6 7182 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 7183
619c5cb6
VZ		 7184 /* Set the command: ADD or DEL */
7185 if (set)
7186 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7187 else
7188 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 7189 }
7190
619c5cb6
VZ		 7191 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7192 if (rc < 0)
7193 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7194 return rc;
a2fbb9ea
ET		 7195}
7196
619c5cb6
VZ		 7197int bnx2x_del_all_macs(struct bnx2x *bp,
7198 struct bnx2x_vlan_mac_obj *mac_obj,
7199 int mac_type, bool wait_for_comp)
e665bfda 7200{
619c5cb6
VZ		 7201 int rc;
7202 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 7203
619c5cb6
VZ		 7204 /* Wait for completion of requested */
7205 if (wait_for_comp)
7206 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 7207
619c5cb6
VZ		 7208 /* Set the mac type of addresses we want to clear */
7209 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 7210
619c5cb6
VZ		 7211 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7212 if (rc < 0)
7213 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 7214
619c5cb6 7215 return rc;
0793f83f
DK		 7216}
7217
619c5cb6 7218int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 7219{
619c5cb6 7220 unsigned long ramrod_flags = 0;
e665bfda 7221
614c76df
DK		 7222#ifdef BCM_CNIC
7223 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) {
7224 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n");
7225 return 0;
7226 }
7227#endif
7228
619c5cb6 7229 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 7230
619c5cb6
VZ		 7231 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7232 /* Eth MAC is set on RSS leading client (fp[0]) */
7233 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7234 BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 7235}
6e30dd4e 7236
619c5cb6 7237int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 7238{
619c5cb6 7239 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 7240}
a2fbb9ea 7241
d6214d7a 7242/**
e8920674 7243 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 7244 *
e8920674 7245 * @bp: driver handle
d6214d7a 7246 *
e8920674 7247 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 7248 */
9ee3d37b 7249static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 7250{
9ee3d37b 7251 switch (int_mode) {
d6214d7a
DK		 7252 case INT_MODE_MSI:
7253 bnx2x_enable_msi(bp);
7254 /* falling through... */
7255 case INT_MODE_INTx:
6383c0b3 7256 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7257 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 7258 break;
d6214d7a
DK		 7259 default:
7260 /* Set number of queues according to bp->multi_mode value */
7261 bnx2x_set_num_queues(bp);
ca00392c 7262
d6214d7a
DK		 7263 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7264 bp->num_queues);
ca00392c 7265
d6214d7a
DK		 7266 /* if we can't use MSI-X we only need one fp,
7267 * so try to enable MSI-X with the requested number of fp's
7268 * and fallback to MSI or legacy INTx with one fp
7269 */
9ee3d37b 7270 if (bnx2x_enable_msix(bp)) {
d6214d7a
DK		 7271 /* failed to enable MSI-X */
7272 if (bp->multi_mode)
7273 DP(NETIF_MSG_IFUP,
7274 "Multi requested but failed to "
7275 "enable MSI-X (%d), "
7276 "set number of queues to %d\n",
7277 bp->num_queues,
6383c0b3
AE		 7278 1 + NON_ETH_CONTEXT_USE);
7279 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7280
9ee3d37b 7281 /* Try to enable MSI */
d6214d7a
DK		 7282 if (!(bp->flags & DISABLE_MSI_FLAG))
7283 bnx2x_enable_msi(bp);
7284 }
9f6c9258
DK		 7285 break;
7286 }
a2fbb9ea
ET		 7287}
7288
c2bff63f
DK		 7289/* must be called prioir to any HW initializations */
7290static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7291{
7292 return L2_ILT_LINES(bp);
7293}
7294
523224a3
DK		 7295void bnx2x_ilt_set_info(struct bnx2x *bp)
7296{
7297 struct ilt_client_info *ilt_client;
7298 struct bnx2x_ilt *ilt = BP_ILT(bp);
7299 u16 line = 0;
7300
7301 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7302 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7303
7304 /* CDU */
7305 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7306 ilt_client->client_num = ILT_CLIENT_CDU;
7307 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7308 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7309 ilt_client->start = line;
619c5cb6 7310 line += bnx2x_cid_ilt_lines(bp);
523224a3
DK		 7311#ifdef BCM_CNIC
7312 line += CNIC_ILT_LINES;
7313#endif
7314 ilt_client->end = line - 1;
7315
7316 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7317 "flags 0x%x, hw psz %d\n",
7318 ilt_client->start,
7319 ilt_client->end,
7320 ilt_client->page_size,
7321 ilt_client->flags,
7322 ilog2(ilt_client->page_size >> 12));
7323
7324 /* QM */
7325 if (QM_INIT(bp->qm_cid_count)) {
7326 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7327 ilt_client->client_num = ILT_CLIENT_QM;
7328 ilt_client->page_size = QM_ILT_PAGE_SZ;
7329 ilt_client->flags = 0;
7330 ilt_client->start = line;
7331
7332 /* 4 bytes for each cid */
7333 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7334 QM_ILT_PAGE_SZ);
7335
7336 ilt_client->end = line - 1;
7337
7338 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7339 "flags 0x%x, hw psz %d\n",
7340 ilt_client->start,
7341 ilt_client->end,
7342 ilt_client->page_size,
7343 ilt_client->flags,
7344 ilog2(ilt_client->page_size >> 12));
7345
7346 }
7347 /* SRC */
7348 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7349#ifdef BCM_CNIC
7350 ilt_client->client_num = ILT_CLIENT_SRC;
7351 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7352 ilt_client->flags = 0;
7353 ilt_client->start = line;
7354 line += SRC_ILT_LINES;
7355 ilt_client->end = line - 1;
7356
7357 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7358 "flags 0x%x, hw psz %d\n",
7359 ilt_client->start,
7360 ilt_client->end,
7361 ilt_client->page_size,
7362 ilt_client->flags,
7363 ilog2(ilt_client->page_size >> 12));
7364
7365#else
7366 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7367#endif
9f6c9258 7368
523224a3
DK		 7369 /* TM */
7370 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7371#ifdef BCM_CNIC
7372 ilt_client->client_num = ILT_CLIENT_TM;
7373 ilt_client->page_size = TM_ILT_PAGE_SZ;
7374 ilt_client->flags = 0;
7375 ilt_client->start = line;
7376 line += TM_ILT_LINES;
7377 ilt_client->end = line - 1;
7378
7379 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7380 "flags 0x%x, hw psz %d\n",
7381 ilt_client->start,
7382 ilt_client->end,
7383 ilt_client->page_size,
7384 ilt_client->flags,
7385 ilog2(ilt_client->page_size >> 12));
9f6c9258 7386
523224a3
DK		 7387#else
7388 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7389#endif
619c5cb6 7390 BUG_ON(line > ILT_MAX_LINES);
523224a3 7391}
f85582f8 7392
619c5cb6
VZ		 7393/**
7394 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7395 *
7396 * @bp: driver handle
7397 * @fp: pointer to fastpath
7398 * @init_params: pointer to parameters structure
7399 *
7400 * parameters configured:
7401 * - HC configuration
7402 * - Queue's CDU context
7403 */
7404static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7405 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 7406{
6383c0b3
AE		 7407
7408 u8 cos;
619c5cb6
VZ		 7409 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7410 if (!IS_FCOE_FP(fp)) {
7411 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7412 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7413
7414 /* If HC is supporterd, enable host coalescing in the transition
7415 * to INIT state.
7416 */
7417 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7418 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7419
7420 /* HC rate */
7421 init_params->rx.hc_rate = bp->rx_ticks ?
7422 (1000000 / bp->rx_ticks) : 0;
7423 init_params->tx.hc_rate = bp->tx_ticks ?
7424 (1000000 / bp->tx_ticks) : 0;
7425
7426 /* FW SB ID */
7427 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7428 fp->fw_sb_id;
7429
7430 /*
7431 * CQ index among the SB indices: FCoE clients uses the default
7432 * SB, therefore it's different.
7433 */
6383c0b3
AE		 7434 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7435 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 7436 }
7437
6383c0b3
AE		 7438 /* set maximum number of COSs supported by this queue */
7439 init_params->max_cos = fp->max_cos;
7440
94f05b0f 7441 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 7442 fp->index, init_params->max_cos);
7443
7444 /* set the context pointers queue object */
7445 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7446 init_params->cxts[cos] =
7447 &bp->context.vcxt[fp->txdata[cos].cid].eth;
619c5cb6
VZ		 7448}
7449
6383c0b3
AE		 7450int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7451 struct bnx2x_queue_state_params *q_params,
7452 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7453 int tx_index, bool leading)
7454{
7455 memset(tx_only_params, 0, sizeof(*tx_only_params));
7456
7457 /* Set the command */
7458 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7459
7460 /* Set tx-only QUEUE flags: don't zero statistics */
7461 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7462
7463 /* choose the index of the cid to send the slow path on */
7464 tx_only_params->cid_index = tx_index;
7465
7466 /* Set general TX_ONLY_SETUP parameters */
7467 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7468
7469 /* Set Tx TX_ONLY_SETUP parameters */
7470 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7471
7472 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7473 "cos %d, primary cid %d, cid %d, "
94f05b0f 7474 "client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 7475 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7476 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7477 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7478
7479 /* send the ramrod */
7480 return bnx2x_queue_state_change(bp, q_params);
7481}
7482
7483
619c5cb6
VZ		 7484/**
7485 * bnx2x_setup_queue - setup queue
7486 *
7487 * @bp: driver handle
7488 * @fp: pointer to fastpath
7489 * @leading: is leading
7490 *
7491 * This function performs 2 steps in a Queue state machine
7492 * actually: 1) RESET->INIT 2) INIT->SETUP
7493 */
7494
7495int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7496 bool leading)
7497{
7498 struct bnx2x_queue_state_params q_params = {0};
7499 struct bnx2x_queue_setup_params *setup_params =
7500 &q_params.params.setup;
6383c0b3
AE		 7501 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7502 &q_params.params.tx_only;
a2fbb9ea 7503 int rc;
6383c0b3
AE		 7504 u8 tx_index;
7505
94f05b0f 7506 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index);
a2fbb9ea 7507
ec6ba945
VZ		 7508 /* reset IGU state skip FCoE L2 queue */
7509 if (!IS_FCOE_FP(fp))
7510 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 7511 IGU_INT_ENABLE, 0);
a2fbb9ea 7512
619c5cb6
VZ		 7513 q_params.q_obj = &fp->q_obj;
7514 /* We want to wait for completion in this context */
7515 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7516
619c5cb6
VZ		 7517 /* Prepare the INIT parameters */
7518 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 7519
619c5cb6
VZ		 7520 /* Set the command */
7521 q_params.cmd = BNX2X_Q_CMD_INIT;
7522
7523 /* Change the state to INIT */
7524 rc = bnx2x_queue_state_change(bp, &q_params);
7525 if (rc) {
6383c0b3 7526 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 7527 return rc;
7528 }
ec6ba945 7529
94f05b0f 7530 DP(BNX2X_MSG_SP, "init complete\n");
6383c0b3
AE		 7531
7532
619c5cb6
VZ		 7533 /* Now move the Queue to the SETUP state... */
7534 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 7535
619c5cb6
VZ		 7536 /* Set QUEUE flags */
7537 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 7538
619c5cb6 7539 /* Set general SETUP parameters */
6383c0b3
AE		 7540 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7541 FIRST_TX_COS_INDEX);
619c5cb6 7542
6383c0b3 7543 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 7544 &setup_params->rxq_params);
7545
6383c0b3
AE		 7546 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7547 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 7548
7549 /* Set the command */
7550 q_params.cmd = BNX2X_Q_CMD_SETUP;
7551
7552 /* Change the state to SETUP */
7553 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 7554 if (rc) {
7555 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7556 return rc;
7557 }
7558
7559 /* loop through the relevant tx-only indices */
7560 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7561 tx_index < fp->max_cos;
7562 tx_index++) {
7563
7564 /* prepare and send tx-only ramrod*/
7565 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7566 tx_only_params, tx_index, leading);
7567 if (rc) {
7568 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7569 fp->index, tx_index);
7570 return rc;
7571 }
7572 }
523224a3 7573
34f80b04 7574 return rc;
a2fbb9ea
ET		 7575}
7576
619c5cb6 7577static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 7578{
619c5cb6 7579 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 7580 struct bnx2x_fp_txdata *txdata;
619c5cb6 7581 struct bnx2x_queue_state_params q_params = {0};
6383c0b3
AE		 7582 int rc, tx_index;
7583
94f05b0f 7584 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 7585
619c5cb6
VZ		 7586 q_params.q_obj = &fp->q_obj;
7587 /* We want to wait for completion in this context */
7588 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7589
6383c0b3
AE		 7590
7591 /* close tx-only connections */
7592 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7593 tx_index < fp->max_cos;
7594 tx_index++){
7595
7596 /* ascertain this is a normal queue*/
7597 txdata = &fp->txdata[tx_index];
7598
94f05b0f 7599 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n",
6383c0b3
AE		 7600 txdata->txq_index);
7601
7602 /* send halt terminate on tx-only connection */
7603 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7604 memset(&q_params.params.terminate, 0,
7605 sizeof(q_params.params.terminate));
7606 q_params.params.terminate.cid_index = tx_index;
7607
7608 rc = bnx2x_queue_state_change(bp, &q_params);
7609 if (rc)
7610 return rc;
7611
7612 /* send halt terminate on tx-only connection */
7613 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7614 memset(&q_params.params.cfc_del, 0,
7615 sizeof(q_params.params.cfc_del));
7616 q_params.params.cfc_del.cid_index = tx_index;
7617 rc = bnx2x_queue_state_change(bp, &q_params);
7618 if (rc)
7619 return rc;
7620 }
7621 /* Stop the primary connection: */
7622 /* ...halt the connection */
619c5cb6
VZ		 7623 q_params.cmd = BNX2X_Q_CMD_HALT;
7624 rc = bnx2x_queue_state_change(bp, &q_params);
7625 if (rc)
da5a662a 7626 return rc;
a2fbb9ea 7627
6383c0b3 7628 /* ...terminate the connection */
619c5cb6 7629 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 7630 memset(&q_params.params.terminate, 0,
7631 sizeof(q_params.params.terminate));
7632 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 7633 rc = bnx2x_queue_state_change(bp, &q_params);
7634 if (rc)
523224a3 7635 return rc;
6383c0b3 7636 /* ...delete cfc entry */
619c5cb6 7637 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 7638 memset(&q_params.params.cfc_del, 0,
7639 sizeof(q_params.params.cfc_del));
7640 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 7641 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 7642}
7643
7644
34f80b04
EG		 7645static void bnx2x_reset_func(struct bnx2x *bp)
7646{
7647 int port = BP_PORT(bp);
7648 int func = BP_FUNC(bp);
f2e0899f 7649 int i;
523224a3
DK		 7650
7651 /* Disable the function in the FW */
7652 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7653 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7654 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7655 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7656
7657 /* FP SBs */
ec6ba945 7658 for_each_eth_queue(bp, i) {
523224a3 7659 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 7660 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7661 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7662 SB_DISABLED);
523224a3
DK		 7663 }
7664
619c5cb6
VZ		 7665#ifdef BCM_CNIC
7666 /* CNIC SB */
7667 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7668 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7669 SB_DISABLED);
7670#endif
523224a3 7671 /* SP SB */
619c5cb6 7672 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7673 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7674 SB_DISABLED);
523224a3
DK		 7675
7676 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7677 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7678 0);
34f80b04
EG		 7679
7680 /* Configure IGU */
f2e0899f
DK		 7681 if (bp->common.int_block == INT_BLOCK_HC) {
7682 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7683 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7684 } else {
7685 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7686 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7687 }
34f80b04 7688
37b091ba
MC		 7689#ifdef BCM_CNIC
7690 /* Disable Timer scan */
7691 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7692 /*
7693 * Wait for at least 10ms and up to 2 second for the timers scan to
7694 * complete
7695 */
7696 for (i = 0; i < 200; i++) {
7697 msleep(10);
7698 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7699 break;
7700 }
7701#endif
34f80b04 7702 /* Clear ILT */
f2e0899f
DK		 7703 bnx2x_clear_func_ilt(bp, func);
7704
7705 /* Timers workaround bug for E2: if this is vnic-3,
7706 * we need to set the entire ilt range for this timers.
7707 */
619c5cb6 7708 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 7709 struct ilt_client_info ilt_cli;
7710 /* use dummy TM client */
7711 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7712 ilt_cli.start = 0;
7713 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7714 ilt_cli.client_num = ILT_CLIENT_TM;
7715
7716 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7717 }
7718
7719 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 7720 if (!CHIP_IS_E1x(bp))
f2e0899f 7721 bnx2x_pf_disable(bp);
523224a3
DK		 7722
7723 bp->dmae_ready = 0;
34f80b04
EG		 7724}
7725
7726static void bnx2x_reset_port(struct bnx2x *bp)
7727{
7728 int port = BP_PORT(bp);
7729 u32 val;
7730
619c5cb6
VZ		 7731 /* Reset physical Link */
7732 bnx2x__link_reset(bp);
7733
34f80b04
EG		 7734 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7735
7736 /* Do not rcv packets to BRB */
7737 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7738 /* Do not direct rcv packets that are not for MCP to the BRB */
7739 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7740 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7741
7742 /* Configure AEU */
7743 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7744
7745 msleep(100);
7746 /* Check for BRB port occupancy */
7747 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7748 if (val)
7749 DP(NETIF_MSG_IFDOWN,
33471629 7750 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7751
7752 /* TODO: Close Doorbell port? */
7753}
7754
619c5cb6 7755static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 7756{
619c5cb6 7757 struct bnx2x_func_state_params func_params = {0};
34f80b04 7758
619c5cb6
VZ		 7759 /* Prepare parameters for function state transitions */
7760 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 7761
619c5cb6
VZ		 7762 func_params.f_obj = &bp->func_obj;
7763 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 7764
619c5cb6 7765 func_params.params.hw_init.load_phase = load_code;
49d66772 7766
619c5cb6 7767 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 7768}
7769
619c5cb6 7770static inline int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 7771{
619c5cb6
VZ		 7772 struct bnx2x_func_state_params func_params = {0};
7773 int rc;
228241eb 7774
619c5cb6
VZ		 7775 /* Prepare parameters for function state transitions */
7776 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7777 func_params.f_obj = &bp->func_obj;
7778 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 7779
619c5cb6
VZ		 7780 /*
7781 * Try to stop the function the 'good way'. If fails (in case
7782 * of a parity error during bnx2x_chip_cleanup()) and we are
7783 * not in a debug mode, perform a state transaction in order to
7784 * enable further HW_RESET transaction.
7785 */
7786 rc = bnx2x_func_state_change(bp, &func_params);
7787 if (rc) {
34f80b04 7788#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 7789 return rc;
34f80b04 7790#else
619c5cb6
VZ		 7791 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7792 "transaction\n");
7793 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7794 return bnx2x_func_state_change(bp, &func_params);
34f80b04 7795#endif
228241eb 7796 }
a2fbb9ea 7797
619c5cb6
VZ		 7798 return 0;
7799}
523224a3 7800
619c5cb6
VZ		 7801/**
7802 * bnx2x_send_unload_req - request unload mode from the MCP.
7803 *
7804 * @bp: driver handle
7805 * @unload_mode: requested function's unload mode
7806 *
7807 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7808 */
7809u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7810{
7811 u32 reset_code = 0;
7812 int port = BP_PORT(bp);
3101c2bc 7813
619c5cb6 7814 /* Select the UNLOAD request mode */
65abd74d
YG		 7815 if (unload_mode == UNLOAD_NORMAL)
7816 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7817
7d0446c2 7818 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7819 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7820
7d0446c2 7821 else if (bp->wol) {
65abd74d
YG		 7822 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7823 u8 *mac_addr = bp->dev->dev_addr;
7824 u32 val;
f9977903
DK		 7825 u16 pmc;
7826
65abd74d 7827 /* The mac address is written to entries 1-4 to
f9977903
DK		 7828 * preserve entry 0 which is used by the PMF
7829 */
3395a033 7830 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 7831
7832 val = (mac_addr[0] << 8) | mac_addr[1];
7833 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7834
7835 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7836 (mac_addr[4] << 8) | mac_addr[5];
7837 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7838
f9977903
DK		 7839 /* Enable the PME and clear the status */
7840 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
7841 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
7842 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
7843
65abd74d
YG		 7844 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7845
7846 } else
7847 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7848
619c5cb6
VZ		 7849 /* Send the request to the MCP */
7850 if (!BP_NOMCP(bp))
7851 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7852 else {
7853 int path = BP_PATH(bp);
7854
7855 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7856 "%d, %d, %d\n",
7857 path, load_count[path][0], load_count[path][1],
7858 load_count[path][2]);
7859 load_count[path][0]--;
7860 load_count[path][1 + port]--;
7861 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7862 "%d, %d, %d\n",
7863 path, load_count[path][0], load_count[path][1],
7864 load_count[path][2]);
7865 if (load_count[path][0] == 0)
7866 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7867 else if (load_count[path][1 + port] == 0)
7868 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7869 else
7870 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7871 }
7872
7873 return reset_code;
7874}
7875
7876/**
7877 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7878 *
7879 * @bp: driver handle
7880 */
7881void bnx2x_send_unload_done(struct bnx2x *bp)
7882{
7883 /* Report UNLOAD_DONE to MCP */
7884 if (!BP_NOMCP(bp))
7885 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7886}
7887
6debea87
DK		 7888static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7889{
7890 int tout = 50;
7891 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7892
7893 if (!bp->port.pmf)
7894 return 0;
7895
7896 /*
7897 * (assumption: No Attention from MCP at this stage)
7898 * PMF probably in the middle of TXdisable/enable transaction
7899 * 1. Sync IRS for default SB
7900 * 2. Sync SP queue - this guarantes us that attention handling started
7901 * 3. Wait, that TXdisable/enable transaction completes
7902 *
7903 * 1+2 guranty that if DCBx attention was scheduled it already changed
7904 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7905 * received complettion for the transaction the state is TX_STOPPED.
7906 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7907 * transaction.
7908 */
7909
7910 /* make sure default SB ISR is done */
7911 if (msix)
7912 synchronize_irq(bp->msix_table[0].vector);
7913 else
7914 synchronize_irq(bp->pdev->irq);
7915
7916 flush_workqueue(bnx2x_wq);
7917
7918 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7919 BNX2X_F_STATE_STARTED && tout--)
7920 msleep(20);
7921
7922 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7923 BNX2X_F_STATE_STARTED) {
7924#ifdef BNX2X_STOP_ON_ERROR
7925 return -EBUSY;
7926#else
7927 /*
7928 * Failed to complete the transaction in a "good way"
7929 * Force both transactions with CLR bit
7930 */
7931 struct bnx2x_func_state_params func_params = {0};
7932
7933 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7934 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7935
7936 func_params.f_obj = &bp->func_obj;
7937 __set_bit(RAMROD_DRV_CLR_ONLY,
7938 &func_params.ramrod_flags);
7939
7940 /* STARTED-->TX_ST0PPED */
7941 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7942 bnx2x_func_state_change(bp, &func_params);
7943
7944 /* TX_ST0PPED-->STARTED */
7945 func_params.cmd = BNX2X_F_CMD_TX_START;
7946 return bnx2x_func_state_change(bp, &func_params);
7947#endif
7948 }
7949
7950 return 0;
7951}
7952
619c5cb6
VZ		 7953void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7954{
7955 int port = BP_PORT(bp);
6383c0b3
AE		 7956 int i, rc = 0;
7957 u8 cos;
619c5cb6
VZ		 7958 struct bnx2x_mcast_ramrod_params rparam = {0};
7959 u32 reset_code;
7960
7961 /* Wait until tx fastpath tasks complete */
7962 for_each_tx_queue(bp, i) {
7963 struct bnx2x_fastpath *fp = &bp->fp[i];
7964
6383c0b3
AE		 7965 for_each_cos_in_tx_queue(fp, cos)
7966 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
619c5cb6
VZ		 7967#ifdef BNX2X_STOP_ON_ERROR
7968 if (rc)
7969 return;
7970#endif
7971 }
7972
7973 /* Give HW time to discard old tx messages */
7974 usleep_range(1000, 1000);
7975
7976 /* Clean all ETH MACs */
7977 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7978 if (rc < 0)
7979 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7980
7981 /* Clean up UC list */
7982 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7983 true);
7984 if (rc < 0)
7985 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7986 "%d\n", rc);
7987
7988 /* Disable LLH */
7989 if (!CHIP_IS_E1(bp))
7990 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7991
7992 /* Set "drop all" (stop Rx).
7993 * We need to take a netif_addr_lock() here in order to prevent
7994 * a race between the completion code and this code.
7995 */
7996 netif_addr_lock_bh(bp->dev);
7997 /* Schedule the rx_mode command */
7998 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7999 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8000 else
8001 bnx2x_set_storm_rx_mode(bp);
8002
8003 /* Cleanup multicast configuration */
8004 rparam.mcast_obj = &bp->mcast_obj;
8005 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8006 if (rc < 0)
8007 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8008
8009 netif_addr_unlock_bh(bp->dev);
8010
8011
6debea87
DK		 8012
8013 /*
8014 * Send the UNLOAD_REQUEST to the MCP. This will return if
8015 * this function should perform FUNC, PORT or COMMON HW
8016 * reset.
8017 */
8018 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8019
8020 /*
8021 * (assumption: No Attention from MCP at this stage)
8022 * PMF probably in the middle of TXdisable/enable transaction
8023 */
8024 rc = bnx2x_func_wait_started(bp);
8025 if (rc) {
8026 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8027#ifdef BNX2X_STOP_ON_ERROR
8028 return;
8029#endif
8030 }
8031
34f80b04 8032 /* Close multi and leading connections
619c5cb6
VZ		 8033 * Completions for ramrods are collected in a synchronous way
8034 */
523224a3 8035 for_each_queue(bp, i)
619c5cb6 8036 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 8037#ifdef BNX2X_STOP_ON_ERROR
8038 return;
8039#else
228241eb 8040 goto unload_error;
523224a3 8041#endif
619c5cb6
VZ		 8042 /* If SP settings didn't get completed so far - something
8043 * very wrong has happen.
8044 */
8045 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8046 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 8047
619c5cb6
VZ		 8048#ifndef BNX2X_STOP_ON_ERROR
8049unload_error:
8050#endif
523224a3 8051 rc = bnx2x_func_stop(bp);
da5a662a 8052 if (rc) {
523224a3 8053 BNX2X_ERR("Function stop failed!\n");
da5a662a 8054#ifdef BNX2X_STOP_ON_ERROR
523224a3 8055 return;
523224a3 8056#endif
34f80b04 8057 }
a2fbb9ea 8058
523224a3
DK		 8059 /* Disable HW interrupts, NAPI */
8060 bnx2x_netif_stop(bp, 1);
8061
8062 /* Release IRQs */
d6214d7a 8063 bnx2x_free_irq(bp);
523224a3 8064
a2fbb9ea 8065 /* Reset the chip */
619c5cb6
VZ		 8066 rc = bnx2x_reset_hw(bp, reset_code);
8067 if (rc)
8068 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 8069
356e2385 8070
619c5cb6
VZ		 8071 /* Report UNLOAD_DONE to MCP */
8072 bnx2x_send_unload_done(bp);
72fd0718
VZ		 8073}
8074
9f6c9258 8075void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 8076{
8077 u32 val;
8078
8079 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
8080
8081 if (CHIP_IS_E1(bp)) {
8082 int port = BP_PORT(bp);
8083 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8084 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8085
8086 val = REG_RD(bp, addr);
8087 val &= ~(0x300);
8088 REG_WR(bp, addr, val);
619c5cb6 8089 } else {
72fd0718
VZ		 8090 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8091 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8092 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8093 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8094 }
8095}
8096
72fd0718
VZ		 8097/* Close gates #2, #3 and #4: */
8098static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8099{
c9ee9206 8100 u32 val;
72fd0718
VZ		 8101
8102 /* Gates #2 and #4a are closed/opened for "not E1" only */
8103 if (!CHIP_IS_E1(bp)) {
8104 /* #4 */
c9ee9206 8105 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 8106 /* #2 */
c9ee9206 8107 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 8108 }
8109
8110 /* #3 */
c9ee9206
VZ		 8111 if (CHIP_IS_E1x(bp)) {
8112 /* Prevent interrupts from HC on both ports */
8113 val = REG_RD(bp, HC_REG_CONFIG_1);
8114 REG_WR(bp, HC_REG_CONFIG_1,
8115 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8116 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8117
8118 val = REG_RD(bp, HC_REG_CONFIG_0);
8119 REG_WR(bp, HC_REG_CONFIG_0,
8120 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8121 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8122 } else {
8123 /* Prevent incomming interrupts in IGU */
8124 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8125
8126 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8127 (!close) ?
8128 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8129 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8130 }
72fd0718
VZ		 8131
8132 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
8133 close ? "closing" : "opening");
8134 mmiowb();
8135}
8136
8137#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8138
8139static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8140{
8141 /* Do some magic... */
8142 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8143 *magic_val = val & SHARED_MF_CLP_MAGIC;
8144 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8145}
8146
e8920674
DK		 8147/**
8148 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 8149 *
e8920674
DK		 8150 * @bp: driver handle
8151 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 8152 */
8153static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8154{
8155 /* Restore the `magic' bit value... */
72fd0718
VZ		 8156 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8157 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8158 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8159}
8160
f85582f8 8161/**
e8920674 8162 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 8163 *
e8920674
DK		 8164 * @bp: driver handle
8165 * @magic_val: old value of 'magic' bit.
8166 *
8167 * Takes care of CLP configurations.
72fd0718
VZ		 8168 */
8169static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8170{
8171 u32 shmem;
8172 u32 validity_offset;
8173
8174 DP(NETIF_MSG_HW, "Starting\n");
8175
8176 /* Set `magic' bit in order to save MF config */
8177 if (!CHIP_IS_E1(bp))
8178 bnx2x_clp_reset_prep(bp, magic_val);
8179
8180 /* Get shmem offset */
8181 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8182 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8183
8184 /* Clear validity map flags */
8185 if (shmem > 0)
8186 REG_WR(bp, shmem + validity_offset, 0);
8187}
8188
8189#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8190#define MCP_ONE_TIMEOUT 100 /* 100 ms */
8191
e8920674
DK		 8192/**
8193 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 8194 *
e8920674 8195 * @bp: driver handle
72fd0718
VZ		 8196 */
8197static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
8198{
8199 /* special handling for emulation and FPGA,
8200 wait 10 times longer */
8201 if (CHIP_REV_IS_SLOW(bp))
8202 msleep(MCP_ONE_TIMEOUT*10);
8203 else
8204 msleep(MCP_ONE_TIMEOUT);
8205}
8206
1b6e2ceb
DK		 8207/*
8208 * initializes bp->common.shmem_base and waits for validity signature to appear
8209 */
8210static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 8211{
1b6e2ceb
DK		 8212 int cnt = 0;
8213 u32 val = 0;
72fd0718 8214
1b6e2ceb
DK		 8215 do {
8216 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8217 if (bp->common.shmem_base) {
8218 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8219 if (val & SHR_MEM_VALIDITY_MB)
8220 return 0;
8221 }
72fd0718 8222
1b6e2ceb 8223 bnx2x_mcp_wait_one(bp);
72fd0718 8224
1b6e2ceb 8225 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 8226
1b6e2ceb 8227 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 8228
1b6e2ceb
DK		 8229 return -ENODEV;
8230}
72fd0718 8231
1b6e2ceb
DK		 8232static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8233{
8234 int rc = bnx2x_init_shmem(bp);
72fd0718 8235
72fd0718
VZ		 8236 /* Restore the `magic' bit value */
8237 if (!CHIP_IS_E1(bp))
8238 bnx2x_clp_reset_done(bp, magic_val);
8239
8240 return rc;
8241}
8242
8243static void bnx2x_pxp_prep(struct bnx2x *bp)
8244{
8245 if (!CHIP_IS_E1(bp)) {
8246 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8247 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 8248 mmiowb();
8249 }
8250}
8251
8252/*
8253 * Reset the whole chip except for:
8254 * - PCIE core
8255 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8256 * one reset bit)
8257 * - IGU
8258 * - MISC (including AEU)
8259 * - GRC
8260 * - RBCN, RBCP
8261 */
c9ee9206 8262static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 8263{
8264 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 8265 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 8266
8267 /*
8268 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8269 * (per chip) blocks.
8270 */
8271 global_bits2 =
8272 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8273 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 8274
8736c826 8275 /* Don't reset the following blocks */
72fd0718
VZ		 8276 not_reset_mask1 =
8277 MISC_REGISTERS_RESET_REG_1_RST_HC |
8278 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8279 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8280
8281 not_reset_mask2 =
c9ee9206 8282 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 8283 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8284 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8285 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8286 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8287 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8288 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 8289 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8290 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8291 MISC_REGISTERS_RESET_REG_2_PGLC;
72fd0718 8292
8736c826
VZ		 8293 /*
8294 * Keep the following blocks in reset:
8295 * - all xxMACs are handled by the bnx2x_link code.
8296 */
8297 stay_reset2 =
8298 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8299 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8300 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8301 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8302 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8303 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8304 MISC_REGISTERS_RESET_REG_2_XMAC |
8305 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8306
8307 /* Full reset masks according to the chip */
72fd0718
VZ		 8308 reset_mask1 = 0xffffffff;
8309
8310 if (CHIP_IS_E1(bp))
8311 reset_mask2 = 0xffff;
8736c826 8312 else if (CHIP_IS_E1H(bp))
72fd0718 8313 reset_mask2 = 0x1ffff;
8736c826
VZ		 8314 else if (CHIP_IS_E2(bp))
8315 reset_mask2 = 0xfffff;
8316 else /* CHIP_IS_E3 */
8317 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 8318
8319 /* Don't reset global blocks unless we need to */
8320 if (!global)
8321 reset_mask2 &= ~global_bits2;
8322
8323 /*
8324 * In case of attention in the QM, we need to reset PXP
8325 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8326 * because otherwise QM reset would release 'close the gates' shortly
8327 * before resetting the PXP, then the PSWRQ would send a write
8328 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8329 * read the payload data from PSWWR, but PSWWR would not
8330 * respond. The write queue in PGLUE would stuck, dmae commands
8331 * would not return. Therefore it's important to reset the second
8332 * reset register (containing the
8333 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8334 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8335 * bit).
8336 */
72fd0718
VZ		 8337 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8338 reset_mask2 & (~not_reset_mask2));
8339
c9ee9206
VZ		 8340 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8341 reset_mask1 & (~not_reset_mask1));
8342
72fd0718
VZ		 8343 barrier();
8344 mmiowb();
8345
8736c826
VZ		 8346 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8347 reset_mask2 & (~stay_reset2));
8348
8349 barrier();
8350 mmiowb();
8351
c9ee9206 8352 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 8353 mmiowb();
8354}
8355
c9ee9206
VZ		 8356/**
8357 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8358 * It should get cleared in no more than 1s.
8359 *
8360 * @bp: driver handle
8361 *
8362 * It should get cleared in no more than 1s. Returns 0 if
8363 * pending writes bit gets cleared.
8364 */
8365static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8366{
8367 u32 cnt = 1000;
8368 u32 pend_bits = 0;
8369
8370 do {
8371 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8372
8373 if (pend_bits == 0)
8374 break;
8375
8376 usleep_range(1000, 1000);
8377 } while (cnt-- > 0);
8378
8379 if (cnt <= 0) {
8380 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8381 pend_bits);
8382 return -EBUSY;
8383 }
8384
8385 return 0;
8386}
8387
8388static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 8389{
8390 int cnt = 1000;
8391 u32 val = 0;
8392 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8393
8394
8395 /* Empty the Tetris buffer, wait for 1s */
8396 do {
8397 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8398 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8399 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8400 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8401 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8402 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8403 ((port_is_idle_0 & 0x1) == 0x1) &&
8404 ((port_is_idle_1 & 0x1) == 0x1) &&
8405 (pgl_exp_rom2 == 0xffffffff))
8406 break;
c9ee9206 8407 usleep_range(1000, 1000);
72fd0718
VZ		 8408 } while (cnt-- > 0);
8409
8410 if (cnt <= 0) {
8411 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8412 " are still"
8413 " outstanding read requests after 1s!\n");
8414 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8415 " port_is_idle_0=0x%08x,"
8416 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8417 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8418 pgl_exp_rom2);
8419 return -EAGAIN;
8420 }
8421
8422 barrier();
8423
8424 /* Close gates #2, #3 and #4 */
8425 bnx2x_set_234_gates(bp, true);
8426
c9ee9206
VZ		 8427 /* Poll for IGU VQs for 57712 and newer chips */
8428 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8429 return -EAGAIN;
8430
8431
72fd0718
VZ		 8432 /* TBD: Indicate that "process kill" is in progress to MCP */
8433
8434 /* Clear "unprepared" bit */
8435 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8436 barrier();
8437
8438 /* Make sure all is written to the chip before the reset */
8439 mmiowb();
8440
8441 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8442 * PSWHST, GRC and PSWRD Tetris buffer.
8443 */
c9ee9206 8444 usleep_range(1000, 1000);
72fd0718
VZ		 8445
8446 /* Prepare to chip reset: */
8447 /* MCP */
c9ee9206
VZ		 8448 if (global)
8449 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 8450
8451 /* PXP */
8452 bnx2x_pxp_prep(bp);
8453 barrier();
8454
8455 /* reset the chip */
c9ee9206 8456 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 8457 barrier();
8458
8459 /* Recover after reset: */
8460 /* MCP */
c9ee9206 8461 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 8462 return -EAGAIN;
8463
c9ee9206
VZ		 8464 /* TBD: Add resetting the NO_MCP mode DB here */
8465
72fd0718
VZ		 8466 /* PXP */
8467 bnx2x_pxp_prep(bp);
8468
8469 /* Open the gates #2, #3 and #4 */
8470 bnx2x_set_234_gates(bp, false);
8471
8472 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8473 * reset state, re-enable attentions. */
8474
a2fbb9ea
ET		 8475 return 0;
8476}
8477
c9ee9206 8478int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 8479{
8480 int rc = 0;
c9ee9206 8481 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 8482 u32 load_code;
8483
8484 /* if not going to reset MCP - load "fake" driver to reset HW while
8485 * driver is owner of the HW
8486 */
8487 if (!global && !BP_NOMCP(bp)) {
8488 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0);
8489 if (!load_code) {
8490 BNX2X_ERR("MCP response failure, aborting\n");
8491 rc = -EAGAIN;
8492 goto exit_leader_reset;
8493 }
8494 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
8495 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
8496 BNX2X_ERR("MCP unexpected resp, aborting\n");
8497 rc = -EAGAIN;
8498 goto exit_leader_reset2;
8499 }
8500 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
8501 if (!load_code) {
8502 BNX2X_ERR("MCP response failure, aborting\n");
8503 rc = -EAGAIN;
8504 goto exit_leader_reset2;
8505 }
8506 }
c9ee9206 8507
72fd0718 8508 /* Try to recover after the failure */
c9ee9206
VZ		 8509 if (bnx2x_process_kill(bp, global)) {
8510 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8511 "Aii!\n", BP_PATH(bp));
72fd0718 8512 rc = -EAGAIN;
95c6c616 8513 goto exit_leader_reset2;
72fd0718
VZ		 8514 }
8515
c9ee9206
VZ		 8516 /*
8517 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8518 * state.
8519 */
72fd0718 8520 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 8521 if (global)
8522 bnx2x_clear_reset_global(bp);
72fd0718 8523
95c6c616
AE		 8524exit_leader_reset2:
8525 /* unload "fake driver" if it was loaded */
8526 if (!global && !BP_NOMCP(bp)) {
8527 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
8528 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8529 }
72fd0718
VZ		 8530exit_leader_reset:
8531 bp->is_leader = 0;
c9ee9206
VZ		 8532 bnx2x_release_leader_lock(bp);
8533 smp_mb();
72fd0718
VZ		 8534 return rc;
8535}
8536
c9ee9206
VZ		 8537static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8538{
8539 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8540
8541 /* Disconnect this device */
8542 netif_device_detach(bp->dev);
8543
8544 /*
8545 * Block ifup for all function on this engine until "process kill"
8546 * or power cycle.
8547 */
8548 bnx2x_set_reset_in_progress(bp);
8549
8550 /* Shut down the power */
8551 bnx2x_set_power_state(bp, PCI_D3hot);
8552
8553 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8554
8555 smp_mb();
8556}
8557
8558/*
8559 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 8560 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 8561 * will never be called when netif_running(bp->dev) is false.
8562 */
8563static void bnx2x_parity_recover(struct bnx2x *bp)
8564{
c9ee9206 8565 bool global = false;
95c6c616 8566 bool is_parity;
c9ee9206 8567
72fd0718
VZ		 8568 DP(NETIF_MSG_HW, "Handling parity\n");
8569 while (1) {
8570 switch (bp->recovery_state) {
8571 case BNX2X_RECOVERY_INIT:
8572 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 8573 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
8574 WARN_ON(!is_parity);
c9ee9206 8575
72fd0718 8576 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 8577 if (bnx2x_trylock_leader_lock(bp)) {
8578 bnx2x_set_reset_in_progress(bp);
8579 /*
8580 * Check if there is a global attention and if
8581 * there was a global attention, set the global
8582 * reset bit.
8583 */
8584
8585 if (global)
8586 bnx2x_set_reset_global(bp);
8587
72fd0718 8588 bp->is_leader = 1;
c9ee9206 8589 }
72fd0718
VZ		 8590
8591 /* Stop the driver */
8592 /* If interface has been removed - break */
8593 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8594 return;
8595
8596 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 8597
c9ee9206
VZ		 8598 /* Ensure "is_leader", MCP command sequence and
8599 * "recovery_state" update values are seen on other
8600 * CPUs.
72fd0718 8601 */
c9ee9206 8602 smp_mb();
72fd0718
VZ		 8603 break;
8604
8605 case BNX2X_RECOVERY_WAIT:
8606 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8607 if (bp->is_leader) {
c9ee9206 8608 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 8609 bool other_load_status =
8610 bnx2x_get_load_status(bp, other_engine);
8611 bool load_status =
8612 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 8613 global = bnx2x_reset_is_global(bp);
8614
8615 /*
8616 * In case of a parity in a global block, let
8617 * the first leader that performs a
8618 * leader_reset() reset the global blocks in
8619 * order to clear global attentions. Otherwise
8620 * the the gates will remain closed for that
8621 * engine.
8622 */
889b9af3
AE		 8623 if (load_status ||
8624 (global && other_load_status)) {
72fd0718
VZ		 8625 /* Wait until all other functions get
8626 * down.
8627 */
7be08a72 8628 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8629 HZ/10);
8630 return;
8631 } else {
8632 /* If all other functions got down -
8633 * try to bring the chip back to
8634 * normal. In any case it's an exit
8635 * point for a leader.
8636 */
c9ee9206
VZ		 8637 if (bnx2x_leader_reset(bp)) {
8638 bnx2x_recovery_failed(bp);
72fd0718
VZ		 8639 return;
8640 }
8641
c9ee9206
VZ		 8642 /* If we are here, means that the
8643 * leader has succeeded and doesn't
8644 * want to be a leader any more. Try
8645 * to continue as a none-leader.
8646 */
8647 break;
72fd0718
VZ		 8648 }
8649 } else { /* non-leader */
c9ee9206 8650 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 8651 /* Try to get a LEADER_LOCK HW lock as
8652 * long as a former leader may have
8653 * been unloaded by the user or
8654 * released a leadership by another
8655 * reason.
8656 */
c9ee9206 8657 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 8658 /* I'm a leader now! Restart a
8659 * switch case.
8660 */
8661 bp->is_leader = 1;
8662 break;
8663 }
8664
7be08a72 8665 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8666 HZ/10);
8667 return;
8668
c9ee9206
VZ		 8669 } else {
8670 /*
8671 * If there was a global attention, wait
8672 * for it to be cleared.
8673 */
8674 if (bnx2x_reset_is_global(bp)) {
8675 schedule_delayed_work(
7be08a72
AE		 8676 &bp->sp_rtnl_task,
8677 HZ/10);
c9ee9206
VZ		 8678 return;
8679 }
8680
95c6c616
AE		 8681 bp->recovery_state =
8682 BNX2X_RECOVERY_NIC_LOADING;
8683 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
8684 netdev_err(bp->dev,
8685 "Recovery failed. "
8686 "Power cycle "
8687 "needed\n");
8688 /* Disconnect this device */
8689 netif_device_detach(bp->dev);
8690 /* Shut down the power */
8691 bnx2x_set_power_state(
8692 bp, PCI_D3hot);
8693 smp_mb();
8694 } else {
c9ee9206
VZ		 8695 bp->recovery_state =
8696 BNX2X_RECOVERY_DONE;
8697 smp_mb();
8698 }
8699
72fd0718
VZ		 8700 return;
8701 }
8702 }
8703 default:
8704 return;
8705 }
8706 }
8707}
8708
8709/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8710 * scheduled on a general queue in order to prevent a dead lock.
8711 */
7be08a72 8712static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 8713{
7be08a72 8714 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 8715
8716 rtnl_lock();
8717
8718 if (!netif_running(bp->dev))
7be08a72
AE		 8719 goto sp_rtnl_exit;
8720
8721 /* if stop on error is defined no recovery flows should be executed */
8722#ifdef BNX2X_STOP_ON_ERROR
8723 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8724 "so reset not done to allow debug dump,\n"
8725 "you will need to reboot when done\n");
b1fb8740 8726 goto sp_rtnl_not_reset;
7be08a72 8727#endif
34f80b04 8728
7be08a72
AE		 8729 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8730 /*
b1fb8740
VZ		 8731 * Clear all pending SP commands as we are going to reset the
8732 * function anyway.
7be08a72 8733 */
b1fb8740
VZ		 8734 bp->sp_rtnl_state = 0;
8735 smp_mb();
8736
72fd0718 8737 bnx2x_parity_recover(bp);
b1fb8740
VZ		 8738
8739 goto sp_rtnl_exit;
8740 }
8741
8742 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8743 /*
8744 * Clear all pending SP commands as we are going to reset the
8745 * function anyway.
8746 */
8747 bp->sp_rtnl_state = 0;
8748 smp_mb();
8749
72fd0718
VZ		 8750 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8751 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740
VZ		 8752
8753 goto sp_rtnl_exit;
72fd0718 8754 }
b1fb8740
VZ		 8755#ifdef BNX2X_STOP_ON_ERROR
8756sp_rtnl_not_reset:
8757#endif
8758 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8759 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
34f80b04 8760
8304859a
AE		 8761 /*
8762 * in case of fan failure we need to reset id if the "stop on error"
8763 * debug flag is set, since we trying to prevent permanent overheating
8764 * damage
8765 */
8766 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
5219e4c9 8767 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n");
8304859a
AE		 8768 netif_device_detach(bp->dev);
8769 bnx2x_close(bp->dev);
8770 }
8771
7be08a72 8772sp_rtnl_exit:
34f80b04
EG		 8773 rtnl_unlock();
8774}
8775
a2fbb9ea
ET		 8776/* end of nic load/unload */
8777
3deb8167
YR		 8778static void bnx2x_period_task(struct work_struct *work)
8779{
8780 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8781
8782 if (!netif_running(bp->dev))
8783 goto period_task_exit;
8784
8785 if (CHIP_REV_IS_SLOW(bp)) {
8786 BNX2X_ERR("period task called on emulation, ignoring\n");
8787 goto period_task_exit;
8788 }
8789
8790 bnx2x_acquire_phy_lock(bp);
8791 /*
8792 * The barrier is needed to ensure the ordering between the writing to
8793 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8794 * the reading here.
8795 */
8796 smp_mb();
8797 if (bp->port.pmf) {
8798 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8799
8800 /* Re-queue task in 1 sec */
8801 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8802 }
8803
8804 bnx2x_release_phy_lock(bp);
8805period_task_exit:
8806 return;
8807}
8808
a2fbb9ea
ET		 8809/*
8810 * Init service functions
8811 */
8812
8d96286a 8813static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 8814{
8815 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8816 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8817 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 8818}
8819
f2e0899f 8820static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 8821{
f2e0899f 8822 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 8823
8824 /* Flush all outstanding writes */
8825 mmiowb();
8826
8827 /* Pretend to be function 0 */
8828 REG_WR(bp, reg, 0);
f2e0899f 8829 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 8830
8831 /* From now we are in the "like-E1" mode */
8832 bnx2x_int_disable(bp);
8833
8834 /* Flush all outstanding writes */
8835 mmiowb();
8836
f2e0899f
DK		 8837 /* Restore the original function */
8838 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8839 REG_RD(bp, reg);
f1ef27ef
EG		 8840}
8841
f2e0899f 8842static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 8843{
f2e0899f 8844 if (CHIP_IS_E1(bp))
f1ef27ef 8845 bnx2x_int_disable(bp);
f2e0899f
DK		 8846 else
8847 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 8848}
8849
34f80b04
EG		 8850static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8851{
8852 u32 val;
8853
f16da43b
AE		 8854 /* possibly another driver is trying to reset the chip */
8855 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8856
8857 /* check if doorbell queue is reset */
8858 if (REG_RD(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET)
8859 & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
7a06a122 8860
7a06a122
DK		 8861 /*
8862 * Check if it is the UNDI driver
34f80b04
EG		 8863 * UNDI driver initializes CID offset for normal bell to 0x7
8864 */
8865 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8866 if (val == 0x7) {
8867 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 8868 /* save our pf_num */
8869 int orig_pf_num = bp->pf_num;
619c5cb6
VZ		 8870 int port;
8871 u32 swap_en, swap_val, value;
34f80b04 8872
b4661739
EG		 8873 /* clear the UNDI indication */
8874 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8875
34f80b04
EG		 8876 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8877
8878 /* try unload UNDI on port 0 */
f2e0899f 8879 bp->pf_num = 0;
da5a662a 8880 bp->fw_seq =
f2e0899f 8881 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8882 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 8883 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8884
8885 /* if UNDI is loaded on the other port */
8886 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8887
da5a662a 8888 /* send "DONE" for previous unload */
a22f0788
YR		 8889 bnx2x_fw_command(bp,
8890 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8891
8892 /* unload UNDI on port 1 */
f2e0899f 8893 bp->pf_num = 1;
da5a662a 8894 bp->fw_seq =
f2e0899f 8895 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 8896 DRV_MSG_SEQ_NUMBER_MASK);
8897 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8898
a22f0788 8899 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8900 }
8901
f2e0899f 8902 bnx2x_undi_int_disable(bp);
619c5cb6 8903 port = BP_PORT(bp);
da5a662a
VZ		 8904
8905 /* close input traffic and wait for it */
8906 /* Do not rcv packets to BRB */
619c5cb6
VZ		 8907 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8908 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
da5a662a
VZ		 8909 /* Do not direct rcv packets that are not for MCP to
8910 * the BRB */
619c5cb6
VZ		 8911 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8912 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
da5a662a 8913 /* clear AEU */
619c5cb6
VZ		 8914 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8915 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
da5a662a
VZ		 8916 msleep(10);
8917
8918 /* save NIG port swap info */
8919 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8920 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 8921 /* reset device */
8922 REG_WR(bp,
8923 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 8924 0xd3ffffff);
619c5cb6
VZ		 8925
8926 value = 0x1400;
8927 if (CHIP_IS_E3(bp)) {
8928 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8929 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8930 }
8931
34f80b04
EG		 8932 REG_WR(bp,
8933 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
619c5cb6
VZ		 8934 value);
8935
da5a662a
VZ		 8936 /* take the NIG out of reset and restore swap values */
8937 REG_WR(bp,
8938 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8939 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8940 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8941 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8942
8943 /* send unload done to the MCP */
a22f0788 8944 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8945
8946 /* restore our func and fw_seq */
f2e0899f 8947 bp->pf_num = orig_pf_num;
7a06a122 8948 }
34f80b04 8949 }
f16da43b
AE		 8950
8951 /* now it's safe to release the lock */
8952 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
34f80b04
EG		 8953}
8954
8955static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8956{
1d187b34 8957 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 8958 u16 pmc;
34f80b04
EG		 8959
8960 /* Get the chip revision id and number. */
8961 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8962 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8963 id = ((val & 0xffff) << 16);
8964 val = REG_RD(bp, MISC_REG_CHIP_REV);
8965 id |= ((val & 0xf) << 12);
8966 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8967 id |= ((val & 0xff) << 4);
5a40e08e 8968 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 8969 id |= (val & 0xf);
8970 bp->common.chip_id = id;
523224a3
DK		 8971
8972 /* Set doorbell size */
8973 bp->db_size = (1 << BNX2X_DB_SHIFT);
8974
619c5cb6 8975 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8976 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8977 if ((val & 1) == 0)
8978 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8979 else
8980 val = (val >> 1) & 1;
8981 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8982 "2_PORT_MODE");
8983 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8984 CHIP_2_PORT_MODE;
8985
8986 if (CHIP_MODE_IS_4_PORT(bp))
8987 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8988 else
8989 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8990 } else {
8991 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8992 bp->pfid = bp->pf_num; /* 0..7 */
8993 }
8994
f2e0899f
DK		 8995 bp->link_params.chip_id = bp->common.chip_id;
8996 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 8997
1c06328c
EG		 8998 val = (REG_RD(bp, 0x2874) & 0x55);
8999 if ((bp->common.chip_id & 0x1) ||
9000 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9001 bp->flags |= ONE_PORT_FLAG;
9002 BNX2X_DEV_INFO("single port device\n");
9003 }
9004
34f80b04 9005 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 9006 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 9007 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9008 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9009 bp->common.flash_size, bp->common.flash_size);
9010
1b6e2ceb
DK		 9011 bnx2x_init_shmem(bp);
9012
619c5cb6
VZ		 9013
9014
f2e0899f
DK		 9015 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9016 MISC_REG_GENERIC_CR_1 :
9017 MISC_REG_GENERIC_CR_0));
1b6e2ceb 9018
34f80b04 9019 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 9020 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 9021 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9022 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 9023
f2e0899f 9024 if (!bp->common.shmem_base) {
34f80b04
EG		 9025 BNX2X_DEV_INFO("MCP not active\n");
9026 bp->flags |= NO_MCP_FLAG;
9027 return;
9028 }
9029
34f80b04 9030 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 9031 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 9032
9033 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9034 SHARED_HW_CFG_LED_MODE_MASK) >>
9035 SHARED_HW_CFG_LED_MODE_SHIFT);
9036
c2c8b03e
EG		 9037 bp->link_params.feature_config_flags = 0;
9038 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9039 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9040 bp->link_params.feature_config_flags |=
9041 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9042 else
9043 bp->link_params.feature_config_flags &=
9044 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9045
34f80b04
EG		 9046 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9047 bp->common.bc_ver = val;
9048 BNX2X_DEV_INFO("bc_ver %X\n", val);
9049 if (val < BNX2X_BC_VER) {
9050 /* for now only warn
9051 * later we might need to enforce this */
f2e0899f
DK		 9052 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
9053 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 9054 }
4d295db0 9055 bp->link_params.feature_config_flags |=
a22f0788 9056 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 9057 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9058
a22f0788
YR		 9059 bp->link_params.feature_config_flags |=
9060 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9061 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 9062
85242eea
YR		 9063 bp->link_params.feature_config_flags |=
9064 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9065 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
0e898dd7
BW		 9066 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9067 BC_SUPPORTS_PFC_STATS : 0;
85242eea 9068
1d187b34
BW		 9069 boot_mode = SHMEM_RD(bp,
9070 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9071 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9072 switch (boot_mode) {
9073 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9074 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9075 break;
9076 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9077 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9078 break;
9079 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9080 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9081 break;
9082 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9083 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9084 break;
9085 }
9086
f9a3ebbe
DK		 9087 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9088 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9089
72ce58c3 9090 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 9091 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 9092
9093 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9094 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9095 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9096 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9097
cdaa7cb8
VZ		 9098 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9099 val, val2, val3, val4);
34f80b04
EG		 9100}
9101
f2e0899f
DK		 9102#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9103#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9104
9105static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9106{
9107 int pfid = BP_FUNC(bp);
f2e0899f
DK		 9108 int igu_sb_id;
9109 u32 val;
6383c0b3 9110 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 9111
9112 bp->igu_base_sb = 0xff;
f2e0899f 9113 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 9114 int vn = BP_VN(bp);
6383c0b3 9115 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 9116 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9117 FP_SB_MAX_E1x;
9118
9119 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9120 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9121
9122 return;
9123 }
9124
9125 /* IGU in normal mode - read CAM */
9126 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9127 igu_sb_id++) {
9128 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9129 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9130 continue;
9131 fid = IGU_FID(val);
9132 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9133 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9134 continue;
9135 if (IGU_VEC(val) == 0)
9136 /* default status block */
9137 bp->igu_dsb_id = igu_sb_id;
9138 else {
9139 if (bp->igu_base_sb == 0xff)
9140 bp->igu_base_sb = igu_sb_id;
6383c0b3 9141 igu_sb_cnt++;
f2e0899f
DK		 9142 }
9143 }
9144 }
619c5cb6 9145
6383c0b3
AE		 9146#ifdef CONFIG_PCI_MSI
9147 /*
9148 * It's expected that number of CAM entries for this functions is equal
9149 * to the number evaluated based on the MSI-X table size. We want a
9150 * harsh warning if these values are different!
619c5cb6 9151 */
6383c0b3
AE		 9152 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
9153#endif
619c5cb6 9154
6383c0b3 9155 if (igu_sb_cnt == 0)
f2e0899f
DK		 9156 BNX2X_ERR("CAM configuration error\n");
9157}
9158
34f80b04
EG		 9159static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9160 u32 switch_cfg)
a2fbb9ea 9161{
a22f0788
YR		 9162 int cfg_size = 0, idx, port = BP_PORT(bp);
9163
9164 /* Aggregation of supported attributes of all external phys */
9165 bp->port.supported[0] = 0;
9166 bp->port.supported[1] = 0;
b7737c9b
YR		 9167 switch (bp->link_params.num_phys) {
9168 case 1:
a22f0788
YR		 9169 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9170 cfg_size = 1;
9171 break;
b7737c9b 9172 case 2:
a22f0788
YR		 9173 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9174 cfg_size = 1;
9175 break;
9176 case 3:
9177 if (bp->link_params.multi_phy_config &
9178 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9179 bp->port.supported[1] =
9180 bp->link_params.phy[EXT_PHY1].supported;
9181 bp->port.supported[0] =
9182 bp->link_params.phy[EXT_PHY2].supported;
9183 } else {
9184 bp->port.supported[0] =
9185 bp->link_params.phy[EXT_PHY1].supported;
9186 bp->port.supported[1] =
9187 bp->link_params.phy[EXT_PHY2].supported;
9188 }
9189 cfg_size = 2;
9190 break;
b7737c9b 9191 }
a2fbb9ea 9192
a22f0788 9193 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 9194 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 9195 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 9196 SHMEM_RD(bp,
a22f0788
YR		 9197 dev_info.port_hw_config[port].external_phy_config),
9198 SHMEM_RD(bp,
9199 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 9200 return;
f85582f8 9201 }
a2fbb9ea 9202
619c5cb6
VZ		 9203 if (CHIP_IS_E3(bp))
9204 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9205 else {
9206 switch (switch_cfg) {
9207 case SWITCH_CFG_1G:
9208 bp->port.phy_addr = REG_RD(
9209 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9210 break;
9211 case SWITCH_CFG_10G:
9212 bp->port.phy_addr = REG_RD(
9213 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9214 break;
9215 default:
9216 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9217 bp->port.link_config[0]);
9218 return;
9219 }
a2fbb9ea 9220 }
619c5cb6 9221 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 9222 /* mask what we support according to speed_cap_mask per configuration */
9223 for (idx = 0; idx < cfg_size; idx++) {
9224 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9225 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 9226 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 9227
a22f0788 9228 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9229 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 9230 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 9231
a22f0788 9232 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9233 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 9234 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 9235
a22f0788 9236 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9237 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 9238 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 9239
a22f0788 9240 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9241 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 9242 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 9243 SUPPORTED_1000baseT_Full);
a2fbb9ea 9244
a22f0788 9245 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9246 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 9247 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 9248
a22f0788 9249 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 9250 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 9251 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9252
9253 }
a2fbb9ea 9254
a22f0788
YR		 9255 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9256 bp->port.supported[1]);
a2fbb9ea
ET		 9257}
9258
34f80b04 9259static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 9260{
a22f0788
YR		 9261 u32 link_config, idx, cfg_size = 0;
9262 bp->port.advertising[0] = 0;
9263 bp->port.advertising[1] = 0;
9264 switch (bp->link_params.num_phys) {
9265 case 1:
9266 case 2:
9267 cfg_size = 1;
9268 break;
9269 case 3:
9270 cfg_size = 2;
9271 break;
9272 }
9273 for (idx = 0; idx < cfg_size; idx++) {
9274 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9275 link_config = bp->port.link_config[idx];
9276 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 9277 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 9278 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9279 bp->link_params.req_line_speed[idx] =
9280 SPEED_AUTO_NEG;
9281 bp->port.advertising[idx] |=
9282 bp->port.supported[idx];
f85582f8
DK		 9283 } else {
9284 /* force 10G, no AN */
a22f0788
YR		 9285 bp->link_params.req_line_speed[idx] =
9286 SPEED_10000;
9287 bp->port.advertising[idx] |=
9288 (ADVERTISED_10000baseT_Full |
f85582f8 9289 ADVERTISED_FIBRE);
a22f0788 9290 continue;
f85582f8
DK		 9291 }
9292 break;
a2fbb9ea 9293
f85582f8 9294 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 9295 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9296 bp->link_params.req_line_speed[idx] =
9297 SPEED_10;
9298 bp->port.advertising[idx] |=
9299 (ADVERTISED_10baseT_Full |
f85582f8
DK		 9300 ADVERTISED_TP);
9301 } else {
754a2f52 9302 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9303 "Invalid link_config 0x%x"
9304 " speed_cap_mask 0x%x\n",
9305 link_config,
a22f0788 9306 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9307 return;
9308 }
9309 break;
a2fbb9ea 9310
f85582f8 9311 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 9312 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9313 bp->link_params.req_line_speed[idx] =
9314 SPEED_10;
9315 bp->link_params.req_duplex[idx] =
9316 DUPLEX_HALF;
9317 bp->port.advertising[idx] |=
9318 (ADVERTISED_10baseT_Half |
f85582f8
DK		 9319 ADVERTISED_TP);
9320 } else {
754a2f52 9321 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9322 "Invalid link_config 0x%x"
9323 " speed_cap_mask 0x%x\n",
9324 link_config,
9325 bp->link_params.speed_cap_mask[idx]);
9326 return;
9327 }
9328 break;
a2fbb9ea 9329
f85582f8
DK		 9330 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9331 if (bp->port.supported[idx] &
9332 SUPPORTED_100baseT_Full) {
a22f0788
YR		 9333 bp->link_params.req_line_speed[idx] =
9334 SPEED_100;
9335 bp->port.advertising[idx] |=
9336 (ADVERTISED_100baseT_Full |
f85582f8
DK		 9337 ADVERTISED_TP);
9338 } else {
754a2f52 9339 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9340 "Invalid link_config 0x%x"
9341 " speed_cap_mask 0x%x\n",
9342 link_config,
9343 bp->link_params.speed_cap_mask[idx]);
9344 return;
9345 }
9346 break;
a2fbb9ea 9347
f85582f8
DK		 9348 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9349 if (bp->port.supported[idx] &
9350 SUPPORTED_100baseT_Half) {
9351 bp->link_params.req_line_speed[idx] =
9352 SPEED_100;
9353 bp->link_params.req_duplex[idx] =
9354 DUPLEX_HALF;
a22f0788
YR		 9355 bp->port.advertising[idx] |=
9356 (ADVERTISED_100baseT_Half |
f85582f8
DK		 9357 ADVERTISED_TP);
9358 } else {
754a2f52 9359 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9360 "Invalid link_config 0x%x"
9361 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9362 link_config,
9363 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9364 return;
9365 }
9366 break;
a2fbb9ea 9367
f85582f8 9368 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 9369 if (bp->port.supported[idx] &
9370 SUPPORTED_1000baseT_Full) {
9371 bp->link_params.req_line_speed[idx] =
9372 SPEED_1000;
9373 bp->port.advertising[idx] |=
9374 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 9375 ADVERTISED_TP);
9376 } else {
754a2f52 9377 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9378 "Invalid link_config 0x%x"
9379 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9380 link_config,
9381 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9382 return;
9383 }
9384 break;
a2fbb9ea 9385
f85582f8 9386 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 9387 if (bp->port.supported[idx] &
9388 SUPPORTED_2500baseX_Full) {
9389 bp->link_params.req_line_speed[idx] =
9390 SPEED_2500;
9391 bp->port.advertising[idx] |=
9392 (ADVERTISED_2500baseX_Full |
34f80b04 9393 ADVERTISED_TP);
f85582f8 9394 } else {
754a2f52 9395 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9396 "Invalid link_config 0x%x"
9397 " speed_cap_mask 0x%x\n",
a22f0788 9398 link_config,
f85582f8
DK		 9399 bp->link_params.speed_cap_mask[idx]);
9400 return;
9401 }
9402 break;
a2fbb9ea 9403
f85582f8 9404 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 9405 if (bp->port.supported[idx] &
9406 SUPPORTED_10000baseT_Full) {
9407 bp->link_params.req_line_speed[idx] =
9408 SPEED_10000;
9409 bp->port.advertising[idx] |=
9410 (ADVERTISED_10000baseT_Full |
34f80b04 9411 ADVERTISED_FIBRE);
f85582f8 9412 } else {
754a2f52 9413 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9414 "Invalid link_config 0x%x"
9415 " speed_cap_mask 0x%x\n",
a22f0788 9416 link_config,
f85582f8
DK		 9417 bp->link_params.speed_cap_mask[idx]);
9418 return;
9419 }
9420 break;
3c9ada22
YR		 9421 case PORT_FEATURE_LINK_SPEED_20G:
9422 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 9423
3c9ada22 9424 break;
f85582f8 9425 default:
754a2f52
DK		 9426 BNX2X_ERR("NVRAM config error. "
9427 "BAD link speed link_config 0x%x\n",
9428 link_config);
f85582f8
DK		 9429 bp->link_params.req_line_speed[idx] =
9430 SPEED_AUTO_NEG;
9431 bp->port.advertising[idx] =
9432 bp->port.supported[idx];
9433 break;
9434 }
a2fbb9ea 9435
a22f0788 9436 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 9437 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 9438 if ((bp->link_params.req_flow_ctrl[idx] ==
9439 BNX2X_FLOW_CTRL_AUTO) &&
9440 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9441 bp->link_params.req_flow_ctrl[idx] =
9442 BNX2X_FLOW_CTRL_NONE;
9443 }
a2fbb9ea 9444
a22f0788
YR		 9445 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9446 " 0x%x advertising 0x%x\n",
9447 bp->link_params.req_line_speed[idx],
9448 bp->link_params.req_duplex[idx],
9449 bp->link_params.req_flow_ctrl[idx],
9450 bp->port.advertising[idx]);
9451 }
a2fbb9ea
ET		 9452}
9453
e665bfda
MC		 9454static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9455{
9456 mac_hi = cpu_to_be16(mac_hi);
9457 mac_lo = cpu_to_be32(mac_lo);
9458 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9459 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9460}
9461
34f80b04 9462static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 9463{
34f80b04 9464 int port = BP_PORT(bp);
589abe3a 9465 u32 config;
6f38ad93 9466 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 9467
c18487ee 9468 bp->link_params.bp = bp;
34f80b04 9469 bp->link_params.port = port;
c18487ee 9470
c18487ee 9471 bp->link_params.lane_config =
a2fbb9ea 9472 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 9473
a22f0788 9474 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 9475 SHMEM_RD(bp,
9476 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 9477 bp->link_params.speed_cap_mask[1] =
9478 SHMEM_RD(bp,
9479 dev_info.port_hw_config[port].speed_capability_mask2);
9480 bp->port.link_config[0] =
a2fbb9ea
ET		 9481 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9482
a22f0788
YR		 9483 bp->port.link_config[1] =
9484 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 9485
a22f0788
YR		 9486 bp->link_params.multi_phy_config =
9487 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 9488 /* If the device is capable of WoL, set the default state according
9489 * to the HW
9490 */
4d295db0 9491 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 9492 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9493 (config & PORT_FEATURE_WOL_ENABLED));
9494
f85582f8 9495 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 9496 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 9497 bp->link_params.lane_config,
a22f0788
YR		 9498 bp->link_params.speed_cap_mask[0],
9499 bp->port.link_config[0]);
a2fbb9ea 9500
a22f0788 9501 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 9502 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 9503 bnx2x_phy_probe(&bp->link_params);
c18487ee 9504 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 9505
9506 bnx2x_link_settings_requested(bp);
9507
01cd4528
EG		 9508 /*
9509 * If connected directly, work with the internal PHY, otherwise, work
9510 * with the external PHY
9511 */
b7737c9b
YR		 9512 ext_phy_config =
9513 SHMEM_RD(bp,
9514 dev_info.port_hw_config[port].external_phy_config);
9515 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 9516 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 9517 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 9518
9519 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9520 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9521 bp->mdio.prtad =
b7737c9b 9522 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 9523
9524 /*
9525 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9526 * In MF mode, it is set to cover self test cases
9527 */
9528 if (IS_MF(bp))
9529 bp->port.need_hw_lock = 1;
9530 else
9531 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9532 bp->common.shmem_base,
9533 bp->common.shmem2_base);
0793f83f 9534}
01cd4528 9535
b306f5ed 9536void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 9537{
7185bb33 9538#ifdef BCM_CNIC
bf61ee14 9539 int port = BP_PORT(bp);
bf61ee14 9540
2ba45142 9541 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9542 drv_lic_key[port].max_iscsi_conn);
2ba45142 9543
b306f5ed 9544 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 9545 bp->cnic_eth_dev.max_iscsi_conn =
9546 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9547 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9548
b306f5ed
DK		 9549 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9550 bp->cnic_eth_dev.max_iscsi_conn);
9551
9552 /*
9553 * If maximum allowed number of connections is zero -
9554 * disable the feature.
9555 */
9556 if (!bp->cnic_eth_dev.max_iscsi_conn)
9557 bp->flags |= NO_ISCSI_FLAG;
7185bb33
DK		 9558#else
9559 bp->flags |= NO_ISCSI_FLAG;
9560#endif
b306f5ed
DK		 9561}
9562
9563static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
9564{
7185bb33 9565#ifdef BCM_CNIC
b306f5ed
DK		 9566 int port = BP_PORT(bp);
9567 int func = BP_ABS_FUNC(bp);
9568
9569 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9570 drv_lic_key[port].max_fcoe_conn);
9571
9572 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 9573 bp->cnic_eth_dev.max_fcoe_conn =
9574 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9575 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9576
bf61ee14
VZ		 9577 /* Read the WWN: */
9578 if (!IS_MF(bp)) {
9579 /* Port info */
9580 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9581 SHMEM_RD(bp,
9582 dev_info.port_hw_config[port].
9583 fcoe_wwn_port_name_upper);
9584 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9585 SHMEM_RD(bp,
9586 dev_info.port_hw_config[port].
9587 fcoe_wwn_port_name_lower);
9588
9589 /* Node info */
9590 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9591 SHMEM_RD(bp,
9592 dev_info.port_hw_config[port].
9593 fcoe_wwn_node_name_upper);
9594 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9595 SHMEM_RD(bp,
9596 dev_info.port_hw_config[port].
9597 fcoe_wwn_node_name_lower);
9598 } else if (!IS_MF_SD(bp)) {
9599 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9600
9601 /*
9602 * Read the WWN info only if the FCoE feature is enabled for
9603 * this function.
9604 */
9605 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9606 /* Port info */
9607 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9608 MF_CFG_RD(bp, func_ext_config[func].
9609 fcoe_wwn_port_name_upper);
9610 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9611 MF_CFG_RD(bp, func_ext_config[func].
9612 fcoe_wwn_port_name_lower);
9613
9614 /* Node info */
9615 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9616 MF_CFG_RD(bp, func_ext_config[func].
9617 fcoe_wwn_node_name_upper);
9618 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9619 MF_CFG_RD(bp, func_ext_config[func].
9620 fcoe_wwn_node_name_lower);
9621 }
9622 }
9623
b306f5ed 9624 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 9625
bf61ee14
VZ		 9626 /*
9627 * If maximum allowed number of connections is zero -
2ba45142
VZ		 9628 * disable the feature.
9629 */
2ba45142
VZ		 9630 if (!bp->cnic_eth_dev.max_fcoe_conn)
9631 bp->flags |= NO_FCOE_FLAG;
7185bb33
DK		 9632#else
9633 bp->flags |= NO_FCOE_FLAG;
9634#endif
2ba45142 9635}
b306f5ed
DK		 9636
9637static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9638{
9639 /*
9640 * iSCSI may be dynamically disabled but reading
9641 * info here we will decrease memory usage by driver
9642 * if the feature is disabled for good
9643 */
9644 bnx2x_get_iscsi_info(bp);
9645 bnx2x_get_fcoe_info(bp);
9646}
2ba45142 9647
0793f83f
DK		 9648static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9649{
9650 u32 val, val2;
9651 int func = BP_ABS_FUNC(bp);
9652 int port = BP_PORT(bp);
2ba45142
VZ		 9653#ifdef BCM_CNIC
9654 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9655 u8 *fip_mac = bp->fip_mac;
9656#endif
0793f83f 9657
619c5cb6
VZ		 9658 /* Zero primary MAC configuration */
9659 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9660
0793f83f
DK		 9661 if (BP_NOMCP(bp)) {
9662 BNX2X_ERROR("warning: random MAC workaround active\n");
9663 random_ether_addr(bp->dev->dev_addr);
9664 } else if (IS_MF(bp)) {
9665 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9666 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9667 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9668 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9669 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 9670
9671#ifdef BCM_CNIC
614c76df
DK		 9672 /*
9673 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142
VZ		 9674 * FCoE MAC then the appropriate feature should be disabled.
9675 */
0793f83f
DK		 9676 if (IS_MF_SI(bp)) {
9677 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9678 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9679 val2 = MF_CFG_RD(bp, func_ext_config[func].
9680 iscsi_mac_addr_upper);
9681 val = MF_CFG_RD(bp, func_ext_config[func].
9682 iscsi_mac_addr_lower);
2ba45142 9683 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0f9dad10
JP		 9684 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9685 iscsi_mac);
2ba45142
VZ		 9686 } else
9687 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9688
9689 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9690 val2 = MF_CFG_RD(bp, func_ext_config[func].
9691 fcoe_mac_addr_upper);
9692 val = MF_CFG_RD(bp, func_ext_config[func].
9693 fcoe_mac_addr_lower);
2ba45142 9694 bnx2x_set_mac_buf(fip_mac, val, val2);
614c76df 9695 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
0f9dad10 9696 fip_mac);
2ba45142 9697
2ba45142
VZ		 9698 } else
9699 bp->flags |= NO_FCOE_FLAG;
614c76df
DK		 9700 } else { /* SD mode */
9701 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) {
9702 /* use primary mac as iscsi mac */
9703 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
9704 /* Zero primary MAC configuration */
9705 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9706
9707 BNX2X_DEV_INFO("SD ISCSI MODE\n");
9708 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9709 iscsi_mac);
9710 }
0793f83f 9711 }
37b091ba 9712#endif
0793f83f
DK		 9713 } else {
9714 /* in SF read MACs from port configuration */
9715 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9716 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9717 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9718
9719#ifdef BCM_CNIC
9720 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9721 iscsi_mac_upper);
9722 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9723 iscsi_mac_lower);
2ba45142 9724 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 9725
9726 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9727 fcoe_fip_mac_upper);
9728 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9729 fcoe_fip_mac_lower);
9730 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 9731#endif
9732 }
9733
9734 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9735 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9736
ec6ba945 9737#ifdef BCM_CNIC
c03bd39c
VZ		 9738 /* Set the FCoE MAC in MF_SD mode */
9739 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9740 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
426b9241
DK		 9741
9742 /* Disable iSCSI if MAC configuration is
9743 * invalid.
9744 */
9745 if (!is_valid_ether_addr(iscsi_mac)) {
9746 bp->flags |= NO_ISCSI_FLAG;
9747 memset(iscsi_mac, 0, ETH_ALEN);
9748 }
9749
9750 /* Disable FCoE if MAC configuration is
9751 * invalid.
9752 */
9753 if (!is_valid_ether_addr(fip_mac)) {
9754 bp->flags |= NO_FCOE_FLAG;
9755 memset(bp->fip_mac, 0, ETH_ALEN);
9756 }
ec6ba945 9757#endif
619c5cb6 9758
614c76df 9759 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6
VZ		 9760 dev_err(&bp->pdev->dev,
9761 "bad Ethernet MAC address configuration: "
0f9dad10 9762 "%pM, change it manually before bringing up "
619c5cb6 9763 "the appropriate network interface\n",
0f9dad10 9764 bp->dev->dev_addr);
34f80b04
EG		 9765}
9766
9767static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9768{
0793f83f 9769 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 9770 int vn;
0793f83f 9771 u32 val = 0;
34f80b04 9772 int rc = 0;
a2fbb9ea 9773
34f80b04 9774 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 9775
6383c0b3
AE		 9776 /*
9777 * initialize IGU parameters
9778 */
f2e0899f
DK		 9779 if (CHIP_IS_E1x(bp)) {
9780 bp->common.int_block = INT_BLOCK_HC;
9781
9782 bp->igu_dsb_id = DEF_SB_IGU_ID;
9783 bp->igu_base_sb = 0;
f2e0899f
DK		 9784 } else {
9785 bp->common.int_block = INT_BLOCK_IGU;
7a06a122
DK		 9786
9787 /* do not allow device reset during IGU info preocessing */
9788 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9789
f2e0899f 9790 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 9791
9792 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9793 int tout = 5000;
9794
9795 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9796
9797 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9798 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9799 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9800
9801 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9802 tout--;
9803 usleep_range(1000, 1000);
9804 }
9805
9806 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9807 dev_err(&bp->pdev->dev,
9808 "FORCING Normal Mode failed!!!\n");
9809 return -EPERM;
9810 }
9811 }
9812
f2e0899f 9813 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 9814 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 9815 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9816 } else
619c5cb6 9817 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 9818
f2e0899f
DK		 9819 bnx2x_get_igu_cam_info(bp);
9820
7a06a122 9821 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
f2e0899f 9822 }
619c5cb6
VZ		 9823
9824 /*
9825 * set base FW non-default (fast path) status block id, this value is
9826 * used to initialize the fw_sb_id saved on the fp/queue structure to
9827 * determine the id used by the FW.
9828 */
9829 if (CHIP_IS_E1x(bp))
9830 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9831 else /*
9832 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9833 * the same queue are indicated on the same IGU SB). So we prefer
9834 * FW and IGU SBs to be the same value.
9835 */
9836 bp->base_fw_ndsb = bp->igu_base_sb;
9837
9838 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9839 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9840 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 9841
9842 /*
9843 * Initialize MF configuration
9844 */
523224a3 9845
fb3bff17
DK		 9846 bp->mf_ov = 0;
9847 bp->mf_mode = 0;
3395a033 9848 vn = BP_VN(bp);
0793f83f 9849
f2e0899f 9850 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 9851 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9852 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9853 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9854
f2e0899f
DK		 9855 if (SHMEM2_HAS(bp, mf_cfg_addr))
9856 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9857 else
9858 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 9859 offsetof(struct shmem_region, func_mb) +
9860 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 9861 /*
9862 * get mf configuration:
25985edc 9863 * 1. existence of MF configuration
0793f83f
DK		 9864 * 2. MAC address must be legal (check only upper bytes)
9865 * for Switch-Independent mode;
9866 * OVLAN must be legal for Switch-Dependent mode
9867 * 3. SF_MODE configures specific MF mode
9868 */
9869 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9870 /* get mf configuration */
9871 val = SHMEM_RD(bp,
9872 dev_info.shared_feature_config.config);
9873 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9874
9875 switch (val) {
9876 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9877 val = MF_CFG_RD(bp, func_mf_config[func].
9878 mac_upper);
9879 /* check for legal mac (upper bytes)*/
9880 if (val != 0xffff) {
9881 bp->mf_mode = MULTI_FUNCTION_SI;
9882 bp->mf_config[vn] = MF_CFG_RD(bp,
9883 func_mf_config[func].config);
9884 } else
619c5cb6
VZ		 9885 BNX2X_DEV_INFO("illegal MAC address "
9886 "for SI\n");
0793f83f
DK		 9887 break;
9888 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9889 /* get OV configuration */
9890 val = MF_CFG_RD(bp,
9891 func_mf_config[FUNC_0].e1hov_tag);
9892 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9893
9894 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9895 bp->mf_mode = MULTI_FUNCTION_SD;
9896 bp->mf_config[vn] = MF_CFG_RD(bp,
9897 func_mf_config[func].config);
9898 } else
754a2f52 9899 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 9900 break;
9901 default:
9902 /* Unknown configuration: reset mf_config */
9903 bp->mf_config[vn] = 0;
754a2f52 9904 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
0793f83f
DK		 9905 }
9906 }
a2fbb9ea 9907
2691d51d 9908 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 9909 IS_MF(bp) ? "multi" : "single");
2691d51d 9910
0793f83f
DK		 9911 switch (bp->mf_mode) {
9912 case MULTI_FUNCTION_SD:
9913 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9914 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 9915 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 9916 bp->mf_ov = val;
619c5cb6
VZ		 9917 bp->path_has_ovlan = true;
9918
9919 BNX2X_DEV_INFO("MF OV for func %d is %d "
9920 "(0x%04x)\n", func, bp->mf_ov,
9921 bp->mf_ov);
2691d51d 9922 } else {
619c5cb6
VZ		 9923 dev_err(&bp->pdev->dev,
9924 "No valid MF OV for func %d, "
9925 "aborting\n", func);
9926 return -EPERM;
34f80b04 9927 }
0793f83f
DK		 9928 break;
9929 case MULTI_FUNCTION_SI:
9930 BNX2X_DEV_INFO("func %d is in MF "
9931 "switch-independent mode\n", func);
9932 break;
9933 default:
9934 if (vn) {
619c5cb6
VZ		 9935 dev_err(&bp->pdev->dev,
9936 "VN %d is in a single function mode, "
9937 "aborting\n", vn);
9938 return -EPERM;
2691d51d 9939 }
0793f83f 9940 break;
34f80b04 9941 }
0793f83f 9942
619c5cb6
VZ		 9943 /* check if other port on the path needs ovlan:
9944 * Since MF configuration is shared between ports
9945 * Possible mixed modes are only
9946 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9947 */
9948 if (CHIP_MODE_IS_4_PORT(bp) &&
9949 !bp->path_has_ovlan &&
9950 !IS_MF(bp) &&
9951 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9952 u8 other_port = !BP_PORT(bp);
9953 u8 other_func = BP_PATH(bp) + 2*other_port;
9954 val = MF_CFG_RD(bp,
9955 func_mf_config[other_func].e1hov_tag);
9956 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9957 bp->path_has_ovlan = true;
9958 }
34f80b04 9959 }
a2fbb9ea 9960
f2e0899f
DK		 9961 /* adjust igu_sb_cnt to MF for E1x */
9962 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 9963 bp->igu_sb_cnt /= E1HVN_MAX;
9964
619c5cb6
VZ		 9965 /* port info */
9966 bnx2x_get_port_hwinfo(bp);
f2e0899f 9967
0793f83f
DK		 9968 /* Get MAC addresses */
9969 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 9970
2ba45142 9971 bnx2x_get_cnic_info(bp);
2ba45142 9972
34f80b04
EG		 9973 return rc;
9974}
9975
34f24c7f
VZ		 9976static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9977{
9978 int cnt, i, block_end, rodi;
fcdf95cb 9979 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 9980 char str_id_reg[VENDOR_ID_LEN+1];
9981 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 9982 char *vpd_data;
9983 char *vpd_extended_data = NULL;
34f24c7f
VZ		 9984 u8 len;
9985
fcdf95cb 9986 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 9987 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9988
9989 if (cnt < BNX2X_VPD_LEN)
9990 goto out_not_found;
9991
fcdf95cb
BW		 9992 /* VPD RO tag should be first tag after identifier string, hence
9993 * we should be able to find it in first BNX2X_VPD_LEN chars
9994 */
9995 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 9996 PCI_VPD_LRDT_RO_DATA);
9997 if (i < 0)
9998 goto out_not_found;
9999
34f24c7f 10000 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 10001 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 10002
10003 i += PCI_VPD_LRDT_TAG_SIZE;
10004
fcdf95cb
BW		 10005 if (block_end > BNX2X_VPD_LEN) {
10006 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10007 if (vpd_extended_data == NULL)
10008 goto out_not_found;
10009
10010 /* read rest of vpd image into vpd_extended_data */
10011 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10012 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10013 block_end - BNX2X_VPD_LEN,
10014 vpd_extended_data + BNX2X_VPD_LEN);
10015 if (cnt < (block_end - BNX2X_VPD_LEN))
10016 goto out_not_found;
10017 vpd_data = vpd_extended_data;
10018 } else
10019 vpd_data = vpd_start;
10020
10021 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 10022
10023 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10024 PCI_VPD_RO_KEYWORD_MFR_ID);
10025 if (rodi < 0)
10026 goto out_not_found;
10027
10028 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10029
10030 if (len != VENDOR_ID_LEN)
10031 goto out_not_found;
10032
10033 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10034
10035 /* vendor specific info */
10036 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10037 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10038 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10039 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10040
10041 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10042 PCI_VPD_RO_KEYWORD_VENDOR0);
10043 if (rodi >= 0) {
10044 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10045
10046 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10047
10048 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10049 memcpy(bp->fw_ver, &vpd_data[rodi], len);
10050 bp->fw_ver[len] = ' ';
10051 }
10052 }
fcdf95cb 10053 kfree(vpd_extended_data);
34f24c7f
VZ		 10054 return;
10055 }
10056out_not_found:
fcdf95cb 10057 kfree(vpd_extended_data);
34f24c7f
VZ		 10058 return;
10059}
10060
619c5cb6
VZ		 10061static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10062{
10063 u32 flags = 0;
10064
10065 if (CHIP_REV_IS_FPGA(bp))
10066 SET_FLAGS(flags, MODE_FPGA);
10067 else if (CHIP_REV_IS_EMUL(bp))
10068 SET_FLAGS(flags, MODE_EMUL);
10069 else
10070 SET_FLAGS(flags, MODE_ASIC);
10071
10072 if (CHIP_MODE_IS_4_PORT(bp))
10073 SET_FLAGS(flags, MODE_PORT4);
10074 else
10075 SET_FLAGS(flags, MODE_PORT2);
10076
10077 if (CHIP_IS_E2(bp))
10078 SET_FLAGS(flags, MODE_E2);
10079 else if (CHIP_IS_E3(bp)) {
10080 SET_FLAGS(flags, MODE_E3);
10081 if (CHIP_REV(bp) == CHIP_REV_Ax)
10082 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 10083 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10084 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 10085 }
10086
10087 if (IS_MF(bp)) {
10088 SET_FLAGS(flags, MODE_MF);
10089 switch (bp->mf_mode) {
10090 case MULTI_FUNCTION_SD:
10091 SET_FLAGS(flags, MODE_MF_SD);
10092 break;
10093 case MULTI_FUNCTION_SI:
10094 SET_FLAGS(flags, MODE_MF_SI);
10095 break;
10096 }
10097 } else
10098 SET_FLAGS(flags, MODE_SF);
10099
10100#if defined(__LITTLE_ENDIAN)
10101 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10102#else /*(__BIG_ENDIAN)*/
10103 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10104#endif
10105 INIT_MODE_FLAGS(bp) = flags;
10106}
10107
34f80b04
EG		 10108static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10109{
f2e0899f 10110 int func;
87942b46 10111 int timer_interval;
34f80b04
EG		 10112 int rc;
10113
34f80b04 10114 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 10115 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 10116 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 10117#ifdef BCM_CNIC
10118 mutex_init(&bp->cnic_mutex);
10119#endif
a2fbb9ea 10120
1cf167f2 10121 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 10122 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 10123 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
34f80b04 10124 rc = bnx2x_get_hwinfo(bp);
619c5cb6
VZ		 10125 if (rc)
10126 return rc;
34f80b04 10127
619c5cb6
VZ		 10128 bnx2x_set_modes_bitmap(bp);
10129
10130 rc = bnx2x_alloc_mem_bp(bp);
10131 if (rc)
10132 return rc;
523224a3 10133
34f24c7f 10134 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 10135
10136 func = BP_FUNC(bp);
10137
34f80b04
EG		 10138 /* need to reset chip if undi was active */
10139 if (!BP_NOMCP(bp))
10140 bnx2x_undi_unload(bp);
10141
10142 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 10143 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 10144
10145 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 10146 dev_err(&bp->pdev->dev, "MCP disabled, "
10147 "must load devices in order!\n");
34f80b04 10148
555f6c78 10149 bp->multi_mode = multi_mode;
555f6c78 10150
614c76df
DK		 10151 bp->disable_tpa = disable_tpa;
10152
10153#ifdef BCM_CNIC
10154 bp->disable_tpa |= IS_MF_ISCSI_SD(bp);
10155#endif
10156
7a9b2557 10157 /* Set TPA flags */
614c76df 10158 if (bp->disable_tpa) {
7a9b2557
VZ		 10159 bp->flags &= ~TPA_ENABLE_FLAG;
10160 bp->dev->features &= ~NETIF_F_LRO;
10161 } else {
10162 bp->flags |= TPA_ENABLE_FLAG;
10163 bp->dev->features |= NETIF_F_LRO;
10164 }
10165
a18f5128
EG		 10166 if (CHIP_IS_E1(bp))
10167 bp->dropless_fc = 0;
10168 else
10169 bp->dropless_fc = dropless_fc;
10170
8d5726c4 10171 bp->mrrs = mrrs;
7a9b2557 10172
34f80b04 10173 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 10174
7d323bfd 10175 /* make sure that the numbers are in the right granularity */
523224a3
DK		 10176 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10177 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 10178
87942b46
EG		 10179 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
10180 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 10181
10182 init_timer(&bp->timer);
10183 bp->timer.expires = jiffies + bp->current_interval;
10184 bp->timer.data = (unsigned long) bp;
10185 bp->timer.function = bnx2x_timer;
10186
785b9b1a 10187 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 10188 bnx2x_dcbx_init_params(bp);
10189
619c5cb6
VZ		 10190#ifdef BCM_CNIC
10191 if (CHIP_IS_E1x(bp))
10192 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10193 else
10194 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10195#endif
10196
6383c0b3
AE		 10197 /* multiple tx priority */
10198 if (CHIP_IS_E1x(bp))
10199 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10200 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10201 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10202 if (CHIP_IS_E3B0(bp))
10203 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10204
34f80b04 10205 return rc;
a2fbb9ea
ET		 10206}
10207
a2fbb9ea 10208
de0c62db
DK		 10209/****************************************************************************
10210* General service functions
10211****************************************************************************/
a2fbb9ea 10212
619c5cb6
VZ		 10213/*
10214 * net_device service functions
10215 */
10216
bb2a0f7a 10217/* called with rtnl_lock */
a2fbb9ea
ET		 10218static int bnx2x_open(struct net_device *dev)
10219{
10220 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 10221 bool global = false;
10222 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3 10223 bool other_load_status, load_status;
a2fbb9ea 10224
6eccabb3
EG		 10225 netif_carrier_off(dev);
10226
a2fbb9ea
ET		 10227 bnx2x_set_power_state(bp, PCI_D0);
10228
889b9af3
AE		 10229 other_load_status = bnx2x_get_load_status(bp, other_engine);
10230 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 10231
10232 /*
10233 * If parity had happen during the unload, then attentions
10234 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10235 * want the first function loaded on the current engine to
10236 * complete the recovery.
10237 */
10238 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10239 bnx2x_chk_parity_attn(bp, &global, true))
72fd0718 10240 do {
c9ee9206
VZ		 10241 /*
10242 * If there are attentions and they are in a global
10243 * blocks, set the GLOBAL_RESET bit regardless whether
10244 * it will be this function that will complete the
10245 * recovery or not.
72fd0718 10246 */
c9ee9206
VZ		 10247 if (global)
10248 bnx2x_set_reset_global(bp);
72fd0718 10249
c9ee9206
VZ		 10250 /*
10251 * Only the first function on the current engine should
10252 * try to recover in open. In case of attentions in
10253 * global blocks only the first in the chip should try
10254 * to recover.
72fd0718 10255 */
889b9af3
AE		 10256 if ((!load_status &&
10257 (!global || !other_load_status)) &&
c9ee9206
VZ		 10258 bnx2x_trylock_leader_lock(bp) &&
10259 !bnx2x_leader_reset(bp)) {
10260 netdev_info(bp->dev, "Recovered in open\n");
72fd0718
VZ		 10261 break;
10262 }
10263
c9ee9206 10264 /* recovery has failed... */
72fd0718 10265 bnx2x_set_power_state(bp, PCI_D3hot);
c9ee9206 10266 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 10267
c9ee9206 10268 netdev_err(bp->dev, "Recovery flow hasn't been properly"
72fd0718
VZ		 10269 " completed yet. Try again later. If u still see this"
10270 " message after a few retries then power cycle is"
c9ee9206 10271 " required.\n");
72fd0718
VZ		 10272
10273 return -EAGAIN;
10274 } while (0);
72fd0718
VZ		 10275
10276 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 10277 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 10278}
10279
bb2a0f7a 10280/* called with rtnl_lock */
8304859a 10281int bnx2x_close(struct net_device *dev)
a2fbb9ea 10282{
a2fbb9ea
ET		 10283 struct bnx2x *bp = netdev_priv(dev);
10284
10285 /* Unload the driver, release IRQs */
bb2a0f7a 10286 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
c9ee9206
VZ		 10287
10288 /* Power off */
d3dbfee0 10289 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 10290
10291 return 0;
10292}
10293
619c5cb6
VZ		 10294static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
10295 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 10296{
619c5cb6
VZ		 10297 int mc_count = netdev_mc_count(bp->dev);
10298 struct bnx2x_mcast_list_elem *mc_mac =
10299 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
10300 struct netdev_hw_addr *ha;
6e30dd4e 10301
619c5cb6
VZ		 10302 if (!mc_mac)
10303 return -ENOMEM;
6e30dd4e 10304
619c5cb6 10305 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 10306
619c5cb6
VZ		 10307 netdev_for_each_mc_addr(ha, bp->dev) {
10308 mc_mac->mac = bnx2x_mc_addr(ha);
10309 list_add_tail(&mc_mac->link, &p->mcast_list);
10310 mc_mac++;
6e30dd4e 10311 }
619c5cb6
VZ		 10312
10313 p->mcast_list_len = mc_count;
10314
10315 return 0;
6e30dd4e
VZ		 10316}
10317
619c5cb6
VZ		 10318static inline void bnx2x_free_mcast_macs_list(
10319 struct bnx2x_mcast_ramrod_params *p)
10320{
10321 struct bnx2x_mcast_list_elem *mc_mac =
10322 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10323 link);
10324
10325 WARN_ON(!mc_mac);
10326 kfree(mc_mac);
10327}
10328
10329/**
10330 * bnx2x_set_uc_list - configure a new unicast MACs list.
10331 *
10332 * @bp: driver handle
6e30dd4e 10333 *
619c5cb6 10334 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 10335 */
619c5cb6 10336static inline int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 10337{
619c5cb6 10338 int rc;
6e30dd4e 10339 struct net_device *dev = bp->dev;
6e30dd4e 10340 struct netdev_hw_addr *ha;
619c5cb6
VZ		 10341 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10342 unsigned long ramrod_flags = 0;
6e30dd4e 10343
619c5cb6
VZ		 10344 /* First schedule a cleanup up of old configuration */
10345 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10346 if (rc < 0) {
10347 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10348 return rc;
10349 }
6e30dd4e
VZ		 10350
10351 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 10352 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10353 BNX2X_UC_LIST_MAC, &ramrod_flags);
10354 if (rc < 0) {
10355 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10356 rc);
10357 return rc;
6e30dd4e
VZ		 10358 }
10359 }
10360
619c5cb6
VZ		 10361 /* Execute the pending commands */
10362 __set_bit(RAMROD_CONT, &ramrod_flags);
10363 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10364 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 10365}
10366
619c5cb6 10367static inline int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 10368{
619c5cb6
VZ		 10369 struct net_device *dev = bp->dev;
10370 struct bnx2x_mcast_ramrod_params rparam = {0};
10371 int rc = 0;
6e30dd4e 10372
619c5cb6 10373 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 10374
619c5cb6
VZ		 10375 /* first, clear all configured multicast MACs */
10376 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10377 if (rc < 0) {
10378 BNX2X_ERR("Failed to clear multicast "
10379 "configuration: %d\n", rc);
10380 return rc;
10381 }
6e30dd4e 10382
619c5cb6
VZ		 10383 /* then, configure a new MACs list */
10384 if (netdev_mc_count(dev)) {
10385 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10386 if (rc) {
10387 BNX2X_ERR("Failed to create multicast MACs "
10388 "list: %d\n", rc);
10389 return rc;
10390 }
6e30dd4e 10391
619c5cb6
VZ		 10392 /* Now add the new MACs */
10393 rc = bnx2x_config_mcast(bp, &rparam,
10394 BNX2X_MCAST_CMD_ADD);
10395 if (rc < 0)
10396 BNX2X_ERR("Failed to set a new multicast "
10397 "configuration: %d\n", rc);
6e30dd4e 10398
619c5cb6
VZ		 10399 bnx2x_free_mcast_macs_list(&rparam);
10400 }
6e30dd4e 10401
619c5cb6 10402 return rc;
6e30dd4e
VZ		 10403}
10404
6e30dd4e 10405
619c5cb6 10406/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 10407void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 10408{
10409 struct bnx2x *bp = netdev_priv(dev);
10410 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 10411
10412 if (bp->state != BNX2X_STATE_OPEN) {
10413 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10414 return;
10415 }
10416
619c5cb6 10417 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 10418
10419 if (dev->flags & IFF_PROMISC)
10420 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 10421 else if ((dev->flags & IFF_ALLMULTI) ||
10422 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10423 CHIP_IS_E1(bp)))
34f80b04 10424 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 10425 else {
10426 /* some multicasts */
619c5cb6 10427 if (bnx2x_set_mc_list(bp) < 0)
6e30dd4e 10428 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 10429
619c5cb6 10430 if (bnx2x_set_uc_list(bp) < 0)
6e30dd4e 10431 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 10432 }
10433
10434 bp->rx_mode = rx_mode;
614c76df
DK		 10435#ifdef BCM_CNIC
10436 /* handle ISCSI SD mode */
10437 if (IS_MF_ISCSI_SD(bp))
10438 bp->rx_mode = BNX2X_RX_MODE_NONE;
10439#endif
619c5cb6
VZ		 10440
10441 /* Schedule the rx_mode command */
10442 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10443 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10444 return;
10445 }
10446
34f80b04
EG		 10447 bnx2x_set_storm_rx_mode(bp);
10448}
10449
c18487ee 10450/* called with rtnl_lock */
01cd4528
EG		 10451static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10452 int devad, u16 addr)
a2fbb9ea 10453{
01cd4528
EG		 10454 struct bnx2x *bp = netdev_priv(netdev);
10455 u16 value;
10456 int rc;
a2fbb9ea 10457
01cd4528
EG		 10458 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10459 prtad, devad, addr);
a2fbb9ea 10460
01cd4528
EG		 10461 /* The HW expects different devad if CL22 is used */
10462 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 10463
01cd4528 10464 bnx2x_acquire_phy_lock(bp);
e10bc84d 10465 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 10466 bnx2x_release_phy_lock(bp);
10467 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 10468
01cd4528
EG		 10469 if (!rc)
10470 rc = value;
10471 return rc;
10472}
a2fbb9ea 10473
01cd4528
EG		 10474/* called with rtnl_lock */
10475static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10476 u16 addr, u16 value)
10477{
10478 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 10479 int rc;
10480
10481 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10482 " value 0x%x\n", prtad, devad, addr, value);
10483
01cd4528
EG		 10484 /* The HW expects different devad if CL22 is used */
10485 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 10486
01cd4528 10487 bnx2x_acquire_phy_lock(bp);
e10bc84d 10488 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 10489 bnx2x_release_phy_lock(bp);
10490 return rc;
10491}
c18487ee 10492
01cd4528
EG		 10493/* called with rtnl_lock */
10494static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10495{
10496 struct bnx2x *bp = netdev_priv(dev);
10497 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 10498
01cd4528
EG		 10499 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10500 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 10501
01cd4528
EG		 10502 if (!netif_running(dev))
10503 return -EAGAIN;
10504
10505 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 10506}
10507
257ddbda 10508#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 10509static void poll_bnx2x(struct net_device *dev)
10510{
10511 struct bnx2x *bp = netdev_priv(dev);
10512
10513 disable_irq(bp->pdev->irq);
10514 bnx2x_interrupt(bp->pdev->irq, dev);
10515 enable_irq(bp->pdev->irq);
10516}
10517#endif
10518
614c76df
DK		 10519static int bnx2x_validate_addr(struct net_device *dev)
10520{
10521 struct bnx2x *bp = netdev_priv(dev);
10522
10523 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr))
10524 return -EADDRNOTAVAIL;
10525 return 0;
10526}
10527
c64213cd
SH		 10528static const struct net_device_ops bnx2x_netdev_ops = {
10529 .ndo_open = bnx2x_open,
10530 .ndo_stop = bnx2x_close,
10531 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 10532 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 10533 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 10534 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 10535 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 10536 .ndo_do_ioctl = bnx2x_ioctl,
10537 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 10538 .ndo_fix_features = bnx2x_fix_features,
10539 .ndo_set_features = bnx2x_set_features,
c64213cd 10540 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 10541#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 10542 .ndo_poll_controller = poll_bnx2x,
10543#endif
6383c0b3
AE		 10544 .ndo_setup_tc = bnx2x_setup_tc,
10545
bf61ee14
VZ		 10546#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10547 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10548#endif
c64213cd
SH		 10549};
10550
619c5cb6
VZ		 10551static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10552{
10553 struct device *dev = &bp->pdev->dev;
10554
10555 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10556 bp->flags |= USING_DAC_FLAG;
10557 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10558 dev_err(dev, "dma_set_coherent_mask failed, "
10559 "aborting\n");
10560 return -EIO;
10561 }
10562 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10563 dev_err(dev, "System does not support DMA, aborting\n");
10564 return -EIO;
10565 }
10566
10567 return 0;
10568}
10569
34f80b04 10570static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
619c5cb6
VZ		 10571 struct net_device *dev,
10572 unsigned long board_type)
a2fbb9ea
ET		 10573{
10574 struct bnx2x *bp;
10575 int rc;
c22610d0 10576 u32 pci_cfg_dword;
65087cfe
AE		 10577 bool chip_is_e1x = (board_type == BCM57710 ||
10578 board_type == BCM57711 ||
10579 board_type == BCM57711E);
a2fbb9ea
ET		 10580
10581 SET_NETDEV_DEV(dev, &pdev->dev);
10582 bp = netdev_priv(dev);
10583
34f80b04
EG		 10584 bp->dev = dev;
10585 bp->pdev = pdev;
a2fbb9ea 10586 bp->flags = 0;
a2fbb9ea
ET		 10587
10588 rc = pci_enable_device(pdev);
10589 if (rc) {
cdaa7cb8
VZ		 10590 dev_err(&bp->pdev->dev,
10591 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 10592 goto err_out;
10593 }
10594
10595 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10596 dev_err(&bp->pdev->dev,
10597 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 10598 rc = -ENODEV;
10599 goto err_out_disable;
10600 }
10601
10602 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10603 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10604 " base address, aborting\n");
a2fbb9ea
ET		 10605 rc = -ENODEV;
10606 goto err_out_disable;
10607 }
10608
34f80b04
EG		 10609 if (atomic_read(&pdev->enable_cnt) == 1) {
10610 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10611 if (rc) {
cdaa7cb8
VZ		 10612 dev_err(&bp->pdev->dev,
10613 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 10614 goto err_out_disable;
10615 }
a2fbb9ea 10616
34f80b04
EG		 10617 pci_set_master(pdev);
10618 pci_save_state(pdev);
10619 }
a2fbb9ea
ET		 10620
10621 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10622 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 10623 dev_err(&bp->pdev->dev,
10624 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 10625 rc = -EIO;
10626 goto err_out_release;
10627 }
10628
77c98e6a
JM		 10629 if (!pci_is_pcie(pdev)) {
10630 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 10631 rc = -EIO;
10632 goto err_out_release;
10633 }
10634
619c5cb6
VZ		 10635 rc = bnx2x_set_coherency_mask(bp);
10636 if (rc)
a2fbb9ea 10637 goto err_out_release;
a2fbb9ea 10638
34f80b04
EG		 10639 dev->mem_start = pci_resource_start(pdev, 0);
10640 dev->base_addr = dev->mem_start;
10641 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 10642
10643 dev->irq = pdev->irq;
10644
275f165f 10645 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 10646 if (!bp->regview) {
cdaa7cb8
VZ		 10647 dev_err(&bp->pdev->dev,
10648 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 10649 rc = -ENOMEM;
10650 goto err_out_release;
10651 }
10652
c22610d0
AE		 10653 /* In E1/E1H use pci device function given by kernel.
10654 * In E2/E3 read physical function from ME register since these chips
10655 * support Physical Device Assignment where kernel BDF maybe arbitrary
10656 * (depending on hypervisor).
10657 */
10658 if (chip_is_e1x)
10659 bp->pf_num = PCI_FUNC(pdev->devfn);
10660 else {/* chip is E2/3*/
10661 pci_read_config_dword(bp->pdev,
10662 PCICFG_ME_REGISTER, &pci_cfg_dword);
10663 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
10664 ME_REG_ABS_PF_NUM_SHIFT);
10665 }
10666 DP(BNX2X_MSG_SP, "me reg PF num: %d\n", bp->pf_num);
10667
a2fbb9ea
ET		 10668 bnx2x_set_power_state(bp, PCI_D0);
10669
34f80b04
EG		 10670 /* clean indirect addresses */
10671 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10672 PCICFG_VENDOR_ID_OFFSET);
a5c53dbc
DK		 10673 /*
10674 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 10675 * is not used by the driver.
10676 */
10677 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10678 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10679 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10680 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
a5c53dbc 10681
65087cfe 10682 if (chip_is_e1x) {
a5c53dbc
DK		 10683 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10684 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10685 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10686 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10687 }
a2fbb9ea 10688
2189400b 10689 /*
619c5cb6 10690 * Enable internal target-read (in case we are probed after PF FLR).
2189400b 10691 * Must be done prior to any BAR read access. Only for 57712 and up
619c5cb6 10692 */
65087cfe 10693 if (!chip_is_e1x)
2189400b 10694 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
619c5cb6 10695
72fd0718 10696 /* Reset the load counter */
889b9af3 10697 bnx2x_clear_load_status(bp);
72fd0718 10698
34f80b04 10699 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 10700
c64213cd 10701 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 10702 bnx2x_set_ethtool_ops(dev);
5316bc0b 10703
01789349
JP		 10704 dev->priv_flags |= IFF_UNICAST_FLT;
10705
66371c44 10706 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6e68c912
MS		 10707 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO |
10708 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
66371c44
MM		 10709
10710 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10711 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10712
10713 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 10714 if (bp->flags & USING_DAC_FLAG)
66371c44 10715 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 10716
538dd2e3
MB		 10717 /* Add Loopback capability to the device */
10718 dev->hw_features |= NETIF_F_LOOPBACK;
10719
98507672 10720#ifdef BCM_DCBNL
785b9b1a
SR		 10721 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10722#endif
10723
01cd4528
EG		 10724 /* get_port_hwinfo() will set prtad and mmds properly */
10725 bp->mdio.prtad = MDIO_PRTAD_NONE;
10726 bp->mdio.mmds = 0;
10727 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10728 bp->mdio.dev = dev;
10729 bp->mdio.mdio_read = bnx2x_mdio_read;
10730 bp->mdio.mdio_write = bnx2x_mdio_write;
10731
a2fbb9ea
ET		 10732 return 0;
10733
a2fbb9ea 10734err_out_release:
34f80b04
EG		 10735 if (atomic_read(&pdev->enable_cnt) == 1)
10736 pci_release_regions(pdev);
a2fbb9ea
ET		 10737
10738err_out_disable:
10739 pci_disable_device(pdev);
10740 pci_set_drvdata(pdev, NULL);
10741
10742err_out:
10743 return rc;
10744}
10745
37f9ce62
EG		 10746static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10747 int *width, int *speed)
25047950
ET		 10748{
10749 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10750
37f9ce62 10751 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 10752
37f9ce62
EG		 10753 /* return value of 1=2.5GHz 2=5GHz */
10754 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 10755}
37f9ce62 10756
6891dd25 10757static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 10758{
37f9ce62 10759 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 10760 struct bnx2x_fw_file_hdr *fw_hdr;
10761 struct bnx2x_fw_file_section *sections;
94a78b79 10762 u32 offset, len, num_ops;
37f9ce62 10763 u16 *ops_offsets;
94a78b79 10764 int i;
37f9ce62 10765 const u8 *fw_ver;
94a78b79
VZ		 10766
10767 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10768 return -EINVAL;
10769
10770 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10771 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10772
10773 /* Make sure none of the offsets and sizes make us read beyond
10774 * the end of the firmware data */
10775 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10776 offset = be32_to_cpu(sections[i].offset);
10777 len = be32_to_cpu(sections[i].len);
10778 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 10779 dev_err(&bp->pdev->dev,
10780 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 10781 return -EINVAL;
10782 }
10783 }
10784
10785 /* Likewise for the init_ops offsets */
10786 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10787 ops_offsets = (u16 *)(firmware->data + offset);
10788 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10789
10790 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10791 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 10792 dev_err(&bp->pdev->dev,
10793 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 10794 return -EINVAL;
10795 }
10796 }
10797
10798 /* Check FW version */
10799 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10800 fw_ver = firmware->data + offset;
10801 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10802 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10803 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10804 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 10805 dev_err(&bp->pdev->dev,
10806 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 10807 fw_ver[0], fw_ver[1], fw_ver[2],
10808 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10809 BCM_5710_FW_MINOR_VERSION,
10810 BCM_5710_FW_REVISION_VERSION,
10811 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 10812 return -EINVAL;
94a78b79
VZ		 10813 }
10814
10815 return 0;
10816}
10817
ab6ad5a4 10818static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10819{
ab6ad5a4
EG		 10820 const __be32 *source = (const __be32 *)_source;
10821 u32 *target = (u32 *)_target;
94a78b79 10822 u32 i;
94a78b79
VZ		 10823
10824 for (i = 0; i < n/4; i++)
10825 target[i] = be32_to_cpu(source[i]);
10826}
10827
10828/*
10829 Ops array is stored in the following format:
10830 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10831 */
ab6ad5a4 10832static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 10833{
ab6ad5a4
EG		 10834 const __be32 *source = (const __be32 *)_source;
10835 struct raw_op *target = (struct raw_op *)_target;
94a78b79 10836 u32 i, j, tmp;
94a78b79 10837
ab6ad5a4 10838 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 10839 tmp = be32_to_cpu(source[j]);
10840 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 10841 target[i].offset = tmp & 0xffffff;
10842 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 10843 }
10844}
ab6ad5a4 10845
523224a3
DK		 10846/**
10847 * IRO array is stored in the following format:
10848 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10849 */
10850static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10851{
10852 const __be32 *source = (const __be32 *)_source;
10853 struct iro *target = (struct iro *)_target;
10854 u32 i, j, tmp;
10855
10856 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10857 target[i].base = be32_to_cpu(source[j]);
10858 j++;
10859 tmp = be32_to_cpu(source[j]);
10860 target[i].m1 = (tmp >> 16) & 0xffff;
10861 target[i].m2 = tmp & 0xffff;
10862 j++;
10863 tmp = be32_to_cpu(source[j]);
10864 target[i].m3 = (tmp >> 16) & 0xffff;
10865 target[i].size = tmp & 0xffff;
10866 j++;
10867 }
10868}
10869
ab6ad5a4 10870static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10871{
ab6ad5a4
EG		 10872 const __be16 *source = (const __be16 *)_source;
10873 u16 *target = (u16 *)_target;
94a78b79 10874 u32 i;
94a78b79
VZ		 10875
10876 for (i = 0; i < n/2; i++)
10877 target[i] = be16_to_cpu(source[i]);
10878}
10879
7995c64e
JP		 10880#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10881do { \
10882 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10883 bp->arr = kmalloc(len, GFP_KERNEL); \
10884 if (!bp->arr) { \
10885 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10886 goto lbl; \
10887 } \
10888 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10889 (u8 *)bp->arr, len); \
10890} while (0)
94a78b79 10891
6891dd25 10892int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 10893{
94a78b79 10894 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 10895 int rc;
94a78b79 10896
94a78b79 10897
eb2afd4a
DK		 10898 if (!bp->firmware) {
10899 const char *fw_file_name;
94a78b79 10900
eb2afd4a
DK		 10901 if (CHIP_IS_E1(bp))
10902 fw_file_name = FW_FILE_NAME_E1;
10903 else if (CHIP_IS_E1H(bp))
10904 fw_file_name = FW_FILE_NAME_E1H;
10905 else if (!CHIP_IS_E1x(bp))
10906 fw_file_name = FW_FILE_NAME_E2;
10907 else {
10908 BNX2X_ERR("Unsupported chip revision\n");
10909 return -EINVAL;
10910 }
10911 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 10912
eb2afd4a
DK		 10913 rc = request_firmware(&bp->firmware, fw_file_name,
10914 &bp->pdev->dev);
10915 if (rc) {
10916 BNX2X_ERR("Can't load firmware file %s\n",
10917 fw_file_name);
10918 goto request_firmware_exit;
10919 }
10920
10921 rc = bnx2x_check_firmware(bp);
10922 if (rc) {
10923 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10924 goto request_firmware_exit;
10925 }
94a78b79
VZ		 10926 }
10927
10928 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10929
10930 /* Initialize the pointers to the init arrays */
10931 /* Blob */
10932 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10933
10934 /* Opcodes */
10935 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10936
10937 /* Offsets */
ab6ad5a4
EG		 10938 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10939 be16_to_cpu_n);
94a78b79
VZ		 10940
10941 /* STORMs firmware */
573f2035
EG		 10942 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10943 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10944 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10945 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10946 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10947 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10948 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10949 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10950 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10951 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10952 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10953 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10954 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10955 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10956 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10957 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 10958 /* IRO */
10959 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 10960
10961 return 0;
ab6ad5a4 10962
523224a3
DK		 10963iro_alloc_err:
10964 kfree(bp->init_ops_offsets);
94a78b79
VZ		 10965init_offsets_alloc_err:
10966 kfree(bp->init_ops);
10967init_ops_alloc_err:
10968 kfree(bp->init_data);
10969request_firmware_exit:
10970 release_firmware(bp->firmware);
10971
10972 return rc;
10973}
10974
619c5cb6
VZ		 10975static void bnx2x_release_firmware(struct bnx2x *bp)
10976{
10977 kfree(bp->init_ops_offsets);
10978 kfree(bp->init_ops);
10979 kfree(bp->init_data);
10980 release_firmware(bp->firmware);
eb2afd4a 10981 bp->firmware = NULL;
619c5cb6
VZ		 10982}
10983
10984
10985static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10986 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10987 .init_hw_cmn = bnx2x_init_hw_common,
10988 .init_hw_port = bnx2x_init_hw_port,
10989 .init_hw_func = bnx2x_init_hw_func,
10990
10991 .reset_hw_cmn = bnx2x_reset_common,
10992 .reset_hw_port = bnx2x_reset_port,
10993 .reset_hw_func = bnx2x_reset_func,
10994
10995 .gunzip_init = bnx2x_gunzip_init,
10996 .gunzip_end = bnx2x_gunzip_end,
10997
10998 .init_fw = bnx2x_init_firmware,
10999 .release_fw = bnx2x_release_firmware,
11000};
11001
11002void bnx2x__init_func_obj(struct bnx2x *bp)
11003{
11004 /* Prepare DMAE related driver resources */
11005 bnx2x_setup_dmae(bp);
11006
11007 bnx2x_init_func_obj(bp, &bp->func_obj,
11008 bnx2x_sp(bp, func_rdata),
11009 bnx2x_sp_mapping(bp, func_rdata),
11010 &bnx2x_func_sp_drv);
11011}
11012
11013/* must be called after sriov-enable */
6383c0b3 11014static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 11015{
6383c0b3 11016 int cid_count = BNX2X_L2_CID_COUNT(bp);
94a78b79 11017
523224a3
DK		 11018#ifdef BCM_CNIC
11019 cid_count += CNIC_CID_MAX;
11020#endif
11021 return roundup(cid_count, QM_CID_ROUND);
11022}
f85582f8 11023
619c5cb6 11024/**
6383c0b3 11025 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 11026 *
11027 * @dev: pci device
11028 *
11029 */
6383c0b3 11030static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
619c5cb6
VZ		 11031{
11032 int pos;
11033 u16 control;
11034
11035 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 11036
11037 /*
11038 * If MSI-X is not supported - return number of SBs needed to support
11039 * one fast path queue: one FP queue + SB for CNIC
11040 */
619c5cb6 11041 if (!pos)
6383c0b3 11042 return 1 + CNIC_PRESENT;
619c5cb6 11043
6383c0b3
AE		 11044 /*
11045 * The value in the PCI configuration space is the index of the last
11046 * entry, namely one less than the actual size of the table, which is
11047 * exactly what we want to return from this function: number of all SBs
11048 * without the default SB.
11049 */
619c5cb6 11050 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
6383c0b3 11051 return control & PCI_MSIX_FLAGS_QSIZE;
619c5cb6
VZ		 11052}
11053
a2fbb9ea
ET		 11054static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11055 const struct pci_device_id *ent)
11056{
a2fbb9ea
ET		 11057 struct net_device *dev = NULL;
11058 struct bnx2x *bp;
37f9ce62 11059 int pcie_width, pcie_speed;
6383c0b3
AE		 11060 int rc, max_non_def_sbs;
11061 int rx_count, tx_count, rss_count;
11062 /*
11063 * An estimated maximum supported CoS number according to the chip
11064 * version.
11065 * We will try to roughly estimate the maximum number of CoSes this chip
11066 * may support in order to minimize the memory allocated for Tx
11067 * netdev_queue's. This number will be accurately calculated during the
11068 * initialization of bp->max_cos based on the chip versions AND chip
11069 * revision in the bnx2x_init_bp().
11070 */
11071 u8 max_cos_est = 0;
523224a3 11072
f2e0899f
DK		 11073 switch (ent->driver_data) {
11074 case BCM57710:
11075 case BCM57711:
11076 case BCM57711E:
6383c0b3
AE		 11077 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11078 break;
11079
f2e0899f 11080 case BCM57712:
619c5cb6 11081 case BCM57712_MF:
6383c0b3
AE		 11082 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11083 break;
11084
619c5cb6
VZ		 11085 case BCM57800:
11086 case BCM57800_MF:
11087 case BCM57810:
11088 case BCM57810_MF:
11089 case BCM57840:
11090 case BCM57840_MF:
6383c0b3 11091 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
f2e0899f 11092 break;
a2fbb9ea 11093
f2e0899f
DK		 11094 default:
11095 pr_err("Unknown board_type (%ld), aborting\n",
11096 ent->driver_data);
870634b0 11097 return -ENODEV;
f2e0899f
DK		 11098 }
11099
6383c0b3
AE		 11100 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11101
11102 /* !!! FIXME !!!
11103 * Do not allow the maximum SB count to grow above 16
11104 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
11105 * We will use the FP_SB_MAX_E1x macro for this matter.
11106 */
11107 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
11108
11109 WARN_ON(!max_non_def_sbs);
11110
11111 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11112 rss_count = max_non_def_sbs - CNIC_PRESENT;
11113
11114 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11115 rx_count = rss_count + FCOE_PRESENT;
11116
11117 /*
11118 * Maximum number of netdev Tx queues:
11119 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11120 */
11121 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
f85582f8 11122
a2fbb9ea 11123 /* dev zeroed in init_etherdev */
6383c0b3 11124 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
34f80b04 11125 if (!dev) {
cdaa7cb8 11126 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 11127 return -ENOMEM;
34f80b04 11128 }
a2fbb9ea 11129
a2fbb9ea 11130 bp = netdev_priv(dev);
a2fbb9ea 11131
6383c0b3
AE		 11132 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
11133 tx_count, rx_count);
df4770de 11134
6383c0b3
AE		 11135 bp->igu_sb_cnt = max_non_def_sbs;
11136 bp->msg_enable = debug;
11137 pci_set_drvdata(pdev, dev);
523224a3 11138
619c5cb6 11139 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
a2fbb9ea
ET		 11140 if (rc < 0) {
11141 free_netdev(dev);
11142 return rc;
11143 }
11144
94f05b0f 11145 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs);
619c5cb6 11146
34f80b04 11147 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 11148 if (rc)
11149 goto init_one_exit;
11150
6383c0b3
AE		 11151 /*
11152 * Map doorbels here as we need the real value of bp->max_cos which
11153 * is initialized in bnx2x_init_bp().
11154 */
11155 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11156 min_t(u64, BNX2X_DB_SIZE(bp),
11157 pci_resource_len(pdev, 2)));
11158 if (!bp->doorbells) {
11159 dev_err(&bp->pdev->dev,
11160 "Cannot map doorbell space, aborting\n");
11161 rc = -ENOMEM;
11162 goto init_one_exit;
11163 }
11164
523224a3 11165 /* calc qm_cid_count */
6383c0b3 11166 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
523224a3 11167
ec6ba945 11168#ifdef BCM_CNIC
62ac0dc9
DK		 11169 /* disable FCOE L2 queue for E1x */
11170 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 11171 bp->flags |= NO_FCOE_FLAG;
11172
11173#endif
11174
25985edc 11175 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 11176 * needed, set bp->num_queues appropriately.
11177 */
11178 bnx2x_set_int_mode(bp);
11179
11180 /* Add all NAPI objects */
11181 bnx2x_add_all_napi(bp);
11182
b340007f
VZ		 11183 rc = register_netdev(dev);
11184 if (rc) {
11185 dev_err(&pdev->dev, "Cannot register net device\n");
11186 goto init_one_exit;
11187 }
11188
ec6ba945
VZ		 11189#ifdef BCM_CNIC
11190 if (!NO_FCOE(bp)) {
11191 /* Add storage MAC address */
11192 rtnl_lock();
11193 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11194 rtnl_unlock();
11195 }
11196#endif
11197
37f9ce62 11198 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 11199
94f05b0f
JP		 11200 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11201 board_info[ent->driver_data].name,
11202 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11203 pcie_width,
11204 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11205 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11206 "5GHz (Gen2)" : "2.5GHz",
11207 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 11208
a2fbb9ea 11209 return 0;
34f80b04
EG		 11210
11211init_one_exit:
11212 if (bp->regview)
11213 iounmap(bp->regview);
11214
11215 if (bp->doorbells)
11216 iounmap(bp->doorbells);
11217
11218 free_netdev(dev);
11219
11220 if (atomic_read(&pdev->enable_cnt) == 1)
11221 pci_release_regions(pdev);
11222
11223 pci_disable_device(pdev);
11224 pci_set_drvdata(pdev, NULL);
11225
11226 return rc;
a2fbb9ea
ET		 11227}
11228
11229static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11230{
11231 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 11232 struct bnx2x *bp;
11233
11234 if (!dev) {
cdaa7cb8 11235 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 11236 return;
11237 }
228241eb 11238 bp = netdev_priv(dev);
a2fbb9ea 11239
ec6ba945
VZ		 11240#ifdef BCM_CNIC
11241 /* Delete storage MAC address */
11242 if (!NO_FCOE(bp)) {
11243 rtnl_lock();
11244 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11245 rtnl_unlock();
11246 }
11247#endif
11248
98507672
SR		 11249#ifdef BCM_DCBNL
11250 /* Delete app tlvs from dcbnl */
11251 bnx2x_dcbnl_update_applist(bp, true);
11252#endif
11253
a2fbb9ea
ET		 11254 unregister_netdev(dev);
11255
d6214d7a
DK		 11256 /* Delete all NAPI objects */
11257 bnx2x_del_all_napi(bp);
11258
084d6cbb
VZ		 11259 /* Power on: we can't let PCI layer write to us while we are in D3 */
11260 bnx2x_set_power_state(bp, PCI_D0);
11261
d6214d7a
DK		 11262 /* Disable MSI/MSI-X */
11263 bnx2x_disable_msi(bp);
f85582f8 11264
084d6cbb
VZ		 11265 /* Power off */
11266 bnx2x_set_power_state(bp, PCI_D3hot);
11267
72fd0718 11268 /* Make sure RESET task is not scheduled before continuing */
7be08a72 11269 cancel_delayed_work_sync(&bp->sp_rtnl_task);
72fd0718 11270
a2fbb9ea
ET		 11271 if (bp->regview)
11272 iounmap(bp->regview);
11273
11274 if (bp->doorbells)
11275 iounmap(bp->doorbells);
11276
eb2afd4a
DK		 11277 bnx2x_release_firmware(bp);
11278
523224a3
DK		 11279 bnx2x_free_mem_bp(bp);
11280
a2fbb9ea 11281 free_netdev(dev);
34f80b04
EG		 11282
11283 if (atomic_read(&pdev->enable_cnt) == 1)
11284 pci_release_regions(pdev);
11285
a2fbb9ea
ET		 11286 pci_disable_device(pdev);
11287 pci_set_drvdata(pdev, NULL);
11288}
11289
f8ef6e44
YG		 11290static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
11291{
11292 int i;
11293
11294 bp->state = BNX2X_STATE_ERROR;
11295
11296 bp->rx_mode = BNX2X_RX_MODE_NONE;
11297
619c5cb6
VZ		 11298#ifdef BCM_CNIC
11299 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
11300#endif
11301 /* Stop Tx */
11302 bnx2x_tx_disable(bp);
11303
f8ef6e44
YG		 11304 bnx2x_netif_stop(bp, 0);
11305
11306 del_timer_sync(&bp->timer);
619c5cb6
VZ		 11307
11308 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 11309
11310 /* Release IRQs */
d6214d7a 11311 bnx2x_free_irq(bp);
f8ef6e44 11312
f8ef6e44
YG		 11313 /* Free SKBs, SGEs, TPA pool and driver internals */
11314 bnx2x_free_skbs(bp);
523224a3 11315
ec6ba945 11316 for_each_rx_queue(bp, i)
f8ef6e44 11317 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 11318
f8ef6e44
YG		 11319 bnx2x_free_mem(bp);
11320
11321 bp->state = BNX2X_STATE_CLOSED;
11322
619c5cb6
VZ		 11323 netif_carrier_off(bp->dev);
11324
f8ef6e44
YG		 11325 return 0;
11326}
11327
11328static void bnx2x_eeh_recover(struct bnx2x *bp)
11329{
11330 u32 val;
11331
11332 mutex_init(&bp->port.phy_mutex);
11333
11334 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
11335 bp->link_params.shmem_base = bp->common.shmem_base;
11336 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
11337
11338 if (!bp->common.shmem_base ||
11339 (bp->common.shmem_base < 0xA0000) ||
11340 (bp->common.shmem_base >= 0xC0000)) {
11341 BNX2X_DEV_INFO("MCP not active\n");
11342 bp->flags |= NO_MCP_FLAG;
11343 return;
11344 }
11345
11346 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
11347 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11348 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11349 BNX2X_ERR("BAD MCP validity signature\n");
f8ef6e44
YG		 11350}
11351
493adb1f
WX		 11352/**
11353 * bnx2x_io_error_detected - called when PCI error is detected
11354 * @pdev: Pointer to PCI device
11355 * @state: The current pci connection state
11356 *
11357 * This function is called after a PCI bus error affecting
11358 * this device has been detected.
11359 */
11360static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11361 pci_channel_state_t state)
11362{
11363 struct net_device *dev = pci_get_drvdata(pdev);
11364 struct bnx2x *bp = netdev_priv(dev);
11365
11366 rtnl_lock();
11367
11368 netif_device_detach(dev);
11369
07ce50e4
DN		 11370 if (state == pci_channel_io_perm_failure) {
11371 rtnl_unlock();
11372 return PCI_ERS_RESULT_DISCONNECT;
11373 }
11374
493adb1f 11375 if (netif_running(dev))
f8ef6e44 11376 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 11377
11378 pci_disable_device(pdev);
11379
11380 rtnl_unlock();
11381
11382 /* Request a slot reset */
11383 return PCI_ERS_RESULT_NEED_RESET;
11384}
11385
11386/**
11387 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11388 * @pdev: Pointer to PCI device
11389 *
11390 * Restart the card from scratch, as if from a cold-boot.
11391 */
11392static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11393{
11394 struct net_device *dev = pci_get_drvdata(pdev);
11395 struct bnx2x *bp = netdev_priv(dev);
11396
11397 rtnl_lock();
11398
11399 if (pci_enable_device(pdev)) {
11400 dev_err(&pdev->dev,
11401 "Cannot re-enable PCI device after reset\n");
11402 rtnl_unlock();
11403 return PCI_ERS_RESULT_DISCONNECT;
11404 }
11405
11406 pci_set_master(pdev);
11407 pci_restore_state(pdev);
11408
11409 if (netif_running(dev))
11410 bnx2x_set_power_state(bp, PCI_D0);
11411
11412 rtnl_unlock();
11413
11414 return PCI_ERS_RESULT_RECOVERED;
11415}
11416
11417/**
11418 * bnx2x_io_resume - called when traffic can start flowing again
11419 * @pdev: Pointer to PCI device
11420 *
11421 * This callback is called when the error recovery driver tells us that
11422 * its OK to resume normal operation.
11423 */
11424static void bnx2x_io_resume(struct pci_dev *pdev)
11425{
11426 struct net_device *dev = pci_get_drvdata(pdev);
11427 struct bnx2x *bp = netdev_priv(dev);
11428
72fd0718 11429 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
754a2f52
DK		 11430 netdev_err(bp->dev, "Handling parity error recovery. "
11431 "Try again later\n");
72fd0718
VZ		 11432 return;
11433 }
11434
493adb1f
WX		 11435 rtnl_lock();
11436
f8ef6e44
YG		 11437 bnx2x_eeh_recover(bp);
11438
493adb1f 11439 if (netif_running(dev))
f8ef6e44 11440 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 11441
11442 netif_device_attach(dev);
11443
11444 rtnl_unlock();
11445}
11446
11447static struct pci_error_handlers bnx2x_err_handler = {
11448 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 11449 .slot_reset = bnx2x_io_slot_reset,
11450 .resume = bnx2x_io_resume,
493adb1f
WX		 11451};
11452
a2fbb9ea 11453static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 11454 .name = DRV_MODULE_NAME,
11455 .id_table = bnx2x_pci_tbl,
11456 .probe = bnx2x_init_one,
11457 .remove = __devexit_p(bnx2x_remove_one),
11458 .suspend = bnx2x_suspend,
11459 .resume = bnx2x_resume,
11460 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 11461};
11462
11463static int __init bnx2x_init(void)
11464{
dd21ca6d
SG		 11465 int ret;
11466
7995c64e 11467 pr_info("%s", version);
938cf541 11468
1cf167f2
EG		 11469 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11470 if (bnx2x_wq == NULL) {
7995c64e 11471 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 11472 return -ENOMEM;
11473 }
11474
dd21ca6d
SG		 11475 ret = pci_register_driver(&bnx2x_pci_driver);
11476 if (ret) {
7995c64e 11477 pr_err("Cannot register driver\n");
dd21ca6d
SG		 11478 destroy_workqueue(bnx2x_wq);
11479 }
11480 return ret;
a2fbb9ea
ET		 11481}
11482
11483static void __exit bnx2x_cleanup(void)
11484{
11485 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 11486
11487 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 11488}
11489
3deb8167
YR		 11490void bnx2x_notify_link_changed(struct bnx2x *bp)
11491{
11492 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11493}
11494
a2fbb9ea
ET		 11495module_init(bnx2x_init);
11496module_exit(bnx2x_cleanup);
11497
993ac7b5 11498#ifdef BCM_CNIC
619c5cb6
VZ		 11499/**
11500 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11501 *
11502 * @bp: driver handle
11503 * @set: set or clear the CAM entry
11504 *
11505 * This function will wait until the ramdord completion returns.
11506 * Return 0 if success, -ENODEV if ramrod doesn't return.
11507 */
11508static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11509{
11510 unsigned long ramrod_flags = 0;
11511
11512 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11513 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11514 &bp->iscsi_l2_mac_obj, true,
11515 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11516}
993ac7b5
MC		 11517
11518/* count denotes the number of new completions we have seen */
11519static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11520{
11521 struct eth_spe *spe;
11522
11523#ifdef BNX2X_STOP_ON_ERROR
11524 if (unlikely(bp->panic))
11525 return;
11526#endif
11527
11528 spin_lock_bh(&bp->spq_lock);
c2bff63f 11529 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 11530 bp->cnic_spq_pending -= count;
11531
993ac7b5 11532
c2bff63f
DK		 11533 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11534 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11535 & SPE_HDR_CONN_TYPE) >>
11536 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 11537 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11538 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 11539
11540 /* Set validation for iSCSI L2 client before sending SETUP
11541 * ramrod
11542 */
11543 if (type == ETH_CONNECTION_TYPE) {
c2bff63f 11544 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
619c5cb6
VZ		 11545 bnx2x_set_ctx_validation(bp, &bp->context.
11546 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11547 BNX2X_ISCSI_ETH_CID);
c2bff63f
DK		 11548 }
11549
619c5cb6
VZ		 11550 /*
11551 * There may be not more than 8 L2, not more than 8 L5 SPEs
11552 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 11553 * COMMON ramrods is not more than the EQ and SPQ can
11554 * accommodate.
c2bff63f 11555 */
6e30dd4e
VZ		 11556 if (type == ETH_CONNECTION_TYPE) {
11557 if (!atomic_read(&bp->cq_spq_left))
11558 break;
11559 else
11560 atomic_dec(&bp->cq_spq_left);
11561 } else if (type == NONE_CONNECTION_TYPE) {
11562 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 11563 break;
11564 else
6e30dd4e 11565 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 11566 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11567 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 11568 if (bp->cnic_spq_pending >=
11569 bp->cnic_eth_dev.max_kwqe_pending)
11570 break;
11571 else
11572 bp->cnic_spq_pending++;
11573 } else {
11574 BNX2X_ERR("Unknown SPE type: %d\n", type);
11575 bnx2x_panic();
993ac7b5 11576 break;
c2bff63f 11577 }
993ac7b5
MC		 11578
11579 spe = bnx2x_sp_get_next(bp);
11580 *spe = *bp->cnic_kwq_cons;
11581
993ac7b5
MC		 11582 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11583 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11584
11585 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11586 bp->cnic_kwq_cons = bp->cnic_kwq;
11587 else
11588 bp->cnic_kwq_cons++;
11589 }
11590 bnx2x_sp_prod_update(bp);
11591 spin_unlock_bh(&bp->spq_lock);
11592}
11593
11594static int bnx2x_cnic_sp_queue(struct net_device *dev,
11595 struct kwqe_16 *kwqes[], u32 count)
11596{
11597 struct bnx2x *bp = netdev_priv(dev);
11598 int i;
11599
11600#ifdef BNX2X_STOP_ON_ERROR
11601 if (unlikely(bp->panic))
11602 return -EIO;
11603#endif
11604
95c6c616
AE		 11605 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
11606 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
11607 netdev_err(dev, "Handling parity error recovery. Try again "
11608 "later\n");
11609 return -EAGAIN;
11610 }
11611
993ac7b5
MC		 11612 spin_lock_bh(&bp->spq_lock);
11613
11614 for (i = 0; i < count; i++) {
11615 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11616
11617 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11618 break;
11619
11620 *bp->cnic_kwq_prod = *spe;
11621
11622 bp->cnic_kwq_pending++;
11623
11624 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11625 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 11626 spe->data.update_data_addr.hi,
11627 spe->data.update_data_addr.lo,
993ac7b5
MC		 11628 bp->cnic_kwq_pending);
11629
11630 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11631 bp->cnic_kwq_prod = bp->cnic_kwq;
11632 else
11633 bp->cnic_kwq_prod++;
11634 }
11635
11636 spin_unlock_bh(&bp->spq_lock);
11637
11638 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11639 bnx2x_cnic_sp_post(bp, 0);
11640
11641 return i;
11642}
11643
11644static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11645{
11646 struct cnic_ops *c_ops;
11647 int rc = 0;
11648
11649 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 11650 c_ops = rcu_dereference_protected(bp->cnic_ops,
11651 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 11652 if (c_ops)
11653 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11654 mutex_unlock(&bp->cnic_mutex);
11655
11656 return rc;
11657}
11658
11659static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11660{
11661 struct cnic_ops *c_ops;
11662 int rc = 0;
11663
11664 rcu_read_lock();
11665 c_ops = rcu_dereference(bp->cnic_ops);
11666 if (c_ops)
11667 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11668 rcu_read_unlock();
11669
11670 return rc;
11671}
11672
11673/*
11674 * for commands that have no data
11675 */
9f6c9258 11676int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 11677{
11678 struct cnic_ctl_info ctl = {0};
11679
11680 ctl.cmd = cmd;
11681
11682 return bnx2x_cnic_ctl_send(bp, &ctl);
11683}
11684
619c5cb6 11685static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 11686{
619c5cb6 11687 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 11688
11689 /* first we tell CNIC and only then we count this as a completion */
11690 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11691 ctl.data.comp.cid = cid;
619c5cb6 11692 ctl.data.comp.error = err;
993ac7b5
MC		 11693
11694 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 11695 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 11696}
11697
619c5cb6
VZ		 11698
11699/* Called with netif_addr_lock_bh() taken.
11700 * Sets an rx_mode config for an iSCSI ETH client.
11701 * Doesn't block.
11702 * Completion should be checked outside.
11703 */
11704static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11705{
11706 unsigned long accept_flags = 0, ramrod_flags = 0;
11707 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11708 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11709
11710 if (start) {
11711 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11712 * because it's the only way for UIO Queue to accept
11713 * multicasts (in non-promiscuous mode only one Queue per
11714 * function will receive multicast packets (leading in our
11715 * case).
11716 */
11717 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11718 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11719 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11720 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11721
11722 /* Clear STOP_PENDING bit if START is requested */
11723 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11724
11725 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11726 } else
11727 /* Clear START_PENDING bit if STOP is requested */
11728 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11729
11730 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11731 set_bit(sched_state, &bp->sp_state);
11732 else {
11733 __set_bit(RAMROD_RX, &ramrod_flags);
11734 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11735 ramrod_flags);
11736 }
11737}
11738
11739
993ac7b5
MC		 11740static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11741{
11742 struct bnx2x *bp = netdev_priv(dev);
11743 int rc = 0;
11744
11745 switch (ctl->cmd) {
11746 case DRV_CTL_CTXTBL_WR_CMD: {
11747 u32 index = ctl->data.io.offset;
11748 dma_addr_t addr = ctl->data.io.dma_addr;
11749
11750 bnx2x_ilt_wr(bp, index, addr);
11751 break;
11752 }
11753
c2bff63f
DK		 11754 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11755 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 11756
11757 bnx2x_cnic_sp_post(bp, count);
11758 break;
11759 }
11760
11761 /* rtnl_lock is held. */
11762 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 11763 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11764 unsigned long sp_bits = 0;
11765
11766 /* Configure the iSCSI classification object */
11767 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11768 cp->iscsi_l2_client_id,
11769 cp->iscsi_l2_cid, BP_FUNC(bp),
11770 bnx2x_sp(bp, mac_rdata),
11771 bnx2x_sp_mapping(bp, mac_rdata),
11772 BNX2X_FILTER_MAC_PENDING,
11773 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11774 &bp->macs_pool);
ec6ba945 11775
523224a3 11776 /* Set iSCSI MAC address */
619c5cb6
VZ		 11777 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11778 if (rc)
11779 break;
523224a3
DK		 11780
11781 mmiowb();
11782 barrier();
11783
619c5cb6
VZ		 11784 /* Start accepting on iSCSI L2 ring */
11785
11786 netif_addr_lock_bh(dev);
11787 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11788 netif_addr_unlock_bh(dev);
11789
11790 /* bits to wait on */
11791 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11792 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11793
11794 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11795 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 11796
993ac7b5
MC		 11797 break;
11798 }
11799
11800 /* rtnl_lock is held. */
11801 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 11802 unsigned long sp_bits = 0;
993ac7b5 11803
523224a3 11804 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 11805 netif_addr_lock_bh(dev);
11806 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11807 netif_addr_unlock_bh(dev);
11808
11809 /* bits to wait on */
11810 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11811 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11812
11813 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11814 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 11815
11816 mmiowb();
11817 barrier();
11818
11819 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 11820 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11821 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 11822 break;
11823 }
c2bff63f
DK		 11824 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11825 int count = ctl->data.credit.credit_count;
11826
11827 smp_mb__before_atomic_inc();
6e30dd4e 11828 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 11829 smp_mb__after_atomic_inc();
11830 break;
11831 }
1d187b34
BW		 11832 case DRV_CTL_ULP_REGISTER_CMD: {
11833 int ulp_type = ctl->data.ulp_type;
11834
11835 if (CHIP_IS_E3(bp)) {
11836 int idx = BP_FW_MB_IDX(bp);
11837 u32 cap;
11838
11839 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11840 if (ulp_type == CNIC_ULP_ISCSI)
11841 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11842 else if (ulp_type == CNIC_ULP_FCOE)
11843 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11844 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11845 }
11846 break;
11847 }
11848 case DRV_CTL_ULP_UNREGISTER_CMD: {
11849 int ulp_type = ctl->data.ulp_type;
11850
11851 if (CHIP_IS_E3(bp)) {
11852 int idx = BP_FW_MB_IDX(bp);
11853 u32 cap;
11854
11855 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
11856 if (ulp_type == CNIC_ULP_ISCSI)
11857 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
11858 else if (ulp_type == CNIC_ULP_FCOE)
11859 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
11860 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
11861 }
11862 break;
11863 }
993ac7b5
MC		 11864
11865 default:
11866 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11867 rc = -EINVAL;
11868 }
11869
11870 return rc;
11871}
11872
9f6c9258 11873void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 11874{
11875 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11876
11877 if (bp->flags & USING_MSIX_FLAG) {
11878 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11879 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11880 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11881 } else {
11882 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11883 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11884 }
619c5cb6 11885 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 11886 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11887 else
11888 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11889
619c5cb6
VZ		 11890 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11891 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 11892 cp->irq_arr[1].status_blk = bp->def_status_blk;
11893 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 11894 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 11895
11896 cp->num_irq = 2;
11897}
11898
11899static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11900 void *data)
11901{
11902 struct bnx2x *bp = netdev_priv(dev);
11903 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11904
11905 if (ops == NULL)
11906 return -EINVAL;
11907
993ac7b5
MC		 11908 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11909 if (!bp->cnic_kwq)
11910 return -ENOMEM;
11911
11912 bp->cnic_kwq_cons = bp->cnic_kwq;
11913 bp->cnic_kwq_prod = bp->cnic_kwq;
11914 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11915
11916 bp->cnic_spq_pending = 0;
11917 bp->cnic_kwq_pending = 0;
11918
11919 bp->cnic_data = data;
11920
11921 cp->num_irq = 0;
619c5cb6 11922 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 11923 cp->iro_arr = bp->iro_arr;
993ac7b5 11924
993ac7b5 11925 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 11926
993ac7b5
MC		 11927 rcu_assign_pointer(bp->cnic_ops, ops);
11928
11929 return 0;
11930}
11931
11932static int bnx2x_unregister_cnic(struct net_device *dev)
11933{
11934 struct bnx2x *bp = netdev_priv(dev);
11935 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11936
11937 mutex_lock(&bp->cnic_mutex);
993ac7b5 11938 cp->drv_state = 0;
2cfa5a04 11939 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 11940 mutex_unlock(&bp->cnic_mutex);
11941 synchronize_rcu();
11942 kfree(bp->cnic_kwq);
11943 bp->cnic_kwq = NULL;
11944
11945 return 0;
11946}
11947
11948struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11949{
11950 struct bnx2x *bp = netdev_priv(dev);
11951 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11952
2ba45142
VZ		 11953 /* If both iSCSI and FCoE are disabled - return NULL in
11954 * order to indicate CNIC that it should not try to work
11955 * with this device.
11956 */
11957 if (NO_ISCSI(bp) && NO_FCOE(bp))
11958 return NULL;
11959
993ac7b5
MC		 11960 cp->drv_owner = THIS_MODULE;
11961 cp->chip_id = CHIP_ID(bp);
11962 cp->pdev = bp->pdev;
11963 cp->io_base = bp->regview;
11964 cp->io_base2 = bp->doorbells;
11965 cp->max_kwqe_pending = 8;
523224a3 11966 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 11967 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11968 bnx2x_cid_ilt_lines(bp);
993ac7b5 11969 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 11970 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 11971 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11972 cp->drv_ctl = bnx2x_drv_ctl;
11973 cp->drv_register_cnic = bnx2x_register_cnic;
11974 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945 11975 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
619c5cb6
VZ		 11976 cp->iscsi_l2_client_id =
11977 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
c2bff63f
DK		 11978 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11979
2ba45142
VZ		 11980 if (NO_ISCSI_OOO(bp))
11981 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11982
11983 if (NO_ISCSI(bp))
11984 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11985
11986 if (NO_FCOE(bp))
11987 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11988
c2bff63f
DK		 11989 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11990 "starting cid %d\n",
11991 cp->ctx_blk_size,
11992 cp->ctx_tbl_offset,
11993 cp->ctx_tbl_len,
11994 cp->starting_cid);
993ac7b5
MC		 11995 return cp;
11996}
11997EXPORT_SYMBOL(bnx2x_cnic_probe);
11998
11999#endif /* BCM_CNIC */
94a78b79 12000
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