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bnx2x: Support of PF driver of a VF close request
[thirdparty/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
85b26ea1 3 * Copyright (c) 2007-2012 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/dma-mapping.h>
35#include <linux/bitops.h>
36#include <linux/irq.h>
37#include <linux/delay.h>
38#include <asm/byteorder.h>
39#include <linux/time.h>
40#include <linux/ethtool.h>
41#include <linux/mii.h>
0c6671b0 42#include <linux/if_vlan.h>
a2fbb9ea 43#include <net/ip.h>
619c5cb6 44#include <net/ipv6.h>
a2fbb9ea
ET		 45#include <net/tcp.h>
46#include <net/checksum.h>
34f80b04 47#include <net/ip6_checksum.h>
a2fbb9ea
ET		 48#include <linux/workqueue.h>
49#include <linux/crc32.h>
34f80b04 50#include <linux/crc32c.h>
a2fbb9ea
ET		 51#include <linux/prefetch.h>
52#include <linux/zlib.h>
a2fbb9ea 53#include <linux/io.h>
452427b0 54#include <linux/semaphore.h>
45229b42 55#include <linux/stringify.h>
7ab24bfd 56#include <linux/vmalloc.h>
a2fbb9ea 57
a2fbb9ea
ET		 58#include "bnx2x.h"
59#include "bnx2x_init.h"
94a78b79 60#include "bnx2x_init_ops.h"
9f6c9258 61#include "bnx2x_cmn.h"
1ab4434c
AE		 62#include "bnx2x_vfpf.h"
63#include "bnx2x_sriov.h"
e4901dde 64#include "bnx2x_dcb.h"
042181f5 65#include "bnx2x_sp.h"
a2fbb9ea 66
94a78b79
VZ		 67#include <linux/firmware.h>
68#include "bnx2x_fw_file_hdr.h"
69/* FW files */
45229b42
BH		 70#define FW_FILE_VERSION \
71 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
72 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
73 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
74 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 75#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
76#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 77#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 78
2e499d3c
BW		 79#define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
80
34f80b04
EG		 81/* Time in jiffies before concluding the transmitter is hung */
82#define TX_TIMEOUT (5*HZ)
a2fbb9ea 83
0329aba1 84static char version[] =
619c5cb6 85 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 86 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
87
24e3fcef 88MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 89MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 90 "BCM57710/57711/57711E/"
91 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
92 "57840/57840_MF Driver");
a2fbb9ea
ET		 93MODULE_LICENSE("GPL");
94MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 95MODULE_FIRMWARE(FW_FILE_NAME_E1);
96MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 97MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 98
ca00392c 99
d6214d7a 100int num_queues;
54b9ddaa 101module_param(num_queues, int, 0);
96305234
DK		 102MODULE_PARM_DESC(num_queues,
103 " Set number of queues (default is as a number of CPUs)");
555f6c78 104
19680c48 105static int disable_tpa;
19680c48 106module_param(disable_tpa, int, 0);
9898f86d 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 108
9ee3d37b
DK		 109#define INT_MODE_INTx 1
110#define INT_MODE_MSI 2
0e8d2ec5 111int int_mode;
8badd27a 112module_param(int_mode, int, 0);
619c5cb6 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 114 "(1 INT#x; 2 MSI)");
8badd27a 115
a18f5128
EG		 116static int dropless_fc;
117module_param(dropless_fc, int, 0);
118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
8d5726c4
EG		 120static int mrrs = -1;
121module_param(mrrs, int, 0);
122MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123
9898f86d 124static int debug;
a2fbb9ea 125module_param(debug, int, 0);
9898f86d
EG		 126MODULE_PARM_DESC(debug, " Default debug msglevel");
127
a2fbb9ea 128
619c5cb6
VZ		 129
130struct workqueue_struct *bnx2x_wq;
ec6ba945 131
a2fbb9ea
ET		 132enum bnx2x_board_type {
133 BCM57710 = 0,
619c5cb6
VZ		 134 BCM57711,
135 BCM57711E,
136 BCM57712,
137 BCM57712_MF,
1ab4434c 138 BCM57712_VF,
619c5cb6
VZ		 139 BCM57800,
140 BCM57800_MF,
1ab4434c 141 BCM57800_VF,
619c5cb6
VZ		 142 BCM57810,
143 BCM57810_MF,
1ab4434c 144 BCM57810_VF,
c3def943
YM		 145 BCM57840_4_10,
146 BCM57840_2_20,
7e8e02df 147 BCM57840_MF,
1ab4434c 148 BCM57840_VF,
7e8e02df 149 BCM57811,
1ab4434c
AE		 150 BCM57811_MF,
151 BCM57840_O,
152 BCM57840_MFO,
153 BCM57811_VF
a2fbb9ea
ET		 154};
155
34f80b04 156/* indexed by board_type, above */
53a10565 157static struct {
a2fbb9ea 158 char *name;
0329aba1 159} board_info[] = {
1ab4434c
AE		 160 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
161 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
162 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
163 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
164 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
165 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
166 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
167 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
168 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
169 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
170 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
171 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
172 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
173 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
174 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
175 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
176 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
177 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
178 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
179 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
180 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 181};
182
619c5cb6
VZ		 183#ifndef PCI_DEVICE_ID_NX2_57710
184#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
185#endif
186#ifndef PCI_DEVICE_ID_NX2_57711
187#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
188#endif
189#ifndef PCI_DEVICE_ID_NX2_57711E
190#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
191#endif
192#ifndef PCI_DEVICE_ID_NX2_57712
193#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
194#endif
195#ifndef PCI_DEVICE_ID_NX2_57712_MF
196#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
197#endif
198#ifndef PCI_DEVICE_ID_NX2_57800
199#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
200#endif
201#ifndef PCI_DEVICE_ID_NX2_57800_MF
202#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
203#endif
204#ifndef PCI_DEVICE_ID_NX2_57810
205#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
206#endif
207#ifndef PCI_DEVICE_ID_NX2_57810_MF
208#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
209#endif
c3def943
YM		 210#ifndef PCI_DEVICE_ID_NX2_57840_O
211#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
212#endif
213#ifndef PCI_DEVICE_ID_NX2_57840_4_10
214#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
215#endif
216#ifndef PCI_DEVICE_ID_NX2_57840_2_20
217#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
218#endif
219#ifndef PCI_DEVICE_ID_NX2_57840_MFO
220#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 221#endif
222#ifndef PCI_DEVICE_ID_NX2_57840_MF
223#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
224#endif
7e8e02df
BW		 225#ifndef PCI_DEVICE_ID_NX2_57811
226#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
227#endif
228#ifndef PCI_DEVICE_ID_NX2_57811_MF
229#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
230#endif
a3aa1884 231static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 232 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
233 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
234 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 235 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 236 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
237 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
238 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
239 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
240 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 241 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
242 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
243 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
244 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 245 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
7e8e02df
BW		 246 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
247 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
a2fbb9ea
ET		 248 { 0 }
249};
250
251MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
252
452427b0
YM		 253/* Global resources for unloading a previously loaded device */
254#define BNX2X_PREV_WAIT_NEEDED 1
255static DEFINE_SEMAPHORE(bnx2x_prev_sem);
256static LIST_HEAD(bnx2x_prev_list);
a2fbb9ea
ET		 257/****************************************************************************
258* General service functions
259****************************************************************************/
260
1191cb83 261static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 262 u32 addr, dma_addr_t mapping)
263{
264 REG_WR(bp, addr, U64_LO(mapping));
265 REG_WR(bp, addr + 4, U64_HI(mapping));
266}
267
1191cb83
ED		 268static void storm_memset_spq_addr(struct bnx2x *bp,
269 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 270{
271 u32 addr = XSEM_REG_FAST_MEMORY +
272 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
273
274 __storm_memset_dma_mapping(bp, addr, mapping);
275}
276
1191cb83
ED		 277static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
278 u16 pf_id)
523224a3 279{
619c5cb6
VZ		 280 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
281 pf_id);
282 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
283 pf_id);
284 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
285 pf_id);
286 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
287 pf_id);
523224a3
DK		 288}
289
1191cb83
ED		 290static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
291 u8 enable)
619c5cb6
VZ		 292{
293 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
294 enable);
295 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
296 enable);
297 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
298 enable);
299 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
300 enable);
301}
523224a3 302
1191cb83
ED		 303static void storm_memset_eq_data(struct bnx2x *bp,
304 struct event_ring_data *eq_data,
523224a3
DK		 305 u16 pfid)
306{
307 size_t size = sizeof(struct event_ring_data);
308
309 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
310
311 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
312}
313
1191cb83
ED		 314static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
315 u16 pfid)
523224a3
DK		 316{
317 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
318 REG_WR16(bp, addr, eq_prod);
319}
320
a2fbb9ea
ET		 321/* used only at init
322 * locking is done by mcp
323 */
8d96286a 324static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 325{
326 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
327 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
328 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
329 PCICFG_VENDOR_ID_OFFSET);
330}
331
a2fbb9ea
ET		 332static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
333{
334 u32 val;
335
336 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
337 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
338 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
339 PCICFG_VENDOR_ID_OFFSET);
340
341 return val;
342}
a2fbb9ea 343
f2e0899f
DK		 344#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
345#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
346#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
347#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
348#define DMAE_DP_DST_NONE "dst_addr [none]"
349
fd1fc79d
AE		 350void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
351{
352 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
353
354 switch (dmae->opcode & DMAE_COMMAND_DST) {
355 case DMAE_CMD_DST_PCI:
356 if (src_type == DMAE_CMD_SRC_PCI)
357 DP(msglvl, "DMAE: opcode 0x%08x\n"
358 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
359 "comp_addr [%x:%08x], comp_val 0x%08x\n",
360 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
361 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
362 dmae->comp_addr_hi, dmae->comp_addr_lo,
363 dmae->comp_val);
364 else
365 DP(msglvl, "DMAE: opcode 0x%08x\n"
366 "src [%08x], len [%d*4], dst [%x:%08x]\n"
367 "comp_addr [%x:%08x], comp_val 0x%08x\n",
368 dmae->opcode, dmae->src_addr_lo >> 2,
369 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
370 dmae->comp_addr_hi, dmae->comp_addr_lo,
371 dmae->comp_val);
372 break;
373 case DMAE_CMD_DST_GRC:
374 if (src_type == DMAE_CMD_SRC_PCI)
375 DP(msglvl, "DMAE: opcode 0x%08x\n"
376 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
377 "comp_addr [%x:%08x], comp_val 0x%08x\n",
378 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
379 dmae->len, dmae->dst_addr_lo >> 2,
380 dmae->comp_addr_hi, dmae->comp_addr_lo,
381 dmae->comp_val);
382 else
383 DP(msglvl, "DMAE: opcode 0x%08x\n"
384 "src [%08x], len [%d*4], dst [%08x]\n"
385 "comp_addr [%x:%08x], comp_val 0x%08x\n",
386 dmae->opcode, dmae->src_addr_lo >> 2,
387 dmae->len, dmae->dst_addr_lo >> 2,
388 dmae->comp_addr_hi, dmae->comp_addr_lo,
389 dmae->comp_val);
390 break;
391 default:
392 if (src_type == DMAE_CMD_SRC_PCI)
393 DP(msglvl, "DMAE: opcode 0x%08x\n"
394 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
395 "comp_addr [%x:%08x] comp_val 0x%08x\n",
396 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
397 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
398 dmae->comp_val);
399 else
400 DP(msglvl, "DMAE: opcode 0x%08x\n"
401 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
402 "comp_addr [%x:%08x] comp_val 0x%08x\n",
403 dmae->opcode, dmae->src_addr_lo >> 2,
404 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
405 dmae->comp_val);
406 break;
407 }
408}
f2e0899f 409
a2fbb9ea 410/* copy command into DMAE command memory and set DMAE command go */
6c719d00 411void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 412{
413 u32 cmd_offset;
414 int i;
415
416 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
417 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
418 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 419 }
420 REG_WR(bp, dmae_reg_go_c[idx], 1);
421}
422
f2e0899f 423u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 424{
f2e0899f
DK		 425 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
426 DMAE_CMD_C_ENABLE);
427}
ad8d3948 428
f2e0899f
DK		 429u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
430{
431 return opcode & ~DMAE_CMD_SRC_RESET;
432}
ad8d3948 433
f2e0899f
DK		 434u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
435 bool with_comp, u8 comp_type)
436{
437 u32 opcode = 0;
438
439 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
440 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 441
f2e0899f
DK		 442 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
443
444 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 445 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
446 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 447 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 448
a2fbb9ea 449#ifdef __BIG_ENDIAN
f2e0899f 450 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 451#else
f2e0899f 452 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 453#endif
f2e0899f
DK		 454 if (with_comp)
455 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
456 return opcode;
457}
458
fd1fc79d 459void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 460 struct dmae_command *dmae,
461 u8 src_type, u8 dst_type)
f2e0899f
DK		 462{
463 memset(dmae, 0, sizeof(struct dmae_command));
464
465 /* set the opcode */
466 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
467 true, DMAE_COMP_PCI);
468
469 /* fill in the completion parameters */
470 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
471 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
472 dmae->comp_val = DMAE_COMP_VAL;
473}
474
fd1fc79d
AE		 475/* issue a dmae command over the init-channel and wait for completion */
476int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
f2e0899f
DK		 477{
478 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 479 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 480 int rc = 0;
481
619c5cb6
VZ		 482 /*
483 * Lock the dmae channel. Disable BHs to prevent a dead-lock
484 * as long as this code is called both from syscall context and
485 * from ndo_set_rx_mode() flow that may be called from BH.
486 */
6e30dd4e 487 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 488
f2e0899f 489 /* reset completion */
a2fbb9ea
ET		 490 *wb_comp = 0;
491
f2e0899f
DK		 492 /* post the command on the channel used for initializations */
493 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 494
f2e0899f 495 /* wait for completion */
a2fbb9ea 496 udelay(5);
f2e0899f 497 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 498
95c6c616
AE		 499 if (!cnt ||
500 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
501 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 502 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 503 rc = DMAE_TIMEOUT;
504 goto unlock;
a2fbb9ea 505 }
ad8d3948 506 cnt--;
f2e0899f 507 udelay(50);
a2fbb9ea 508 }
f2e0899f
DK		 509 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
510 BNX2X_ERR("DMAE PCI error!\n");
511 rc = DMAE_PCI_ERROR;
512 }
513
f2e0899f 514unlock:
6e30dd4e 515 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 516 return rc;
517}
518
519void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
520 u32 len32)
521{
522 struct dmae_command dmae;
523
524 if (!bp->dmae_ready) {
525 u32 *data = bnx2x_sp(bp, wb_data[0]);
526
127a425e
AE		 527 if (CHIP_IS_E1(bp))
528 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
529 else
530 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 531 return;
532 }
533
534 /* set opcode and fixed command fields */
535 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
536
537 /* fill in addresses and len */
538 dmae.src_addr_lo = U64_LO(dma_addr);
539 dmae.src_addr_hi = U64_HI(dma_addr);
540 dmae.dst_addr_lo = dst_addr >> 2;
541 dmae.dst_addr_hi = 0;
542 dmae.len = len32;
543
f2e0899f
DK		 544 /* issue the command and wait for completion */
545 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 546}
547
c18487ee 548void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 549{
5ff7b6d4 550 struct dmae_command dmae;
ad8d3948
EG		 551
552 if (!bp->dmae_ready) {
553 u32 *data = bnx2x_sp(bp, wb_data[0]);
554 int i;
555
51c1a580 556 if (CHIP_IS_E1(bp))
127a425e
AE		 557 for (i = 0; i < len32; i++)
558 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 559 else
127a425e
AE		 560 for (i = 0; i < len32; i++)
561 data[i] = REG_RD(bp, src_addr + i*4);
562
ad8d3948
EG		 563 return;
564 }
565
f2e0899f
DK		 566 /* set opcode and fixed command fields */
567 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 568
f2e0899f 569 /* fill in addresses and len */
5ff7b6d4
EG		 570 dmae.src_addr_lo = src_addr >> 2;
571 dmae.src_addr_hi = 0;
572 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
573 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
574 dmae.len = len32;
ad8d3948 575
f2e0899f
DK		 576 /* issue the command and wait for completion */
577 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 578}
579
8d96286a 580static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
581 u32 addr, u32 len)
573f2035 582{
02e3c6cb 583 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 584 int offset = 0;
585
02e3c6cb 586 while (len > dmae_wr_max) {
573f2035 587 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 588 addr + offset, dmae_wr_max);
589 offset += dmae_wr_max * 4;
590 len -= dmae_wr_max;
573f2035
EG		 591 }
592
593 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
594}
595
a2fbb9ea
ET		 596static int bnx2x_mc_assert(struct bnx2x *bp)
597{
a2fbb9ea 598 char last_idx;
34f80b04
EG		 599 int i, rc = 0;
600 u32 row0, row1, row2, row3;
601
602 /* XSTORM */
603 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
604 XSTORM_ASSERT_LIST_INDEX_OFFSET);
605 if (last_idx)
606 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
607
608 /* print the asserts */
609 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
610
611 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i));
613 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
614 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
615 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
616 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
617 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
618 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
619
620 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 621 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 622 i, row3, row2, row1, row0);
623 rc++;
624 } else {
625 break;
626 }
627 }
628
629 /* TSTORM */
630 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
631 TSTORM_ASSERT_LIST_INDEX_OFFSET);
632 if (last_idx)
633 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
634
635 /* print the asserts */
636 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
637
638 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_OFFSET(i));
640 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
641 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
642 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
643 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
644 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
645 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
646
647 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 648 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 649 i, row3, row2, row1, row0);
650 rc++;
651 } else {
652 break;
653 }
654 }
655
656 /* CSTORM */
657 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
658 CSTORM_ASSERT_LIST_INDEX_OFFSET);
659 if (last_idx)
660 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
661
662 /* print the asserts */
663 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
664
665 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i));
667 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
669 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
670 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
671 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
672 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
673
674 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 675 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 676 i, row3, row2, row1, row0);
677 rc++;
678 } else {
679 break;
680 }
681 }
682
683 /* USTORM */
684 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
685 USTORM_ASSERT_LIST_INDEX_OFFSET);
686 if (last_idx)
687 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
688
689 /* print the asserts */
690 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
691
692 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i));
694 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_OFFSET(i) + 4);
696 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
697 USTORM_ASSERT_LIST_OFFSET(i) + 8);
698 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
699 USTORM_ASSERT_LIST_OFFSET(i) + 12);
700
701 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
51c1a580 702 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
34f80b04
EG		 703 i, row3, row2, row1, row0);
704 rc++;
705 } else {
706 break;
a2fbb9ea
ET		 707 }
708 }
34f80b04 709
a2fbb9ea
ET		 710 return rc;
711}
c14423fe 712
7a25cc73 713void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 714{
7a25cc73 715 u32 addr, val;
a2fbb9ea 716 u32 mark, offset;
4781bfad 717 __be32 data[9];
a2fbb9ea 718 int word;
f2e0899f 719 u32 trace_shmem_base;
2145a920
VZ		 720 if (BP_NOMCP(bp)) {
721 BNX2X_ERR("NO MCP - can not dump\n");
722 return;
723 }
7a25cc73
DK		 724 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
725 (bp->common.bc_ver & 0xff0000) >> 16,
726 (bp->common.bc_ver & 0xff00) >> 8,
727 (bp->common.bc_ver & 0xff));
728
729 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
730 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 731 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 732
f2e0899f
DK		 733 if (BP_PATH(bp) == 0)
734 trace_shmem_base = bp->common.shmem_base;
735 else
736 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
de128804
DK		 737 addr = trace_shmem_base - 0x800;
738
739 /* validate TRCB signature */
740 mark = REG_RD(bp, addr);
741 if (mark != MFW_TRACE_SIGNATURE) {
742 BNX2X_ERR("Trace buffer signature is missing.");
743 return ;
744 }
745
746 /* read cyclic buffer pointer */
747 addr += 4;
cdaa7cb8 748 mark = REG_RD(bp, addr);
f2e0899f
DK		 749 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
750 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 751 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 752
7a25cc73 753 printk("%s", lvl);
f2e0899f 754 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 755 for (word = 0; word < 8; word++)
cdaa7cb8 756 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 757 data[8] = 0x0;
7995c64e 758 pr_cont("%s", (char *)data);
a2fbb9ea 759 }
cdaa7cb8 760 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 761 for (word = 0; word < 8; word++)
cdaa7cb8 762 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 763 data[8] = 0x0;
7995c64e 764 pr_cont("%s", (char *)data);
a2fbb9ea 765 }
7a25cc73
DK		 766 printk("%s" "end of fw dump\n", lvl);
767}
768
1191cb83 769static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 770{
771 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 772}
773
6c719d00 774void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 775{
776 int i;
523224a3
DK		 777 u16 j;
778 struct hc_sp_status_block_data sp_sb_data;
779 int func = BP_FUNC(bp);
780#ifdef BNX2X_STOP_ON_ERROR
781 u16 start = 0, end = 0;
6383c0b3 782 u8 cos;
523224a3 783#endif
a2fbb9ea 784
66e855f3 785 bp->stats_state = STATS_STATE_DISABLED;
7a752993 786 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 787 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
788
a2fbb9ea
ET		 789 BNX2X_ERR("begin crash dump -----------------\n");
790
8440d2b6
EG		 791 /* Indices */
792 /* Common */
51c1a580 793 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
619c5cb6
VZ		 794 bp->def_idx, bp->def_att_idx, bp->attn_state,
795 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 796 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
797 bp->def_status_blk->atten_status_block.attn_bits,
798 bp->def_status_blk->atten_status_block.attn_bits_ack,
799 bp->def_status_blk->atten_status_block.status_block_id,
800 bp->def_status_blk->atten_status_block.attn_bits_index);
801 BNX2X_ERR(" def (");
802 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
803 pr_cont("0x%x%s",
f1deab50
JP		 804 bp->def_status_blk->sp_sb.index_values[i],
805 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
523224a3
DK		 806
807 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
808 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
809 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
810 i*sizeof(u32));
811
f1deab50 812 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
523224a3
DK		 813 sp_sb_data.igu_sb_id,
814 sp_sb_data.igu_seg_id,
815 sp_sb_data.p_func.pf_id,
816 sp_sb_data.p_func.vnic_id,
817 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 818 sp_sb_data.p_func.vf_valid,
819 sp_sb_data.state);
523224a3 820
8440d2b6 821
ec6ba945 822 for_each_eth_queue(bp, i) {
a2fbb9ea 823 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 824 int loop;
f2e0899f 825 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 826 struct hc_status_block_data_e1x sb_data_e1x;
827 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 828 CHIP_IS_E1x(bp) ?
829 sb_data_e1x.common.state_machine :
830 sb_data_e2.common.state_machine;
523224a3 831 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 832 CHIP_IS_E1x(bp) ?
833 sb_data_e1x.index_data :
834 sb_data_e2.index_data;
6383c0b3 835 u8 data_size, cos;
523224a3 836 u32 *sb_data_p;
6383c0b3 837 struct bnx2x_fp_txdata txdata;
523224a3
DK		 838
839 /* Rx */
51c1a580 840 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 841 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 842 fp->rx_comp_prod,
66e855f3 843 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 844 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 845 fp->rx_sge_prod, fp->last_max_sge,
523224a3 846 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 847
523224a3 848 /* Tx */
6383c0b3
AE		 849 for_each_cos_in_tx_queue(fp, cos)
850 {
65565884 851 txdata = *fp->txdata_ptr[cos];
51c1a580 852 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 853 i, txdata.tx_pkt_prod,
854 txdata.tx_pkt_cons, txdata.tx_bd_prod,
855 txdata.tx_bd_cons,
856 le16_to_cpu(*txdata.tx_cons_sb));
857 }
523224a3 858
619c5cb6
VZ		 859 loop = CHIP_IS_E1x(bp) ?
860 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 861
862 /* host sb data */
863
ec6ba945
VZ		 864 if (IS_FCOE_FP(fp))
865 continue;
55c11941 866
523224a3
DK		 867 BNX2X_ERR(" run indexes (");
868 for (j = 0; j < HC_SB_MAX_SM; j++)
869 pr_cont("0x%x%s",
870 fp->sb_running_index[j],
871 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
872
873 BNX2X_ERR(" indexes (");
874 for (j = 0; j < loop; j++)
875 pr_cont("0x%x%s",
876 fp->sb_index_values[j],
877 (j == loop - 1) ? ")" : " ");
878 /* fw sb data */
619c5cb6
VZ		 879 data_size = CHIP_IS_E1x(bp) ?
880 sizeof(struct hc_status_block_data_e1x) :
881 sizeof(struct hc_status_block_data_e2);
523224a3 882 data_size /= sizeof(u32);
619c5cb6
VZ		 883 sb_data_p = CHIP_IS_E1x(bp) ?
884 (u32 *)&sb_data_e1x :
885 (u32 *)&sb_data_e2;
523224a3
DK		 886 /* copy sb data in here */
887 for (j = 0; j < data_size; j++)
888 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
889 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
890 j * sizeof(u32));
891
619c5cb6 892 if (!CHIP_IS_E1x(bp)) {
51c1a580 893 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 894 sb_data_e2.common.p_func.pf_id,
895 sb_data_e2.common.p_func.vf_id,
896 sb_data_e2.common.p_func.vf_valid,
897 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 898 sb_data_e2.common.same_igu_sb_1b,
899 sb_data_e2.common.state);
f2e0899f 900 } else {
51c1a580 901 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 902 sb_data_e1x.common.p_func.pf_id,
903 sb_data_e1x.common.p_func.vf_id,
904 sb_data_e1x.common.p_func.vf_valid,
905 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 906 sb_data_e1x.common.same_igu_sb_1b,
907 sb_data_e1x.common.state);
f2e0899f 908 }
523224a3
DK		 909
910 /* SB_SMs data */
911 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 912 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
913 j, hc_sm_p[j].__flags,
914 hc_sm_p[j].igu_sb_id,
915 hc_sm_p[j].igu_seg_id,
916 hc_sm_p[j].time_to_expire,
917 hc_sm_p[j].timer_value);
523224a3
DK		 918 }
919
920 /* Indecies data */
921 for (j = 0; j < loop; j++) {
51c1a580 922 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 923 hc_index_p[j].flags,
924 hc_index_p[j].timeout);
925 }
8440d2b6 926 }
a2fbb9ea 927
523224a3 928#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 929 /* Rings */
930 /* Rx */
55c11941 931 for_each_valid_rx_queue(bp, i) {
8440d2b6 932 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 933
934 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
935 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 936 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 937 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
938 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
939
c3eefaf6 940 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 941 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 942 }
943
3196a88a
EG		 944 start = RX_SGE(fp->rx_sge_prod);
945 end = RX_SGE(fp->last_max_sge);
8440d2b6 946 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 947 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
948 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
949
c3eefaf6
EG		 950 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
951 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 952 }
953
a2fbb9ea
ET		 954 start = RCQ_BD(fp->rx_comp_cons - 10);
955 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 956 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 957 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
958
c3eefaf6
EG		 959 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
960 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 961 }
962 }
963
8440d2b6 964 /* Tx */
55c11941 965 for_each_valid_tx_queue(bp, i) {
8440d2b6 966 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3 967 for_each_cos_in_tx_queue(fp, cos) {
65565884 968 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3
AE		 969
970 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
971 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
972 for (j = start; j != end; j = TX_BD(j + 1)) {
973 struct sw_tx_bd *sw_bd =
974 &txdata->tx_buf_ring[j];
975
51c1a580 976 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 977 i, cos, j, sw_bd->skb,
978 sw_bd->first_bd);
979 }
8440d2b6 980
6383c0b3
AE		 981 start = TX_BD(txdata->tx_bd_cons - 10);
982 end = TX_BD(txdata->tx_bd_cons + 254);
983 for (j = start; j != end; j = TX_BD(j + 1)) {
984 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 985
51c1a580 986 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 987 i, cos, j, tx_bd[0], tx_bd[1],
988 tx_bd[2], tx_bd[3]);
989 }
8440d2b6
EG		 990 }
991 }
523224a3 992#endif
34f80b04 993 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 994 bnx2x_mc_assert(bp);
995 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 996}
997
619c5cb6
VZ		 998/*
999 * FLR Support for E2
1000 *
1001 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1002 * initialization.
1003 */
1004#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
89db4ad8
AE		 1005#define FLR_WAIT_INTERVAL 50 /* usec */
1006#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1007
1008struct pbf_pN_buf_regs {
1009 int pN;
1010 u32 init_crd;
1011 u32 crd;
1012 u32 crd_freed;
1013};
1014
1015struct pbf_pN_cmd_regs {
1016 int pN;
1017 u32 lines_occup;
1018 u32 lines_freed;
1019};
1020
1021static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1022 struct pbf_pN_buf_regs *regs,
1023 u32 poll_count)
1024{
1025 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1026 u32 cur_cnt = poll_count;
1027
1028 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1029 crd = crd_start = REG_RD(bp, regs->crd);
1030 init_crd = REG_RD(bp, regs->init_crd);
1031
1032 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1033 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1034 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1035
1036 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1037 (init_crd - crd_start))) {
1038 if (cur_cnt--) {
89db4ad8 1039 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1040 crd = REG_RD(bp, regs->crd);
1041 crd_freed = REG_RD(bp, regs->crd_freed);
1042 } else {
1043 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1044 regs->pN);
1045 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1046 regs->pN, crd);
1047 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1048 regs->pN, crd_freed);
1049 break;
1050 }
1051 }
1052 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1053 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1054}
1055
1056static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1057 struct pbf_pN_cmd_regs *regs,
1058 u32 poll_count)
1059{
1060 u32 occup, to_free, freed, freed_start;
1061 u32 cur_cnt = poll_count;
1062
1063 occup = to_free = REG_RD(bp, regs->lines_occup);
1064 freed = freed_start = REG_RD(bp, regs->lines_freed);
1065
1066 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1067 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1068
1069 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1070 if (cur_cnt--) {
89db4ad8 1071 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1072 occup = REG_RD(bp, regs->lines_occup);
1073 freed = REG_RD(bp, regs->lines_freed);
1074 } else {
1075 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1076 regs->pN);
1077 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1078 regs->pN, occup);
1079 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1080 regs->pN, freed);
1081 break;
1082 }
1083 }
1084 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1085 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1086}
1087
1191cb83
ED		 1088static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1089 u32 expected, u32 poll_count)
619c5cb6
VZ		 1090{
1091 u32 cur_cnt = poll_count;
1092 u32 val;
1093
1094 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1095 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1096
1097 return val;
1098}
1099
1191cb83
ED		 1100static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1101 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1102{
1103 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1104 if (val != 0) {
1105 BNX2X_ERR("%s usage count=%d\n", msg, val);
1106 return 1;
1107 }
1108 return 0;
1109}
1110
1111static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1112{
1113 /* adjust polling timeout */
1114 if (CHIP_REV_IS_EMUL(bp))
1115 return FLR_POLL_CNT * 2000;
1116
1117 if (CHIP_REV_IS_FPGA(bp))
1118 return FLR_POLL_CNT * 120;
1119
1120 return FLR_POLL_CNT;
1121}
1122
1123static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1124{
1125 struct pbf_pN_cmd_regs cmd_regs[] = {
1126 {0, (CHIP_IS_E3B0(bp)) ?
1127 PBF_REG_TQ_OCCUPANCY_Q0 :
1128 PBF_REG_P0_TQ_OCCUPANCY,
1129 (CHIP_IS_E3B0(bp)) ?
1130 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1131 PBF_REG_P0_TQ_LINES_FREED_CNT},
1132 {1, (CHIP_IS_E3B0(bp)) ?
1133 PBF_REG_TQ_OCCUPANCY_Q1 :
1134 PBF_REG_P1_TQ_OCCUPANCY,
1135 (CHIP_IS_E3B0(bp)) ?
1136 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1137 PBF_REG_P1_TQ_LINES_FREED_CNT},
1138 {4, (CHIP_IS_E3B0(bp)) ?
1139 PBF_REG_TQ_OCCUPANCY_LB_Q :
1140 PBF_REG_P4_TQ_OCCUPANCY,
1141 (CHIP_IS_E3B0(bp)) ?
1142 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1143 PBF_REG_P4_TQ_LINES_FREED_CNT}
1144 };
1145
1146 struct pbf_pN_buf_regs buf_regs[] = {
1147 {0, (CHIP_IS_E3B0(bp)) ?
1148 PBF_REG_INIT_CRD_Q0 :
1149 PBF_REG_P0_INIT_CRD ,
1150 (CHIP_IS_E3B0(bp)) ?
1151 PBF_REG_CREDIT_Q0 :
1152 PBF_REG_P0_CREDIT,
1153 (CHIP_IS_E3B0(bp)) ?
1154 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1155 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1156 {1, (CHIP_IS_E3B0(bp)) ?
1157 PBF_REG_INIT_CRD_Q1 :
1158 PBF_REG_P1_INIT_CRD,
1159 (CHIP_IS_E3B0(bp)) ?
1160 PBF_REG_CREDIT_Q1 :
1161 PBF_REG_P1_CREDIT,
1162 (CHIP_IS_E3B0(bp)) ?
1163 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1164 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1165 {4, (CHIP_IS_E3B0(bp)) ?
1166 PBF_REG_INIT_CRD_LB_Q :
1167 PBF_REG_P4_INIT_CRD,
1168 (CHIP_IS_E3B0(bp)) ?
1169 PBF_REG_CREDIT_LB_Q :
1170 PBF_REG_P4_CREDIT,
1171 (CHIP_IS_E3B0(bp)) ?
1172 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1173 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1174 };
1175
1176 int i;
1177
1178 /* Verify the command queues are flushed P0, P1, P4 */
1179 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1180 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1181
1182
1183 /* Verify the transmission buffers are flushed P0, P1, P4 */
1184 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1185 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1186}
1187
1188#define OP_GEN_PARAM(param) \
1189 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1190
1191#define OP_GEN_TYPE(type) \
1192 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1193
1194#define OP_GEN_AGG_VECT(index) \
1195 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1196
1197
1191cb83 1198static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
619c5cb6
VZ		 1199 u32 poll_cnt)
1200{
1201 struct sdm_op_gen op_gen = {0};
1202
1203 u32 comp_addr = BAR_CSTRORM_INTMEM +
1204 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1205 int ret = 0;
1206
1207 if (REG_RD(bp, comp_addr)) {
89db4ad8 1208 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1209 return 1;
1210 }
1211
1212 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1213 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1214 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1215 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1216
89db4ad8 1217 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
619c5cb6
VZ		 1218 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1219
1220 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1221 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1222 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1223 (REG_RD(bp, comp_addr)));
619c5cb6
VZ		 1224 ret = 1;
1225 }
1226 /* Zero completion for nxt FLR */
1227 REG_WR(bp, comp_addr, 0);
1228
1229 return ret;
1230}
1231
b56e9670 1232u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1233{
619c5cb6
VZ		 1234 u16 status;
1235
2a80eebc 1236 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1237 return status & PCI_EXP_DEVSTA_TRPND;
1238}
1239
1240/* PF FLR specific routines
1241*/
1242static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1243{
1244
1245 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1246 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1247 CFC_REG_NUM_LCIDS_INSIDE_PF,
1248 "CFC PF usage counter timed out",
1249 poll_cnt))
1250 return 1;
1251
1252
1253 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 DORQ_REG_PF_USAGE_CNT,
1256 "DQ PF usage counter timed out",
1257 poll_cnt))
1258 return 1;
1259
1260 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1261 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1262 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1263 "QM PF usage counter timed out",
1264 poll_cnt))
1265 return 1;
1266
1267 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1268 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1269 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1270 "Timers VNIC usage counter timed out",
1271 poll_cnt))
1272 return 1;
1273 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1274 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1275 "Timers NUM_SCANS usage counter timed out",
1276 poll_cnt))
1277 return 1;
1278
1279 /* Wait DMAE PF usage counter to zero */
1280 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1281 dmae_reg_go_c[INIT_DMAE_C(bp)],
1282 "DMAE dommand register timed out",
1283 poll_cnt))
1284 return 1;
1285
1286 return 0;
1287}
1288
1289static void bnx2x_hw_enable_status(struct bnx2x *bp)
1290{
1291 u32 val;
1292
1293 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1294 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1295
1296 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1297 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1298
1299 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1300 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1301
1302 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1303 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1304
1305 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1306 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1307
1308 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1309 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1310
1311 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1312 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1313
1314 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1315 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1316 val);
1317}
1318
1319static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1320{
1321 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1322
1323 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1324
1325 /* Re-enable PF target read access */
1326 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1327
1328 /* Poll HW usage counters */
89db4ad8 1329 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1330 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1331 return -EBUSY;
1332
1333 /* Zero the igu 'trailing edge' and 'leading edge' */
1334
1335 /* Send the FW cleanup command */
1336 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1337 return -EBUSY;
1338
1339 /* ATC cleanup */
1340
1341 /* Verify TX hw is flushed */
1342 bnx2x_tx_hw_flushed(bp, poll_cnt);
1343
1344 /* Wait 100ms (not adjusted according to platform) */
1345 msleep(100);
1346
1347 /* Verify no pending pci transactions */
1348 if (bnx2x_is_pcie_pending(bp->pdev))
1349 BNX2X_ERR("PCIE Transactions still pending\n");
1350
1351 /* Debug */
1352 bnx2x_hw_enable_status(bp);
1353
1354 /*
1355 * Master enable - Due to WB DMAE writes performed before this
1356 * register is re-initialized as part of the regular function init
1357 */
1358 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1359
1360 return 0;
1361}
1362
f2e0899f 1363static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1364{
34f80b04 1365 int port = BP_PORT(bp);
a2fbb9ea
ET		 1366 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1367 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1368 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1369 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1370 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1371
1372 if (msix) {
8badd27a
EG		 1373 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1374 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1375 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1376 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1377 if (single_msix)
1378 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1379 } else if (msi) {
1380 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1381 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1383 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1384 } else {
1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1387 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1388 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1389
a0fd065c 1390 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1391 DP(NETIF_MSG_IFUP,
1392 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1393
a0fd065c 1394 REG_WR(bp, addr, val);
615f8fd9 1395
a0fd065c
DK		 1396 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1397 }
a2fbb9ea
ET		 1398 }
1399
a0fd065c
DK		 1400 if (CHIP_IS_E1(bp))
1401 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1402
51c1a580
MS		 1403 DP(NETIF_MSG_IFUP,
1404 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1405 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1406
1407 REG_WR(bp, addr, val);
37dbbf32
EG		 1408 /*
1409 * Ensure that HC_CONFIG is written before leading/trailing edge config
1410 */
1411 mmiowb();
1412 barrier();
34f80b04 1413
f2e0899f 1414 if (!CHIP_IS_E1(bp)) {
34f80b04 1415 /* init leading/trailing edge */
fb3bff17 1416 if (IS_MF(bp)) {
3395a033 1417 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1418 if (bp->port.pmf)
4acac6a5
EG		 1419 /* enable nig and gpio3 attention */
1420 val |= 0x1100;
34f80b04
EG		 1421 } else
1422 val = 0xffff;
1423
1424 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1425 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1426 }
37dbbf32
EG		 1427
1428 /* Make sure that interrupts are indeed enabled from here on */
1429 mmiowb();
a2fbb9ea
ET		 1430}
1431
f2e0899f
DK		 1432static void bnx2x_igu_int_enable(struct bnx2x *bp)
1433{
1434 u32 val;
30a5de77
DK		 1435 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1436 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1437 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1438
1439 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1440
1441 if (msix) {
1442 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1443 IGU_PF_CONF_SINGLE_ISR_EN);
1444 val |= (IGU_PF_CONF_FUNC_EN |
1445 IGU_PF_CONF_MSI_MSIX_EN |
1446 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1447
1448 if (single_msix)
1449 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1450 } else if (msi) {
1451 val &= ~IGU_PF_CONF_INT_LINE_EN;
1452 val |= (IGU_PF_CONF_FUNC_EN |
1453 IGU_PF_CONF_MSI_MSIX_EN |
1454 IGU_PF_CONF_ATTN_BIT_EN |
1455 IGU_PF_CONF_SINGLE_ISR_EN);
1456 } else {
1457 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1458 val |= (IGU_PF_CONF_FUNC_EN |
1459 IGU_PF_CONF_INT_LINE_EN |
1460 IGU_PF_CONF_ATTN_BIT_EN |
1461 IGU_PF_CONF_SINGLE_ISR_EN);
1462 }
1463
51c1a580 1464 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1465 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1466
1467 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1468
79a8557a
YM		 1469 if (val & IGU_PF_CONF_INT_LINE_EN)
1470 pci_intx(bp->pdev, true);
1471
f2e0899f
DK		 1472 barrier();
1473
1474 /* init leading/trailing edge */
1475 if (IS_MF(bp)) {
3395a033 1476 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1477 if (bp->port.pmf)
1478 /* enable nig and gpio3 attention */
1479 val |= 0x1100;
1480 } else
1481 val = 0xffff;
1482
1483 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1484 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1485
1486 /* Make sure that interrupts are indeed enabled from here on */
1487 mmiowb();
1488}
1489
1490void bnx2x_int_enable(struct bnx2x *bp)
1491{
1492 if (bp->common.int_block == INT_BLOCK_HC)
1493 bnx2x_hc_int_enable(bp);
1494 else
1495 bnx2x_igu_int_enable(bp);
1496}
1497
1498static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1499{
34f80b04 1500 int port = BP_PORT(bp);
a2fbb9ea
ET		 1501 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1502 u32 val = REG_RD(bp, addr);
1503
a0fd065c
DK		 1504 /*
1505 * in E1 we must use only PCI configuration space to disable
1506 * MSI/MSIX capablility
1507 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1508 */
1509 if (CHIP_IS_E1(bp)) {
1510 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1511 * Use mask register to prevent from HC sending interrupts
1512 * after we exit the function
1513 */
1514 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1515
1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1517 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1518 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1519 } else
1520 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1521 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1522 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1523 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea 1524
51c1a580
MS		 1525 DP(NETIF_MSG_IFDOWN,
1526 "write %x to HC %d (addr 0x%x)\n",
a2fbb9ea
ET		 1527 val, port, addr);
1528
8badd27a
EG		 1529 /* flush all outstanding writes */
1530 mmiowb();
1531
a2fbb9ea
ET		 1532 REG_WR(bp, addr, val);
1533 if (REG_RD(bp, addr) != val)
1534 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1535}
1536
f2e0899f
DK		 1537static void bnx2x_igu_int_disable(struct bnx2x *bp)
1538{
1539 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1540
1541 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1542 IGU_PF_CONF_INT_LINE_EN |
1543 IGU_PF_CONF_ATTN_BIT_EN);
1544
51c1a580 1545 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
f2e0899f
DK		 1546
1547 /* flush all outstanding writes */
1548 mmiowb();
1549
1550 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1551 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1552 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1553}
1554
910cc727 1555static void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1556{
1557 if (bp->common.int_block == INT_BLOCK_HC)
1558 bnx2x_hc_int_disable(bp);
1559 else
1560 bnx2x_igu_int_disable(bp);
1561}
1562
9f6c9258 1563void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1564{
a2fbb9ea 1565 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1566 int i, offset;
a2fbb9ea 1567
f8ef6e44
YG		 1568 if (disable_hw)
1569 /* prevent the HW from sending interrupts */
1570 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1571
1572 /* make sure all ISRs are done */
1573 if (msix) {
8badd27a
EG		 1574 synchronize_irq(bp->msix_table[0].vector);
1575 offset = 1;
55c11941
MS		 1576 if (CNIC_SUPPORT(bp))
1577 offset++;
ec6ba945 1578 for_each_eth_queue(bp, i)
754a2f52 1579 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1580 } else
1581 synchronize_irq(bp->pdev->irq);
1582
1583 /* make sure sp_task is not running */
1cf167f2 1584 cancel_delayed_work(&bp->sp_task);
3deb8167 1585 cancel_delayed_work(&bp->period_task);
1cf167f2 1586 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1587}
1588
34f80b04 1589/* fast path */
a2fbb9ea
ET		 1590
1591/*
34f80b04 1592 * General service functions
a2fbb9ea
ET		 1593 */
1594
72fd0718
VZ		 1595/* Return true if succeeded to acquire the lock */
1596static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1597{
1598 u32 lock_status;
1599 u32 resource_bit = (1 << resource);
1600 int func = BP_FUNC(bp);
1601 u32 hw_lock_control_reg;
1602
51c1a580
MS		 1603 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1604 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1605
1606 /* Validating that the resource is within range */
1607 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1608 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1609 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1610 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1611 return false;
72fd0718
VZ		 1612 }
1613
1614 if (func <= 5)
1615 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1616 else
1617 hw_lock_control_reg =
1618 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1619
1620 /* Try to acquire the lock */
1621 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1622 lock_status = REG_RD(bp, hw_lock_control_reg);
1623 if (lock_status & resource_bit)
1624 return true;
1625
51c1a580
MS		 1626 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1627 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1628 return false;
1629}
1630
c9ee9206
VZ		 1631/**
1632 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1633 *
1634 * @bp: driver handle
1635 *
1636 * Returns the recovery leader resource id according to the engine this function
1637 * belongs to. Currently only only 2 engines is supported.
1638 */
1191cb83 1639static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1640{
1641 if (BP_PATH(bp))
1642 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1643 else
1644 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1645}
1646
1647/**
1648 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1649 *
1650 * @bp: driver handle
1651 *
1191cb83 1652 * Tries to aquire a leader lock for current engine.
c9ee9206 1653 */
1191cb83 1654static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1655{
1656 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1657}
1658
619c5cb6 1659static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1660
fd1fc79d
AE		 1661/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1662static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1663{
1664 /* Set the interrupt occurred bit for the sp-task to recognize it
1665 * must ack the interrupt and transition according to the IGU
1666 * state machine.
1667 */
1668 atomic_set(&bp->interrupt_occurred, 1);
1669
1670 /* The sp_task must execute only after this bit
1671 * is set, otherwise we will get out of sync and miss all
1672 * further interrupts. Hence, the barrier.
1673 */
1674 smp_wmb();
1675
1676 /* schedule sp_task to workqueue */
1677 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1678}
3196a88a 1679
619c5cb6 1680void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1681{
1682 struct bnx2x *bp = fp->bp;
1683 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1684 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1685 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1686 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1687
34f80b04 1688 DP(BNX2X_MSG_SP,
a2fbb9ea 1689 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1690 fp->index, cid, command, bp->state,
34f80b04 1691 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1692
fd1fc79d
AE		 1693 /* If cid is within VF range, replace the slowpath object with the
1694 * one corresponding to this VF
1695 */
1696 if (cid >= BNX2X_FIRST_VF_CID &&
1697 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1698 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1699
619c5cb6
VZ		 1700 switch (command) {
1701 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1702 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1703 drv_cmd = BNX2X_Q_CMD_UPDATE;
1704 break;
d6cae238 1705
619c5cb6 1706 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1707 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1708 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1709 break;
1710
6383c0b3 1711 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1712 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1713 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1714 break;
1715
619c5cb6 1716 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1717 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1718 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1719 break;
1720
619c5cb6 1721 case (RAMROD_CMD_ID_ETH_TERMINATE):
d6cae238 1722 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1723 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1724 break;
1725
619c5cb6 1726 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1727 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1728 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1729 break;
619c5cb6
VZ		 1730
1731 default:
1732 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1733 command, fp->index);
1734 return;
523224a3 1735 }
3196a88a 1736
619c5cb6
VZ		 1737 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1738 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1739 /* q_obj->complete_cmd() failure means that this was
1740 * an unexpected completion.
1741 *
1742 * In this case we don't want to increase the bp->spq_left
1743 * because apparently we haven't sent this command the first
1744 * place.
1745 */
1746#ifdef BNX2X_STOP_ON_ERROR
1747 bnx2x_panic();
1748#else
1749 return;
1750#endif
fd1fc79d
AE		 1751 /* SRIOV: reschedule any 'in_progress' operations */
1752 bnx2x_iov_sp_event(bp, cid, true);
619c5cb6 1753
8fe23fbd 1754 smp_mb__before_atomic_inc();
6e30dd4e 1755 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1756 /* push the change in bp->spq_left and towards the memory */
1757 smp_mb__after_atomic_inc();
49d66772 1758
d6cae238
VZ		 1759 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1760
a3348722
BW		 1761 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1762 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1763 /* if Q update ramrod is completed for last Q in AFEX vif set
1764 * flow, then ACK MCP at the end
1765 *
1766 * mark pending ACK to MCP bit.
1767 * prevent case that both bits are cleared.
1768 * At the end of load/unload driver checks that
1769 * sp_state is cleaerd, and this order prevents
1770 * races
1771 */
1772 smp_mb__before_clear_bit();
1773 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1774 wmb();
1775 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1776 smp_mb__after_clear_bit();
1777
fd1fc79d
AE		 1778 /* schedule the sp task as mcp ack is required */
1779 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1780 }
1781
523224a3 1782 return;
a2fbb9ea
ET		 1783}
1784
9f6c9258 1785irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1786{
555f6c78 1787 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1788 u16 status = bnx2x_ack_int(bp);
34f80b04 1789 u16 mask;
ca00392c 1790 int i;
6383c0b3 1791 u8 cos;
a2fbb9ea 1792
34f80b04 1793 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1794 if (unlikely(status == 0)) {
1795 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1796 return IRQ_NONE;
1797 }
f5372251 1798 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1799
3196a88a
EG		 1800#ifdef BNX2X_STOP_ON_ERROR
1801 if (unlikely(bp->panic))
1802 return IRQ_HANDLED;
1803#endif
1804
ec6ba945 1805 for_each_eth_queue(bp, i) {
ca00392c 1806 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1807
55c11941 1808 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1809 if (status & mask) {
619c5cb6 1810 /* Handle Rx or Tx according to SB id */
54b9ddaa 1811 prefetch(fp->rx_cons_sb);
6383c0b3 1812 for_each_cos_in_tx_queue(fp, cos)
65565884 1813 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1814 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1815 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1816 status &= ~mask;
1817 }
a2fbb9ea
ET		 1818 }
1819
55c11941
MS		 1820 if (CNIC_SUPPORT(bp)) {
1821 mask = 0x2;
1822 if (status & (mask | 0x1)) {
1823 struct cnic_ops *c_ops = NULL;
993ac7b5 1824
55c11941
MS		 1825 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1826 rcu_read_lock();
1827 c_ops = rcu_dereference(bp->cnic_ops);
1828 if (c_ops)
1829 c_ops->cnic_handler(bp->cnic_data,
1830 NULL);
1831 rcu_read_unlock();
1832 }
993ac7b5 1833
55c11941
MS		 1834 status &= ~mask;
1835 }
993ac7b5 1836 }
a2fbb9ea 1837
34f80b04 1838 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1839
1840 /* schedule sp task to perform default status block work, ack
1841 * attentions and enable interrupts.
1842 */
1843 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1844
1845 status &= ~0x1;
1846 if (!status)
1847 return IRQ_HANDLED;
1848 }
1849
cdaa7cb8
VZ		 1850 if (unlikely(status))
1851 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1852 status);
a2fbb9ea 1853
c18487ee 1854 return IRQ_HANDLED;
a2fbb9ea
ET		 1855}
1856
c18487ee
YR		 1857/* Link */
1858
1859/*
1860 * General service functions
1861 */
a2fbb9ea 1862
9f6c9258 1863int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1864{
1865 u32 lock_status;
1866 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1867 int func = BP_FUNC(bp);
1868 u32 hw_lock_control_reg;
c18487ee 1869 int cnt;
a2fbb9ea 1870
c18487ee
YR		 1871 /* Validating that the resource is within range */
1872 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1873 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1874 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1875 return -EINVAL;
1876 }
a2fbb9ea 1877
4a37fb66
YG		 1878 if (func <= 5) {
1879 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1880 } else {
1881 hw_lock_control_reg =
1882 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1883 }
1884
c18487ee 1885 /* Validating that the resource is not already taken */
4a37fb66 1886 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1887 if (lock_status & resource_bit) {
51c1a580 1888 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 1889 lock_status, resource_bit);
1890 return -EEXIST;
1891 }
a2fbb9ea 1892
46230476
EG		 1893 /* Try for 5 second every 5ms */
1894 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1895 /* Try to acquire the lock */
4a37fb66
YG		 1896 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1897 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1898 if (lock_status & resource_bit)
1899 return 0;
a2fbb9ea 1900
c18487ee 1901 msleep(5);
a2fbb9ea 1902 }
51c1a580 1903 BNX2X_ERR("Timeout\n");
c18487ee
YR		 1904 return -EAGAIN;
1905}
a2fbb9ea 1906
c9ee9206
VZ		 1907int bnx2x_release_leader_lock(struct bnx2x *bp)
1908{
1909 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1910}
1911
9f6c9258 1912int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1913{
1914 u32 lock_status;
1915 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1916 int func = BP_FUNC(bp);
1917 u32 hw_lock_control_reg;
a2fbb9ea 1918
c18487ee
YR		 1919 /* Validating that the resource is within range */
1920 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1921 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 1922 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1923 return -EINVAL;
1924 }
1925
4a37fb66
YG		 1926 if (func <= 5) {
1927 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1928 } else {
1929 hw_lock_control_reg =
1930 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1931 }
1932
c18487ee 1933 /* Validating that the resource is currently taken */
4a37fb66 1934 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 1935 if (!(lock_status & resource_bit)) {
51c1a580 1936 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
c18487ee
YR		 1937 lock_status, resource_bit);
1938 return -EFAULT;
a2fbb9ea
ET		 1939 }
1940
9f6c9258
DK		 1941 REG_WR(bp, hw_lock_control_reg, resource_bit);
1942 return 0;
c18487ee 1943}
a2fbb9ea 1944
9f6c9258 1945
4acac6a5
EG		 1946int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1947{
1948 /* The GPIO should be swapped if swap register is set and active */
1949 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1950 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1951 int gpio_shift = gpio_num +
1952 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1953 u32 gpio_mask = (1 << gpio_shift);
1954 u32 gpio_reg;
1955 int value;
1956
1957 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1958 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1959 return -EINVAL;
1960 }
1961
1962 /* read GPIO value */
1963 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1964
1965 /* get the requested pin value */
1966 if ((gpio_reg & gpio_mask) == gpio_mask)
1967 value = 1;
1968 else
1969 value = 0;
1970
1971 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1972
1973 return value;
1974}
1975
17de50b7 1976int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1977{
1978 /* The GPIO should be swapped if swap register is set and active */
1979 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1980 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1981 int gpio_shift = gpio_num +
1982 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1983 u32 gpio_mask = (1 << gpio_shift);
1984 u32 gpio_reg;
a2fbb9ea 1985
c18487ee
YR		 1986 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1987 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1988 return -EINVAL;
1989 }
a2fbb9ea 1990
4a37fb66 1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1992 /* read GPIO and mask except the float bits */
1993 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1994
c18487ee
YR		 1995 switch (mode) {
1996 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 1997 DP(NETIF_MSG_LINK,
1998 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 1999 gpio_num, gpio_shift);
2000 /* clear FLOAT and set CLR */
2001 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2002 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2003 break;
a2fbb9ea 2004
c18487ee 2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2006 DP(NETIF_MSG_LINK,
2007 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2008 gpio_num, gpio_shift);
2009 /* clear FLOAT and set SET */
2010 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2011 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2012 break;
a2fbb9ea 2013
17de50b7 2014 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2015 DP(NETIF_MSG_LINK,
2016 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2017 gpio_num, gpio_shift);
2018 /* set FLOAT */
2019 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2020 break;
a2fbb9ea 2021
c18487ee
YR		 2022 default:
2023 break;
a2fbb9ea
ET		 2024 }
2025
c18487ee 2026 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2027 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2028
c18487ee 2029 return 0;
a2fbb9ea
ET		 2030}
2031
0d40f0d4
YR		 2032int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2033{
2034 u32 gpio_reg = 0;
2035 int rc = 0;
2036
2037 /* Any port swapping should be handled by caller. */
2038
2039 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2040 /* read GPIO and mask except the float bits */
2041 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2042 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2043 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2044 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2045
2046 switch (mode) {
2047 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2048 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2049 /* set CLR */
2050 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2051 break;
2052
2053 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2054 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2055 /* set SET */
2056 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2057 break;
2058
2059 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2060 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2061 /* set FLOAT */
2062 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2063 break;
2064
2065 default:
2066 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2067 rc = -EINVAL;
2068 break;
2069 }
2070
2071 if (rc == 0)
2072 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2073
2074 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2075
2076 return rc;
2077}
2078
4acac6a5
EG		 2079int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2080{
2081 /* The GPIO should be swapped if swap register is set and active */
2082 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2083 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2084 int gpio_shift = gpio_num +
2085 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2086 u32 gpio_mask = (1 << gpio_shift);
2087 u32 gpio_reg;
2088
2089 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2090 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2091 return -EINVAL;
2092 }
2093
2094 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2095 /* read GPIO int */
2096 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2097
2098 switch (mode) {
2099 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2100 DP(NETIF_MSG_LINK,
2101 "Clear GPIO INT %d (shift %d) -> output low\n",
2102 gpio_num, gpio_shift);
4acac6a5
EG		 2103 /* clear SET and set CLR */
2104 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2105 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2106 break;
2107
2108 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2109 DP(NETIF_MSG_LINK,
2110 "Set GPIO INT %d (shift %d) -> output high\n",
2111 gpio_num, gpio_shift);
4acac6a5
EG		 2112 /* clear CLR and set SET */
2113 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2114 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2115 break;
2116
2117 default:
2118 break;
2119 }
2120
2121 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2122 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2123
2124 return 0;
2125}
2126
d6d99a3f 2127static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2128{
c18487ee 2129 u32 spio_reg;
a2fbb9ea 2130
d6d99a3f
YM		 2131 /* Only 2 SPIOs are configurable */
2132 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2133 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2134 return -EINVAL;
a2fbb9ea
ET		 2135 }
2136
4a37fb66 2137 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2138 /* read SPIO and mask except the float bits */
d6d99a3f 2139 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2140
c18487ee 2141 switch (mode) {
d6d99a3f
YM		 2142 case MISC_SPIO_OUTPUT_LOW:
2143 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2144 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2145 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2146 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2147 break;
a2fbb9ea 2148
d6d99a3f
YM		 2149 case MISC_SPIO_OUTPUT_HIGH:
2150 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2151 /* clear FLOAT and set SET */
d6d99a3f
YM		 2152 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2153 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2154 break;
a2fbb9ea 2155
d6d99a3f
YM		 2156 case MISC_SPIO_INPUT_HI_Z:
2157 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2158 /* set FLOAT */
d6d99a3f 2159 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2160 break;
a2fbb9ea 2161
c18487ee
YR		 2162 default:
2163 break;
a2fbb9ea
ET		 2164 }
2165
c18487ee 2166 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2167 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2168
a2fbb9ea
ET		 2169 return 0;
2170}
2171
9f6c9258 2172void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2173{
a22f0788 2174 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2175 switch (bp->link_vars.ieee_fc &
2176 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2177 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2178 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2179 ADVERTISED_Pause);
c18487ee 2180 break;
356e2385 2181
c18487ee 2182 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2183 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2184 ADVERTISED_Pause);
c18487ee 2185 break;
356e2385 2186
c18487ee 2187 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2188 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2189 break;
356e2385 2190
c18487ee 2191 default:
a22f0788 2192 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2193 ADVERTISED_Pause);
c18487ee
YR		 2194 break;
2195 }
2196}
f1410647 2197
cd1dfce2 2198static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2199{
cd1dfce2
YM		 2200 /* Initialize link parameters structure variables
2201 * It is recommended to turn off RX FC for jumbo frames
2202 * for better performance
2203 */
2204 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2205 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2206 else
2207 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2208}
a2fbb9ea 2209
cd1dfce2
YM		 2210int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2211{
2212 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2213 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2214
2215 if (!BP_NOMCP(bp)) {
2216 bnx2x_set_requested_fc(bp);
4a37fb66 2217 bnx2x_acquire_phy_lock(bp);
b5bf9068 2218
a22f0788 2219 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2220 struct link_params *lp = &bp->link_params;
2221 lp->loopback_mode = LOOPBACK_XGXS;
2222 /* do PHY loopback at 10G speed, if possible */
2223 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2224 if (lp->speed_cap_mask[cfx_idx] &
2225 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2226 lp->req_line_speed[cfx_idx] =
2227 SPEED_10000;
2228 else
2229 lp->req_line_speed[cfx_idx] =
2230 SPEED_1000;
2231 }
a22f0788 2232 }
b5bf9068 2233
8970b2e4
MS		 2234 if (load_mode == LOAD_LOOPBACK_EXT) {
2235 struct link_params *lp = &bp->link_params;
2236 lp->loopback_mode = LOOPBACK_EXT;
2237 }
2238
19680c48 2239 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2240
4a37fb66 2241 bnx2x_release_phy_lock(bp);
a2fbb9ea 2242
3c96c68b
EG		 2243 bnx2x_calc_fc_adv(bp);
2244
cd1dfce2 2245 if (bp->link_vars.link_up) {
b5bf9068 2246 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2247 bnx2x_link_report(bp);
cd1dfce2
YM		 2248 }
2249 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2250 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2251 return rc;
2252 }
f5372251 2253 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2254 return -EINVAL;
a2fbb9ea
ET		 2255}
2256
9f6c9258 2257void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2258{
19680c48 2259 if (!BP_NOMCP(bp)) {
4a37fb66 2260 bnx2x_acquire_phy_lock(bp);
19680c48 2261 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2262 bnx2x_release_phy_lock(bp);
a2fbb9ea 2263
19680c48
EG		 2264 bnx2x_calc_fc_adv(bp);
2265 } else
f5372251 2266 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2267}
a2fbb9ea 2268
c18487ee
YR		 2269static void bnx2x__link_reset(struct bnx2x *bp)
2270{
19680c48 2271 if (!BP_NOMCP(bp)) {
4a37fb66 2272 bnx2x_acquire_phy_lock(bp);
5d07d868 2273 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2274 bnx2x_release_phy_lock(bp);
19680c48 2275 } else
f5372251 2276 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2277}
a2fbb9ea 2278
5d07d868
YM		 2279void bnx2x_force_link_reset(struct bnx2x *bp)
2280{
2281 bnx2x_acquire_phy_lock(bp);
2282 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2283 bnx2x_release_phy_lock(bp);
2284}
2285
a22f0788 2286u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2287{
2145a920 2288 u8 rc = 0;
a2fbb9ea 2289
2145a920
VZ		 2290 if (!BP_NOMCP(bp)) {
2291 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2292 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2293 is_serdes);
2145a920
VZ		 2294 bnx2x_release_phy_lock(bp);
2295 } else
2296 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2297
c18487ee
YR		 2298 return rc;
2299}
a2fbb9ea 2300
34f80b04 2301
2691d51d
EG		 2302/* Calculates the sum of vn_min_rates.
2303 It's needed for further normalizing of the min_rates.
2304 Returns:
2305 sum of vn_min_rates.
2306 or
2307 0 - if all the min_rates are 0.
2308 In the later case fainess algorithm should be deactivated.
2309 If not all min_rates are zero then those that are zeroes will be set to 1.
2310 */
b475d78f
YM		 2311static void bnx2x_calc_vn_min(struct bnx2x *bp,
2312 struct cmng_init_input *input)
2691d51d
EG		 2313{
2314 int all_zero = 1;
2691d51d
EG		 2315 int vn;
2316
3395a033 2317 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2318 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2319 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2320 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2321
2322 /* Skip hidden vns */
2323 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2324 vn_min_rate = 0;
2691d51d 2325 /* If min rate is zero - set it to 1 */
b475d78f 2326 else if (!vn_min_rate)
2691d51d
EG		 2327 vn_min_rate = DEF_MIN_RATE;
2328 else
2329 all_zero = 0;
2330
b475d78f 2331 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2332 }
2333
30ae438b
DK		 2334 /* if ETS or all min rates are zeros - disable fairness */
2335 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2336 input->flags.cmng_enables &=
30ae438b
DK		 2337 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2338 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2339 } else if (all_zero) {
b475d78f 2340 input->flags.cmng_enables &=
b015e3d1 2341 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2342 DP(NETIF_MSG_IFUP,
2343 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2344 } else
b475d78f 2345 input->flags.cmng_enables |=
b015e3d1 2346 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2347}
2348
b475d78f
YM		 2349static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2350 struct cmng_init_input *input)
34f80b04 2351{
b475d78f 2352 u16 vn_max_rate;
f2e0899f 2353 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2354
b475d78f 2355 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2356 vn_max_rate = 0;
b475d78f 2357 else {
faa6fcbb
DK		 2358 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2359
b475d78f 2360 if (IS_MF_SI(bp)) {
faa6fcbb
DK		 2361 /* maxCfg in percents of linkspeed */
2362 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2363 } else /* SD modes */
faa6fcbb
DK		 2364 /* maxCfg is absolute in 100Mb units */
2365 vn_max_rate = maxCfg * 100;
34f80b04 2366 }
f85582f8 2367
b475d78f 2368 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2369
b475d78f 2370 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2371}
f85582f8 2372
b475d78f 2373
523224a3
DK		 2374static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2375{
2376 if (CHIP_REV_IS_SLOW(bp))
2377 return CMNG_FNS_NONE;
fb3bff17 2378 if (IS_MF(bp))
523224a3
DK		 2379 return CMNG_FNS_MINMAX;
2380
2381 return CMNG_FNS_NONE;
2382}
2383
2ae17f66 2384void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2385{
0793f83f 2386 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2387
2388 if (BP_NOMCP(bp))
2389 return; /* what should be the default bvalue in this case */
2390
0793f83f
DK		 2391 /* For 2 port configuration the absolute function number formula
2392 * is:
2393 * abs_func = 2 * vn + BP_PORT + BP_PATH
2394 *
2395 * and there are 4 functions per port
2396 *
2397 * For 4 port configuration it is
2398 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2399 *
2400 * and there are 2 functions per port
2401 */
3395a033 2402 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2403 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2404
2405 if (func >= E1H_FUNC_MAX)
2406 break;
2407
f2e0899f 2408 bp->mf_config[vn] =
523224a3
DK		 2409 MF_CFG_RD(bp, func_mf_config[func].config);
2410 }
a3348722
BW		 2411 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2412 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2413 bp->flags |= MF_FUNC_DIS;
2414 } else {
2415 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2416 bp->flags &= ~MF_FUNC_DIS;
2417 }
523224a3
DK		 2418}
2419
2420static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2421{
b475d78f
YM		 2422 struct cmng_init_input input;
2423 memset(&input, 0, sizeof(struct cmng_init_input));
2424
2425 input.port_rate = bp->link_vars.line_speed;
523224a3
DK		 2426
2427 if (cmng_type == CMNG_FNS_MINMAX) {
2428 int vn;
2429
523224a3
DK		 2430 /* read mf conf from shmem */
2431 if (read_cfg)
2432 bnx2x_read_mf_cfg(bp);
2433
523224a3 2434 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2435 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2436
2437 /* calculate and set min-max rate for each vn */
c4154f25 2438 if (bp->port.pmf)
3395a033 2439 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2440 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2441
2442 /* always enable rate shaping and fairness */
b475d78f 2443 input.flags.cmng_enables |=
523224a3 2444 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2445
2446 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2447 return;
2448 }
2449
2450 /* rate shaping and fairness are disabled */
2451 DP(NETIF_MSG_IFUP,
2452 "rate shaping and fairness are disabled\n");
2453}
34f80b04 2454
1191cb83
ED		 2455static void storm_memset_cmng(struct bnx2x *bp,
2456 struct cmng_init *cmng,
2457 u8 port)
2458{
2459 int vn;
2460 size_t size = sizeof(struct cmng_struct_per_port);
2461
2462 u32 addr = BAR_XSTRORM_INTMEM +
2463 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2464
2465 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2466
2467 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2468 int func = func_by_vn(bp, vn);
2469
2470 addr = BAR_XSTRORM_INTMEM +
2471 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2472 size = sizeof(struct rate_shaping_vars_per_vn);
2473 __storm_memset_struct(bp, addr, size,
2474 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2475
2476 addr = BAR_XSTRORM_INTMEM +
2477 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2478 size = sizeof(struct fairness_vars_per_vn);
2479 __storm_memset_struct(bp, addr, size,
2480 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2481 }
2482}
2483
c18487ee
YR		 2484/* This function is called upon link interrupt */
2485static void bnx2x_link_attn(struct bnx2x *bp)
2486{
bb2a0f7a
YG		 2487 /* Make sure that we are synced with the current statistics */
2488 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2489
c18487ee 2490 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2491
bb2a0f7a
YG		 2492 if (bp->link_vars.link_up) {
2493
1c06328c 2494 /* dropless flow control */
f2e0899f 2495 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2496 int port = BP_PORT(bp);
2497 u32 pause_enabled = 0;
2498
2499 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2500 pause_enabled = 1;
2501
2502 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2503 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2504 pause_enabled);
2505 }
2506
619c5cb6 2507 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2508 struct host_port_stats *pstats;
2509
2510 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2511 /* reset old mac stats */
bb2a0f7a
YG		 2512 memset(&(pstats->mac_stx[0]), 0,
2513 sizeof(struct mac_stx));
2514 }
f34d28ea 2515 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2516 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2517 }
2518
f2e0899f
DK		 2519 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2520 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2521
f2e0899f
DK		 2522 if (cmng_fns != CMNG_FNS_NONE) {
2523 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2524 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2525 } else
2526 /* rate shaping and fairness are disabled */
2527 DP(NETIF_MSG_IFUP,
2528 "single function mode without fairness\n");
34f80b04 2529 }
9fdc3e95 2530
2ae17f66
VZ		 2531 __bnx2x_link_report(bp);
2532
9fdc3e95
DK		 2533 if (IS_MF(bp))
2534 bnx2x_link_sync_notify(bp);
c18487ee 2535}
a2fbb9ea 2536
9f6c9258 2537void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2538{
2ae17f66 2539 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2540 return;
a2fbb9ea 2541
00253a8c 2542 /* read updated dcb configuration */
ad5afc89
AE		 2543 if (IS_PF(bp)) {
2544 bnx2x_dcbx_pmf_update(bp);
2545 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2546 if (bp->link_vars.link_up)
2547 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2548 else
2549 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2550 /* indicate link status */
2551 bnx2x_link_report(bp);
a2fbb9ea 2552
ad5afc89
AE		 2553 } else { /* VF */
2554 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2555 SUPPORTED_10baseT_Full |
2556 SUPPORTED_100baseT_Half |
2557 SUPPORTED_100baseT_Full |
2558 SUPPORTED_1000baseT_Full |
2559 SUPPORTED_2500baseX_Full |
2560 SUPPORTED_10000baseT_Full |
2561 SUPPORTED_TP |
2562 SUPPORTED_FIBRE |
2563 SUPPORTED_Autoneg |
2564 SUPPORTED_Pause |
2565 SUPPORTED_Asym_Pause);
2566 bp->port.advertising[0] = bp->port.supported[0];
2567
2568 bp->link_params.bp = bp;
2569 bp->link_params.port = BP_PORT(bp);
2570 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2571 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2572 bp->link_params.req_line_speed[0] = SPEED_10000;
2573 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2574 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2575 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2576 bp->link_vars.line_speed = SPEED_10000;
2577 bp->link_vars.link_status =
2578 (LINK_STATUS_LINK_UP |
2579 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2580 bp->link_vars.link_up = 1;
2581 bp->link_vars.duplex = DUPLEX_FULL;
2582 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2583 __bnx2x_link_report(bp);
bb2a0f7a 2584 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2585 }
a2fbb9ea 2586}
a2fbb9ea 2587
a3348722
BW		 2588static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2589 u16 vlan_val, u8 allowed_prio)
2590{
2591 struct bnx2x_func_state_params func_params = {0};
2592 struct bnx2x_func_afex_update_params *f_update_params =
2593 &func_params.params.afex_update;
2594
2595 func_params.f_obj = &bp->func_obj;
2596 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2597
2598 /* no need to wait for RAMROD completion, so don't
2599 * set RAMROD_COMP_WAIT flag
2600 */
2601
2602 f_update_params->vif_id = vifid;
2603 f_update_params->afex_default_vlan = vlan_val;
2604 f_update_params->allowed_priorities = allowed_prio;
2605
2606 /* if ramrod can not be sent, response to MCP immediately */
2607 if (bnx2x_func_state_change(bp, &func_params) < 0)
2608 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2609
2610 return 0;
2611}
2612
2613static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2614 u16 vif_index, u8 func_bit_map)
2615{
2616 struct bnx2x_func_state_params func_params = {0};
2617 struct bnx2x_func_afex_viflists_params *update_params =
2618 &func_params.params.afex_viflists;
2619 int rc;
2620 u32 drv_msg_code;
2621
2622 /* validate only LIST_SET and LIST_GET are received from switch */
2623 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2624 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2625 cmd_type);
2626
2627 func_params.f_obj = &bp->func_obj;
2628 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2629
2630 /* set parameters according to cmd_type */
2631 update_params->afex_vif_list_command = cmd_type;
2632 update_params->vif_list_index = cpu_to_le16(vif_index);
2633 update_params->func_bit_map =
2634 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2635 update_params->func_to_clear = 0;
2636 drv_msg_code =
2637 (cmd_type == VIF_LIST_RULE_GET) ?
2638 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2639 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2640
2641 /* if ramrod can not be sent, respond to MCP immediately for
2642 * SET and GET requests (other are not triggered from MCP)
2643 */
2644 rc = bnx2x_func_state_change(bp, &func_params);
2645 if (rc < 0)
2646 bnx2x_fw_command(bp, drv_msg_code, 0);
2647
2648 return 0;
2649}
2650
2651static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2652{
2653 struct afex_stats afex_stats;
2654 u32 func = BP_ABS_FUNC(bp);
2655 u32 mf_config;
2656 u16 vlan_val;
2657 u32 vlan_prio;
2658 u16 vif_id;
2659 u8 allowed_prio;
2660 u8 vlan_mode;
2661 u32 addr_to_write, vifid, addrs, stats_type, i;
2662
2663 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2664 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2665 DP(BNX2X_MSG_MCP,
2666 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2667 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2668 }
2669
2670 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2671 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2672 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2673 DP(BNX2X_MSG_MCP,
2674 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2675 vifid, addrs);
2676 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2677 addrs);
2678 }
2679
2680 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2681 addr_to_write = SHMEM2_RD(bp,
2682 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2683 stats_type = SHMEM2_RD(bp,
2684 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2685
2686 DP(BNX2X_MSG_MCP,
2687 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2688 addr_to_write);
2689
2690 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2691
2692 /* write response to scratchpad, for MCP */
2693 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2694 REG_WR(bp, addr_to_write + i*sizeof(u32),
2695 *(((u32 *)(&afex_stats))+i));
2696
2697 /* send ack message to MCP */
2698 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2699 }
2700
2701 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2702 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2703 bp->mf_config[BP_VN(bp)] = mf_config;
2704 DP(BNX2X_MSG_MCP,
2705 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2706 mf_config);
2707
2708 /* if VIF_SET is "enabled" */
2709 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2710 /* set rate limit directly to internal RAM */
2711 struct cmng_init_input cmng_input;
2712 struct rate_shaping_vars_per_vn m_rs_vn;
2713 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2714 u32 addr = BAR_XSTRORM_INTMEM +
2715 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2716
2717 bp->mf_config[BP_VN(bp)] = mf_config;
2718
2719 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2720 m_rs_vn.vn_counter.rate =
2721 cmng_input.vnic_max_rate[BP_VN(bp)];
2722 m_rs_vn.vn_counter.quota =
2723 (m_rs_vn.vn_counter.rate *
2724 RS_PERIODIC_TIMEOUT_USEC) / 8;
2725
2726 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2727
2728 /* read relevant values from mf_cfg struct in shmem */
2729 vif_id =
2730 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2731 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2732 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2733 vlan_val =
2734 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2735 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2736 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2737 vlan_prio = (mf_config &
2738 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2739 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2740 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2741 vlan_mode =
2742 (MF_CFG_RD(bp,
2743 func_mf_config[func].afex_config) &
2744 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2745 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2746 allowed_prio =
2747 (MF_CFG_RD(bp,
2748 func_mf_config[func].afex_config) &
2749 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2750 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2751
2752 /* send ramrod to FW, return in case of failure */
2753 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2754 allowed_prio))
2755 return;
2756
2757 bp->afex_def_vlan_tag = vlan_val;
2758 bp->afex_vlan_mode = vlan_mode;
2759 } else {
2760 /* notify link down because BP->flags is disabled */
2761 bnx2x_link_report(bp);
2762
2763 /* send INVALID VIF ramrod to FW */
2764 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2765
2766 /* Reset the default afex VLAN */
2767 bp->afex_def_vlan_tag = -1;
2768 }
2769 }
2770}
2771
34f80b04
EG		 2772static void bnx2x_pmf_update(struct bnx2x *bp)
2773{
2774 int port = BP_PORT(bp);
2775 u32 val;
2776
2777 bp->port.pmf = 1;
51c1a580 2778 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2779
3deb8167
YR		 2780 /*
2781 * We need the mb() to ensure the ordering between the writing to
2782 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2783 */
2784 smp_mb();
2785
2786 /* queue a periodic task */
2787 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2788
ef01854e
DK		 2789 bnx2x_dcbx_pmf_update(bp);
2790
34f80b04 2791 /* enable nig attention */
3395a033 2792 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2793 if (bp->common.int_block == INT_BLOCK_HC) {
2794 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2795 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2796 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2797 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2798 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2799 }
bb2a0f7a
YG		 2800
2801 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2802}
2803
c18487ee 2804/* end of Link */
a2fbb9ea
ET		 2805
2806/* slow path */
2807
2808/*
2809 * General service functions
2810 */
2811
2691d51d 2812/* send the MCP a request, block until there is a reply */
a22f0788 2813u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2814{
f2e0899f 2815 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2816 u32 seq;
2691d51d
EG		 2817 u32 rc = 0;
2818 u32 cnt = 1;
2819 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2820
c4ff7cbf 2821 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2822 seq = ++bp->fw_seq;
f2e0899f
DK		 2823 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2824 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2825
754a2f52
DK		 2826 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2827 (command | seq), param);
2691d51d
EG		 2828
2829 do {
2830 /* let the FW do it's magic ... */
2831 msleep(delay);
2832
f2e0899f 2833 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2834
c4ff7cbf
EG		 2835 /* Give the FW up to 5 second (500*10ms) */
2836 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2837
2838 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2839 cnt*delay, rc, seq);
2840
2841 /* is this a reply to our command? */
2842 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2843 rc &= FW_MSG_CODE_MASK;
2844 else {
2845 /* FW BUG! */
2846 BNX2X_ERR("FW failed to respond!\n");
2847 bnx2x_fw_dump(bp);
2848 rc = 0;
2849 }
c4ff7cbf 2850 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2851
2852 return rc;
2853}
2854
ec6ba945 2855
1191cb83
ED		 2856static void storm_memset_func_cfg(struct bnx2x *bp,
2857 struct tstorm_eth_function_common_config *tcfg,
2858 u16 abs_fid)
2859{
2860 size_t size = sizeof(struct tstorm_eth_function_common_config);
2861
2862 u32 addr = BAR_TSTRORM_INTMEM +
2863 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2864
2865 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2866}
2867
619c5cb6
VZ		 2868void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2869{
2870 if (CHIP_IS_E1x(bp)) {
2871 struct tstorm_eth_function_common_config tcfg = {0};
2872
2873 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2874 }
2875
2876 /* Enable the function in the FW */
2877 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2878 storm_memset_func_en(bp, p->func_id, 1);
2879
2880 /* spq */
2881 if (p->func_flgs & FUNC_FLG_SPQ) {
2882 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2883 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2884 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2885 }
2886}
2887
6383c0b3
AE		 2888/**
2889 * bnx2x_get_tx_only_flags - Return common flags
2890 *
2891 * @bp device handle
2892 * @fp queue handle
2893 * @zero_stats TRUE if statistics zeroing is needed
2894 *
2895 * Return the flags that are common for the Tx-only and not normal connections.
2896 */
1191cb83
ED		 2897static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2898 struct bnx2x_fastpath *fp,
2899 bool zero_stats)
28912902 2900{
619c5cb6
VZ		 2901 unsigned long flags = 0;
2902
2903 /* PF driver will always initialize the Queue to an ACTIVE state */
2904 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2905
6383c0b3
AE		 2906 /* tx only connections collect statistics (on the same index as the
2907 * parent connection). The statistics are zeroed when the parent
2908 * connection is initialized.
2909 */
50f0a562
BW		 2910
2911 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2912 if (zero_stats)
2913 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2914
6383c0b3
AE		 2915
2916 return flags;
2917}
2918
1191cb83
ED		 2919static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2920 struct bnx2x_fastpath *fp,
2921 bool leading)
6383c0b3
AE		 2922{
2923 unsigned long flags = 0;
2924
619c5cb6
VZ		 2925 /* calculate other queue flags */
2926 if (IS_MF_SD(bp))
2927 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2928
a3348722 2929 if (IS_FCOE_FP(fp)) {
619c5cb6 2930 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 2931 /* For FCoE - force usage of default priority (for afex) */
2932 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2933 }
523224a3 2934
f5219d8e 2935 if (!fp->disable_tpa) {
619c5cb6 2936 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 2937 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 2938 if (fp->mode == TPA_MODE_GRO)
2939 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 2940 }
619c5cb6 2941
619c5cb6
VZ		 2942 if (leading) {
2943 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2944 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2945 }
523224a3 2946
619c5cb6
VZ		 2947 /* Always set HW VLAN stripping */
2948 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2949
a3348722
BW		 2950 /* configure silent vlan removal */
2951 if (IS_MF_AFEX(bp))
2952 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2953
6383c0b3
AE		 2954
2955 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2956}
2957
619c5cb6 2958static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2959 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2960 u8 cos)
619c5cb6
VZ		 2961{
2962 gen_init->stat_id = bnx2x_stats_id(fp);
2963 gen_init->spcl_id = fp->cl_id;
2964
2965 /* Always use mini-jumbo MTU for FCoE L2 ring */
2966 if (IS_FCOE_FP(fp))
2967 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2968 else
2969 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2970
2971 gen_init->cos = cos;
619c5cb6
VZ		 2972}
2973
2974static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2975 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2976 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2977{
619c5cb6 2978 u8 max_sge = 0;
523224a3
DK		 2979 u16 sge_sz = 0;
2980 u16 tpa_agg_size = 0;
2981
523224a3 2982 if (!fp->disable_tpa) {
dfacf138
DK		 2983 pause->sge_th_lo = SGE_TH_LO(bp);
2984 pause->sge_th_hi = SGE_TH_HI(bp);
2985
2986 /* validate SGE ring has enough to cross high threshold */
2987 WARN_ON(bp->dropless_fc &&
2988 pause->sge_th_hi + FW_PREFETCH_CNT >
2989 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2990
523224a3
DK		 2991 tpa_agg_size = min_t(u32,
2992 (min_t(u32, 8, MAX_SKB_FRAGS) *
2993 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2994 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2995 SGE_PAGE_SHIFT;
2996 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2997 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2998 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2999 0xffff);
3000 }
3001
3002 /* pause - not for e1 */
3003 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3004 pause->bd_th_lo = BD_TH_LO(bp);
3005 pause->bd_th_hi = BD_TH_HI(bp);
3006
3007 pause->rcq_th_lo = RCQ_TH_LO(bp);
3008 pause->rcq_th_hi = RCQ_TH_HI(bp);
3009 /*
3010 * validate that rings have enough entries to cross
3011 * high thresholds
3012 */
3013 WARN_ON(bp->dropless_fc &&
3014 pause->bd_th_hi + FW_PREFETCH_CNT >
3015 bp->rx_ring_size);
3016 WARN_ON(bp->dropless_fc &&
3017 pause->rcq_th_hi + FW_PREFETCH_CNT >
3018 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3019
523224a3
DK		 3020 pause->pri_map = 1;
3021 }
3022
3023 /* rxq setup */
523224a3
DK		 3024 rxq_init->dscr_map = fp->rx_desc_mapping;
3025 rxq_init->sge_map = fp->rx_sge_mapping;
3026 rxq_init->rcq_map = fp->rx_comp_mapping;
3027 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3028
619c5cb6
VZ		 3029 /* This should be a maximum number of data bytes that may be
3030 * placed on the BD (not including paddings).
3031 */
e52fcb24
ED		 3032 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3033 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3034
523224a3 3035 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3036 rxq_init->tpa_agg_sz = tpa_agg_size;
3037 rxq_init->sge_buf_sz = sge_sz;
3038 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3039 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3040 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3041
3042 /* Maximum number or simultaneous TPA aggregation for this Queue.
3043 *
3044 * For PF Clients it should be the maximum avaliable number.
3045 * VF driver(s) may want to define it to a smaller value.
3046 */
dfacf138 3047 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3048
523224a3
DK		 3049 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3050 rxq_init->fw_sb_id = fp->fw_sb_id;
3051
ec6ba945
VZ		 3052 if (IS_FCOE_FP(fp))
3053 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3054 else
6383c0b3 3055 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3056 /* configure silent vlan removal
3057 * if multi function mode is afex, then mask default vlan
3058 */
3059 if (IS_MF_AFEX(bp)) {
3060 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3061 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3062 }
523224a3
DK		 3063}
3064
619c5cb6 3065static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3066 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3067 u8 cos)
523224a3 3068{
65565884 3069 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3070 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3071 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3072 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3073
619c5cb6
VZ		 3074 /*
3075 * set the tss leading client id for TX classfication ==
3076 * leading RSS client id
3077 */
3078 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3079
ec6ba945
VZ		 3080 if (IS_FCOE_FP(fp)) {
3081 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3082 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3083 }
523224a3
DK		 3084}
3085
8d96286a 3086static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3087{
3088 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 3089 struct event_ring_data eq_data = { {0} };
3090 u16 flags;
3091
619c5cb6 3092 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3093 /* reset IGU PF statistics: MSIX + ATTN */
3094 /* PF */
3095 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3096 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3097 (CHIP_MODE_IS_4_PORT(bp) ?
3098 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3099 /* ATTN */
3100 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3101 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3102 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3103 (CHIP_MODE_IS_4_PORT(bp) ?
3104 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3105 }
3106
523224a3
DK		 3107 /* function setup flags */
3108 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3109
619c5cb6
VZ		 3110 /* This flag is relevant for E1x only.
3111 * E2 doesn't have a TPA configuration in a function level.
523224a3 3112 */
619c5cb6 3113 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 3114
3115 func_init.func_flgs = flags;
3116 func_init.pf_id = BP_FUNC(bp);
3117 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3118 func_init.spq_map = bp->spq_mapping;
3119 func_init.spq_prod = bp->spq_prod_idx;
3120
3121 bnx2x_func_init(bp, &func_init);
3122
3123 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3124
3125 /*
619c5cb6
VZ		 3126 * Congestion management values depend on the link rate
3127 * There is no active link so initial link rate is set to 10 Gbps.
3128 * When the link comes up The congestion management values are
3129 * re-calculated according to the actual link rate.
3130 */
523224a3
DK		 3131 bp->link_vars.line_speed = SPEED_10000;
3132 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3133
3134 /* Only the PMF sets the HW */
3135 if (bp->port.pmf)
3136 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3137
523224a3
DK		 3138 /* init Event Queue */
3139 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3140 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3141 eq_data.producer = bp->eq_prod;
3142 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3143 eq_data.sb_id = DEF_SB_ID;
3144 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3145}
3146
3147
3148static void bnx2x_e1h_disable(struct bnx2x *bp)
3149{
3150 int port = BP_PORT(bp);
3151
619c5cb6 3152 bnx2x_tx_disable(bp);
523224a3
DK		 3153
3154 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3155}
3156
3157static void bnx2x_e1h_enable(struct bnx2x *bp)
3158{
3159 int port = BP_PORT(bp);
3160
3161 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3162
3163 /* Tx queue should be only reenabled */
3164 netif_tx_wake_all_queues(bp->dev);
3165
3166 /*
3167 * Should not call netif_carrier_on since it will be called if the link
3168 * is up when checking for link state
3169 */
3170}
3171
1d187b34
BW		 3172#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3173
3174static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3175{
3176 struct eth_stats_info *ether_stat =
3177 &bp->slowpath->drv_info_to_mcp.ether_stat;
3178
786fdf0b
DC		 3179 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3180 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3181
15192a8c
BW		 3182 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3183 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3184 ether_stat->mac_local);
1d187b34
BW		 3185
3186 ether_stat->mtu_size = bp->dev->mtu;
3187
3188 if (bp->dev->features & NETIF_F_RXCSUM)
3189 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3190 if (bp->dev->features & NETIF_F_TSO)
3191 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3192 ether_stat->feature_flags |= bp->common.boot_mode;
3193
3194 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3195
3196 ether_stat->txq_size = bp->tx_ring_size;
3197 ether_stat->rxq_size = bp->rx_ring_size;
3198}
3199
3200static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3201{
3202 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3203 struct fcoe_stats_info *fcoe_stat =
3204 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3205
55c11941
MS		 3206 if (!CNIC_LOADED(bp))
3207 return;
3208
2e499d3c
BW		 3209 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3210 bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3211
3212 fcoe_stat->qos_priority =
3213 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3214
3215 /* insert FCoE stats from ramrod response */
3216 if (!NO_FCOE(bp)) {
3217 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3218 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3219 tstorm_queue_statistics;
3220
3221 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3222 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3223 xstorm_queue_statistics;
3224
3225 struct fcoe_statistics_params *fw_fcoe_stat =
3226 &bp->fw_stats_data->fcoe;
3227
3228 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3229 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3230
3231 ADD_64(fcoe_stat->rx_bytes_hi,
3232 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3233 fcoe_stat->rx_bytes_lo,
3234 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3235
3236 ADD_64(fcoe_stat->rx_bytes_hi,
3237 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3238 fcoe_stat->rx_bytes_lo,
3239 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3240
3241 ADD_64(fcoe_stat->rx_bytes_hi,
3242 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3243 fcoe_stat->rx_bytes_lo,
3244 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3245
3246 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3247 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3248
3249 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3250 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3251
3252 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3253 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3254
3255 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
f33f1fcc 3256 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34
BW		 3257
3258 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3259 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3260
3261 ADD_64(fcoe_stat->tx_bytes_hi,
3262 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3263 fcoe_stat->tx_bytes_lo,
3264 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3265
3266 ADD_64(fcoe_stat->tx_bytes_hi,
3267 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3268 fcoe_stat->tx_bytes_lo,
3269 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3270
3271 ADD_64(fcoe_stat->tx_bytes_hi,
3272 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3273 fcoe_stat->tx_bytes_lo,
3274 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3275
3276 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3277 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3278
3279 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3280 fcoe_q_xstorm_stats->ucast_pkts_sent);
3281
3282 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3283 fcoe_q_xstorm_stats->bcast_pkts_sent);
3284
3285 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3286 fcoe_q_xstorm_stats->mcast_pkts_sent);
3287 }
3288
1d187b34
BW		 3289 /* ask L5 driver to add data to the struct */
3290 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3291}
3292
3293static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3294{
3295 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3296 struct iscsi_stats_info *iscsi_stat =
3297 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3298
55c11941
MS		 3299 if (!CNIC_LOADED(bp))
3300 return;
3301
2e499d3c
BW		 3302 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3303 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
1d187b34
BW		 3304
3305 iscsi_stat->qos_priority =
3306 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3307
1d187b34
BW		 3308 /* ask L5 driver to add data to the struct */
3309 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3310}
3311
0793f83f
DK		 3312/* called due to MCP event (on pmf):
3313 * reread new bandwidth configuration
3314 * configure FW
3315 * notify others function about the change
3316 */
1191cb83 3317static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3318{
3319 if (bp->link_vars.link_up) {
3320 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3321 bnx2x_link_sync_notify(bp);
3322 }
3323 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3324}
3325
1191cb83 3326static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3327{
3328 bnx2x_config_mf_bw(bp);
3329 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3330}
3331
c8c60d88
YM		 3332static void bnx2x_handle_eee_event(struct bnx2x *bp)
3333{
3334 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3335 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3336}
3337
1d187b34
BW		 3338static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3339{
3340 enum drv_info_opcode op_code;
3341 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3342
3343 /* if drv_info version supported by MFW doesn't match - send NACK */
3344 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3345 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3346 return;
3347 }
3348
3349 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3350 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3351
3352 memset(&bp->slowpath->drv_info_to_mcp, 0,
3353 sizeof(union drv_info_to_mcp));
3354
3355 switch (op_code) {
3356 case ETH_STATS_OPCODE:
3357 bnx2x_drv_info_ether_stat(bp);
3358 break;
3359 case FCOE_STATS_OPCODE:
3360 bnx2x_drv_info_fcoe_stat(bp);
3361 break;
3362 case ISCSI_STATS_OPCODE:
3363 bnx2x_drv_info_iscsi_stat(bp);
3364 break;
3365 default:
3366 /* if op code isn't supported - send NACK */
3367 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3368 return;
3369 }
3370
3371 /* if we got drv_info attn from MFW then these fields are defined in
3372 * shmem2 for sure
3373 */
3374 SHMEM2_WR(bp, drv_info_host_addr_lo,
3375 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3376 SHMEM2_WR(bp, drv_info_host_addr_hi,
3377 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3378
3379 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3380}
3381
523224a3
DK		 3382static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3383{
3384 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3385
3386 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3387
3388 /*
3389 * This is the only place besides the function initialization
3390 * where the bp->flags can change so it is done without any
3391 * locks
3392 */
f2e0899f 3393 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3394 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3395 bp->flags |= MF_FUNC_DIS;
3396
3397 bnx2x_e1h_disable(bp);
3398 } else {
51c1a580 3399 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3400 bp->flags &= ~MF_FUNC_DIS;
3401
3402 bnx2x_e1h_enable(bp);
3403 }
3404 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3405 }
3406 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 3407 bnx2x_config_mf_bw(bp);
523224a3
DK		 3408 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3409 }
3410
3411 /* Report results to MCP */
3412 if (dcc_event)
3413 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3414 else
3415 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3416}
3417
3418/* must be called under the spq lock */
1191cb83 3419static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3420{
3421 struct eth_spe *next_spe = bp->spq_prod_bd;
3422
3423 if (bp->spq_prod_bd == bp->spq_last_bd) {
3424 bp->spq_prod_bd = bp->spq;
3425 bp->spq_prod_idx = 0;
51c1a580 3426 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3427 } else {
3428 bp->spq_prod_bd++;
3429 bp->spq_prod_idx++;
3430 }
3431 return next_spe;
3432}
3433
3434/* must be called under the spq lock */
1191cb83 3435static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3436{
3437 int func = BP_FUNC(bp);
3438
53e51e2f
VZ		 3439 /*
3440 * Make sure that BD data is updated before writing the producer:
3441 * BD data is written to the memory, the producer is read from the
3442 * memory, thus we need a full memory barrier to ensure the ordering.
3443 */
3444 mb();
28912902 3445
523224a3 3446 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3447 bp->spq_prod_idx);
28912902
MC		 3448 mmiowb();
3449}
3450
619c5cb6
VZ		 3451/**
3452 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3453 *
3454 * @cmd: command to check
3455 * @cmd_type: command type
3456 */
1191cb83 3457static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3458{
3459 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3460 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3461 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3462 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3463 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3464 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3465 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3466 return true;
3467 else
3468 return false;
3469
3470}
3471
3472
3473/**
3474 * bnx2x_sp_post - place a single command on an SP ring
3475 *
3476 * @bp: driver handle
3477 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3478 * @cid: SW CID the command is related to
3479 * @data_hi: command private data address (high 32 bits)
3480 * @data_lo: command private data address (low 32 bits)
3481 * @cmd_type: command type (e.g. NONE, ETH)
3482 *
3483 * SP data is handled as if it's always an address pair, thus data fields are
3484 * not swapped to little endian in upper functions. Instead this function swaps
3485 * data as if it's two u32 fields.
3486 */
9f6c9258 3487int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3488 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3489{
28912902 3490 struct eth_spe *spe;
523224a3 3491 u16 type;
619c5cb6 3492 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3493
a2fbb9ea 3494#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3495 if (unlikely(bp->panic)) {
3496 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3497 return -EIO;
51c1a580 3498 }
a2fbb9ea
ET		 3499#endif
3500
34f80b04 3501 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3502
6e30dd4e
VZ		 3503 if (common) {
3504 if (!atomic_read(&bp->eq_spq_left)) {
3505 BNX2X_ERR("BUG! EQ ring full!\n");
3506 spin_unlock_bh(&bp->spq_lock);
3507 bnx2x_panic();
3508 return -EBUSY;
3509 }
3510 } else if (!atomic_read(&bp->cq_spq_left)) {
3511 BNX2X_ERR("BUG! SPQ ring full!\n");
3512 spin_unlock_bh(&bp->spq_lock);
3513 bnx2x_panic();
3514 return -EBUSY;
a2fbb9ea 3515 }
f1410647 3516
28912902
MC		 3517 spe = bnx2x_sp_get_next(bp);
3518
a2fbb9ea 3519 /* CID needs port number to be encoded int it */
28912902 3520 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3521 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3522 HW_CID(bp, cid));
523224a3 3523
619c5cb6 3524 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3525
523224a3
DK		 3526 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3527 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3528
523224a3
DK		 3529 spe->hdr.type = cpu_to_le16(type);
3530
3531 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3532 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3533
d6cae238
VZ		 3534 /*
3535 * It's ok if the actual decrement is issued towards the memory
3536 * somewhere between the spin_lock and spin_unlock. Thus no
3537 * more explict memory barrier is needed.
3538 */
3539 if (common)
3540 atomic_dec(&bp->eq_spq_left);
3541 else
3542 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3543
a2fbb9ea 3544
51c1a580
MS		 3545 DP(BNX2X_MSG_SP,
3546 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3547 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3548 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3549 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3550 HW_CID(bp, cid), data_hi, data_lo, type,
3551 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3552
28912902 3553 bnx2x_sp_prod_update(bp);
34f80b04 3554 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3555 return 0;
3556}
3557
3558/* acquire split MCP access lock register */
4a37fb66 3559static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3560{
72fd0718 3561 u32 j, val;
34f80b04 3562 int rc = 0;
a2fbb9ea
ET		 3563
3564 might_sleep();
72fd0718 3565 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3566 val = (1UL << 31);
3567 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3568 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3569 if (val & (1L << 31))
3570 break;
3571
3572 msleep(5);
3573 }
a2fbb9ea 3574 if (!(val & (1L << 31))) {
19680c48 3575 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3576 rc = -EBUSY;
3577 }
3578
3579 return rc;
3580}
3581
4a37fb66
YG		 3582/* release split MCP access lock register */
3583static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3584{
72fd0718 3585 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3586}
3587
523224a3
DK		 3588#define BNX2X_DEF_SB_ATT_IDX 0x0001
3589#define BNX2X_DEF_SB_IDX 0x0002
3590
1191cb83 3591static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3592{
523224a3 3593 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3594 u16 rc = 0;
3595
3596 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3597 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3598 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3599 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3600 }
523224a3
DK		 3601
3602 if (bp->def_idx != def_sb->sp_sb.running_index) {
3603 bp->def_idx = def_sb->sp_sb.running_index;
3604 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3605 }
523224a3
DK		 3606
3607 /* Do not reorder: indecies reading should complete before handling */
3608 barrier();
a2fbb9ea
ET		 3609 return rc;
3610}
3611
3612/*
3613 * slow path service functions
3614 */
3615
3616static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3617{
34f80b04 3618 int port = BP_PORT(bp);
a2fbb9ea
ET		 3619 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3620 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3621 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3622 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3623 u32 aeu_mask;
87942b46 3624 u32 nig_mask = 0;
f2e0899f 3625 u32 reg_addr;
a2fbb9ea 3626
a2fbb9ea
ET		 3627 if (bp->attn_state & asserted)
3628 BNX2X_ERR("IGU ERROR\n");
3629
3fcaf2e5
EG		 3630 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3631 aeu_mask = REG_RD(bp, aeu_addr);
3632
a2fbb9ea 3633 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3634 aeu_mask, asserted);
72fd0718 3635 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3636 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3637
3fcaf2e5
EG		 3638 REG_WR(bp, aeu_addr, aeu_mask);
3639 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3640
3fcaf2e5 3641 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3642 bp->attn_state |= asserted;
3fcaf2e5 3643 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3644
3645 if (asserted & ATTN_HARD_WIRED_MASK) {
3646 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3647
a5e9a7cf
EG		 3648 bnx2x_acquire_phy_lock(bp);
3649
877e9aa4 3650 /* save nig interrupt mask */
87942b46 3651 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3652
361c391e
YR		 3653 /* If nig_mask is not set, no need to call the update
3654 * function.
3655 */
3656 if (nig_mask) {
3657 REG_WR(bp, nig_int_mask_addr, 0);
3658
3659 bnx2x_link_attn(bp);
3660 }
a2fbb9ea
ET		 3661
3662 /* handle unicore attn? */
3663 }
3664 if (asserted & ATTN_SW_TIMER_4_FUNC)
3665 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3666
3667 if (asserted & GPIO_2_FUNC)
3668 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3669
3670 if (asserted & GPIO_3_FUNC)
3671 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3672
3673 if (asserted & GPIO_4_FUNC)
3674 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3675
3676 if (port == 0) {
3677 if (asserted & ATTN_GENERAL_ATTN_1) {
3678 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3679 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3680 }
3681 if (asserted & ATTN_GENERAL_ATTN_2) {
3682 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3683 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3684 }
3685 if (asserted & ATTN_GENERAL_ATTN_3) {
3686 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3687 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3688 }
3689 } else {
3690 if (asserted & ATTN_GENERAL_ATTN_4) {
3691 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3692 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3693 }
3694 if (asserted & ATTN_GENERAL_ATTN_5) {
3695 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3696 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3697 }
3698 if (asserted & ATTN_GENERAL_ATTN_6) {
3699 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3700 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3701 }
3702 }
3703
3704 } /* if hardwired */
3705
f2e0899f
DK		 3706 if (bp->common.int_block == INT_BLOCK_HC)
3707 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3708 COMMAND_REG_ATTN_BITS_SET);
3709 else
3710 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3711
3712 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3713 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3714 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3715
3716 /* now set back the mask */
a5e9a7cf 3717 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 3718 /* Verify that IGU ack through BAR was written before restoring
3719 * NIG mask. This loop should exit after 2-3 iterations max.
3720 */
3721 if (bp->common.int_block != INT_BLOCK_HC) {
3722 u32 cnt = 0, igu_acked;
3723 do {
3724 igu_acked = REG_RD(bp,
3725 IGU_REG_ATTENTION_ACK_BITS);
3726 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3727 (++cnt < MAX_IGU_ATTN_ACK_TO));
3728 if (!igu_acked)
3729 DP(NETIF_MSG_HW,
3730 "Failed to verify IGU ack on time\n");
3731 barrier();
3732 }
87942b46 3733 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3734 bnx2x_release_phy_lock(bp);
3735 }
a2fbb9ea
ET		 3736}
3737
1191cb83 3738static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 3739{
3740 int port = BP_PORT(bp);
b7737c9b 3741 u32 ext_phy_config;
fd4ef40d 3742 /* mark the failure */
b7737c9b
YR		 3743 ext_phy_config =
3744 SHMEM_RD(bp,
3745 dev_info.port_hw_config[port].external_phy_config);
3746
3747 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3748 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3749 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3750 ext_phy_config);
fd4ef40d
EG		 3751
3752 /* log the failure */
51c1a580
MS		 3753 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3754 "Please contact OEM Support for assistance\n");
8304859a
AE		 3755
3756 /*
3757 * Scheudle device reset (unload)
3758 * This is due to some boards consuming sufficient power when driver is
3759 * up to overheat if fan fails.
3760 */
3761 smp_mb__before_clear_bit();
3762 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3763 smp_mb__after_clear_bit();
3764 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3765
fd4ef40d 3766}
ab6ad5a4 3767
1191cb83 3768static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3769{
34f80b04 3770 int port = BP_PORT(bp);
877e9aa4 3771 int reg_offset;
d90d96ba 3772 u32 val;
877e9aa4 3773
34f80b04
EG		 3774 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3775 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3776
34f80b04 3777 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3778
3779 val = REG_RD(bp, reg_offset);
3780 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3781 REG_WR(bp, reg_offset, val);
3782
3783 BNX2X_ERR("SPIO5 hw attention\n");
3784
fd4ef40d 3785 /* Fan failure attention */
d90d96ba 3786 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3787 bnx2x_fan_failure(bp);
877e9aa4 3788 }
34f80b04 3789
3deb8167 3790 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3791 bnx2x_acquire_phy_lock(bp);
3792 bnx2x_handle_module_detect_int(&bp->link_params);
3793 bnx2x_release_phy_lock(bp);
3794 }
3795
34f80b04
EG		 3796 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3797
3798 val = REG_RD(bp, reg_offset);
3799 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3800 REG_WR(bp, reg_offset, val);
3801
3802 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3803 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3804 bnx2x_panic();
3805 }
877e9aa4
ET		 3806}
3807
1191cb83 3808static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 3809{
3810 u32 val;
3811
0626b899 3812 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3813
3814 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3815 BNX2X_ERR("DB hw attention 0x%x\n", val);
3816 /* DORQ discard attention */
3817 if (val & 0x2)
3818 BNX2X_ERR("FATAL error from DORQ\n");
3819 }
34f80b04
EG		 3820
3821 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3822
3823 int port = BP_PORT(bp);
3824 int reg_offset;
3825
3826 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3827 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3828
3829 val = REG_RD(bp, reg_offset);
3830 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3831 REG_WR(bp, reg_offset, val);
3832
3833 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3834 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3835 bnx2x_panic();
3836 }
877e9aa4
ET		 3837}
3838
1191cb83 3839static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 3840{
3841 u32 val;
3842
3843 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3844
3845 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3846 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3847 /* CFC error attention */
3848 if (val & 0x2)
3849 BNX2X_ERR("FATAL error from CFC\n");
3850 }
3851
3852 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3853 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3854 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3855 /* RQ_USDMDP_FIFO_OVERFLOW */
3856 if (val & 0x18000)
3857 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3858
3859 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3860 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3861 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3862 }
877e9aa4 3863 }
34f80b04
EG		 3864
3865 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3866
3867 int port = BP_PORT(bp);
3868 int reg_offset;
3869
3870 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3871 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3872
3873 val = REG_RD(bp, reg_offset);
3874 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3875 REG_WR(bp, reg_offset, val);
3876
3877 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3878 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3879 bnx2x_panic();
3880 }
877e9aa4
ET		 3881}
3882
1191cb83 3883static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 3884{
34f80b04
EG		 3885 u32 val;
3886
877e9aa4
ET		 3887 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3888
34f80b04
EG		 3889 if (attn & BNX2X_PMF_LINK_ASSERT) {
3890 int func = BP_FUNC(bp);
3891
3892 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 3893 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 3894 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3895 func_mf_config[BP_ABS_FUNC(bp)].config);
3896 val = SHMEM_RD(bp,
3897 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3898 if (val & DRV_STATUS_DCC_EVENT_MASK)
3899 bnx2x_dcc_event(bp,
3900 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3901
3902 if (val & DRV_STATUS_SET_MF_BW)
3903 bnx2x_set_mf_bw(bp);
3904
1d187b34
BW		 3905 if (val & DRV_STATUS_DRV_INFO_REQ)
3906 bnx2x_handle_drv_info_req(bp);
2691d51d 3907 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3908 bnx2x_pmf_update(bp);
3909
e4901dde 3910 if (bp->port.pmf &&
785b9b1a
SR		 3911 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3912 bp->dcbx_enabled > 0)
e4901dde
VZ		 3913 /* start dcbx state machine */
3914 bnx2x_dcbx_set_params(bp,
3915 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 3916 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3917 bnx2x_handle_afex_cmd(bp,
3918 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 3919 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3920 bnx2x_handle_eee_event(bp);
3deb8167
YR		 3921 if (bp->link_vars.periodic_flags &
3922 PERIODIC_FLAGS_LINK_EVENT) {
3923 /* sync with link */
3924 bnx2x_acquire_phy_lock(bp);
3925 bp->link_vars.periodic_flags &=
3926 ~PERIODIC_FLAGS_LINK_EVENT;
3927 bnx2x_release_phy_lock(bp);
3928 if (IS_MF(bp))
3929 bnx2x_link_sync_notify(bp);
3930 bnx2x_link_report(bp);
3931 }
3932 /* Always call it here: bnx2x_link_report() will
3933 * prevent the link indication duplication.
3934 */
3935 bnx2x__link_status_update(bp);
34f80b04 3936 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3937
3938 BNX2X_ERR("MC assert!\n");
d6cae238 3939 bnx2x_mc_assert(bp);
877e9aa4
ET		 3940 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3941 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3942 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3943 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3944 bnx2x_panic();
3945
3946 } else if (attn & BNX2X_MCP_ASSERT) {
3947
3948 BNX2X_ERR("MCP assert!\n");
3949 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3950 bnx2x_fw_dump(bp);
877e9aa4
ET		 3951
3952 } else
3953 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3954 }
3955
3956 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3957 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3958 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3959 val = CHIP_IS_E1(bp) ? 0 :
3960 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3961 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3962 }
3963 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3964 val = CHIP_IS_E1(bp) ? 0 :
3965 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3966 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3967 }
877e9aa4 3968 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3969 }
3970}
3971
c9ee9206
VZ		 3972/*
3973 * Bits map:
3974 * 0-7 - Engine0 load counter.
3975 * 8-15 - Engine1 load counter.
3976 * 16 - Engine0 RESET_IN_PROGRESS bit.
3977 * 17 - Engine1 RESET_IN_PROGRESS bit.
3978 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3979 * on the engine
3980 * 19 - Engine1 ONE_IS_LOADED.
3981 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3982 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3983 * just the one belonging to its engine).
3984 *
3985 */
3986#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3987
3988#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3989#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3990#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3991#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3992#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3993#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3994#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3995
3996/*
3997 * Set the GLOBAL_RESET bit.
3998 *
3999 * Should be run under rtnl lock
4000 */
4001void bnx2x_set_reset_global(struct bnx2x *bp)
4002{
f16da43b
AE		 4003 u32 val;
4004 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4005 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4006 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4007 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4008}
4009
4010/*
4011 * Clear the GLOBAL_RESET bit.
4012 *
4013 * Should be run under rtnl lock
4014 */
1191cb83 4015static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4016{
f16da43b
AE		 4017 u32 val;
4018 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4019 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4020 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4021 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4022}
f85582f8 4023
72fd0718 4024/*
c9ee9206
VZ		 4025 * Checks the GLOBAL_RESET bit.
4026 *
72fd0718
VZ		 4027 * should be run under rtnl lock
4028 */
1191cb83 4029static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206
VZ		 4030{
4031 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4032
4033 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4034 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4035}
4036
4037/*
4038 * Clear RESET_IN_PROGRESS bit for the current engine.
4039 *
4040 * Should be run under rtnl lock
4041 */
1191cb83 4042static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4043{
f16da43b 4044 u32 val;
c9ee9206
VZ		 4045 u32 bit = BP_PATH(bp) ?
4046 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4047 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4048 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4049
4050 /* Clear the bit */
4051 val &= ~bit;
4052 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4053
4054 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4055}
4056
4057/*
c9ee9206
VZ		 4058 * Set RESET_IN_PROGRESS for the current engine.
4059 *
72fd0718
VZ		 4060 * should be run under rtnl lock
4061 */
c9ee9206 4062void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4063{
f16da43b 4064 u32 val;
c9ee9206
VZ		 4065 u32 bit = BP_PATH(bp) ?
4066 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4067 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4068 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4069
4070 /* Set the bit */
4071 val |= bit;
4072 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4073 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4074}
4075
4076/*
c9ee9206 4077 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4078 * should be run under rtnl lock
4079 */
c9ee9206 4080bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4081{
c9ee9206
VZ		 4082 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4083 u32 bit = engine ?
4084 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4085
4086 /* return false if bit is set */
4087 return (val & bit) ? false : true;
72fd0718
VZ		 4088}
4089
4090/*
889b9af3 4091 * set pf load for the current pf.
c9ee9206 4092 *
72fd0718
VZ		 4093 * should be run under rtnl lock
4094 */
889b9af3 4095void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4096{
f16da43b 4097 u32 val1, val;
c9ee9206
VZ		 4098 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4099 BNX2X_PATH0_LOAD_CNT_MASK;
4100 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4101 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4102
f16da43b
AE		 4103 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4104 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4105
51c1a580 4106 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4107
c9ee9206
VZ		 4108 /* get the current counter value */
4109 val1 = (val & mask) >> shift;
4110
889b9af3
AE		 4111 /* set bit of that PF */
4112 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4113
4114 /* clear the old value */
4115 val &= ~mask;
4116
4117 /* set the new one */
4118 val |= ((val1 << shift) & mask);
4119
4120 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4121 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4122}
4123
c9ee9206 4124/**
889b9af3 4125 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4126 *
4127 * @bp: driver handle
4128 *
4129 * Should be run under rtnl lock.
4130 * Decrements the load counter for the current engine. Returns
889b9af3 4131 * whether other functions are still loaded
72fd0718 4132 */
889b9af3 4133bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4134{
f16da43b 4135 u32 val1, val;
c9ee9206
VZ		 4136 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4137 BNX2X_PATH0_LOAD_CNT_MASK;
4138 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4139 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4140
f16da43b
AE		 4141 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4142 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4143 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4144
c9ee9206
VZ		 4145 /* get the current counter value */
4146 val1 = (val & mask) >> shift;
4147
889b9af3
AE		 4148 /* clear bit of that PF */
4149 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4150
4151 /* clear the old value */
4152 val &= ~mask;
4153
4154 /* set the new one */
4155 val |= ((val1 << shift) & mask);
4156
4157 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4158 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4159 return val1 != 0;
72fd0718
VZ		 4160}
4161
4162/*
889b9af3 4163 * Read the load status for the current engine.
c9ee9206 4164 *
72fd0718
VZ		 4165 * should be run under rtnl lock
4166 */
1191cb83 4167static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4168{
c9ee9206
VZ		 4169 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4170 BNX2X_PATH0_LOAD_CNT_MASK);
4171 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4172 BNX2X_PATH0_LOAD_CNT_SHIFT);
4173 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4174
51c1a580 4175 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4176
4177 val = (val & mask) >> shift;
4178
51c1a580
MS		 4179 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4180 engine, val);
c9ee9206 4181
889b9af3 4182 return val != 0;
72fd0718
VZ		 4183}
4184
1191cb83 4185static void _print_next_block(int idx, const char *blk)
72fd0718 4186{
f1deab50 4187 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4188}
4189
1191cb83
ED		 4190static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4191 bool print)
72fd0718
VZ		 4192{
4193 int i = 0;
4194 u32 cur_bit = 0;
4195 for (i = 0; sig; i++) {
4196 cur_bit = ((u32)0x1 << i);
4197 if (sig & cur_bit) {
4198 switch (cur_bit) {
4199 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 4200 if (print)
4201 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 4202 break;
4203 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 4204 if (print)
4205 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 4206 break;
4207 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 4208 if (print)
4209 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 4210 break;
4211 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 4212 if (print)
4213 _print_next_block(par_num++,
4214 "SEARCHER");
4215 break;
4216 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4217 if (print)
4218 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 4219 break;
4220 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 4221 if (print)
4222 _print_next_block(par_num++, "TSEMI");
4223 break;
4224 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4225 if (print)
4226 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 4227 break;
4228 }
4229
4230 /* Clear the bit */
4231 sig &= ~cur_bit;
4232 }
4233 }
4234
4235 return par_num;
4236}
4237
1191cb83
ED		 4238static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4239 bool *global, bool print)
72fd0718
VZ		 4240{
4241 int i = 0;
4242 u32 cur_bit = 0;
4243 for (i = 0; sig; i++) {
4244 cur_bit = ((u32)0x1 << i);
4245 if (sig & cur_bit) {
4246 switch (cur_bit) {
c9ee9206
VZ		 4247 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4248 if (print)
4249 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 4250 break;
4251 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 4252 if (print)
4253 _print_next_block(par_num++, "QM");
4254 break;
4255 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4256 if (print)
4257 _print_next_block(par_num++, "TM");
72fd0718
VZ		 4258 break;
4259 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 4260 if (print)
4261 _print_next_block(par_num++, "XSDM");
4262 break;
4263 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4264 if (print)
4265 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 4266 break;
4267 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 4268 if (print)
4269 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 4270 break;
4271 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 4272 if (print)
4273 _print_next_block(par_num++,
4274 "DOORBELLQ");
4275 break;
4276 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4277 if (print)
4278 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 4279 break;
4280 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 4281 if (print)
4282 _print_next_block(par_num++,
4283 "VAUX PCI CORE");
4284 *global = true;
72fd0718
VZ		 4285 break;
4286 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 4287 if (print)
4288 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 4289 break;
4290 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 4291 if (print)
4292 _print_next_block(par_num++, "USDM");
72fd0718 4293 break;
8736c826
VZ		 4294 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4295 if (print)
4296 _print_next_block(par_num++, "UCM");
4297 break;
72fd0718 4298 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 4299 if (print)
4300 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 4301 break;
4302 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 4303 if (print)
4304 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 4305 break;
4306 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 4307 if (print)
4308 _print_next_block(par_num++, "CSDM");
72fd0718 4309 break;
8736c826
VZ		 4310 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4311 if (print)
4312 _print_next_block(par_num++, "CCM");
4313 break;
72fd0718
VZ		 4314 }
4315
4316 /* Clear the bit */
4317 sig &= ~cur_bit;
4318 }
4319 }
4320
4321 return par_num;
4322}
4323
1191cb83
ED		 4324static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4325 bool print)
72fd0718
VZ		 4326{
4327 int i = 0;
4328 u32 cur_bit = 0;
4329 for (i = 0; sig; i++) {
4330 cur_bit = ((u32)0x1 << i);
4331 if (sig & cur_bit) {
4332 switch (cur_bit) {
4333 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 4334 if (print)
4335 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 4336 break;
4337 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 4338 if (print)
4339 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 4340 break;
4341 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 4342 if (print)
4343 _print_next_block(par_num++,
72fd0718
VZ		 4344 "PXPPCICLOCKCLIENT");
4345 break;
4346 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 4347 if (print)
4348 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 4349 break;
4350 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 4351 if (print)
4352 _print_next_block(par_num++, "CDU");
4353 break;
4354 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4355 if (print)
4356 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 4357 break;
4358 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 4359 if (print)
4360 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 4361 break;
4362 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 4363 if (print)
4364 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 4365 break;
4366 }
4367
4368 /* Clear the bit */
4369 sig &= ~cur_bit;
4370 }
4371 }
4372
4373 return par_num;
4374}
4375
1191cb83
ED		 4376static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4377 bool *global, bool print)
72fd0718
VZ		 4378{
4379 int i = 0;
4380 u32 cur_bit = 0;
4381 for (i = 0; sig; i++) {
4382 cur_bit = ((u32)0x1 << i);
4383 if (sig & cur_bit) {
4384 switch (cur_bit) {
4385 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 4386 if (print)
4387 _print_next_block(par_num++, "MCP ROM");
4388 *global = true;
72fd0718
VZ		 4389 break;
4390 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 4391 if (print)
4392 _print_next_block(par_num++,
4393 "MCP UMP RX");
4394 *global = true;
72fd0718
VZ		 4395 break;
4396 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 4397 if (print)
4398 _print_next_block(par_num++,
4399 "MCP UMP TX");
4400 *global = true;
72fd0718
VZ		 4401 break;
4402 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 4403 if (print)
4404 _print_next_block(par_num++,
4405 "MCP SCPAD");
4406 *global = true;
72fd0718
VZ		 4407 break;
4408 }
4409
4410 /* Clear the bit */
4411 sig &= ~cur_bit;
4412 }
4413 }
4414
4415 return par_num;
4416}
4417
1191cb83
ED		 4418static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4419 bool print)
8736c826
VZ		 4420{
4421 int i = 0;
4422 u32 cur_bit = 0;
4423 for (i = 0; sig; i++) {
4424 cur_bit = ((u32)0x1 << i);
4425 if (sig & cur_bit) {
4426 switch (cur_bit) {
4427 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4428 if (print)
4429 _print_next_block(par_num++, "PGLUE_B");
4430 break;
4431 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4432 if (print)
4433 _print_next_block(par_num++, "ATC");
4434 break;
4435 }
4436
4437 /* Clear the bit */
4438 sig &= ~cur_bit;
4439 }
4440 }
4441
4442 return par_num;
4443}
4444
1191cb83
ED		 4445static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4446 u32 *sig)
72fd0718 4447{
8736c826
VZ		 4448 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4449 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4450 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4451 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4452 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4453 int par_num = 0;
51c1a580
MS		 4454 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4455 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4456 sig[0] & HW_PRTY_ASSERT_SET_0,
4457 sig[1] & HW_PRTY_ASSERT_SET_1,
4458 sig[2] & HW_PRTY_ASSERT_SET_2,
4459 sig[3] & HW_PRTY_ASSERT_SET_3,
4460 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4461 if (print)
4462 netdev_err(bp->dev,
4463 "Parity errors detected in blocks: ");
4464 par_num = bnx2x_check_blocks_with_parity0(
8736c826 4465 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
c9ee9206 4466 par_num = bnx2x_check_blocks_with_parity1(
8736c826 4467 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
c9ee9206 4468 par_num = bnx2x_check_blocks_with_parity2(
8736c826 4469 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
c9ee9206 4470 par_num = bnx2x_check_blocks_with_parity3(
8736c826
VZ		 4471 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4472 par_num = bnx2x_check_blocks_with_parity4(
4473 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4474
c9ee9206
VZ		 4475 if (print)
4476 pr_cont("\n");
8736c826 4477
72fd0718
VZ		 4478 return true;
4479 } else
4480 return false;
4481}
4482
c9ee9206
VZ		 4483/**
4484 * bnx2x_chk_parity_attn - checks for parity attentions.
4485 *
4486 * @bp: driver handle
4487 * @global: true if there was a global attention
4488 * @print: show parity attention in syslog
4489 */
4490bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4491{
8736c826 4492 struct attn_route attn = { {0} };
72fd0718
VZ		 4493 int port = BP_PORT(bp);
4494
4495 attn.sig[0] = REG_RD(bp,
4496 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4497 port*4);
4498 attn.sig[1] = REG_RD(bp,
4499 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4500 port*4);
4501 attn.sig[2] = REG_RD(bp,
4502 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4503 port*4);
4504 attn.sig[3] = REG_RD(bp,
4505 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4506 port*4);
4507
8736c826
VZ		 4508 if (!CHIP_IS_E1x(bp))
4509 attn.sig[4] = REG_RD(bp,
4510 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4511 port*4);
4512
4513 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4514}
4515
f2e0899f 4516
1191cb83 4517static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 4518{
4519 u32 val;
4520 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4521
4522 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4523 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4524 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 4525 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 4526 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 4527 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 4528 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 4529 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 4530 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 4531 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 4532 if (val &
4533 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 4534 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 4535 if (val &
4536 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 4537 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 4538 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 4539 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 4540 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 4541 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 4542 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 4543 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 4544 }
4545 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4546 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4547 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4548 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4549 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4550 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 4551 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 4552 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 4553 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 4554 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 4555 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 4556 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4557 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4558 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 4559 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 4560 }
4561
4562 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4563 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4564 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4565 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4566 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4567 }
4568
4569}
4570
72fd0718
VZ		 4571static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4572{
4573 struct attn_route attn, *group_mask;
34f80b04 4574 int port = BP_PORT(bp);
877e9aa4 4575 int index;
a2fbb9ea
ET		 4576 u32 reg_addr;
4577 u32 val;
3fcaf2e5 4578 u32 aeu_mask;
c9ee9206 4579 bool global = false;
a2fbb9ea
ET		 4580
4581 /* need to take HW lock because MCP or other port might also
4582 try to handle this event */
4a37fb66 4583 bnx2x_acquire_alr(bp);
a2fbb9ea 4584
c9ee9206
VZ		 4585 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4586#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4587 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4588 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4589 /* Disable HW interrupts */
4590 bnx2x_int_disable(bp);
72fd0718
VZ		 4591 /* In case of parity errors don't handle attentions so that
4592 * other function would "see" parity errors.
4593 */
c9ee9206
VZ		 4594#else
4595 bnx2x_panic();
4596#endif
4597 bnx2x_release_alr(bp);
72fd0718
VZ		 4598 return;
4599 }
4600
a2fbb9ea
ET		 4601 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4602 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4603 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4604 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4605 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4606 attn.sig[4] =
4607 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4608 else
4609 attn.sig[4] = 0;
4610
4611 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4612 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4613
4614 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4615 if (deasserted & (1 << index)) {
72fd0718 4616 group_mask = &bp->attn_group[index];
a2fbb9ea 4617
51c1a580 4618 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 4619 index,
4620 group_mask->sig[0], group_mask->sig[1],
4621 group_mask->sig[2], group_mask->sig[3],
4622 group_mask->sig[4]);
a2fbb9ea 4623
f2e0899f
DK		 4624 bnx2x_attn_int_deasserted4(bp,
4625 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4626 bnx2x_attn_int_deasserted3(bp,
72fd0718 4627 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4628 bnx2x_attn_int_deasserted1(bp,
72fd0718 4629 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4630 bnx2x_attn_int_deasserted2(bp,
72fd0718 4631 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4632 bnx2x_attn_int_deasserted0(bp,
72fd0718 4633 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4634 }
4635 }
4636
4a37fb66 4637 bnx2x_release_alr(bp);
a2fbb9ea 4638
f2e0899f
DK		 4639 if (bp->common.int_block == INT_BLOCK_HC)
4640 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4641 COMMAND_REG_ATTN_BITS_CLR);
4642 else
4643 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4644
4645 val = ~deasserted;
f2e0899f
DK		 4646 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4647 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4648 REG_WR(bp, reg_addr, val);
a2fbb9ea 4649
a2fbb9ea 4650 if (~bp->attn_state & deasserted)
3fcaf2e5 4651 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4652
4653 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4654 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4655
3fcaf2e5
EG		 4656 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4657 aeu_mask = REG_RD(bp, reg_addr);
4658
4659 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4660 aeu_mask, deasserted);
72fd0718 4661 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4662 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4663
3fcaf2e5
EG		 4664 REG_WR(bp, reg_addr, aeu_mask);
4665 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4666
4667 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4668 bp->attn_state &= ~deasserted;
4669 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4670}
4671
4672static void bnx2x_attn_int(struct bnx2x *bp)
4673{
4674 /* read local copy of bits */
68d59484
EG		 4675 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4676 attn_bits);
4677 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4678 attn_bits_ack);
a2fbb9ea
ET		 4679 u32 attn_state = bp->attn_state;
4680
4681 /* look for changed bits */
4682 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4683 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4684
4685 DP(NETIF_MSG_HW,
4686 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4687 attn_bits, attn_ack, asserted, deasserted);
4688
4689 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4690 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4691
4692 /* handle bits that were raised */
4693 if (asserted)
4694 bnx2x_attn_int_asserted(bp, asserted);
4695
4696 if (deasserted)
4697 bnx2x_attn_int_deasserted(bp, deasserted);
4698}
4699
619c5cb6
VZ		 4700void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4701 u16 index, u8 op, u8 update)
4702{
dc1ba591
AE		 4703 u32 igu_addr = bp->igu_base_addr;
4704 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 4705 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4706 igu_addr);
4707}
4708
1191cb83 4709static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 4710{
4711 /* No memory barriers */
4712 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4713 mmiowb(); /* keep prod updates ordered */
4714}
4715
523224a3
DK		 4716static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4717 union event_ring_elem *elem)
4718{
619c5cb6
VZ		 4719 u8 err = elem->message.error;
4720
523224a3 4721 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4722 (cid < bp->cnic_eth_dev.starting_cid &&
4723 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4724 return 1;
4725
4726 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4727
619c5cb6
VZ		 4728 if (unlikely(err)) {
4729
523224a3
DK		 4730 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4731 cid);
4732 bnx2x_panic_dump(bp);
4733 }
619c5cb6 4734 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4735 return 0;
4736}
523224a3 4737
1191cb83 4738static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 4739{
4740 struct bnx2x_mcast_ramrod_params rparam;
4741 int rc;
4742
4743 memset(&rparam, 0, sizeof(rparam));
4744
4745 rparam.mcast_obj = &bp->mcast_obj;
4746
4747 netif_addr_lock_bh(bp->dev);
4748
4749 /* Clear pending state for the last command */
4750 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4751
4752 /* If there are pending mcast commands - send them */
4753 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4754 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4755 if (rc < 0)
4756 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4757 rc);
4758 }
4759
4760 netif_addr_unlock_bh(bp->dev);
4761}
4762
1191cb83
ED		 4763static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4764 union event_ring_elem *elem)
619c5cb6
VZ		 4765{
4766 unsigned long ramrod_flags = 0;
4767 int rc = 0;
4768 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4769 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4770
4771 /* Always push next commands out, don't wait here */
4772 __set_bit(RAMROD_CONT, &ramrod_flags);
4773
4774 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4775 case BNX2X_FILTER_MAC_PENDING:
51c1a580 4776 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 4777 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 4778 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4779 else
15192a8c 4780 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6
VZ		 4781
4782 break;
619c5cb6 4783 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 4784 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 4785 /* This is only relevant for 57710 where multicast MACs are
4786 * configured as unicast MACs using the same ramrod.
4787 */
4788 bnx2x_handle_mcast_eqe(bp);
4789 return;
4790 default:
4791 BNX2X_ERR("Unsupported classification command: %d\n",
4792 elem->message.data.eth_event.echo);
4793 return;
4794 }
4795
4796 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4797
4798 if (rc < 0)
4799 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4800 else if (rc > 0)
4801 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4802
4803}
4804
619c5cb6 4805static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 4806
1191cb83 4807static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 4808{
4809 netif_addr_lock_bh(bp->dev);
4810
4811 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4812
4813 /* Send rx_mode command again if was requested */
4814 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4815 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 4816 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4817 &bp->sp_state))
4818 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4819 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4820 &bp->sp_state))
4821 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 4822
4823 netif_addr_unlock_bh(bp->dev);
4824}
4825
1191cb83 4826static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 4827 union event_ring_elem *elem)
4828{
4829 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4830 DP(BNX2X_MSG_SP,
4831 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4832 elem->message.data.vif_list_event.func_bit_map);
4833 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4834 elem->message.data.vif_list_event.func_bit_map);
4835 } else if (elem->message.data.vif_list_event.echo ==
4836 VIF_LIST_RULE_SET) {
4837 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4838 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4839 }
4840}
4841
4842/* called with rtnl_lock */
1191cb83 4843static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 4844{
4845 int q, rc;
4846 struct bnx2x_fastpath *fp;
4847 struct bnx2x_queue_state_params queue_params = {NULL};
4848 struct bnx2x_queue_update_params *q_update_params =
4849 &queue_params.params.update;
4850
4851 /* Send Q update command with afex vlan removal values for all Qs */
4852 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4853
4854 /* set silent vlan removal values according to vlan mode */
4855 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4856 &q_update_params->update_flags);
4857 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4858 &q_update_params->update_flags);
4859 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4860
4861 /* in access mode mark mask and value are 0 to strip all vlans */
4862 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4863 q_update_params->silent_removal_value = 0;
4864 q_update_params->silent_removal_mask = 0;
4865 } else {
4866 q_update_params->silent_removal_value =
4867 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4868 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4869 }
4870
4871 for_each_eth_queue(bp, q) {
4872 /* Set the appropriate Queue object */
4873 fp = &bp->fp[q];
15192a8c 4874 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 4875
4876 /* send the ramrod */
4877 rc = bnx2x_queue_state_change(bp, &queue_params);
4878 if (rc < 0)
4879 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4880 q);
4881 }
4882
a3348722 4883 if (!NO_FCOE(bp)) {
65565884 4884 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 4885 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 4886
4887 /* clear pending completion bit */
4888 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4889
4890 /* mark latest Q bit */
4891 smp_mb__before_clear_bit();
4892 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4893 smp_mb__after_clear_bit();
4894
4895 /* send Q update ramrod for FCoE Q */
4896 rc = bnx2x_queue_state_change(bp, &queue_params);
4897 if (rc < 0)
4898 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4899 q);
4900 } else {
4901 /* If no FCoE ring - ACK MCP now */
4902 bnx2x_link_report(bp);
4903 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4904 }
a3348722
BW		 4905}
4906
1191cb83 4907static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 4908 struct bnx2x *bp, u32 cid)
4909{
94f05b0f 4910 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 4911
4912 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 4913 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 4914 else
15192a8c 4915 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 4916}
4917
523224a3
DK		 4918static void bnx2x_eq_int(struct bnx2x *bp)
4919{
4920 u16 hw_cons, sw_cons, sw_prod;
4921 union event_ring_elem *elem;
55c11941 4922 u8 echo;
523224a3
DK		 4923 u32 cid;
4924 u8 opcode;
fd1fc79d 4925 int rc, spqe_cnt = 0;
619c5cb6
VZ		 4926 struct bnx2x_queue_sp_obj *q_obj;
4927 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4928 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4929
4930 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4931
4932 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4933 * when we get the the next-page we nned to adjust so the loop
4934 * condition below will be met. The next element is the size of a
4935 * regular element and hence incrementing by 1
4936 */
4937 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4938 hw_cons++;
4939
25985edc 4940 /* This function may never run in parallel with itself for a
523224a3
DK		 4941 * specific bp, thus there is no need in "paired" read memory
4942 * barrier here.
4943 */
4944 sw_cons = bp->eq_cons;
4945 sw_prod = bp->eq_prod;
4946
d6cae238 4947 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 4948 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4949
4950 for (; sw_cons != hw_cons;
4951 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4952
4953
4954 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4955
fd1fc79d
AE		 4956 rc = bnx2x_iov_eq_sp_event(bp, elem);
4957 if (!rc) {
4958 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
4959 rc);
4960 goto next_spqe;
4961 }
523224a3
DK		 4962 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4963 opcode = elem->message.opcode;
4964
4965
4966 /* handle eq element */
4967 switch (opcode) {
fd1fc79d
AE		 4968 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
4969 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
4970 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
4971 continue;
4972
523224a3 4973 case EVENT_RING_OPCODE_STAT_QUERY:
51c1a580
MS		 4974 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4975 "got statistics comp event %d\n",
619c5cb6 4976 bp->stats_comp++);
523224a3 4977 /* nothing to do with stats comp */
d6cae238 4978 goto next_spqe;
523224a3
DK		 4979
4980 case EVENT_RING_OPCODE_CFC_DEL:
4981 /* handle according to cid range */
4982 /*
4983 * we may want to verify here that the bp state is
4984 * HALTING
4985 */
d6cae238 4986 DP(BNX2X_MSG_SP,
523224a3 4987 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 4988
4989 if (CNIC_LOADED(bp) &&
4990 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 4991 goto next_spqe;
55c11941 4992
619c5cb6
VZ		 4993 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4994
4995 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4996 break;
4997
4998
523224a3
DK		 4999
5000 goto next_spqe;
e4901dde
VZ		 5001
5002 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5003 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6debea87
DK		 5004 if (f_obj->complete_cmd(bp, f_obj,
5005 BNX2X_F_CMD_TX_STOP))
5006 break;
e4901dde
VZ		 5007 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5008 goto next_spqe;
619c5cb6 5009
e4901dde 5010 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5011 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6debea87
DK		 5012 if (f_obj->complete_cmd(bp, f_obj,
5013 BNX2X_F_CMD_TX_START))
5014 break;
e4901dde
VZ		 5015 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5016 goto next_spqe;
55c11941 5017
a3348722 5018 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5019 echo = elem->message.data.function_update_event.echo;
5020 if (echo == SWITCH_UPDATE) {
5021 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5022 "got FUNC_SWITCH_UPDATE ramrod\n");
5023 if (f_obj->complete_cmd(
5024 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5025 break;
a3348722 5026
55c11941
MS		 5027 } else {
5028 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5029 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5030 f_obj->complete_cmd(bp, f_obj,
5031 BNX2X_F_CMD_AFEX_UPDATE);
5032
5033 /* We will perform the Queues update from
5034 * sp_rtnl task as all Queue SP operations
5035 * should run under rtnl_lock.
5036 */
5037 smp_mb__before_clear_bit();
5038 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5039 &bp->sp_rtnl_state);
5040 smp_mb__after_clear_bit();
5041
5042 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5043 }
a3348722 5044
a3348722
BW		 5045 goto next_spqe;
5046
5047 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5048 f_obj->complete_cmd(bp, f_obj,
5049 BNX2X_F_CMD_AFEX_VIFLISTS);
5050 bnx2x_after_afex_vif_lists(bp, elem);
5051 goto next_spqe;
619c5cb6 5052 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5053 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5054 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5055 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5056 break;
5057
5058 goto next_spqe;
5059
5060 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5061 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5062 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5063 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5064 break;
5065
5066 goto next_spqe;
523224a3
DK		 5067 }
5068
5069 switch (opcode | bp->state) {
619c5cb6
VZ		 5070 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5071 BNX2X_STATE_OPEN):
5072 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5073 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 5074 cid = elem->message.data.eth_event.echo &
5075 BNX2X_SWCID_MASK;
d6cae238 5076 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 5077 cid);
5078 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5079 break;
5080
619c5cb6
VZ		 5081 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5082 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5083 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5084 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5085 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5086 BNX2X_STATE_OPEN):
5087 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5088 BNX2X_STATE_DIAG):
5089 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5090 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5091 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 5092 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5093 break;
5094
619c5cb6
VZ		 5095 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5096 BNX2X_STATE_OPEN):
5097 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5098 BNX2X_STATE_DIAG):
5099 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5100 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5101 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5102 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5103 break;
5104
619c5cb6
VZ		 5105 case (EVENT_RING_OPCODE_FILTERS_RULES |
5106 BNX2X_STATE_OPEN):
5107 case (EVENT_RING_OPCODE_FILTERS_RULES |
5108 BNX2X_STATE_DIAG):
5109 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5110 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5111 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5112 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5113 break;
5114 default:
5115 /* unknown event log error and continue */
619c5cb6
VZ		 5116 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5117 elem->message.opcode, bp->state);
523224a3
DK		 5118 }
5119next_spqe:
5120 spqe_cnt++;
5121 } /* for */
5122
8fe23fbd 5123 smp_mb__before_atomic_inc();
6e30dd4e 5124 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5125
5126 bp->eq_cons = sw_cons;
5127 bp->eq_prod = sw_prod;
5128 /* Make sure that above mem writes were issued towards the memory */
5129 smp_wmb();
5130
5131 /* update producer */
5132 bnx2x_update_eq_prod(bp, bp->eq_prod);
5133}
5134
a2fbb9ea
ET		 5135static void bnx2x_sp_task(struct work_struct *work)
5136{
1cf167f2 5137 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5138
fd1fc79d 5139 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5140
fd1fc79d
AE		 5141 /* make sure the atomic interupt_occurred has been written */
5142 smp_rmb();
5143 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5144
fd1fc79d
AE		 5145 /* what work needs to be performed? */
5146 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5147
fd1fc79d
AE		 5148 DP(BNX2X_MSG_SP, "status %x\n", status);
5149 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5150 atomic_set(&bp->interrupt_occurred, 0);
5151
5152 /* HW attentions */
5153 if (status & BNX2X_DEF_SB_ATT_IDX) {
5154 bnx2x_attn_int(bp);
5155 status &= ~BNX2X_DEF_SB_ATT_IDX;
5156 }
5157
5158 /* SP events: STAT_QUERY and others */
5159 if (status & BNX2X_DEF_SB_IDX) {
5160 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5161
55c11941 5162 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5163 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5164 /* Prevent local bottom-halves from running as
5165 * we are going to change the local NAPI list.
5166 */
5167 local_bh_disable();
5168 napi_schedule(&bnx2x_fcoe(bp, napi));
5169 local_bh_enable();
5170 }
5171
5172 /* Handle EQ completions */
5173 bnx2x_eq_int(bp);
5174 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5175 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5176
5177 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5178 }
55c11941 5179
fd1fc79d
AE		 5180 /* if status is non zero then perhaps something went wrong */
5181 if (unlikely(status))
5182 DP(BNX2X_MSG_SP,
5183 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5184
fd1fc79d
AE		 5185 /* ack status block only if something was actually handled */
5186 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5187 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
523224a3 5188
cdaa7cb8
VZ		 5189 }
5190
fd1fc79d
AE		 5191 /* must be called after the EQ processing (since eq leads to sriov
5192 * ramrod completion flows).
5193 * This flow may have been scheduled by the arrival of a ramrod
5194 * completion, or by the sriov code rescheduling itself.
5195 */
5196 bnx2x_iov_sp_task(bp);
a3348722
BW		 5197
5198 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5199 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5200 &bp->sp_state)) {
5201 bnx2x_link_report(bp);
5202 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5203 }
a2fbb9ea
ET		 5204}
5205
9f6c9258 5206irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5207{
5208 struct net_device *dev = dev_instance;
5209 struct bnx2x *bp = netdev_priv(dev);
5210
523224a3
DK		 5211 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5212 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5213
5214#ifdef BNX2X_STOP_ON_ERROR
5215 if (unlikely(bp->panic))
5216 return IRQ_HANDLED;
5217#endif
5218
55c11941 5219 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5220 struct cnic_ops *c_ops;
5221
5222 rcu_read_lock();
5223 c_ops = rcu_dereference(bp->cnic_ops);
5224 if (c_ops)
5225 c_ops->cnic_handler(bp->cnic_data, NULL);
5226 rcu_read_unlock();
5227 }
55c11941 5228
fd1fc79d
AE		 5229 /* schedule sp task to perform default status block work, ack
5230 * attentions and enable interrupts.
5231 */
5232 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5233
5234 return IRQ_HANDLED;
5235}
5236
5237/* end of slow path */
5238
619c5cb6
VZ		 5239
5240void bnx2x_drv_pulse(struct bnx2x *bp)
5241{
5242 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5243 bp->fw_drv_pulse_wr_seq);
5244}
5245
5246
a2fbb9ea
ET		 5247static void bnx2x_timer(unsigned long data)
5248{
5249 struct bnx2x *bp = (struct bnx2x *) data;
5250
5251 if (!netif_running(bp->dev))
5252 return;
5253
67c431a5
AE		 5254 if (IS_PF(bp) &&
5255 !BP_NOMCP(bp)) {
f2e0899f 5256 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 5257 u32 drv_pulse;
5258 u32 mcp_pulse;
5259
5260 ++bp->fw_drv_pulse_wr_seq;
5261 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5262 /* TBD - add SYSTEM_TIME */
5263 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5264 bnx2x_drv_pulse(bp);
a2fbb9ea 5265
f2e0899f 5266 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5267 MCP_PULSE_SEQ_MASK);
5268 /* The delta between driver pulse and mcp response
5269 * should be 1 (before mcp response) or 0 (after mcp response)
5270 */
5271 if ((drv_pulse != mcp_pulse) &&
5272 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5273 /* someone lost a heartbeat... */
5274 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5275 drv_pulse, mcp_pulse);
5276 }
5277 }
5278
f34d28ea 5279 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5280 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5281
a2fbb9ea
ET		 5282 mod_timer(&bp->timer, jiffies + bp->current_interval);
5283}
5284
5285/* end of Statistics */
5286
5287/* nic init */
5288
5289/*
5290 * nic init service functions
5291 */
5292
1191cb83 5293static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5294{
523224a3
DK		 5295 u32 i;
5296 if (!(len%4) && !(addr%4))
5297 for (i = 0; i < len; i += 4)
5298 REG_WR(bp, addr + i, fill);
5299 else
5300 for (i = 0; i < len; i++)
5301 REG_WR8(bp, addr + i, fill);
34f80b04 5302
34f80b04
EG		 5303}
5304
523224a3 5305/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5306static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5307 int fw_sb_id,
5308 u32 *sb_data_p,
5309 u32 data_size)
34f80b04 5310{
a2fbb9ea 5311 int index;
523224a3
DK		 5312 for (index = 0; index < data_size; index++)
5313 REG_WR(bp, BAR_CSTRORM_INTMEM +
5314 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5315 sizeof(u32)*index,
5316 *(sb_data_p + index));
5317}
a2fbb9ea 5318
1191cb83 5319static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5320{
5321 u32 *sb_data_p;
5322 u32 data_size = 0;
f2e0899f 5323 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5324 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5325
523224a3 5326 /* disable the function first */
619c5cb6 5327 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5328 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5329 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5330 sb_data_e2.common.p_func.vf_valid = false;
5331 sb_data_p = (u32 *)&sb_data_e2;
5332 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5333 } else {
5334 memset(&sb_data_e1x, 0,
5335 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5336 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5337 sb_data_e1x.common.p_func.vf_valid = false;
5338 sb_data_p = (u32 *)&sb_data_e1x;
5339 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5340 }
523224a3 5341 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5342
523224a3
DK		 5343 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5344 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5345 CSTORM_STATUS_BLOCK_SIZE);
5346 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5347 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5348 CSTORM_SYNC_BLOCK_SIZE);
5349}
34f80b04 5350
523224a3 5351/* helper: writes SP SB data to FW */
1191cb83 5352static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5353 struct hc_sp_status_block_data *sp_sb_data)
5354{
5355 int func = BP_FUNC(bp);
5356 int i;
5357 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5358 REG_WR(bp, BAR_CSTRORM_INTMEM +
5359 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5360 i*sizeof(u32),
5361 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5362}
5363
1191cb83 5364static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5365{
5366 int func = BP_FUNC(bp);
523224a3
DK		 5367 struct hc_sp_status_block_data sp_sb_data;
5368 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5369
619c5cb6 5370 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5371 sp_sb_data.p_func.vf_valid = false;
5372
5373 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5374
5375 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5376 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5377 CSTORM_SP_STATUS_BLOCK_SIZE);
5378 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5379 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5380 CSTORM_SP_SYNC_BLOCK_SIZE);
5381
5382}
5383
5384
1191cb83 5385static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5386 int igu_sb_id, int igu_seg_id)
5387{
5388 hc_sm->igu_sb_id = igu_sb_id;
5389 hc_sm->igu_seg_id = igu_seg_id;
5390 hc_sm->timer_value = 0xFF;
5391 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5392}
5393
150966ad
AE		 5394
5395/* allocates state machine ids. */
1191cb83 5396static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5397{
5398 /* zero out state machine indices */
5399 /* rx indices */
5400 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5401
5402 /* tx indices */
5403 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5404 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5405 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5406 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5407
5408 /* map indices */
5409 /* rx indices */
5410 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5411 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5412
5413 /* tx indices */
5414 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5415 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5416 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5417 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5418 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5419 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5420 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5421 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5422}
5423
b93288d5 5424void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5425 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5426{
523224a3
DK		 5427 int igu_seg_id;
5428
f2e0899f 5429 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5430 struct hc_status_block_data_e1x sb_data_e1x;
5431 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5432 int data_size;
5433 u32 *sb_data_p;
5434
f2e0899f
DK		 5435 if (CHIP_INT_MODE_IS_BC(bp))
5436 igu_seg_id = HC_SEG_ACCESS_NORM;
5437 else
5438 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5439
5440 bnx2x_zero_fp_sb(bp, fw_sb_id);
5441
619c5cb6 5442 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5443 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5444 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5445 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5446 sb_data_e2.common.p_func.vf_id = vfid;
5447 sb_data_e2.common.p_func.vf_valid = vf_valid;
5448 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5449 sb_data_e2.common.same_igu_sb_1b = true;
5450 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5451 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5452 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5453 sb_data_p = (u32 *)&sb_data_e2;
5454 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5455 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5456 } else {
5457 memset(&sb_data_e1x, 0,
5458 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5459 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5460 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5461 sb_data_e1x.common.p_func.vf_id = 0xff;
5462 sb_data_e1x.common.p_func.vf_valid = false;
5463 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5464 sb_data_e1x.common.same_igu_sb_1b = true;
5465 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5466 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5467 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5468 sb_data_p = (u32 *)&sb_data_e1x;
5469 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5470 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5471 }
523224a3
DK		 5472
5473 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5474 igu_sb_id, igu_seg_id);
5475 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5476 igu_sb_id, igu_seg_id);
5477
51c1a580 5478 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3
DK		 5479
5480 /* write indecies to HW */
5481 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5482}
5483
619c5cb6 5484static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 5485 u16 tx_usec, u16 rx_usec)
5486{
6383c0b3 5487 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 5488 false, rx_usec);
6383c0b3
AE		 5489 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5490 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5491 tx_usec);
5492 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5493 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5494 tx_usec);
5495 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5496 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5497 tx_usec);
523224a3 5498}
f2e0899f 5499
523224a3
DK		 5500static void bnx2x_init_def_sb(struct bnx2x *bp)
5501{
5502 struct host_sp_status_block *def_sb = bp->def_status_blk;
5503 dma_addr_t mapping = bp->def_status_blk_mapping;
5504 int igu_sp_sb_index;
5505 int igu_seg_id;
34f80b04
EG		 5506 int port = BP_PORT(bp);
5507 int func = BP_FUNC(bp);
f2eaeb58 5508 int reg_offset, reg_offset_en5;
a2fbb9ea 5509 u64 section;
523224a3
DK		 5510 int index;
5511 struct hc_sp_status_block_data sp_sb_data;
5512 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5513
f2e0899f
DK		 5514 if (CHIP_INT_MODE_IS_BC(bp)) {
5515 igu_sp_sb_index = DEF_SB_IGU_ID;
5516 igu_seg_id = HC_SEG_ACCESS_DEF;
5517 } else {
5518 igu_sp_sb_index = bp->igu_dsb_id;
5519 igu_seg_id = IGU_SEG_ACCESS_DEF;
5520 }
a2fbb9ea
ET		 5521
5522 /* ATTN */
523224a3 5523 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 5524 atten_status_block);
523224a3 5525 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 5526
49d66772
ET		 5527 bp->attn_state = 0;
5528
a2fbb9ea
ET		 5529 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5530 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 5531 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5532 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 5533 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 5534 int sindex;
5535 /* take care of sig[0]..sig[4] */
5536 for (sindex = 0; sindex < 4; sindex++)
5537 bp->attn_group[index].sig[sindex] =
5538 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 5539
619c5cb6 5540 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5541 /*
5542 * enable5 is separate from the rest of the registers,
5543 * and therefore the address skip is 4
5544 * and not 16 between the different groups
5545 */
5546 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 5547 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 5548 else
5549 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 5550 }
5551
f2e0899f
DK		 5552 if (bp->common.int_block == INT_BLOCK_HC) {
5553 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5554 HC_REG_ATTN_MSG0_ADDR_L);
5555
5556 REG_WR(bp, reg_offset, U64_LO(section));
5557 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 5558 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5559 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5560 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5561 }
a2fbb9ea 5562
523224a3
DK		 5563 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5564 sp_sb);
a2fbb9ea 5565
523224a3 5566 bnx2x_zero_sp_sb(bp);
a2fbb9ea 5567
619c5cb6 5568 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 5569 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5570 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5571 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5572 sp_sb_data.igu_seg_id = igu_seg_id;
5573 sp_sb_data.p_func.pf_id = func;
f2e0899f 5574 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 5575 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 5576
523224a3 5577 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 5578
523224a3 5579 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 5580}
5581
9f6c9258 5582void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 5583{
a2fbb9ea
ET		 5584 int i;
5585
ec6ba945 5586 for_each_eth_queue(bp, i)
523224a3 5587 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5588 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5589}
5590
a2fbb9ea
ET		 5591static void bnx2x_init_sp_ring(struct bnx2x *bp)
5592{
a2fbb9ea 5593 spin_lock_init(&bp->spq_lock);
6e30dd4e 5594 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5595
a2fbb9ea 5596 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5597 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5598 bp->spq_prod_bd = bp->spq;
5599 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5600}
5601
523224a3 5602static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5603{
5604 int i;
523224a3
DK		 5605 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5606 union event_ring_elem *elem =
5607 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5608
523224a3
DK		 5609 elem->next_page.addr.hi =
5610 cpu_to_le32(U64_HI(bp->eq_mapping +
5611 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5612 elem->next_page.addr.lo =
5613 cpu_to_le32(U64_LO(bp->eq_mapping +
5614 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5615 }
523224a3
DK		 5616 bp->eq_cons = 0;
5617 bp->eq_prod = NUM_EQ_DESC;
5618 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 5619 /* we want a warning message before it gets rought... */
5620 atomic_set(&bp->eq_spq_left,
5621 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5622}
5623
619c5cb6
VZ		 5624
5625/* called with netif_addr_lock_bh() */
5626void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5627 unsigned long rx_mode_flags,
5628 unsigned long rx_accept_flags,
5629 unsigned long tx_accept_flags,
5630 unsigned long ramrod_flags)
ab532cf3 5631{
619c5cb6
VZ		 5632 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5633 int rc;
5634
5635 memset(&ramrod_param, 0, sizeof(ramrod_param));
5636
5637 /* Prepare ramrod parameters */
5638 ramrod_param.cid = 0;
5639 ramrod_param.cl_id = cl_id;
5640 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5641 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5642
619c5cb6
VZ		 5643 ramrod_param.pstate = &bp->sp_state;
5644 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5645
619c5cb6
VZ		 5646 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5647 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5648
5649 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5650
5651 ramrod_param.ramrod_flags = ramrod_flags;
5652 ramrod_param.rx_mode_flags = rx_mode_flags;
5653
5654 ramrod_param.rx_accept_flags = rx_accept_flags;
5655 ramrod_param.tx_accept_flags = tx_accept_flags;
5656
5657 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5658 if (rc < 0) {
5659 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5660 return;
5661 }
a2fbb9ea
ET		 5662}
5663
619c5cb6
VZ		 5664/* called with netif_addr_lock_bh() */
5665void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 5666{
619c5cb6
VZ		 5667 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5668 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 5669
619c5cb6
VZ		 5670 if (!NO_FCOE(bp))
5671
5672 /* Configure rx_mode of FCoE Queue */
5673 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
619c5cb6
VZ		 5674
5675 switch (bp->rx_mode) {
5676 case BNX2X_RX_MODE_NONE:
5677 /*
5678 * 'drop all' supersedes any accept flags that may have been
5679 * passed to the function.
5680 */
5681 break;
5682 case BNX2X_RX_MODE_NORMAL:
5683 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5684 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5685 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5686
5687 /* internal switching mode */
5688 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5689 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5690 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5691
5692 break;
5693 case BNX2X_RX_MODE_ALLMULTI:
5694 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5695 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5696 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5697
5698 /* internal switching mode */
5699 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5700 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5701 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5702
5703 break;
5704 case BNX2X_RX_MODE_PROMISC:
5705 /* According to deffinition of SI mode, iface in promisc mode
5706 * should receive matched and unmatched (in resolution of port)
5707 * unicast packets.
5708 */
5709 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5710 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5711 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5712 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5713
5714 /* internal switching mode */
5715 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5716 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5717
5718 if (IS_MF_SI(bp))
5719 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5720 else
5721 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5722
5723 break;
5724 default:
5725 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5726 return;
5727 }
de832a55 5728
619c5cb6
VZ		 5729 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5730 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5731 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5732 }
5733
619c5cb6
VZ		 5734 __set_bit(RAMROD_RX, &ramrod_flags);
5735 __set_bit(RAMROD_TX, &ramrod_flags);
5736
5737 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5738 tx_accept_flags, ramrod_flags);
5739}
5740
5741static void bnx2x_init_internal_common(struct bnx2x *bp)
5742{
5743 int i;
5744
0793f83f
DK		 5745 if (IS_MF_SI(bp))
5746 /*
5747 * In switch independent mode, the TSTORM needs to accept
5748 * packets that failed classification, since approximate match
5749 * mac addresses aren't written to NIG LLH
5750 */
5751 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5752 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5753 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5754 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5755 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5756
523224a3
DK		 5757 /* Zero this manually as its initialization is
5758 currently missing in the initTool */
5759 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5760 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5761 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5762 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5763 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5764 CHIP_INT_MODE_IS_BC(bp) ?
5765 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5766 }
523224a3 5767}
8a1c38d1 5768
471de716
EG		 5769static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5770{
5771 switch (load_code) {
5772 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5773 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5774 bnx2x_init_internal_common(bp);
5775 /* no break */
5776
5777 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5778 /* nothing to do */
471de716
EG		 5779 /* no break */
5780
5781 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5782 /* internal memory per function is
5783 initialized inside bnx2x_pf_init */
471de716
EG		 5784 break;
5785
5786 default:
5787 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5788 break;
5789 }
5790}
5791
619c5cb6 5792static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5793{
55c11941 5794 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 5795}
523224a3 5796
619c5cb6
VZ		 5797static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5798{
55c11941 5799 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 5800}
5801
1191cb83 5802static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 5803{
5804 if (CHIP_IS_E1x(fp->bp))
5805 return BP_L_ID(fp->bp) + fp->index;
5806 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5807 return bnx2x_fp_igu_sb_id(fp);
5808}
5809
6383c0b3 5810static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5811{
5812 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5813 u8 cos;
619c5cb6 5814 unsigned long q_type = 0;
6383c0b3 5815 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 5816 fp->rx_queue = fp_idx;
b3b83c3f 5817 fp->cid = fp_idx;
619c5cb6
VZ		 5818 fp->cl_id = bnx2x_fp_cl_id(fp);
5819 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5820 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5821 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5822 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5823
523224a3 5824 /* init shortcut */
619c5cb6 5825 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 5826
523224a3
DK		 5827 /* Setup SB indicies */
5828 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5829
619c5cb6
VZ		 5830 /* Configure Queue State object */
5831 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5832 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5833
5834 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5835
5836 /* init tx data */
5837 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 5838 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5839 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5840 FP_COS_TO_TXQ(fp, cos, bp),
5841 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5842 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 5843 }
5844
ad5afc89
AE		 5845 /* nothing more for vf to do here */
5846 if (IS_VF(bp))
5847 return;
5848
5849 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5850 fp->fw_sb_id, fp->igu_sb_id);
5851 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 5852 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5853 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 5854 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5855
5856 /**
5857 * Configure classification DBs: Always enable Tx switching
5858 */
5859 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5860
ad5afc89
AE		 5861 DP(NETIF_MSG_IFUP,
5862 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5863 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5864 fp->igu_sb_id);
523224a3
DK		 5865}
5866
1191cb83
ED		 5867static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5868{
5869 int i;
5870
5871 for (i = 1; i <= NUM_TX_RINGS; i++) {
5872 struct eth_tx_next_bd *tx_next_bd =
5873 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5874
5875 tx_next_bd->addr_hi =
5876 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5877 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5878 tx_next_bd->addr_lo =
5879 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5880 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5881 }
5882
5883 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5884 txdata->tx_db.data.zero_fill1 = 0;
5885 txdata->tx_db.data.prod = 0;
5886
5887 txdata->tx_pkt_prod = 0;
5888 txdata->tx_pkt_cons = 0;
5889 txdata->tx_bd_prod = 0;
5890 txdata->tx_bd_cons = 0;
5891 txdata->tx_pkt = 0;
5892}
5893
55c11941
MS		 5894static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5895{
5896 int i;
5897
5898 for_each_tx_queue_cnic(bp, i)
5899 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5900}
1191cb83
ED		 5901static void bnx2x_init_tx_rings(struct bnx2x *bp)
5902{
5903 int i;
5904 u8 cos;
5905
55c11941 5906 for_each_eth_queue(bp, i)
1191cb83 5907 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 5908 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 5909}
5910
55c11941 5911void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 5912{
ec6ba945
VZ		 5913 if (!NO_FCOE(bp))
5914 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5915
5916 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5917 BNX2X_VF_ID_INVALID, false,
619c5cb6 5918 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5919
55c11941
MS		 5920 /* ensure status block indices were read */
5921 rmb();
5922 bnx2x_init_rx_rings_cnic(bp);
5923 bnx2x_init_tx_rings_cnic(bp);
5924
5925 /* flush all */
5926 mb();
5927 mmiowb();
5928}
a2fbb9ea 5929
55c11941
MS		 5930void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5931{
5932 int i;
5933
5934 for_each_eth_queue(bp, i)
5935 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 5936
5937 /* ensure status block indices were read */
5938 rmb();
5939 bnx2x_init_rx_rings(bp);
5940 bnx2x_init_tx_rings(bp);
5941
5942 if (IS_VF(bp))
5943 return;
5944
020c7e3f
YR		 5945 /* Initialize MOD_ABS interrupts */
5946 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5947 bp->common.shmem_base, bp->common.shmem2_base,
5948 BP_PORT(bp));
16119785 5949
523224a3 5950 bnx2x_init_def_sb(bp);
5c862848 5951 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5952 bnx2x_init_sp_ring(bp);
523224a3 5953 bnx2x_init_eq_ring(bp);
471de716 5954 bnx2x_init_internal(bp, load_code);
523224a3 5955 bnx2x_pf_init(bp);
0ef00459
EG		 5956 bnx2x_stats_init(bp);
5957
0ef00459
EG		 5958 /* flush all before enabling interrupts */
5959 mb();
5960 mmiowb();
5961
615f8fd9 5962 bnx2x_int_enable(bp);
eb8da205
EG		 5963
5964 /* Check for SPIO5 */
5965 bnx2x_attn_int_deasserted0(bp,
5966 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5967 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5968}
5969
5970/* end of nic init */
5971
5972/*
5973 * gzip service functions
5974 */
5975
5976static int bnx2x_gunzip_init(struct bnx2x *bp)
5977{
1a983142
FT		 5978 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5979 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5980 if (bp->gunzip_buf == NULL)
5981 goto gunzip_nomem1;
5982
5983 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5984 if (bp->strm == NULL)
5985 goto gunzip_nomem2;
5986
7ab24bfd 5987 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5988 if (bp->strm->workspace == NULL)
5989 goto gunzip_nomem3;
5990
5991 return 0;
5992
5993gunzip_nomem3:
5994 kfree(bp->strm);
5995 bp->strm = NULL;
5996
5997gunzip_nomem2:
1a983142
FT		 5998 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5999 bp->gunzip_mapping);
a2fbb9ea
ET		 6000 bp->gunzip_buf = NULL;
6001
6002gunzip_nomem1:
51c1a580 6003 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6004 return -ENOMEM;
6005}
6006
6007static void bnx2x_gunzip_end(struct bnx2x *bp)
6008{
b3b83c3f 6009 if (bp->strm) {
7ab24bfd 6010 vfree(bp->strm->workspace);
b3b83c3f
DK		 6011 kfree(bp->strm);
6012 bp->strm = NULL;
6013 }
a2fbb9ea
ET		 6014
6015 if (bp->gunzip_buf) {
1a983142
FT		 6016 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6017 bp->gunzip_mapping);
a2fbb9ea
ET		 6018 bp->gunzip_buf = NULL;
6019 }
6020}
6021
94a78b79 6022static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6023{
6024 int n, rc;
6025
6026 /* check gzip header */
94a78b79
VZ		 6027 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6028 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6029 return -EINVAL;
94a78b79 6030 }
a2fbb9ea
ET		 6031
6032 n = 10;
6033
34f80b04 6034#define FNAME 0x8
a2fbb9ea
ET		 6035
6036 if (zbuf[3] & FNAME)
6037 while ((zbuf[n++] != 0) && (n < len));
6038
94a78b79 6039 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6040 bp->strm->avail_in = len - n;
6041 bp->strm->next_out = bp->gunzip_buf;
6042 bp->strm->avail_out = FW_BUF_SIZE;
6043
6044 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6045 if (rc != Z_OK)
6046 return rc;
6047
6048 rc = zlib_inflate(bp->strm, Z_FINISH);
6049 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6050 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6051 bp->strm->msg);
a2fbb9ea
ET		 6052
6053 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6054 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6055 netdev_err(bp->dev,
6056 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6057 bp->gunzip_outlen);
a2fbb9ea
ET		 6058 bp->gunzip_outlen >>= 2;
6059
6060 zlib_inflateEnd(bp->strm);
6061
6062 if (rc == Z_STREAM_END)
6063 return 0;
6064
6065 return rc;
6066}
6067
6068/* nic load/unload */
6069
6070/*
34f80b04 6071 * General service functions
a2fbb9ea
ET		 6072 */
6073
6074/* send a NIG loopback debug packet */
6075static void bnx2x_lb_pckt(struct bnx2x *bp)
6076{
a2fbb9ea 6077 u32 wb_write[3];
a2fbb9ea
ET		 6078
6079 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6080 wb_write[0] = 0x55555555;
6081 wb_write[1] = 0x55555555;
34f80b04 6082 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6083 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6084
6085 /* NON-IP protocol */
a2fbb9ea
ET		 6086 wb_write[0] = 0x09000000;
6087 wb_write[1] = 0x55555555;
34f80b04 6088 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6089 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6090}
6091
6092/* some of the internal memories
6093 * are not directly readable from the driver
6094 * to test them we send debug packets
6095 */
6096static int bnx2x_int_mem_test(struct bnx2x *bp)
6097{
6098 int factor;
6099 int count, i;
6100 u32 val = 0;
6101
ad8d3948 6102 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6103 factor = 120;
ad8d3948
EG		 6104 else if (CHIP_REV_IS_EMUL(bp))
6105 factor = 200;
6106 else
a2fbb9ea 6107 factor = 1;
a2fbb9ea 6108
a2fbb9ea
ET		 6109 /* Disable inputs of parser neighbor blocks */
6110 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6111 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6112 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6113 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6114
6115 /* Write 0 to parser credits for CFC search request */
6116 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6117
6118 /* send Ethernet packet */
6119 bnx2x_lb_pckt(bp);
6120
6121 /* TODO do i reset NIG statistic? */
6122 /* Wait until NIG register shows 1 packet of size 0x10 */
6123 count = 1000 * factor;
6124 while (count) {
34f80b04 6125
a2fbb9ea
ET		 6126 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6127 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6128 if (val == 0x10)
6129 break;
6130
6131 msleep(10);
6132 count--;
6133 }
6134 if (val != 0x10) {
6135 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6136 return -1;
6137 }
6138
6139 /* Wait until PRS register shows 1 packet */
6140 count = 1000 * factor;
6141 while (count) {
6142 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6143 if (val == 1)
6144 break;
6145
6146 msleep(10);
6147 count--;
6148 }
6149 if (val != 0x1) {
6150 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6151 return -2;
6152 }
6153
6154 /* Reset and init BRB, PRS */
34f80b04 6155 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6156 msleep(50);
34f80b04 6157 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6158 msleep(50);
619c5cb6
VZ		 6159 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6160 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6161
6162 DP(NETIF_MSG_HW, "part2\n");
6163
6164 /* Disable inputs of parser neighbor blocks */
6165 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6166 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6167 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6168 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6169
6170 /* Write 0 to parser credits for CFC search request */
6171 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6172
6173 /* send 10 Ethernet packets */
6174 for (i = 0; i < 10; i++)
6175 bnx2x_lb_pckt(bp);
6176
6177 /* Wait until NIG register shows 10 + 1
6178 packets of size 11*0x10 = 0xb0 */
6179 count = 1000 * factor;
6180 while (count) {
34f80b04 6181
a2fbb9ea
ET		 6182 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6183 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6184 if (val == 0xb0)
6185 break;
6186
6187 msleep(10);
6188 count--;
6189 }
6190 if (val != 0xb0) {
6191 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6192 return -3;
6193 }
6194
6195 /* Wait until PRS register shows 2 packets */
6196 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6197 if (val != 2)
6198 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6199
6200 /* Write 1 to parser credits for CFC search request */
6201 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6202
6203 /* Wait until PRS register shows 3 packets */
6204 msleep(10 * factor);
6205 /* Wait until NIG register shows 1 packet of size 0x10 */
6206 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6207 if (val != 3)
6208 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6209
6210 /* clear NIG EOP FIFO */
6211 for (i = 0; i < 11; i++)
6212 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6213 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6214 if (val != 1) {
6215 BNX2X_ERR("clear of NIG failed\n");
6216 return -4;
6217 }
6218
6219 /* Reset and init BRB, PRS, NIG */
6220 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6221 msleep(50);
6222 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6223 msleep(50);
619c5cb6
VZ		 6224 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6225 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6226 if (!CNIC_SUPPORT(bp))
6227 /* set NIC mode */
6228 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6229
6230 /* Enable inputs of parser neighbor blocks */
6231 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6232 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6233 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6234 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6235
6236 DP(NETIF_MSG_HW, "done\n");
6237
6238 return 0; /* OK */
6239}
6240
4a33bc03 6241static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6242{
b343d002
YM		 6243 u32 val;
6244
a2fbb9ea 6245 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6246 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6247 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6248 else
6249 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6250 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6251 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6252 /*
6253 * mask read length error interrupts in brb for parser
6254 * (parsing unit and 'checksum and crc' unit)
6255 * these errors are legal (PU reads fixed length and CAC can cause
6256 * read length error on truncated packets)
6257 */
6258 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6259 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6260 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6261 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6262 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6263 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6264/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6265/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6266 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6267 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6268 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6269/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6270/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6271 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6272 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6273 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6274 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6275/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6276/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6277
b343d002
YM		 6278 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6279 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6280 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6281 if (!CHIP_IS_E1x(bp))
6282 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6283 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6284 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6285
a2fbb9ea
ET		 6286 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6287 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6288 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6289/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6290
6291 if (!CHIP_IS_E1x(bp))
6292 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6293 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6294
a2fbb9ea
ET		 6295 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6296 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6297/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6298 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6299}
6300
81f75bbf
EG		 6301static void bnx2x_reset_common(struct bnx2x *bp)
6302{
619c5cb6
VZ		 6303 u32 val = 0x1400;
6304
81f75bbf
EG		 6305 /* reset_common */
6306 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6307 0xd3ffff7f);
619c5cb6
VZ		 6308
6309 if (CHIP_IS_E3(bp)) {
6310 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6311 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6312 }
6313
6314 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6315}
6316
6317static void bnx2x_setup_dmae(struct bnx2x *bp)
6318{
6319 bp->dmae_ready = 0;
6320 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6321}
6322
573f2035
EG		 6323static void bnx2x_init_pxp(struct bnx2x *bp)
6324{
6325 u16 devctl;
6326 int r_order, w_order;
6327
2a80eebc 6328 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6329 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6330 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6331 if (bp->mrrs == -1)
6332 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6333 else {
6334 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6335 r_order = bp->mrrs;
6336 }
6337
6338 bnx2x_init_pxp_arb(bp, r_order, w_order);
6339}
fd4ef40d
EG		 6340
6341static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6342{
2145a920 6343 int is_required;
fd4ef40d 6344 u32 val;
2145a920 6345 int port;
fd4ef40d 6346
2145a920
VZ		 6347 if (BP_NOMCP(bp))
6348 return;
6349
6350 is_required = 0;
fd4ef40d
EG		 6351 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6352 SHARED_HW_CFG_FAN_FAILURE_MASK;
6353
6354 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6355 is_required = 1;
6356
6357 /*
6358 * The fan failure mechanism is usually related to the PHY type since
6359 * the power consumption of the board is affected by the PHY. Currently,
6360 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6361 */
6362 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6363 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6364 is_required |=
d90d96ba
YR		 6365 bnx2x_fan_failure_det_req(
6366 bp,
6367 bp->common.shmem_base,
a22f0788 6368 bp->common.shmem2_base,
d90d96ba 6369 port);
fd4ef40d
EG		 6370 }
6371
6372 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6373
6374 if (is_required == 0)
6375 return;
6376
6377 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6378 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6379
6380 /* set to active low mode */
6381 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6382 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6383 REG_WR(bp, MISC_REG_SPIO_INT, val);
6384
6385 /* enable interrupt to signal the IGU */
6386 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6387 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6388 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6389}
6390
c9ee9206 6391void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6392{
6393 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6394 val &= ~IGU_PF_CONF_FUNC_EN;
6395
6396 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6397 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6398 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6399}
6400
1191cb83 6401static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6402{
6403 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6404 /* Avoid common init in case MFW supports LFA */
6405 if (SHMEM2_RD(bp, size) >
6406 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6407 return;
619c5cb6
VZ		 6408 shmem_base[0] = bp->common.shmem_base;
6409 shmem2_base[0] = bp->common.shmem2_base;
6410 if (!CHIP_IS_E1x(bp)) {
6411 shmem_base[1] =
6412 SHMEM2_RD(bp, other_shmem_base_addr);
6413 shmem2_base[1] =
6414 SHMEM2_RD(bp, other_shmem2_base_addr);
6415 }
6416 bnx2x_acquire_phy_lock(bp);
6417 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6418 bp->common.chip_id);
6419 bnx2x_release_phy_lock(bp);
6420}
6421
6422/**
6423 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6424 *
6425 * @bp: driver handle
6426 */
6427static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 6428{
619c5cb6 6429 u32 val;
a2fbb9ea 6430
51c1a580 6431 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 6432
2031bd3a
DK		 6433 /*
6434 * take the UNDI lock to protect undi_unload flow from accessing
6435 * registers while we're resetting the chip
6436 */
7a06a122 6437 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6438
81f75bbf 6439 bnx2x_reset_common(bp);
34f80b04 6440 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 6441
619c5cb6
VZ		 6442 val = 0xfffc;
6443 if (CHIP_IS_E3(bp)) {
6444 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6445 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6446 }
6447 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6448
7a06a122 6449 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 6450
619c5cb6 6451 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 6452
619c5cb6
VZ		 6453 if (!CHIP_IS_E1x(bp)) {
6454 u8 abs_func_id;
f2e0899f
DK		 6455
6456 /**
6457 * 4-port mode or 2-port mode we need to turn of master-enable
6458 * for everyone, after that, turn it back on for self.
6459 * so, we disregard multi-function or not, and always disable
6460 * for all functions on the given path, this means 0,2,4,6 for
6461 * path 0 and 1,3,5,7 for path 1
6462 */
619c5cb6
VZ		 6463 for (abs_func_id = BP_PATH(bp);
6464 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6465 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 6466 REG_WR(bp,
6467 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6468 1);
6469 continue;
6470 }
6471
619c5cb6 6472 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 6473 /* clear pf enable */
6474 bnx2x_pf_disable(bp);
6475 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6476 }
6477 }
a2fbb9ea 6478
619c5cb6 6479 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 6480 if (CHIP_IS_E1(bp)) {
6481 /* enable HW interrupt from PXP on USDM overflow
6482 bit 16 on INT_MASK_0 */
6483 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6484 }
a2fbb9ea 6485
619c5cb6 6486 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 6487 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 6488
6489#ifdef __BIG_ENDIAN
34f80b04
EG		 6490 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6491 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6492 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6493 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6494 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 6495 /* make sure this value is 0 */
6496 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 6497
6498/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6499 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6500 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6501 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6502 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 6503#endif
6504
523224a3
DK		 6505 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6506
34f80b04
EG		 6507 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6508 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 6509
34f80b04
EG		 6510 /* let the HW do it's magic ... */
6511 msleep(100);
6512 /* finish PXP init */
6513 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6514 if (val != 1) {
6515 BNX2X_ERR("PXP2 CFG failed\n");
6516 return -EBUSY;
6517 }
6518 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6519 if (val != 1) {
6520 BNX2X_ERR("PXP2 RD_INIT failed\n");
6521 return -EBUSY;
6522 }
a2fbb9ea 6523
f2e0899f
DK		 6524 /* Timers bug workaround E2 only. We need to set the entire ILT to
6525 * have entries with value "0" and valid bit on.
6526 * This needs to be done by the first PF that is loaded in a path
6527 * (i.e. common phase)
6528 */
619c5cb6
VZ		 6529 if (!CHIP_IS_E1x(bp)) {
6530/* In E2 there is a bug in the timers block that can cause function 6 / 7
6531 * (i.e. vnic3) to start even if it is marked as "scan-off".
6532 * This occurs when a different function (func2,3) is being marked
6533 * as "scan-off". Real-life scenario for example: if a driver is being
6534 * load-unloaded while func6,7 are down. This will cause the timer to access
6535 * the ilt, translate to a logical address and send a request to read/write.
6536 * Since the ilt for the function that is down is not valid, this will cause
6537 * a translation error which is unrecoverable.
6538 * The Workaround is intended to make sure that when this happens nothing fatal
6539 * will occur. The workaround:
6540 * 1. First PF driver which loads on a path will:
6541 * a. After taking the chip out of reset, by using pretend,
6542 * it will write "0" to the following registers of
6543 * the other vnics.
6544 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6545 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6546 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6547 * And for itself it will write '1' to
6548 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6549 * dmae-operations (writing to pram for example.)
6550 * note: can be done for only function 6,7 but cleaner this
6551 * way.
6552 * b. Write zero+valid to the entire ILT.
6553 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6554 * VNIC3 (of that port). The range allocated will be the
6555 * entire ILT. This is needed to prevent ILT range error.
6556 * 2. Any PF driver load flow:
6557 * a. ILT update with the physical addresses of the allocated
6558 * logical pages.
6559 * b. Wait 20msec. - note that this timeout is needed to make
6560 * sure there are no requests in one of the PXP internal
6561 * queues with "old" ILT addresses.
6562 * c. PF enable in the PGLC.
6563 * d. Clear the was_error of the PF in the PGLC. (could have
6564 * occured while driver was down)
6565 * e. PF enable in the CFC (WEAK + STRONG)
6566 * f. Timers scan enable
6567 * 3. PF driver unload flow:
6568 * a. Clear the Timers scan_en.
6569 * b. Polling for scan_on=0 for that PF.
6570 * c. Clear the PF enable bit in the PXP.
6571 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6572 * e. Write zero+valid to all ILT entries (The valid bit must
6573 * stay set)
6574 * f. If this is VNIC 3 of a port then also init
6575 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6576 * to the last enrty in the ILT.
6577 *
6578 * Notes:
6579 * Currently the PF error in the PGLC is non recoverable.
6580 * In the future the there will be a recovery routine for this error.
6581 * Currently attention is masked.
6582 * Having an MCP lock on the load/unload process does not guarantee that
6583 * there is no Timer disable during Func6/7 enable. This is because the
6584 * Timers scan is currently being cleared by the MCP on FLR.
6585 * Step 2.d can be done only for PF6/7 and the driver can also check if
6586 * there is error before clearing it. But the flow above is simpler and
6587 * more general.
6588 * All ILT entries are written by zero+valid and not just PF6/7
6589 * ILT entries since in the future the ILT entries allocation for
6590 * PF-s might be dynamic.
6591 */
f2e0899f
DK		 6592 struct ilt_client_info ilt_cli;
6593 struct bnx2x_ilt ilt;
6594 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6595 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6596
b595076a 6597 /* initialize dummy TM client */
f2e0899f
DK		 6598 ilt_cli.start = 0;
6599 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6600 ilt_cli.client_num = ILT_CLIENT_TM;
6601
6602 /* Step 1: set zeroes to all ilt page entries with valid bit on
6603 * Step 2: set the timers first/last ilt entry to point
6604 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 6605 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 6606 *
6607 * both steps performed by call to bnx2x_ilt_client_init_op()
6608 * with dummy TM client
6609 *
6610 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6611 * and his brother are split registers
6612 */
6613 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6614 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6615 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6616
6617 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6618 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6619 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6620 }
6621
6622
34f80b04
EG		 6623 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6624 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 6625
619c5cb6 6626 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6627 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6628 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 6629 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 6630
619c5cb6 6631 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6632
6633 /* let the HW do it's magic ... */
6634 do {
6635 msleep(200);
6636 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6637 } while (factor-- && (val != 1));
6638
6639 if (val != 1) {
6640 BNX2X_ERR("ATC_INIT failed\n");
6641 return -EBUSY;
6642 }
6643 }
6644
619c5cb6 6645 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6646
b56e9670
AE		 6647 bnx2x_iov_init_dmae(bp);
6648
34f80b04
EG		 6649 /* clean the DMAE memory */
6650 bp->dmae_ready = 1;
619c5cb6
VZ		 6651 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6652
6653 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6654
6655 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6656
6657 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6658
619c5cb6 6659 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6660
34f80b04
EG		 6661 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6662 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6663 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6664 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6665
619c5cb6 6666 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6667
f85582f8 6668
523224a3
DK		 6669 /* QM queues pointers table */
6670 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6671
34f80b04
EG		 6672 /* soft reset pulse */
6673 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6674 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6675
55c11941
MS		 6676 if (CNIC_SUPPORT(bp))
6677 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6678
619c5cb6 6679 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 6680 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 6681 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 6682 /* enable hw interrupt from doorbell Q */
6683 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 6684
619c5cb6 6685 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 6686
619c5cb6 6687 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 6688 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 6689
f2e0899f 6690 if (!CHIP_IS_E1(bp))
619c5cb6 6691 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 6692
a3348722
BW		 6693 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6694 if (IS_MF_AFEX(bp)) {
6695 /* configure that VNTag and VLAN headers must be
6696 * received in afex mode
6697 */
6698 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6699 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6700 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6701 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6702 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6703 } else {
6704 /* Bit-map indicating which L2 hdrs may appear
6705 * after the basic Ethernet header
6706 */
6707 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6708 bp->path_has_ovlan ? 7 : 6);
6709 }
6710 }
a2fbb9ea 6711
619c5cb6
VZ		 6712 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6713 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6714 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6715 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 6716
619c5cb6
VZ		 6717 if (!CHIP_IS_E1x(bp)) {
6718 /* reset VFC memories */
6719 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6720 VFC_MEMORIES_RST_REG_CAM_RST |
6721 VFC_MEMORIES_RST_REG_RAM_RST);
6722 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6723 VFC_MEMORIES_RST_REG_CAM_RST |
6724 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 6725
619c5cb6
VZ		 6726 msleep(20);
6727 }
a2fbb9ea 6728
619c5cb6
VZ		 6729 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6730 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6731 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6732 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6733
34f80b04
EG		 6734 /* sync semi rtc */
6735 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6736 0x80000000);
6737 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6738 0x80000000);
a2fbb9ea 6739
619c5cb6
VZ		 6740 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6741 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6742 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6743
a3348722
BW		 6744 if (!CHIP_IS_E1x(bp)) {
6745 if (IS_MF_AFEX(bp)) {
6746 /* configure that VNTag and VLAN headers must be
6747 * sent in afex mode
6748 */
6749 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6750 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6751 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6752 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6753 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6754 } else {
6755 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6756 bp->path_has_ovlan ? 7 : 6);
6757 }
6758 }
f2e0899f 6759
34f80b04 6760 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6761
619c5cb6
VZ		 6762 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6763
55c11941
MS		 6764 if (CNIC_SUPPORT(bp)) {
6765 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6766 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6767 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6768 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6769 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6770 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6771 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6772 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6773 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6774 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6775 }
34f80b04 6776 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6777
34f80b04
EG		 6778 if (sizeof(union cdu_context) != 1024)
6779 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 6780 dev_alert(&bp->pdev->dev,
6781 "please adjust the size of cdu_context(%ld)\n",
6782 (long)sizeof(union cdu_context));
a2fbb9ea 6783
619c5cb6 6784 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6785 val = (4 << 24) + (0 << 12) + 1024;
6786 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6787
619c5cb6 6788 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6789 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6790 /* enable context validation interrupt from CFC */
6791 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6792
6793 /* set the thresholds to prevent CFC/CDU race */
6794 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6795
619c5cb6 6796 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6797
619c5cb6 6798 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6799 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6800
619c5cb6
VZ		 6801 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6802 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6803
34f80b04
EG		 6804 /* Reset PCIE errors for debug */
6805 REG_WR(bp, 0x2814, 0xffffffff);
6806 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6807
619c5cb6 6808 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6809 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6810 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6811 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6812 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6813 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6814 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6815 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6816 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6817 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6818 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6819 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6820 }
6821
619c5cb6 6822 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6823 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6824 /* in E3 this done in per-port section */
6825 if (!CHIP_IS_E3(bp))
6826 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6827 }
619c5cb6
VZ		 6828 if (CHIP_IS_E1H(bp))
6829 /* not applicable for E2 (and above ...) */
6830 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6831
6832 if (CHIP_REV_IS_SLOW(bp))
6833 msleep(200);
6834
6835 /* finish CFC init */
6836 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6837 if (val != 1) {
6838 BNX2X_ERR("CFC LL_INIT failed\n");
6839 return -EBUSY;
6840 }
6841 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6842 if (val != 1) {
6843 BNX2X_ERR("CFC AC_INIT failed\n");
6844 return -EBUSY;
6845 }
6846 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6847 if (val != 1) {
6848 BNX2X_ERR("CFC CAM_INIT failed\n");
6849 return -EBUSY;
6850 }
6851 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6852
f2e0899f
DK		 6853 if (CHIP_IS_E1(bp)) {
6854 /* read NIG statistic
6855 to see if this is our first up since powerup */
6856 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6857 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6858
f2e0899f
DK		 6859 /* do internal memory self test */
6860 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6861 BNX2X_ERR("internal mem self test failed\n");
6862 return -EBUSY;
6863 }
34f80b04
EG		 6864 }
6865
fd4ef40d
EG		 6866 bnx2x_setup_fan_failure_detection(bp);
6867
34f80b04
EG		 6868 /* clear PXP2 attentions */
6869 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6870
4a33bc03 6871 bnx2x_enable_blocks_attention(bp);
c9ee9206 6872 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6873
6bbca910 6874 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6875 if (CHIP_IS_E1x(bp))
6876 bnx2x__common_init_phy(bp);
6bbca910
YR		 6877 } else
6878 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6879
34f80b04
EG		 6880 return 0;
6881}
a2fbb9ea 6882
619c5cb6
VZ		 6883/**
6884 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6885 *
6886 * @bp: driver handle
6887 */
6888static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6889{
6890 int rc = bnx2x_init_hw_common(bp);
6891
6892 if (rc)
6893 return rc;
6894
6895 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6896 if (!BP_NOMCP(bp))
6897 bnx2x__common_init_phy(bp);
6898
6899 return 0;
6900}
6901
523224a3 6902static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6903{
6904 int port = BP_PORT(bp);
619c5cb6 6905 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6906 u32 low, high;
34f80b04 6907 u32 val;
a2fbb9ea 6908
619c5cb6 6909
51c1a580 6910 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 6911
6912 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6913
619c5cb6
VZ		 6914 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6915 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6916 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6917
f2e0899f
DK		 6918 /* Timers bug workaround: disables the pf_master bit in pglue at
6919 * common phase, we need to enable it here before any dmae access are
6920 * attempted. Therefore we manually added the enable-master to the
6921 * port phase (it also happens in the function phase)
6922 */
619c5cb6 6923 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6924 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6925
619c5cb6
VZ		 6926 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6927 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6928 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6929 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6930
6931 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6932 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6933 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6934 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6935
523224a3
DK		 6936 /* QM cid (connection) count */
6937 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6938
55c11941
MS		 6939 if (CNIC_SUPPORT(bp)) {
6940 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6941 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6942 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6943 }
cdaa7cb8 6944
619c5cb6 6945 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 6946
2b674047
DK		 6947 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6948
f2e0899f 6949 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6950
6951 if (IS_MF(bp))
6952 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6953 else if (bp->dev->mtu > 4096) {
6954 if (bp->flags & ONE_PORT_FLAG)
6955 low = 160;
6956 else {
6957 val = bp->dev->mtu;
6958 /* (24*1024 + val*4)/256 */
6959 low = 96 + (val/64) +
6960 ((val % 64) ? 1 : 0);
6961 }
6962 } else
6963 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6964 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6965 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6966 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6967 }
1c06328c 6968
619c5cb6
VZ		 6969 if (CHIP_MODE_IS_4_PORT(bp))
6970 REG_WR(bp, (BP_PORT(bp) ?
6971 BRB1_REG_MAC_GUARANTIED_1 :
6972 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6973
ca00392c 6974
619c5cb6 6975 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 6976 if (CHIP_IS_E3B0(bp)) {
6977 if (IS_MF_AFEX(bp)) {
6978 /* configure headers for AFEX mode */
6979 REG_WR(bp, BP_PORT(bp) ?
6980 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6981 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6982 REG_WR(bp, BP_PORT(bp) ?
6983 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6984 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6985 REG_WR(bp, BP_PORT(bp) ?
6986 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6987 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6988 } else {
6989 /* Ovlan exists only if we are in multi-function +
6990 * switch-dependent mode, in switch-independent there
6991 * is no ovlan headers
6992 */
6993 REG_WR(bp, BP_PORT(bp) ?
6994 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6995 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6996 (bp->path_has_ovlan ? 7 : 6));
6997 }
6998 }
356e2385 6999
619c5cb6
VZ		 7000 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7001 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7002 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7003 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7004
619c5cb6
VZ		 7005 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7006 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7007 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7008 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7009
619c5cb6
VZ		 7010 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7011 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7012
619c5cb6
VZ		 7013 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7014
7015 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7016 /* configure PBF to work without PAUSE mtu 9000 */
7017 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7018
f2e0899f
DK		 7019 /* update threshold */
7020 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7021 /* update init credit */
7022 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7023
f2e0899f
DK		 7024 /* probe changes */
7025 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7026 udelay(50);
7027 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7028 }
a2fbb9ea 7029
55c11941
MS		 7030 if (CNIC_SUPPORT(bp))
7031 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7032
619c5cb6
VZ		 7033 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7034 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7035
7036 if (CHIP_IS_E1(bp)) {
7037 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7038 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7039 }
619c5cb6 7040 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7041
619c5cb6 7042 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7043
619c5cb6 7044 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 7045 /* init aeu_mask_attn_func_0/1:
7046 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7047 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7048 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7049 val = IS_MF(bp) ? 0xF7 : 0x7;
7050 /* Enable DCBX attention for all but E1 */
7051 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7052 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7053
619c5cb6
VZ		 7054 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7055
7056 if (!CHIP_IS_E1x(bp)) {
7057 /* Bit-map indicating which L2 hdrs may appear after the
7058 * basic Ethernet header
7059 */
a3348722
BW		 7060 if (IS_MF_AFEX(bp))
7061 REG_WR(bp, BP_PORT(bp) ?
7062 NIG_REG_P1_HDRS_AFTER_BASIC :
7063 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7064 else
7065 REG_WR(bp, BP_PORT(bp) ?
7066 NIG_REG_P1_HDRS_AFTER_BASIC :
7067 NIG_REG_P0_HDRS_AFTER_BASIC,
7068 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7069
7070 if (CHIP_IS_E3(bp))
7071 REG_WR(bp, BP_PORT(bp) ?
7072 NIG_REG_LLH1_MF_MODE :
7073 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7074 }
7075 if (!CHIP_IS_E3(bp))
7076 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7077
f2e0899f 7078 if (!CHIP_IS_E1(bp)) {
fb3bff17 7079 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7080 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7081 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7082
619c5cb6 7083 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7084 val = 0;
7085 switch (bp->mf_mode) {
7086 case MULTI_FUNCTION_SD:
7087 val = 1;
7088 break;
7089 case MULTI_FUNCTION_SI:
a3348722 7090 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7091 val = 2;
7092 break;
7093 }
7094
7095 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7096 NIG_REG_LLH0_CLS_TYPE), val);
7097 }
1c06328c
EG		 7098 {
7099 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7100 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7101 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7102 }
34f80b04
EG		 7103 }
7104
619c5cb6
VZ		 7105
7106 /* If SPIO5 is set to generate interrupts, enable it for this port */
7107 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7108 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7109 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7110 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7111 val = REG_RD(bp, reg_addr);
f1410647 7112 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7113 REG_WR(bp, reg_addr, val);
f1410647 7114 }
a2fbb9ea 7115
34f80b04
EG		 7116 return 0;
7117}
7118
34f80b04
EG		 7119static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7120{
7121 int reg;
32d68de1 7122 u32 wb_write[2];
34f80b04 7123
f2e0899f 7124 if (CHIP_IS_E1(bp))
34f80b04 7125 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7126 else
7127 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7128
32d68de1
YM		 7129 wb_write[0] = ONCHIP_ADDR1(addr);
7130 wb_write[1] = ONCHIP_ADDR2(addr);
7131 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7132}
7133
b56e9670 7134void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7135{
7136 u32 data, ctl, cnt = 100;
7137 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7138 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7139 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7140 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7141 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7142 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7143
7144 /* Not supported in BC mode */
7145 if (CHIP_INT_MODE_IS_BC(bp))
7146 return;
7147
7148 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7149 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7150 IGU_REGULAR_CLEANUP_SET |
7151 IGU_REGULAR_BCLEANUP;
7152
7153 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7154 func_encode << IGU_CTRL_REG_FID_SHIFT |
7155 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7156
7157 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7158 data, igu_addr_data);
7159 REG_WR(bp, igu_addr_data, data);
7160 mmiowb();
7161 barrier();
7162 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7163 ctl, igu_addr_ctl);
7164 REG_WR(bp, igu_addr_ctl, ctl);
7165 mmiowb();
7166 barrier();
7167
7168 /* wait for clean up to finish */
7169 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7170 msleep(20);
7171
7172
7173 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7174 DP(NETIF_MSG_HW,
7175 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7176 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7177 }
7178}
7179
7180static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7181{
619c5cb6 7182 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7183}
7184
1191cb83 7185static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7186{
7187 u32 i, base = FUNC_ILT_BASE(func);
7188 for (i = base; i < base + ILT_PER_FUNC; i++)
7189 bnx2x_ilt_wr(bp, i, 0);
7190}
7191
55c11941 7192
910cc727 7193static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7194{
7195 int port = BP_PORT(bp);
7196 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7197 /* T1 hash bits value determines the T1 number of entries */
7198 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7199}
7200
7201static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7202{
7203 int rc;
7204 struct bnx2x_func_state_params func_params = {NULL};
7205 struct bnx2x_func_switch_update_params *switch_update_params =
7206 &func_params.params.switch_update;
7207
7208 /* Prepare parameters for function state transitions */
7209 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7210 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7211
7212 func_params.f_obj = &bp->func_obj;
7213 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7214
7215 /* Function parameters */
7216 switch_update_params->suspend = suspend;
7217
7218 rc = bnx2x_func_state_change(bp, &func_params);
7219
7220 return rc;
7221}
7222
910cc727 7223static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7224{
7225 int rc, i, port = BP_PORT(bp);
7226 int vlan_en = 0, mac_en[NUM_MACS];
7227
7228
7229 /* Close input from network */
7230 if (bp->mf_mode == SINGLE_FUNCTION) {
7231 bnx2x_set_rx_filter(&bp->link_params, 0);
7232 } else {
7233 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7234 NIG_REG_LLH0_FUNC_EN);
7235 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7236 NIG_REG_LLH0_FUNC_EN, 0);
7237 for (i = 0; i < NUM_MACS; i++) {
7238 mac_en[i] = REG_RD(bp, port ?
7239 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7240 4 * i) :
7241 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7242 4 * i));
7243 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7244 4 * i) :
7245 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7246 }
7247 }
7248
7249 /* Close BMC to host */
7250 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7251 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7252
7253 /* Suspend Tx switching to the PF. Completion of this ramrod
7254 * further guarantees that all the packets of that PF / child
7255 * VFs in BRB were processed by the Parser, so it is safe to
7256 * change the NIC_MODE register.
7257 */
7258 rc = bnx2x_func_switch_update(bp, 1);
7259 if (rc) {
7260 BNX2X_ERR("Can't suspend tx-switching!\n");
7261 return rc;
7262 }
7263
7264 /* Change NIC_MODE register */
7265 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7266
7267 /* Open input from network */
7268 if (bp->mf_mode == SINGLE_FUNCTION) {
7269 bnx2x_set_rx_filter(&bp->link_params, 1);
7270 } else {
7271 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7272 NIG_REG_LLH0_FUNC_EN, vlan_en);
7273 for (i = 0; i < NUM_MACS; i++) {
7274 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7275 4 * i) :
7276 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7277 mac_en[i]);
7278 }
7279 }
7280
7281 /* Enable BMC to host */
7282 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7283 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7284
7285 /* Resume Tx switching to the PF */
7286 rc = bnx2x_func_switch_update(bp, 0);
7287 if (rc) {
7288 BNX2X_ERR("Can't resume tx-switching!\n");
7289 return rc;
7290 }
7291
7292 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7293 return 0;
7294}
7295
7296int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7297{
7298 int rc;
7299
7300 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7301
7302 if (CONFIGURE_NIC_MODE(bp)) {
7303 /* Configrue searcher as part of function hw init */
7304 bnx2x_init_searcher(bp);
7305
7306 /* Reset NIC mode */
7307 rc = bnx2x_reset_nic_mode(bp);
7308 if (rc)
7309 BNX2X_ERR("Can't change NIC mode!\n");
7310 return rc;
7311 }
7312
7313 return 0;
7314}
7315
523224a3 7316static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7317{
7318 int port = BP_PORT(bp);
7319 int func = BP_FUNC(bp);
619c5cb6 7320 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7321 struct bnx2x_ilt *ilt = BP_ILT(bp);
7322 u16 cdu_ilt_start;
8badd27a 7323 u32 addr, val;
f4a66897 7324 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7325 int i, main_mem_width, rc;
34f80b04 7326
51c1a580 7327 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7328
619c5cb6 7329 /* FLR cleanup - hmmm */
89db4ad8
AE		 7330 if (!CHIP_IS_E1x(bp)) {
7331 rc = bnx2x_pf_flr_clnup(bp);
7332 if (rc)
7333 return rc;
7334 }
619c5cb6 7335
8badd27a 7336 /* set MSI reconfigure capability */
f2e0899f
DK		 7337 if (bp->common.int_block == INT_BLOCK_HC) {
7338 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7339 val = REG_RD(bp, addr);
7340 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7341 REG_WR(bp, addr, val);
7342 }
8badd27a 7343
619c5cb6
VZ		 7344 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7345 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7346
523224a3
DK		 7347 ilt = BP_ILT(bp);
7348 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7349
290ca2bb
AE		 7350 if (IS_SRIOV(bp))
7351 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7352 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7353
7354 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7355 * those of the VFs, so start line should be reset
7356 */
7357 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7358 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7359 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7360 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7361 bp->context[i].cxt_mapping;
7362 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7363 }
290ca2bb 7364
523224a3 7365 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7366
55c11941
MS		 7367 if (!CONFIGURE_NIC_MODE(bp)) {
7368 bnx2x_init_searcher(bp);
7369 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7370 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7371 } else {
7372 /* Set NIC mode */
7373 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7374 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
37b091ba 7375
55c11941 7376 }
37b091ba 7377
619c5cb6 7378 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7379 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7380
7381 /* Turn on a single ISR mode in IGU if driver is going to use
7382 * INT#x or MSI
7383 */
7384 if (!(bp->flags & USING_MSIX_FLAG))
7385 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7386 /*
7387 * Timers workaround bug: function init part.
7388 * Need to wait 20msec after initializing ILT,
7389 * needed to make sure there are no requests in
7390 * one of the PXP internal queues with "old" ILT addresses
7391 */
7392 msleep(20);
7393 /*
7394 * Master enable - Due to WB DMAE writes performed before this
7395 * register is re-initialized as part of the regular function
7396 * init
7397 */
7398 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7399 /* Enable the function in IGU */
7400 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7401 }
7402
523224a3 7403 bp->dmae_ready = 1;
34f80b04 7404
619c5cb6 7405 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 7406
619c5cb6 7407 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7408 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7409
619c5cb6
VZ		 7410 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7411 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7412 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7413 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7414 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7415 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7416 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7417 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7418 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7419 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7420 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7421 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7422 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7423
7424 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7425 REG_WR(bp, QM_REG_PF_EN, 1);
7426
619c5cb6
VZ		 7427 if (!CHIP_IS_E1x(bp)) {
7428 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7429 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7430 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7431 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7432 }
7433 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7434
7435 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7436 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
b56e9670
AE		 7437
7438 bnx2x_iov_init_dq(bp);
7439
619c5cb6
VZ		 7440 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7441 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7442 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7443 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7444 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7445 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7446 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7447 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7448 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7449 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7450 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7451
619c5cb6 7452 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 7453
619c5cb6 7454 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 7455
619c5cb6 7456 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7457 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7458
fb3bff17 7459 if (IS_MF(bp)) {
34f80b04 7460 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 7461 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 7462 }
7463
619c5cb6 7464 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 7465
34f80b04 7466 /* HC init per function */
f2e0899f
DK		 7467 if (bp->common.int_block == INT_BLOCK_HC) {
7468 if (CHIP_IS_E1H(bp)) {
7469 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7470
7471 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7472 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7473 }
619c5cb6 7474 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 7475
7476 } else {
7477 int num_segs, sb_idx, prod_offset;
7478
34f80b04
EG		 7479 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7480
619c5cb6 7481 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7483 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7484 }
7485
619c5cb6 7486 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7487
619c5cb6 7488 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7489 int dsb_idx = 0;
7490 /**
7491 * Producer memory:
7492 * E2 mode: address 0-135 match to the mapping memory;
7493 * 136 - PF0 default prod; 137 - PF1 default prod;
7494 * 138 - PF2 default prod; 139 - PF3 default prod;
7495 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7496 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7497 * 144-147 reserved.
7498 *
7499 * E1.5 mode - In backward compatible mode;
7500 * for non default SB; each even line in the memory
7501 * holds the U producer and each odd line hold
7502 * the C producer. The first 128 producers are for
7503 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7504 * producers are for the DSB for each PF.
7505 * Each PF has five segments: (the order inside each
7506 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7507 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7508 * 144-147 attn prods;
7509 */
7510 /* non-default-status-blocks */
7511 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7512 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7513 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7514 prod_offset = (bp->igu_base_sb + sb_idx) *
7515 num_segs;
7516
7517 for (i = 0; i < num_segs; i++) {
7518 addr = IGU_REG_PROD_CONS_MEMORY +
7519 (prod_offset + i) * 4;
7520 REG_WR(bp, addr, 0);
7521 }
7522 /* send consumer update with value 0 */
7523 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7524 USTORM_ID, 0, IGU_INT_NOP, 1);
7525 bnx2x_igu_clear_sb(bp,
7526 bp->igu_base_sb + sb_idx);
7527 }
7528
7529 /* default-status-blocks */
7530 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7531 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7532
7533 if (CHIP_MODE_IS_4_PORT(bp))
7534 dsb_idx = BP_FUNC(bp);
7535 else
3395a033 7536 dsb_idx = BP_VN(bp);
f2e0899f
DK		 7537
7538 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7539 IGU_BC_BASE_DSB_PROD + dsb_idx :
7540 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7541
3395a033
DK		 7542 /*
7543 * igu prods come in chunks of E1HVN_MAX (4) -
7544 * does not matters what is the current chip mode
7545 */
f2e0899f
DK		 7546 for (i = 0; i < (num_segs * E1HVN_MAX);
7547 i += E1HVN_MAX) {
7548 addr = IGU_REG_PROD_CONS_MEMORY +
7549 (prod_offset + i)*4;
7550 REG_WR(bp, addr, 0);
7551 }
7552 /* send consumer update with 0 */
7553 if (CHIP_INT_MODE_IS_BC(bp)) {
7554 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7555 USTORM_ID, 0, IGU_INT_NOP, 1);
7556 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7557 CSTORM_ID, 0, IGU_INT_NOP, 1);
7558 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7559 XSTORM_ID, 0, IGU_INT_NOP, 1);
7560 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7561 TSTORM_ID, 0, IGU_INT_NOP, 1);
7562 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7563 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7564 } else {
7565 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7566 USTORM_ID, 0, IGU_INT_NOP, 1);
7567 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7568 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7569 }
7570 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7571
7572 /* !!! these should become driver const once
7573 rf-tool supports split-68 const */
7574 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7575 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7576 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7577 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7578 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7579 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7580 }
34f80b04 7581 }
34f80b04 7582
c14423fe 7583 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 7584 REG_WR(bp, 0x2114, 0xffffffff);
7585 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 7586
f4a66897
VZ		 7587 if (CHIP_IS_E1x(bp)) {
7588 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7589 main_mem_base = HC_REG_MAIN_MEMORY +
7590 BP_PORT(bp) * (main_mem_size * 4);
7591 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7592 main_mem_width = 8;
7593
7594 val = REG_RD(bp, main_mem_prty_clr);
7595 if (val)
51c1a580
MS		 7596 DP(NETIF_MSG_HW,
7597 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7598 val);
f4a66897
VZ		 7599
7600 /* Clear "false" parity errors in MSI-X table */
7601 for (i = main_mem_base;
7602 i < main_mem_base + main_mem_size * 4;
7603 i += main_mem_width) {
7604 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7605 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7606 i, main_mem_width / 4);
7607 }
7608 /* Clear HC parity attention */
7609 REG_RD(bp, main_mem_prty_clr);
7610 }
7611
619c5cb6
VZ		 7612#ifdef BNX2X_STOP_ON_ERROR
7613 /* Enable STORMs SP logging */
7614 REG_WR8(bp, BAR_USTRORM_INTMEM +
7615 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7616 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7617 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7618 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7619 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7620 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7621 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7622#endif
7623
b7737c9b 7624 bnx2x_phy_probe(&bp->link_params);
f85582f8 7625
34f80b04
EG		 7626 return 0;
7627}
7628
a2fbb9ea 7629
55c11941
MS		 7630void bnx2x_free_mem_cnic(struct bnx2x *bp)
7631{
7632 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7633
7634 if (!CHIP_IS_E1x(bp))
7635 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7636 sizeof(struct host_hc_status_block_e2));
7637 else
7638 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7639 sizeof(struct host_hc_status_block_e1x));
7640
7641 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7642}
7643
9f6c9258 7644void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 7645{
a052997e
MS		 7646 int i;
7647
a2fbb9ea 7648 /* fastpath */
b3b83c3f 7649 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 7650 /* end of fastpath */
7651
7652 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 7653 sizeof(struct host_sp_status_block));
a2fbb9ea 7654
619c5cb6
VZ		 7655 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7656 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7657
a2fbb9ea 7658 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 7659 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7660
a052997e
MS		 7661 for (i = 0; i < L2_ILT_LINES(bp); i++)
7662 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7663 bp->context[i].size);
523224a3
DK		 7664 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7665
7666 BNX2X_FREE(bp->ilt->lines);
f85582f8 7667
7a9b2557 7668 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 7669
523224a3
DK		 7670 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7671 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 7672}
7673
a2fbb9ea 7674
55c11941 7675int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 7676{
619c5cb6
VZ		 7677 if (!CHIP_IS_E1x(bp))
7678 /* size = the status block + ramrod buffers */
f2e0899f
DK		 7679 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7680 sizeof(struct host_hc_status_block_e2));
7681 else
55c11941
MS		 7682 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7683 &bp->cnic_sb_mapping,
7684 sizeof(struct
7685 host_hc_status_block_e1x));
8badd27a 7686
55c11941
MS		 7687 if (CONFIGURE_NIC_MODE(bp))
7688 /* allocate searcher T2 table, as it wan't allocated before */
7689 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7690
7691 /* write address to which L5 should insert its values */
7692 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7693 &bp->slowpath->drv_info_to_mcp;
7694
7695 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7696 goto alloc_mem_err;
7697
7698 return 0;
7699
7700alloc_mem_err:
7701 bnx2x_free_mem_cnic(bp);
7702 BNX2X_ERR("Can't allocate memory\n");
7703 return -ENOMEM;
7704}
7705
7706int bnx2x_alloc_mem(struct bnx2x *bp)
7707{
7708 int i, allocated, context_size;
a2fbb9ea 7709
55c11941
MS		 7710 if (!CONFIGURE_NIC_MODE(bp))
7711 /* allocate searcher T2 table */
7712 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
8badd27a 7713
523224a3
DK		 7714 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7715 sizeof(struct host_sp_status_block));
a2fbb9ea 7716
523224a3
DK		 7717 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7718 sizeof(struct bnx2x_slowpath));
a2fbb9ea 7719
a052997e
MS		 7720 /* Allocate memory for CDU context:
7721 * This memory is allocated separately and not in the generic ILT
7722 * functions because CDU differs in few aspects:
7723 * 1. There are multiple entities allocating memory for context -
7724 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7725 * its own ILT lines.
7726 * 2. Since CDU page-size is not a single 4KB page (which is the case
7727 * for the other ILT clients), to be efficient we want to support
7728 * allocation of sub-page-size in the last entry.
7729 * 3. Context pointers are used by the driver to pass to FW / update
7730 * the context (for the other ILT clients the pointers are used just to
7731 * free the memory during unload).
7732 */
7733 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 7734
a052997e
MS		 7735 for (i = 0, allocated = 0; allocated < context_size; i++) {
7736 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7737 (context_size - allocated));
7738 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7739 &bp->context[i].cxt_mapping,
7740 bp->context[i].size);
7741 allocated += bp->context[i].size;
7742 }
523224a3 7743 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 7744
523224a3
DK		 7745 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7746 goto alloc_mem_err;
65abd74d 7747
67c431a5
AE		 7748 if (bnx2x_iov_alloc_mem(bp))
7749 goto alloc_mem_err;
7750
9f6c9258
DK		 7751 /* Slow path ring */
7752 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 7753
523224a3
DK		 7754 /* EQ */
7755 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7756 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 7757
9f6c9258 7758 return 0;
e1510706 7759
9f6c9258
DK		 7760alloc_mem_err:
7761 bnx2x_free_mem(bp);
51c1a580 7762 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 7763 return -ENOMEM;
65abd74d
YG		 7764}
7765
a2fbb9ea
ET		 7766/*
7767 * Init service functions
7768 */
a2fbb9ea 7769
619c5cb6
VZ		 7770int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7771 struct bnx2x_vlan_mac_obj *obj, bool set,
7772 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 7773{
619c5cb6
VZ		 7774 int rc;
7775 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 7776
619c5cb6 7777 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 7778
619c5cb6
VZ		 7779 /* Fill general parameters */
7780 ramrod_param.vlan_mac_obj = obj;
7781 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 7782
619c5cb6
VZ		 7783 /* Fill a user request section if needed */
7784 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7785 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 7786
619c5cb6 7787 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 7788
619c5cb6
VZ		 7789 /* Set the command: ADD or DEL */
7790 if (set)
7791 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7792 else
7793 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 7794 }
7795
619c5cb6 7796 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 7797
7798 if (rc == -EEXIST) {
7799 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7800 /* do not treat adding same MAC as error */
7801 rc = 0;
7802 } else if (rc < 0)
619c5cb6 7803 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 7804
619c5cb6 7805 return rc;
a2fbb9ea
ET		 7806}
7807
619c5cb6
VZ		 7808int bnx2x_del_all_macs(struct bnx2x *bp,
7809 struct bnx2x_vlan_mac_obj *mac_obj,
7810 int mac_type, bool wait_for_comp)
e665bfda 7811{
619c5cb6
VZ		 7812 int rc;
7813 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 7814
619c5cb6
VZ		 7815 /* Wait for completion of requested */
7816 if (wait_for_comp)
7817 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 7818
619c5cb6
VZ		 7819 /* Set the mac type of addresses we want to clear */
7820 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 7821
619c5cb6
VZ		 7822 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7823 if (rc < 0)
7824 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 7825
619c5cb6 7826 return rc;
0793f83f
DK		 7827}
7828
619c5cb6 7829int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 7830{
619c5cb6 7831 unsigned long ramrod_flags = 0;
e665bfda 7832
a3348722
BW		 7833 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7834 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
51c1a580
MS		 7835 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7836 "Ignoring Zero MAC for STORAGE SD mode\n");
614c76df
DK		 7837 return 0;
7838 }
614c76df 7839
619c5cb6 7840 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 7841
619c5cb6
VZ		 7842 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7843 /* Eth MAC is set on RSS leading client (fp[0]) */
15192a8c
BW		 7844 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7845 set, BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 7846}
6e30dd4e 7847
619c5cb6 7848int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 7849{
619c5cb6 7850 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 7851}
a2fbb9ea 7852
d6214d7a 7853/**
e8920674 7854 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 7855 *
e8920674 7856 * @bp: driver handle
d6214d7a 7857 *
e8920674 7858 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 7859 */
1ab4434c 7860int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 7861{
1ab4434c
AE		 7862 int rc = 0;
7863
7864 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7865 return -EINVAL;
7866
9ee3d37b 7867 switch (int_mode) {
1ab4434c
AE		 7868 case BNX2X_INT_MODE_MSIX:
7869 /* attempt to enable msix */
7870 rc = bnx2x_enable_msix(bp);
7871
7872 /* msix attained */
7873 if (!rc)
7874 return 0;
7875
7876 /* vfs use only msix */
7877 if (rc && IS_VF(bp))
7878 return rc;
7879
7880 /* failed to enable multiple MSI-X */
7881 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7882 bp->num_queues,
7883 1 + bp->num_cnic_queues);
7884
7885 /* falling through... */
7886 case BNX2X_INT_MODE_MSI:
d6214d7a 7887 bnx2x_enable_msi(bp);
1ab4434c 7888
d6214d7a 7889 /* falling through... */
1ab4434c 7890 case BNX2X_INT_MODE_INTX:
55c11941
MS		 7891 bp->num_ethernet_queues = 1;
7892 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 7893 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 7894 break;
d6214d7a 7895 default:
1ab4434c
AE		 7896 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7897 return -EINVAL;
9f6c9258 7898 }
1ab4434c 7899 return 0;
a2fbb9ea
ET		 7900}
7901
1ab4434c 7902/* must be called prior to any HW initializations */
c2bff63f
DK		 7903static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7904{
290ca2bb
AE		 7905 if (IS_SRIOV(bp))
7906 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 7907 return L2_ILT_LINES(bp);
7908}
7909
523224a3
DK		 7910void bnx2x_ilt_set_info(struct bnx2x *bp)
7911{
7912 struct ilt_client_info *ilt_client;
7913 struct bnx2x_ilt *ilt = BP_ILT(bp);
7914 u16 line = 0;
7915
7916 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7917 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7918
7919 /* CDU */
7920 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7921 ilt_client->client_num = ILT_CLIENT_CDU;
7922 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7923 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7924 ilt_client->start = line;
619c5cb6 7925 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 7926
7927 if (CNIC_SUPPORT(bp))
7928 line += CNIC_ILT_LINES;
523224a3
DK		 7929 ilt_client->end = line - 1;
7930
51c1a580 7931 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 7932 ilt_client->start,
7933 ilt_client->end,
7934 ilt_client->page_size,
7935 ilt_client->flags,
7936 ilog2(ilt_client->page_size >> 12));
7937
7938 /* QM */
7939 if (QM_INIT(bp->qm_cid_count)) {
7940 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7941 ilt_client->client_num = ILT_CLIENT_QM;
7942 ilt_client->page_size = QM_ILT_PAGE_SZ;
7943 ilt_client->flags = 0;
7944 ilt_client->start = line;
7945
7946 /* 4 bytes for each cid */
7947 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7948 QM_ILT_PAGE_SZ);
7949
7950 ilt_client->end = line - 1;
7951
51c1a580
MS		 7952 DP(NETIF_MSG_IFUP,
7953 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 7954 ilt_client->start,
7955 ilt_client->end,
7956 ilt_client->page_size,
7957 ilt_client->flags,
7958 ilog2(ilt_client->page_size >> 12));
7959
7960 }
523224a3 7961
55c11941
MS		 7962 if (CNIC_SUPPORT(bp)) {
7963 /* SRC */
7964 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7965 ilt_client->client_num = ILT_CLIENT_SRC;
7966 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7967 ilt_client->flags = 0;
7968 ilt_client->start = line;
7969 line += SRC_ILT_LINES;
7970 ilt_client->end = line - 1;
523224a3 7971
55c11941
MS		 7972 DP(NETIF_MSG_IFUP,
7973 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7974 ilt_client->start,
7975 ilt_client->end,
7976 ilt_client->page_size,
7977 ilt_client->flags,
7978 ilog2(ilt_client->page_size >> 12));
9f6c9258 7979
55c11941
MS		 7980 /* TM */
7981 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7982 ilt_client->client_num = ILT_CLIENT_TM;
7983 ilt_client->page_size = TM_ILT_PAGE_SZ;
7984 ilt_client->flags = 0;
7985 ilt_client->start = line;
7986 line += TM_ILT_LINES;
7987 ilt_client->end = line - 1;
523224a3 7988
55c11941
MS		 7989 DP(NETIF_MSG_IFUP,
7990 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7991 ilt_client->start,
7992 ilt_client->end,
7993 ilt_client->page_size,
7994 ilt_client->flags,
7995 ilog2(ilt_client->page_size >> 12));
7996 }
9f6c9258 7997
619c5cb6 7998 BUG_ON(line > ILT_MAX_LINES);
523224a3 7999}
f85582f8 8000
619c5cb6
VZ		 8001/**
8002 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8003 *
8004 * @bp: driver handle
8005 * @fp: pointer to fastpath
8006 * @init_params: pointer to parameters structure
8007 *
8008 * parameters configured:
8009 * - HC configuration
8010 * - Queue's CDU context
8011 */
1191cb83 8012static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8013 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8014{
6383c0b3
AE		 8015
8016 u8 cos;
a052997e
MS		 8017 int cxt_index, cxt_offset;
8018
619c5cb6
VZ		 8019 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8020 if (!IS_FCOE_FP(fp)) {
8021 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8022 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8023
8024 /* If HC is supporterd, enable host coalescing in the transition
8025 * to INIT state.
8026 */
8027 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8028 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8029
8030 /* HC rate */
8031 init_params->rx.hc_rate = bp->rx_ticks ?
8032 (1000000 / bp->rx_ticks) : 0;
8033 init_params->tx.hc_rate = bp->tx_ticks ?
8034 (1000000 / bp->tx_ticks) : 0;
8035
8036 /* FW SB ID */
8037 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8038 fp->fw_sb_id;
8039
8040 /*
8041 * CQ index among the SB indices: FCoE clients uses the default
8042 * SB, therefore it's different.
8043 */
6383c0b3
AE		 8044 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8045 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8046 }
8047
6383c0b3
AE		 8048 /* set maximum number of COSs supported by this queue */
8049 init_params->max_cos = fp->max_cos;
8050
51c1a580 8051 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8052 fp->index, init_params->max_cos);
8053
8054 /* set the context pointers queue object */
a052997e 8055 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8056 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8057 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8058 ILT_PAGE_CIDS);
6383c0b3 8059 init_params->cxts[cos] =
a052997e
MS		 8060 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8061 }
619c5cb6
VZ		 8062}
8063
910cc727 8064static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8065 struct bnx2x_queue_state_params *q_params,
8066 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8067 int tx_index, bool leading)
8068{
8069 memset(tx_only_params, 0, sizeof(*tx_only_params));
8070
8071 /* Set the command */
8072 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8073
8074 /* Set tx-only QUEUE flags: don't zero statistics */
8075 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8076
8077 /* choose the index of the cid to send the slow path on */
8078 tx_only_params->cid_index = tx_index;
8079
8080 /* Set general TX_ONLY_SETUP parameters */
8081 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8082
8083 /* Set Tx TX_ONLY_SETUP parameters */
8084 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8085
51c1a580
MS		 8086 DP(NETIF_MSG_IFUP,
8087 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8088 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8089 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8090 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8091
8092 /* send the ramrod */
8093 return bnx2x_queue_state_change(bp, q_params);
8094}
8095
8096
619c5cb6
VZ		 8097/**
8098 * bnx2x_setup_queue - setup queue
8099 *
8100 * @bp: driver handle
8101 * @fp: pointer to fastpath
8102 * @leading: is leading
8103 *
8104 * This function performs 2 steps in a Queue state machine
8105 * actually: 1) RESET->INIT 2) INIT->SETUP
8106 */
8107
8108int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8109 bool leading)
8110{
3b603066 8111 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8112 struct bnx2x_queue_setup_params *setup_params =
8113 &q_params.params.setup;
6383c0b3
AE		 8114 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8115 &q_params.params.tx_only;
a2fbb9ea 8116 int rc;
6383c0b3
AE		 8117 u8 tx_index;
8118
51c1a580 8119 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8120
ec6ba945
VZ		 8121 /* reset IGU state skip FCoE L2 queue */
8122 if (!IS_FCOE_FP(fp))
8123 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8124 IGU_INT_ENABLE, 0);
a2fbb9ea 8125
15192a8c 8126 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8127 /* We want to wait for completion in this context */
8128 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8129
619c5cb6
VZ		 8130 /* Prepare the INIT parameters */
8131 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8132
619c5cb6
VZ		 8133 /* Set the command */
8134 q_params.cmd = BNX2X_Q_CMD_INIT;
8135
8136 /* Change the state to INIT */
8137 rc = bnx2x_queue_state_change(bp, &q_params);
8138 if (rc) {
6383c0b3 8139 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8140 return rc;
8141 }
ec6ba945 8142
51c1a580 8143 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3
AE		 8144
8145
619c5cb6
VZ		 8146 /* Now move the Queue to the SETUP state... */
8147 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8148
619c5cb6
VZ		 8149 /* Set QUEUE flags */
8150 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8151
619c5cb6 8152 /* Set general SETUP parameters */
6383c0b3
AE		 8153 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8154 FIRST_TX_COS_INDEX);
619c5cb6 8155
6383c0b3 8156 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8157 &setup_params->rxq_params);
8158
6383c0b3
AE		 8159 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8160 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8161
8162 /* Set the command */
8163 q_params.cmd = BNX2X_Q_CMD_SETUP;
8164
55c11941
MS		 8165 if (IS_FCOE_FP(fp))
8166 bp->fcoe_init = true;
8167
619c5cb6
VZ		 8168 /* Change the state to SETUP */
8169 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8170 if (rc) {
8171 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8172 return rc;
8173 }
8174
8175 /* loop through the relevant tx-only indices */
8176 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8177 tx_index < fp->max_cos;
8178 tx_index++) {
8179
8180 /* prepare and send tx-only ramrod*/
8181 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8182 tx_only_params, tx_index, leading);
8183 if (rc) {
8184 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8185 fp->index, tx_index);
8186 return rc;
8187 }
8188 }
523224a3 8189
34f80b04 8190 return rc;
a2fbb9ea
ET		 8191}
8192
619c5cb6 8193static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8194{
619c5cb6 8195 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8196 struct bnx2x_fp_txdata *txdata;
3b603066 8197 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8198 int rc, tx_index;
8199
51c1a580 8200 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8201
15192a8c 8202 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8203 /* We want to wait for completion in this context */
8204 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8205
6383c0b3
AE		 8206
8207 /* close tx-only connections */
8208 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8209 tx_index < fp->max_cos;
8210 tx_index++){
8211
8212 /* ascertain this is a normal queue*/
65565884 8213 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8214
51c1a580 8215 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8216 txdata->txq_index);
8217
8218 /* send halt terminate on tx-only connection */
8219 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8220 memset(&q_params.params.terminate, 0,
8221 sizeof(q_params.params.terminate));
8222 q_params.params.terminate.cid_index = tx_index;
8223
8224 rc = bnx2x_queue_state_change(bp, &q_params);
8225 if (rc)
8226 return rc;
8227
8228 /* send halt terminate on tx-only connection */
8229 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8230 memset(&q_params.params.cfc_del, 0,
8231 sizeof(q_params.params.cfc_del));
8232 q_params.params.cfc_del.cid_index = tx_index;
8233 rc = bnx2x_queue_state_change(bp, &q_params);
8234 if (rc)
8235 return rc;
8236 }
8237 /* Stop the primary connection: */
8238 /* ...halt the connection */
619c5cb6
VZ		 8239 q_params.cmd = BNX2X_Q_CMD_HALT;
8240 rc = bnx2x_queue_state_change(bp, &q_params);
8241 if (rc)
da5a662a 8242 return rc;
a2fbb9ea 8243
6383c0b3 8244 /* ...terminate the connection */
619c5cb6 8245 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8246 memset(&q_params.params.terminate, 0,
8247 sizeof(q_params.params.terminate));
8248 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8249 rc = bnx2x_queue_state_change(bp, &q_params);
8250 if (rc)
523224a3 8251 return rc;
6383c0b3 8252 /* ...delete cfc entry */
619c5cb6 8253 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8254 memset(&q_params.params.cfc_del, 0,
8255 sizeof(q_params.params.cfc_del));
8256 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8257 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8258}
8259
8260
34f80b04
EG		 8261static void bnx2x_reset_func(struct bnx2x *bp)
8262{
8263 int port = BP_PORT(bp);
8264 int func = BP_FUNC(bp);
f2e0899f 8265 int i;
523224a3
DK		 8266
8267 /* Disable the function in the FW */
8268 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8269 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8270 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8271 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8272
8273 /* FP SBs */
ec6ba945 8274 for_each_eth_queue(bp, i) {
523224a3 8275 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8276 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8277 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8278 SB_DISABLED);
523224a3
DK		 8279 }
8280
55c11941
MS		 8281 if (CNIC_LOADED(bp))
8282 /* CNIC SB */
8283 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8284 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8285 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8286
523224a3 8287 /* SP SB */
619c5cb6 8288 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8289 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8290 SB_DISABLED);
523224a3
DK		 8291
8292 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8293 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8294 0);
34f80b04
EG		 8295
8296 /* Configure IGU */
f2e0899f
DK		 8297 if (bp->common.int_block == INT_BLOCK_HC) {
8298 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8299 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8300 } else {
8301 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8302 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8303 }
34f80b04 8304
55c11941
MS		 8305 if (CNIC_LOADED(bp)) {
8306 /* Disable Timer scan */
8307 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8308 /*
8309 * Wait for at least 10ms and up to 2 second for the timers
8310 * scan to complete
8311 */
8312 for (i = 0; i < 200; i++) {
8313 msleep(10);
8314 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8315 break;
8316 }
37b091ba 8317 }
34f80b04 8318 /* Clear ILT */
f2e0899f
DK		 8319 bnx2x_clear_func_ilt(bp, func);
8320
8321 /* Timers workaround bug for E2: if this is vnic-3,
8322 * we need to set the entire ilt range for this timers.
8323 */
619c5cb6 8324 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 8325 struct ilt_client_info ilt_cli;
8326 /* use dummy TM client */
8327 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8328 ilt_cli.start = 0;
8329 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8330 ilt_cli.client_num = ILT_CLIENT_TM;
8331
8332 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8333 }
8334
8335 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 8336 if (!CHIP_IS_E1x(bp))
f2e0899f 8337 bnx2x_pf_disable(bp);
523224a3
DK		 8338
8339 bp->dmae_ready = 0;
34f80b04
EG		 8340}
8341
8342static void bnx2x_reset_port(struct bnx2x *bp)
8343{
8344 int port = BP_PORT(bp);
8345 u32 val;
8346
619c5cb6
VZ		 8347 /* Reset physical Link */
8348 bnx2x__link_reset(bp);
8349
34f80b04
EG		 8350 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8351
8352 /* Do not rcv packets to BRB */
8353 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8354 /* Do not direct rcv packets that are not for MCP to the BRB */
8355 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8356 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8357
8358 /* Configure AEU */
8359 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8360
8361 msleep(100);
8362 /* Check for BRB port occupancy */
8363 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8364 if (val)
8365 DP(NETIF_MSG_IFDOWN,
33471629 8366 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 8367
8368 /* TODO: Close Doorbell port? */
8369}
8370
1191cb83 8371static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 8372{
3b603066 8373 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 8374
619c5cb6
VZ		 8375 /* Prepare parameters for function state transitions */
8376 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 8377
619c5cb6
VZ		 8378 func_params.f_obj = &bp->func_obj;
8379 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 8380
619c5cb6 8381 func_params.params.hw_init.load_phase = load_code;
49d66772 8382
619c5cb6 8383 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 8384}
8385
1191cb83 8386static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 8387{
3b603066 8388 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 8389 int rc;
228241eb 8390
619c5cb6
VZ		 8391 /* Prepare parameters for function state transitions */
8392 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8393 func_params.f_obj = &bp->func_obj;
8394 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 8395
619c5cb6
VZ		 8396 /*
8397 * Try to stop the function the 'good way'. If fails (in case
8398 * of a parity error during bnx2x_chip_cleanup()) and we are
8399 * not in a debug mode, perform a state transaction in order to
8400 * enable further HW_RESET transaction.
8401 */
8402 rc = bnx2x_func_state_change(bp, &func_params);
8403 if (rc) {
34f80b04 8404#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 8405 return rc;
34f80b04 8406#else
51c1a580 8407 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 8408 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8409 return bnx2x_func_state_change(bp, &func_params);
34f80b04 8410#endif
228241eb 8411 }
a2fbb9ea 8412
619c5cb6
VZ		 8413 return 0;
8414}
523224a3 8415
619c5cb6
VZ		 8416/**
8417 * bnx2x_send_unload_req - request unload mode from the MCP.
8418 *
8419 * @bp: driver handle
8420 * @unload_mode: requested function's unload mode
8421 *
8422 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8423 */
8424u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8425{
8426 u32 reset_code = 0;
8427 int port = BP_PORT(bp);
3101c2bc 8428
619c5cb6 8429 /* Select the UNLOAD request mode */
65abd74d
YG		 8430 if (unload_mode == UNLOAD_NORMAL)
8431 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8432
7d0446c2 8433 else if (bp->flags & NO_WOL_FLAG)
65abd74d 8434 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 8435
7d0446c2 8436 else if (bp->wol) {
65abd74d
YG		 8437 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8438 u8 *mac_addr = bp->dev->dev_addr;
8439 u32 val;
f9977903
DK		 8440 u16 pmc;
8441
65abd74d 8442 /* The mac address is written to entries 1-4 to
f9977903
DK		 8443 * preserve entry 0 which is used by the PMF
8444 */
3395a033 8445 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 8446
8447 val = (mac_addr[0] << 8) | mac_addr[1];
8448 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8449
8450 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8451 (mac_addr[4] << 8) | mac_addr[5];
8452 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8453
f9977903
DK		 8454 /* Enable the PME and clear the status */
8455 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8456 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8457 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8458
65abd74d
YG		 8459 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8460
8461 } else
8462 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 8463
619c5cb6
VZ		 8464 /* Send the request to the MCP */
8465 if (!BP_NOMCP(bp))
8466 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8467 else {
8468 int path = BP_PATH(bp);
8469
51c1a580 8470 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
619c5cb6
VZ		 8471 path, load_count[path][0], load_count[path][1],
8472 load_count[path][2]);
8473 load_count[path][0]--;
8474 load_count[path][1 + port]--;
51c1a580 8475 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
619c5cb6
VZ		 8476 path, load_count[path][0], load_count[path][1],
8477 load_count[path][2]);
8478 if (load_count[path][0] == 0)
8479 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8480 else if (load_count[path][1 + port] == 0)
8481 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8482 else
8483 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8484 }
8485
8486 return reset_code;
8487}
8488
8489/**
8490 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8491 *
8492 * @bp: driver handle
5d07d868 8493 * @keep_link: true iff link should be kept up
619c5cb6 8494 */
5d07d868 8495void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 8496{
5d07d868
YM		 8497 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8498
619c5cb6
VZ		 8499 /* Report UNLOAD_DONE to MCP */
8500 if (!BP_NOMCP(bp))
5d07d868 8501 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 8502}
8503
1191cb83 8504static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 8505{
8506 int tout = 50;
8507 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8508
8509 if (!bp->port.pmf)
8510 return 0;
8511
8512 /*
8513 * (assumption: No Attention from MCP at this stage)
8514 * PMF probably in the middle of TXdisable/enable transaction
8515 * 1. Sync IRS for default SB
8516 * 2. Sync SP queue - this guarantes us that attention handling started
8517 * 3. Wait, that TXdisable/enable transaction completes
8518 *
8519 * 1+2 guranty that if DCBx attention was scheduled it already changed
8520 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8521 * received complettion for the transaction the state is TX_STOPPED.
8522 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8523 * transaction.
8524 */
8525
8526 /* make sure default SB ISR is done */
8527 if (msix)
8528 synchronize_irq(bp->msix_table[0].vector);
8529 else
8530 synchronize_irq(bp->pdev->irq);
8531
8532 flush_workqueue(bnx2x_wq);
8533
8534 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8535 BNX2X_F_STATE_STARTED && tout--)
8536 msleep(20);
8537
8538 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8539 BNX2X_F_STATE_STARTED) {
8540#ifdef BNX2X_STOP_ON_ERROR
51c1a580 8541 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 8542 return -EBUSY;
8543#else
8544 /*
8545 * Failed to complete the transaction in a "good way"
8546 * Force both transactions with CLR bit
8547 */
3b603066 8548 struct bnx2x_func_state_params func_params = {NULL};
6debea87 8549
51c1a580
MS		 8550 DP(NETIF_MSG_IFDOWN,
8551 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
6debea87
DK		 8552
8553 func_params.f_obj = &bp->func_obj;
8554 __set_bit(RAMROD_DRV_CLR_ONLY,
8555 &func_params.ramrod_flags);
8556
8557 /* STARTED-->TX_ST0PPED */
8558 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8559 bnx2x_func_state_change(bp, &func_params);
8560
8561 /* TX_ST0PPED-->STARTED */
8562 func_params.cmd = BNX2X_F_CMD_TX_START;
8563 return bnx2x_func_state_change(bp, &func_params);
8564#endif
8565 }
8566
8567 return 0;
8568}
8569
5d07d868 8570void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 8571{
8572 int port = BP_PORT(bp);
6383c0b3
AE		 8573 int i, rc = 0;
8574 u8 cos;
3b603066 8575 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 8576 u32 reset_code;
8577
8578 /* Wait until tx fastpath tasks complete */
8579 for_each_tx_queue(bp, i) {
8580 struct bnx2x_fastpath *fp = &bp->fp[i];
8581
6383c0b3 8582 for_each_cos_in_tx_queue(fp, cos)
65565884 8583 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 8584#ifdef BNX2X_STOP_ON_ERROR
8585 if (rc)
8586 return;
8587#endif
8588 }
8589
8590 /* Give HW time to discard old tx messages */
8591 usleep_range(1000, 1000);
8592
8593 /* Clean all ETH MACs */
15192a8c
BW		 8594 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8595 false);
619c5cb6
VZ		 8596 if (rc < 0)
8597 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8598
8599 /* Clean up UC list */
15192a8c 8600 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 8601 true);
8602 if (rc < 0)
51c1a580
MS		 8603 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8604 rc);
619c5cb6
VZ		 8605
8606 /* Disable LLH */
8607 if (!CHIP_IS_E1(bp))
8608 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8609
8610 /* Set "drop all" (stop Rx).
8611 * We need to take a netif_addr_lock() here in order to prevent
8612 * a race between the completion code and this code.
8613 */
8614 netif_addr_lock_bh(bp->dev);
8615 /* Schedule the rx_mode command */
8616 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8617 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8618 else
8619 bnx2x_set_storm_rx_mode(bp);
8620
8621 /* Cleanup multicast configuration */
8622 rparam.mcast_obj = &bp->mcast_obj;
8623 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8624 if (rc < 0)
8625 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8626
8627 netif_addr_unlock_bh(bp->dev);
8628
8629
6debea87
DK		 8630
8631 /*
8632 * Send the UNLOAD_REQUEST to the MCP. This will return if
8633 * this function should perform FUNC, PORT or COMMON HW
8634 * reset.
8635 */
8636 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8637
8638 /*
8639 * (assumption: No Attention from MCP at this stage)
8640 * PMF probably in the middle of TXdisable/enable transaction
8641 */
8642 rc = bnx2x_func_wait_started(bp);
8643 if (rc) {
8644 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8645#ifdef BNX2X_STOP_ON_ERROR
8646 return;
8647#endif
8648 }
8649
34f80b04 8650 /* Close multi and leading connections
619c5cb6
VZ		 8651 * Completions for ramrods are collected in a synchronous way
8652 */
55c11941 8653 for_each_eth_queue(bp, i)
619c5cb6 8654 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 8655#ifdef BNX2X_STOP_ON_ERROR
8656 return;
8657#else
228241eb 8658 goto unload_error;
523224a3 8659#endif
55c11941
MS		 8660
8661 if (CNIC_LOADED(bp)) {
8662 for_each_cnic_queue(bp, i)
8663 if (bnx2x_stop_queue(bp, i))
8664#ifdef BNX2X_STOP_ON_ERROR
8665 return;
8666#else
8667 goto unload_error;
8668#endif
8669 }
8670
619c5cb6
VZ		 8671 /* If SP settings didn't get completed so far - something
8672 * very wrong has happen.
8673 */
8674 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8675 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 8676
619c5cb6
VZ		 8677#ifndef BNX2X_STOP_ON_ERROR
8678unload_error:
8679#endif
523224a3 8680 rc = bnx2x_func_stop(bp);
da5a662a 8681 if (rc) {
523224a3 8682 BNX2X_ERR("Function stop failed!\n");
da5a662a 8683#ifdef BNX2X_STOP_ON_ERROR
523224a3 8684 return;
523224a3 8685#endif
34f80b04 8686 }
a2fbb9ea 8687
523224a3
DK		 8688 /* Disable HW interrupts, NAPI */
8689 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 8690 /* Delete all NAPI objects */
8691 bnx2x_del_all_napi(bp);
55c11941
MS		 8692 if (CNIC_LOADED(bp))
8693 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 8694
8695 /* Release IRQs */
d6214d7a 8696 bnx2x_free_irq(bp);
523224a3 8697
a2fbb9ea 8698 /* Reset the chip */
619c5cb6
VZ		 8699 rc = bnx2x_reset_hw(bp, reset_code);
8700 if (rc)
8701 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 8702
356e2385 8703
619c5cb6 8704 /* Report UNLOAD_DONE to MCP */
5d07d868 8705 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 8706}
8707
9f6c9258 8708void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 8709{
8710 u32 val;
8711
51c1a580 8712 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 8713
8714 if (CHIP_IS_E1(bp)) {
8715 int port = BP_PORT(bp);
8716 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8717 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8718
8719 val = REG_RD(bp, addr);
8720 val &= ~(0x300);
8721 REG_WR(bp, addr, val);
619c5cb6 8722 } else {
72fd0718
VZ		 8723 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8724 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8725 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8726 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8727 }
8728}
8729
72fd0718
VZ		 8730/* Close gates #2, #3 and #4: */
8731static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8732{
c9ee9206 8733 u32 val;
72fd0718
VZ		 8734
8735 /* Gates #2 and #4a are closed/opened for "not E1" only */
8736 if (!CHIP_IS_E1(bp)) {
8737 /* #4 */
c9ee9206 8738 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 8739 /* #2 */
c9ee9206 8740 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 8741 }
8742
8743 /* #3 */
c9ee9206
VZ		 8744 if (CHIP_IS_E1x(bp)) {
8745 /* Prevent interrupts from HC on both ports */
8746 val = REG_RD(bp, HC_REG_CONFIG_1);
8747 REG_WR(bp, HC_REG_CONFIG_1,
8748 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8749 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8750
8751 val = REG_RD(bp, HC_REG_CONFIG_0);
8752 REG_WR(bp, HC_REG_CONFIG_0,
8753 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8754 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8755 } else {
8756 /* Prevent incomming interrupts in IGU */
8757 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8758
8759 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8760 (!close) ?
8761 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8762 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8763 }
72fd0718 8764
51c1a580 8765 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 8766 close ? "closing" : "opening");
8767 mmiowb();
8768}
8769
8770#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8771
8772static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8773{
8774 /* Do some magic... */
8775 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8776 *magic_val = val & SHARED_MF_CLP_MAGIC;
8777 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8778}
8779
e8920674
DK		 8780/**
8781 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 8782 *
e8920674
DK		 8783 * @bp: driver handle
8784 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 8785 */
8786static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8787{
8788 /* Restore the `magic' bit value... */
72fd0718
VZ		 8789 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8790 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8791 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8792}
8793
f85582f8 8794/**
e8920674 8795 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 8796 *
e8920674
DK		 8797 * @bp: driver handle
8798 * @magic_val: old value of 'magic' bit.
8799 *
8800 * Takes care of CLP configurations.
72fd0718
VZ		 8801 */
8802static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8803{
8804 u32 shmem;
8805 u32 validity_offset;
8806
51c1a580 8807 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 8808
8809 /* Set `magic' bit in order to save MF config */
8810 if (!CHIP_IS_E1(bp))
8811 bnx2x_clp_reset_prep(bp, magic_val);
8812
8813 /* Get shmem offset */
8814 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 8815 validity_offset =
8816 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 8817
8818 /* Clear validity map flags */
8819 if (shmem > 0)
8820 REG_WR(bp, shmem + validity_offset, 0);
8821}
8822
8823#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8824#define MCP_ONE_TIMEOUT 100 /* 100 ms */
8825
e8920674
DK		 8826/**
8827 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 8828 *
e8920674 8829 * @bp: driver handle
72fd0718 8830 */
1191cb83 8831static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 8832{
8833 /* special handling for emulation and FPGA,
8834 wait 10 times longer */
8835 if (CHIP_REV_IS_SLOW(bp))
8836 msleep(MCP_ONE_TIMEOUT*10);
8837 else
8838 msleep(MCP_ONE_TIMEOUT);
8839}
8840
1b6e2ceb
DK		 8841/*
8842 * initializes bp->common.shmem_base and waits for validity signature to appear
8843 */
8844static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 8845{
1b6e2ceb
DK		 8846 int cnt = 0;
8847 u32 val = 0;
72fd0718 8848
1b6e2ceb
DK		 8849 do {
8850 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8851 if (bp->common.shmem_base) {
8852 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8853 if (val & SHR_MEM_VALIDITY_MB)
8854 return 0;
8855 }
72fd0718 8856
1b6e2ceb 8857 bnx2x_mcp_wait_one(bp);
72fd0718 8858
1b6e2ceb 8859 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 8860
1b6e2ceb 8861 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 8862
1b6e2ceb
DK		 8863 return -ENODEV;
8864}
72fd0718 8865
1b6e2ceb
DK		 8866static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8867{
8868 int rc = bnx2x_init_shmem(bp);
72fd0718 8869
72fd0718
VZ		 8870 /* Restore the `magic' bit value */
8871 if (!CHIP_IS_E1(bp))
8872 bnx2x_clp_reset_done(bp, magic_val);
8873
8874 return rc;
8875}
8876
8877static void bnx2x_pxp_prep(struct bnx2x *bp)
8878{
8879 if (!CHIP_IS_E1(bp)) {
8880 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8881 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 8882 mmiowb();
8883 }
8884}
8885
8886/*
8887 * Reset the whole chip except for:
8888 * - PCIE core
8889 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8890 * one reset bit)
8891 * - IGU
8892 * - MISC (including AEU)
8893 * - GRC
8894 * - RBCN, RBCP
8895 */
c9ee9206 8896static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 8897{
8898 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 8899 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 8900
8901 /*
8902 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8903 * (per chip) blocks.
8904 */
8905 global_bits2 =
8906 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8907 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 8908
c55e771b
BW		 8909 /* Don't reset the following blocks.
8910 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
8911 * reset, as in 4 port device they might still be owned
8912 * by the MCP (there is only one leader per path).
8913 */
72fd0718
VZ		 8914 not_reset_mask1 =
8915 MISC_REGISTERS_RESET_REG_1_RST_HC |
8916 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8917 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8918
8919 not_reset_mask2 =
c9ee9206 8920 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 8921 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8922 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8923 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8924 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8925 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8926 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 8927 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8928 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 8929 MISC_REGISTERS_RESET_REG_2_PGLC |
8930 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8931 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8932 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8933 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8934 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8935 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 8936
8736c826
VZ		 8937 /*
8938 * Keep the following blocks in reset:
8939 * - all xxMACs are handled by the bnx2x_link code.
8940 */
8941 stay_reset2 =
8736c826
VZ		 8942 MISC_REGISTERS_RESET_REG_2_XMAC |
8943 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8944
8945 /* Full reset masks according to the chip */
72fd0718
VZ		 8946 reset_mask1 = 0xffffffff;
8947
8948 if (CHIP_IS_E1(bp))
8949 reset_mask2 = 0xffff;
8736c826 8950 else if (CHIP_IS_E1H(bp))
72fd0718 8951 reset_mask2 = 0x1ffff;
8736c826
VZ		 8952 else if (CHIP_IS_E2(bp))
8953 reset_mask2 = 0xfffff;
8954 else /* CHIP_IS_E3 */
8955 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 8956
8957 /* Don't reset global blocks unless we need to */
8958 if (!global)
8959 reset_mask2 &= ~global_bits2;
8960
8961 /*
8962 * In case of attention in the QM, we need to reset PXP
8963 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8964 * because otherwise QM reset would release 'close the gates' shortly
8965 * before resetting the PXP, then the PSWRQ would send a write
8966 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8967 * read the payload data from PSWWR, but PSWWR would not
8968 * respond. The write queue in PGLUE would stuck, dmae commands
8969 * would not return. Therefore it's important to reset the second
8970 * reset register (containing the
8971 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8972 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8973 * bit).
8974 */
72fd0718
VZ		 8975 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8976 reset_mask2 & (~not_reset_mask2));
8977
c9ee9206
VZ		 8978 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8979 reset_mask1 & (~not_reset_mask1));
8980
72fd0718
VZ		 8981 barrier();
8982 mmiowb();
8983
8736c826
VZ		 8984 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8985 reset_mask2 & (~stay_reset2));
8986
8987 barrier();
8988 mmiowb();
8989
c9ee9206 8990 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 8991 mmiowb();
8992}
8993
c9ee9206
VZ		 8994/**
8995 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8996 * It should get cleared in no more than 1s.
8997 *
8998 * @bp: driver handle
8999 *
9000 * It should get cleared in no more than 1s. Returns 0 if
9001 * pending writes bit gets cleared.
9002 */
9003static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9004{
9005 u32 cnt = 1000;
9006 u32 pend_bits = 0;
9007
9008 do {
9009 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9010
9011 if (pend_bits == 0)
9012 break;
9013
9014 usleep_range(1000, 1000);
9015 } while (cnt-- > 0);
9016
9017 if (cnt <= 0) {
9018 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9019 pend_bits);
9020 return -EBUSY;
9021 }
9022
9023 return 0;
9024}
9025
9026static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9027{
9028 int cnt = 1000;
9029 u32 val = 0;
9030 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
c55e771b 9031 u32 tags_63_32 = 0;
72fd0718
VZ		 9032
9033
9034 /* Empty the Tetris buffer, wait for 1s */
9035 do {
9036 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9037 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9038 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9039 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9040 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9041 if (CHIP_IS_E3(bp))
9042 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9043
72fd0718
VZ		 9044 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9045 ((port_is_idle_0 & 0x1) == 0x1) &&
9046 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9047 (pgl_exp_rom2 == 0xffffffff) &&
9048 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9049 break;
c9ee9206 9050 usleep_range(1000, 1000);
72fd0718
VZ		 9051 } while (cnt-- > 0);
9052
9053 if (cnt <= 0) {
51c1a580
MS		 9054 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9055 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9056 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9057 pgl_exp_rom2);
9058 return -EAGAIN;
9059 }
9060
9061 barrier();
9062
9063 /* Close gates #2, #3 and #4 */
9064 bnx2x_set_234_gates(bp, true);
9065
c9ee9206
VZ		 9066 /* Poll for IGU VQs for 57712 and newer chips */
9067 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9068 return -EAGAIN;
9069
9070
72fd0718
VZ		 9071 /* TBD: Indicate that "process kill" is in progress to MCP */
9072
9073 /* Clear "unprepared" bit */
9074 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9075 barrier();
9076
9077 /* Make sure all is written to the chip before the reset */
9078 mmiowb();
9079
9080 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9081 * PSWHST, GRC and PSWRD Tetris buffer.
9082 */
c9ee9206 9083 usleep_range(1000, 1000);
72fd0718
VZ		 9084
9085 /* Prepare to chip reset: */
9086 /* MCP */
c9ee9206
VZ		 9087 if (global)
9088 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9089
9090 /* PXP */
9091 bnx2x_pxp_prep(bp);
9092 barrier();
9093
9094 /* reset the chip */
c9ee9206 9095 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9096 barrier();
9097
9098 /* Recover after reset: */
9099 /* MCP */
c9ee9206 9100 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9101 return -EAGAIN;
9102
c9ee9206
VZ		 9103 /* TBD: Add resetting the NO_MCP mode DB here */
9104
72fd0718
VZ		 9105 /* Open the gates #2, #3 and #4 */
9106 bnx2x_set_234_gates(bp, false);
9107
9108 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9109 * reset state, re-enable attentions. */
9110
a2fbb9ea
ET		 9111 return 0;
9112}
9113
910cc727 9114static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9115{
9116 int rc = 0;
c9ee9206 9117 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9118 u32 load_code;
9119
9120 /* if not going to reset MCP - load "fake" driver to reset HW while
9121 * driver is owner of the HW
9122 */
9123 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9124 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9125 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9126 if (!load_code) {
9127 BNX2X_ERR("MCP response failure, aborting\n");
9128 rc = -EAGAIN;
9129 goto exit_leader_reset;
9130 }
9131 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9132 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9133 BNX2X_ERR("MCP unexpected resp, aborting\n");
9134 rc = -EAGAIN;
9135 goto exit_leader_reset2;
9136 }
9137 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9138 if (!load_code) {
9139 BNX2X_ERR("MCP response failure, aborting\n");
9140 rc = -EAGAIN;
9141 goto exit_leader_reset2;
9142 }
9143 }
c9ee9206 9144
72fd0718 9145 /* Try to recover after the failure */
c9ee9206 9146 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9147 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9148 BP_PATH(bp));
72fd0718 9149 rc = -EAGAIN;
95c6c616 9150 goto exit_leader_reset2;
72fd0718
VZ		 9151 }
9152
c9ee9206
VZ		 9153 /*
9154 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9155 * state.
9156 */
72fd0718 9157 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9158 if (global)
9159 bnx2x_clear_reset_global(bp);
72fd0718 9160
95c6c616
AE		 9161exit_leader_reset2:
9162 /* unload "fake driver" if it was loaded */
9163 if (!global && !BP_NOMCP(bp)) {
9164 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9165 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9166 }
72fd0718
VZ		 9167exit_leader_reset:
9168 bp->is_leader = 0;
c9ee9206
VZ		 9169 bnx2x_release_leader_lock(bp);
9170 smp_mb();
72fd0718
VZ		 9171 return rc;
9172}
9173
1191cb83 9174static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9175{
9176 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9177
9178 /* Disconnect this device */
9179 netif_device_detach(bp->dev);
9180
9181 /*
9182 * Block ifup for all function on this engine until "process kill"
9183 * or power cycle.
9184 */
9185 bnx2x_set_reset_in_progress(bp);
9186
9187 /* Shut down the power */
9188 bnx2x_set_power_state(bp, PCI_D3hot);
9189
9190 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9191
9192 smp_mb();
9193}
9194
9195/*
9196 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9197 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9198 * will never be called when netif_running(bp->dev) is false.
9199 */
9200static void bnx2x_parity_recover(struct bnx2x *bp)
9201{
c9ee9206 9202 bool global = false;
7a752993 9203 u32 error_recovered, error_unrecovered;
95c6c616 9204 bool is_parity;
c9ee9206 9205
72fd0718
VZ		 9206 DP(NETIF_MSG_HW, "Handling parity\n");
9207 while (1) {
9208 switch (bp->recovery_state) {
9209 case BNX2X_RECOVERY_INIT:
9210 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9211 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9212 WARN_ON(!is_parity);
c9ee9206 9213
72fd0718 9214 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9215 if (bnx2x_trylock_leader_lock(bp)) {
9216 bnx2x_set_reset_in_progress(bp);
9217 /*
9218 * Check if there is a global attention and if
9219 * there was a global attention, set the global
9220 * reset bit.
9221 */
9222
9223 if (global)
9224 bnx2x_set_reset_global(bp);
9225
72fd0718 9226 bp->is_leader = 1;
c9ee9206 9227 }
72fd0718
VZ		 9228
9229 /* Stop the driver */
9230 /* If interface has been removed - break */
5d07d868 9231 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 9232 return;
9233
9234 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 9235
c9ee9206
VZ		 9236 /* Ensure "is_leader", MCP command sequence and
9237 * "recovery_state" update values are seen on other
9238 * CPUs.
72fd0718 9239 */
c9ee9206 9240 smp_mb();
72fd0718
VZ		 9241 break;
9242
9243 case BNX2X_RECOVERY_WAIT:
9244 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9245 if (bp->is_leader) {
c9ee9206 9246 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 9247 bool other_load_status =
9248 bnx2x_get_load_status(bp, other_engine);
9249 bool load_status =
9250 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 9251 global = bnx2x_reset_is_global(bp);
9252
9253 /*
9254 * In case of a parity in a global block, let
9255 * the first leader that performs a
9256 * leader_reset() reset the global blocks in
9257 * order to clear global attentions. Otherwise
9258 * the the gates will remain closed for that
9259 * engine.
9260 */
889b9af3
AE		 9261 if (load_status ||
9262 (global && other_load_status)) {
72fd0718
VZ		 9263 /* Wait until all other functions get
9264 * down.
9265 */
7be08a72 9266 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9267 HZ/10);
9268 return;
9269 } else {
9270 /* If all other functions got down -
9271 * try to bring the chip back to
9272 * normal. In any case it's an exit
9273 * point for a leader.
9274 */
c9ee9206
VZ		 9275 if (bnx2x_leader_reset(bp)) {
9276 bnx2x_recovery_failed(bp);
72fd0718
VZ		 9277 return;
9278 }
9279
c9ee9206
VZ		 9280 /* If we are here, means that the
9281 * leader has succeeded and doesn't
9282 * want to be a leader any more. Try
9283 * to continue as a none-leader.
9284 */
9285 break;
72fd0718
VZ		 9286 }
9287 } else { /* non-leader */
c9ee9206 9288 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 9289 /* Try to get a LEADER_LOCK HW lock as
9290 * long as a former leader may have
9291 * been unloaded by the user or
9292 * released a leadership by another
9293 * reason.
9294 */
c9ee9206 9295 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 9296 /* I'm a leader now! Restart a
9297 * switch case.
9298 */
9299 bp->is_leader = 1;
9300 break;
9301 }
9302
7be08a72 9303 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 9304 HZ/10);
9305 return;
9306
c9ee9206
VZ		 9307 } else {
9308 /*
9309 * If there was a global attention, wait
9310 * for it to be cleared.
9311 */
9312 if (bnx2x_reset_is_global(bp)) {
9313 schedule_delayed_work(
7be08a72
AE		 9314 &bp->sp_rtnl_task,
9315 HZ/10);
c9ee9206
VZ		 9316 return;
9317 }
9318
7a752993
AE		 9319 error_recovered =
9320 bp->eth_stats.recoverable_error;
9321 error_unrecovered =
9322 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 9323 bp->recovery_state =
9324 BNX2X_RECOVERY_NIC_LOADING;
9325 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 9326 error_unrecovered++;
95c6c616 9327 netdev_err(bp->dev,
51c1a580 9328 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 9329 /* Disconnect this device */
9330 netif_device_detach(bp->dev);
9331 /* Shut down the power */
9332 bnx2x_set_power_state(
9333 bp, PCI_D3hot);
9334 smp_mb();
9335 } else {
c9ee9206
VZ		 9336 bp->recovery_state =
9337 BNX2X_RECOVERY_DONE;
7a752993 9338 error_recovered++;
c9ee9206
VZ		 9339 smp_mb();
9340 }
7a752993
AE		 9341 bp->eth_stats.recoverable_error =
9342 error_recovered;
9343 bp->eth_stats.unrecoverable_error =
9344 error_unrecovered;
c9ee9206 9345
72fd0718
VZ		 9346 return;
9347 }
9348 }
9349 default:
9350 return;
9351 }
9352 }
9353}
9354
56ad3152
MS		 9355static int bnx2x_close(struct net_device *dev);
9356
72fd0718
VZ		 9357/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9358 * scheduled on a general queue in order to prevent a dead lock.
9359 */
7be08a72 9360static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 9361{
7be08a72 9362 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 9363
9364 rtnl_lock();
9365
9366 if (!netif_running(bp->dev))
7be08a72
AE		 9367 goto sp_rtnl_exit;
9368
9369 /* if stop on error is defined no recovery flows should be executed */
9370#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9371 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
7be08a72 9372 "you will need to reboot when done\n");
b1fb8740 9373 goto sp_rtnl_not_reset;
7be08a72 9374#endif
34f80b04 9375
7be08a72
AE		 9376 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9377 /*
b1fb8740
VZ		 9378 * Clear all pending SP commands as we are going to reset the
9379 * function anyway.
7be08a72 9380 */
b1fb8740
VZ		 9381 bp->sp_rtnl_state = 0;
9382 smp_mb();
9383
72fd0718 9384 bnx2x_parity_recover(bp);
b1fb8740
VZ		 9385
9386 goto sp_rtnl_exit;
9387 }
9388
9389 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9390 /*
9391 * Clear all pending SP commands as we are going to reset the
9392 * function anyway.
9393 */
9394 bp->sp_rtnl_state = 0;
9395 smp_mb();
9396
5d07d868 9397 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
72fd0718 9398 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740
VZ		 9399
9400 goto sp_rtnl_exit;
72fd0718 9401 }
b1fb8740
VZ		 9402#ifdef BNX2X_STOP_ON_ERROR
9403sp_rtnl_not_reset:
9404#endif
9405 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9406 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 9407 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9408 bnx2x_after_function_update(bp);
8304859a
AE		 9409 /*
9410 * in case of fan failure we need to reset id if the "stop on error"
9411 * debug flag is set, since we trying to prevent permanent overheating
9412 * damage
9413 */
9414 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 9415 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 9416 netif_device_detach(bp->dev);
9417 bnx2x_close(bp->dev);
9418 }
9419
381ac16b
AE		 9420 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9421 DP(BNX2X_MSG_SP,
9422 "sending set mcast vf pf channel message from rtnl sp-task\n");
9423 bnx2x_vfpf_set_mcast(bp->dev);
9424 }
9425
9426 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9427 &bp->sp_rtnl_state)) {
9428 DP(BNX2X_MSG_SP,
9429 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9430 bnx2x_vfpf_storm_rx_mode(bp);
9431 }
9432
7be08a72 9433sp_rtnl_exit:
34f80b04
EG		 9434 rtnl_unlock();
9435}
9436
a2fbb9ea
ET		 9437/* end of nic load/unload */
9438
3deb8167
YR		 9439static void bnx2x_period_task(struct work_struct *work)
9440{
9441 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9442
9443 if (!netif_running(bp->dev))
9444 goto period_task_exit;
9445
9446 if (CHIP_REV_IS_SLOW(bp)) {
9447 BNX2X_ERR("period task called on emulation, ignoring\n");
9448 goto period_task_exit;
9449 }
9450
9451 bnx2x_acquire_phy_lock(bp);
9452 /*
9453 * The barrier is needed to ensure the ordering between the writing to
9454 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9455 * the reading here.
9456 */
9457 smp_mb();
9458 if (bp->port.pmf) {
9459 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9460
9461 /* Re-queue task in 1 sec */
9462 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9463 }
9464
9465 bnx2x_release_phy_lock(bp);
9466period_task_exit:
9467 return;
9468}
9469
a2fbb9ea
ET		 9470/*
9471 * Init service functions
9472 */
9473
b56e9670 9474u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 9475{
9476 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9477 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9478 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 9479}
9480
f2e0899f 9481static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 9482{
f2e0899f 9483 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 9484
9485 /* Flush all outstanding writes */
9486 mmiowb();
9487
9488 /* Pretend to be function 0 */
9489 REG_WR(bp, reg, 0);
f2e0899f 9490 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 9491
9492 /* From now we are in the "like-E1" mode */
9493 bnx2x_int_disable(bp);
9494
9495 /* Flush all outstanding writes */
9496 mmiowb();
9497
f2e0899f
DK		 9498 /* Restore the original function */
9499 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9500 REG_RD(bp, reg);
f1ef27ef
EG		 9501}
9502
f2e0899f 9503static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 9504{
f2e0899f 9505 if (CHIP_IS_E1(bp))
f1ef27ef 9506 bnx2x_int_disable(bp);
f2e0899f
DK		 9507 else
9508 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 9509}
9510
0329aba1 9511static void bnx2x_prev_unload_close_mac(struct bnx2x *bp)
34f80b04 9512{
452427b0
YM		 9513 u32 val, base_addr, offset, mask, reset_reg;
9514 bool mac_stopped = false;
9515 u8 port = BP_PORT(bp);
34f80b04 9516
452427b0 9517 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 9518
452427b0
YM		 9519 if (!CHIP_IS_E3(bp)) {
9520 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9521 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9522 if ((mask & reset_reg) && val) {
9523 u32 wb_data[2];
9524 BNX2X_DEV_INFO("Disable bmac Rx\n");
9525 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9526 : NIG_REG_INGRESS_BMAC0_MEM;
9527 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9528 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 9529
452427b0
YM		 9530 /*
9531 * use rd/wr since we cannot use dmae. This is safe
9532 * since MCP won't access the bus due to the request
9533 * to unload, and no function on the path can be
9534 * loaded at this time.
9535 */
9536 wb_data[0] = REG_RD(bp, base_addr + offset);
9537 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9538 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9539 REG_WR(bp, base_addr + offset, wb_data[0]);
9540 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9541
9542 }
9543 BNX2X_DEV_INFO("Disable emac Rx\n");
9544 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9545
9546 mac_stopped = true;
9547 } else {
9548 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9549 BNX2X_DEV_INFO("Disable xmac Rx\n");
9550 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9551 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9552 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9553 val & ~(1 << 1));
9554 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9555 val | (1 << 1));
9556 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9557 mac_stopped = true;
9558 }
9559 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9560 if (mask & reset_reg) {
9561 BNX2X_DEV_INFO("Disable umac Rx\n");
9562 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9563 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9564 mac_stopped = true;
9565 }
9566 }
9567
9568 if (mac_stopped)
9569 msleep(20);
9570
9571}
9572
9573#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9574#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9575#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9576#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9577
1dd06ae8 9578static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
452427b0
YM		 9579{
9580 u16 rcq, bd;
9581 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9582
9583 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9584 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9585
9586 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9587 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9588
9589 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9590 port, bd, rcq);
9591}
9592
0329aba1 9593static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 9594{
5d07d868
YM		 9595 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9596 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 9597 if (!rc) {
9598 BNX2X_ERR("MCP response failure, aborting\n");
9599 return -EBUSY;
9600 }
9601
9602 return 0;
9603}
9604
c63da990
BW		 9605static struct bnx2x_prev_path_list *
9606 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9607{
9608 struct bnx2x_prev_path_list *tmp_list;
9609
9610 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9611 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9612 bp->pdev->bus->number == tmp_list->bus &&
9613 BP_PATH(bp) == tmp_list->path)
9614 return tmp_list;
9615
9616 return NULL;
9617}
9618
0329aba1 9619static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 9620{
9621 struct bnx2x_prev_path_list *tmp_list;
9622 int rc = false;
9623
9624 if (down_trylock(&bnx2x_prev_sem))
9625 return false;
9626
9627 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9628 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9629 bp->pdev->bus->number == tmp_list->bus &&
9630 BP_PATH(bp) == tmp_list->path) {
9631 rc = true;
9632 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9633 BP_PATH(bp));
9634 break;
9635 }
9636 }
9637
9638 up(&bnx2x_prev_sem);
9639
9640 return rc;
9641}
9642
c63da990 9643static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 9644{
9645 struct bnx2x_prev_path_list *tmp_list;
9646 int rc;
9647
ea4b3857 9648 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 9649 if (!tmp_list) {
9650 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9651 return -ENOMEM;
9652 }
9653
9654 tmp_list->bus = bp->pdev->bus->number;
9655 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9656 tmp_list->path = BP_PATH(bp);
c63da990 9657 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 9658
9659 rc = down_interruptible(&bnx2x_prev_sem);
9660 if (rc) {
9661 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9662 kfree(tmp_list);
9663 } else {
9664 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9665 BP_PATH(bp));
9666 list_add(&tmp_list->list, &bnx2x_prev_list);
9667 up(&bnx2x_prev_sem);
9668 }
9669
9670 return rc;
9671}
9672
0329aba1 9673static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 9674{
2a80eebc 9675 int i;
452427b0
YM		 9676 u16 status;
9677 struct pci_dev *dev = bp->pdev;
9678
8eee694c
YM		 9679
9680 if (CHIP_IS_E1x(bp)) {
9681 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9682 return -EINVAL;
9683 }
9684
9685 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9686 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9687 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9688 bp->common.bc_ver);
9689 return -EINVAL;
9690 }
452427b0 9691
452427b0
YM		 9692 /* Wait for Transaction Pending bit clean */
9693 for (i = 0; i < 4; i++) {
9694 if (i)
9695 msleep((1 << (i - 1)) * 100);
9696
2a80eebc 9697 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
452427b0
YM		 9698 if (!(status & PCI_EXP_DEVSTA_TRPND))
9699 goto clear;
9700 }
9701
9702 dev_err(&dev->dev,
9703 "transaction is not cleared; proceeding with reset anyway\n");
9704
9705clear:
452427b0 9706
8eee694c 9707 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 9708 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9709
9710 return 0;
9711}
9712
0329aba1 9713static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 9714{
9715 int rc;
9716
9717 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9718
9719 /* Test if previous unload process was already finished for this path */
9720 if (bnx2x_prev_is_path_marked(bp))
9721 return bnx2x_prev_mcp_done(bp);
9722
9723 /* If function has FLR capabilities, and existing FW version matches
9724 * the one required, then FLR will be sufficient to clean any residue
9725 * left by previous driver
9726 */
ad5afc89 9727 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
8eee694c
YM		 9728
9729 if (!rc) {
9730 /* fw version is good */
9731 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9732 rc = bnx2x_do_flr(bp);
9733 }
9734
9735 if (!rc) {
9736 /* FLR was performed */
9737 BNX2X_DEV_INFO("FLR successful\n");
9738 return 0;
9739 }
9740
9741 BNX2X_DEV_INFO("Could not FLR\n");
452427b0
YM		 9742
9743 /* Close the MCP request, return failure*/
9744 rc = bnx2x_prev_mcp_done(bp);
9745 if (!rc)
9746 rc = BNX2X_PREV_WAIT_NEEDED;
9747
9748 return rc;
9749}
9750
0329aba1 9751static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 9752{
9753 u32 reset_reg, tmp_reg = 0, rc;
c63da990 9754 bool prev_undi = false;
452427b0
YM		 9755 /* It is possible a previous function received 'common' answer,
9756 * but hasn't loaded yet, therefore creating a scenario of
9757 * multiple functions receiving 'common' on the same path.
9758 */
9759 BNX2X_DEV_INFO("Common unload Flow\n");
9760
9761 if (bnx2x_prev_is_path_marked(bp))
9762 return bnx2x_prev_mcp_done(bp);
9763
9764 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9765
9766 /* Reset should be performed after BRB is emptied */
9767 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9768 u32 timer_count = 1000;
452427b0
YM		 9769
9770 /* Close the MAC Rx to prevent BRB from filling up */
9771 bnx2x_prev_unload_close_mac(bp);
9772
9773 /* Check if the UNDI driver was previously loaded
34f80b04
EG		 9774 * UNDI driver initializes CID offset for normal bell to 0x7
9775 */
452427b0
YM		 9776 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9777 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9778 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9779 if (tmp_reg == 0x7) {
9780 BNX2X_DEV_INFO("UNDI previously loaded\n");
9781 prev_undi = true;
9782 /* clear the UNDI indication */
9783 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
34f80b04 9784 }
452427b0
YM		 9785 }
9786 /* wait until BRB is empty */
9787 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9788 while (timer_count) {
9789 u32 prev_brb = tmp_reg;
34f80b04 9790
452427b0
YM		 9791 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9792 if (!tmp_reg)
9793 break;
619c5cb6 9794
452427b0 9795 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 9796
452427b0
YM		 9797 /* reset timer as long as BRB actually gets emptied */
9798 if (prev_brb > tmp_reg)
9799 timer_count = 1000;
9800 else
9801 timer_count--;
da5a662a 9802
452427b0
YM		 9803 /* If UNDI resides in memory, manually increment it */
9804 if (prev_undi)
9805 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
da5a662a 9806
452427b0 9807 udelay(10);
7a06a122 9808 }
452427b0
YM		 9809
9810 if (!timer_count)
9811 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9812
34f80b04 9813 }
f16da43b 9814
452427b0
YM		 9815 /* No packets are in the pipeline, path is ready for reset */
9816 bnx2x_reset_common(bp);
9817
c63da990 9818 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 9819 if (rc) {
9820 bnx2x_prev_mcp_done(bp);
9821 return rc;
9822 }
9823
9824 return bnx2x_prev_mcp_done(bp);
9825}
9826
24f06716
AE		 9827/* previous driver DMAE transaction may have occurred when pre-boot stage ended
9828 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9829 * the addresses of the transaction, resulting in was-error bit set in the pci
9830 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9831 * to clear the interrupt which detected this from the pglueb and the was done
9832 * bit
9833 */
0329aba1 9834static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
24f06716 9835{
4a25417c
AE		 9836 if (!CHIP_IS_E1x(bp)) {
9837 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9838 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9839 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9840 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9841 1 << BP_FUNC(bp));
9842 }
24f06716
AE		 9843 }
9844}
9845
0329aba1 9846static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 9847{
9848 int time_counter = 10;
9849 u32 rc, fw, hw_lock_reg, hw_lock_val;
c63da990 9850 struct bnx2x_prev_path_list *prev_list;
452427b0
YM		 9851 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9852
24f06716
AE		 9853 /* clear hw from errors which may have resulted from an interrupted
9854 * dmae transaction.
9855 */
9856 bnx2x_prev_interrupted_dmae(bp);
9857
9858 /* Release previously held locks */
452427b0
YM		 9859 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9860 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9861 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9862
9863 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9864 if (hw_lock_val) {
9865 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9866 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9867 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9868 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9869 }
9870
9871 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9872 REG_WR(bp, hw_lock_reg, 0xffffffff);
9873 } else
9874 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9875
9876 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9877 BNX2X_DEV_INFO("Release previously held alr\n");
9878 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9879 }
9880
9881
9882 do {
9883 /* Lock MCP using an unload request */
9884 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9885 if (!fw) {
9886 BNX2X_ERR("MCP response failure, aborting\n");
9887 rc = -EBUSY;
9888 break;
9889 }
9890
9891 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9892 rc = bnx2x_prev_unload_common(bp);
9893 break;
9894 }
9895
9896 /* non-common reply from MCP night require looping */
9897 rc = bnx2x_prev_unload_uncommon(bp);
9898 if (rc != BNX2X_PREV_WAIT_NEEDED)
9899 break;
9900
9901 msleep(20);
9902 } while (--time_counter);
9903
9904 if (!time_counter || rc) {
9905 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9906 rc = -EBUSY;
9907 }
9908
c63da990
BW		 9909 /* Mark function if its port was used to boot from SAN */
9910 prev_list = bnx2x_prev_path_get_entry(bp);
9911 if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
9912 bp->link_params.feature_config_flags |=
9913 FEATURE_CONFIG_BOOT_FROM_SAN;
9914
452427b0
YM		 9915 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9916
9917 return rc;
34f80b04
EG		 9918}
9919
0329aba1 9920static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 9921{
1d187b34 9922 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 9923 u16 pmc;
34f80b04
EG		 9924
9925 /* Get the chip revision id and number. */
9926 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9927 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9928 id = ((val & 0xffff) << 16);
9929 val = REG_RD(bp, MISC_REG_CHIP_REV);
9930 id |= ((val & 0xf) << 12);
9931 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9932 id |= ((val & 0xff) << 4);
5a40e08e 9933 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 9934 id |= (val & 0xf);
9935 bp->common.chip_id = id;
523224a3 9936
7e8e02df
BW		 9937 /* force 57811 according to MISC register */
9938 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9939 if (CHIP_IS_57810(bp))
9940 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9941 (bp->common.chip_id & 0x0000FFFF);
9942 else if (CHIP_IS_57810_MF(bp))
9943 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9944 (bp->common.chip_id & 0x0000FFFF);
9945 bp->common.chip_id |= 0x1;
9946 }
9947
523224a3
DK		 9948 /* Set doorbell size */
9949 bp->db_size = (1 << BNX2X_DB_SHIFT);
9950
619c5cb6 9951 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 9952 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9953 if ((val & 1) == 0)
9954 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9955 else
9956 val = (val >> 1) & 1;
9957 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9958 "2_PORT_MODE");
9959 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9960 CHIP_2_PORT_MODE;
9961
9962 if (CHIP_MODE_IS_4_PORT(bp))
9963 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9964 else
9965 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9966 } else {
9967 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9968 bp->pfid = bp->pf_num; /* 0..7 */
9969 }
9970
51c1a580
MS		 9971 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9972
f2e0899f
DK		 9973 bp->link_params.chip_id = bp->common.chip_id;
9974 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 9975
1c06328c
EG		 9976 val = (REG_RD(bp, 0x2874) & 0x55);
9977 if ((bp->common.chip_id & 0x1) ||
9978 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9979 bp->flags |= ONE_PORT_FLAG;
9980 BNX2X_DEV_INFO("single port device\n");
9981 }
9982
34f80b04 9983 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 9984 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 9985 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9986 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9987 bp->common.flash_size, bp->common.flash_size);
9988
1b6e2ceb
DK		 9989 bnx2x_init_shmem(bp);
9990
619c5cb6
VZ		 9991
9992
f2e0899f
DK		 9993 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9994 MISC_REG_GENERIC_CR_1 :
9995 MISC_REG_GENERIC_CR_0));
1b6e2ceb 9996
34f80b04 9997 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 9998 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 9999 if (SHMEM2_RD(bp, size) >
10000 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10001 bp->link_params.lfa_base =
10002 REG_RD(bp, bp->common.shmem2_base +
10003 (u32)offsetof(struct shmem2_region,
10004 lfa_host_addr[BP_PORT(bp)]));
10005 else
10006 bp->link_params.lfa_base = 0;
2691d51d
EG		 10007 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10008 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 10009
f2e0899f 10010 if (!bp->common.shmem_base) {
34f80b04
EG		 10011 BNX2X_DEV_INFO("MCP not active\n");
10012 bp->flags |= NO_MCP_FLAG;
10013 return;
10014 }
10015
34f80b04 10016 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 10017 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 10018
10019 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10020 SHARED_HW_CFG_LED_MODE_MASK) >>
10021 SHARED_HW_CFG_LED_MODE_SHIFT);
10022
c2c8b03e
EG		 10023 bp->link_params.feature_config_flags = 0;
10024 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10025 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10026 bp->link_params.feature_config_flags |=
10027 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10028 else
10029 bp->link_params.feature_config_flags &=
10030 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10031
34f80b04
EG		 10032 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10033 bp->common.bc_ver = val;
10034 BNX2X_DEV_INFO("bc_ver %X\n", val);
10035 if (val < BNX2X_BC_VER) {
10036 /* for now only warn
10037 * later we might need to enforce this */
51c1a580
MS		 10038 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10039 BNX2X_BC_VER, val);
34f80b04 10040 }
4d295db0 10041 bp->link_params.feature_config_flags |=
a22f0788 10042 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 10043 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10044
a22f0788
YR		 10045 bp->link_params.feature_config_flags |=
10046 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10047 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 10048 bp->link_params.feature_config_flags |=
10049 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10050 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 10051 bp->link_params.feature_config_flags |=
10052 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10053 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 10054
10055 bp->link_params.feature_config_flags |=
10056 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10057 FEATURE_CONFIG_MT_SUPPORT : 0;
10058
0e898dd7
BW		 10059 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10060 BC_SUPPORTS_PFC_STATS : 0;
85242eea 10061
2e499d3c
BW		 10062 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10063 BC_SUPPORTS_FCOE_FEATURES : 0;
10064
9876879f
BW		 10065 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10066 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
1d187b34
BW		 10067 boot_mode = SHMEM_RD(bp,
10068 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10069 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10070 switch (boot_mode) {
10071 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10072 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10073 break;
10074 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10075 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10076 break;
10077 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10078 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10079 break;
10080 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10081 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10082 break;
10083 }
10084
f9a3ebbe
DK		 10085 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10086 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10087
72ce58c3 10088 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 10089 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 10090
10091 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10092 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10093 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10094 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10095
cdaa7cb8
VZ		 10096 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10097 val, val2, val3, val4);
34f80b04
EG		 10098}
10099
f2e0899f
DK		 10100#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10101#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10102
0329aba1 10103static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 10104{
10105 int pfid = BP_FUNC(bp);
f2e0899f
DK		 10106 int igu_sb_id;
10107 u32 val;
6383c0b3 10108 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 10109
10110 bp->igu_base_sb = 0xff;
f2e0899f 10111 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 10112 int vn = BP_VN(bp);
6383c0b3 10113 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 10114 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10115 FP_SB_MAX_E1x;
10116
10117 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10118 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10119
9b341bb1 10120 return 0;
f2e0899f
DK		 10121 }
10122
10123 /* IGU in normal mode - read CAM */
10124 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10125 igu_sb_id++) {
10126 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10127 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10128 continue;
10129 fid = IGU_FID(val);
10130 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10131 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10132 continue;
10133 if (IGU_VEC(val) == 0)
10134 /* default status block */
10135 bp->igu_dsb_id = igu_sb_id;
10136 else {
10137 if (bp->igu_base_sb == 0xff)
10138 bp->igu_base_sb = igu_sb_id;
6383c0b3 10139 igu_sb_cnt++;
f2e0899f
DK		 10140 }
10141 }
10142 }
619c5cb6 10143
6383c0b3 10144#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 10145 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10146 * optional that number of CAM entries will not be equal to the value
10147 * advertised in PCI.
10148 * Driver should use the minimal value of both as the actual status
10149 * block count
619c5cb6 10150 */
185d4c8b 10151 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 10152#endif
619c5cb6 10153
9b341bb1 10154 if (igu_sb_cnt == 0) {
f2e0899f 10155 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 10156 return -EINVAL;
10157 }
10158
10159 return 0;
f2e0899f
DK		 10160}
10161
1dd06ae8 10162static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 10163{
a22f0788
YR		 10164 int cfg_size = 0, idx, port = BP_PORT(bp);
10165
10166 /* Aggregation of supported attributes of all external phys */
10167 bp->port.supported[0] = 0;
10168 bp->port.supported[1] = 0;
b7737c9b
YR		 10169 switch (bp->link_params.num_phys) {
10170 case 1:
a22f0788
YR		 10171 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10172 cfg_size = 1;
10173 break;
b7737c9b 10174 case 2:
a22f0788
YR		 10175 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10176 cfg_size = 1;
10177 break;
10178 case 3:
10179 if (bp->link_params.multi_phy_config &
10180 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10181 bp->port.supported[1] =
10182 bp->link_params.phy[EXT_PHY1].supported;
10183 bp->port.supported[0] =
10184 bp->link_params.phy[EXT_PHY2].supported;
10185 } else {
10186 bp->port.supported[0] =
10187 bp->link_params.phy[EXT_PHY1].supported;
10188 bp->port.supported[1] =
10189 bp->link_params.phy[EXT_PHY2].supported;
10190 }
10191 cfg_size = 2;
10192 break;
b7737c9b 10193 }
a2fbb9ea 10194
a22f0788 10195 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 10196 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 10197 SHMEM_RD(bp,
a22f0788
YR		 10198 dev_info.port_hw_config[port].external_phy_config),
10199 SHMEM_RD(bp,
10200 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 10201 return;
f85582f8 10202 }
a2fbb9ea 10203
619c5cb6
VZ		 10204 if (CHIP_IS_E3(bp))
10205 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10206 else {
10207 switch (switch_cfg) {
10208 case SWITCH_CFG_1G:
10209 bp->port.phy_addr = REG_RD(
10210 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10211 break;
10212 case SWITCH_CFG_10G:
10213 bp->port.phy_addr = REG_RD(
10214 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10215 break;
10216 default:
10217 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10218 bp->port.link_config[0]);
10219 return;
10220 }
a2fbb9ea 10221 }
619c5cb6 10222 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 10223 /* mask what we support according to speed_cap_mask per configuration */
10224 for (idx = 0; idx < cfg_size; idx++) {
10225 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10226 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 10227 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 10228
a22f0788 10229 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10230 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 10231 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 10232
a22f0788 10233 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10234 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 10235 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 10236
a22f0788 10237 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10238 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 10239 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 10240
a22f0788 10241 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10242 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 10243 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 10244 SUPPORTED_1000baseT_Full);
a2fbb9ea 10245
a22f0788 10246 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10247 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 10248 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 10249
a22f0788 10250 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 10251 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 10252 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10253
10254 }
a2fbb9ea 10255
a22f0788
YR		 10256 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10257 bp->port.supported[1]);
a2fbb9ea
ET		 10258}
10259
0329aba1 10260static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 10261{
a22f0788
YR		 10262 u32 link_config, idx, cfg_size = 0;
10263 bp->port.advertising[0] = 0;
10264 bp->port.advertising[1] = 0;
10265 switch (bp->link_params.num_phys) {
10266 case 1:
10267 case 2:
10268 cfg_size = 1;
10269 break;
10270 case 3:
10271 cfg_size = 2;
10272 break;
10273 }
10274 for (idx = 0; idx < cfg_size; idx++) {
10275 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10276 link_config = bp->port.link_config[idx];
10277 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 10278 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 10279 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10280 bp->link_params.req_line_speed[idx] =
10281 SPEED_AUTO_NEG;
10282 bp->port.advertising[idx] |=
10283 bp->port.supported[idx];
10bd1f24
MY		 10284 if (bp->link_params.phy[EXT_PHY1].type ==
10285 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10286 bp->port.advertising[idx] |=
10287 (SUPPORTED_100baseT_Half |
10288 SUPPORTED_100baseT_Full);
f85582f8
DK		 10289 } else {
10290 /* force 10G, no AN */
a22f0788
YR		 10291 bp->link_params.req_line_speed[idx] =
10292 SPEED_10000;
10293 bp->port.advertising[idx] |=
10294 (ADVERTISED_10000baseT_Full |
f85582f8 10295 ADVERTISED_FIBRE);
a22f0788 10296 continue;
f85582f8
DK		 10297 }
10298 break;
a2fbb9ea 10299
f85582f8 10300 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 10301 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10302 bp->link_params.req_line_speed[idx] =
10303 SPEED_10;
10304 bp->port.advertising[idx] |=
10305 (ADVERTISED_10baseT_Full |
f85582f8
DK		 10306 ADVERTISED_TP);
10307 } else {
51c1a580 10308 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 10309 link_config,
a22f0788 10310 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10311 return;
10312 }
10313 break;
a2fbb9ea 10314
f85582f8 10315 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 10316 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10317 bp->link_params.req_line_speed[idx] =
10318 SPEED_10;
10319 bp->link_params.req_duplex[idx] =
10320 DUPLEX_HALF;
10321 bp->port.advertising[idx] |=
10322 (ADVERTISED_10baseT_Half |
f85582f8
DK		 10323 ADVERTISED_TP);
10324 } else {
51c1a580 10325 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10326 link_config,
10327 bp->link_params.speed_cap_mask[idx]);
10328 return;
10329 }
10330 break;
a2fbb9ea 10331
f85582f8
DK		 10332 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10333 if (bp->port.supported[idx] &
10334 SUPPORTED_100baseT_Full) {
a22f0788
YR		 10335 bp->link_params.req_line_speed[idx] =
10336 SPEED_100;
10337 bp->port.advertising[idx] |=
10338 (ADVERTISED_100baseT_Full |
f85582f8
DK		 10339 ADVERTISED_TP);
10340 } else {
51c1a580 10341 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 10342 link_config,
10343 bp->link_params.speed_cap_mask[idx]);
10344 return;
10345 }
10346 break;
a2fbb9ea 10347
f85582f8
DK		 10348 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10349 if (bp->port.supported[idx] &
10350 SUPPORTED_100baseT_Half) {
10351 bp->link_params.req_line_speed[idx] =
10352 SPEED_100;
10353 bp->link_params.req_duplex[idx] =
10354 DUPLEX_HALF;
a22f0788
YR		 10355 bp->port.advertising[idx] |=
10356 (ADVERTISED_100baseT_Half |
f85582f8
DK		 10357 ADVERTISED_TP);
10358 } else {
51c1a580 10359 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 10360 link_config,
10361 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10362 return;
10363 }
10364 break;
a2fbb9ea 10365
f85582f8 10366 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 10367 if (bp->port.supported[idx] &
10368 SUPPORTED_1000baseT_Full) {
10369 bp->link_params.req_line_speed[idx] =
10370 SPEED_1000;
10371 bp->port.advertising[idx] |=
10372 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 10373 ADVERTISED_TP);
10374 } else {
51c1a580 10375 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 10376 link_config,
10377 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 10378 return;
10379 }
10380 break;
a2fbb9ea 10381
f85582f8 10382 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 10383 if (bp->port.supported[idx] &
10384 SUPPORTED_2500baseX_Full) {
10385 bp->link_params.req_line_speed[idx] =
10386 SPEED_2500;
10387 bp->port.advertising[idx] |=
10388 (ADVERTISED_2500baseX_Full |
34f80b04 10389 ADVERTISED_TP);
f85582f8 10390 } else {
51c1a580 10391 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 10392 link_config,
f85582f8
DK		 10393 bp->link_params.speed_cap_mask[idx]);
10394 return;
10395 }
10396 break;
a2fbb9ea 10397
f85582f8 10398 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 10399 if (bp->port.supported[idx] &
10400 SUPPORTED_10000baseT_Full) {
10401 bp->link_params.req_line_speed[idx] =
10402 SPEED_10000;
10403 bp->port.advertising[idx] |=
10404 (ADVERTISED_10000baseT_Full |
34f80b04 10405 ADVERTISED_FIBRE);
f85582f8 10406 } else {
51c1a580 10407 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 10408 link_config,
f85582f8
DK		 10409 bp->link_params.speed_cap_mask[idx]);
10410 return;
10411 }
10412 break;
3c9ada22
YR		 10413 case PORT_FEATURE_LINK_SPEED_20G:
10414 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 10415
3c9ada22 10416 break;
f85582f8 10417 default:
51c1a580 10418 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 10419 link_config);
f85582f8
DK		 10420 bp->link_params.req_line_speed[idx] =
10421 SPEED_AUTO_NEG;
10422 bp->port.advertising[idx] =
10423 bp->port.supported[idx];
10424 break;
10425 }
a2fbb9ea 10426
a22f0788 10427 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 10428 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 10429 if (bp->link_params.req_flow_ctrl[idx] ==
10430 BNX2X_FLOW_CTRL_AUTO) {
10431 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10432 bp->link_params.req_flow_ctrl[idx] =
10433 BNX2X_FLOW_CTRL_NONE;
10434 else
10435 bnx2x_set_requested_fc(bp);
a22f0788 10436 }
a2fbb9ea 10437
51c1a580 10438 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 10439 bp->link_params.req_line_speed[idx],
10440 bp->link_params.req_duplex[idx],
10441 bp->link_params.req_flow_ctrl[idx],
10442 bp->port.advertising[idx]);
10443 }
a2fbb9ea
ET		 10444}
10445
0329aba1 10446static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda
MC		 10447{
10448 mac_hi = cpu_to_be16(mac_hi);
10449 mac_lo = cpu_to_be32(mac_lo);
10450 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10451 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10452}
10453
0329aba1 10454static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 10455{
34f80b04 10456 int port = BP_PORT(bp);
589abe3a 10457 u32 config;
c8c60d88 10458 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 10459
c18487ee 10460 bp->link_params.bp = bp;
34f80b04 10461 bp->link_params.port = port;
c18487ee 10462
c18487ee 10463 bp->link_params.lane_config =
a2fbb9ea 10464 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 10465
a22f0788 10466 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 10467 SHMEM_RD(bp,
10468 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 10469 bp->link_params.speed_cap_mask[1] =
10470 SHMEM_RD(bp,
10471 dev_info.port_hw_config[port].speed_capability_mask2);
10472 bp->port.link_config[0] =
a2fbb9ea
ET		 10473 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10474
a22f0788
YR		 10475 bp->port.link_config[1] =
10476 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 10477
a22f0788
YR		 10478 bp->link_params.multi_phy_config =
10479 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 10480 /* If the device is capable of WoL, set the default state according
10481 * to the HW
10482 */
4d295db0 10483 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 10484 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10485 (config & PORT_FEATURE_WOL_ENABLED));
10486
51c1a580 10487 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 10488 bp->link_params.lane_config,
a22f0788
YR		 10489 bp->link_params.speed_cap_mask[0],
10490 bp->port.link_config[0]);
a2fbb9ea 10491
a22f0788 10492 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 10493 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 10494 bnx2x_phy_probe(&bp->link_params);
c18487ee 10495 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 10496
10497 bnx2x_link_settings_requested(bp);
10498
01cd4528
EG		 10499 /*
10500 * If connected directly, work with the internal PHY, otherwise, work
10501 * with the external PHY
10502 */
b7737c9b
YR		 10503 ext_phy_config =
10504 SHMEM_RD(bp,
10505 dev_info.port_hw_config[port].external_phy_config);
10506 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 10507 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 10508 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 10509
10510 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10511 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10512 bp->mdio.prtad =
b7737c9b 10513 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 10514
c8c60d88
YM		 10515 /* Configure link feature according to nvram value */
10516 eee_mode = (((SHMEM_RD(bp, dev_info.
10517 port_feature_config[port].eee_power_mode)) &
10518 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10519 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10520 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10521 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10522 EEE_MODE_ENABLE_LPI |
10523 EEE_MODE_OUTPUT_TIME;
10524 } else {
10525 bp->link_params.eee_mode = 0;
10526 }
0793f83f 10527}
01cd4528 10528
b306f5ed 10529void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 10530{
9e62e912 10531 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 10532 int port = BP_PORT(bp);
2ba45142 10533 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 10534 drv_lic_key[port].max_iscsi_conn);
2ba45142 10535
55c11941
MS		 10536 if (!CNIC_SUPPORT(bp)) {
10537 bp->flags |= no_flags;
10538 return;
10539 }
10540
b306f5ed 10541 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 10542 bp->cnic_eth_dev.max_iscsi_conn =
10543 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10544 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10545
b306f5ed
DK		 10546 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10547 bp->cnic_eth_dev.max_iscsi_conn);
10548
10549 /*
10550 * If maximum allowed number of connections is zero -
10551 * disable the feature.
10552 */
10553 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 10554 bp->flags |= no_flags;
55c11941 10555
b306f5ed
DK		 10556}
10557
0329aba1 10558static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 10559{
10560 /* Port info */
10561 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10562 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10563 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10564 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10565
10566 /* Node info */
10567 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10568 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10569 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10570 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10571}
0329aba1 10572static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 10573{
10574 int port = BP_PORT(bp);
10575 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 10576 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10577 drv_lic_key[port].max_fcoe_conn);
10578
55c11941
MS		 10579 if (!CNIC_SUPPORT(bp)) {
10580 bp->flags |= NO_FCOE_FLAG;
10581 return;
10582 }
10583
b306f5ed 10584 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 10585 bp->cnic_eth_dev.max_fcoe_conn =
10586 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10587 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10588
bf61ee14
VZ		 10589 /* Read the WWN: */
10590 if (!IS_MF(bp)) {
10591 /* Port info */
10592 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10593 SHMEM_RD(bp,
10594 dev_info.port_hw_config[port].
10595 fcoe_wwn_port_name_upper);
10596 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10597 SHMEM_RD(bp,
10598 dev_info.port_hw_config[port].
10599 fcoe_wwn_port_name_lower);
10600
10601 /* Node info */
10602 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10603 SHMEM_RD(bp,
10604 dev_info.port_hw_config[port].
10605 fcoe_wwn_node_name_upper);
10606 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10607 SHMEM_RD(bp,
10608 dev_info.port_hw_config[port].
10609 fcoe_wwn_node_name_lower);
10610 } else if (!IS_MF_SD(bp)) {
bf61ee14
VZ		 10611 /*
10612 * Read the WWN info only if the FCoE feature is enabled for
10613 * this function.
10614 */
7b5342d9 10615 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912
DK		 10616 bnx2x_get_ext_wwn_info(bp, func);
10617
382e513a 10618 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
9e62e912 10619 bnx2x_get_ext_wwn_info(bp, func);
382e513a 10620 }
bf61ee14 10621
b306f5ed 10622 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 10623
bf61ee14
VZ		 10624 /*
10625 * If maximum allowed number of connections is zero -
2ba45142
VZ		 10626 * disable the feature.
10627 */
2ba45142
VZ		 10628 if (!bp->cnic_eth_dev.max_fcoe_conn)
10629 bp->flags |= NO_FCOE_FLAG;
10630}
b306f5ed 10631
0329aba1 10632static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 10633{
10634 /*
10635 * iSCSI may be dynamically disabled but reading
10636 * info here we will decrease memory usage by driver
10637 * if the feature is disabled for good
10638 */
10639 bnx2x_get_iscsi_info(bp);
10640 bnx2x_get_fcoe_info(bp);
10641}
2ba45142 10642
0329aba1 10643static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 10644{
10645 u32 val, val2;
10646 int func = BP_ABS_FUNC(bp);
10647 int port = BP_PORT(bp);
2ba45142
VZ		 10648 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10649 u8 *fip_mac = bp->fip_mac;
0793f83f 10650
55c11941
MS		 10651 if (IS_MF(bp)) {
10652 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 10653 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 10654 * In non SD mode features configuration comes from struct
10655 * func_ext_config.
2ba45142 10656 */
55c11941 10657 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
0793f83f
DK		 10658 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10659 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10660 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 10661 iscsi_mac_addr_upper);
0793f83f 10662 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 10663 iscsi_mac_addr_lower);
2ba45142 10664 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 10665 BNX2X_DEV_INFO
10666 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10667 } else {
2ba45142 10668 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 10669 }
2ba45142
VZ		 10670
10671 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10672 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 10673 fcoe_mac_addr_upper);
2ba45142 10674 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 10675 fcoe_mac_addr_lower);
2ba45142 10676 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 10677 BNX2X_DEV_INFO
10678 ("Read FCoE L2 MAC: %pM\n", fip_mac);
10679 } else {
2ba45142 10680 bp->flags |= NO_FCOE_FLAG;
55c11941 10681 }
a3348722
BW		 10682
10683 bp->mf_ext_config = cfg;
10684
9e62e912 10685 } else { /* SD MODE */
55c11941
MS		 10686 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10687 /* use primary mac as iscsi mac */
10688 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10689
10690 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10691 BNX2X_DEV_INFO
10692 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10693 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10694 /* use primary mac as fip mac */
10695 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10696 BNX2X_DEV_INFO("SD FCoE MODE\n");
10697 BNX2X_DEV_INFO
10698 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 10699 }
0793f83f 10700 }
a3348722 10701
55c11941
MS		 10702 if (IS_MF_STORAGE_SD(bp))
10703 /* Zero primary MAC configuration */
10704 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10705
a3348722
BW		 10706 if (IS_MF_FCOE_AFEX(bp))
10707 /* use FIP MAC as primary MAC */
10708 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10709
0793f83f 10710 } else {
0793f83f 10711 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 10712 iscsi_mac_upper);
0793f83f 10713 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 10714 iscsi_mac_lower);
2ba45142 10715 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 10716
10717 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 10718 fcoe_fip_mac_upper);
c03bd39c 10719 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 10720 fcoe_fip_mac_lower);
c03bd39c 10721 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 10722 }
10723
55c11941 10724 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 10725 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 10726 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
426b9241
DK		 10727 memset(iscsi_mac, 0, ETH_ALEN);
10728 }
10729
55c11941 10730 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 10731 if (!is_valid_ether_addr(fip_mac)) {
10732 bp->flags |= NO_FCOE_FLAG;
10733 memset(bp->fip_mac, 0, ETH_ALEN);
10734 }
55c11941
MS		 10735}
10736
0329aba1 10737static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 10738{
10739 u32 val, val2;
10740 int func = BP_ABS_FUNC(bp);
10741 int port = BP_PORT(bp);
10742
10743 /* Zero primary MAC configuration */
10744 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10745
10746 if (BP_NOMCP(bp)) {
10747 BNX2X_ERROR("warning: random MAC workaround active\n");
10748 eth_hw_addr_random(bp->dev);
10749 } else if (IS_MF(bp)) {
10750 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10751 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10752 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10753 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10754 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10755
10756 if (CNIC_SUPPORT(bp))
10757 bnx2x_get_cnic_mac_hwinfo(bp);
10758 } else {
10759 /* in SF read MACs from port configuration */
10760 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10761 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10762 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10763
10764 if (CNIC_SUPPORT(bp))
10765 bnx2x_get_cnic_mac_hwinfo(bp);
10766 }
10767
10768 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10769 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 10770
614c76df 10771 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6 10772 dev_err(&bp->pdev->dev,
51c1a580
MS		 10773 "bad Ethernet MAC address configuration: %pM\n"
10774 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 10775 bp->dev->dev_addr);
7964211d 10776}
51c1a580 10777
0329aba1 10778static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 10779{
10780 int tmp;
10781 u32 cfg;
51c1a580 10782
7964211d
YM		 10783 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10784 /* Take function: tmp = func */
10785 tmp = BP_ABS_FUNC(bp);
10786 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10787 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10788 } else {
10789 /* Take port: tmp = port */
10790 tmp = BP_PORT(bp);
10791 cfg = SHMEM_RD(bp,
10792 dev_info.port_hw_config[tmp].generic_features);
10793 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10794 }
10795 return cfg;
34f80b04
EG		 10796}
10797
0329aba1 10798static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 10799{
0793f83f 10800 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 10801 int vn;
0793f83f 10802 u32 val = 0;
34f80b04 10803 int rc = 0;
a2fbb9ea 10804
34f80b04 10805 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 10806
6383c0b3
AE		 10807 /*
10808 * initialize IGU parameters
10809 */
f2e0899f
DK		 10810 if (CHIP_IS_E1x(bp)) {
10811 bp->common.int_block = INT_BLOCK_HC;
10812
10813 bp->igu_dsb_id = DEF_SB_IGU_ID;
10814 bp->igu_base_sb = 0;
f2e0899f
DK		 10815 } else {
10816 bp->common.int_block = INT_BLOCK_IGU;
7a06a122
DK		 10817
10818 /* do not allow device reset during IGU info preocessing */
10819 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10820
f2e0899f 10821 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 10822
10823 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10824 int tout = 5000;
10825
10826 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10827
10828 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10829 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10830 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10831
10832 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10833 tout--;
10834 usleep_range(1000, 1000);
10835 }
10836
10837 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10838 dev_err(&bp->pdev->dev,
10839 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 10840 bnx2x_release_hw_lock(bp,
10841 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 10842 return -EPERM;
10843 }
10844 }
10845
f2e0899f 10846 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 10847 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 10848 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10849 } else
619c5cb6 10850 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 10851
9b341bb1 10852 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 10853 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 10854 if (rc)
10855 return rc;
f2e0899f 10856 }
619c5cb6
VZ		 10857
10858 /*
10859 * set base FW non-default (fast path) status block id, this value is
10860 * used to initialize the fw_sb_id saved on the fp/queue structure to
10861 * determine the id used by the FW.
10862 */
10863 if (CHIP_IS_E1x(bp))
10864 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10865 else /*
10866 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10867 * the same queue are indicated on the same IGU SB). So we prefer
10868 * FW and IGU SBs to be the same value.
10869 */
10870 bp->base_fw_ndsb = bp->igu_base_sb;
10871
10872 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10873 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10874 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 10875
10876 /*
10877 * Initialize MF configuration
10878 */
523224a3 10879
fb3bff17
DK		 10880 bp->mf_ov = 0;
10881 bp->mf_mode = 0;
3395a033 10882 vn = BP_VN(bp);
0793f83f 10883
f2e0899f 10884 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 10885 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10886 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10887 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10888
f2e0899f
DK		 10889 if (SHMEM2_HAS(bp, mf_cfg_addr))
10890 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10891 else
10892 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 10893 offsetof(struct shmem_region, func_mb) +
10894 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 10895 /*
10896 * get mf configuration:
25985edc 10897 * 1. existence of MF configuration
0793f83f
DK		 10898 * 2. MAC address must be legal (check only upper bytes)
10899 * for Switch-Independent mode;
10900 * OVLAN must be legal for Switch-Dependent mode
10901 * 3. SF_MODE configures specific MF mode
10902 */
10903 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10904 /* get mf configuration */
10905 val = SHMEM_RD(bp,
10906 dev_info.shared_feature_config.config);
10907 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10908
10909 switch (val) {
10910 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10911 val = MF_CFG_RD(bp, func_mf_config[func].
10912 mac_upper);
10913 /* check for legal mac (upper bytes)*/
10914 if (val != 0xffff) {
10915 bp->mf_mode = MULTI_FUNCTION_SI;
10916 bp->mf_config[vn] = MF_CFG_RD(bp,
10917 func_mf_config[func].config);
10918 } else
51c1a580 10919 BNX2X_DEV_INFO("illegal MAC address for SI\n");
0793f83f 10920 break;
a3348722
BW		 10921 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10922 if ((!CHIP_IS_E1x(bp)) &&
10923 (MF_CFG_RD(bp, func_mf_config[func].
10924 mac_upper) != 0xffff) &&
10925 (SHMEM2_HAS(bp,
10926 afex_driver_support))) {
10927 bp->mf_mode = MULTI_FUNCTION_AFEX;
10928 bp->mf_config[vn] = MF_CFG_RD(bp,
10929 func_mf_config[func].config);
10930 } else {
10931 BNX2X_DEV_INFO("can not configure afex mode\n");
10932 }
10933 break;
0793f83f
DK		 10934 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10935 /* get OV configuration */
10936 val = MF_CFG_RD(bp,
10937 func_mf_config[FUNC_0].e1hov_tag);
10938 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10939
10940 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10941 bp->mf_mode = MULTI_FUNCTION_SD;
10942 bp->mf_config[vn] = MF_CFG_RD(bp,
10943 func_mf_config[func].config);
10944 } else
754a2f52 10945 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 10946 break;
10947 default:
10948 /* Unknown configuration: reset mf_config */
10949 bp->mf_config[vn] = 0;
51c1a580 10950 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 10951 }
10952 }
a2fbb9ea 10953
2691d51d 10954 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 10955 IS_MF(bp) ? "multi" : "single");
2691d51d 10956
0793f83f
DK		 10957 switch (bp->mf_mode) {
10958 case MULTI_FUNCTION_SD:
10959 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10960 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 10961 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 10962 bp->mf_ov = val;
619c5cb6
VZ		 10963 bp->path_has_ovlan = true;
10964
51c1a580
MS		 10965 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10966 func, bp->mf_ov, bp->mf_ov);
2691d51d 10967 } else {
619c5cb6 10968 dev_err(&bp->pdev->dev,
51c1a580
MS		 10969 "No valid MF OV for func %d, aborting\n",
10970 func);
619c5cb6 10971 return -EPERM;
34f80b04 10972 }
0793f83f 10973 break;
a3348722
BW		 10974 case MULTI_FUNCTION_AFEX:
10975 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10976 break;
0793f83f 10977 case MULTI_FUNCTION_SI:
51c1a580
MS		 10978 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10979 func);
0793f83f
DK		 10980 break;
10981 default:
10982 if (vn) {
619c5cb6 10983 dev_err(&bp->pdev->dev,
51c1a580
MS		 10984 "VN %d is in a single function mode, aborting\n",
10985 vn);
619c5cb6 10986 return -EPERM;
2691d51d 10987 }
0793f83f 10988 break;
34f80b04 10989 }
0793f83f 10990
619c5cb6
VZ		 10991 /* check if other port on the path needs ovlan:
10992 * Since MF configuration is shared between ports
10993 * Possible mixed modes are only
10994 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10995 */
10996 if (CHIP_MODE_IS_4_PORT(bp) &&
10997 !bp->path_has_ovlan &&
10998 !IS_MF(bp) &&
10999 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11000 u8 other_port = !BP_PORT(bp);
11001 u8 other_func = BP_PATH(bp) + 2*other_port;
11002 val = MF_CFG_RD(bp,
11003 func_mf_config[other_func].e1hov_tag);
11004 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11005 bp->path_has_ovlan = true;
11006 }
34f80b04 11007 }
a2fbb9ea 11008
f2e0899f
DK		 11009 /* adjust igu_sb_cnt to MF for E1x */
11010 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 11011 bp->igu_sb_cnt /= E1HVN_MAX;
11012
619c5cb6
VZ		 11013 /* port info */
11014 bnx2x_get_port_hwinfo(bp);
f2e0899f 11015
0793f83f
DK		 11016 /* Get MAC addresses */
11017 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 11018
2ba45142 11019 bnx2x_get_cnic_info(bp);
2ba45142 11020
34f80b04
EG		 11021 return rc;
11022}
11023
0329aba1 11024static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 11025{
11026 int cnt, i, block_end, rodi;
fcdf95cb 11027 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 11028 char str_id_reg[VENDOR_ID_LEN+1];
11029 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 11030 char *vpd_data;
11031 char *vpd_extended_data = NULL;
34f24c7f
VZ		 11032 u8 len;
11033
fcdf95cb 11034 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 11035 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11036
11037 if (cnt < BNX2X_VPD_LEN)
11038 goto out_not_found;
11039
fcdf95cb
BW		 11040 /* VPD RO tag should be first tag after identifier string, hence
11041 * we should be able to find it in first BNX2X_VPD_LEN chars
11042 */
11043 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 11044 PCI_VPD_LRDT_RO_DATA);
11045 if (i < 0)
11046 goto out_not_found;
11047
34f24c7f 11048 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 11049 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 11050
11051 i += PCI_VPD_LRDT_TAG_SIZE;
11052
fcdf95cb
BW		 11053 if (block_end > BNX2X_VPD_LEN) {
11054 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11055 if (vpd_extended_data == NULL)
11056 goto out_not_found;
11057
11058 /* read rest of vpd image into vpd_extended_data */
11059 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11060 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11061 block_end - BNX2X_VPD_LEN,
11062 vpd_extended_data + BNX2X_VPD_LEN);
11063 if (cnt < (block_end - BNX2X_VPD_LEN))
11064 goto out_not_found;
11065 vpd_data = vpd_extended_data;
11066 } else
11067 vpd_data = vpd_start;
11068
11069 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 11070
11071 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11072 PCI_VPD_RO_KEYWORD_MFR_ID);
11073 if (rodi < 0)
11074 goto out_not_found;
11075
11076 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11077
11078 if (len != VENDOR_ID_LEN)
11079 goto out_not_found;
11080
11081 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11082
11083 /* vendor specific info */
11084 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11085 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11086 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11087 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11088
11089 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11090 PCI_VPD_RO_KEYWORD_VENDOR0);
11091 if (rodi >= 0) {
11092 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11093
11094 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11095
11096 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11097 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11098 bp->fw_ver[len] = ' ';
11099 }
11100 }
fcdf95cb 11101 kfree(vpd_extended_data);
34f24c7f
VZ		 11102 return;
11103 }
11104out_not_found:
fcdf95cb 11105 kfree(vpd_extended_data);
34f24c7f
VZ		 11106 return;
11107}
11108
0329aba1 11109static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 11110{
11111 u32 flags = 0;
11112
11113 if (CHIP_REV_IS_FPGA(bp))
11114 SET_FLAGS(flags, MODE_FPGA);
11115 else if (CHIP_REV_IS_EMUL(bp))
11116 SET_FLAGS(flags, MODE_EMUL);
11117 else
11118 SET_FLAGS(flags, MODE_ASIC);
11119
11120 if (CHIP_MODE_IS_4_PORT(bp))
11121 SET_FLAGS(flags, MODE_PORT4);
11122 else
11123 SET_FLAGS(flags, MODE_PORT2);
11124
11125 if (CHIP_IS_E2(bp))
11126 SET_FLAGS(flags, MODE_E2);
11127 else if (CHIP_IS_E3(bp)) {
11128 SET_FLAGS(flags, MODE_E3);
11129 if (CHIP_REV(bp) == CHIP_REV_Ax)
11130 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 11131 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11132 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 11133 }
11134
11135 if (IS_MF(bp)) {
11136 SET_FLAGS(flags, MODE_MF);
11137 switch (bp->mf_mode) {
11138 case MULTI_FUNCTION_SD:
11139 SET_FLAGS(flags, MODE_MF_SD);
11140 break;
11141 case MULTI_FUNCTION_SI:
11142 SET_FLAGS(flags, MODE_MF_SI);
11143 break;
a3348722
BW		 11144 case MULTI_FUNCTION_AFEX:
11145 SET_FLAGS(flags, MODE_MF_AFEX);
11146 break;
619c5cb6
VZ		 11147 }
11148 } else
11149 SET_FLAGS(flags, MODE_SF);
11150
11151#if defined(__LITTLE_ENDIAN)
11152 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11153#else /*(__BIG_ENDIAN)*/
11154 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11155#endif
11156 INIT_MODE_FLAGS(bp) = flags;
11157}
11158
0329aba1 11159static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 11160{
f2e0899f 11161 int func;
34f80b04
EG		 11162 int rc;
11163
34f80b04 11164 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 11165 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 11166 spin_lock_init(&bp->stats_lock);
55c11941 11167
a2fbb9ea 11168
1cf167f2 11169 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 11170 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 11171 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
1ab4434c
AE		 11172 if (IS_PF(bp)) {
11173 rc = bnx2x_get_hwinfo(bp);
11174 if (rc)
11175 return rc;
11176 } else {
11177 random_ether_addr(bp->dev->dev_addr);
11178 }
34f80b04 11179
619c5cb6
VZ		 11180 bnx2x_set_modes_bitmap(bp);
11181
11182 rc = bnx2x_alloc_mem_bp(bp);
11183 if (rc)
11184 return rc;
523224a3 11185
34f24c7f 11186 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 11187
11188 func = BP_FUNC(bp);
11189
34f80b04 11190 /* need to reset chip if undi was active */
1ab4434c 11191 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 11192 /* init fw_seq */
11193 bp->fw_seq =
11194 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11195 DRV_MSG_SEQ_NUMBER_MASK;
11196 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11197
11198 bnx2x_prev_unload(bp);
11199 }
11200
34f80b04
EG		 11201
11202 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 11203 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 11204
11205 if (BP_NOMCP(bp) && (func == 0))
51c1a580 11206 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 11207
614c76df 11208 bp->disable_tpa = disable_tpa;
a3348722 11209 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
614c76df 11210
7a9b2557 11211 /* Set TPA flags */
614c76df 11212 if (bp->disable_tpa) {
621b4d66 11213 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11214 bp->dev->features &= ~NETIF_F_LRO;
11215 } else {
621b4d66 11216 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
7a9b2557
VZ		 11217 bp->dev->features |= NETIF_F_LRO;
11218 }
11219
a18f5128
EG		 11220 if (CHIP_IS_E1(bp))
11221 bp->dropless_fc = 0;
11222 else
7964211d 11223 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 11224
8d5726c4 11225 bp->mrrs = mrrs;
7a9b2557 11226
a3348722 11227 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 11228 if (IS_VF(bp))
11229 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 11230
7d323bfd 11231 /* make sure that the numbers are in the right granularity */
523224a3
DK		 11232 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11233 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 11234
fc543637 11235 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04
EG		 11236
11237 init_timer(&bp->timer);
11238 bp->timer.expires = jiffies + bp->current_interval;
11239 bp->timer.data = (unsigned long) bp;
11240 bp->timer.function = bnx2x_timer;
11241
0370cf90
BW		 11242 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11243 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11244 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11245 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11246 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11247 bnx2x_dcbx_init_params(bp);
11248 } else {
11249 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11250 }
e4901dde 11251
619c5cb6
VZ		 11252 if (CHIP_IS_E1x(bp))
11253 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11254 else
11255 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 11256
6383c0b3 11257 /* multiple tx priority */
1ab4434c
AE		 11258 if (IS_VF(bp))
11259 bp->max_cos = 1;
11260 else if (CHIP_IS_E1x(bp))
6383c0b3 11261 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 11262 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 11263 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 11264 else if (CHIP_IS_E3B0(bp))
6383c0b3 11265 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 11266 else
11267 BNX2X_ERR("unknown chip %x revision %x\n",
11268 CHIP_NUM(bp), CHIP_REV(bp));
11269 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 11270
55c11941
MS		 11271 /* We need at least one default status block for slow-path events,
11272 * second status block for the L2 queue, and a third status block for
11273 * CNIC if supproted.
11274 */
11275 if (CNIC_SUPPORT(bp))
11276 bp->min_msix_vec_cnt = 3;
11277 else
11278 bp->min_msix_vec_cnt = 2;
11279 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11280
34f80b04 11281 return rc;
a2fbb9ea
ET		 11282}
11283
a2fbb9ea 11284
de0c62db
DK		 11285/****************************************************************************
11286* General service functions
11287****************************************************************************/
a2fbb9ea 11288
619c5cb6
VZ		 11289/*
11290 * net_device service functions
11291 */
11292
bb2a0f7a 11293/* called with rtnl_lock */
a2fbb9ea
ET		 11294static int bnx2x_open(struct net_device *dev)
11295{
11296 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 11297 bool global = false;
11298 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3 11299 bool other_load_status, load_status;
a2fbb9ea 11300
1355b704
MY		 11301 bp->stats_init = true;
11302
6eccabb3
EG		 11303 netif_carrier_off(dev);
11304
a2fbb9ea
ET		 11305 bnx2x_set_power_state(bp, PCI_D0);
11306
ad5afc89 11307 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 11308 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11309 * want the first function loaded on the current engine to
11310 * complete the recovery.
ad5afc89 11311 * Parity recovery is only relevant for PF driver.
c9ee9206 11312 */
ad5afc89
AE		 11313 if (IS_PF(bp)) {
11314 other_load_status = bnx2x_get_load_status(bp, other_engine);
11315 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11316 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11317 bnx2x_chk_parity_attn(bp, &global, true)) {
11318 do {
11319 /* If there are attentions and they are in a
11320 * global blocks, set the GLOBAL_RESET bit
11321 * regardless whether it will be this function
11322 * that will complete the recovery or not.
11323 */
11324 if (global)
11325 bnx2x_set_reset_global(bp);
72fd0718 11326
ad5afc89
AE		 11327 /* Only the first function on the current
11328 * engine should try to recover in open. In case
11329 * of attentions in global blocks only the first
11330 * in the chip should try to recover.
11331 */
11332 if ((!load_status &&
11333 (!global || !other_load_status)) &&
11334 bnx2x_trylock_leader_lock(bp) &&
11335 !bnx2x_leader_reset(bp)) {
11336 netdev_info(bp->dev,
11337 "Recovered in open\n");
11338 break;
11339 }
72fd0718 11340
ad5afc89
AE		 11341 /* recovery has failed... */
11342 bnx2x_set_power_state(bp, PCI_D3hot);
11343 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 11344
ad5afc89
AE		 11345 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11346 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 11347
ad5afc89
AE		 11348 return -EAGAIN;
11349 } while (0);
11350 }
11351 }
72fd0718
VZ		 11352
11353 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 11354 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 11355}
11356
bb2a0f7a 11357/* called with rtnl_lock */
56ad3152 11358static int bnx2x_close(struct net_device *dev)
a2fbb9ea 11359{
a2fbb9ea
ET		 11360 struct bnx2x *bp = netdev_priv(dev);
11361
11362 /* Unload the driver, release IRQs */
5d07d868 11363 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206
VZ		 11364
11365 /* Power off */
d3dbfee0 11366 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 11367
11368 return 0;
11369}
11370
1191cb83
ED		 11371static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11372 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 11373{
619c5cb6
VZ		 11374 int mc_count = netdev_mc_count(bp->dev);
11375 struct bnx2x_mcast_list_elem *mc_mac =
11376 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11377 struct netdev_hw_addr *ha;
6e30dd4e 11378
619c5cb6
VZ		 11379 if (!mc_mac)
11380 return -ENOMEM;
6e30dd4e 11381
619c5cb6 11382 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 11383
619c5cb6
VZ		 11384 netdev_for_each_mc_addr(ha, bp->dev) {
11385 mc_mac->mac = bnx2x_mc_addr(ha);
11386 list_add_tail(&mc_mac->link, &p->mcast_list);
11387 mc_mac++;
6e30dd4e 11388 }
619c5cb6
VZ		 11389
11390 p->mcast_list_len = mc_count;
11391
11392 return 0;
6e30dd4e
VZ		 11393}
11394
1191cb83 11395static void bnx2x_free_mcast_macs_list(
619c5cb6
VZ		 11396 struct bnx2x_mcast_ramrod_params *p)
11397{
11398 struct bnx2x_mcast_list_elem *mc_mac =
11399 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11400 link);
11401
11402 WARN_ON(!mc_mac);
11403 kfree(mc_mac);
11404}
11405
11406/**
11407 * bnx2x_set_uc_list - configure a new unicast MACs list.
11408 *
11409 * @bp: driver handle
6e30dd4e 11410 *
619c5cb6 11411 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 11412 */
1191cb83 11413static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 11414{
619c5cb6 11415 int rc;
6e30dd4e 11416 struct net_device *dev = bp->dev;
6e30dd4e 11417 struct netdev_hw_addr *ha;
15192a8c 11418 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 11419 unsigned long ramrod_flags = 0;
6e30dd4e 11420
619c5cb6
VZ		 11421 /* First schedule a cleanup up of old configuration */
11422 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11423 if (rc < 0) {
11424 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11425 return rc;
11426 }
6e30dd4e
VZ		 11427
11428 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 11429 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11430 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 11431 if (rc == -EEXIST) {
11432 DP(BNX2X_MSG_SP,
11433 "Failed to schedule ADD operations: %d\n", rc);
11434 /* do not treat adding same MAC as error */
11435 rc = 0;
11436
11437 } else if (rc < 0) {
11438
619c5cb6
VZ		 11439 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11440 rc);
11441 return rc;
6e30dd4e
VZ		 11442 }
11443 }
11444
619c5cb6
VZ		 11445 /* Execute the pending commands */
11446 __set_bit(RAMROD_CONT, &ramrod_flags);
11447 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11448 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 11449}
11450
1191cb83 11451static int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 11452{
619c5cb6 11453 struct net_device *dev = bp->dev;
3b603066 11454 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 11455 int rc = 0;
6e30dd4e 11456
619c5cb6 11457 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 11458
619c5cb6
VZ		 11459 /* first, clear all configured multicast MACs */
11460 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11461 if (rc < 0) {
51c1a580 11462 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 11463 return rc;
11464 }
6e30dd4e 11465
619c5cb6
VZ		 11466 /* then, configure a new MACs list */
11467 if (netdev_mc_count(dev)) {
11468 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11469 if (rc) {
51c1a580
MS		 11470 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11471 rc);
619c5cb6
VZ		 11472 return rc;
11473 }
6e30dd4e 11474
619c5cb6
VZ		 11475 /* Now add the new MACs */
11476 rc = bnx2x_config_mcast(bp, &rparam,
11477 BNX2X_MCAST_CMD_ADD);
11478 if (rc < 0)
51c1a580
MS		 11479 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11480 rc);
6e30dd4e 11481
619c5cb6
VZ		 11482 bnx2x_free_mcast_macs_list(&rparam);
11483 }
6e30dd4e 11484
619c5cb6 11485 return rc;
6e30dd4e
VZ		 11486}
11487
6e30dd4e 11488
619c5cb6 11489/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 11490void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 11491{
11492 struct bnx2x *bp = netdev_priv(dev);
11493 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 11494
11495 if (bp->state != BNX2X_STATE_OPEN) {
11496 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11497 return;
11498 }
11499
619c5cb6 11500 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 11501
11502 if (dev->flags & IFF_PROMISC)
11503 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 11504 else if ((dev->flags & IFF_ALLMULTI) ||
11505 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11506 CHIP_IS_E1(bp)))
34f80b04 11507 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e 11508 else {
381ac16b
AE		 11509 if (IS_PF(bp)) {
11510 /* some multicasts */
11511 if (bnx2x_set_mc_list(bp) < 0)
11512 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 11513
381ac16b
AE		 11514 if (bnx2x_set_uc_list(bp) < 0)
11515 rx_mode = BNX2X_RX_MODE_PROMISC;
11516 } else {
11517 /* configuring mcast to a vf involves sleeping (when we
11518 * wait for the pf's response). Since this function is
11519 * called from non sleepable context we must schedule
11520 * a work item for this purpose
11521 */
11522 smp_mb__before_clear_bit();
11523 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11524 &bp->sp_rtnl_state);
11525 smp_mb__after_clear_bit();
11526 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11527 }
34f80b04
EG		 11528 }
11529
11530 bp->rx_mode = rx_mode;
614c76df
DK		 11531 /* handle ISCSI SD mode */
11532 if (IS_MF_ISCSI_SD(bp))
11533 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 11534
11535 /* Schedule the rx_mode command */
11536 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11537 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11538 return;
11539 }
11540
381ac16b
AE		 11541 if (IS_PF(bp)) {
11542 bnx2x_set_storm_rx_mode(bp);
11543 } else {
11544 /* configuring rx mode to storms in a vf involves sleeping (when
11545 * we wait for the pf's response). Since this function is
11546 * called from non sleepable context we must schedule
11547 * a work item for this purpose
11548 */
11549 smp_mb__before_clear_bit();
11550 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11551 &bp->sp_rtnl_state);
11552 smp_mb__after_clear_bit();
11553 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11554 }
34f80b04
EG		 11555}
11556
c18487ee 11557/* called with rtnl_lock */
01cd4528
EG		 11558static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11559 int devad, u16 addr)
a2fbb9ea 11560{
01cd4528
EG		 11561 struct bnx2x *bp = netdev_priv(netdev);
11562 u16 value;
11563 int rc;
a2fbb9ea 11564
01cd4528
EG		 11565 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11566 prtad, devad, addr);
a2fbb9ea 11567
01cd4528
EG		 11568 /* The HW expects different devad if CL22 is used */
11569 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 11570
01cd4528 11571 bnx2x_acquire_phy_lock(bp);
e10bc84d 11572 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 11573 bnx2x_release_phy_lock(bp);
11574 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 11575
01cd4528
EG		 11576 if (!rc)
11577 rc = value;
11578 return rc;
11579}
a2fbb9ea 11580
01cd4528
EG		 11581/* called with rtnl_lock */
11582static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11583 u16 addr, u16 value)
11584{
11585 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 11586 int rc;
11587
51c1a580
MS		 11588 DP(NETIF_MSG_LINK,
11589 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11590 prtad, devad, addr, value);
01cd4528 11591
01cd4528
EG		 11592 /* The HW expects different devad if CL22 is used */
11593 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 11594
01cd4528 11595 bnx2x_acquire_phy_lock(bp);
e10bc84d 11596 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 11597 bnx2x_release_phy_lock(bp);
11598 return rc;
11599}
c18487ee 11600
01cd4528
EG		 11601/* called with rtnl_lock */
11602static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11603{
11604 struct bnx2x *bp = netdev_priv(dev);
11605 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 11606
01cd4528
EG		 11607 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11608 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 11609
01cd4528
EG		 11610 if (!netif_running(dev))
11611 return -EAGAIN;
11612
11613 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 11614}
11615
257ddbda 11616#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 11617static void poll_bnx2x(struct net_device *dev)
11618{
11619 struct bnx2x *bp = netdev_priv(dev);
14a15d61 11620 int i;
a2fbb9ea 11621
14a15d61
MS		 11622 for_each_eth_queue(bp, i) {
11623 struct bnx2x_fastpath *fp = &bp->fp[i];
11624 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11625 }
a2fbb9ea
ET		 11626}
11627#endif
11628
614c76df
DK		 11629static int bnx2x_validate_addr(struct net_device *dev)
11630{
11631 struct bnx2x *bp = netdev_priv(dev);
11632
51c1a580
MS		 11633 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11634 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 11635 return -EADDRNOTAVAIL;
51c1a580 11636 }
614c76df
DK		 11637 return 0;
11638}
11639
c64213cd
SH		 11640static const struct net_device_ops bnx2x_netdev_ops = {
11641 .ndo_open = bnx2x_open,
11642 .ndo_stop = bnx2x_close,
11643 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 11644 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 11645 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 11646 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 11647 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 11648 .ndo_do_ioctl = bnx2x_ioctl,
11649 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 11650 .ndo_fix_features = bnx2x_fix_features,
11651 .ndo_set_features = bnx2x_set_features,
c64213cd 11652 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 11653#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 11654 .ndo_poll_controller = poll_bnx2x,
11655#endif
6383c0b3
AE		 11656 .ndo_setup_tc = bnx2x_setup_tc,
11657
55c11941 11658#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 11659 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11660#endif
c64213cd
SH		 11661};
11662
1191cb83 11663static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 11664{
11665 struct device *dev = &bp->pdev->dev;
11666
11667 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11668 bp->flags |= USING_DAC_FLAG;
11669 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
51c1a580 11670 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
619c5cb6
VZ		 11671 return -EIO;
11672 }
11673 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11674 dev_err(dev, "System does not support DMA, aborting\n");
11675 return -EIO;
11676 }
11677
11678 return 0;
11679}
11680
1ab4434c
AE		 11681static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11682 struct net_device *dev, unsigned long board_type)
a2fbb9ea 11683{
a2fbb9ea 11684 int rc;
c22610d0 11685 u32 pci_cfg_dword;
65087cfe
AE		 11686 bool chip_is_e1x = (board_type == BCM57710 ||
11687 board_type == BCM57711 ||
11688 board_type == BCM57711E);
a2fbb9ea
ET		 11689
11690 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 11691
34f80b04
EG		 11692 bp->dev = dev;
11693 bp->pdev = pdev;
a2fbb9ea
ET		 11694
11695 rc = pci_enable_device(pdev);
11696 if (rc) {
cdaa7cb8
VZ		 11697 dev_err(&bp->pdev->dev,
11698 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 11699 goto err_out;
11700 }
11701
11702 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 11703 dev_err(&bp->pdev->dev,
11704 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 11705 rc = -ENODEV;
11706 goto err_out_disable;
11707 }
11708
1ab4434c
AE		 11709 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11710 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 11711 rc = -ENODEV;
11712 goto err_out_disable;
11713 }
11714
092a5fc9
YR		 11715 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11716 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11717 PCICFG_REVESION_ID_ERROR_VAL) {
11718 pr_err("PCI device error, probably due to fan failure, aborting\n");
11719 rc = -ENODEV;
11720 goto err_out_disable;
11721 }
11722
34f80b04
EG		 11723 if (atomic_read(&pdev->enable_cnt) == 1) {
11724 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11725 if (rc) {
cdaa7cb8
VZ		 11726 dev_err(&bp->pdev->dev,
11727 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 11728 goto err_out_disable;
11729 }
a2fbb9ea 11730
34f80b04
EG		 11731 pci_set_master(pdev);
11732 pci_save_state(pdev);
11733 }
a2fbb9ea 11734
1ab4434c
AE		 11735 if (IS_PF(bp)) {
11736 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11737 if (bp->pm_cap == 0) {
11738 dev_err(&bp->pdev->dev,
11739 "Cannot find power management capability, aborting\n");
11740 rc = -EIO;
11741 goto err_out_release;
11742 }
a2fbb9ea
ET		 11743 }
11744
77c98e6a 11745 if (!pci_is_pcie(pdev)) {
51c1a580 11746 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 11747 rc = -EIO;
11748 goto err_out_release;
11749 }
11750
619c5cb6
VZ		 11751 rc = bnx2x_set_coherency_mask(bp);
11752 if (rc)
a2fbb9ea 11753 goto err_out_release;
a2fbb9ea 11754
34f80b04
EG		 11755 dev->mem_start = pci_resource_start(pdev, 0);
11756 dev->base_addr = dev->mem_start;
11757 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 11758
11759 dev->irq = pdev->irq;
11760
275f165f 11761 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 11762 if (!bp->regview) {
cdaa7cb8
VZ		 11763 dev_err(&bp->pdev->dev,
11764 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 11765 rc = -ENOMEM;
11766 goto err_out_release;
11767 }
11768
c22610d0
AE		 11769 /* In E1/E1H use pci device function given by kernel.
11770 * In E2/E3 read physical function from ME register since these chips
11771 * support Physical Device Assignment where kernel BDF maybe arbitrary
11772 * (depending on hypervisor).
11773 */
11774 if (chip_is_e1x)
11775 bp->pf_num = PCI_FUNC(pdev->devfn);
11776 else {/* chip is E2/3*/
11777 pci_read_config_dword(bp->pdev,
11778 PCICFG_ME_REGISTER, &pci_cfg_dword);
11779 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11780 ME_REG_ABS_PF_NUM_SHIFT);
11781 }
51c1a580 11782 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 11783
a2fbb9ea
ET		 11784 bnx2x_set_power_state(bp, PCI_D0);
11785
34f80b04
EG		 11786 /* clean indirect addresses */
11787 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11788 PCICFG_VENDOR_ID_OFFSET);
a5c53dbc
DK		 11789 /*
11790 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 11791 * is not used by the driver.
11792 */
1ab4434c
AE		 11793 if (IS_PF(bp)) {
11794 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11795 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11796 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11797 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11798
11799 if (chip_is_e1x) {
11800 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11801 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11802 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11803 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11804 }
a5c53dbc 11805
1ab4434c
AE		 11806 /* Enable internal target-read (in case we are probed after PF
11807 * FLR). Must be done prior to any BAR read access. Only for
11808 * 57712 and up
11809 */
11810 if (!chip_is_e1x)
11811 REG_WR(bp,
11812 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 11813 }
a2fbb9ea 11814
34f80b04 11815 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 11816
c64213cd 11817 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 11818 bnx2x_set_ethtool_ops(dev);
5316bc0b 11819
01789349
JP		 11820 dev->priv_flags |= IFF_UNICAST_FLT;
11821
66371c44 11822 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66
DK		 11823 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11824 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11825 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
66371c44
MM		 11826
11827 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11828 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11829
11830 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 11831 if (bp->flags & USING_DAC_FLAG)
66371c44 11832 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 11833
538dd2e3
MB		 11834 /* Add Loopback capability to the device */
11835 dev->hw_features |= NETIF_F_LOOPBACK;
11836
98507672 11837#ifdef BCM_DCBNL
785b9b1a
SR		 11838 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11839#endif
11840
01cd4528
EG		 11841 /* get_port_hwinfo() will set prtad and mmds properly */
11842 bp->mdio.prtad = MDIO_PRTAD_NONE;
11843 bp->mdio.mmds = 0;
11844 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11845 bp->mdio.dev = dev;
11846 bp->mdio.mdio_read = bnx2x_mdio_read;
11847 bp->mdio.mdio_write = bnx2x_mdio_write;
11848
a2fbb9ea
ET		 11849 return 0;
11850
a2fbb9ea 11851err_out_release:
34f80b04
EG		 11852 if (atomic_read(&pdev->enable_cnt) == 1)
11853 pci_release_regions(pdev);
a2fbb9ea
ET		 11854
11855err_out_disable:
11856 pci_disable_device(pdev);
11857 pci_set_drvdata(pdev, NULL);
11858
11859err_out:
11860 return rc;
11861}
11862
1dd06ae8 11863static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
25047950 11864{
1ab4434c 11865 u32 val = 0;
25047950 11866
1ab4434c 11867 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
37f9ce62 11868 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 11869
37f9ce62
EG		 11870 /* return value of 1=2.5GHz 2=5GHz */
11871 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 11872}
37f9ce62 11873
6891dd25 11874static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 11875{
37f9ce62 11876 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 11877 struct bnx2x_fw_file_hdr *fw_hdr;
11878 struct bnx2x_fw_file_section *sections;
94a78b79 11879 u32 offset, len, num_ops;
37f9ce62 11880 u16 *ops_offsets;
94a78b79 11881 int i;
37f9ce62 11882 const u8 *fw_ver;
94a78b79 11883
51c1a580
MS		 11884 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11885 BNX2X_ERR("Wrong FW size\n");
94a78b79 11886 return -EINVAL;
51c1a580 11887 }
94a78b79
VZ		 11888
11889 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11890 sections = (struct bnx2x_fw_file_section *)fw_hdr;
11891
11892 /* Make sure none of the offsets and sizes make us read beyond
11893 * the end of the firmware data */
11894 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11895 offset = be32_to_cpu(sections[i].offset);
11896 len = be32_to_cpu(sections[i].len);
11897 if (offset + len > firmware->size) {
51c1a580 11898 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 11899 return -EINVAL;
11900 }
11901 }
11902
11903 /* Likewise for the init_ops offsets */
11904 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11905 ops_offsets = (u16 *)(firmware->data + offset);
11906 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11907
11908 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11909 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 11910 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 11911 return -EINVAL;
11912 }
11913 }
11914
11915 /* Check FW version */
11916 offset = be32_to_cpu(fw_hdr->fw_version.offset);
11917 fw_ver = firmware->data + offset;
11918 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11919 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11920 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11921 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 11922 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11923 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11924 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 11925 BCM_5710_FW_MINOR_VERSION,
11926 BCM_5710_FW_REVISION_VERSION,
11927 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 11928 return -EINVAL;
94a78b79
VZ		 11929 }
11930
11931 return 0;
11932}
11933
1191cb83 11934static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 11935{
ab6ad5a4
EG		 11936 const __be32 *source = (const __be32 *)_source;
11937 u32 *target = (u32 *)_target;
94a78b79 11938 u32 i;
94a78b79
VZ		 11939
11940 for (i = 0; i < n/4; i++)
11941 target[i] = be32_to_cpu(source[i]);
11942}
11943
11944/*
11945 Ops array is stored in the following format:
11946 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11947 */
1191cb83 11948static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 11949{
ab6ad5a4
EG		 11950 const __be32 *source = (const __be32 *)_source;
11951 struct raw_op *target = (struct raw_op *)_target;
94a78b79 11952 u32 i, j, tmp;
94a78b79 11953
ab6ad5a4 11954 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 11955 tmp = be32_to_cpu(source[j]);
11956 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 11957 target[i].offset = tmp & 0xffffff;
11958 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 11959 }
11960}
ab6ad5a4 11961
1aa8b471 11962/* IRO array is stored in the following format:
523224a3
DK		 11963 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11964 */
1191cb83 11965static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 11966{
11967 const __be32 *source = (const __be32 *)_source;
11968 struct iro *target = (struct iro *)_target;
11969 u32 i, j, tmp;
11970
11971 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11972 target[i].base = be32_to_cpu(source[j]);
11973 j++;
11974 tmp = be32_to_cpu(source[j]);
11975 target[i].m1 = (tmp >> 16) & 0xffff;
11976 target[i].m2 = tmp & 0xffff;
11977 j++;
11978 tmp = be32_to_cpu(source[j]);
11979 target[i].m3 = (tmp >> 16) & 0xffff;
11980 target[i].size = tmp & 0xffff;
11981 j++;
11982 }
11983}
11984
1191cb83 11985static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 11986{
ab6ad5a4
EG		 11987 const __be16 *source = (const __be16 *)_source;
11988 u16 *target = (u16 *)_target;
94a78b79 11989 u32 i;
94a78b79
VZ		 11990
11991 for (i = 0; i < n/2; i++)
11992 target[i] = be16_to_cpu(source[i]);
11993}
11994
7995c64e
JP		 11995#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11996do { \
11997 u32 len = be32_to_cpu(fw_hdr->arr.len); \
11998 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 11999 if (!bp->arr) \
7995c64e 12000 goto lbl; \
7995c64e
JP		 12001 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12002 (u8 *)bp->arr, len); \
12003} while (0)
94a78b79 12004
3b603066 12005static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 12006{
c0ea452e 12007 const char *fw_file_name;
94a78b79 12008 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 12009 int rc;
94a78b79 12010
c0ea452e
MS		 12011 if (bp->firmware)
12012 return 0;
94a78b79 12013
c0ea452e
MS		 12014 if (CHIP_IS_E1(bp))
12015 fw_file_name = FW_FILE_NAME_E1;
12016 else if (CHIP_IS_E1H(bp))
12017 fw_file_name = FW_FILE_NAME_E1H;
12018 else if (!CHIP_IS_E1x(bp))
12019 fw_file_name = FW_FILE_NAME_E2;
12020 else {
12021 BNX2X_ERR("Unsupported chip revision\n");
12022 return -EINVAL;
12023 }
12024 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 12025
c0ea452e
MS		 12026 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12027 if (rc) {
12028 BNX2X_ERR("Can't load firmware file %s\n",
12029 fw_file_name);
12030 goto request_firmware_exit;
12031 }
eb2afd4a 12032
c0ea452e
MS		 12033 rc = bnx2x_check_firmware(bp);
12034 if (rc) {
12035 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12036 goto request_firmware_exit;
94a78b79
VZ		 12037 }
12038
12039 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12040
12041 /* Initialize the pointers to the init arrays */
12042 /* Blob */
12043 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12044
12045 /* Opcodes */
12046 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12047
12048 /* Offsets */
ab6ad5a4
EG		 12049 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12050 be16_to_cpu_n);
94a78b79
VZ		 12051
12052 /* STORMs firmware */
573f2035
EG		 12053 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12054 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12055 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12056 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12057 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12058 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12059 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12060 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12061 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12062 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12063 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12064 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12065 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12066 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12067 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12068 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 12069 /* IRO */
12070 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 12071
12072 return 0;
ab6ad5a4 12073
523224a3
DK		 12074iro_alloc_err:
12075 kfree(bp->init_ops_offsets);
94a78b79
VZ		 12076init_offsets_alloc_err:
12077 kfree(bp->init_ops);
12078init_ops_alloc_err:
12079 kfree(bp->init_data);
12080request_firmware_exit:
12081 release_firmware(bp->firmware);
127d0a19 12082 bp->firmware = NULL;
94a78b79
VZ		 12083
12084 return rc;
12085}
12086
619c5cb6
VZ		 12087static void bnx2x_release_firmware(struct bnx2x *bp)
12088{
12089 kfree(bp->init_ops_offsets);
12090 kfree(bp->init_ops);
12091 kfree(bp->init_data);
12092 release_firmware(bp->firmware);
eb2afd4a 12093 bp->firmware = NULL;
619c5cb6
VZ		 12094}
12095
12096
12097static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12098 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12099 .init_hw_cmn = bnx2x_init_hw_common,
12100 .init_hw_port = bnx2x_init_hw_port,
12101 .init_hw_func = bnx2x_init_hw_func,
12102
12103 .reset_hw_cmn = bnx2x_reset_common,
12104 .reset_hw_port = bnx2x_reset_port,
12105 .reset_hw_func = bnx2x_reset_func,
12106
12107 .gunzip_init = bnx2x_gunzip_init,
12108 .gunzip_end = bnx2x_gunzip_end,
12109
12110 .init_fw = bnx2x_init_firmware,
12111 .release_fw = bnx2x_release_firmware,
12112};
12113
12114void bnx2x__init_func_obj(struct bnx2x *bp)
12115{
12116 /* Prepare DMAE related driver resources */
12117 bnx2x_setup_dmae(bp);
12118
12119 bnx2x_init_func_obj(bp, &bp->func_obj,
12120 bnx2x_sp(bp, func_rdata),
12121 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 12122 bnx2x_sp(bp, func_afex_rdata),
12123 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 12124 &bnx2x_func_sp_drv);
12125}
12126
12127/* must be called after sriov-enable */
1191cb83 12128static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 12129{
37ae41a9 12130 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 12131
290ca2bb
AE		 12132 if (IS_SRIOV(bp))
12133 cid_count += BNX2X_VF_CIDS;
12134
55c11941
MS		 12135 if (CNIC_SUPPORT(bp))
12136 cid_count += CNIC_CID_MAX;
290ca2bb 12137
523224a3
DK		 12138 return roundup(cid_count, QM_CID_ROUND);
12139}
f85582f8 12140
619c5cb6 12141/**
6383c0b3 12142 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 12143 *
12144 * @dev: pci device
12145 *
12146 */
55c11941 12147static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
1ab4434c 12148 int cnic_cnt, bool is_vf)
619c5cb6 12149{
1ab4434c
AE		 12150 int pos, index;
12151 u16 control = 0;
619c5cb6
VZ		 12152
12153 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 12154
12155 /*
12156 * If MSI-X is not supported - return number of SBs needed to support
12157 * one fast path queue: one FP queue + SB for CNIC
12158 */
1ab4434c
AE		 12159 if (!pos) {
12160 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 12161 return 1 + cnic_cnt;
1ab4434c
AE		 12162 }
12163 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 12164
6383c0b3
AE		 12165 /*
12166 * The value in the PCI configuration space is the index of the last
12167 * entry, namely one less than the actual size of the table, which is
12168 * exactly what we want to return from this function: number of all SBs
12169 * without the default SB.
1ab4434c 12170 * For VFs there is no default SB, then we return (index+1).
6383c0b3 12171 */
619c5cb6 12172 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
619c5cb6 12173
1ab4434c 12174 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 12175
1ab4434c
AE		 12176 return is_vf ? index + 1 : index;
12177}
523224a3 12178
1ab4434c
AE		 12179static int set_max_cos_est(int chip_id)
12180{
12181 switch (chip_id) {
f2e0899f
DK		 12182 case BCM57710:
12183 case BCM57711:
12184 case BCM57711E:
1ab4434c 12185 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 12186 case BCM57712:
619c5cb6 12187 case BCM57712_MF:
1ab4434c
AE		 12188 case BCM57712_VF:
12189 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 12190 case BCM57800:
12191 case BCM57800_MF:
1ab4434c 12192 case BCM57800_VF:
619c5cb6
VZ		 12193 case BCM57810:
12194 case BCM57810_MF:
c3def943
YM		 12195 case BCM57840_4_10:
12196 case BCM57840_2_20:
1ab4434c 12197 case BCM57840_O:
c3def943 12198 case BCM57840_MFO:
1ab4434c 12199 case BCM57810_VF:
619c5cb6 12200 case BCM57840_MF:
1ab4434c 12201 case BCM57840_VF:
7e8e02df
BW		 12202 case BCM57811:
12203 case BCM57811_MF:
1ab4434c
AE		 12204 case BCM57811_VF:
12205 return BNX2X_MULTI_TX_COS_E3B0;
12206 return 1;
f2e0899f 12207 default:
1ab4434c 12208 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 12209 return -ENODEV;
f2e0899f 12210 }
1ab4434c 12211}
f2e0899f 12212
1ab4434c
AE		 12213static int set_is_vf(int chip_id)
12214{
12215 switch (chip_id) {
12216 case BCM57712_VF:
12217 case BCM57800_VF:
12218 case BCM57810_VF:
12219 case BCM57840_VF:
12220 case BCM57811_VF:
12221 return true;
12222 default:
12223 return false;
12224 }
12225}
6383c0b3 12226
1ab4434c
AE		 12227struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12228
12229static int bnx2x_init_one(struct pci_dev *pdev,
12230 const struct pci_device_id *ent)
12231{
12232 struct net_device *dev = NULL;
12233 struct bnx2x *bp;
12234 int pcie_width, pcie_speed;
12235 int rc, max_non_def_sbs;
12236 int rx_count, tx_count, rss_count, doorbell_size;
12237 int max_cos_est;
12238 bool is_vf;
12239 int cnic_cnt;
12240
12241 /* An estimated maximum supported CoS number according to the chip
12242 * version.
12243 * We will try to roughly estimate the maximum number of CoSes this chip
12244 * may support in order to minimize the memory allocated for Tx
12245 * netdev_queue's. This number will be accurately calculated during the
12246 * initialization of bp->max_cos based on the chip versions AND chip
12247 * revision in the bnx2x_init_bp().
12248 */
12249 max_cos_est = set_max_cos_est(ent->driver_data);
12250 if (max_cos_est < 0)
12251 return max_cos_est;
12252 is_vf = set_is_vf(ent->driver_data);
12253 cnic_cnt = is_vf ? 0 : 1;
12254
12255 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
6383c0b3
AE		 12256
12257 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
1ab4434c
AE		 12258 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12259
12260 if (rss_count < 1)
12261 return -EINVAL;
6383c0b3
AE		 12262
12263 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 12264 rx_count = rss_count + cnic_cnt;
6383c0b3 12265
1ab4434c 12266 /* Maximum number of netdev Tx queues:
37ae41a9 12267 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 12268 */
55c11941 12269 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 12270
a2fbb9ea 12271 /* dev zeroed in init_etherdev */
6383c0b3 12272 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 12273 if (!dev)
a2fbb9ea
ET		 12274 return -ENOMEM;
12275
a2fbb9ea 12276 bp = netdev_priv(dev);
a2fbb9ea 12277
1ab4434c
AE		 12278 bp->flags = 0;
12279 if (is_vf)
12280 bp->flags |= IS_VF_FLAG;
12281
6383c0b3 12282 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 12283 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 12284 bp->msg_enable = debug;
55c11941 12285 bp->cnic_support = cnic_cnt;
4bd9b0ff 12286 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 12287
6383c0b3 12288 pci_set_drvdata(pdev, dev);
523224a3 12289
1ab4434c 12290 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 12291 if (rc < 0) {
12292 free_netdev(dev);
12293 return rc;
12294 }
12295
1ab4434c
AE		 12296 BNX2X_DEV_INFO("This is a %s function\n",
12297 IS_PF(bp) ? "physical" : "virtual");
55c11941 12298 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 12299 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509
MS		 12300 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12301 tx_count, rx_count);
12302
34f80b04 12303 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 12304 if (rc)
12305 goto init_one_exit;
12306
1ab4434c
AE		 12307 /* Map doorbells here as we need the real value of bp->max_cos which
12308 * is initialized in bnx2x_init_bp() to determine the number of
12309 * l2 connections.
6383c0b3 12310 */
1ab4434c
AE		 12311 if (IS_VF(bp)) {
12312 /* vf doorbells are embedded within the regview */
12313 bp->doorbells = bp->regview + PXP_VF_ADDR_DB_START;
12314
12315 /* allocate vf2pf mailbox for vf to pf channel */
12316 BNX2X_PCI_ALLOC(bp->vf2pf_mbox, &bp->vf2pf_mbox_mapping,
12317 sizeof(struct bnx2x_vf_mbx_msg));
12318 } else {
12319 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12320 if (doorbell_size > pci_resource_len(pdev, 2)) {
12321 dev_err(&bp->pdev->dev,
12322 "Cannot map doorbells, bar size too small, aborting\n");
12323 rc = -ENOMEM;
12324 goto init_one_exit;
12325 }
12326 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12327 doorbell_size);
37ae41a9 12328 }
6383c0b3
AE		 12329 if (!bp->doorbells) {
12330 dev_err(&bp->pdev->dev,
12331 "Cannot map doorbell space, aborting\n");
12332 rc = -ENOMEM;
12333 goto init_one_exit;
12334 }
12335
be1f1ffa
AE		 12336 if (IS_VF(bp)) {
12337 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12338 if (rc)
12339 goto init_one_exit;
12340 }
12341
290ca2bb
AE		 12342 /* Enable SRIOV if capability found in configuration space.
12343 * Once the generic SR-IOV framework makes it in from the
12344 * pci tree this will be revised, to allow dynamic control
12345 * over the number of VFs. Right now, change the num of vfs
12346 * param below to enable SR-IOV.
12347 */
12348 rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/);
12349 if (rc)
12350 goto init_one_exit;
12351
523224a3 12352 /* calc qm_cid_count */
6383c0b3 12353 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 12354 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 12355
55c11941 12356 /* disable FCOE L2 queue for E1x*/
62ac0dc9 12357 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 12358 bp->flags |= NO_FCOE_FLAG;
12359
477864dd
DK		 12360 /* disable FCOE for 57840 device, until FW supports it */
12361 switch (ent->driver_data) {
12362 case BCM57840_O:
12363 case BCM57840_4_10:
12364 case BCM57840_2_20:
12365 case BCM57840_MFO:
12366 case BCM57840_MF:
12367 bp->flags |= NO_FCOE_FLAG;
12368 }
0e8d2ec5
MS		 12369
12370 /* Set bp->num_queues for MSI-X mode*/
12371 bnx2x_set_num_queues(bp);
12372
25985edc 12373 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 12374 * needed.
d6214d7a 12375 */
1ab4434c
AE		 12376 rc = bnx2x_set_int_mode(bp);
12377 if (rc) {
12378 dev_err(&pdev->dev, "Cannot set interrupts\n");
12379 goto init_one_exit;
12380 }
d6214d7a 12381
1ab4434c 12382 /* register the net device */
b340007f
VZ		 12383 rc = register_netdev(dev);
12384 if (rc) {
12385 dev_err(&pdev->dev, "Cannot register net device\n");
12386 goto init_one_exit;
12387 }
1ab4434c 12388 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 12389
55c11941 12390
ec6ba945
VZ		 12391 if (!NO_FCOE(bp)) {
12392 /* Add storage MAC address */
12393 rtnl_lock();
12394 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12395 rtnl_unlock();
12396 }
ec6ba945 12397
37f9ce62 12398 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
1ab4434c
AE		 12399 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12400 pcie_width, pcie_speed);
d6214d7a 12401
51c1a580
MS		 12402 BNX2X_DEV_INFO(
12403 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
94f05b0f
JP		 12404 board_info[ent->driver_data].name,
12405 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12406 pcie_width,
12407 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12408 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12409 "5GHz (Gen2)" : "2.5GHz",
12410 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 12411
a2fbb9ea 12412 return 0;
34f80b04 12413
1ab4434c
AE		 12414alloc_mem_err:
12415 BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
12416 sizeof(struct bnx2x_vf_mbx_msg));
12417 rc = -ENOMEM;
12418
34f80b04
EG		 12419init_one_exit:
12420 if (bp->regview)
12421 iounmap(bp->regview);
12422
1ab4434c 12423 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 12424 iounmap(bp->doorbells);
12425
12426 free_netdev(dev);
12427
12428 if (atomic_read(&pdev->enable_cnt) == 1)
12429 pci_release_regions(pdev);
12430
12431 pci_disable_device(pdev);
12432 pci_set_drvdata(pdev, NULL);
12433
12434 return rc;
a2fbb9ea
ET		 12435}
12436
0329aba1 12437static void bnx2x_remove_one(struct pci_dev *pdev)
a2fbb9ea
ET		 12438{
12439 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 12440 struct bnx2x *bp;
12441
12442 if (!dev) {
cdaa7cb8 12443 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 12444 return;
12445 }
228241eb 12446 bp = netdev_priv(dev);
a2fbb9ea 12447
ec6ba945
VZ		 12448 /* Delete storage MAC address */
12449 if (!NO_FCOE(bp)) {
12450 rtnl_lock();
12451 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12452 rtnl_unlock();
12453 }
ec6ba945 12454
98507672
SR		 12455#ifdef BCM_DCBNL
12456 /* Delete app tlvs from dcbnl */
12457 bnx2x_dcbnl_update_applist(bp, true);
12458#endif
12459
a2fbb9ea
ET		 12460 unregister_netdev(dev);
12461
084d6cbb 12462 /* Power on: we can't let PCI layer write to us while we are in D3 */
1ab4434c
AE		 12463 if (IS_PF(bp))
12464 bnx2x_set_power_state(bp, PCI_D0);
084d6cbb 12465
d6214d7a
DK		 12466 /* Disable MSI/MSI-X */
12467 bnx2x_disable_msi(bp);
f85582f8 12468
084d6cbb 12469 /* Power off */
1ab4434c
AE		 12470 if (IS_PF(bp))
12471 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 12472
72fd0718 12473 /* Make sure RESET task is not scheduled before continuing */
7be08a72 12474 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb
AE		 12475
12476 bnx2x_iov_remove_one(bp);
12477
4513f925
AE		 12478 /* send message via vfpf channel to release the resources of this vf */
12479 if (IS_VF(bp))
12480 bnx2x_vfpf_release(bp);
72fd0718 12481
a2fbb9ea
ET		 12482 if (bp->regview)
12483 iounmap(bp->regview);
12484
1ab4434c
AE		 12485 /* for vf doorbells are part of the regview and were unmapped along with
12486 * it. FW is only loaded by PF.
12487 */
12488 if (IS_PF(bp)) {
12489 if (bp->doorbells)
12490 iounmap(bp->doorbells);
eb2afd4a 12491
1ab4434c
AE		 12492 bnx2x_release_firmware(bp);
12493 }
523224a3
DK		 12494 bnx2x_free_mem_bp(bp);
12495
a2fbb9ea 12496 free_netdev(dev);
34f80b04
EG		 12497
12498 if (atomic_read(&pdev->enable_cnt) == 1)
12499 pci_release_regions(pdev);
12500
a2fbb9ea
ET		 12501 pci_disable_device(pdev);
12502 pci_set_drvdata(pdev, NULL);
12503}
12504
f8ef6e44
YG		 12505static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12506{
12507 int i;
12508
12509 bp->state = BNX2X_STATE_ERROR;
12510
12511 bp->rx_mode = BNX2X_RX_MODE_NONE;
12512
55c11941
MS		 12513 if (CNIC_LOADED(bp))
12514 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12515
619c5cb6
VZ		 12516 /* Stop Tx */
12517 bnx2x_tx_disable(bp);
12518
f8ef6e44 12519 bnx2x_netif_stop(bp, 0);
26614ba5
MS		 12520 /* Delete all NAPI objects */
12521 bnx2x_del_all_napi(bp);
55c11941
MS		 12522 if (CNIC_LOADED(bp))
12523 bnx2x_del_all_napi_cnic(bp);
f8ef6e44
YG		 12524
12525 del_timer_sync(&bp->timer);
619c5cb6
VZ		 12526
12527 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 12528
12529 /* Release IRQs */
d6214d7a 12530 bnx2x_free_irq(bp);
f8ef6e44 12531
f8ef6e44
YG		 12532 /* Free SKBs, SGEs, TPA pool and driver internals */
12533 bnx2x_free_skbs(bp);
523224a3 12534
ec6ba945 12535 for_each_rx_queue(bp, i)
f8ef6e44 12536 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 12537
f8ef6e44
YG		 12538 bnx2x_free_mem(bp);
12539
12540 bp->state = BNX2X_STATE_CLOSED;
12541
619c5cb6
VZ		 12542 netif_carrier_off(bp->dev);
12543
f8ef6e44
YG		 12544 return 0;
12545}
12546
12547static void bnx2x_eeh_recover(struct bnx2x *bp)
12548{
12549 u32 val;
12550
12551 mutex_init(&bp->port.phy_mutex);
12552
f8ef6e44
YG		 12553
12554 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12555 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12556 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12557 BNX2X_ERR("BAD MCP validity signature\n");
f8ef6e44
YG		 12558}
12559
493adb1f
WX		 12560/**
12561 * bnx2x_io_error_detected - called when PCI error is detected
12562 * @pdev: Pointer to PCI device
12563 * @state: The current pci connection state
12564 *
12565 * This function is called after a PCI bus error affecting
12566 * this device has been detected.
12567 */
12568static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12569 pci_channel_state_t state)
12570{
12571 struct net_device *dev = pci_get_drvdata(pdev);
12572 struct bnx2x *bp = netdev_priv(dev);
12573
12574 rtnl_lock();
12575
12576 netif_device_detach(dev);
12577
07ce50e4
DN		 12578 if (state == pci_channel_io_perm_failure) {
12579 rtnl_unlock();
12580 return PCI_ERS_RESULT_DISCONNECT;
12581 }
12582
493adb1f 12583 if (netif_running(dev))
f8ef6e44 12584 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 12585
12586 pci_disable_device(pdev);
12587
12588 rtnl_unlock();
12589
12590 /* Request a slot reset */
12591 return PCI_ERS_RESULT_NEED_RESET;
12592}
12593
12594/**
12595 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12596 * @pdev: Pointer to PCI device
12597 *
12598 * Restart the card from scratch, as if from a cold-boot.
12599 */
12600static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12601{
12602 struct net_device *dev = pci_get_drvdata(pdev);
12603 struct bnx2x *bp = netdev_priv(dev);
12604
12605 rtnl_lock();
12606
12607 if (pci_enable_device(pdev)) {
12608 dev_err(&pdev->dev,
12609 "Cannot re-enable PCI device after reset\n");
12610 rtnl_unlock();
12611 return PCI_ERS_RESULT_DISCONNECT;
12612 }
12613
12614 pci_set_master(pdev);
12615 pci_restore_state(pdev);
12616
12617 if (netif_running(dev))
12618 bnx2x_set_power_state(bp, PCI_D0);
12619
12620 rtnl_unlock();
12621
12622 return PCI_ERS_RESULT_RECOVERED;
12623}
12624
12625/**
12626 * bnx2x_io_resume - called when traffic can start flowing again
12627 * @pdev: Pointer to PCI device
12628 *
12629 * This callback is called when the error recovery driver tells us that
12630 * its OK to resume normal operation.
12631 */
12632static void bnx2x_io_resume(struct pci_dev *pdev)
12633{
12634 struct net_device *dev = pci_get_drvdata(pdev);
12635 struct bnx2x *bp = netdev_priv(dev);
12636
72fd0718 12637 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 12638 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 12639 return;
12640 }
12641
493adb1f
WX		 12642 rtnl_lock();
12643
f8ef6e44
YG		 12644 bnx2x_eeh_recover(bp);
12645
493adb1f 12646 if (netif_running(dev))
f8ef6e44 12647 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 12648
12649 netif_device_attach(dev);
12650
12651 rtnl_unlock();
12652}
12653
3646f0e5 12654static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 12655 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 12656 .slot_reset = bnx2x_io_slot_reset,
12657 .resume = bnx2x_io_resume,
493adb1f
WX		 12658};
12659
a2fbb9ea 12660static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 12661 .name = DRV_MODULE_NAME,
12662 .id_table = bnx2x_pci_tbl,
12663 .probe = bnx2x_init_one,
0329aba1 12664 .remove = bnx2x_remove_one,
493adb1f
WX		 12665 .suspend = bnx2x_suspend,
12666 .resume = bnx2x_resume,
12667 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 12668};
12669
12670static int __init bnx2x_init(void)
12671{
dd21ca6d
SG		 12672 int ret;
12673
7995c64e 12674 pr_info("%s", version);
938cf541 12675
1cf167f2
EG		 12676 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12677 if (bnx2x_wq == NULL) {
7995c64e 12678 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 12679 return -ENOMEM;
12680 }
12681
dd21ca6d
SG		 12682 ret = pci_register_driver(&bnx2x_pci_driver);
12683 if (ret) {
7995c64e 12684 pr_err("Cannot register driver\n");
dd21ca6d
SG		 12685 destroy_workqueue(bnx2x_wq);
12686 }
12687 return ret;
a2fbb9ea
ET		 12688}
12689
12690static void __exit bnx2x_cleanup(void)
12691{
452427b0 12692 struct list_head *pos, *q;
a2fbb9ea 12693 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 12694
12695 destroy_workqueue(bnx2x_wq);
452427b0
YM		 12696
12697 /* Free globablly allocated resources */
12698 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12699 struct bnx2x_prev_path_list *tmp =
12700 list_entry(pos, struct bnx2x_prev_path_list, list);
12701 list_del(pos);
12702 kfree(tmp);
12703 }
a2fbb9ea
ET		 12704}
12705
3deb8167
YR		 12706void bnx2x_notify_link_changed(struct bnx2x *bp)
12707{
12708 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12709}
12710
a2fbb9ea
ET		 12711module_init(bnx2x_init);
12712module_exit(bnx2x_cleanup);
12713
619c5cb6
VZ		 12714/**
12715 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12716 *
12717 * @bp: driver handle
12718 * @set: set or clear the CAM entry
12719 *
12720 * This function will wait until the ramdord completion returns.
12721 * Return 0 if success, -ENODEV if ramrod doesn't return.
12722 */
1191cb83 12723static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 12724{
12725 unsigned long ramrod_flags = 0;
12726
12727 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12728 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12729 &bp->iscsi_l2_mac_obj, true,
12730 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12731}
993ac7b5
MC		 12732
12733/* count denotes the number of new completions we have seen */
12734static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12735{
12736 struct eth_spe *spe;
a052997e 12737 int cxt_index, cxt_offset;
993ac7b5
MC		 12738
12739#ifdef BNX2X_STOP_ON_ERROR
12740 if (unlikely(bp->panic))
12741 return;
12742#endif
12743
12744 spin_lock_bh(&bp->spq_lock);
c2bff63f 12745 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 12746 bp->cnic_spq_pending -= count;
12747
993ac7b5 12748
c2bff63f
DK		 12749 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12750 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12751 & SPE_HDR_CONN_TYPE) >>
12752 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 12753 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12754 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 12755
12756 /* Set validation for iSCSI L2 client before sending SETUP
12757 * ramrod
12758 */
12759 if (type == ETH_CONNECTION_TYPE) {
a052997e 12760 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 12761 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 12762 ILT_PAGE_CIDS;
37ae41a9 12763 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 12764 (cxt_index * ILT_PAGE_CIDS);
12765 bnx2x_set_ctx_validation(bp,
12766 &bp->context[cxt_index].
12767 vcxt[cxt_offset].eth,
37ae41a9 12768 BNX2X_ISCSI_ETH_CID(bp));
a052997e 12769 }
c2bff63f
DK		 12770 }
12771
619c5cb6
VZ		 12772 /*
12773 * There may be not more than 8 L2, not more than 8 L5 SPEs
12774 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 12775 * COMMON ramrods is not more than the EQ and SPQ can
12776 * accommodate.
c2bff63f 12777 */
6e30dd4e
VZ		 12778 if (type == ETH_CONNECTION_TYPE) {
12779 if (!atomic_read(&bp->cq_spq_left))
12780 break;
12781 else
12782 atomic_dec(&bp->cq_spq_left);
12783 } else if (type == NONE_CONNECTION_TYPE) {
12784 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 12785 break;
12786 else
6e30dd4e 12787 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 12788 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12789 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 12790 if (bp->cnic_spq_pending >=
12791 bp->cnic_eth_dev.max_kwqe_pending)
12792 break;
12793 else
12794 bp->cnic_spq_pending++;
12795 } else {
12796 BNX2X_ERR("Unknown SPE type: %d\n", type);
12797 bnx2x_panic();
993ac7b5 12798 break;
c2bff63f 12799 }
993ac7b5
MC		 12800
12801 spe = bnx2x_sp_get_next(bp);
12802 *spe = *bp->cnic_kwq_cons;
12803
51c1a580 12804 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 12805 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12806
12807 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12808 bp->cnic_kwq_cons = bp->cnic_kwq;
12809 else
12810 bp->cnic_kwq_cons++;
12811 }
12812 bnx2x_sp_prod_update(bp);
12813 spin_unlock_bh(&bp->spq_lock);
12814}
12815
12816static int bnx2x_cnic_sp_queue(struct net_device *dev,
12817 struct kwqe_16 *kwqes[], u32 count)
12818{
12819 struct bnx2x *bp = netdev_priv(dev);
12820 int i;
12821
12822#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 12823 if (unlikely(bp->panic)) {
12824 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 12825 return -EIO;
51c1a580 12826 }
993ac7b5
MC		 12827#endif
12828
95c6c616
AE		 12829 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12830 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 12831 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 12832 return -EAGAIN;
12833 }
12834
993ac7b5
MC		 12835 spin_lock_bh(&bp->spq_lock);
12836
12837 for (i = 0; i < count; i++) {
12838 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12839
12840 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12841 break;
12842
12843 *bp->cnic_kwq_prod = *spe;
12844
12845 bp->cnic_kwq_pending++;
12846
51c1a580 12847 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 12848 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 12849 spe->data.update_data_addr.hi,
12850 spe->data.update_data_addr.lo,
993ac7b5
MC		 12851 bp->cnic_kwq_pending);
12852
12853 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12854 bp->cnic_kwq_prod = bp->cnic_kwq;
12855 else
12856 bp->cnic_kwq_prod++;
12857 }
12858
12859 spin_unlock_bh(&bp->spq_lock);
12860
12861 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12862 bnx2x_cnic_sp_post(bp, 0);
12863
12864 return i;
12865}
12866
12867static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12868{
12869 struct cnic_ops *c_ops;
12870 int rc = 0;
12871
12872 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 12873 c_ops = rcu_dereference_protected(bp->cnic_ops,
12874 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 12875 if (c_ops)
12876 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12877 mutex_unlock(&bp->cnic_mutex);
12878
12879 return rc;
12880}
12881
12882static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12883{
12884 struct cnic_ops *c_ops;
12885 int rc = 0;
12886
12887 rcu_read_lock();
12888 c_ops = rcu_dereference(bp->cnic_ops);
12889 if (c_ops)
12890 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12891 rcu_read_unlock();
12892
12893 return rc;
12894}
12895
12896/*
12897 * for commands that have no data
12898 */
9f6c9258 12899int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 12900{
12901 struct cnic_ctl_info ctl = {0};
12902
12903 ctl.cmd = cmd;
12904
12905 return bnx2x_cnic_ctl_send(bp, &ctl);
12906}
12907
619c5cb6 12908static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 12909{
619c5cb6 12910 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 12911
12912 /* first we tell CNIC and only then we count this as a completion */
12913 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12914 ctl.data.comp.cid = cid;
619c5cb6 12915 ctl.data.comp.error = err;
993ac7b5
MC		 12916
12917 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 12918 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 12919}
12920
619c5cb6
VZ		 12921
12922/* Called with netif_addr_lock_bh() taken.
12923 * Sets an rx_mode config for an iSCSI ETH client.
12924 * Doesn't block.
12925 * Completion should be checked outside.
12926 */
12927static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12928{
12929 unsigned long accept_flags = 0, ramrod_flags = 0;
12930 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12931 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12932
12933 if (start) {
12934 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12935 * because it's the only way for UIO Queue to accept
12936 * multicasts (in non-promiscuous mode only one Queue per
12937 * function will receive multicast packets (leading in our
12938 * case).
12939 */
12940 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12941 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12942 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12943 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12944
12945 /* Clear STOP_PENDING bit if START is requested */
12946 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12947
12948 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12949 } else
12950 /* Clear START_PENDING bit if STOP is requested */
12951 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12952
12953 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12954 set_bit(sched_state, &bp->sp_state);
12955 else {
12956 __set_bit(RAMROD_RX, &ramrod_flags);
12957 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12958 ramrod_flags);
12959 }
12960}
12961
12962
993ac7b5
MC		 12963static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12964{
12965 struct bnx2x *bp = netdev_priv(dev);
12966 int rc = 0;
12967
12968 switch (ctl->cmd) {
12969 case DRV_CTL_CTXTBL_WR_CMD: {
12970 u32 index = ctl->data.io.offset;
12971 dma_addr_t addr = ctl->data.io.dma_addr;
12972
12973 bnx2x_ilt_wr(bp, index, addr);
12974 break;
12975 }
12976
c2bff63f
DK		 12977 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12978 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 12979
12980 bnx2x_cnic_sp_post(bp, count);
12981 break;
12982 }
12983
12984 /* rtnl_lock is held. */
12985 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 12986 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12987 unsigned long sp_bits = 0;
12988
12989 /* Configure the iSCSI classification object */
12990 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12991 cp->iscsi_l2_client_id,
12992 cp->iscsi_l2_cid, BP_FUNC(bp),
12993 bnx2x_sp(bp, mac_rdata),
12994 bnx2x_sp_mapping(bp, mac_rdata),
12995 BNX2X_FILTER_MAC_PENDING,
12996 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12997 &bp->macs_pool);
ec6ba945 12998
523224a3 12999 /* Set iSCSI MAC address */
619c5cb6
VZ		 13000 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13001 if (rc)
13002 break;
523224a3
DK		 13003
13004 mmiowb();
13005 barrier();
13006
619c5cb6
VZ		 13007 /* Start accepting on iSCSI L2 ring */
13008
13009 netif_addr_lock_bh(dev);
13010 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13011 netif_addr_unlock_bh(dev);
13012
13013 /* bits to wait on */
13014 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13015 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13016
13017 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13018 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 13019
993ac7b5
MC		 13020 break;
13021 }
13022
13023 /* rtnl_lock is held. */
13024 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 13025 unsigned long sp_bits = 0;
993ac7b5 13026
523224a3 13027 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 13028 netif_addr_lock_bh(dev);
13029 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13030 netif_addr_unlock_bh(dev);
13031
13032 /* bits to wait on */
13033 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13034 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13035
13036 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13037 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 13038
13039 mmiowb();
13040 barrier();
13041
13042 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 13043 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13044 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 13045 break;
13046 }
c2bff63f
DK		 13047 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13048 int count = ctl->data.credit.credit_count;
13049
13050 smp_mb__before_atomic_inc();
6e30dd4e 13051 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 13052 smp_mb__after_atomic_inc();
13053 break;
13054 }
1d187b34 13055 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 13056 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 13057
13058 if (CHIP_IS_E3(bp)) {
13059 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 13060 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13061 int path = BP_PATH(bp);
13062 int port = BP_PORT(bp);
13063 int i;
13064 u32 scratch_offset;
13065 u32 *host_addr;
1d187b34 13066
2e499d3c 13067 /* first write capability to shmem2 */
1d187b34
BW		 13068 if (ulp_type == CNIC_ULP_ISCSI)
13069 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13070 else if (ulp_type == CNIC_ULP_FCOE)
13071 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13072 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 13073
13074 if ((ulp_type != CNIC_ULP_FCOE) ||
13075 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13076 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13077 break;
13078
13079 /* if reached here - should write fcoe capabilities */
13080 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13081 if (!scratch_offset)
13082 break;
13083 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13084 fcoe_features[path][port]);
13085 host_addr = (u32 *) &(ctl->data.register_data.
13086 fcoe_features);
13087 for (i = 0; i < sizeof(struct fcoe_capabilities);
13088 i += 4)
13089 REG_WR(bp, scratch_offset + i,
13090 *(host_addr + i/4));
1d187b34
BW		 13091 }
13092 break;
13093 }
2e499d3c 13094
1d187b34
BW		 13095 case DRV_CTL_ULP_UNREGISTER_CMD: {
13096 int ulp_type = ctl->data.ulp_type;
13097
13098 if (CHIP_IS_E3(bp)) {
13099 int idx = BP_FW_MB_IDX(bp);
13100 u32 cap;
13101
13102 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13103 if (ulp_type == CNIC_ULP_ISCSI)
13104 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13105 else if (ulp_type == CNIC_ULP_FCOE)
13106 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13107 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13108 }
13109 break;
13110 }
993ac7b5
MC		 13111
13112 default:
13113 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13114 rc = -EINVAL;
13115 }
13116
13117 return rc;
13118}
13119
9f6c9258 13120void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 13121{
13122 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13123
13124 if (bp->flags & USING_MSIX_FLAG) {
13125 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13126 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13127 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13128 } else {
13129 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13130 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13131 }
619c5cb6 13132 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 13133 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13134 else
13135 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13136
619c5cb6
VZ		 13137 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13138 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 13139 cp->irq_arr[1].status_blk = bp->def_status_blk;
13140 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 13141 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 13142
13143 cp->num_irq = 2;
13144}
13145
37ae41a9
MS		 13146void bnx2x_setup_cnic_info(struct bnx2x *bp)
13147{
13148 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13149
13150
13151 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13152 bnx2x_cid_ilt_lines(bp);
13153 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13154 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13155 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13156
13157 if (NO_ISCSI_OOO(bp))
13158 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13159}
13160
993ac7b5
MC		 13161static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13162 void *data)
13163{
13164 struct bnx2x *bp = netdev_priv(dev);
13165 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 13166 int rc;
13167
13168 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 13169
51c1a580
MS		 13170 if (ops == NULL) {
13171 BNX2X_ERR("NULL ops received\n");
993ac7b5 13172 return -EINVAL;
51c1a580 13173 }
993ac7b5 13174
55c11941
MS		 13175 if (!CNIC_SUPPORT(bp)) {
13176 BNX2X_ERR("Can't register CNIC when not supported\n");
13177 return -EOPNOTSUPP;
13178 }
13179
13180 if (!CNIC_LOADED(bp)) {
13181 rc = bnx2x_load_cnic(bp);
13182 if (rc) {
13183 BNX2X_ERR("CNIC-related load failed\n");
13184 return rc;
13185 }
13186
13187 }
13188
13189 bp->cnic_enabled = true;
13190
993ac7b5
MC		 13191 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13192 if (!bp->cnic_kwq)
13193 return -ENOMEM;
13194
13195 bp->cnic_kwq_cons = bp->cnic_kwq;
13196 bp->cnic_kwq_prod = bp->cnic_kwq;
13197 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13198
13199 bp->cnic_spq_pending = 0;
13200 bp->cnic_kwq_pending = 0;
13201
13202 bp->cnic_data = data;
13203
13204 cp->num_irq = 0;
619c5cb6 13205 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 13206 cp->iro_arr = bp->iro_arr;
993ac7b5 13207
993ac7b5 13208 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 13209
993ac7b5
MC		 13210 rcu_assign_pointer(bp->cnic_ops, ops);
13211
13212 return 0;
13213}
13214
13215static int bnx2x_unregister_cnic(struct net_device *dev)
13216{
13217 struct bnx2x *bp = netdev_priv(dev);
13218 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13219
13220 mutex_lock(&bp->cnic_mutex);
993ac7b5 13221 cp->drv_state = 0;
2cfa5a04 13222 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 13223 mutex_unlock(&bp->cnic_mutex);
13224 synchronize_rcu();
13225 kfree(bp->cnic_kwq);
13226 bp->cnic_kwq = NULL;
13227
13228 return 0;
13229}
13230
13231struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13232{
13233 struct bnx2x *bp = netdev_priv(dev);
13234 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13235
2ba45142
VZ		 13236 /* If both iSCSI and FCoE are disabled - return NULL in
13237 * order to indicate CNIC that it should not try to work
13238 * with this device.
13239 */
13240 if (NO_ISCSI(bp) && NO_FCOE(bp))
13241 return NULL;
13242
993ac7b5
MC		 13243 cp->drv_owner = THIS_MODULE;
13244 cp->chip_id = CHIP_ID(bp);
13245 cp->pdev = bp->pdev;
13246 cp->io_base = bp->regview;
13247 cp->io_base2 = bp->doorbells;
13248 cp->max_kwqe_pending = 8;
523224a3 13249 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 13250 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13251 bnx2x_cid_ilt_lines(bp);
993ac7b5 13252 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 13253 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 13254 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13255 cp->drv_ctl = bnx2x_drv_ctl;
13256 cp->drv_register_cnic = bnx2x_register_cnic;
13257 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 13258 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 13259 cp->iscsi_l2_client_id =
13260 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 13261 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 13262
2ba45142
VZ		 13263 if (NO_ISCSI_OOO(bp))
13264 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13265
13266 if (NO_ISCSI(bp))
13267 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13268
13269 if (NO_FCOE(bp))
13270 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13271
51c1a580
MS		 13272 BNX2X_DEV_INFO(
13273 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 13274 cp->ctx_blk_size,
13275 cp->ctx_tbl_offset,
13276 cp->ctx_tbl_len,
13277 cp->starting_cid);
993ac7b5
MC		 13278 return cp;
13279}
993ac7b5 13280
be1f1ffa
AE		 13281int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping)
13282{
13283 struct cstorm_vf_zone_data __iomem *zone_data =
13284 REG_ADDR(bp, PXP_VF_ADDR_CSDM_GLOBAL_START);
13285 int tout = 600, interval = 100; /* wait for 60 seconds */
13286
13287 if (*done) {
13288 BNX2X_ERR("done was non zero before message to pf was sent\n");
13289 WARN_ON(true);
13290 return -EINVAL;
13291 }
13292
13293 /* Write message address */
13294 writel(U64_LO(msg_mapping),
13295 &zone_data->non_trigger.vf_pf_channel.msg_addr_lo);
13296 writel(U64_HI(msg_mapping),
13297 &zone_data->non_trigger.vf_pf_channel.msg_addr_hi);
13298
13299 /* make sure the address is written before FW accesses it */
13300 wmb();
13301
13302 /* Trigger the PF FW */
13303 writeb(1, &zone_data->trigger.vf_pf_channel.addr_valid);
13304
13305 /* Wait for PF to complete */
13306 while ((tout >= 0) && (!*done)) {
13307 msleep(interval);
13308 tout -= 1;
13309
13310 /* progress indicator - HV can take its own sweet time in
13311 * answering VFs...
13312 */
13313 DP_CONT(BNX2X_MSG_IOV, ".");
13314 }
13315
13316 if (!*done) {
13317 BNX2X_ERR("PF response has timed out\n");
13318 return -EAGAIN;
13319 }
13320 DP(BNX2X_MSG_SP, "Got a response from PF\n");
13321 return 0;
13322}
13323
13324int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id)
13325{
13326 u32 me_reg;
13327 int tout = 10, interval = 100; /* Wait for 1 sec */
13328
13329 do {
13330 /* pxp traps vf read of doorbells and returns me reg value */
13331 me_reg = readl(bp->doorbells);
13332 if (GOOD_ME_REG(me_reg))
13333 break;
13334
13335 msleep(interval);
13336
13337 BNX2X_ERR("Invalid ME register value: 0x%08x\n. Is pf driver up?",
13338 me_reg);
13339 } while (tout-- > 0);
13340
13341 if (!GOOD_ME_REG(me_reg)) {
13342 BNX2X_ERR("Invalid ME register value: 0x%08x\n", me_reg);
13343 return -EINVAL;
13344 }
13345
13346 BNX2X_ERR("valid ME register value: 0x%08x\n", me_reg);
13347
13348 *vf_id = (me_reg & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT;
94a78b79 13349
be1f1ffa
AE		 13350 return 0;
13351}
13352
13353int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count)
13354{
13355 int rc = 0, attempts = 0;
13356 struct vfpf_acquire_tlv *req = &bp->vf2pf_mbox->req.acquire;
13357 struct pfvf_acquire_resp_tlv *resp = &bp->vf2pf_mbox->resp.acquire_resp;
13358 u32 vf_id;
13359 bool resources_acquired = false;
13360
13361 /* clear mailbox and prep first tlv */
13362 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_ACQUIRE, sizeof(*req));
13363
13364 if (bnx2x_get_vf_id(bp, &vf_id))
13365 return -EAGAIN;
13366
13367 req->vfdev_info.vf_id = vf_id;
13368 req->vfdev_info.vf_os = 0;
13369
13370 req->resc_request.num_rxqs = rx_count;
13371 req->resc_request.num_txqs = tx_count;
13372 req->resc_request.num_sbs = bp->igu_sb_cnt;
13373 req->resc_request.num_mac_filters = VF_ACQUIRE_MAC_FILTERS;
13374 req->resc_request.num_mc_filters = VF_ACQUIRE_MC_FILTERS;
13375
13376 /* add list termination tlv */
13377 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13378 sizeof(struct channel_list_end_tlv));
13379
13380 /* output tlvs list */
13381 bnx2x_dp_tlv_list(bp, req);
13382
13383 while (!resources_acquired) {
13384 DP(BNX2X_MSG_SP, "attempting to acquire resources\n");
13385
13386 /* send acquire request */
13387 rc = bnx2x_send_msg2pf(bp,
13388 &resp->hdr.status,
13389 bp->vf2pf_mbox_mapping);
13390
13391 /* PF timeout */
13392 if (rc)
13393 return rc;
13394
13395 /* copy acquire response from buffer to bp */
13396 memcpy(&bp->acquire_resp, resp, sizeof(bp->acquire_resp));
13397
13398 attempts++;
13399
13400 /* test whether the PF accepted our request. If not, humble the
13401 * the request and try again.
13402 */
13403 if (bp->acquire_resp.hdr.status == PFVF_STATUS_SUCCESS) {
13404 DP(BNX2X_MSG_SP, "resources acquired\n");
13405 resources_acquired = true;
13406 } else if (bp->acquire_resp.hdr.status ==
13407 PFVF_STATUS_NO_RESOURCE &&
13408 attempts < VF_ACQUIRE_THRESH) {
13409 DP(BNX2X_MSG_SP,
13410 "PF unwilling to fulfill resource request. Try PF recommended amount\n");
13411
13412 /* humble our request */
13413 req->resc_request.num_txqs =
13414 bp->acquire_resp.resc.num_txqs;
13415 req->resc_request.num_rxqs =
13416 bp->acquire_resp.resc.num_rxqs;
13417 req->resc_request.num_sbs =
13418 bp->acquire_resp.resc.num_sbs;
13419 req->resc_request.num_mac_filters =
13420 bp->acquire_resp.resc.num_mac_filters;
13421 req->resc_request.num_vlan_filters =
13422 bp->acquire_resp.resc.num_vlan_filters;
13423 req->resc_request.num_mc_filters =
13424 bp->acquire_resp.resc.num_mc_filters;
13425
13426 /* Clear response buffer */
13427 memset(&bp->vf2pf_mbox->resp, 0,
13428 sizeof(union pfvf_tlvs));
13429 } else {
13430 /* PF reports error */
13431 BNX2X_ERR("Failed to get the requested amount of resources: %d. Breaking...\n",
13432 bp->acquire_resp.hdr.status);
13433 return -EAGAIN;
13434 }
13435 }
13436
13437 /* get HW info */
13438 bp->common.chip_id |= (bp->acquire_resp.pfdev_info.chip_num & 0xffff);
13439 bp->link_params.chip_id = bp->common.chip_id;
13440 bp->db_size = bp->acquire_resp.pfdev_info.db_size;
13441 bp->common.int_block = INT_BLOCK_IGU;
13442 bp->common.chip_port_mode = CHIP_2_PORT_MODE;
13443 bp->igu_dsb_id = -1;
13444 bp->mf_ov = 0;
13445 bp->mf_mode = 0;
13446 bp->common.flash_size = 0;
13447 bp->flags |=
13448 NO_WOL_FLAG | NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG | NO_FCOE_FLAG;
13449 bp->igu_sb_cnt = 1;
13450 bp->igu_base_sb = bp->acquire_resp.resc.hw_sbs[0].hw_sb_id;
13451 strlcpy(bp->fw_ver, bp->acquire_resp.pfdev_info.fw_ver,
13452 sizeof(bp->fw_ver));
13453
13454 if (is_valid_ether_addr(bp->acquire_resp.resc.current_mac_addr))
13455 memcpy(bp->dev->dev_addr,
13456 bp->acquire_resp.resc.current_mac_addr,
13457 ETH_ALEN);
13458
13459 return 0;
13460}
4513f925
AE		 13461
13462int bnx2x_vfpf_release(struct bnx2x *bp)
13463{
13464 struct vfpf_release_tlv *req = &bp->vf2pf_mbox->req.release;
13465 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13466 u32 rc = 0, vf_id;
13467
13468 /* clear mailbox and prep first tlv */
13469 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_RELEASE, sizeof(*req));
13470
13471 if (bnx2x_get_vf_id(bp, &vf_id))
13472 return -EAGAIN;
13473
13474 req->vf_id = vf_id;
13475
13476 /* add list termination tlv */
13477 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13478 sizeof(struct channel_list_end_tlv));
13479
13480 /* output tlvs list */
13481 bnx2x_dp_tlv_list(bp, req);
13482
13483 /* send release request */
13484 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13485
13486 if (rc)
13487 /* PF timeout */
13488 return rc;
13489 if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
13490 /* PF released us */
13491 DP(BNX2X_MSG_SP, "vf released\n");
13492 } else {
13493 /* PF reports error */
13494 BNX2X_ERR("PF failed our release request - are we out of sync? response status: %d\n",
13495 resp->hdr.status);
13496 return -EAGAIN;
13497 }
13498
13499 return 0;
13500}
8d9ac297
AE		 13501
13502/* Tell PF about SB addresses */
13503int bnx2x_vfpf_init(struct bnx2x *bp)
13504{
13505 struct vfpf_init_tlv *req = &bp->vf2pf_mbox->req.init;
13506 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13507 int rc, i;
13508
13509 /* clear mailbox and prep first tlv */
13510 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_INIT, sizeof(*req));
13511
13512 /* status blocks */
13513 for_each_eth_queue(bp, i)
13514 req->sb_addr[i] = (dma_addr_t)bnx2x_fp(bp, i,
13515 status_blk_mapping);
13516
13517 /* statistics - requests only supports single queue for now */
13518 req->stats_addr = bp->fw_stats_data_mapping +
13519 offsetof(struct bnx2x_fw_stats_data, queue_stats);
13520
13521 /* add list termination tlv */
13522 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13523 sizeof(struct channel_list_end_tlv));
13524
13525 /* output tlvs list */
13526 bnx2x_dp_tlv_list(bp, req);
13527
13528 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13529 if (rc)
13530 return rc;
13531
13532 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13533 BNX2X_ERR("INIT VF failed: %d. Breaking...\n",
13534 resp->hdr.status);
13535 return -EAGAIN;
13536 }
13537
13538 DP(BNX2X_MSG_SP, "INIT VF Succeeded\n");
13539 return 0;
13540}
13541
9b176b6b
AE		 13542/* CLOSE VF - opposite to INIT_VF */
13543void bnx2x_vfpf_close_vf(struct bnx2x *bp)
13544{
13545 struct vfpf_close_tlv *req = &bp->vf2pf_mbox->req.close;
13546 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13547 int i, rc;
13548 u32 vf_id;
13549
13550 /* If we haven't got a valid VF id, there is no sense to
13551 * continue with sending messages
13552 */
13553 if (bnx2x_get_vf_id(bp, &vf_id))
13554 goto free_irq;
13555
13556 /* Close the queues */
13557 for_each_queue(bp, i)
13558 bnx2x_vfpf_teardown_queue(bp, i);
13559
13560 /* clear mailbox and prep first tlv */
13561 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_CLOSE, sizeof(*req));
13562
13563 req->vf_id = vf_id;
13564
13565 /* add list termination tlv */
13566 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13567 sizeof(struct channel_list_end_tlv));
13568
13569 /* output tlvs list */
13570 bnx2x_dp_tlv_list(bp, req);
13571
13572 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13573
13574 if (rc)
13575 BNX2X_ERR("Sending CLOSE failed. rc was: %d\n", rc);
13576
13577 else if (resp->hdr.status != PFVF_STATUS_SUCCESS)
13578 BNX2X_ERR("Sending CLOSE failed: pf response was %d\n",
13579 resp->hdr.status);
13580
13581free_irq:
13582 /* Disable HW interrupts, NAPI */
13583 bnx2x_netif_stop(bp, 0);
13584 /* Delete all NAPI objects */
13585 bnx2x_del_all_napi(bp);
13586
13587 /* Release IRQs */
13588 bnx2x_free_irq(bp);
13589}
13590
8d9ac297
AE		 13591/* ask the pf to open a queue for the vf */
13592int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx)
13593{
13594 struct vfpf_setup_q_tlv *req = &bp->vf2pf_mbox->req.setup_q;
13595 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13596 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
13597 u16 tpa_agg_size = 0, flags = 0;
13598 int rc;
13599
13600 /* clear mailbox and prep first tlv */
13601 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SETUP_Q, sizeof(*req));
13602
13603 /* select tpa mode to request */
13604 if (!fp->disable_tpa) {
13605 flags |= VFPF_QUEUE_FLG_TPA;
13606 flags |= VFPF_QUEUE_FLG_TPA_IPV6;
13607 if (fp->mode == TPA_MODE_GRO)
13608 flags |= VFPF_QUEUE_FLG_TPA_GRO;
13609 tpa_agg_size = TPA_AGG_SIZE;
13610 }
13611
13612 /* calculate queue flags */
13613 flags |= VFPF_QUEUE_FLG_STATS;
13614 flags |= VFPF_QUEUE_FLG_CACHE_ALIGN;
13615 flags |= IS_MF_SD(bp) ? VFPF_QUEUE_FLG_OV : 0;
13616 flags |= VFPF_QUEUE_FLG_VLAN;
13617 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
13618
13619 /* Common */
13620 req->vf_qid = fp_idx;
13621 req->param_valid = VFPF_RXQ_VALID | VFPF_TXQ_VALID;
13622
13623 /* Rx */
13624 req->rxq.rcq_addr = fp->rx_comp_mapping;
13625 req->rxq.rcq_np_addr = fp->rx_comp_mapping + BCM_PAGE_SIZE;
13626 req->rxq.rxq_addr = fp->rx_desc_mapping;
13627 req->rxq.sge_addr = fp->rx_sge_mapping;
13628 req->rxq.vf_sb = fp_idx;
13629 req->rxq.sb_index = HC_INDEX_ETH_RX_CQ_CONS;
13630 req->rxq.hc_rate = bp->rx_ticks ? 1000000/bp->rx_ticks : 0;
13631 req->rxq.mtu = bp->dev->mtu;
13632 req->rxq.buf_sz = fp->rx_buf_size;
13633 req->rxq.sge_buf_sz = BCM_PAGE_SIZE * PAGES_PER_SGE;
13634 req->rxq.tpa_agg_sz = tpa_agg_size;
13635 req->rxq.max_sge_pkt = SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
13636 req->rxq.max_sge_pkt = ((req->rxq.max_sge_pkt + PAGES_PER_SGE - 1) &
13637 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
13638 req->rxq.flags = flags;
13639 req->rxq.drop_flags = 0;
13640 req->rxq.cache_line_log = BNX2X_RX_ALIGN_SHIFT;
13641 req->rxq.stat_id = -1; /* No stats at the moment */
13642
13643 /* Tx */
13644 req->txq.txq_addr = fp->txdata_ptr[FIRST_TX_COS_INDEX]->tx_desc_mapping;
13645 req->txq.vf_sb = fp_idx;
13646 req->txq.sb_index = HC_INDEX_ETH_TX_CQ_CONS_COS0;
13647 req->txq.hc_rate = bp->tx_ticks ? 1000000/bp->tx_ticks : 0;
13648 req->txq.flags = flags;
13649 req->txq.traffic_type = LLFC_TRAFFIC_TYPE_NW;
13650
13651 /* add list termination tlv */
13652 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13653 sizeof(struct channel_list_end_tlv));
13654
13655 /* output tlvs list */
13656 bnx2x_dp_tlv_list(bp, req);
13657
13658 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13659 if (rc)
13660 BNX2X_ERR("Sending SETUP_Q message for queue[%d] failed!\n",
13661 fp_idx);
13662
13663 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13664 BNX2X_ERR("Status of SETUP_Q for queue[%d] is %d\n",
13665 fp_idx, resp->hdr.status);
13666 return -EINVAL;
13667 }
13668 return rc;
13669}
13670
9b176b6b
AE		 13671int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx)
13672{
13673 struct vfpf_q_op_tlv *req = &bp->vf2pf_mbox->req.q_op;
13674 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13675 int rc;
13676
13677 /* clear mailbox and prep first tlv */
13678 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_TEARDOWN_Q,
13679 sizeof(*req));
13680
13681 req->vf_qid = qidx;
13682
13683 /* add list termination tlv */
13684 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13685 sizeof(struct channel_list_end_tlv));
13686
13687 /* output tlvs list */
13688 bnx2x_dp_tlv_list(bp, req);
13689
13690 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13691
13692 if (rc) {
13693 BNX2X_ERR("Sending TEARDOWN for queue %d failed: %d\n", qidx,
13694 rc);
13695 return rc;
13696 }
13697
13698 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13699 BNX2X_ERR("TEARDOWN for queue %d failed: %d\n", qidx,
13700 resp->hdr.status);
13701 return -EINVAL;
13702 }
13703
13704 return 0;
13705}
13706
8d9ac297
AE		 13707/* request pf to add a mac for the vf */
13708int bnx2x_vfpf_set_mac(struct bnx2x *bp)
13709{
13710 struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13711 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13712 int rc;
13713
13714 /* clear mailbox and prep first tlv */
13715 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13716 sizeof(*req));
13717
13718 req->flags = VFPF_SET_Q_FILTERS_MAC_VLAN_CHANGED;
13719 req->vf_qid = 0;
13720 req->n_mac_vlan_filters = 1;
13721 req->filters[0].flags =
13722 VFPF_Q_FILTER_DEST_MAC_VALID | VFPF_Q_FILTER_SET_MAC;
13723
13724 /* copy mac from device to request */
13725 memcpy(req->filters[0].mac, bp->dev->dev_addr, ETH_ALEN);
13726
13727 /* add list termination tlv */
13728 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13729 sizeof(struct channel_list_end_tlv));
13730
13731 /* output tlvs list */
13732 bnx2x_dp_tlv_list(bp, req);
13733
13734 /* send message to pf */
13735 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13736 if (rc) {
13737 BNX2X_ERR("failed to send message to pf. rc was %d\n", rc);
13738 return rc;
13739 }
13740
13741 /* PF failed the transaction */
13742 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13743 BNX2X_ERR("vfpf SET MAC failed: %d\n", resp->hdr.status);
13744 return -EINVAL;
13745 }
13746
13747 return 0;
13748}
381ac16b
AE		 13749
13750int bnx2x_vfpf_set_mcast(struct net_device *dev)
13751{
13752 struct bnx2x *bp = netdev_priv(dev);
13753 struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13754 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13755 int rc, i = 0;
13756 struct netdev_hw_addr *ha;
13757
13758 if (bp->state != BNX2X_STATE_OPEN) {
13759 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
13760 return -EINVAL;
13761 }
13762
13763 /* clear mailbox and prep first tlv */
13764 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13765 sizeof(*req));
13766
13767 /* Get Rx mode requested */
13768 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
13769
13770 netdev_for_each_mc_addr(ha, dev) {
13771 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
13772 bnx2x_mc_addr(ha));
13773 memcpy(req->multicast[i], bnx2x_mc_addr(ha), ETH_ALEN);
13774 i++;
13775 }
13776
13777 /* We support four PFVF_MAX_MULTICAST_PER_VF mcast
13778 * addresses tops
13779 */
13780 if (i >= PFVF_MAX_MULTICAST_PER_VF) {
13781 DP(NETIF_MSG_IFUP,
13782 "VF supports not more than %d multicast MAC addresses\n",
13783 PFVF_MAX_MULTICAST_PER_VF);
13784 return -EINVAL;
13785 }
13786
13787 req->n_multicast = i;
13788 req->flags |= VFPF_SET_Q_FILTERS_MULTICAST_CHANGED;
13789 req->vf_qid = 0;
13790
13791 /* add list termination tlv */
13792 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13793 sizeof(struct channel_list_end_tlv));
13794
13795 /* output tlvs list */
13796 bnx2x_dp_tlv_list(bp, req);
13797
13798 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13799 if (rc) {
13800 BNX2X_ERR("Sending a message failed: %d\n", rc);
13801 return rc;
13802 }
13803
13804 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13805 BNX2X_ERR("Set Rx mode/multicast failed: %d\n",
13806 resp->hdr.status);
13807 return -EINVAL;
13808 }
13809
13810 return 0;
13811}
13812
13813int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp)
13814{
13815 int mode = bp->rx_mode;
13816 struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13817 struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13818 int rc;
13819
13820 /* clear mailbox and prep first tlv */
13821 bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13822 sizeof(*req));
13823
13824 DP(NETIF_MSG_IFUP, "Rx mode is %d\n", mode);
13825
13826 switch (mode) {
13827 case BNX2X_RX_MODE_NONE: /* no Rx */
13828 req->rx_mask = VFPF_RX_MASK_ACCEPT_NONE;
13829 break;
13830 case BNX2X_RX_MODE_NORMAL:
13831 req->rx_mask = VFPF_RX_MASK_ACCEPT_MATCHED_MULTICAST;
13832 req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST;
13833 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
13834 break;
13835 case BNX2X_RX_MODE_ALLMULTI:
13836 req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_MULTICAST;
13837 req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST;
13838 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
13839 break;
13840 case BNX2X_RX_MODE_PROMISC:
13841 req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_UNICAST;
13842 req->rx_mask |= VFPF_RX_MASK_ACCEPT_ALL_MULTICAST;
13843 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
13844 break;
13845 default:
13846 BNX2X_ERR("BAD rx mode (%d)\n", mode);
13847 return -EINVAL;
13848 }
13849
13850 req->flags |= VFPF_SET_Q_FILTERS_RX_MASK_CHANGED;
13851 req->vf_qid = 0;
13852
13853 /* add list termination tlv */
13854 bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13855 sizeof(struct channel_list_end_tlv));
13856
13857 /* output tlvs list */
13858 bnx2x_dp_tlv_list(bp, req);
13859
13860 rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13861 if (rc)
13862 BNX2X_ERR("Sending a message failed: %d\n", rc);
13863
13864 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13865 BNX2X_ERR("Set Rx mode failed: %d\n", resp->hdr.status);
13866 return -EINVAL;
13867 }
13868
13869 return rc;
13870}
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