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Commit | Line | Data |
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34f80b04 | 1 | /* bnx2x_main.c: Broadcom Everest network driver. |
a2fbb9ea | 2 | * |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
ca00392c | 13 | * Slowpath and fastpath rework by Vladislav Zolotarov |
c14423fe | 14 | * Statistics and Link management by Yitchak Gertner |
a2fbb9ea ET |
15 | * |
16 | */ | |
17 | ||
f1deab50 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
a2fbb9ea ET |
20 | #include <linux/module.h> |
21 | #include <linux/moduleparam.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/device.h> /* for dev_info() */ | |
24 | #include <linux/timer.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
a2fbb9ea ET |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/bitops.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/byteorder.h> | |
39 | #include <linux/time.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/mii.h> | |
0c6671b0 | 42 | #include <linux/if_vlan.h> |
a2fbb9ea | 43 | #include <net/ip.h> |
619c5cb6 | 44 | #include <net/ipv6.h> |
a2fbb9ea ET |
45 | #include <net/tcp.h> |
46 | #include <net/checksum.h> | |
34f80b04 | 47 | #include <net/ip6_checksum.h> |
a2fbb9ea ET |
48 | #include <linux/workqueue.h> |
49 | #include <linux/crc32.h> | |
34f80b04 | 50 | #include <linux/crc32c.h> |
a2fbb9ea ET |
51 | #include <linux/prefetch.h> |
52 | #include <linux/zlib.h> | |
a2fbb9ea | 53 | #include <linux/io.h> |
452427b0 | 54 | #include <linux/semaphore.h> |
45229b42 | 55 | #include <linux/stringify.h> |
7ab24bfd | 56 | #include <linux/vmalloc.h> |
a2fbb9ea | 57 | |
a2fbb9ea ET |
58 | #include "bnx2x.h" |
59 | #include "bnx2x_init.h" | |
94a78b79 | 60 | #include "bnx2x_init_ops.h" |
9f6c9258 | 61 | #include "bnx2x_cmn.h" |
1ab4434c | 62 | #include "bnx2x_vfpf.h" |
e4901dde | 63 | #include "bnx2x_dcb.h" |
042181f5 | 64 | #include "bnx2x_sp.h" |
a2fbb9ea | 65 | |
94a78b79 VZ |
66 | #include <linux/firmware.h> |
67 | #include "bnx2x_fw_file_hdr.h" | |
68 | /* FW files */ | |
45229b42 BH |
69 | #define FW_FILE_VERSION \ |
70 | __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ | |
71 | __stringify(BCM_5710_FW_MINOR_VERSION) "." \ | |
72 | __stringify(BCM_5710_FW_REVISION_VERSION) "." \ | |
73 | __stringify(BCM_5710_FW_ENGINEERING_VERSION) | |
560131f3 DK |
74 | #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" |
75 | #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" | |
f2e0899f | 76 | #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" |
94a78b79 | 77 | |
34f80b04 EG |
78 | /* Time in jiffies before concluding the transmitter is hung */ |
79 | #define TX_TIMEOUT (5*HZ) | |
a2fbb9ea | 80 | |
0329aba1 | 81 | static char version[] = |
619c5cb6 | 82 | "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver " |
a2fbb9ea ET |
83 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
84 | ||
24e3fcef | 85 | MODULE_AUTHOR("Eliezer Tamir"); |
f2e0899f | 86 | MODULE_DESCRIPTION("Broadcom NetXtreme II " |
619c5cb6 VZ |
87 | "BCM57710/57711/57711E/" |
88 | "57712/57712_MF/57800/57800_MF/57810/57810_MF/" | |
89 | "57840/57840_MF Driver"); | |
a2fbb9ea ET |
90 | MODULE_LICENSE("GPL"); |
91 | MODULE_VERSION(DRV_MODULE_VERSION); | |
45229b42 BH |
92 | MODULE_FIRMWARE(FW_FILE_NAME_E1); |
93 | MODULE_FIRMWARE(FW_FILE_NAME_E1H); | |
f2e0899f | 94 | MODULE_FIRMWARE(FW_FILE_NAME_E2); |
a2fbb9ea | 95 | |
d6214d7a | 96 | int num_queues; |
54b9ddaa | 97 | module_param(num_queues, int, 0); |
96305234 DK |
98 | MODULE_PARM_DESC(num_queues, |
99 | " Set number of queues (default is as a number of CPUs)"); | |
555f6c78 | 100 | |
19680c48 | 101 | static int disable_tpa; |
19680c48 | 102 | module_param(disable_tpa, int, 0); |
9898f86d | 103 | MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); |
8badd27a | 104 | |
0e8d2ec5 | 105 | int int_mode; |
8badd27a | 106 | module_param(int_mode, int, 0); |
619c5cb6 | 107 | MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " |
cdaa7cb8 | 108 | "(1 INT#x; 2 MSI)"); |
8badd27a | 109 | |
a18f5128 EG |
110 | static int dropless_fc; |
111 | module_param(dropless_fc, int, 0); | |
112 | MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); | |
113 | ||
8d5726c4 EG |
114 | static int mrrs = -1; |
115 | module_param(mrrs, int, 0); | |
116 | MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); | |
117 | ||
9898f86d | 118 | static int debug; |
a2fbb9ea | 119 | module_param(debug, int, 0); |
9898f86d EG |
120 | MODULE_PARM_DESC(debug, " Default debug msglevel"); |
121 | ||
619c5cb6 | 122 | struct workqueue_struct *bnx2x_wq; |
ec6ba945 | 123 | |
1ef1d45a BW |
124 | struct bnx2x_mac_vals { |
125 | u32 xmac_addr; | |
126 | u32 xmac_val; | |
127 | u32 emac_addr; | |
128 | u32 emac_val; | |
129 | u32 umac_addr; | |
130 | u32 umac_val; | |
131 | u32 bmac_addr; | |
132 | u32 bmac_val[2]; | |
133 | }; | |
134 | ||
a2fbb9ea ET |
135 | enum bnx2x_board_type { |
136 | BCM57710 = 0, | |
619c5cb6 VZ |
137 | BCM57711, |
138 | BCM57711E, | |
139 | BCM57712, | |
140 | BCM57712_MF, | |
1ab4434c | 141 | BCM57712_VF, |
619c5cb6 VZ |
142 | BCM57800, |
143 | BCM57800_MF, | |
1ab4434c | 144 | BCM57800_VF, |
619c5cb6 VZ |
145 | BCM57810, |
146 | BCM57810_MF, | |
1ab4434c | 147 | BCM57810_VF, |
c3def943 YM |
148 | BCM57840_4_10, |
149 | BCM57840_2_20, | |
7e8e02df | 150 | BCM57840_MF, |
1ab4434c | 151 | BCM57840_VF, |
7e8e02df | 152 | BCM57811, |
1ab4434c AE |
153 | BCM57811_MF, |
154 | BCM57840_O, | |
155 | BCM57840_MFO, | |
156 | BCM57811_VF | |
a2fbb9ea ET |
157 | }; |
158 | ||
34f80b04 | 159 | /* indexed by board_type, above */ |
53a10565 | 160 | static struct { |
a2fbb9ea | 161 | char *name; |
0329aba1 | 162 | } board_info[] = { |
1ab4434c AE |
163 | [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" }, |
164 | [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" }, | |
165 | [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" }, | |
166 | [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" }, | |
167 | [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" }, | |
168 | [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" }, | |
169 | [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" }, | |
170 | [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" }, | |
171 | [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" }, | |
172 | [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" }, | |
173 | [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" }, | |
174 | [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" }, | |
175 | [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" }, | |
176 | [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" }, | |
177 | [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
178 | [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }, | |
179 | [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" }, | |
180 | [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" }, | |
181 | [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" }, | |
182 | [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" }, | |
183 | [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" } | |
a2fbb9ea ET |
184 | }; |
185 | ||
619c5cb6 VZ |
186 | #ifndef PCI_DEVICE_ID_NX2_57710 |
187 | #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 | |
188 | #endif | |
189 | #ifndef PCI_DEVICE_ID_NX2_57711 | |
190 | #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 | |
191 | #endif | |
192 | #ifndef PCI_DEVICE_ID_NX2_57711E | |
193 | #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E | |
194 | #endif | |
195 | #ifndef PCI_DEVICE_ID_NX2_57712 | |
196 | #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 | |
197 | #endif | |
198 | #ifndef PCI_DEVICE_ID_NX2_57712_MF | |
199 | #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF | |
200 | #endif | |
8395be5e AE |
201 | #ifndef PCI_DEVICE_ID_NX2_57712_VF |
202 | #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF | |
203 | #endif | |
619c5cb6 VZ |
204 | #ifndef PCI_DEVICE_ID_NX2_57800 |
205 | #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 | |
206 | #endif | |
207 | #ifndef PCI_DEVICE_ID_NX2_57800_MF | |
208 | #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF | |
209 | #endif | |
8395be5e AE |
210 | #ifndef PCI_DEVICE_ID_NX2_57800_VF |
211 | #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF | |
212 | #endif | |
619c5cb6 VZ |
213 | #ifndef PCI_DEVICE_ID_NX2_57810 |
214 | #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 | |
215 | #endif | |
216 | #ifndef PCI_DEVICE_ID_NX2_57810_MF | |
217 | #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF | |
218 | #endif | |
c3def943 YM |
219 | #ifndef PCI_DEVICE_ID_NX2_57840_O |
220 | #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE | |
221 | #endif | |
8395be5e AE |
222 | #ifndef PCI_DEVICE_ID_NX2_57810_VF |
223 | #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF | |
224 | #endif | |
c3def943 YM |
225 | #ifndef PCI_DEVICE_ID_NX2_57840_4_10 |
226 | #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 | |
227 | #endif | |
228 | #ifndef PCI_DEVICE_ID_NX2_57840_2_20 | |
229 | #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 | |
230 | #endif | |
231 | #ifndef PCI_DEVICE_ID_NX2_57840_MFO | |
232 | #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE | |
619c5cb6 VZ |
233 | #endif |
234 | #ifndef PCI_DEVICE_ID_NX2_57840_MF | |
235 | #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF | |
236 | #endif | |
8395be5e AE |
237 | #ifndef PCI_DEVICE_ID_NX2_57840_VF |
238 | #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF | |
239 | #endif | |
7e8e02df BW |
240 | #ifndef PCI_DEVICE_ID_NX2_57811 |
241 | #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 | |
242 | #endif | |
243 | #ifndef PCI_DEVICE_ID_NX2_57811_MF | |
244 | #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF | |
245 | #endif | |
8395be5e AE |
246 | #ifndef PCI_DEVICE_ID_NX2_57811_VF |
247 | #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF | |
248 | #endif | |
249 | ||
a3aa1884 | 250 | static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { |
e4ed7113 EG |
251 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, |
252 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, | |
253 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, | |
f2e0899f | 254 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, |
619c5cb6 | 255 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, |
8395be5e | 256 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, |
619c5cb6 VZ |
257 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, |
258 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, | |
8395be5e | 259 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, |
619c5cb6 VZ |
260 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, |
261 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, | |
c3def943 YM |
262 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, |
263 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, | |
264 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, | |
8395be5e | 265 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, |
c3def943 | 266 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, |
619c5cb6 | 267 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, |
8395be5e | 268 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, |
7e8e02df BW |
269 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, |
270 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, | |
8395be5e | 271 | { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, |
a2fbb9ea ET |
272 | { 0 } |
273 | }; | |
274 | ||
275 | MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); | |
276 | ||
452427b0 YM |
277 | /* Global resources for unloading a previously loaded device */ |
278 | #define BNX2X_PREV_WAIT_NEEDED 1 | |
279 | static DEFINE_SEMAPHORE(bnx2x_prev_sem); | |
280 | static LIST_HEAD(bnx2x_prev_list); | |
a2fbb9ea ET |
281 | /**************************************************************************** |
282 | * General service functions | |
283 | ****************************************************************************/ | |
284 | ||
1191cb83 | 285 | static void __storm_memset_dma_mapping(struct bnx2x *bp, |
619c5cb6 VZ |
286 | u32 addr, dma_addr_t mapping) |
287 | { | |
288 | REG_WR(bp, addr, U64_LO(mapping)); | |
289 | REG_WR(bp, addr + 4, U64_HI(mapping)); | |
290 | } | |
291 | ||
1191cb83 ED |
292 | static void storm_memset_spq_addr(struct bnx2x *bp, |
293 | dma_addr_t mapping, u16 abs_fid) | |
619c5cb6 VZ |
294 | { |
295 | u32 addr = XSEM_REG_FAST_MEMORY + | |
296 | XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); | |
297 | ||
298 | __storm_memset_dma_mapping(bp, addr, mapping); | |
299 | } | |
300 | ||
1191cb83 ED |
301 | static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, |
302 | u16 pf_id) | |
523224a3 | 303 | { |
619c5cb6 VZ |
304 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), |
305 | pf_id); | |
306 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), | |
307 | pf_id); | |
308 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), | |
309 | pf_id); | |
310 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), | |
311 | pf_id); | |
523224a3 DK |
312 | } |
313 | ||
1191cb83 ED |
314 | static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, |
315 | u8 enable) | |
619c5cb6 VZ |
316 | { |
317 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), | |
318 | enable); | |
319 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), | |
320 | enable); | |
321 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), | |
322 | enable); | |
323 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), | |
324 | enable); | |
325 | } | |
523224a3 | 326 | |
1191cb83 ED |
327 | static void storm_memset_eq_data(struct bnx2x *bp, |
328 | struct event_ring_data *eq_data, | |
523224a3 DK |
329 | u16 pfid) |
330 | { | |
331 | size_t size = sizeof(struct event_ring_data); | |
332 | ||
333 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); | |
334 | ||
335 | __storm_memset_struct(bp, addr, size, (u32 *)eq_data); | |
336 | } | |
337 | ||
1191cb83 ED |
338 | static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, |
339 | u16 pfid) | |
523224a3 DK |
340 | { |
341 | u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); | |
342 | REG_WR16(bp, addr, eq_prod); | |
343 | } | |
344 | ||
a2fbb9ea ET |
345 | /* used only at init |
346 | * locking is done by mcp | |
347 | */ | |
8d96286a | 348 | static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) |
a2fbb9ea ET |
349 | { |
350 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
351 | pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); | |
352 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
353 | PCICFG_VENDOR_ID_OFFSET); | |
354 | } | |
355 | ||
a2fbb9ea ET |
356 | static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) |
357 | { | |
358 | u32 val; | |
359 | ||
360 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); | |
361 | pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); | |
362 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
363 | PCICFG_VENDOR_ID_OFFSET); | |
364 | ||
365 | return val; | |
366 | } | |
a2fbb9ea | 367 | |
f2e0899f DK |
368 | #define DMAE_DP_SRC_GRC "grc src_addr [%08x]" |
369 | #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" | |
370 | #define DMAE_DP_DST_GRC "grc dst_addr [%08x]" | |
371 | #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" | |
372 | #define DMAE_DP_DST_NONE "dst_addr [none]" | |
373 | ||
6bf07b8e YM |
374 | static void bnx2x_dp_dmae(struct bnx2x *bp, |
375 | struct dmae_command *dmae, int msglvl) | |
fd1fc79d AE |
376 | { |
377 | u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; | |
6bf07b8e | 378 | int i; |
fd1fc79d AE |
379 | |
380 | switch (dmae->opcode & DMAE_COMMAND_DST) { | |
381 | case DMAE_CMD_DST_PCI: | |
382 | if (src_type == DMAE_CMD_SRC_PCI) | |
383 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
384 | "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" | |
385 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
386 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
387 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
388 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
389 | dmae->comp_val); | |
390 | else | |
391 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
392 | "src [%08x], len [%d*4], dst [%x:%08x]\n" | |
393 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
394 | dmae->opcode, dmae->src_addr_lo >> 2, | |
395 | dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, | |
396 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
397 | dmae->comp_val); | |
398 | break; | |
399 | case DMAE_CMD_DST_GRC: | |
400 | if (src_type == DMAE_CMD_SRC_PCI) | |
401 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
402 | "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" | |
403 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
404 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
405 | dmae->len, dmae->dst_addr_lo >> 2, | |
406 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
407 | dmae->comp_val); | |
408 | else | |
409 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
410 | "src [%08x], len [%d*4], dst [%08x]\n" | |
411 | "comp_addr [%x:%08x], comp_val 0x%08x\n", | |
412 | dmae->opcode, dmae->src_addr_lo >> 2, | |
413 | dmae->len, dmae->dst_addr_lo >> 2, | |
414 | dmae->comp_addr_hi, dmae->comp_addr_lo, | |
415 | dmae->comp_val); | |
416 | break; | |
417 | default: | |
418 | if (src_type == DMAE_CMD_SRC_PCI) | |
419 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
420 | "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" | |
421 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
422 | dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, | |
423 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
424 | dmae->comp_val); | |
425 | else | |
426 | DP(msglvl, "DMAE: opcode 0x%08x\n" | |
427 | "src_addr [%08x] len [%d * 4] dst_addr [none]\n" | |
428 | "comp_addr [%x:%08x] comp_val 0x%08x\n", | |
429 | dmae->opcode, dmae->src_addr_lo >> 2, | |
430 | dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, | |
431 | dmae->comp_val); | |
432 | break; | |
433 | } | |
6bf07b8e YM |
434 | |
435 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) | |
436 | DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", | |
437 | i, *(((u32 *)dmae) + i)); | |
fd1fc79d | 438 | } |
f2e0899f | 439 | |
a2fbb9ea | 440 | /* copy command into DMAE command memory and set DMAE command go */ |
6c719d00 | 441 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) |
a2fbb9ea ET |
442 | { |
443 | u32 cmd_offset; | |
444 | int i; | |
445 | ||
446 | cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); | |
447 | for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { | |
448 | REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); | |
a2fbb9ea ET |
449 | } |
450 | REG_WR(bp, dmae_reg_go_c[idx], 1); | |
451 | } | |
452 | ||
f2e0899f | 453 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) |
a2fbb9ea | 454 | { |
f2e0899f DK |
455 | return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | |
456 | DMAE_CMD_C_ENABLE); | |
457 | } | |
ad8d3948 | 458 | |
f2e0899f DK |
459 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) |
460 | { | |
461 | return opcode & ~DMAE_CMD_SRC_RESET; | |
462 | } | |
ad8d3948 | 463 | |
f2e0899f DK |
464 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, |
465 | bool with_comp, u8 comp_type) | |
466 | { | |
467 | u32 opcode = 0; | |
468 | ||
469 | opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | | |
470 | (dst_type << DMAE_COMMAND_DST_SHIFT)); | |
ad8d3948 | 471 | |
f2e0899f DK |
472 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
473 | ||
474 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | |
3395a033 DK |
475 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
476 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | |
f2e0899f | 477 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
a2fbb9ea | 478 | |
a2fbb9ea | 479 | #ifdef __BIG_ENDIAN |
f2e0899f | 480 | opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; |
a2fbb9ea | 481 | #else |
f2e0899f | 482 | opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; |
a2fbb9ea | 483 | #endif |
f2e0899f DK |
484 | if (with_comp) |
485 | opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); | |
486 | return opcode; | |
487 | } | |
488 | ||
fd1fc79d | 489 | void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, |
8d96286a | 490 | struct dmae_command *dmae, |
491 | u8 src_type, u8 dst_type) | |
f2e0899f DK |
492 | { |
493 | memset(dmae, 0, sizeof(struct dmae_command)); | |
494 | ||
495 | /* set the opcode */ | |
496 | dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, | |
497 | true, DMAE_COMP_PCI); | |
498 | ||
499 | /* fill in the completion parameters */ | |
500 | dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); | |
501 | dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); | |
502 | dmae->comp_val = DMAE_COMP_VAL; | |
503 | } | |
504 | ||
fd1fc79d AE |
505 | /* issue a dmae command over the init-channel and wait for completion */ |
506 | int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae) | |
f2e0899f DK |
507 | { |
508 | u32 *wb_comp = bnx2x_sp(bp, wb_comp); | |
5e374b5a | 509 | int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; |
f2e0899f DK |
510 | int rc = 0; |
511 | ||
6bf07b8e YM |
512 | bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); |
513 | ||
514 | /* Lock the dmae channel. Disable BHs to prevent a dead-lock | |
619c5cb6 VZ |
515 | * as long as this code is called both from syscall context and |
516 | * from ndo_set_rx_mode() flow that may be called from BH. | |
517 | */ | |
6e30dd4e | 518 | spin_lock_bh(&bp->dmae_lock); |
5ff7b6d4 | 519 | |
f2e0899f | 520 | /* reset completion */ |
a2fbb9ea ET |
521 | *wb_comp = 0; |
522 | ||
f2e0899f DK |
523 | /* post the command on the channel used for initializations */ |
524 | bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); | |
a2fbb9ea | 525 | |
f2e0899f | 526 | /* wait for completion */ |
a2fbb9ea | 527 | udelay(5); |
f2e0899f | 528 | while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { |
ad8d3948 | 529 | |
95c6c616 AE |
530 | if (!cnt || |
531 | (bp->recovery_state != BNX2X_RECOVERY_DONE && | |
532 | bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
c3eefaf6 | 533 | BNX2X_ERR("DMAE timeout!\n"); |
f2e0899f DK |
534 | rc = DMAE_TIMEOUT; |
535 | goto unlock; | |
a2fbb9ea | 536 | } |
ad8d3948 | 537 | cnt--; |
f2e0899f | 538 | udelay(50); |
a2fbb9ea | 539 | } |
f2e0899f DK |
540 | if (*wb_comp & DMAE_PCI_ERR_FLAG) { |
541 | BNX2X_ERR("DMAE PCI error!\n"); | |
542 | rc = DMAE_PCI_ERROR; | |
543 | } | |
544 | ||
f2e0899f | 545 | unlock: |
6e30dd4e | 546 | spin_unlock_bh(&bp->dmae_lock); |
f2e0899f DK |
547 | return rc; |
548 | } | |
549 | ||
550 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
551 | u32 len32) | |
552 | { | |
6bf07b8e | 553 | int rc; |
f2e0899f DK |
554 | struct dmae_command dmae; |
555 | ||
556 | if (!bp->dmae_ready) { | |
557 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
558 | ||
127a425e AE |
559 | if (CHIP_IS_E1(bp)) |
560 | bnx2x_init_ind_wr(bp, dst_addr, data, len32); | |
561 | else | |
562 | bnx2x_init_str_wr(bp, dst_addr, data, len32); | |
f2e0899f DK |
563 | return; |
564 | } | |
565 | ||
566 | /* set opcode and fixed command fields */ | |
567 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); | |
568 | ||
569 | /* fill in addresses and len */ | |
570 | dmae.src_addr_lo = U64_LO(dma_addr); | |
571 | dmae.src_addr_hi = U64_HI(dma_addr); | |
572 | dmae.dst_addr_lo = dst_addr >> 2; | |
573 | dmae.dst_addr_hi = 0; | |
574 | dmae.len = len32; | |
575 | ||
f2e0899f | 576 | /* issue the command and wait for completion */ |
6bf07b8e YM |
577 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae); |
578 | if (rc) { | |
579 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
580 | bnx2x_panic(); | |
581 | } | |
a2fbb9ea ET |
582 | } |
583 | ||
c18487ee | 584 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) |
a2fbb9ea | 585 | { |
6bf07b8e | 586 | int rc; |
5ff7b6d4 | 587 | struct dmae_command dmae; |
ad8d3948 EG |
588 | |
589 | if (!bp->dmae_ready) { | |
590 | u32 *data = bnx2x_sp(bp, wb_data[0]); | |
591 | int i; | |
592 | ||
51c1a580 | 593 | if (CHIP_IS_E1(bp)) |
127a425e AE |
594 | for (i = 0; i < len32; i++) |
595 | data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); | |
51c1a580 | 596 | else |
127a425e AE |
597 | for (i = 0; i < len32; i++) |
598 | data[i] = REG_RD(bp, src_addr + i*4); | |
599 | ||
ad8d3948 EG |
600 | return; |
601 | } | |
602 | ||
f2e0899f DK |
603 | /* set opcode and fixed command fields */ |
604 | bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); | |
a2fbb9ea | 605 | |
f2e0899f | 606 | /* fill in addresses and len */ |
5ff7b6d4 EG |
607 | dmae.src_addr_lo = src_addr >> 2; |
608 | dmae.src_addr_hi = 0; | |
609 | dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); | |
610 | dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); | |
611 | dmae.len = len32; | |
ad8d3948 | 612 | |
f2e0899f | 613 | /* issue the command and wait for completion */ |
6bf07b8e YM |
614 | rc = bnx2x_issue_dmae_with_comp(bp, &dmae); |
615 | if (rc) { | |
616 | BNX2X_ERR("DMAE returned failure %d\n", rc); | |
617 | bnx2x_panic(); | |
c957d09f | 618 | } |
ad8d3948 EG |
619 | } |
620 | ||
8d96286a | 621 | static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, |
622 | u32 addr, u32 len) | |
573f2035 | 623 | { |
02e3c6cb | 624 | int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); |
573f2035 EG |
625 | int offset = 0; |
626 | ||
02e3c6cb | 627 | while (len > dmae_wr_max) { |
573f2035 | 628 | bnx2x_write_dmae(bp, phys_addr + offset, |
02e3c6cb VZ |
629 | addr + offset, dmae_wr_max); |
630 | offset += dmae_wr_max * 4; | |
631 | len -= dmae_wr_max; | |
573f2035 EG |
632 | } |
633 | ||
634 | bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); | |
635 | } | |
636 | ||
a2fbb9ea ET |
637 | static int bnx2x_mc_assert(struct bnx2x *bp) |
638 | { | |
a2fbb9ea | 639 | char last_idx; |
34f80b04 EG |
640 | int i, rc = 0; |
641 | u32 row0, row1, row2, row3; | |
642 | ||
643 | /* XSTORM */ | |
644 | last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM + | |
645 | XSTORM_ASSERT_LIST_INDEX_OFFSET); | |
646 | if (last_idx) | |
647 | BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
648 | ||
649 | /* print the asserts */ | |
650 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
651 | ||
652 | row0 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
653 | XSTORM_ASSERT_LIST_OFFSET(i)); | |
654 | row1 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
655 | XSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
656 | row2 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
657 | XSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
658 | row3 = REG_RD(bp, BAR_XSTRORM_INTMEM + | |
659 | XSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
660 | ||
661 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 662 | BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
663 | i, row3, row2, row1, row0); |
664 | rc++; | |
665 | } else { | |
666 | break; | |
667 | } | |
668 | } | |
669 | ||
670 | /* TSTORM */ | |
671 | last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM + | |
672 | TSTORM_ASSERT_LIST_INDEX_OFFSET); | |
673 | if (last_idx) | |
674 | BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
675 | ||
676 | /* print the asserts */ | |
677 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
678 | ||
679 | row0 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
680 | TSTORM_ASSERT_LIST_OFFSET(i)); | |
681 | row1 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
682 | TSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
683 | row2 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
684 | TSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
685 | row3 = REG_RD(bp, BAR_TSTRORM_INTMEM + | |
686 | TSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
687 | ||
688 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 689 | BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
690 | i, row3, row2, row1, row0); |
691 | rc++; | |
692 | } else { | |
693 | break; | |
694 | } | |
695 | } | |
696 | ||
697 | /* CSTORM */ | |
698 | last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM + | |
699 | CSTORM_ASSERT_LIST_INDEX_OFFSET); | |
700 | if (last_idx) | |
701 | BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
702 | ||
703 | /* print the asserts */ | |
704 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
705 | ||
706 | row0 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
707 | CSTORM_ASSERT_LIST_OFFSET(i)); | |
708 | row1 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
709 | CSTORM_ASSERT_LIST_OFFSET(i) + 4); | |
710 | row2 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
711 | CSTORM_ASSERT_LIST_OFFSET(i) + 8); | |
712 | row3 = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
713 | CSTORM_ASSERT_LIST_OFFSET(i) + 12); | |
714 | ||
715 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 716 | BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
717 | i, row3, row2, row1, row0); |
718 | rc++; | |
719 | } else { | |
720 | break; | |
721 | } | |
722 | } | |
723 | ||
724 | /* USTORM */ | |
725 | last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM + | |
726 | USTORM_ASSERT_LIST_INDEX_OFFSET); | |
727 | if (last_idx) | |
728 | BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); | |
729 | ||
730 | /* print the asserts */ | |
731 | for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { | |
732 | ||
733 | row0 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
734 | USTORM_ASSERT_LIST_OFFSET(i)); | |
735 | row1 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
736 | USTORM_ASSERT_LIST_OFFSET(i) + 4); | |
737 | row2 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
738 | USTORM_ASSERT_LIST_OFFSET(i) + 8); | |
739 | row3 = REG_RD(bp, BAR_USTRORM_INTMEM + | |
740 | USTORM_ASSERT_LIST_OFFSET(i) + 12); | |
741 | ||
742 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | |
51c1a580 | 743 | BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", |
34f80b04 EG |
744 | i, row3, row2, row1, row0); |
745 | rc++; | |
746 | } else { | |
747 | break; | |
a2fbb9ea ET |
748 | } |
749 | } | |
34f80b04 | 750 | |
a2fbb9ea ET |
751 | return rc; |
752 | } | |
c14423fe | 753 | |
7a25cc73 | 754 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) |
a2fbb9ea | 755 | { |
7a25cc73 | 756 | u32 addr, val; |
a2fbb9ea | 757 | u32 mark, offset; |
4781bfad | 758 | __be32 data[9]; |
a2fbb9ea | 759 | int word; |
f2e0899f | 760 | u32 trace_shmem_base; |
2145a920 VZ |
761 | if (BP_NOMCP(bp)) { |
762 | BNX2X_ERR("NO MCP - can not dump\n"); | |
763 | return; | |
764 | } | |
7a25cc73 DK |
765 | netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", |
766 | (bp->common.bc_ver & 0xff0000) >> 16, | |
767 | (bp->common.bc_ver & 0xff00) >> 8, | |
768 | (bp->common.bc_ver & 0xff)); | |
769 | ||
770 | val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); | |
771 | if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) | |
51c1a580 | 772 | BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); |
cdaa7cb8 | 773 | |
f2e0899f DK |
774 | if (BP_PATH(bp) == 0) |
775 | trace_shmem_base = bp->common.shmem_base; | |
776 | else | |
777 | trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); | |
de128804 DK |
778 | addr = trace_shmem_base - 0x800; |
779 | ||
780 | /* validate TRCB signature */ | |
781 | mark = REG_RD(bp, addr); | |
782 | if (mark != MFW_TRACE_SIGNATURE) { | |
783 | BNX2X_ERR("Trace buffer signature is missing."); | |
784 | return ; | |
785 | } | |
786 | ||
787 | /* read cyclic buffer pointer */ | |
788 | addr += 4; | |
cdaa7cb8 | 789 | mark = REG_RD(bp, addr); |
f2e0899f DK |
790 | mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) |
791 | + ((mark + 0x3) & ~0x3) - 0x08000000; | |
7a25cc73 | 792 | printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); |
a2fbb9ea | 793 | |
7a25cc73 | 794 | printk("%s", lvl); |
2de67439 YM |
795 | |
796 | /* dump buffer after the mark */ | |
f2e0899f | 797 | for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { |
a2fbb9ea | 798 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 799 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 800 | data[8] = 0x0; |
7995c64e | 801 | pr_cont("%s", (char *)data); |
a2fbb9ea | 802 | } |
2de67439 YM |
803 | |
804 | /* dump buffer before the mark */ | |
cdaa7cb8 | 805 | for (offset = addr + 4; offset <= mark; offset += 0x8*4) { |
a2fbb9ea | 806 | for (word = 0; word < 8; word++) |
cdaa7cb8 | 807 | data[word] = htonl(REG_RD(bp, offset + 4*word)); |
a2fbb9ea | 808 | data[8] = 0x0; |
7995c64e | 809 | pr_cont("%s", (char *)data); |
a2fbb9ea | 810 | } |
7a25cc73 DK |
811 | printk("%s" "end of fw dump\n", lvl); |
812 | } | |
813 | ||
1191cb83 | 814 | static void bnx2x_fw_dump(struct bnx2x *bp) |
7a25cc73 DK |
815 | { |
816 | bnx2x_fw_dump_lvl(bp, KERN_ERR); | |
a2fbb9ea ET |
817 | } |
818 | ||
823e1d90 YM |
819 | static void bnx2x_hc_int_disable(struct bnx2x *bp) |
820 | { | |
821 | int port = BP_PORT(bp); | |
822 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; | |
823 | u32 val = REG_RD(bp, addr); | |
824 | ||
825 | /* in E1 we must use only PCI configuration space to disable | |
16a5fd92 YM |
826 | * MSI/MSIX capability |
827 | * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block | |
823e1d90 YM |
828 | */ |
829 | if (CHIP_IS_E1(bp)) { | |
830 | /* Since IGU_PF_CONF_MSI_MSIX_EN still always on | |
831 | * Use mask register to prevent from HC sending interrupts | |
832 | * after we exit the function | |
833 | */ | |
834 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0); | |
835 | ||
836 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
837 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
838 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
839 | } else | |
840 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
841 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
842 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | |
843 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
844 | ||
845 | DP(NETIF_MSG_IFDOWN, | |
846 | "write %x to HC %d (addr 0x%x)\n", | |
847 | val, port, addr); | |
848 | ||
849 | /* flush all outstanding writes */ | |
850 | mmiowb(); | |
851 | ||
852 | REG_WR(bp, addr, val); | |
853 | if (REG_RD(bp, addr) != val) | |
6bf07b8e | 854 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
855 | } |
856 | ||
857 | static void bnx2x_igu_int_disable(struct bnx2x *bp) | |
858 | { | |
859 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
860 | ||
861 | val &= ~(IGU_PF_CONF_MSI_MSIX_EN | | |
862 | IGU_PF_CONF_INT_LINE_EN | | |
863 | IGU_PF_CONF_ATTN_BIT_EN); | |
864 | ||
865 | DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); | |
866 | ||
867 | /* flush all outstanding writes */ | |
868 | mmiowb(); | |
869 | ||
870 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
871 | if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) | |
6bf07b8e | 872 | BNX2X_ERR("BUG! Proper val not read from IGU!\n"); |
823e1d90 YM |
873 | } |
874 | ||
875 | static void bnx2x_int_disable(struct bnx2x *bp) | |
876 | { | |
877 | if (bp->common.int_block == INT_BLOCK_HC) | |
878 | bnx2x_hc_int_disable(bp); | |
879 | else | |
880 | bnx2x_igu_int_disable(bp); | |
881 | } | |
882 | ||
883 | void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) | |
a2fbb9ea ET |
884 | { |
885 | int i; | |
523224a3 DK |
886 | u16 j; |
887 | struct hc_sp_status_block_data sp_sb_data; | |
888 | int func = BP_FUNC(bp); | |
889 | #ifdef BNX2X_STOP_ON_ERROR | |
890 | u16 start = 0, end = 0; | |
6383c0b3 | 891 | u8 cos; |
523224a3 | 892 | #endif |
823e1d90 YM |
893 | if (disable_int) |
894 | bnx2x_int_disable(bp); | |
a2fbb9ea | 895 | |
66e855f3 | 896 | bp->stats_state = STATS_STATE_DISABLED; |
7a752993 | 897 | bp->eth_stats.unrecoverable_error++; |
66e855f3 YG |
898 | DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); |
899 | ||
a2fbb9ea ET |
900 | BNX2X_ERR("begin crash dump -----------------\n"); |
901 | ||
8440d2b6 EG |
902 | /* Indices */ |
903 | /* Common */ | |
51c1a580 | 904 | BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", |
619c5cb6 VZ |
905 | bp->def_idx, bp->def_att_idx, bp->attn_state, |
906 | bp->spq_prod_idx, bp->stats_counter); | |
523224a3 DK |
907 | BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", |
908 | bp->def_status_blk->atten_status_block.attn_bits, | |
909 | bp->def_status_blk->atten_status_block.attn_bits_ack, | |
910 | bp->def_status_blk->atten_status_block.status_block_id, | |
911 | bp->def_status_blk->atten_status_block.attn_bits_index); | |
912 | BNX2X_ERR(" def ("); | |
913 | for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) | |
914 | pr_cont("0x%x%s", | |
f1deab50 JP |
915 | bp->def_status_blk->sp_sb.index_values[i], |
916 | (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); | |
523224a3 DK |
917 | |
918 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
919 | *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
920 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
921 | i*sizeof(u32)); | |
922 | ||
f1deab50 | 923 | pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", |
523224a3 DK |
924 | sp_sb_data.igu_sb_id, |
925 | sp_sb_data.igu_seg_id, | |
926 | sp_sb_data.p_func.pf_id, | |
927 | sp_sb_data.p_func.vnic_id, | |
928 | sp_sb_data.p_func.vf_id, | |
619c5cb6 VZ |
929 | sp_sb_data.p_func.vf_valid, |
930 | sp_sb_data.state); | |
523224a3 | 931 | |
ec6ba945 | 932 | for_each_eth_queue(bp, i) { |
a2fbb9ea | 933 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
523224a3 | 934 | int loop; |
f2e0899f | 935 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
936 | struct hc_status_block_data_e1x sb_data_e1x; |
937 | struct hc_status_block_sm *hc_sm_p = | |
619c5cb6 VZ |
938 | CHIP_IS_E1x(bp) ? |
939 | sb_data_e1x.common.state_machine : | |
940 | sb_data_e2.common.state_machine; | |
523224a3 | 941 | struct hc_index_data *hc_index_p = |
619c5cb6 VZ |
942 | CHIP_IS_E1x(bp) ? |
943 | sb_data_e1x.index_data : | |
944 | sb_data_e2.index_data; | |
6383c0b3 | 945 | u8 data_size, cos; |
523224a3 | 946 | u32 *sb_data_p; |
6383c0b3 | 947 | struct bnx2x_fp_txdata txdata; |
523224a3 DK |
948 | |
949 | /* Rx */ | |
51c1a580 | 950 | BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", |
8440d2b6 | 951 | i, fp->rx_bd_prod, fp->rx_bd_cons, |
523224a3 | 952 | fp->rx_comp_prod, |
66e855f3 | 953 | fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); |
51c1a580 | 954 | BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", |
8440d2b6 | 955 | fp->rx_sge_prod, fp->last_max_sge, |
523224a3 | 956 | le16_to_cpu(fp->fp_hc_idx)); |
a2fbb9ea | 957 | |
523224a3 | 958 | /* Tx */ |
6383c0b3 AE |
959 | for_each_cos_in_tx_queue(fp, cos) |
960 | { | |
65565884 | 961 | txdata = *fp->txdata_ptr[cos]; |
51c1a580 | 962 | BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", |
6383c0b3 AE |
963 | i, txdata.tx_pkt_prod, |
964 | txdata.tx_pkt_cons, txdata.tx_bd_prod, | |
965 | txdata.tx_bd_cons, | |
966 | le16_to_cpu(*txdata.tx_cons_sb)); | |
967 | } | |
523224a3 | 968 | |
619c5cb6 VZ |
969 | loop = CHIP_IS_E1x(bp) ? |
970 | HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; | |
523224a3 DK |
971 | |
972 | /* host sb data */ | |
973 | ||
ec6ba945 VZ |
974 | if (IS_FCOE_FP(fp)) |
975 | continue; | |
55c11941 | 976 | |
523224a3 DK |
977 | BNX2X_ERR(" run indexes ("); |
978 | for (j = 0; j < HC_SB_MAX_SM; j++) | |
979 | pr_cont("0x%x%s", | |
980 | fp->sb_running_index[j], | |
981 | (j == HC_SB_MAX_SM - 1) ? ")" : " "); | |
982 | ||
983 | BNX2X_ERR(" indexes ("); | |
984 | for (j = 0; j < loop; j++) | |
985 | pr_cont("0x%x%s", | |
986 | fp->sb_index_values[j], | |
987 | (j == loop - 1) ? ")" : " "); | |
988 | /* fw sb data */ | |
619c5cb6 VZ |
989 | data_size = CHIP_IS_E1x(bp) ? |
990 | sizeof(struct hc_status_block_data_e1x) : | |
991 | sizeof(struct hc_status_block_data_e2); | |
523224a3 | 992 | data_size /= sizeof(u32); |
619c5cb6 VZ |
993 | sb_data_p = CHIP_IS_E1x(bp) ? |
994 | (u32 *)&sb_data_e1x : | |
995 | (u32 *)&sb_data_e2; | |
523224a3 DK |
996 | /* copy sb data in here */ |
997 | for (j = 0; j < data_size; j++) | |
998 | *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + | |
999 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + | |
1000 | j * sizeof(u32)); | |
1001 | ||
619c5cb6 | 1002 | if (!CHIP_IS_E1x(bp)) { |
51c1a580 | 1003 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1004 | sb_data_e2.common.p_func.pf_id, |
1005 | sb_data_e2.common.p_func.vf_id, | |
1006 | sb_data_e2.common.p_func.vf_valid, | |
1007 | sb_data_e2.common.p_func.vnic_id, | |
619c5cb6 VZ |
1008 | sb_data_e2.common.same_igu_sb_1b, |
1009 | sb_data_e2.common.state); | |
f2e0899f | 1010 | } else { |
51c1a580 | 1011 | pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", |
f2e0899f DK |
1012 | sb_data_e1x.common.p_func.pf_id, |
1013 | sb_data_e1x.common.p_func.vf_id, | |
1014 | sb_data_e1x.common.p_func.vf_valid, | |
1015 | sb_data_e1x.common.p_func.vnic_id, | |
619c5cb6 VZ |
1016 | sb_data_e1x.common.same_igu_sb_1b, |
1017 | sb_data_e1x.common.state); | |
f2e0899f | 1018 | } |
523224a3 DK |
1019 | |
1020 | /* SB_SMs data */ | |
1021 | for (j = 0; j < HC_SB_MAX_SM; j++) { | |
51c1a580 MS |
1022 | pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", |
1023 | j, hc_sm_p[j].__flags, | |
1024 | hc_sm_p[j].igu_sb_id, | |
1025 | hc_sm_p[j].igu_seg_id, | |
1026 | hc_sm_p[j].time_to_expire, | |
1027 | hc_sm_p[j].timer_value); | |
523224a3 DK |
1028 | } |
1029 | ||
16a5fd92 | 1030 | /* Indices data */ |
523224a3 | 1031 | for (j = 0; j < loop; j++) { |
51c1a580 | 1032 | pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, |
523224a3 DK |
1033 | hc_index_p[j].flags, |
1034 | hc_index_p[j].timeout); | |
1035 | } | |
8440d2b6 | 1036 | } |
a2fbb9ea | 1037 | |
523224a3 | 1038 | #ifdef BNX2X_STOP_ON_ERROR |
04c46736 YM |
1039 | |
1040 | /* event queue */ | |
6bf07b8e | 1041 | BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); |
04c46736 YM |
1042 | for (i = 0; i < NUM_EQ_DESC; i++) { |
1043 | u32 *data = (u32 *)&bp->eq_ring[i].message.data; | |
1044 | ||
1045 | BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", | |
1046 | i, bp->eq_ring[i].message.opcode, | |
1047 | bp->eq_ring[i].message.error); | |
1048 | BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]); | |
1049 | } | |
1050 | ||
8440d2b6 EG |
1051 | /* Rings */ |
1052 | /* Rx */ | |
55c11941 | 1053 | for_each_valid_rx_queue(bp, i) { |
8440d2b6 | 1054 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea ET |
1055 | |
1056 | start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); | |
1057 | end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); | |
8440d2b6 | 1058 | for (j = start; j != end; j = RX_BD(j + 1)) { |
a2fbb9ea ET |
1059 | u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; |
1060 | struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; | |
1061 | ||
c3eefaf6 | 1062 | BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", |
44151acb | 1063 | i, j, rx_bd[1], rx_bd[0], sw_bd->data); |
a2fbb9ea ET |
1064 | } |
1065 | ||
3196a88a EG |
1066 | start = RX_SGE(fp->rx_sge_prod); |
1067 | end = RX_SGE(fp->last_max_sge); | |
8440d2b6 | 1068 | for (j = start; j != end; j = RX_SGE(j + 1)) { |
7a9b2557 VZ |
1069 | u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; |
1070 | struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; | |
1071 | ||
c3eefaf6 EG |
1072 | BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", |
1073 | i, j, rx_sge[1], rx_sge[0], sw_page->page); | |
7a9b2557 VZ |
1074 | } |
1075 | ||
a2fbb9ea ET |
1076 | start = RCQ_BD(fp->rx_comp_cons - 10); |
1077 | end = RCQ_BD(fp->rx_comp_cons + 503); | |
8440d2b6 | 1078 | for (j = start; j != end; j = RCQ_BD(j + 1)) { |
a2fbb9ea ET |
1079 | u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; |
1080 | ||
c3eefaf6 EG |
1081 | BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", |
1082 | i, j, cqe[0], cqe[1], cqe[2], cqe[3]); | |
a2fbb9ea ET |
1083 | } |
1084 | } | |
1085 | ||
8440d2b6 | 1086 | /* Tx */ |
55c11941 | 1087 | for_each_valid_tx_queue(bp, i) { |
8440d2b6 | 1088 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
6383c0b3 | 1089 | for_each_cos_in_tx_queue(fp, cos) { |
65565884 | 1090 | struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; |
6383c0b3 AE |
1091 | |
1092 | start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); | |
1093 | end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); | |
1094 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1095 | struct sw_tx_bd *sw_bd = | |
1096 | &txdata->tx_buf_ring[j]; | |
1097 | ||
51c1a580 | 1098 | BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", |
6383c0b3 AE |
1099 | i, cos, j, sw_bd->skb, |
1100 | sw_bd->first_bd); | |
1101 | } | |
8440d2b6 | 1102 | |
6383c0b3 AE |
1103 | start = TX_BD(txdata->tx_bd_cons - 10); |
1104 | end = TX_BD(txdata->tx_bd_cons + 254); | |
1105 | for (j = start; j != end; j = TX_BD(j + 1)) { | |
1106 | u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; | |
8440d2b6 | 1107 | |
51c1a580 | 1108 | BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", |
6383c0b3 AE |
1109 | i, cos, j, tx_bd[0], tx_bd[1], |
1110 | tx_bd[2], tx_bd[3]); | |
1111 | } | |
8440d2b6 EG |
1112 | } |
1113 | } | |
523224a3 | 1114 | #endif |
34f80b04 | 1115 | bnx2x_fw_dump(bp); |
a2fbb9ea ET |
1116 | bnx2x_mc_assert(bp); |
1117 | BNX2X_ERR("end crash dump -----------------\n"); | |
a2fbb9ea ET |
1118 | } |
1119 | ||
619c5cb6 VZ |
1120 | /* |
1121 | * FLR Support for E2 | |
1122 | * | |
1123 | * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW | |
1124 | * initialization. | |
1125 | */ | |
16a5fd92 | 1126 | #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ |
89db4ad8 AE |
1127 | #define FLR_WAIT_INTERVAL 50 /* usec */ |
1128 | #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ | |
619c5cb6 VZ |
1129 | |
1130 | struct pbf_pN_buf_regs { | |
1131 | int pN; | |
1132 | u32 init_crd; | |
1133 | u32 crd; | |
1134 | u32 crd_freed; | |
1135 | }; | |
1136 | ||
1137 | struct pbf_pN_cmd_regs { | |
1138 | int pN; | |
1139 | u32 lines_occup; | |
1140 | u32 lines_freed; | |
1141 | }; | |
1142 | ||
1143 | static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, | |
1144 | struct pbf_pN_buf_regs *regs, | |
1145 | u32 poll_count) | |
1146 | { | |
1147 | u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; | |
1148 | u32 cur_cnt = poll_count; | |
1149 | ||
1150 | crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); | |
1151 | crd = crd_start = REG_RD(bp, regs->crd); | |
1152 | init_crd = REG_RD(bp, regs->init_crd); | |
1153 | ||
1154 | DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); | |
1155 | DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); | |
1156 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); | |
1157 | ||
1158 | while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < | |
1159 | (init_crd - crd_start))) { | |
1160 | if (cur_cnt--) { | |
89db4ad8 | 1161 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1162 | crd = REG_RD(bp, regs->crd); |
1163 | crd_freed = REG_RD(bp, regs->crd_freed); | |
1164 | } else { | |
1165 | DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", | |
1166 | regs->pN); | |
1167 | DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", | |
1168 | regs->pN, crd); | |
1169 | DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", | |
1170 | regs->pN, crd_freed); | |
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", | |
89db4ad8 | 1175 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1176 | } |
1177 | ||
1178 | static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, | |
1179 | struct pbf_pN_cmd_regs *regs, | |
1180 | u32 poll_count) | |
1181 | { | |
1182 | u32 occup, to_free, freed, freed_start; | |
1183 | u32 cur_cnt = poll_count; | |
1184 | ||
1185 | occup = to_free = REG_RD(bp, regs->lines_occup); | |
1186 | freed = freed_start = REG_RD(bp, regs->lines_freed); | |
1187 | ||
1188 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); | |
1189 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); | |
1190 | ||
1191 | while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { | |
1192 | if (cur_cnt--) { | |
89db4ad8 | 1193 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1194 | occup = REG_RD(bp, regs->lines_occup); |
1195 | freed = REG_RD(bp, regs->lines_freed); | |
1196 | } else { | |
1197 | DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", | |
1198 | regs->pN); | |
1199 | DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", | |
1200 | regs->pN, occup); | |
1201 | DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", | |
1202 | regs->pN, freed); | |
1203 | break; | |
1204 | } | |
1205 | } | |
1206 | DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", | |
89db4ad8 | 1207 | poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); |
619c5cb6 VZ |
1208 | } |
1209 | ||
1191cb83 ED |
1210 | static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, |
1211 | u32 expected, u32 poll_count) | |
619c5cb6 VZ |
1212 | { |
1213 | u32 cur_cnt = poll_count; | |
1214 | u32 val; | |
1215 | ||
1216 | while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) | |
89db4ad8 | 1217 | udelay(FLR_WAIT_INTERVAL); |
619c5cb6 VZ |
1218 | |
1219 | return val; | |
1220 | } | |
1221 | ||
d16132ce AE |
1222 | int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1223 | char *msg, u32 poll_cnt) | |
619c5cb6 VZ |
1224 | { |
1225 | u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); | |
1226 | if (val != 0) { | |
1227 | BNX2X_ERR("%s usage count=%d\n", msg, val); | |
1228 | return 1; | |
1229 | } | |
1230 | return 0; | |
1231 | } | |
1232 | ||
d16132ce AE |
1233 | /* Common routines with VF FLR cleanup */ |
1234 | u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) | |
619c5cb6 VZ |
1235 | { |
1236 | /* adjust polling timeout */ | |
1237 | if (CHIP_REV_IS_EMUL(bp)) | |
1238 | return FLR_POLL_CNT * 2000; | |
1239 | ||
1240 | if (CHIP_REV_IS_FPGA(bp)) | |
1241 | return FLR_POLL_CNT * 120; | |
1242 | ||
1243 | return FLR_POLL_CNT; | |
1244 | } | |
1245 | ||
d16132ce | 1246 | void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) |
619c5cb6 VZ |
1247 | { |
1248 | struct pbf_pN_cmd_regs cmd_regs[] = { | |
1249 | {0, (CHIP_IS_E3B0(bp)) ? | |
1250 | PBF_REG_TQ_OCCUPANCY_Q0 : | |
1251 | PBF_REG_P0_TQ_OCCUPANCY, | |
1252 | (CHIP_IS_E3B0(bp)) ? | |
1253 | PBF_REG_TQ_LINES_FREED_CNT_Q0 : | |
1254 | PBF_REG_P0_TQ_LINES_FREED_CNT}, | |
1255 | {1, (CHIP_IS_E3B0(bp)) ? | |
1256 | PBF_REG_TQ_OCCUPANCY_Q1 : | |
1257 | PBF_REG_P1_TQ_OCCUPANCY, | |
1258 | (CHIP_IS_E3B0(bp)) ? | |
1259 | PBF_REG_TQ_LINES_FREED_CNT_Q1 : | |
1260 | PBF_REG_P1_TQ_LINES_FREED_CNT}, | |
1261 | {4, (CHIP_IS_E3B0(bp)) ? | |
1262 | PBF_REG_TQ_OCCUPANCY_LB_Q : | |
1263 | PBF_REG_P4_TQ_OCCUPANCY, | |
1264 | (CHIP_IS_E3B0(bp)) ? | |
1265 | PBF_REG_TQ_LINES_FREED_CNT_LB_Q : | |
1266 | PBF_REG_P4_TQ_LINES_FREED_CNT} | |
1267 | }; | |
1268 | ||
1269 | struct pbf_pN_buf_regs buf_regs[] = { | |
1270 | {0, (CHIP_IS_E3B0(bp)) ? | |
1271 | PBF_REG_INIT_CRD_Q0 : | |
1272 | PBF_REG_P0_INIT_CRD , | |
1273 | (CHIP_IS_E3B0(bp)) ? | |
1274 | PBF_REG_CREDIT_Q0 : | |
1275 | PBF_REG_P0_CREDIT, | |
1276 | (CHIP_IS_E3B0(bp)) ? | |
1277 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : | |
1278 | PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, | |
1279 | {1, (CHIP_IS_E3B0(bp)) ? | |
1280 | PBF_REG_INIT_CRD_Q1 : | |
1281 | PBF_REG_P1_INIT_CRD, | |
1282 | (CHIP_IS_E3B0(bp)) ? | |
1283 | PBF_REG_CREDIT_Q1 : | |
1284 | PBF_REG_P1_CREDIT, | |
1285 | (CHIP_IS_E3B0(bp)) ? | |
1286 | PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : | |
1287 | PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, | |
1288 | {4, (CHIP_IS_E3B0(bp)) ? | |
1289 | PBF_REG_INIT_CRD_LB_Q : | |
1290 | PBF_REG_P4_INIT_CRD, | |
1291 | (CHIP_IS_E3B0(bp)) ? | |
1292 | PBF_REG_CREDIT_LB_Q : | |
1293 | PBF_REG_P4_CREDIT, | |
1294 | (CHIP_IS_E3B0(bp)) ? | |
1295 | PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : | |
1296 | PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, | |
1297 | }; | |
1298 | ||
1299 | int i; | |
1300 | ||
1301 | /* Verify the command queues are flushed P0, P1, P4 */ | |
1302 | for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) | |
1303 | bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); | |
1304 | ||
619c5cb6 VZ |
1305 | /* Verify the transmission buffers are flushed P0, P1, P4 */ |
1306 | for (i = 0; i < ARRAY_SIZE(buf_regs); i++) | |
1307 | bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); | |
1308 | } | |
1309 | ||
1310 | #define OP_GEN_PARAM(param) \ | |
1311 | (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) | |
1312 | ||
1313 | #define OP_GEN_TYPE(type) \ | |
1314 | (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) | |
1315 | ||
1316 | #define OP_GEN_AGG_VECT(index) \ | |
1317 | (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) | |
1318 | ||
d16132ce | 1319 | int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) |
619c5cb6 | 1320 | { |
86564c3f | 1321 | u32 op_gen_command = 0; |
619c5cb6 VZ |
1322 | u32 comp_addr = BAR_CSTRORM_INTMEM + |
1323 | CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); | |
1324 | int ret = 0; | |
1325 | ||
1326 | if (REG_RD(bp, comp_addr)) { | |
89db4ad8 | 1327 | BNX2X_ERR("Cleanup complete was not 0 before sending\n"); |
619c5cb6 VZ |
1328 | return 1; |
1329 | } | |
1330 | ||
86564c3f YM |
1331 | op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); |
1332 | op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); | |
1333 | op_gen_command |= OP_GEN_AGG_VECT(clnup_func); | |
1334 | op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; | |
619c5cb6 | 1335 | |
89db4ad8 | 1336 | DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); |
86564c3f | 1337 | REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); |
619c5cb6 VZ |
1338 | |
1339 | if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { | |
1340 | BNX2X_ERR("FW final cleanup did not succeed\n"); | |
51c1a580 MS |
1341 | DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", |
1342 | (REG_RD(bp, comp_addr))); | |
d16132ce AE |
1343 | bnx2x_panic(); |
1344 | return 1; | |
619c5cb6 | 1345 | } |
16a5fd92 | 1346 | /* Zero completion for next FLR */ |
619c5cb6 VZ |
1347 | REG_WR(bp, comp_addr, 0); |
1348 | ||
1349 | return ret; | |
1350 | } | |
1351 | ||
b56e9670 | 1352 | u8 bnx2x_is_pcie_pending(struct pci_dev *dev) |
619c5cb6 | 1353 | { |
619c5cb6 VZ |
1354 | u16 status; |
1355 | ||
2a80eebc | 1356 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
619c5cb6 VZ |
1357 | return status & PCI_EXP_DEVSTA_TRPND; |
1358 | } | |
1359 | ||
1360 | /* PF FLR specific routines | |
1361 | */ | |
1362 | static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) | |
1363 | { | |
619c5cb6 VZ |
1364 | /* wait for CFC PF usage-counter to zero (includes all the VFs) */ |
1365 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1366 | CFC_REG_NUM_LCIDS_INSIDE_PF, | |
1367 | "CFC PF usage counter timed out", | |
1368 | poll_cnt)) | |
1369 | return 1; | |
1370 | ||
619c5cb6 VZ |
1371 | /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ |
1372 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1373 | DORQ_REG_PF_USAGE_CNT, | |
1374 | "DQ PF usage counter timed out", | |
1375 | poll_cnt)) | |
1376 | return 1; | |
1377 | ||
1378 | /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ | |
1379 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1380 | QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), | |
1381 | "QM PF usage counter timed out", | |
1382 | poll_cnt)) | |
1383 | return 1; | |
1384 | ||
1385 | /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ | |
1386 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1387 | TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), | |
1388 | "Timers VNIC usage counter timed out", | |
1389 | poll_cnt)) | |
1390 | return 1; | |
1391 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1392 | TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), | |
1393 | "Timers NUM_SCANS usage counter timed out", | |
1394 | poll_cnt)) | |
1395 | return 1; | |
1396 | ||
1397 | /* Wait DMAE PF usage counter to zero */ | |
1398 | if (bnx2x_flr_clnup_poll_hw_counter(bp, | |
1399 | dmae_reg_go_c[INIT_DMAE_C(bp)], | |
6bf07b8e | 1400 | "DMAE command register timed out", |
619c5cb6 VZ |
1401 | poll_cnt)) |
1402 | return 1; | |
1403 | ||
1404 | return 0; | |
1405 | } | |
1406 | ||
1407 | static void bnx2x_hw_enable_status(struct bnx2x *bp) | |
1408 | { | |
1409 | u32 val; | |
1410 | ||
1411 | val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); | |
1412 | DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); | |
1413 | ||
1414 | val = REG_RD(bp, PBF_REG_DISABLE_PF); | |
1415 | DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); | |
1416 | ||
1417 | val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); | |
1418 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); | |
1419 | ||
1420 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); | |
1421 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); | |
1422 | ||
1423 | val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); | |
1424 | DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); | |
1425 | ||
1426 | val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); | |
1427 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); | |
1428 | ||
1429 | val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); | |
1430 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); | |
1431 | ||
1432 | val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
1433 | DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", | |
1434 | val); | |
1435 | } | |
1436 | ||
1437 | static int bnx2x_pf_flr_clnup(struct bnx2x *bp) | |
1438 | { | |
1439 | u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); | |
1440 | ||
1441 | DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); | |
1442 | ||
1443 | /* Re-enable PF target read access */ | |
1444 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
1445 | ||
1446 | /* Poll HW usage counters */ | |
89db4ad8 | 1447 | DP(BNX2X_MSG_SP, "Polling usage counters\n"); |
619c5cb6 VZ |
1448 | if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) |
1449 | return -EBUSY; | |
1450 | ||
1451 | /* Zero the igu 'trailing edge' and 'leading edge' */ | |
1452 | ||
1453 | /* Send the FW cleanup command */ | |
1454 | if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) | |
1455 | return -EBUSY; | |
1456 | ||
1457 | /* ATC cleanup */ | |
1458 | ||
1459 | /* Verify TX hw is flushed */ | |
1460 | bnx2x_tx_hw_flushed(bp, poll_cnt); | |
1461 | ||
1462 | /* Wait 100ms (not adjusted according to platform) */ | |
1463 | msleep(100); | |
1464 | ||
1465 | /* Verify no pending pci transactions */ | |
1466 | if (bnx2x_is_pcie_pending(bp->pdev)) | |
1467 | BNX2X_ERR("PCIE Transactions still pending\n"); | |
1468 | ||
1469 | /* Debug */ | |
1470 | bnx2x_hw_enable_status(bp); | |
1471 | ||
1472 | /* | |
1473 | * Master enable - Due to WB DMAE writes performed before this | |
1474 | * register is re-initialized as part of the regular function init | |
1475 | */ | |
1476 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
1477 | ||
1478 | return 0; | |
1479 | } | |
1480 | ||
f2e0899f | 1481 | static void bnx2x_hc_int_enable(struct bnx2x *bp) |
a2fbb9ea | 1482 | { |
34f80b04 | 1483 | int port = BP_PORT(bp); |
a2fbb9ea ET |
1484 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
1485 | u32 val = REG_RD(bp, addr); | |
69c326b3 DK |
1486 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1487 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1488 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
a2fbb9ea ET |
1489 | |
1490 | if (msix) { | |
8badd27a EG |
1491 | val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
1492 | HC_CONFIG_0_REG_INT_LINE_EN_0); | |
a2fbb9ea ET |
1493 | val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
1494 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
69c326b3 DK |
1495 | if (single_msix) |
1496 | val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; | |
8badd27a EG |
1497 | } else if (msi) { |
1498 | val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; | |
1499 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
1500 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | |
1501 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
a2fbb9ea ET |
1502 | } else { |
1503 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | |
615f8fd9 | 1504 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | |
a2fbb9ea ET |
1505 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
1506 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | |
615f8fd9 | 1507 | |
a0fd065c | 1508 | if (!CHIP_IS_E1(bp)) { |
51c1a580 MS |
1509 | DP(NETIF_MSG_IFUP, |
1510 | "write %x to HC %d (addr 0x%x)\n", val, port, addr); | |
615f8fd9 | 1511 | |
a0fd065c | 1512 | REG_WR(bp, addr, val); |
615f8fd9 | 1513 | |
a0fd065c DK |
1514 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
1515 | } | |
a2fbb9ea ET |
1516 | } |
1517 | ||
a0fd065c DK |
1518 | if (CHIP_IS_E1(bp)) |
1519 | REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); | |
1520 | ||
51c1a580 MS |
1521 | DP(NETIF_MSG_IFUP, |
1522 | "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, | |
1523 | (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); | |
a2fbb9ea ET |
1524 | |
1525 | REG_WR(bp, addr, val); | |
37dbbf32 EG |
1526 | /* |
1527 | * Ensure that HC_CONFIG is written before leading/trailing edge config | |
1528 | */ | |
1529 | mmiowb(); | |
1530 | barrier(); | |
34f80b04 | 1531 | |
f2e0899f | 1532 | if (!CHIP_IS_E1(bp)) { |
34f80b04 | 1533 | /* init leading/trailing edge */ |
fb3bff17 | 1534 | if (IS_MF(bp)) { |
3395a033 | 1535 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
34f80b04 | 1536 | if (bp->port.pmf) |
4acac6a5 EG |
1537 | /* enable nig and gpio3 attention */ |
1538 | val |= 0x1100; | |
34f80b04 EG |
1539 | } else |
1540 | val = 0xffff; | |
1541 | ||
1542 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
1543 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
1544 | } | |
37dbbf32 EG |
1545 | |
1546 | /* Make sure that interrupts are indeed enabled from here on */ | |
1547 | mmiowb(); | |
a2fbb9ea ET |
1548 | } |
1549 | ||
f2e0899f DK |
1550 | static void bnx2x_igu_int_enable(struct bnx2x *bp) |
1551 | { | |
1552 | u32 val; | |
30a5de77 DK |
1553 | bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; |
1554 | bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; | |
1555 | bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; | |
f2e0899f DK |
1556 | |
1557 | val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
1558 | ||
1559 | if (msix) { | |
1560 | val &= ~(IGU_PF_CONF_INT_LINE_EN | | |
1561 | IGU_PF_CONF_SINGLE_ISR_EN); | |
ebe61d80 | 1562 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f | 1563 | IGU_PF_CONF_ATTN_BIT_EN); |
30a5de77 DK |
1564 | |
1565 | if (single_msix) | |
1566 | val |= IGU_PF_CONF_SINGLE_ISR_EN; | |
f2e0899f DK |
1567 | } else if (msi) { |
1568 | val &= ~IGU_PF_CONF_INT_LINE_EN; | |
ebe61d80 | 1569 | val |= (IGU_PF_CONF_MSI_MSIX_EN | |
f2e0899f DK |
1570 | IGU_PF_CONF_ATTN_BIT_EN | |
1571 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1572 | } else { | |
1573 | val &= ~IGU_PF_CONF_MSI_MSIX_EN; | |
ebe61d80 | 1574 | val |= (IGU_PF_CONF_INT_LINE_EN | |
f2e0899f DK |
1575 | IGU_PF_CONF_ATTN_BIT_EN | |
1576 | IGU_PF_CONF_SINGLE_ISR_EN); | |
1577 | } | |
1578 | ||
ebe61d80 YM |
1579 | /* Clean previous status - need to configure igu prior to ack*/ |
1580 | if ((!msix) || single_msix) { | |
1581 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1582 | bnx2x_ack_int(bp); | |
1583 | } | |
1584 | ||
1585 | val |= IGU_PF_CONF_FUNC_EN; | |
1586 | ||
51c1a580 | 1587 | DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", |
f2e0899f DK |
1588 | val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); |
1589 | ||
1590 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
1591 | ||
79a8557a YM |
1592 | if (val & IGU_PF_CONF_INT_LINE_EN) |
1593 | pci_intx(bp->pdev, true); | |
1594 | ||
f2e0899f DK |
1595 | barrier(); |
1596 | ||
1597 | /* init leading/trailing edge */ | |
1598 | if (IS_MF(bp)) { | |
3395a033 | 1599 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
1600 | if (bp->port.pmf) |
1601 | /* enable nig and gpio3 attention */ | |
1602 | val |= 0x1100; | |
1603 | } else | |
1604 | val = 0xffff; | |
1605 | ||
1606 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); | |
1607 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
1608 | ||
1609 | /* Make sure that interrupts are indeed enabled from here on */ | |
1610 | mmiowb(); | |
1611 | } | |
1612 | ||
1613 | void bnx2x_int_enable(struct bnx2x *bp) | |
1614 | { | |
1615 | if (bp->common.int_block == INT_BLOCK_HC) | |
1616 | bnx2x_hc_int_enable(bp); | |
1617 | else | |
1618 | bnx2x_igu_int_enable(bp); | |
1619 | } | |
1620 | ||
9f6c9258 | 1621 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) |
a2fbb9ea | 1622 | { |
a2fbb9ea | 1623 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
8badd27a | 1624 | int i, offset; |
a2fbb9ea | 1625 | |
f8ef6e44 YG |
1626 | if (disable_hw) |
1627 | /* prevent the HW from sending interrupts */ | |
1628 | bnx2x_int_disable(bp); | |
a2fbb9ea ET |
1629 | |
1630 | /* make sure all ISRs are done */ | |
1631 | if (msix) { | |
8badd27a EG |
1632 | synchronize_irq(bp->msix_table[0].vector); |
1633 | offset = 1; | |
55c11941 MS |
1634 | if (CNIC_SUPPORT(bp)) |
1635 | offset++; | |
ec6ba945 | 1636 | for_each_eth_queue(bp, i) |
754a2f52 | 1637 | synchronize_irq(bp->msix_table[offset++].vector); |
a2fbb9ea ET |
1638 | } else |
1639 | synchronize_irq(bp->pdev->irq); | |
1640 | ||
1641 | /* make sure sp_task is not running */ | |
1cf167f2 | 1642 | cancel_delayed_work(&bp->sp_task); |
3deb8167 | 1643 | cancel_delayed_work(&bp->period_task); |
1cf167f2 | 1644 | flush_workqueue(bnx2x_wq); |
a2fbb9ea ET |
1645 | } |
1646 | ||
34f80b04 | 1647 | /* fast path */ |
a2fbb9ea ET |
1648 | |
1649 | /* | |
34f80b04 | 1650 | * General service functions |
a2fbb9ea ET |
1651 | */ |
1652 | ||
72fd0718 VZ |
1653 | /* Return true if succeeded to acquire the lock */ |
1654 | static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) | |
1655 | { | |
1656 | u32 lock_status; | |
1657 | u32 resource_bit = (1 << resource); | |
1658 | int func = BP_FUNC(bp); | |
1659 | u32 hw_lock_control_reg; | |
1660 | ||
51c1a580 MS |
1661 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1662 | "Trying to take a lock on resource %d\n", resource); | |
72fd0718 VZ |
1663 | |
1664 | /* Validating that the resource is within range */ | |
1665 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1666 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
72fd0718 VZ |
1667 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
1668 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | |
0fdf4d09 | 1669 | return false; |
72fd0718 VZ |
1670 | } |
1671 | ||
1672 | if (func <= 5) | |
1673 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1674 | else | |
1675 | hw_lock_control_reg = | |
1676 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1677 | ||
1678 | /* Try to acquire the lock */ | |
1679 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); | |
1680 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
1681 | if (lock_status & resource_bit) | |
1682 | return true; | |
1683 | ||
51c1a580 MS |
1684 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, |
1685 | "Failed to get a lock on resource %d\n", resource); | |
72fd0718 VZ |
1686 | return false; |
1687 | } | |
1688 | ||
c9ee9206 VZ |
1689 | /** |
1690 | * bnx2x_get_leader_lock_resource - get the recovery leader resource id | |
1691 | * | |
1692 | * @bp: driver handle | |
1693 | * | |
1694 | * Returns the recovery leader resource id according to the engine this function | |
1695 | * belongs to. Currently only only 2 engines is supported. | |
1696 | */ | |
1191cb83 | 1697 | static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) |
c9ee9206 VZ |
1698 | { |
1699 | if (BP_PATH(bp)) | |
1700 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; | |
1701 | else | |
1702 | return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; | |
1703 | } | |
1704 | ||
1705 | /** | |
2de67439 | 1706 | * bnx2x_trylock_leader_lock- try to acquire a leader lock. |
c9ee9206 VZ |
1707 | * |
1708 | * @bp: driver handle | |
1709 | * | |
2de67439 | 1710 | * Tries to acquire a leader lock for current engine. |
c9ee9206 | 1711 | */ |
1191cb83 | 1712 | static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) |
c9ee9206 VZ |
1713 | { |
1714 | return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1715 | } | |
1716 | ||
619c5cb6 | 1717 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); |
55c11941 | 1718 | |
fd1fc79d AE |
1719 | /* schedule the sp task and mark that interrupt occurred (runs from ISR) */ |
1720 | static int bnx2x_schedule_sp_task(struct bnx2x *bp) | |
1721 | { | |
1722 | /* Set the interrupt occurred bit for the sp-task to recognize it | |
1723 | * must ack the interrupt and transition according to the IGU | |
1724 | * state machine. | |
1725 | */ | |
1726 | atomic_set(&bp->interrupt_occurred, 1); | |
1727 | ||
1728 | /* The sp_task must execute only after this bit | |
1729 | * is set, otherwise we will get out of sync and miss all | |
1730 | * further interrupts. Hence, the barrier. | |
1731 | */ | |
1732 | smp_wmb(); | |
1733 | ||
1734 | /* schedule sp_task to workqueue */ | |
1735 | return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); | |
1736 | } | |
3196a88a | 1737 | |
619c5cb6 | 1738 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) |
a2fbb9ea ET |
1739 | { |
1740 | struct bnx2x *bp = fp->bp; | |
1741 | int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
1742 | int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); | |
619c5cb6 | 1743 | enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; |
15192a8c | 1744 | struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a2fbb9ea | 1745 | |
34f80b04 | 1746 | DP(BNX2X_MSG_SP, |
a2fbb9ea | 1747 | "fp %d cid %d got ramrod #%d state is %x type is %d\n", |
0626b899 | 1748 | fp->index, cid, command, bp->state, |
34f80b04 | 1749 | rr_cqe->ramrod_cqe.ramrod_type); |
a2fbb9ea | 1750 | |
fd1fc79d AE |
1751 | /* If cid is within VF range, replace the slowpath object with the |
1752 | * one corresponding to this VF | |
1753 | */ | |
1754 | if (cid >= BNX2X_FIRST_VF_CID && | |
1755 | cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) | |
1756 | bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); | |
1757 | ||
619c5cb6 VZ |
1758 | switch (command) { |
1759 | case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): | |
d6cae238 | 1760 | DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); |
619c5cb6 VZ |
1761 | drv_cmd = BNX2X_Q_CMD_UPDATE; |
1762 | break; | |
d6cae238 | 1763 | |
619c5cb6 | 1764 | case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): |
d6cae238 | 1765 | DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); |
619c5cb6 | 1766 | drv_cmd = BNX2X_Q_CMD_SETUP; |
a2fbb9ea ET |
1767 | break; |
1768 | ||
6383c0b3 | 1769 | case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): |
51c1a580 | 1770 | DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); |
6383c0b3 AE |
1771 | drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; |
1772 | break; | |
1773 | ||
619c5cb6 | 1774 | case (RAMROD_CMD_ID_ETH_HALT): |
d6cae238 | 1775 | DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); |
619c5cb6 | 1776 | drv_cmd = BNX2X_Q_CMD_HALT; |
a2fbb9ea ET |
1777 | break; |
1778 | ||
619c5cb6 | 1779 | case (RAMROD_CMD_ID_ETH_TERMINATE): |
6bf07b8e | 1780 | DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); |
619c5cb6 | 1781 | drv_cmd = BNX2X_Q_CMD_TERMINATE; |
a2fbb9ea ET |
1782 | break; |
1783 | ||
619c5cb6 | 1784 | case (RAMROD_CMD_ID_ETH_EMPTY): |
d6cae238 | 1785 | DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); |
619c5cb6 | 1786 | drv_cmd = BNX2X_Q_CMD_EMPTY; |
993ac7b5 | 1787 | break; |
619c5cb6 VZ |
1788 | |
1789 | default: | |
1790 | BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", | |
1791 | command, fp->index); | |
1792 | return; | |
523224a3 | 1793 | } |
3196a88a | 1794 | |
619c5cb6 VZ |
1795 | if ((drv_cmd != BNX2X_Q_CMD_MAX) && |
1796 | q_obj->complete_cmd(bp, q_obj, drv_cmd)) | |
1797 | /* q_obj->complete_cmd() failure means that this was | |
1798 | * an unexpected completion. | |
1799 | * | |
1800 | * In this case we don't want to increase the bp->spq_left | |
1801 | * because apparently we haven't sent this command the first | |
1802 | * place. | |
1803 | */ | |
1804 | #ifdef BNX2X_STOP_ON_ERROR | |
1805 | bnx2x_panic(); | |
1806 | #else | |
1807 | return; | |
1808 | #endif | |
fd1fc79d AE |
1809 | /* SRIOV: reschedule any 'in_progress' operations */ |
1810 | bnx2x_iov_sp_event(bp, cid, true); | |
619c5cb6 | 1811 | |
8fe23fbd | 1812 | smp_mb__before_atomic_inc(); |
6e30dd4e | 1813 | atomic_inc(&bp->cq_spq_left); |
619c5cb6 VZ |
1814 | /* push the change in bp->spq_left and towards the memory */ |
1815 | smp_mb__after_atomic_inc(); | |
49d66772 | 1816 | |
d6cae238 VZ |
1817 | DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); |
1818 | ||
a3348722 BW |
1819 | if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && |
1820 | (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { | |
1821 | /* if Q update ramrod is completed for last Q in AFEX vif set | |
1822 | * flow, then ACK MCP at the end | |
1823 | * | |
1824 | * mark pending ACK to MCP bit. | |
1825 | * prevent case that both bits are cleared. | |
1826 | * At the end of load/unload driver checks that | |
2de67439 | 1827 | * sp_state is cleared, and this order prevents |
a3348722 BW |
1828 | * races |
1829 | */ | |
1830 | smp_mb__before_clear_bit(); | |
1831 | set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); | |
1832 | wmb(); | |
1833 | clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
1834 | smp_mb__after_clear_bit(); | |
1835 | ||
fd1fc79d AE |
1836 | /* schedule the sp task as mcp ack is required */ |
1837 | bnx2x_schedule_sp_task(bp); | |
a3348722 BW |
1838 | } |
1839 | ||
523224a3 | 1840 | return; |
a2fbb9ea ET |
1841 | } |
1842 | ||
9f6c9258 | 1843 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) |
a2fbb9ea | 1844 | { |
555f6c78 | 1845 | struct bnx2x *bp = netdev_priv(dev_instance); |
a2fbb9ea | 1846 | u16 status = bnx2x_ack_int(bp); |
34f80b04 | 1847 | u16 mask; |
ca00392c | 1848 | int i; |
6383c0b3 | 1849 | u8 cos; |
a2fbb9ea | 1850 | |
34f80b04 | 1851 | /* Return here if interrupt is shared and it's not for us */ |
a2fbb9ea ET |
1852 | if (unlikely(status == 0)) { |
1853 | DP(NETIF_MSG_INTR, "not our interrupt!\n"); | |
1854 | return IRQ_NONE; | |
1855 | } | |
f5372251 | 1856 | DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); |
a2fbb9ea | 1857 | |
3196a88a EG |
1858 | #ifdef BNX2X_STOP_ON_ERROR |
1859 | if (unlikely(bp->panic)) | |
1860 | return IRQ_HANDLED; | |
1861 | #endif | |
1862 | ||
ec6ba945 | 1863 | for_each_eth_queue(bp, i) { |
ca00392c | 1864 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
a2fbb9ea | 1865 | |
55c11941 | 1866 | mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); |
ca00392c | 1867 | if (status & mask) { |
619c5cb6 | 1868 | /* Handle Rx or Tx according to SB id */ |
6383c0b3 | 1869 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 1870 | prefetch(fp->txdata_ptr[cos]->tx_cons_sb); |
523224a3 | 1871 | prefetch(&fp->sb_running_index[SM_RX_ID]); |
54b9ddaa | 1872 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
ca00392c EG |
1873 | status &= ~mask; |
1874 | } | |
a2fbb9ea ET |
1875 | } |
1876 | ||
55c11941 MS |
1877 | if (CNIC_SUPPORT(bp)) { |
1878 | mask = 0x2; | |
1879 | if (status & (mask | 0x1)) { | |
1880 | struct cnic_ops *c_ops = NULL; | |
993ac7b5 | 1881 | |
ad9b4359 MC |
1882 | rcu_read_lock(); |
1883 | c_ops = rcu_dereference(bp->cnic_ops); | |
1884 | if (c_ops && (bp->cnic_eth_dev.drv_state & | |
1885 | CNIC_DRV_STATE_HANDLES_IRQ)) | |
1886 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
1887 | rcu_read_unlock(); | |
993ac7b5 | 1888 | |
55c11941 MS |
1889 | status &= ~mask; |
1890 | } | |
993ac7b5 | 1891 | } |
a2fbb9ea | 1892 | |
34f80b04 | 1893 | if (unlikely(status & 0x1)) { |
fd1fc79d AE |
1894 | |
1895 | /* schedule sp task to perform default status block work, ack | |
1896 | * attentions and enable interrupts. | |
1897 | */ | |
1898 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
1899 | |
1900 | status &= ~0x1; | |
1901 | if (!status) | |
1902 | return IRQ_HANDLED; | |
1903 | } | |
1904 | ||
cdaa7cb8 VZ |
1905 | if (unlikely(status)) |
1906 | DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", | |
34f80b04 | 1907 | status); |
a2fbb9ea | 1908 | |
c18487ee | 1909 | return IRQ_HANDLED; |
a2fbb9ea ET |
1910 | } |
1911 | ||
c18487ee YR |
1912 | /* Link */ |
1913 | ||
1914 | /* | |
1915 | * General service functions | |
1916 | */ | |
a2fbb9ea | 1917 | |
9f6c9258 | 1918 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1919 | { |
1920 | u32 lock_status; | |
1921 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1922 | int func = BP_FUNC(bp); |
1923 | u32 hw_lock_control_reg; | |
c18487ee | 1924 | int cnt; |
a2fbb9ea | 1925 | |
c18487ee YR |
1926 | /* Validating that the resource is within range */ |
1927 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1928 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1929 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1930 | return -EINVAL; | |
1931 | } | |
a2fbb9ea | 1932 | |
4a37fb66 YG |
1933 | if (func <= 5) { |
1934 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1935 | } else { | |
1936 | hw_lock_control_reg = | |
1937 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1938 | } | |
1939 | ||
c18487ee | 1940 | /* Validating that the resource is not already taken */ |
4a37fb66 | 1941 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1942 | if (lock_status & resource_bit) { |
51c1a580 | 1943 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", |
c18487ee YR |
1944 | lock_status, resource_bit); |
1945 | return -EEXIST; | |
1946 | } | |
a2fbb9ea | 1947 | |
46230476 EG |
1948 | /* Try for 5 second every 5ms */ |
1949 | for (cnt = 0; cnt < 1000; cnt++) { | |
c18487ee | 1950 | /* Try to acquire the lock */ |
4a37fb66 YG |
1951 | REG_WR(bp, hw_lock_control_reg + 4, resource_bit); |
1952 | lock_status = REG_RD(bp, hw_lock_control_reg); | |
c18487ee YR |
1953 | if (lock_status & resource_bit) |
1954 | return 0; | |
a2fbb9ea | 1955 | |
639d65b8 | 1956 | usleep_range(5000, 10000); |
a2fbb9ea | 1957 | } |
51c1a580 | 1958 | BNX2X_ERR("Timeout\n"); |
c18487ee YR |
1959 | return -EAGAIN; |
1960 | } | |
a2fbb9ea | 1961 | |
c9ee9206 VZ |
1962 | int bnx2x_release_leader_lock(struct bnx2x *bp) |
1963 | { | |
1964 | return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); | |
1965 | } | |
1966 | ||
9f6c9258 | 1967 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) |
c18487ee YR |
1968 | { |
1969 | u32 lock_status; | |
1970 | u32 resource_bit = (1 << resource); | |
4a37fb66 YG |
1971 | int func = BP_FUNC(bp); |
1972 | u32 hw_lock_control_reg; | |
a2fbb9ea | 1973 | |
c18487ee YR |
1974 | /* Validating that the resource is within range */ |
1975 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | |
51c1a580 | 1976 | BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", |
c18487ee YR |
1977 | resource, HW_LOCK_MAX_RESOURCE_VALUE); |
1978 | return -EINVAL; | |
1979 | } | |
1980 | ||
4a37fb66 YG |
1981 | if (func <= 5) { |
1982 | hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); | |
1983 | } else { | |
1984 | hw_lock_control_reg = | |
1985 | (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); | |
1986 | } | |
1987 | ||
c18487ee | 1988 | /* Validating that the resource is currently taken */ |
4a37fb66 | 1989 | lock_status = REG_RD(bp, hw_lock_control_reg); |
c18487ee | 1990 | if (!(lock_status & resource_bit)) { |
6bf07b8e YM |
1991 | BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", |
1992 | lock_status, resource_bit); | |
c18487ee | 1993 | return -EFAULT; |
a2fbb9ea ET |
1994 | } |
1995 | ||
9f6c9258 DK |
1996 | REG_WR(bp, hw_lock_control_reg, resource_bit); |
1997 | return 0; | |
c18487ee | 1998 | } |
a2fbb9ea | 1999 | |
4acac6a5 EG |
2000 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) |
2001 | { | |
2002 | /* The GPIO should be swapped if swap register is set and active */ | |
2003 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2004 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2005 | int gpio_shift = gpio_num + | |
2006 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2007 | u32 gpio_mask = (1 << gpio_shift); | |
2008 | u32 gpio_reg; | |
2009 | int value; | |
2010 | ||
2011 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2012 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2013 | return -EINVAL; | |
2014 | } | |
2015 | ||
2016 | /* read GPIO value */ | |
2017 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2018 | ||
2019 | /* get the requested pin value */ | |
2020 | if ((gpio_reg & gpio_mask) == gpio_mask) | |
2021 | value = 1; | |
2022 | else | |
2023 | value = 0; | |
2024 | ||
2025 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | |
2026 | ||
2027 | return value; | |
2028 | } | |
2029 | ||
17de50b7 | 2030 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
c18487ee YR |
2031 | { |
2032 | /* The GPIO should be swapped if swap register is set and active */ | |
2033 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
17de50b7 | 2034 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; |
c18487ee YR |
2035 | int gpio_shift = gpio_num + |
2036 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2037 | u32 gpio_mask = (1 << gpio_shift); | |
2038 | u32 gpio_reg; | |
a2fbb9ea | 2039 | |
c18487ee YR |
2040 | if (gpio_num > MISC_REGISTERS_GPIO_3) { |
2041 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2042 | return -EINVAL; | |
2043 | } | |
a2fbb9ea | 2044 | |
4a37fb66 | 2045 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
c18487ee YR |
2046 | /* read GPIO and mask except the float bits */ |
2047 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | |
a2fbb9ea | 2048 | |
c18487ee YR |
2049 | switch (mode) { |
2050 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
51c1a580 MS |
2051 | DP(NETIF_MSG_LINK, |
2052 | "Set GPIO %d (shift %d) -> output low\n", | |
c18487ee YR |
2053 | gpio_num, gpio_shift); |
2054 | /* clear FLOAT and set CLR */ | |
2055 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2056 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | |
2057 | break; | |
a2fbb9ea | 2058 | |
c18487ee | 2059 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: |
51c1a580 MS |
2060 | DP(NETIF_MSG_LINK, |
2061 | "Set GPIO %d (shift %d) -> output high\n", | |
c18487ee YR |
2062 | gpio_num, gpio_shift); |
2063 | /* clear FLOAT and set SET */ | |
2064 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2065 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | |
2066 | break; | |
a2fbb9ea | 2067 | |
17de50b7 | 2068 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: |
51c1a580 MS |
2069 | DP(NETIF_MSG_LINK, |
2070 | "Set GPIO %d (shift %d) -> input\n", | |
c18487ee YR |
2071 | gpio_num, gpio_shift); |
2072 | /* set FLOAT */ | |
2073 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2074 | break; | |
a2fbb9ea | 2075 | |
c18487ee YR |
2076 | default: |
2077 | break; | |
a2fbb9ea ET |
2078 | } |
2079 | ||
c18487ee | 2080 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); |
4a37fb66 | 2081 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); |
f1410647 | 2082 | |
c18487ee | 2083 | return 0; |
a2fbb9ea ET |
2084 | } |
2085 | ||
0d40f0d4 YR |
2086 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) |
2087 | { | |
2088 | u32 gpio_reg = 0; | |
2089 | int rc = 0; | |
2090 | ||
2091 | /* Any port swapping should be handled by caller. */ | |
2092 | ||
2093 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2094 | /* read GPIO and mask except the float bits */ | |
2095 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | |
2096 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2097 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2098 | gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); | |
2099 | ||
2100 | switch (mode) { | |
2101 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | |
2102 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); | |
2103 | /* set CLR */ | |
2104 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); | |
2105 | break; | |
2106 | ||
2107 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | |
2108 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); | |
2109 | /* set SET */ | |
2110 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); | |
2111 | break; | |
2112 | ||
2113 | case MISC_REGISTERS_GPIO_INPUT_HI_Z: | |
2114 | DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); | |
2115 | /* set FLOAT */ | |
2116 | gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); | |
2117 | break; | |
2118 | ||
2119 | default: | |
2120 | BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); | |
2121 | rc = -EINVAL; | |
2122 | break; | |
2123 | } | |
2124 | ||
2125 | if (rc == 0) | |
2126 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | |
2127 | ||
2128 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2129 | ||
2130 | return rc; | |
2131 | } | |
2132 | ||
4acac6a5 EG |
2133 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
2134 | { | |
2135 | /* The GPIO should be swapped if swap register is set and active */ | |
2136 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | |
2137 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | |
2138 | int gpio_shift = gpio_num + | |
2139 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | |
2140 | u32 gpio_mask = (1 << gpio_shift); | |
2141 | u32 gpio_reg; | |
2142 | ||
2143 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | |
2144 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | |
2145 | return -EINVAL; | |
2146 | } | |
2147 | ||
2148 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2149 | /* read GPIO int */ | |
2150 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | |
2151 | ||
2152 | switch (mode) { | |
2153 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | |
51c1a580 MS |
2154 | DP(NETIF_MSG_LINK, |
2155 | "Clear GPIO INT %d (shift %d) -> output low\n", | |
2156 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2157 | /* clear SET and set CLR */ |
2158 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2159 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2160 | break; | |
2161 | ||
2162 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | |
51c1a580 MS |
2163 | DP(NETIF_MSG_LINK, |
2164 | "Set GPIO INT %d (shift %d) -> output high\n", | |
2165 | gpio_num, gpio_shift); | |
4acac6a5 EG |
2166 | /* clear CLR and set SET */ |
2167 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | |
2168 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | |
2169 | break; | |
2170 | ||
2171 | default: | |
2172 | break; | |
2173 | } | |
2174 | ||
2175 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | |
2176 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | |
2177 | ||
2178 | return 0; | |
2179 | } | |
2180 | ||
d6d99a3f | 2181 | static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) |
a2fbb9ea | 2182 | { |
c18487ee | 2183 | u32 spio_reg; |
a2fbb9ea | 2184 | |
d6d99a3f YM |
2185 | /* Only 2 SPIOs are configurable */ |
2186 | if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { | |
2187 | BNX2X_ERR("Invalid SPIO 0x%x\n", spio); | |
c18487ee | 2188 | return -EINVAL; |
a2fbb9ea ET |
2189 | } |
2190 | ||
4a37fb66 | 2191 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2192 | /* read SPIO and mask except the float bits */ |
d6d99a3f | 2193 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); |
a2fbb9ea | 2194 | |
c18487ee | 2195 | switch (mode) { |
d6d99a3f YM |
2196 | case MISC_SPIO_OUTPUT_LOW: |
2197 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); | |
c18487ee | 2198 | /* clear FLOAT and set CLR */ |
d6d99a3f YM |
2199 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2200 | spio_reg |= (spio << MISC_SPIO_CLR_POS); | |
c18487ee | 2201 | break; |
a2fbb9ea | 2202 | |
d6d99a3f YM |
2203 | case MISC_SPIO_OUTPUT_HIGH: |
2204 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); | |
c18487ee | 2205 | /* clear FLOAT and set SET */ |
d6d99a3f YM |
2206 | spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); |
2207 | spio_reg |= (spio << MISC_SPIO_SET_POS); | |
c18487ee | 2208 | break; |
a2fbb9ea | 2209 | |
d6d99a3f YM |
2210 | case MISC_SPIO_INPUT_HI_Z: |
2211 | DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); | |
c18487ee | 2212 | /* set FLOAT */ |
d6d99a3f | 2213 | spio_reg |= (spio << MISC_SPIO_FLOAT_POS); |
c18487ee | 2214 | break; |
a2fbb9ea | 2215 | |
c18487ee YR |
2216 | default: |
2217 | break; | |
a2fbb9ea ET |
2218 | } |
2219 | ||
c18487ee | 2220 | REG_WR(bp, MISC_REG_SPIO, spio_reg); |
4a37fb66 | 2221 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); |
c18487ee | 2222 | |
a2fbb9ea ET |
2223 | return 0; |
2224 | } | |
2225 | ||
9f6c9258 | 2226 | void bnx2x_calc_fc_adv(struct bnx2x *bp) |
a2fbb9ea | 2227 | { |
a22f0788 | 2228 | u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); |
ad33ea3a EG |
2229 | switch (bp->link_vars.ieee_fc & |
2230 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { | |
c18487ee | 2231 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: |
a22f0788 | 2232 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2233 | ADVERTISED_Pause); |
c18487ee | 2234 | break; |
356e2385 | 2235 | |
c18487ee | 2236 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: |
a22f0788 | 2237 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | |
f85582f8 | 2238 | ADVERTISED_Pause); |
c18487ee | 2239 | break; |
356e2385 | 2240 | |
c18487ee | 2241 | case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: |
a22f0788 | 2242 | bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; |
c18487ee | 2243 | break; |
356e2385 | 2244 | |
c18487ee | 2245 | default: |
a22f0788 | 2246 | bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | |
f85582f8 | 2247 | ADVERTISED_Pause); |
c18487ee YR |
2248 | break; |
2249 | } | |
2250 | } | |
f1410647 | 2251 | |
cd1dfce2 | 2252 | static void bnx2x_set_requested_fc(struct bnx2x *bp) |
c18487ee | 2253 | { |
cd1dfce2 YM |
2254 | /* Initialize link parameters structure variables |
2255 | * It is recommended to turn off RX FC for jumbo frames | |
2256 | * for better performance | |
2257 | */ | |
2258 | if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) | |
2259 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; | |
2260 | else | |
2261 | bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; | |
2262 | } | |
a2fbb9ea | 2263 | |
9156b30b DK |
2264 | static void bnx2x_init_dropless_fc(struct bnx2x *bp) |
2265 | { | |
2266 | u32 pause_enabled = 0; | |
2267 | ||
2268 | if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { | |
2269 | if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
2270 | pause_enabled = 1; | |
2271 | ||
2272 | REG_WR(bp, BAR_USTRORM_INTMEM + | |
2273 | USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), | |
2274 | pause_enabled); | |
2275 | } | |
2276 | ||
2277 | DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", | |
2278 | pause_enabled ? "enabled" : "disabled"); | |
2279 | } | |
2280 | ||
cd1dfce2 YM |
2281 | int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) |
2282 | { | |
2283 | int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); | |
2284 | u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; | |
2285 | ||
2286 | if (!BP_NOMCP(bp)) { | |
2287 | bnx2x_set_requested_fc(bp); | |
4a37fb66 | 2288 | bnx2x_acquire_phy_lock(bp); |
b5bf9068 | 2289 | |
a22f0788 | 2290 | if (load_mode == LOAD_DIAG) { |
1cb0c788 YR |
2291 | struct link_params *lp = &bp->link_params; |
2292 | lp->loopback_mode = LOOPBACK_XGXS; | |
2293 | /* do PHY loopback at 10G speed, if possible */ | |
2294 | if (lp->req_line_speed[cfx_idx] < SPEED_10000) { | |
2295 | if (lp->speed_cap_mask[cfx_idx] & | |
2296 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
2297 | lp->req_line_speed[cfx_idx] = | |
2298 | SPEED_10000; | |
2299 | else | |
2300 | lp->req_line_speed[cfx_idx] = | |
2301 | SPEED_1000; | |
2302 | } | |
a22f0788 | 2303 | } |
b5bf9068 | 2304 | |
8970b2e4 MS |
2305 | if (load_mode == LOAD_LOOPBACK_EXT) { |
2306 | struct link_params *lp = &bp->link_params; | |
2307 | lp->loopback_mode = LOOPBACK_EXT; | |
2308 | } | |
2309 | ||
19680c48 | 2310 | rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
b5bf9068 | 2311 | |
4a37fb66 | 2312 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2313 | |
9156b30b DK |
2314 | bnx2x_init_dropless_fc(bp); |
2315 | ||
3c96c68b EG |
2316 | bnx2x_calc_fc_adv(bp); |
2317 | ||
cd1dfce2 | 2318 | if (bp->link_vars.link_up) { |
b5bf9068 | 2319 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
19680c48 | 2320 | bnx2x_link_report(bp); |
cd1dfce2 YM |
2321 | } |
2322 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
a22f0788 | 2323 | bp->link_params.req_line_speed[cfx_idx] = req_line_speed; |
19680c48 EG |
2324 | return rc; |
2325 | } | |
f5372251 | 2326 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); |
19680c48 | 2327 | return -EINVAL; |
a2fbb9ea ET |
2328 | } |
2329 | ||
9f6c9258 | 2330 | void bnx2x_link_set(struct bnx2x *bp) |
a2fbb9ea | 2331 | { |
19680c48 | 2332 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2333 | bnx2x_acquire_phy_lock(bp); |
19680c48 | 2334 | bnx2x_phy_init(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2335 | bnx2x_release_phy_lock(bp); |
a2fbb9ea | 2336 | |
9156b30b DK |
2337 | bnx2x_init_dropless_fc(bp); |
2338 | ||
19680c48 EG |
2339 | bnx2x_calc_fc_adv(bp); |
2340 | } else | |
f5372251 | 2341 | BNX2X_ERR("Bootcode is missing - can not set link\n"); |
c18487ee | 2342 | } |
a2fbb9ea | 2343 | |
c18487ee YR |
2344 | static void bnx2x__link_reset(struct bnx2x *bp) |
2345 | { | |
19680c48 | 2346 | if (!BP_NOMCP(bp)) { |
4a37fb66 | 2347 | bnx2x_acquire_phy_lock(bp); |
5d07d868 | 2348 | bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); |
4a37fb66 | 2349 | bnx2x_release_phy_lock(bp); |
19680c48 | 2350 | } else |
f5372251 | 2351 | BNX2X_ERR("Bootcode is missing - can not reset link\n"); |
c18487ee | 2352 | } |
a2fbb9ea | 2353 | |
5d07d868 YM |
2354 | void bnx2x_force_link_reset(struct bnx2x *bp) |
2355 | { | |
2356 | bnx2x_acquire_phy_lock(bp); | |
2357 | bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); | |
2358 | bnx2x_release_phy_lock(bp); | |
2359 | } | |
2360 | ||
a22f0788 | 2361 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) |
c18487ee | 2362 | { |
2145a920 | 2363 | u8 rc = 0; |
a2fbb9ea | 2364 | |
2145a920 VZ |
2365 | if (!BP_NOMCP(bp)) { |
2366 | bnx2x_acquire_phy_lock(bp); | |
a22f0788 YR |
2367 | rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, |
2368 | is_serdes); | |
2145a920 VZ |
2369 | bnx2x_release_phy_lock(bp); |
2370 | } else | |
2371 | BNX2X_ERR("Bootcode is missing - can not test link\n"); | |
a2fbb9ea | 2372 | |
c18487ee YR |
2373 | return rc; |
2374 | } | |
a2fbb9ea | 2375 | |
2691d51d EG |
2376 | /* Calculates the sum of vn_min_rates. |
2377 | It's needed for further normalizing of the min_rates. | |
2378 | Returns: | |
2379 | sum of vn_min_rates. | |
2380 | or | |
2381 | 0 - if all the min_rates are 0. | |
16a5fd92 | 2382 | In the later case fairness algorithm should be deactivated. |
2691d51d EG |
2383 | If not all min_rates are zero then those that are zeroes will be set to 1. |
2384 | */ | |
b475d78f YM |
2385 | static void bnx2x_calc_vn_min(struct bnx2x *bp, |
2386 | struct cmng_init_input *input) | |
2691d51d EG |
2387 | { |
2388 | int all_zero = 1; | |
2691d51d EG |
2389 | int vn; |
2390 | ||
3395a033 | 2391 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
f2e0899f | 2392 | u32 vn_cfg = bp->mf_config[vn]; |
2691d51d EG |
2393 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2394 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | |
2395 | ||
2396 | /* Skip hidden vns */ | |
2397 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) | |
b475d78f | 2398 | vn_min_rate = 0; |
2691d51d | 2399 | /* If min rate is zero - set it to 1 */ |
b475d78f | 2400 | else if (!vn_min_rate) |
2691d51d EG |
2401 | vn_min_rate = DEF_MIN_RATE; |
2402 | else | |
2403 | all_zero = 0; | |
2404 | ||
b475d78f | 2405 | input->vnic_min_rate[vn] = vn_min_rate; |
2691d51d EG |
2406 | } |
2407 | ||
30ae438b DK |
2408 | /* if ETS or all min rates are zeros - disable fairness */ |
2409 | if (BNX2X_IS_ETS_ENABLED(bp)) { | |
b475d78f | 2410 | input->flags.cmng_enables &= |
30ae438b DK |
2411 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2412 | DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); | |
2413 | } else if (all_zero) { | |
b475d78f | 2414 | input->flags.cmng_enables &= |
b015e3d1 | 2415 | ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
b475d78f YM |
2416 | DP(NETIF_MSG_IFUP, |
2417 | "All MIN values are zeroes fairness will be disabled\n"); | |
b015e3d1 | 2418 | } else |
b475d78f | 2419 | input->flags.cmng_enables |= |
b015e3d1 | 2420 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2691d51d EG |
2421 | } |
2422 | ||
b475d78f YM |
2423 | static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, |
2424 | struct cmng_init_input *input) | |
34f80b04 | 2425 | { |
b475d78f | 2426 | u16 vn_max_rate; |
f2e0899f | 2427 | u32 vn_cfg = bp->mf_config[vn]; |
34f80b04 | 2428 | |
b475d78f | 2429 | if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) |
34f80b04 | 2430 | vn_max_rate = 0; |
b475d78f | 2431 | else { |
faa6fcbb DK |
2432 | u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); |
2433 | ||
b475d78f | 2434 | if (IS_MF_SI(bp)) { |
faa6fcbb DK |
2435 | /* maxCfg in percents of linkspeed */ |
2436 | vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; | |
b475d78f | 2437 | } else /* SD modes */ |
faa6fcbb DK |
2438 | /* maxCfg is absolute in 100Mb units */ |
2439 | vn_max_rate = maxCfg * 100; | |
34f80b04 | 2440 | } |
f85582f8 | 2441 | |
b475d78f | 2442 | DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); |
34f80b04 | 2443 | |
b475d78f | 2444 | input->vnic_max_rate[vn] = vn_max_rate; |
34f80b04 | 2445 | } |
f85582f8 | 2446 | |
523224a3 DK |
2447 | static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) |
2448 | { | |
2449 | if (CHIP_REV_IS_SLOW(bp)) | |
2450 | return CMNG_FNS_NONE; | |
fb3bff17 | 2451 | if (IS_MF(bp)) |
523224a3 DK |
2452 | return CMNG_FNS_MINMAX; |
2453 | ||
2454 | return CMNG_FNS_NONE; | |
2455 | } | |
2456 | ||
2ae17f66 | 2457 | void bnx2x_read_mf_cfg(struct bnx2x *bp) |
523224a3 | 2458 | { |
0793f83f | 2459 | int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); |
523224a3 DK |
2460 | |
2461 | if (BP_NOMCP(bp)) | |
16a5fd92 | 2462 | return; /* what should be the default value in this case */ |
523224a3 | 2463 | |
0793f83f DK |
2464 | /* For 2 port configuration the absolute function number formula |
2465 | * is: | |
2466 | * abs_func = 2 * vn + BP_PORT + BP_PATH | |
2467 | * | |
2468 | * and there are 4 functions per port | |
2469 | * | |
2470 | * For 4 port configuration it is | |
2471 | * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH | |
2472 | * | |
2473 | * and there are 2 functions per port | |
2474 | */ | |
3395a033 | 2475 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
0793f83f DK |
2476 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2477 | ||
2478 | if (func >= E1H_FUNC_MAX) | |
2479 | break; | |
2480 | ||
f2e0899f | 2481 | bp->mf_config[vn] = |
523224a3 DK |
2482 | MF_CFG_RD(bp, func_mf_config[func].config); |
2483 | } | |
a3348722 BW |
2484 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
2485 | DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); | |
2486 | bp->flags |= MF_FUNC_DIS; | |
2487 | } else { | |
2488 | DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); | |
2489 | bp->flags &= ~MF_FUNC_DIS; | |
2490 | } | |
523224a3 DK |
2491 | } |
2492 | ||
2493 | static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |
2494 | { | |
b475d78f YM |
2495 | struct cmng_init_input input; |
2496 | memset(&input, 0, sizeof(struct cmng_init_input)); | |
2497 | ||
2498 | input.port_rate = bp->link_vars.line_speed; | |
523224a3 | 2499 | |
568e2426 | 2500 | if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { |
523224a3 DK |
2501 | int vn; |
2502 | ||
523224a3 DK |
2503 | /* read mf conf from shmem */ |
2504 | if (read_cfg) | |
2505 | bnx2x_read_mf_cfg(bp); | |
2506 | ||
523224a3 | 2507 | /* vn_weight_sum and enable fairness if not 0 */ |
b475d78f | 2508 | bnx2x_calc_vn_min(bp, &input); |
523224a3 DK |
2509 | |
2510 | /* calculate and set min-max rate for each vn */ | |
c4154f25 | 2511 | if (bp->port.pmf) |
3395a033 | 2512 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
b475d78f | 2513 | bnx2x_calc_vn_max(bp, vn, &input); |
523224a3 DK |
2514 | |
2515 | /* always enable rate shaping and fairness */ | |
b475d78f | 2516 | input.flags.cmng_enables |= |
523224a3 | 2517 | CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; |
b475d78f YM |
2518 | |
2519 | bnx2x_init_cmng(&input, &bp->cmng); | |
523224a3 DK |
2520 | return; |
2521 | } | |
2522 | ||
2523 | /* rate shaping and fairness are disabled */ | |
2524 | DP(NETIF_MSG_IFUP, | |
2525 | "rate shaping and fairness are disabled\n"); | |
2526 | } | |
34f80b04 | 2527 | |
1191cb83 ED |
2528 | static void storm_memset_cmng(struct bnx2x *bp, |
2529 | struct cmng_init *cmng, | |
2530 | u8 port) | |
2531 | { | |
2532 | int vn; | |
2533 | size_t size = sizeof(struct cmng_struct_per_port); | |
2534 | ||
2535 | u32 addr = BAR_XSTRORM_INTMEM + | |
2536 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
2537 | ||
2538 | __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); | |
2539 | ||
2540 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { | |
2541 | int func = func_by_vn(bp, vn); | |
2542 | ||
2543 | addr = BAR_XSTRORM_INTMEM + | |
2544 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); | |
2545 | size = sizeof(struct rate_shaping_vars_per_vn); | |
2546 | __storm_memset_struct(bp, addr, size, | |
2547 | (u32 *)&cmng->vnic.vnic_max_rate[vn]); | |
2548 | ||
2549 | addr = BAR_XSTRORM_INTMEM + | |
2550 | XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); | |
2551 | size = sizeof(struct fairness_vars_per_vn); | |
2552 | __storm_memset_struct(bp, addr, size, | |
2553 | (u32 *)&cmng->vnic.vnic_min_rate[vn]); | |
2554 | } | |
2555 | } | |
2556 | ||
568e2426 DK |
2557 | /* init cmng mode in HW according to local configuration */ |
2558 | void bnx2x_set_local_cmng(struct bnx2x *bp) | |
2559 | { | |
2560 | int cmng_fns = bnx2x_get_cmng_fns_mode(bp); | |
2561 | ||
2562 | if (cmng_fns != CMNG_FNS_NONE) { | |
2563 | bnx2x_cmng_fns_init(bp, false, cmng_fns); | |
2564 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
2565 | } else { | |
2566 | /* rate shaping and fairness are disabled */ | |
2567 | DP(NETIF_MSG_IFUP, | |
2568 | "single function mode without fairness\n"); | |
2569 | } | |
2570 | } | |
2571 | ||
c18487ee YR |
2572 | /* This function is called upon link interrupt */ |
2573 | static void bnx2x_link_attn(struct bnx2x *bp) | |
2574 | { | |
bb2a0f7a YG |
2575 | /* Make sure that we are synced with the current statistics */ |
2576 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2577 | ||
c18487ee | 2578 | bnx2x_link_update(&bp->link_params, &bp->link_vars); |
a2fbb9ea | 2579 | |
9156b30b | 2580 | bnx2x_init_dropless_fc(bp); |
1c06328c | 2581 | |
9156b30b | 2582 | if (bp->link_vars.link_up) { |
1c06328c | 2583 | |
619c5cb6 | 2584 | if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { |
bb2a0f7a YG |
2585 | struct host_port_stats *pstats; |
2586 | ||
2587 | pstats = bnx2x_sp(bp, port_stats); | |
619c5cb6 | 2588 | /* reset old mac stats */ |
bb2a0f7a YG |
2589 | memset(&(pstats->mac_stx[0]), 0, |
2590 | sizeof(struct mac_stx)); | |
2591 | } | |
f34d28ea | 2592 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a YG |
2593 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
2594 | } | |
2595 | ||
568e2426 DK |
2596 | if (bp->link_vars.link_up && bp->link_vars.line_speed) |
2597 | bnx2x_set_local_cmng(bp); | |
9fdc3e95 | 2598 | |
2ae17f66 VZ |
2599 | __bnx2x_link_report(bp); |
2600 | ||
9fdc3e95 DK |
2601 | if (IS_MF(bp)) |
2602 | bnx2x_link_sync_notify(bp); | |
c18487ee | 2603 | } |
a2fbb9ea | 2604 | |
9f6c9258 | 2605 | void bnx2x__link_status_update(struct bnx2x *bp) |
c18487ee | 2606 | { |
2ae17f66 | 2607 | if (bp->state != BNX2X_STATE_OPEN) |
c18487ee | 2608 | return; |
a2fbb9ea | 2609 | |
00253a8c | 2610 | /* read updated dcb configuration */ |
ad5afc89 AE |
2611 | if (IS_PF(bp)) { |
2612 | bnx2x_dcbx_pmf_update(bp); | |
2613 | bnx2x_link_status_update(&bp->link_params, &bp->link_vars); | |
2614 | if (bp->link_vars.link_up) | |
2615 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); | |
2616 | else | |
2617 | bnx2x_stats_handle(bp, STATS_EVENT_STOP); | |
2618 | /* indicate link status */ | |
2619 | bnx2x_link_report(bp); | |
a2fbb9ea | 2620 | |
ad5afc89 AE |
2621 | } else { /* VF */ |
2622 | bp->port.supported[0] |= (SUPPORTED_10baseT_Half | | |
2623 | SUPPORTED_10baseT_Full | | |
2624 | SUPPORTED_100baseT_Half | | |
2625 | SUPPORTED_100baseT_Full | | |
2626 | SUPPORTED_1000baseT_Full | | |
2627 | SUPPORTED_2500baseX_Full | | |
2628 | SUPPORTED_10000baseT_Full | | |
2629 | SUPPORTED_TP | | |
2630 | SUPPORTED_FIBRE | | |
2631 | SUPPORTED_Autoneg | | |
2632 | SUPPORTED_Pause | | |
2633 | SUPPORTED_Asym_Pause); | |
2634 | bp->port.advertising[0] = bp->port.supported[0]; | |
2635 | ||
2636 | bp->link_params.bp = bp; | |
2637 | bp->link_params.port = BP_PORT(bp); | |
2638 | bp->link_params.req_duplex[0] = DUPLEX_FULL; | |
2639 | bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; | |
2640 | bp->link_params.req_line_speed[0] = SPEED_10000; | |
2641 | bp->link_params.speed_cap_mask[0] = 0x7f0000; | |
2642 | bp->link_params.switch_cfg = SWITCH_CFG_10G; | |
2643 | bp->link_vars.mac_type = MAC_TYPE_BMAC; | |
2644 | bp->link_vars.line_speed = SPEED_10000; | |
2645 | bp->link_vars.link_status = | |
2646 | (LINK_STATUS_LINK_UP | | |
2647 | LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); | |
2648 | bp->link_vars.link_up = 1; | |
2649 | bp->link_vars.duplex = DUPLEX_FULL; | |
2650 | bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
2651 | __bnx2x_link_report(bp); | |
bb2a0f7a | 2652 | bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); |
ad5afc89 | 2653 | } |
a2fbb9ea | 2654 | } |
a2fbb9ea | 2655 | |
a3348722 BW |
2656 | static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, |
2657 | u16 vlan_val, u8 allowed_prio) | |
2658 | { | |
86564c3f | 2659 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2660 | struct bnx2x_func_afex_update_params *f_update_params = |
2661 | &func_params.params.afex_update; | |
2662 | ||
2663 | func_params.f_obj = &bp->func_obj; | |
2664 | func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; | |
2665 | ||
2666 | /* no need to wait for RAMROD completion, so don't | |
2667 | * set RAMROD_COMP_WAIT flag | |
2668 | */ | |
2669 | ||
2670 | f_update_params->vif_id = vifid; | |
2671 | f_update_params->afex_default_vlan = vlan_val; | |
2672 | f_update_params->allowed_priorities = allowed_prio; | |
2673 | ||
2674 | /* if ramrod can not be sent, response to MCP immediately */ | |
2675 | if (bnx2x_func_state_change(bp, &func_params) < 0) | |
2676 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
2677 | ||
2678 | return 0; | |
2679 | } | |
2680 | ||
2681 | static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, | |
2682 | u16 vif_index, u8 func_bit_map) | |
2683 | { | |
86564c3f | 2684 | struct bnx2x_func_state_params func_params = {NULL}; |
a3348722 BW |
2685 | struct bnx2x_func_afex_viflists_params *update_params = |
2686 | &func_params.params.afex_viflists; | |
2687 | int rc; | |
2688 | u32 drv_msg_code; | |
2689 | ||
2690 | /* validate only LIST_SET and LIST_GET are received from switch */ | |
2691 | if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) | |
2692 | BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", | |
2693 | cmd_type); | |
2694 | ||
2695 | func_params.f_obj = &bp->func_obj; | |
2696 | func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; | |
2697 | ||
2698 | /* set parameters according to cmd_type */ | |
2699 | update_params->afex_vif_list_command = cmd_type; | |
86564c3f | 2700 | update_params->vif_list_index = vif_index; |
a3348722 BW |
2701 | update_params->func_bit_map = |
2702 | (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; | |
2703 | update_params->func_to_clear = 0; | |
2704 | drv_msg_code = | |
2705 | (cmd_type == VIF_LIST_RULE_GET) ? | |
2706 | DRV_MSG_CODE_AFEX_LISTGET_ACK : | |
2707 | DRV_MSG_CODE_AFEX_LISTSET_ACK; | |
2708 | ||
2709 | /* if ramrod can not be sent, respond to MCP immediately for | |
2710 | * SET and GET requests (other are not triggered from MCP) | |
2711 | */ | |
2712 | rc = bnx2x_func_state_change(bp, &func_params); | |
2713 | if (rc < 0) | |
2714 | bnx2x_fw_command(bp, drv_msg_code, 0); | |
2715 | ||
2716 | return 0; | |
2717 | } | |
2718 | ||
2719 | static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) | |
2720 | { | |
2721 | struct afex_stats afex_stats; | |
2722 | u32 func = BP_ABS_FUNC(bp); | |
2723 | u32 mf_config; | |
2724 | u16 vlan_val; | |
2725 | u32 vlan_prio; | |
2726 | u16 vif_id; | |
2727 | u8 allowed_prio; | |
2728 | u8 vlan_mode; | |
2729 | u32 addr_to_write, vifid, addrs, stats_type, i; | |
2730 | ||
2731 | if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { | |
2732 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2733 | DP(BNX2X_MSG_MCP, | |
2734 | "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); | |
2735 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); | |
2736 | } | |
2737 | ||
2738 | if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { | |
2739 | vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2740 | addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); | |
2741 | DP(BNX2X_MSG_MCP, | |
2742 | "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", | |
2743 | vifid, addrs); | |
2744 | bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, | |
2745 | addrs); | |
2746 | } | |
2747 | ||
2748 | if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { | |
2749 | addr_to_write = SHMEM2_RD(bp, | |
2750 | afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); | |
2751 | stats_type = SHMEM2_RD(bp, | |
2752 | afex_param1_to_driver[BP_FW_MB_IDX(bp)]); | |
2753 | ||
2754 | DP(BNX2X_MSG_MCP, | |
2755 | "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", | |
2756 | addr_to_write); | |
2757 | ||
2758 | bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); | |
2759 | ||
2760 | /* write response to scratchpad, for MCP */ | |
2761 | for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) | |
2762 | REG_WR(bp, addr_to_write + i*sizeof(u32), | |
2763 | *(((u32 *)(&afex_stats))+i)); | |
2764 | ||
2765 | /* send ack message to MCP */ | |
2766 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); | |
2767 | } | |
2768 | ||
2769 | if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { | |
2770 | mf_config = MF_CFG_RD(bp, func_mf_config[func].config); | |
2771 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2772 | DP(BNX2X_MSG_MCP, | |
2773 | "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", | |
2774 | mf_config); | |
2775 | ||
2776 | /* if VIF_SET is "enabled" */ | |
2777 | if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { | |
2778 | /* set rate limit directly to internal RAM */ | |
2779 | struct cmng_init_input cmng_input; | |
2780 | struct rate_shaping_vars_per_vn m_rs_vn; | |
2781 | size_t size = sizeof(struct rate_shaping_vars_per_vn); | |
2782 | u32 addr = BAR_XSTRORM_INTMEM + | |
2783 | XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); | |
2784 | ||
2785 | bp->mf_config[BP_VN(bp)] = mf_config; | |
2786 | ||
2787 | bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); | |
2788 | m_rs_vn.vn_counter.rate = | |
2789 | cmng_input.vnic_max_rate[BP_VN(bp)]; | |
2790 | m_rs_vn.vn_counter.quota = | |
2791 | (m_rs_vn.vn_counter.rate * | |
2792 | RS_PERIODIC_TIMEOUT_USEC) / 8; | |
2793 | ||
2794 | __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); | |
2795 | ||
2796 | /* read relevant values from mf_cfg struct in shmem */ | |
2797 | vif_id = | |
2798 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2799 | FUNC_MF_CFG_E1HOV_TAG_MASK) >> | |
2800 | FUNC_MF_CFG_E1HOV_TAG_SHIFT; | |
2801 | vlan_val = | |
2802 | (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
2803 | FUNC_MF_CFG_AFEX_VLAN_MASK) >> | |
2804 | FUNC_MF_CFG_AFEX_VLAN_SHIFT; | |
2805 | vlan_prio = (mf_config & | |
2806 | FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> | |
2807 | FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; | |
2808 | vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); | |
2809 | vlan_mode = | |
2810 | (MF_CFG_RD(bp, | |
2811 | func_mf_config[func].afex_config) & | |
2812 | FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> | |
2813 | FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; | |
2814 | allowed_prio = | |
2815 | (MF_CFG_RD(bp, | |
2816 | func_mf_config[func].afex_config) & | |
2817 | FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> | |
2818 | FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; | |
2819 | ||
2820 | /* send ramrod to FW, return in case of failure */ | |
2821 | if (bnx2x_afex_func_update(bp, vif_id, vlan_val, | |
2822 | allowed_prio)) | |
2823 | return; | |
2824 | ||
2825 | bp->afex_def_vlan_tag = vlan_val; | |
2826 | bp->afex_vlan_mode = vlan_mode; | |
2827 | } else { | |
2828 | /* notify link down because BP->flags is disabled */ | |
2829 | bnx2x_link_report(bp); | |
2830 | ||
2831 | /* send INVALID VIF ramrod to FW */ | |
2832 | bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); | |
2833 | ||
2834 | /* Reset the default afex VLAN */ | |
2835 | bp->afex_def_vlan_tag = -1; | |
2836 | } | |
2837 | } | |
2838 | } | |
2839 | ||
34f80b04 EG |
2840 | static void bnx2x_pmf_update(struct bnx2x *bp) |
2841 | { | |
2842 | int port = BP_PORT(bp); | |
2843 | u32 val; | |
2844 | ||
2845 | bp->port.pmf = 1; | |
51c1a580 | 2846 | DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); |
34f80b04 | 2847 | |
3deb8167 YR |
2848 | /* |
2849 | * We need the mb() to ensure the ordering between the writing to | |
2850 | * bp->port.pmf here and reading it from the bnx2x_periodic_task(). | |
2851 | */ | |
2852 | smp_mb(); | |
2853 | ||
2854 | /* queue a periodic task */ | |
2855 | queue_delayed_work(bnx2x_wq, &bp->period_task, 0); | |
2856 | ||
ef01854e DK |
2857 | bnx2x_dcbx_pmf_update(bp); |
2858 | ||
34f80b04 | 2859 | /* enable nig attention */ |
3395a033 | 2860 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
f2e0899f DK |
2861 | if (bp->common.int_block == INT_BLOCK_HC) { |
2862 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | |
2863 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | |
619c5cb6 | 2864 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
2865 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); |
2866 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); | |
2867 | } | |
bb2a0f7a YG |
2868 | |
2869 | bnx2x_stats_handle(bp, STATS_EVENT_PMF); | |
34f80b04 EG |
2870 | } |
2871 | ||
c18487ee | 2872 | /* end of Link */ |
a2fbb9ea ET |
2873 | |
2874 | /* slow path */ | |
2875 | ||
2876 | /* | |
2877 | * General service functions | |
2878 | */ | |
2879 | ||
2691d51d | 2880 | /* send the MCP a request, block until there is a reply */ |
a22f0788 | 2881 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) |
2691d51d | 2882 | { |
f2e0899f | 2883 | int mb_idx = BP_FW_MB_IDX(bp); |
a5971d43 | 2884 | u32 seq; |
2691d51d EG |
2885 | u32 rc = 0; |
2886 | u32 cnt = 1; | |
2887 | u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; | |
2888 | ||
c4ff7cbf | 2889 | mutex_lock(&bp->fw_mb_mutex); |
a5971d43 | 2890 | seq = ++bp->fw_seq; |
f2e0899f DK |
2891 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); |
2892 | SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); | |
2893 | ||
754a2f52 DK |
2894 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", |
2895 | (command | seq), param); | |
2691d51d EG |
2896 | |
2897 | do { | |
2898 | /* let the FW do it's magic ... */ | |
2899 | msleep(delay); | |
2900 | ||
f2e0899f | 2901 | rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); |
2691d51d | 2902 | |
c4ff7cbf EG |
2903 | /* Give the FW up to 5 second (500*10ms) */ |
2904 | } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); | |
2691d51d EG |
2905 | |
2906 | DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", | |
2907 | cnt*delay, rc, seq); | |
2908 | ||
2909 | /* is this a reply to our command? */ | |
2910 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) | |
2911 | rc &= FW_MSG_CODE_MASK; | |
2912 | else { | |
2913 | /* FW BUG! */ | |
2914 | BNX2X_ERR("FW failed to respond!\n"); | |
2915 | bnx2x_fw_dump(bp); | |
2916 | rc = 0; | |
2917 | } | |
c4ff7cbf | 2918 | mutex_unlock(&bp->fw_mb_mutex); |
2691d51d EG |
2919 | |
2920 | return rc; | |
2921 | } | |
2922 | ||
1191cb83 ED |
2923 | static void storm_memset_func_cfg(struct bnx2x *bp, |
2924 | struct tstorm_eth_function_common_config *tcfg, | |
2925 | u16 abs_fid) | |
2926 | { | |
2927 | size_t size = sizeof(struct tstorm_eth_function_common_config); | |
2928 | ||
2929 | u32 addr = BAR_TSTRORM_INTMEM + | |
2930 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); | |
2931 | ||
2932 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); | |
2933 | } | |
2934 | ||
619c5cb6 VZ |
2935 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) |
2936 | { | |
2937 | if (CHIP_IS_E1x(bp)) { | |
2938 | struct tstorm_eth_function_common_config tcfg = {0}; | |
2939 | ||
2940 | storm_memset_func_cfg(bp, &tcfg, p->func_id); | |
2941 | } | |
2942 | ||
2943 | /* Enable the function in the FW */ | |
2944 | storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); | |
2945 | storm_memset_func_en(bp, p->func_id, 1); | |
2946 | ||
2947 | /* spq */ | |
2948 | if (p->func_flgs & FUNC_FLG_SPQ) { | |
2949 | storm_memset_spq_addr(bp, p->spq_map, p->func_id); | |
2950 | REG_WR(bp, XSEM_REG_FAST_MEMORY + | |
2951 | XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); | |
2952 | } | |
2953 | } | |
2954 | ||
6383c0b3 | 2955 | /** |
16a5fd92 | 2956 | * bnx2x_get_common_flags - Return common flags |
6383c0b3 AE |
2957 | * |
2958 | * @bp device handle | |
2959 | * @fp queue handle | |
2960 | * @zero_stats TRUE if statistics zeroing is needed | |
2961 | * | |
2962 | * Return the flags that are common for the Tx-only and not normal connections. | |
2963 | */ | |
1191cb83 ED |
2964 | static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, |
2965 | struct bnx2x_fastpath *fp, | |
2966 | bool zero_stats) | |
28912902 | 2967 | { |
619c5cb6 VZ |
2968 | unsigned long flags = 0; |
2969 | ||
2970 | /* PF driver will always initialize the Queue to an ACTIVE state */ | |
2971 | __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); | |
28912902 | 2972 | |
6383c0b3 | 2973 | /* tx only connections collect statistics (on the same index as the |
91226790 DK |
2974 | * parent connection). The statistics are zeroed when the parent |
2975 | * connection is initialized. | |
6383c0b3 | 2976 | */ |
50f0a562 BW |
2977 | |
2978 | __set_bit(BNX2X_Q_FLG_STATS, &flags); | |
2979 | if (zero_stats) | |
2980 | __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); | |
2981 | ||
91226790 | 2982 | __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); |
e287a75c | 2983 | __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); |
6383c0b3 | 2984 | |
823e1d90 YM |
2985 | #ifdef BNX2X_STOP_ON_ERROR |
2986 | __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); | |
2987 | #endif | |
2988 | ||
6383c0b3 AE |
2989 | return flags; |
2990 | } | |
2991 | ||
1191cb83 ED |
2992 | static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, |
2993 | struct bnx2x_fastpath *fp, | |
2994 | bool leading) | |
6383c0b3 AE |
2995 | { |
2996 | unsigned long flags = 0; | |
2997 | ||
619c5cb6 VZ |
2998 | /* calculate other queue flags */ |
2999 | if (IS_MF_SD(bp)) | |
3000 | __set_bit(BNX2X_Q_FLG_OV, &flags); | |
28912902 | 3001 | |
a3348722 | 3002 | if (IS_FCOE_FP(fp)) { |
619c5cb6 | 3003 | __set_bit(BNX2X_Q_FLG_FCOE, &flags); |
a3348722 BW |
3004 | /* For FCoE - force usage of default priority (for afex) */ |
3005 | __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); | |
3006 | } | |
523224a3 | 3007 | |
f5219d8e | 3008 | if (!fp->disable_tpa) { |
619c5cb6 | 3009 | __set_bit(BNX2X_Q_FLG_TPA, &flags); |
f5219d8e | 3010 | __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); |
621b4d66 DK |
3011 | if (fp->mode == TPA_MODE_GRO) |
3012 | __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); | |
f5219d8e | 3013 | } |
619c5cb6 | 3014 | |
619c5cb6 VZ |
3015 | if (leading) { |
3016 | __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); | |
3017 | __set_bit(BNX2X_Q_FLG_MCAST, &flags); | |
3018 | } | |
523224a3 | 3019 | |
619c5cb6 VZ |
3020 | /* Always set HW VLAN stripping */ |
3021 | __set_bit(BNX2X_Q_FLG_VLAN, &flags); | |
523224a3 | 3022 | |
a3348722 BW |
3023 | /* configure silent vlan removal */ |
3024 | if (IS_MF_AFEX(bp)) | |
3025 | __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); | |
3026 | ||
6383c0b3 | 3027 | return flags | bnx2x_get_common_flags(bp, fp, true); |
523224a3 DK |
3028 | } |
3029 | ||
619c5cb6 | 3030 | static void bnx2x_pf_q_prep_general(struct bnx2x *bp, |
6383c0b3 AE |
3031 | struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, |
3032 | u8 cos) | |
619c5cb6 VZ |
3033 | { |
3034 | gen_init->stat_id = bnx2x_stats_id(fp); | |
3035 | gen_init->spcl_id = fp->cl_id; | |
3036 | ||
3037 | /* Always use mini-jumbo MTU for FCoE L2 ring */ | |
3038 | if (IS_FCOE_FP(fp)) | |
3039 | gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; | |
3040 | else | |
3041 | gen_init->mtu = bp->dev->mtu; | |
6383c0b3 AE |
3042 | |
3043 | gen_init->cos = cos; | |
619c5cb6 VZ |
3044 | } |
3045 | ||
3046 | static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |
523224a3 | 3047 | struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, |
619c5cb6 | 3048 | struct bnx2x_rxq_setup_params *rxq_init) |
523224a3 | 3049 | { |
619c5cb6 | 3050 | u8 max_sge = 0; |
523224a3 DK |
3051 | u16 sge_sz = 0; |
3052 | u16 tpa_agg_size = 0; | |
3053 | ||
523224a3 | 3054 | if (!fp->disable_tpa) { |
dfacf138 DK |
3055 | pause->sge_th_lo = SGE_TH_LO(bp); |
3056 | pause->sge_th_hi = SGE_TH_HI(bp); | |
3057 | ||
3058 | /* validate SGE ring has enough to cross high threshold */ | |
3059 | WARN_ON(bp->dropless_fc && | |
3060 | pause->sge_th_hi + FW_PREFETCH_CNT > | |
3061 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | |
3062 | ||
924d75ab | 3063 | tpa_agg_size = TPA_AGG_SIZE; |
523224a3 DK |
3064 | max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> |
3065 | SGE_PAGE_SHIFT; | |
3066 | max_sge = ((max_sge + PAGES_PER_SGE - 1) & | |
3067 | (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; | |
924d75ab | 3068 | sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); |
523224a3 DK |
3069 | } |
3070 | ||
3071 | /* pause - not for e1 */ | |
3072 | if (!CHIP_IS_E1(bp)) { | |
dfacf138 DK |
3073 | pause->bd_th_lo = BD_TH_LO(bp); |
3074 | pause->bd_th_hi = BD_TH_HI(bp); | |
3075 | ||
3076 | pause->rcq_th_lo = RCQ_TH_LO(bp); | |
3077 | pause->rcq_th_hi = RCQ_TH_HI(bp); | |
3078 | /* | |
3079 | * validate that rings have enough entries to cross | |
3080 | * high thresholds | |
3081 | */ | |
3082 | WARN_ON(bp->dropless_fc && | |
3083 | pause->bd_th_hi + FW_PREFETCH_CNT > | |
3084 | bp->rx_ring_size); | |
3085 | WARN_ON(bp->dropless_fc && | |
3086 | pause->rcq_th_hi + FW_PREFETCH_CNT > | |
3087 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | |
619c5cb6 | 3088 | |
523224a3 DK |
3089 | pause->pri_map = 1; |
3090 | } | |
3091 | ||
3092 | /* rxq setup */ | |
523224a3 DK |
3093 | rxq_init->dscr_map = fp->rx_desc_mapping; |
3094 | rxq_init->sge_map = fp->rx_sge_mapping; | |
3095 | rxq_init->rcq_map = fp->rx_comp_mapping; | |
3096 | rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; | |
a8c94b91 | 3097 | |
619c5cb6 VZ |
3098 | /* This should be a maximum number of data bytes that may be |
3099 | * placed on the BD (not including paddings). | |
3100 | */ | |
e52fcb24 | 3101 | rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - |
3cdeec22 | 3102 | BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; |
a8c94b91 | 3103 | |
523224a3 | 3104 | rxq_init->cl_qzone_id = fp->cl_qzone_id; |
523224a3 DK |
3105 | rxq_init->tpa_agg_sz = tpa_agg_size; |
3106 | rxq_init->sge_buf_sz = sge_sz; | |
3107 | rxq_init->max_sges_pkt = max_sge; | |
619c5cb6 | 3108 | rxq_init->rss_engine_id = BP_FUNC(bp); |
259afa1f | 3109 | rxq_init->mcast_engine_id = BP_FUNC(bp); |
619c5cb6 VZ |
3110 | |
3111 | /* Maximum number or simultaneous TPA aggregation for this Queue. | |
3112 | * | |
2de67439 | 3113 | * For PF Clients it should be the maximum available number. |
619c5cb6 VZ |
3114 | * VF driver(s) may want to define it to a smaller value. |
3115 | */ | |
dfacf138 | 3116 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
619c5cb6 | 3117 | |
523224a3 DK |
3118 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
3119 | rxq_init->fw_sb_id = fp->fw_sb_id; | |
3120 | ||
ec6ba945 VZ |
3121 | if (IS_FCOE_FP(fp)) |
3122 | rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; | |
3123 | else | |
6383c0b3 | 3124 | rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
a3348722 BW |
3125 | /* configure silent vlan removal |
3126 | * if multi function mode is afex, then mask default vlan | |
3127 | */ | |
3128 | if (IS_MF_AFEX(bp)) { | |
3129 | rxq_init->silent_removal_value = bp->afex_def_vlan_tag; | |
3130 | rxq_init->silent_removal_mask = VLAN_VID_MASK; | |
3131 | } | |
523224a3 DK |
3132 | } |
3133 | ||
619c5cb6 | 3134 | static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, |
6383c0b3 AE |
3135 | struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, |
3136 | u8 cos) | |
523224a3 | 3137 | { |
65565884 | 3138 | txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; |
6383c0b3 | 3139 | txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; |
523224a3 DK |
3140 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; |
3141 | txq_init->fw_sb_id = fp->fw_sb_id; | |
ec6ba945 | 3142 | |
619c5cb6 | 3143 | /* |
16a5fd92 | 3144 | * set the tss leading client id for TX classification == |
619c5cb6 VZ |
3145 | * leading RSS client id |
3146 | */ | |
3147 | txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); | |
3148 | ||
ec6ba945 VZ |
3149 | if (IS_FCOE_FP(fp)) { |
3150 | txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; | |
3151 | txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; | |
3152 | } | |
523224a3 DK |
3153 | } |
3154 | ||
8d96286a | 3155 | static void bnx2x_pf_init(struct bnx2x *bp) |
523224a3 DK |
3156 | { |
3157 | struct bnx2x_func_init_params func_init = {0}; | |
523224a3 DK |
3158 | struct event_ring_data eq_data = { {0} }; |
3159 | u16 flags; | |
3160 | ||
619c5cb6 | 3161 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
3162 | /* reset IGU PF statistics: MSIX + ATTN */ |
3163 | /* PF */ | |
3164 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3165 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3166 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3167 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3168 | /* ATTN */ | |
3169 | REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + | |
3170 | BNX2X_IGU_STAS_MSG_VF_CNT*4 + | |
3171 | BNX2X_IGU_STAS_MSG_PF_CNT*4 + | |
3172 | (CHIP_MODE_IS_4_PORT(bp) ? | |
3173 | BP_FUNC(bp) : BP_VN(bp))*4, 0); | |
3174 | } | |
3175 | ||
523224a3 DK |
3176 | /* function setup flags */ |
3177 | flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); | |
3178 | ||
619c5cb6 VZ |
3179 | /* This flag is relevant for E1x only. |
3180 | * E2 doesn't have a TPA configuration in a function level. | |
523224a3 | 3181 | */ |
619c5cb6 | 3182 | flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0; |
523224a3 DK |
3183 | |
3184 | func_init.func_flgs = flags; | |
3185 | func_init.pf_id = BP_FUNC(bp); | |
3186 | func_init.func_id = BP_FUNC(bp); | |
523224a3 DK |
3187 | func_init.spq_map = bp->spq_mapping; |
3188 | func_init.spq_prod = bp->spq_prod_idx; | |
3189 | ||
3190 | bnx2x_func_init(bp, &func_init); | |
3191 | ||
3192 | memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); | |
3193 | ||
3194 | /* | |
619c5cb6 VZ |
3195 | * Congestion management values depend on the link rate |
3196 | * There is no active link so initial link rate is set to 10 Gbps. | |
3197 | * When the link comes up The congestion management values are | |
3198 | * re-calculated according to the actual link rate. | |
3199 | */ | |
523224a3 DK |
3200 | bp->link_vars.line_speed = SPEED_10000; |
3201 | bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); | |
3202 | ||
3203 | /* Only the PMF sets the HW */ | |
3204 | if (bp->port.pmf) | |
3205 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3206 | ||
86564c3f | 3207 | /* init Event Queue - PCI bus guarantees correct endianity*/ |
523224a3 DK |
3208 | eq_data.base_addr.hi = U64_HI(bp->eq_mapping); |
3209 | eq_data.base_addr.lo = U64_LO(bp->eq_mapping); | |
3210 | eq_data.producer = bp->eq_prod; | |
3211 | eq_data.index_id = HC_SP_INDEX_EQ_CONS; | |
3212 | eq_data.sb_id = DEF_SB_ID; | |
3213 | storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); | |
3214 | } | |
3215 | ||
523224a3 DK |
3216 | static void bnx2x_e1h_disable(struct bnx2x *bp) |
3217 | { | |
3218 | int port = BP_PORT(bp); | |
3219 | ||
619c5cb6 | 3220 | bnx2x_tx_disable(bp); |
523224a3 DK |
3221 | |
3222 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
523224a3 DK |
3223 | } |
3224 | ||
3225 | static void bnx2x_e1h_enable(struct bnx2x *bp) | |
3226 | { | |
3227 | int port = BP_PORT(bp); | |
3228 | ||
3229 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); | |
3230 | ||
16a5fd92 | 3231 | /* Tx queue should be only re-enabled */ |
523224a3 DK |
3232 | netif_tx_wake_all_queues(bp->dev); |
3233 | ||
3234 | /* | |
3235 | * Should not call netif_carrier_on since it will be called if the link | |
3236 | * is up when checking for link state | |
3237 | */ | |
3238 | } | |
3239 | ||
1d187b34 BW |
3240 | #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 |
3241 | ||
3242 | static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) | |
3243 | { | |
3244 | struct eth_stats_info *ether_stat = | |
3245 | &bp->slowpath->drv_info_to_mcp.ether_stat; | |
3ec9f9ca AE |
3246 | struct bnx2x_vlan_mac_obj *mac_obj = |
3247 | &bp->sp_objs->mac_obj; | |
3248 | int i; | |
1d187b34 | 3249 | |
786fdf0b DC |
3250 | strlcpy(ether_stat->version, DRV_MODULE_VERSION, |
3251 | ETH_STAT_INFO_VERSION_LEN); | |
1d187b34 | 3252 | |
3ec9f9ca AE |
3253 | /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the |
3254 | * mac_local field in ether_stat struct. The base address is offset by 2 | |
3255 | * bytes to account for the field being 8 bytes but a mac address is | |
3256 | * only 6 bytes. Likewise, the stride for the get_n_elements function is | |
3257 | * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes | |
3258 | * allocated by the ether_stat struct, so the macs will land in their | |
3259 | * proper positions. | |
3260 | */ | |
3261 | for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) | |
3262 | memset(ether_stat->mac_local + i, 0, | |
3263 | sizeof(ether_stat->mac_local[0])); | |
3264 | mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, | |
3265 | DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, | |
3266 | ether_stat->mac_local + MAC_PAD, MAC_PAD, | |
3267 | ETH_ALEN); | |
1d187b34 | 3268 | ether_stat->mtu_size = bp->dev->mtu; |
1d187b34 BW |
3269 | if (bp->dev->features & NETIF_F_RXCSUM) |
3270 | ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; | |
3271 | if (bp->dev->features & NETIF_F_TSO) | |
3272 | ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; | |
3273 | ether_stat->feature_flags |= bp->common.boot_mode; | |
3274 | ||
3275 | ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; | |
3276 | ||
3277 | ether_stat->txq_size = bp->tx_ring_size; | |
3278 | ether_stat->rxq_size = bp->rx_ring_size; | |
3279 | } | |
3280 | ||
3281 | static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) | |
3282 | { | |
3283 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3284 | struct fcoe_stats_info *fcoe_stat = | |
3285 | &bp->slowpath->drv_info_to_mcp.fcoe_stat; | |
3286 | ||
55c11941 MS |
3287 | if (!CNIC_LOADED(bp)) |
3288 | return; | |
3289 | ||
3ec9f9ca | 3290 | memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); |
1d187b34 BW |
3291 | |
3292 | fcoe_stat->qos_priority = | |
3293 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; | |
3294 | ||
3295 | /* insert FCoE stats from ramrod response */ | |
3296 | if (!NO_FCOE(bp)) { | |
3297 | struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = | |
65565884 | 3298 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3299 | tstorm_queue_statistics; |
3300 | ||
3301 | struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = | |
65565884 | 3302 | &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. |
1d187b34 BW |
3303 | xstorm_queue_statistics; |
3304 | ||
3305 | struct fcoe_statistics_params *fw_fcoe_stat = | |
3306 | &bp->fw_stats_data->fcoe; | |
3307 | ||
86564c3f YM |
3308 | ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, |
3309 | fcoe_stat->rx_bytes_lo, | |
3310 | fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); | |
1d187b34 | 3311 | |
86564c3f YM |
3312 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3313 | fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, | |
3314 | fcoe_stat->rx_bytes_lo, | |
3315 | fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); | |
1d187b34 | 3316 | |
86564c3f YM |
3317 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3318 | fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, | |
3319 | fcoe_stat->rx_bytes_lo, | |
3320 | fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); | |
1d187b34 | 3321 | |
86564c3f YM |
3322 | ADD_64_LE(fcoe_stat->rx_bytes_hi, |
3323 | fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, | |
3324 | fcoe_stat->rx_bytes_lo, | |
3325 | fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); | |
1d187b34 | 3326 | |
86564c3f YM |
3327 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3328 | fcoe_stat->rx_frames_lo, | |
3329 | fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); | |
1d187b34 | 3330 | |
86564c3f YM |
3331 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3332 | fcoe_stat->rx_frames_lo, | |
3333 | fcoe_q_tstorm_stats->rcv_ucast_pkts); | |
1d187b34 | 3334 | |
86564c3f YM |
3335 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3336 | fcoe_stat->rx_frames_lo, | |
3337 | fcoe_q_tstorm_stats->rcv_bcast_pkts); | |
1d187b34 | 3338 | |
86564c3f YM |
3339 | ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, |
3340 | fcoe_stat->rx_frames_lo, | |
3341 | fcoe_q_tstorm_stats->rcv_mcast_pkts); | |
1d187b34 | 3342 | |
86564c3f YM |
3343 | ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, |
3344 | fcoe_stat->tx_bytes_lo, | |
3345 | fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); | |
1d187b34 | 3346 | |
86564c3f YM |
3347 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3348 | fcoe_q_xstorm_stats->ucast_bytes_sent.hi, | |
3349 | fcoe_stat->tx_bytes_lo, | |
3350 | fcoe_q_xstorm_stats->ucast_bytes_sent.lo); | |
1d187b34 | 3351 | |
86564c3f YM |
3352 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3353 | fcoe_q_xstorm_stats->bcast_bytes_sent.hi, | |
3354 | fcoe_stat->tx_bytes_lo, | |
3355 | fcoe_q_xstorm_stats->bcast_bytes_sent.lo); | |
1d187b34 | 3356 | |
86564c3f YM |
3357 | ADD_64_LE(fcoe_stat->tx_bytes_hi, |
3358 | fcoe_q_xstorm_stats->mcast_bytes_sent.hi, | |
3359 | fcoe_stat->tx_bytes_lo, | |
3360 | fcoe_q_xstorm_stats->mcast_bytes_sent.lo); | |
1d187b34 | 3361 | |
86564c3f YM |
3362 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3363 | fcoe_stat->tx_frames_lo, | |
3364 | fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); | |
1d187b34 | 3365 | |
86564c3f YM |
3366 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3367 | fcoe_stat->tx_frames_lo, | |
3368 | fcoe_q_xstorm_stats->ucast_pkts_sent); | |
1d187b34 | 3369 | |
86564c3f YM |
3370 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3371 | fcoe_stat->tx_frames_lo, | |
3372 | fcoe_q_xstorm_stats->bcast_pkts_sent); | |
1d187b34 | 3373 | |
86564c3f YM |
3374 | ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, |
3375 | fcoe_stat->tx_frames_lo, | |
3376 | fcoe_q_xstorm_stats->mcast_pkts_sent); | |
1d187b34 BW |
3377 | } |
3378 | ||
1d187b34 BW |
3379 | /* ask L5 driver to add data to the struct */ |
3380 | bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); | |
1d187b34 BW |
3381 | } |
3382 | ||
3383 | static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) | |
3384 | { | |
3385 | struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; | |
3386 | struct iscsi_stats_info *iscsi_stat = | |
3387 | &bp->slowpath->drv_info_to_mcp.iscsi_stat; | |
3388 | ||
55c11941 MS |
3389 | if (!CNIC_LOADED(bp)) |
3390 | return; | |
3391 | ||
3ec9f9ca AE |
3392 | memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, |
3393 | ETH_ALEN); | |
1d187b34 BW |
3394 | |
3395 | iscsi_stat->qos_priority = | |
3396 | app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; | |
3397 | ||
1d187b34 BW |
3398 | /* ask L5 driver to add data to the struct */ |
3399 | bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); | |
1d187b34 BW |
3400 | } |
3401 | ||
0793f83f DK |
3402 | /* called due to MCP event (on pmf): |
3403 | * reread new bandwidth configuration | |
3404 | * configure FW | |
3405 | * notify others function about the change | |
3406 | */ | |
1191cb83 | 3407 | static void bnx2x_config_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3408 | { |
3409 | if (bp->link_vars.link_up) { | |
3410 | bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); | |
3411 | bnx2x_link_sync_notify(bp); | |
3412 | } | |
3413 | storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); | |
3414 | } | |
3415 | ||
1191cb83 | 3416 | static void bnx2x_set_mf_bw(struct bnx2x *bp) |
0793f83f DK |
3417 | { |
3418 | bnx2x_config_mf_bw(bp); | |
3419 | bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); | |
3420 | } | |
3421 | ||
c8c60d88 YM |
3422 | static void bnx2x_handle_eee_event(struct bnx2x *bp) |
3423 | { | |
3424 | DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); | |
3425 | bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); | |
3426 | } | |
3427 | ||
1d187b34 BW |
3428 | static void bnx2x_handle_drv_info_req(struct bnx2x *bp) |
3429 | { | |
3430 | enum drv_info_opcode op_code; | |
3431 | u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); | |
3432 | ||
3433 | /* if drv_info version supported by MFW doesn't match - send NACK */ | |
3434 | if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { | |
3435 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3436 | return; | |
3437 | } | |
3438 | ||
3439 | op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> | |
3440 | DRV_INFO_CONTROL_OP_CODE_SHIFT; | |
3441 | ||
3442 | memset(&bp->slowpath->drv_info_to_mcp, 0, | |
3443 | sizeof(union drv_info_to_mcp)); | |
3444 | ||
3445 | switch (op_code) { | |
3446 | case ETH_STATS_OPCODE: | |
3447 | bnx2x_drv_info_ether_stat(bp); | |
3448 | break; | |
3449 | case FCOE_STATS_OPCODE: | |
3450 | bnx2x_drv_info_fcoe_stat(bp); | |
3451 | break; | |
3452 | case ISCSI_STATS_OPCODE: | |
3453 | bnx2x_drv_info_iscsi_stat(bp); | |
3454 | break; | |
3455 | default: | |
3456 | /* if op code isn't supported - send NACK */ | |
3457 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); | |
3458 | return; | |
3459 | } | |
3460 | ||
3461 | /* if we got drv_info attn from MFW then these fields are defined in | |
3462 | * shmem2 for sure | |
3463 | */ | |
3464 | SHMEM2_WR(bp, drv_info_host_addr_lo, | |
3465 | U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3466 | SHMEM2_WR(bp, drv_info_host_addr_hi, | |
3467 | U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); | |
3468 | ||
3469 | bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); | |
3470 | } | |
3471 | ||
523224a3 DK |
3472 | static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) |
3473 | { | |
3474 | DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event); | |
3475 | ||
3476 | if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { | |
3477 | ||
3478 | /* | |
3479 | * This is the only place besides the function initialization | |
3480 | * where the bp->flags can change so it is done without any | |
3481 | * locks | |
3482 | */ | |
f2e0899f | 3483 | if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { |
51c1a580 | 3484 | DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); |
523224a3 DK |
3485 | bp->flags |= MF_FUNC_DIS; |
3486 | ||
3487 | bnx2x_e1h_disable(bp); | |
3488 | } else { | |
51c1a580 | 3489 | DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); |
523224a3 DK |
3490 | bp->flags &= ~MF_FUNC_DIS; |
3491 | ||
3492 | bnx2x_e1h_enable(bp); | |
3493 | } | |
3494 | dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; | |
3495 | } | |
3496 | if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { | |
0793f83f | 3497 | bnx2x_config_mf_bw(bp); |
523224a3 DK |
3498 | dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; |
3499 | } | |
3500 | ||
3501 | /* Report results to MCP */ | |
3502 | if (dcc_event) | |
3503 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0); | |
3504 | else | |
3505 | bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0); | |
3506 | } | |
3507 | ||
3508 | /* must be called under the spq lock */ | |
1191cb83 | 3509 | static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) |
523224a3 DK |
3510 | { |
3511 | struct eth_spe *next_spe = bp->spq_prod_bd; | |
3512 | ||
3513 | if (bp->spq_prod_bd == bp->spq_last_bd) { | |
3514 | bp->spq_prod_bd = bp->spq; | |
3515 | bp->spq_prod_idx = 0; | |
51c1a580 | 3516 | DP(BNX2X_MSG_SP, "end of spq\n"); |
523224a3 DK |
3517 | } else { |
3518 | bp->spq_prod_bd++; | |
3519 | bp->spq_prod_idx++; | |
3520 | } | |
3521 | return next_spe; | |
3522 | } | |
3523 | ||
3524 | /* must be called under the spq lock */ | |
1191cb83 | 3525 | static void bnx2x_sp_prod_update(struct bnx2x *bp) |
28912902 MC |
3526 | { |
3527 | int func = BP_FUNC(bp); | |
3528 | ||
53e51e2f VZ |
3529 | /* |
3530 | * Make sure that BD data is updated before writing the producer: | |
3531 | * BD data is written to the memory, the producer is read from the | |
3532 | * memory, thus we need a full memory barrier to ensure the ordering. | |
3533 | */ | |
3534 | mb(); | |
28912902 | 3535 | |
523224a3 | 3536 | REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), |
f85582f8 | 3537 | bp->spq_prod_idx); |
28912902 MC |
3538 | mmiowb(); |
3539 | } | |
3540 | ||
619c5cb6 VZ |
3541 | /** |
3542 | * bnx2x_is_contextless_ramrod - check if the current command ends on EQ | |
3543 | * | |
3544 | * @cmd: command to check | |
3545 | * @cmd_type: command type | |
3546 | */ | |
1191cb83 | 3547 | static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) |
619c5cb6 VZ |
3548 | { |
3549 | if ((cmd_type == NONE_CONNECTION_TYPE) || | |
6383c0b3 | 3550 | (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || |
619c5cb6 VZ |
3551 | (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || |
3552 | (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || | |
3553 | (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || | |
3554 | (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || | |
3555 | (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) | |
3556 | return true; | |
3557 | else | |
3558 | return false; | |
619c5cb6 VZ |
3559 | } |
3560 | ||
619c5cb6 VZ |
3561 | /** |
3562 | * bnx2x_sp_post - place a single command on an SP ring | |
3563 | * | |
3564 | * @bp: driver handle | |
3565 | * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) | |
3566 | * @cid: SW CID the command is related to | |
3567 | * @data_hi: command private data address (high 32 bits) | |
3568 | * @data_lo: command private data address (low 32 bits) | |
3569 | * @cmd_type: command type (e.g. NONE, ETH) | |
3570 | * | |
3571 | * SP data is handled as if it's always an address pair, thus data fields are | |
3572 | * not swapped to little endian in upper functions. Instead this function swaps | |
3573 | * data as if it's two u32 fields. | |
3574 | */ | |
9f6c9258 | 3575 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, |
619c5cb6 | 3576 | u32 data_hi, u32 data_lo, int cmd_type) |
a2fbb9ea | 3577 | { |
28912902 | 3578 | struct eth_spe *spe; |
523224a3 | 3579 | u16 type; |
619c5cb6 | 3580 | bool common = bnx2x_is_contextless_ramrod(command, cmd_type); |
a2fbb9ea | 3581 | |
a2fbb9ea | 3582 | #ifdef BNX2X_STOP_ON_ERROR |
51c1a580 MS |
3583 | if (unlikely(bp->panic)) { |
3584 | BNX2X_ERR("Can't post SP when there is panic\n"); | |
a2fbb9ea | 3585 | return -EIO; |
51c1a580 | 3586 | } |
a2fbb9ea ET |
3587 | #endif |
3588 | ||
34f80b04 | 3589 | spin_lock_bh(&bp->spq_lock); |
a2fbb9ea | 3590 | |
6e30dd4e VZ |
3591 | if (common) { |
3592 | if (!atomic_read(&bp->eq_spq_left)) { | |
3593 | BNX2X_ERR("BUG! EQ ring full!\n"); | |
3594 | spin_unlock_bh(&bp->spq_lock); | |
3595 | bnx2x_panic(); | |
3596 | return -EBUSY; | |
3597 | } | |
3598 | } else if (!atomic_read(&bp->cq_spq_left)) { | |
3599 | BNX2X_ERR("BUG! SPQ ring full!\n"); | |
3600 | spin_unlock_bh(&bp->spq_lock); | |
3601 | bnx2x_panic(); | |
3602 | return -EBUSY; | |
a2fbb9ea | 3603 | } |
f1410647 | 3604 | |
28912902 MC |
3605 | spe = bnx2x_sp_get_next(bp); |
3606 | ||
a2fbb9ea | 3607 | /* CID needs port number to be encoded int it */ |
28912902 | 3608 | spe->hdr.conn_and_cmd_data = |
cdaa7cb8 VZ |
3609 | cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | |
3610 | HW_CID(bp, cid)); | |
523224a3 | 3611 | |
619c5cb6 | 3612 | type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; |
a2fbb9ea | 3613 | |
523224a3 DK |
3614 | type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & |
3615 | SPE_HDR_FUNCTION_ID); | |
a2fbb9ea | 3616 | |
523224a3 DK |
3617 | spe->hdr.type = cpu_to_le16(type); |
3618 | ||
3619 | spe->data.update_data_addr.hi = cpu_to_le32(data_hi); | |
3620 | spe->data.update_data_addr.lo = cpu_to_le32(data_lo); | |
3621 | ||
d6cae238 VZ |
3622 | /* |
3623 | * It's ok if the actual decrement is issued towards the memory | |
3624 | * somewhere between the spin_lock and spin_unlock. Thus no | |
16a5fd92 | 3625 | * more explicit memory barrier is needed. |
d6cae238 VZ |
3626 | */ |
3627 | if (common) | |
3628 | atomic_dec(&bp->eq_spq_left); | |
3629 | else | |
3630 | atomic_dec(&bp->cq_spq_left); | |
6e30dd4e | 3631 | |
51c1a580 MS |
3632 | DP(BNX2X_MSG_SP, |
3633 | "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", | |
cdaa7cb8 VZ |
3634 | bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), |
3635 | (u32)(U64_LO(bp->spq_mapping) + | |
d6cae238 | 3636 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, |
6e30dd4e VZ |
3637 | HW_CID(bp, cid), data_hi, data_lo, type, |
3638 | atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); | |
cdaa7cb8 | 3639 | |
28912902 | 3640 | bnx2x_sp_prod_update(bp); |
34f80b04 | 3641 | spin_unlock_bh(&bp->spq_lock); |
a2fbb9ea ET |
3642 | return 0; |
3643 | } | |
3644 | ||
3645 | /* acquire split MCP access lock register */ | |
4a37fb66 | 3646 | static int bnx2x_acquire_alr(struct bnx2x *bp) |
a2fbb9ea | 3647 | { |
72fd0718 | 3648 | u32 j, val; |
34f80b04 | 3649 | int rc = 0; |
a2fbb9ea ET |
3650 | |
3651 | might_sleep(); | |
72fd0718 | 3652 | for (j = 0; j < 1000; j++) { |
3cdeec22 YM |
3653 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); |
3654 | val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); | |
3655 | if (val & MCPR_ACCESS_LOCK_LOCK) | |
a2fbb9ea ET |
3656 | break; |
3657 | ||
639d65b8 | 3658 | usleep_range(5000, 10000); |
a2fbb9ea | 3659 | } |
3cdeec22 | 3660 | if (!(val & MCPR_ACCESS_LOCK_LOCK)) { |
19680c48 | 3661 | BNX2X_ERR("Cannot acquire MCP access lock register\n"); |
a2fbb9ea ET |
3662 | rc = -EBUSY; |
3663 | } | |
3664 | ||
3665 | return rc; | |
3666 | } | |
3667 | ||
4a37fb66 YG |
3668 | /* release split MCP access lock register */ |
3669 | static void bnx2x_release_alr(struct bnx2x *bp) | |
a2fbb9ea | 3670 | { |
3cdeec22 | 3671 | REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); |
a2fbb9ea ET |
3672 | } |
3673 | ||
523224a3 DK |
3674 | #define BNX2X_DEF_SB_ATT_IDX 0x0001 |
3675 | #define BNX2X_DEF_SB_IDX 0x0002 | |
3676 | ||
1191cb83 | 3677 | static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) |
a2fbb9ea | 3678 | { |
523224a3 | 3679 | struct host_sp_status_block *def_sb = bp->def_status_blk; |
a2fbb9ea ET |
3680 | u16 rc = 0; |
3681 | ||
3682 | barrier(); /* status block is written to by the chip */ | |
a2fbb9ea ET |
3683 | if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { |
3684 | bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; | |
523224a3 | 3685 | rc |= BNX2X_DEF_SB_ATT_IDX; |
a2fbb9ea | 3686 | } |
523224a3 DK |
3687 | |
3688 | if (bp->def_idx != def_sb->sp_sb.running_index) { | |
3689 | bp->def_idx = def_sb->sp_sb.running_index; | |
3690 | rc |= BNX2X_DEF_SB_IDX; | |
a2fbb9ea | 3691 | } |
523224a3 | 3692 | |
16a5fd92 | 3693 | /* Do not reorder: indices reading should complete before handling */ |
523224a3 | 3694 | barrier(); |
a2fbb9ea ET |
3695 | return rc; |
3696 | } | |
3697 | ||
3698 | /* | |
3699 | * slow path service functions | |
3700 | */ | |
3701 | ||
3702 | static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |
3703 | { | |
34f80b04 | 3704 | int port = BP_PORT(bp); |
a2fbb9ea ET |
3705 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3706 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
877e9aa4 ET |
3707 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3708 | NIG_REG_MASK_INTERRUPT_PORT0; | |
3fcaf2e5 | 3709 | u32 aeu_mask; |
87942b46 | 3710 | u32 nig_mask = 0; |
f2e0899f | 3711 | u32 reg_addr; |
a2fbb9ea | 3712 | |
a2fbb9ea ET |
3713 | if (bp->attn_state & asserted) |
3714 | BNX2X_ERR("IGU ERROR\n"); | |
3715 | ||
3fcaf2e5 EG |
3716 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
3717 | aeu_mask = REG_RD(bp, aeu_addr); | |
3718 | ||
a2fbb9ea | 3719 | DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", |
3fcaf2e5 | 3720 | aeu_mask, asserted); |
72fd0718 | 3721 | aeu_mask &= ~(asserted & 0x3ff); |
3fcaf2e5 | 3722 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 3723 | |
3fcaf2e5 EG |
3724 | REG_WR(bp, aeu_addr, aeu_mask); |
3725 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea | 3726 | |
3fcaf2e5 | 3727 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); |
a2fbb9ea | 3728 | bp->attn_state |= asserted; |
3fcaf2e5 | 3729 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); |
a2fbb9ea ET |
3730 | |
3731 | if (asserted & ATTN_HARD_WIRED_MASK) { | |
3732 | if (asserted & ATTN_NIG_FOR_FUNC) { | |
a2fbb9ea | 3733 | |
a5e9a7cf EG |
3734 | bnx2x_acquire_phy_lock(bp); |
3735 | ||
877e9aa4 | 3736 | /* save nig interrupt mask */ |
87942b46 | 3737 | nig_mask = REG_RD(bp, nig_int_mask_addr); |
a2fbb9ea | 3738 | |
361c391e YR |
3739 | /* If nig_mask is not set, no need to call the update |
3740 | * function. | |
3741 | */ | |
3742 | if (nig_mask) { | |
3743 | REG_WR(bp, nig_int_mask_addr, 0); | |
3744 | ||
3745 | bnx2x_link_attn(bp); | |
3746 | } | |
a2fbb9ea ET |
3747 | |
3748 | /* handle unicore attn? */ | |
3749 | } | |
3750 | if (asserted & ATTN_SW_TIMER_4_FUNC) | |
3751 | DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); | |
3752 | ||
3753 | if (asserted & GPIO_2_FUNC) | |
3754 | DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); | |
3755 | ||
3756 | if (asserted & GPIO_3_FUNC) | |
3757 | DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); | |
3758 | ||
3759 | if (asserted & GPIO_4_FUNC) | |
3760 | DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); | |
3761 | ||
3762 | if (port == 0) { | |
3763 | if (asserted & ATTN_GENERAL_ATTN_1) { | |
3764 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); | |
3765 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); | |
3766 | } | |
3767 | if (asserted & ATTN_GENERAL_ATTN_2) { | |
3768 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); | |
3769 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); | |
3770 | } | |
3771 | if (asserted & ATTN_GENERAL_ATTN_3) { | |
3772 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); | |
3773 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); | |
3774 | } | |
3775 | } else { | |
3776 | if (asserted & ATTN_GENERAL_ATTN_4) { | |
3777 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); | |
3778 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); | |
3779 | } | |
3780 | if (asserted & ATTN_GENERAL_ATTN_5) { | |
3781 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); | |
3782 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); | |
3783 | } | |
3784 | if (asserted & ATTN_GENERAL_ATTN_6) { | |
3785 | DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); | |
3786 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); | |
3787 | } | |
3788 | } | |
3789 | ||
3790 | } /* if hardwired */ | |
3791 | ||
f2e0899f DK |
3792 | if (bp->common.int_block == INT_BLOCK_HC) |
3793 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
3794 | COMMAND_REG_ATTN_BITS_SET); | |
3795 | else | |
3796 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); | |
3797 | ||
3798 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, | |
3799 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
3800 | REG_WR(bp, reg_addr, asserted); | |
a2fbb9ea ET |
3801 | |
3802 | /* now set back the mask */ | |
a5e9a7cf | 3803 | if (asserted & ATTN_NIG_FOR_FUNC) { |
27c1151c YR |
3804 | /* Verify that IGU ack through BAR was written before restoring |
3805 | * NIG mask. This loop should exit after 2-3 iterations max. | |
3806 | */ | |
3807 | if (bp->common.int_block != INT_BLOCK_HC) { | |
3808 | u32 cnt = 0, igu_acked; | |
3809 | do { | |
3810 | igu_acked = REG_RD(bp, | |
3811 | IGU_REG_ATTENTION_ACK_BITS); | |
3812 | } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && | |
3813 | (++cnt < MAX_IGU_ATTN_ACK_TO)); | |
3814 | if (!igu_acked) | |
3815 | DP(NETIF_MSG_HW, | |
3816 | "Failed to verify IGU ack on time\n"); | |
3817 | barrier(); | |
3818 | } | |
87942b46 | 3819 | REG_WR(bp, nig_int_mask_addr, nig_mask); |
a5e9a7cf EG |
3820 | bnx2x_release_phy_lock(bp); |
3821 | } | |
a2fbb9ea ET |
3822 | } |
3823 | ||
1191cb83 | 3824 | static void bnx2x_fan_failure(struct bnx2x *bp) |
fd4ef40d EG |
3825 | { |
3826 | int port = BP_PORT(bp); | |
b7737c9b | 3827 | u32 ext_phy_config; |
fd4ef40d | 3828 | /* mark the failure */ |
b7737c9b YR |
3829 | ext_phy_config = |
3830 | SHMEM_RD(bp, | |
3831 | dev_info.port_hw_config[port].external_phy_config); | |
3832 | ||
3833 | ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | |
3834 | ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | |
fd4ef40d | 3835 | SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, |
b7737c9b | 3836 | ext_phy_config); |
fd4ef40d EG |
3837 | |
3838 | /* log the failure */ | |
51c1a580 MS |
3839 | netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" |
3840 | "Please contact OEM Support for assistance\n"); | |
8304859a | 3841 | |
16a5fd92 | 3842 | /* Schedule device reset (unload) |
8304859a AE |
3843 | * This is due to some boards consuming sufficient power when driver is |
3844 | * up to overheat if fan fails. | |
3845 | */ | |
3846 | smp_mb__before_clear_bit(); | |
3847 | set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state); | |
3848 | smp_mb__after_clear_bit(); | |
3849 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
fd4ef40d | 3850 | } |
ab6ad5a4 | 3851 | |
1191cb83 | 3852 | static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
a2fbb9ea | 3853 | { |
34f80b04 | 3854 | int port = BP_PORT(bp); |
877e9aa4 | 3855 | int reg_offset; |
d90d96ba | 3856 | u32 val; |
877e9aa4 | 3857 | |
34f80b04 EG |
3858 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
3859 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
877e9aa4 | 3860 | |
34f80b04 | 3861 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { |
877e9aa4 ET |
3862 | |
3863 | val = REG_RD(bp, reg_offset); | |
3864 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | |
3865 | REG_WR(bp, reg_offset, val); | |
3866 | ||
3867 | BNX2X_ERR("SPIO5 hw attention\n"); | |
3868 | ||
fd4ef40d | 3869 | /* Fan failure attention */ |
d90d96ba | 3870 | bnx2x_hw_reset_phy(&bp->link_params); |
fd4ef40d | 3871 | bnx2x_fan_failure(bp); |
877e9aa4 | 3872 | } |
34f80b04 | 3873 | |
3deb8167 | 3874 | if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { |
589abe3a EG |
3875 | bnx2x_acquire_phy_lock(bp); |
3876 | bnx2x_handle_module_detect_int(&bp->link_params); | |
3877 | bnx2x_release_phy_lock(bp); | |
3878 | } | |
3879 | ||
34f80b04 EG |
3880 | if (attn & HW_INTERRUT_ASSERT_SET_0) { |
3881 | ||
3882 | val = REG_RD(bp, reg_offset); | |
3883 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); | |
3884 | REG_WR(bp, reg_offset, val); | |
3885 | ||
3886 | BNX2X_ERR("FATAL HW block attention set0 0x%x\n", | |
0fc5d009 | 3887 | (u32)(attn & HW_INTERRUT_ASSERT_SET_0)); |
34f80b04 EG |
3888 | bnx2x_panic(); |
3889 | } | |
877e9aa4 ET |
3890 | } |
3891 | ||
1191cb83 | 3892 | static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3893 | { |
3894 | u32 val; | |
3895 | ||
0626b899 | 3896 | if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { |
877e9aa4 ET |
3897 | |
3898 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | |
3899 | BNX2X_ERR("DB hw attention 0x%x\n", val); | |
3900 | /* DORQ discard attention */ | |
3901 | if (val & 0x2) | |
3902 | BNX2X_ERR("FATAL error from DORQ\n"); | |
3903 | } | |
34f80b04 EG |
3904 | |
3905 | if (attn & HW_INTERRUT_ASSERT_SET_1) { | |
3906 | ||
3907 | int port = BP_PORT(bp); | |
3908 | int reg_offset; | |
3909 | ||
3910 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : | |
3911 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); | |
3912 | ||
3913 | val = REG_RD(bp, reg_offset); | |
3914 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); | |
3915 | REG_WR(bp, reg_offset, val); | |
3916 | ||
3917 | BNX2X_ERR("FATAL HW block attention set1 0x%x\n", | |
0fc5d009 | 3918 | (u32)(attn & HW_INTERRUT_ASSERT_SET_1)); |
34f80b04 EG |
3919 | bnx2x_panic(); |
3920 | } | |
877e9aa4 ET |
3921 | } |
3922 | ||
1191cb83 | 3923 | static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) |
877e9aa4 ET |
3924 | { |
3925 | u32 val; | |
3926 | ||
3927 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | |
3928 | ||
3929 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | |
3930 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | |
3931 | /* CFC error attention */ | |
3932 | if (val & 0x2) | |
3933 | BNX2X_ERR("FATAL error from CFC\n"); | |
3934 | } | |
3935 | ||
3936 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | |
877e9aa4 | 3937 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); |
619c5cb6 | 3938 | BNX2X_ERR("PXP hw attention-0 0x%x\n", val); |
877e9aa4 ET |
3939 | /* RQ_USDMDP_FIFO_OVERFLOW */ |
3940 | if (val & 0x18000) | |
3941 | BNX2X_ERR("FATAL error from PXP\n"); | |
619c5cb6 VZ |
3942 | |
3943 | if (!CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
3944 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); |
3945 | BNX2X_ERR("PXP hw attention-1 0x%x\n", val); | |
3946 | } | |
877e9aa4 | 3947 | } |
34f80b04 EG |
3948 | |
3949 | if (attn & HW_INTERRUT_ASSERT_SET_2) { | |
3950 | ||
3951 | int port = BP_PORT(bp); | |
3952 | int reg_offset; | |
3953 | ||
3954 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : | |
3955 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); | |
3956 | ||
3957 | val = REG_RD(bp, reg_offset); | |
3958 | val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); | |
3959 | REG_WR(bp, reg_offset, val); | |
3960 | ||
3961 | BNX2X_ERR("FATAL HW block attention set2 0x%x\n", | |
0fc5d009 | 3962 | (u32)(attn & HW_INTERRUT_ASSERT_SET_2)); |
34f80b04 EG |
3963 | bnx2x_panic(); |
3964 | } | |
877e9aa4 ET |
3965 | } |
3966 | ||
1191cb83 | 3967 | static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) |
877e9aa4 | 3968 | { |
34f80b04 EG |
3969 | u32 val; |
3970 | ||
877e9aa4 ET |
3971 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { |
3972 | ||
34f80b04 EG |
3973 | if (attn & BNX2X_PMF_LINK_ASSERT) { |
3974 | int func = BP_FUNC(bp); | |
3975 | ||
3976 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
a3348722 | 3977 | bnx2x_read_mf_cfg(bp); |
f2e0899f DK |
3978 | bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, |
3979 | func_mf_config[BP_ABS_FUNC(bp)].config); | |
3980 | val = SHMEM_RD(bp, | |
3981 | func_mb[BP_FW_MB_IDX(bp)].drv_status); | |
2691d51d EG |
3982 | if (val & DRV_STATUS_DCC_EVENT_MASK) |
3983 | bnx2x_dcc_event(bp, | |
3984 | (val & DRV_STATUS_DCC_EVENT_MASK)); | |
0793f83f DK |
3985 | |
3986 | if (val & DRV_STATUS_SET_MF_BW) | |
3987 | bnx2x_set_mf_bw(bp); | |
3988 | ||
1d187b34 BW |
3989 | if (val & DRV_STATUS_DRV_INFO_REQ) |
3990 | bnx2x_handle_drv_info_req(bp); | |
d16132ce AE |
3991 | |
3992 | if (val & DRV_STATUS_VF_DISABLED) | |
3993 | bnx2x_vf_handle_flr_event(bp); | |
3994 | ||
2691d51d | 3995 | if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) |
34f80b04 EG |
3996 | bnx2x_pmf_update(bp); |
3997 | ||
e4901dde | 3998 | if (bp->port.pmf && |
785b9b1a SR |
3999 | (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && |
4000 | bp->dcbx_enabled > 0) | |
e4901dde VZ |
4001 | /* start dcbx state machine */ |
4002 | bnx2x_dcbx_set_params(bp, | |
4003 | BNX2X_DCBX_STATE_NEG_RECEIVED); | |
a3348722 BW |
4004 | if (val & DRV_STATUS_AFEX_EVENT_MASK) |
4005 | bnx2x_handle_afex_cmd(bp, | |
4006 | val & DRV_STATUS_AFEX_EVENT_MASK); | |
c8c60d88 YM |
4007 | if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) |
4008 | bnx2x_handle_eee_event(bp); | |
3deb8167 YR |
4009 | if (bp->link_vars.periodic_flags & |
4010 | PERIODIC_FLAGS_LINK_EVENT) { | |
4011 | /* sync with link */ | |
4012 | bnx2x_acquire_phy_lock(bp); | |
4013 | bp->link_vars.periodic_flags &= | |
4014 | ~PERIODIC_FLAGS_LINK_EVENT; | |
4015 | bnx2x_release_phy_lock(bp); | |
4016 | if (IS_MF(bp)) | |
4017 | bnx2x_link_sync_notify(bp); | |
4018 | bnx2x_link_report(bp); | |
4019 | } | |
4020 | /* Always call it here: bnx2x_link_report() will | |
4021 | * prevent the link indication duplication. | |
4022 | */ | |
4023 | bnx2x__link_status_update(bp); | |
34f80b04 | 4024 | } else if (attn & BNX2X_MC_ASSERT_BITS) { |
877e9aa4 ET |
4025 | |
4026 | BNX2X_ERR("MC assert!\n"); | |
d6cae238 | 4027 | bnx2x_mc_assert(bp); |
877e9aa4 ET |
4028 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); |
4029 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | |
4030 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | |
4031 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | |
4032 | bnx2x_panic(); | |
4033 | ||
4034 | } else if (attn & BNX2X_MCP_ASSERT) { | |
4035 | ||
4036 | BNX2X_ERR("MCP assert!\n"); | |
4037 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | |
34f80b04 | 4038 | bnx2x_fw_dump(bp); |
877e9aa4 ET |
4039 | |
4040 | } else | |
4041 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | |
4042 | } | |
4043 | ||
4044 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | |
34f80b04 EG |
4045 | BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); |
4046 | if (attn & BNX2X_GRC_TIMEOUT) { | |
f2e0899f DK |
4047 | val = CHIP_IS_E1(bp) ? 0 : |
4048 | REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); | |
34f80b04 EG |
4049 | BNX2X_ERR("GRC time-out 0x%08x\n", val); |
4050 | } | |
4051 | if (attn & BNX2X_GRC_RSV) { | |
f2e0899f DK |
4052 | val = CHIP_IS_E1(bp) ? 0 : |
4053 | REG_RD(bp, MISC_REG_GRC_RSV_ATTN); | |
34f80b04 EG |
4054 | BNX2X_ERR("GRC reserved 0x%08x\n", val); |
4055 | } | |
877e9aa4 | 4056 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); |
877e9aa4 ET |
4057 | } |
4058 | } | |
4059 | ||
c9ee9206 VZ |
4060 | /* |
4061 | * Bits map: | |
4062 | * 0-7 - Engine0 load counter. | |
4063 | * 8-15 - Engine1 load counter. | |
4064 | * 16 - Engine0 RESET_IN_PROGRESS bit. | |
4065 | * 17 - Engine1 RESET_IN_PROGRESS bit. | |
4066 | * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function | |
4067 | * on the engine | |
4068 | * 19 - Engine1 ONE_IS_LOADED. | |
4069 | * 20 - Chip reset flow bit. When set none-leader must wait for both engines | |
4070 | * leader to complete (check for both RESET_IN_PROGRESS bits and not for | |
4071 | * just the one belonging to its engine). | |
4072 | * | |
4073 | */ | |
4074 | #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 | |
4075 | ||
4076 | #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff | |
4077 | #define BNX2X_PATH0_LOAD_CNT_SHIFT 0 | |
4078 | #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 | |
4079 | #define BNX2X_PATH1_LOAD_CNT_SHIFT 8 | |
4080 | #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 | |
4081 | #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 | |
4082 | #define BNX2X_GLOBAL_RESET_BIT 0x00040000 | |
4083 | ||
4084 | /* | |
4085 | * Set the GLOBAL_RESET bit. | |
4086 | * | |
4087 | * Should be run under rtnl lock | |
4088 | */ | |
4089 | void bnx2x_set_reset_global(struct bnx2x *bp) | |
4090 | { | |
f16da43b AE |
4091 | u32 val; |
4092 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4093 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4094 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); |
f16da43b | 4095 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 VZ |
4096 | } |
4097 | ||
4098 | /* | |
4099 | * Clear the GLOBAL_RESET bit. | |
4100 | * | |
4101 | * Should be run under rtnl lock | |
4102 | */ | |
1191cb83 | 4103 | static void bnx2x_clear_reset_global(struct bnx2x *bp) |
c9ee9206 | 4104 | { |
f16da43b AE |
4105 | u32 val; |
4106 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
4107 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 | 4108 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); |
f16da43b | 4109 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
c9ee9206 | 4110 | } |
f85582f8 | 4111 | |
72fd0718 | 4112 | /* |
c9ee9206 VZ |
4113 | * Checks the GLOBAL_RESET bit. |
4114 | * | |
72fd0718 VZ |
4115 | * should be run under rtnl lock |
4116 | */ | |
1191cb83 | 4117 | static bool bnx2x_reset_is_global(struct bnx2x *bp) |
c9ee9206 | 4118 | { |
3cdeec22 | 4119 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4120 | |
4121 | DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); | |
4122 | return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; | |
4123 | } | |
4124 | ||
4125 | /* | |
4126 | * Clear RESET_IN_PROGRESS bit for the current engine. | |
4127 | * | |
4128 | * Should be run under rtnl lock | |
4129 | */ | |
1191cb83 | 4130 | static void bnx2x_set_reset_done(struct bnx2x *bp) |
72fd0718 | 4131 | { |
f16da43b | 4132 | u32 val; |
c9ee9206 VZ |
4133 | u32 bit = BP_PATH(bp) ? |
4134 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4135 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4136 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4137 | |
4138 | /* Clear the bit */ | |
4139 | val &= ~bit; | |
4140 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4141 | |
4142 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | |
72fd0718 VZ |
4143 | } |
4144 | ||
4145 | /* | |
c9ee9206 VZ |
4146 | * Set RESET_IN_PROGRESS for the current engine. |
4147 | * | |
72fd0718 VZ |
4148 | * should be run under rtnl lock |
4149 | */ | |
c9ee9206 | 4150 | void bnx2x_set_reset_in_progress(struct bnx2x *bp) |
72fd0718 | 4151 | { |
f16da43b | 4152 | u32 val; |
c9ee9206 VZ |
4153 | u32 bit = BP_PATH(bp) ? |
4154 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
f16da43b AE |
4155 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4156 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
c9ee9206 VZ |
4157 | |
4158 | /* Set the bit */ | |
4159 | val |= bit; | |
4160 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4161 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4162 | } |
4163 | ||
4164 | /* | |
c9ee9206 | 4165 | * Checks the RESET_IN_PROGRESS bit for the given engine. |
72fd0718 VZ |
4166 | * should be run under rtnl lock |
4167 | */ | |
c9ee9206 | 4168 | bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) |
72fd0718 | 4169 | { |
3cdeec22 | 4170 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); |
c9ee9206 VZ |
4171 | u32 bit = engine ? |
4172 | BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; | |
4173 | ||
4174 | /* return false if bit is set */ | |
4175 | return (val & bit) ? false : true; | |
72fd0718 VZ |
4176 | } |
4177 | ||
4178 | /* | |
889b9af3 | 4179 | * set pf load for the current pf. |
c9ee9206 | 4180 | * |
72fd0718 VZ |
4181 | * should be run under rtnl lock |
4182 | */ | |
889b9af3 | 4183 | void bnx2x_set_pf_load(struct bnx2x *bp) |
72fd0718 | 4184 | { |
f16da43b | 4185 | u32 val1, val; |
c9ee9206 VZ |
4186 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4187 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4188 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4189 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4190 | |
f16da43b AE |
4191 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4192 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4193 | ||
51c1a580 | 4194 | DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4195 | |
c9ee9206 VZ |
4196 | /* get the current counter value */ |
4197 | val1 = (val & mask) >> shift; | |
4198 | ||
889b9af3 AE |
4199 | /* set bit of that PF */ |
4200 | val1 |= (1 << bp->pf_num); | |
c9ee9206 VZ |
4201 | |
4202 | /* clear the old value */ | |
4203 | val &= ~mask; | |
4204 | ||
4205 | /* set the new one */ | |
4206 | val |= ((val1 << shift) & mask); | |
4207 | ||
4208 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b | 4209 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
72fd0718 VZ |
4210 | } |
4211 | ||
c9ee9206 | 4212 | /** |
889b9af3 | 4213 | * bnx2x_clear_pf_load - clear pf load mark |
c9ee9206 VZ |
4214 | * |
4215 | * @bp: driver handle | |
4216 | * | |
4217 | * Should be run under rtnl lock. | |
4218 | * Decrements the load counter for the current engine. Returns | |
889b9af3 | 4219 | * whether other functions are still loaded |
72fd0718 | 4220 | */ |
889b9af3 | 4221 | bool bnx2x_clear_pf_load(struct bnx2x *bp) |
72fd0718 | 4222 | { |
f16da43b | 4223 | u32 val1, val; |
c9ee9206 VZ |
4224 | u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : |
4225 | BNX2X_PATH0_LOAD_CNT_MASK; | |
4226 | u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4227 | BNX2X_PATH0_LOAD_CNT_SHIFT; | |
72fd0718 | 4228 | |
f16da43b AE |
4229 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4230 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
51c1a580 | 4231 | DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); |
72fd0718 | 4232 | |
c9ee9206 VZ |
4233 | /* get the current counter value */ |
4234 | val1 = (val & mask) >> shift; | |
4235 | ||
889b9af3 AE |
4236 | /* clear bit of that PF */ |
4237 | val1 &= ~(1 << bp->pf_num); | |
c9ee9206 VZ |
4238 | |
4239 | /* clear the old value */ | |
4240 | val &= ~mask; | |
4241 | ||
4242 | /* set the new one */ | |
4243 | val |= ((val1 << shift) & mask); | |
4244 | ||
4245 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); | |
f16da43b AE |
4246 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); |
4247 | return val1 != 0; | |
72fd0718 VZ |
4248 | } |
4249 | ||
4250 | /* | |
889b9af3 | 4251 | * Read the load status for the current engine. |
c9ee9206 | 4252 | * |
72fd0718 VZ |
4253 | * should be run under rtnl lock |
4254 | */ | |
1191cb83 | 4255 | static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) |
72fd0718 | 4256 | { |
c9ee9206 VZ |
4257 | u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : |
4258 | BNX2X_PATH0_LOAD_CNT_MASK); | |
4259 | u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : | |
4260 | BNX2X_PATH0_LOAD_CNT_SHIFT); | |
4261 | u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | |
4262 | ||
51c1a580 | 4263 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); |
c9ee9206 VZ |
4264 | |
4265 | val = (val & mask) >> shift; | |
4266 | ||
51c1a580 MS |
4267 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", |
4268 | engine, val); | |
c9ee9206 | 4269 | |
889b9af3 | 4270 | return val != 0; |
72fd0718 VZ |
4271 | } |
4272 | ||
6bf07b8e YM |
4273 | static void _print_parity(struct bnx2x *bp, u32 reg) |
4274 | { | |
4275 | pr_cont(" [0x%08x] ", REG_RD(bp, reg)); | |
4276 | } | |
4277 | ||
1191cb83 | 4278 | static void _print_next_block(int idx, const char *blk) |
72fd0718 | 4279 | { |
f1deab50 | 4280 | pr_cont("%s%s", idx ? ", " : "", blk); |
72fd0718 VZ |
4281 | } |
4282 | ||
6bf07b8e YM |
4283 | static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, |
4284 | int par_num, bool print) | |
72fd0718 VZ |
4285 | { |
4286 | int i = 0; | |
4287 | u32 cur_bit = 0; | |
4288 | for (i = 0; sig; i++) { | |
4289 | cur_bit = ((u32)0x1 << i); | |
4290 | if (sig & cur_bit) { | |
4291 | switch (cur_bit) { | |
4292 | case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: | |
6bf07b8e | 4293 | if (print) { |
c9ee9206 | 4294 | _print_next_block(par_num++, "BRB"); |
6bf07b8e YM |
4295 | _print_parity(bp, |
4296 | BRB1_REG_BRB1_PRTY_STS); | |
4297 | } | |
72fd0718 VZ |
4298 | break; |
4299 | case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: | |
6bf07b8e | 4300 | if (print) { |
c9ee9206 | 4301 | _print_next_block(par_num++, "PARSER"); |
6bf07b8e YM |
4302 | _print_parity(bp, PRS_REG_PRS_PRTY_STS); |
4303 | } | |
72fd0718 VZ |
4304 | break; |
4305 | case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: | |
6bf07b8e | 4306 | if (print) { |
c9ee9206 | 4307 | _print_next_block(par_num++, "TSDM"); |
6bf07b8e YM |
4308 | _print_parity(bp, |
4309 | TSDM_REG_TSDM_PRTY_STS); | |
4310 | } | |
72fd0718 VZ |
4311 | break; |
4312 | case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: | |
6bf07b8e | 4313 | if (print) { |
c9ee9206 VZ |
4314 | _print_next_block(par_num++, |
4315 | "SEARCHER"); | |
6bf07b8e YM |
4316 | _print_parity(bp, SRC_REG_SRC_PRTY_STS); |
4317 | } | |
c9ee9206 VZ |
4318 | break; |
4319 | case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: | |
6bf07b8e | 4320 | if (print) { |
c9ee9206 | 4321 | _print_next_block(par_num++, "TCM"); |
6bf07b8e YM |
4322 | _print_parity(bp, |
4323 | TCM_REG_TCM_PRTY_STS); | |
4324 | } | |
72fd0718 VZ |
4325 | break; |
4326 | case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: | |
6bf07b8e | 4327 | if (print) { |
c9ee9206 | 4328 | _print_next_block(par_num++, "TSEMI"); |
6bf07b8e YM |
4329 | _print_parity(bp, |
4330 | TSEM_REG_TSEM_PRTY_STS_0); | |
4331 | _print_parity(bp, | |
4332 | TSEM_REG_TSEM_PRTY_STS_1); | |
4333 | } | |
c9ee9206 VZ |
4334 | break; |
4335 | case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: | |
6bf07b8e | 4336 | if (print) { |
c9ee9206 | 4337 | _print_next_block(par_num++, "XPB"); |
6bf07b8e YM |
4338 | _print_parity(bp, GRCBASE_XPB + |
4339 | PB_REG_PB_PRTY_STS); | |
4340 | } | |
72fd0718 VZ |
4341 | break; |
4342 | } | |
4343 | ||
4344 | /* Clear the bit */ | |
4345 | sig &= ~cur_bit; | |
4346 | } | |
4347 | } | |
4348 | ||
4349 | return par_num; | |
4350 | } | |
4351 | ||
6bf07b8e YM |
4352 | static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, |
4353 | int par_num, bool *global, | |
4354 | bool print) | |
72fd0718 VZ |
4355 | { |
4356 | int i = 0; | |
4357 | u32 cur_bit = 0; | |
4358 | for (i = 0; sig; i++) { | |
4359 | cur_bit = ((u32)0x1 << i); | |
4360 | if (sig & cur_bit) { | |
4361 | switch (cur_bit) { | |
c9ee9206 | 4362 | case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: |
6bf07b8e | 4363 | if (print) { |
c9ee9206 | 4364 | _print_next_block(par_num++, "PBF"); |
6bf07b8e YM |
4365 | _print_parity(bp, PBF_REG_PBF_PRTY_STS); |
4366 | } | |
72fd0718 VZ |
4367 | break; |
4368 | case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: | |
6bf07b8e | 4369 | if (print) { |
c9ee9206 | 4370 | _print_next_block(par_num++, "QM"); |
6bf07b8e YM |
4371 | _print_parity(bp, QM_REG_QM_PRTY_STS); |
4372 | } | |
c9ee9206 VZ |
4373 | break; |
4374 | case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: | |
6bf07b8e | 4375 | if (print) { |
c9ee9206 | 4376 | _print_next_block(par_num++, "TM"); |
6bf07b8e YM |
4377 | _print_parity(bp, TM_REG_TM_PRTY_STS); |
4378 | } | |
72fd0718 VZ |
4379 | break; |
4380 | case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: | |
6bf07b8e | 4381 | if (print) { |
c9ee9206 | 4382 | _print_next_block(par_num++, "XSDM"); |
6bf07b8e YM |
4383 | _print_parity(bp, |
4384 | XSDM_REG_XSDM_PRTY_STS); | |
4385 | } | |
c9ee9206 VZ |
4386 | break; |
4387 | case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: | |
6bf07b8e | 4388 | if (print) { |
c9ee9206 | 4389 | _print_next_block(par_num++, "XCM"); |
6bf07b8e YM |
4390 | _print_parity(bp, XCM_REG_XCM_PRTY_STS); |
4391 | } | |
72fd0718 VZ |
4392 | break; |
4393 | case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: | |
6bf07b8e | 4394 | if (print) { |
c9ee9206 | 4395 | _print_next_block(par_num++, "XSEMI"); |
6bf07b8e YM |
4396 | _print_parity(bp, |
4397 | XSEM_REG_XSEM_PRTY_STS_0); | |
4398 | _print_parity(bp, | |
4399 | XSEM_REG_XSEM_PRTY_STS_1); | |
4400 | } | |
72fd0718 VZ |
4401 | break; |
4402 | case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: | |
6bf07b8e | 4403 | if (print) { |
c9ee9206 VZ |
4404 | _print_next_block(par_num++, |
4405 | "DOORBELLQ"); | |
6bf07b8e YM |
4406 | _print_parity(bp, |
4407 | DORQ_REG_DORQ_PRTY_STS); | |
4408 | } | |
c9ee9206 VZ |
4409 | break; |
4410 | case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: | |
6bf07b8e | 4411 | if (print) { |
c9ee9206 | 4412 | _print_next_block(par_num++, "NIG"); |
6bf07b8e YM |
4413 | if (CHIP_IS_E1x(bp)) { |
4414 | _print_parity(bp, | |
4415 | NIG_REG_NIG_PRTY_STS); | |
4416 | } else { | |
4417 | _print_parity(bp, | |
4418 | NIG_REG_NIG_PRTY_STS_0); | |
4419 | _print_parity(bp, | |
4420 | NIG_REG_NIG_PRTY_STS_1); | |
4421 | } | |
4422 | } | |
72fd0718 VZ |
4423 | break; |
4424 | case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: | |
c9ee9206 VZ |
4425 | if (print) |
4426 | _print_next_block(par_num++, | |
4427 | "VAUX PCI CORE"); | |
4428 | *global = true; | |
72fd0718 VZ |
4429 | break; |
4430 | case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: | |
6bf07b8e | 4431 | if (print) { |
c9ee9206 | 4432 | _print_next_block(par_num++, "DEBUG"); |
6bf07b8e YM |
4433 | _print_parity(bp, DBG_REG_DBG_PRTY_STS); |
4434 | } | |
72fd0718 VZ |
4435 | break; |
4436 | case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: | |
6bf07b8e | 4437 | if (print) { |
c9ee9206 | 4438 | _print_next_block(par_num++, "USDM"); |
6bf07b8e YM |
4439 | _print_parity(bp, |
4440 | USDM_REG_USDM_PRTY_STS); | |
4441 | } | |
72fd0718 | 4442 | break; |
8736c826 | 4443 | case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: |
6bf07b8e | 4444 | if (print) { |
8736c826 | 4445 | _print_next_block(par_num++, "UCM"); |
6bf07b8e YM |
4446 | _print_parity(bp, UCM_REG_UCM_PRTY_STS); |
4447 | } | |
8736c826 | 4448 | break; |
72fd0718 | 4449 | case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: |
6bf07b8e | 4450 | if (print) { |
c9ee9206 | 4451 | _print_next_block(par_num++, "USEMI"); |
6bf07b8e YM |
4452 | _print_parity(bp, |
4453 | USEM_REG_USEM_PRTY_STS_0); | |
4454 | _print_parity(bp, | |
4455 | USEM_REG_USEM_PRTY_STS_1); | |
4456 | } | |
72fd0718 VZ |
4457 | break; |
4458 | case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: | |
6bf07b8e | 4459 | if (print) { |
c9ee9206 | 4460 | _print_next_block(par_num++, "UPB"); |
6bf07b8e YM |
4461 | _print_parity(bp, GRCBASE_UPB + |
4462 | PB_REG_PB_PRTY_STS); | |
4463 | } | |
72fd0718 VZ |
4464 | break; |
4465 | case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: | |
6bf07b8e | 4466 | if (print) { |
c9ee9206 | 4467 | _print_next_block(par_num++, "CSDM"); |
6bf07b8e YM |
4468 | _print_parity(bp, |
4469 | CSDM_REG_CSDM_PRTY_STS); | |
4470 | } | |
72fd0718 | 4471 | break; |
8736c826 | 4472 | case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: |
6bf07b8e | 4473 | if (print) { |
8736c826 | 4474 | _print_next_block(par_num++, "CCM"); |
6bf07b8e YM |
4475 | _print_parity(bp, CCM_REG_CCM_PRTY_STS); |
4476 | } | |
8736c826 | 4477 | break; |
72fd0718 VZ |
4478 | } |
4479 | ||
4480 | /* Clear the bit */ | |
4481 | sig &= ~cur_bit; | |
4482 | } | |
4483 | } | |
4484 | ||
4485 | return par_num; | |
4486 | } | |
4487 | ||
6bf07b8e YM |
4488 | static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, |
4489 | int par_num, bool print) | |
72fd0718 VZ |
4490 | { |
4491 | int i = 0; | |
4492 | u32 cur_bit = 0; | |
4493 | for (i = 0; sig; i++) { | |
4494 | cur_bit = ((u32)0x1 << i); | |
4495 | if (sig & cur_bit) { | |
4496 | switch (cur_bit) { | |
4497 | case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: | |
6bf07b8e | 4498 | if (print) { |
c9ee9206 | 4499 | _print_next_block(par_num++, "CSEMI"); |
6bf07b8e YM |
4500 | _print_parity(bp, |
4501 | CSEM_REG_CSEM_PRTY_STS_0); | |
4502 | _print_parity(bp, | |
4503 | CSEM_REG_CSEM_PRTY_STS_1); | |
4504 | } | |
72fd0718 VZ |
4505 | break; |
4506 | case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: | |
6bf07b8e | 4507 | if (print) { |
c9ee9206 | 4508 | _print_next_block(par_num++, "PXP"); |
6bf07b8e YM |
4509 | _print_parity(bp, PXP_REG_PXP_PRTY_STS); |
4510 | _print_parity(bp, | |
4511 | PXP2_REG_PXP2_PRTY_STS_0); | |
4512 | _print_parity(bp, | |
4513 | PXP2_REG_PXP2_PRTY_STS_1); | |
4514 | } | |
72fd0718 VZ |
4515 | break; |
4516 | case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: | |
c9ee9206 VZ |
4517 | if (print) |
4518 | _print_next_block(par_num++, | |
72fd0718 VZ |
4519 | "PXPPCICLOCKCLIENT"); |
4520 | break; | |
4521 | case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: | |
6bf07b8e | 4522 | if (print) { |
c9ee9206 | 4523 | _print_next_block(par_num++, "CFC"); |
6bf07b8e YM |
4524 | _print_parity(bp, |
4525 | CFC_REG_CFC_PRTY_STS); | |
4526 | } | |
72fd0718 VZ |
4527 | break; |
4528 | case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: | |
6bf07b8e | 4529 | if (print) { |
c9ee9206 | 4530 | _print_next_block(par_num++, "CDU"); |
6bf07b8e YM |
4531 | _print_parity(bp, CDU_REG_CDU_PRTY_STS); |
4532 | } | |
c9ee9206 VZ |
4533 | break; |
4534 | case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: | |
6bf07b8e | 4535 | if (print) { |
c9ee9206 | 4536 | _print_next_block(par_num++, "DMAE"); |
6bf07b8e YM |
4537 | _print_parity(bp, |
4538 | DMAE_REG_DMAE_PRTY_STS); | |
4539 | } | |
72fd0718 VZ |
4540 | break; |
4541 | case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: | |
6bf07b8e | 4542 | if (print) { |
c9ee9206 | 4543 | _print_next_block(par_num++, "IGU"); |
6bf07b8e YM |
4544 | if (CHIP_IS_E1x(bp)) |
4545 | _print_parity(bp, | |
4546 | HC_REG_HC_PRTY_STS); | |
4547 | else | |
4548 | _print_parity(bp, | |
4549 | IGU_REG_IGU_PRTY_STS); | |
4550 | } | |
72fd0718 VZ |
4551 | break; |
4552 | case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: | |
6bf07b8e | 4553 | if (print) { |
c9ee9206 | 4554 | _print_next_block(par_num++, "MISC"); |
6bf07b8e YM |
4555 | _print_parity(bp, |
4556 | MISC_REG_MISC_PRTY_STS); | |
4557 | } | |
72fd0718 VZ |
4558 | break; |
4559 | } | |
4560 | ||
4561 | /* Clear the bit */ | |
4562 | sig &= ~cur_bit; | |
4563 | } | |
4564 | } | |
4565 | ||
4566 | return par_num; | |
4567 | } | |
4568 | ||
1191cb83 ED |
4569 | static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, |
4570 | bool *global, bool print) | |
72fd0718 VZ |
4571 | { |
4572 | int i = 0; | |
4573 | u32 cur_bit = 0; | |
4574 | for (i = 0; sig; i++) { | |
4575 | cur_bit = ((u32)0x1 << i); | |
4576 | if (sig & cur_bit) { | |
4577 | switch (cur_bit) { | |
4578 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: | |
c9ee9206 VZ |
4579 | if (print) |
4580 | _print_next_block(par_num++, "MCP ROM"); | |
4581 | *global = true; | |
72fd0718 VZ |
4582 | break; |
4583 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: | |
c9ee9206 VZ |
4584 | if (print) |
4585 | _print_next_block(par_num++, | |
4586 | "MCP UMP RX"); | |
4587 | *global = true; | |
72fd0718 VZ |
4588 | break; |
4589 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: | |
c9ee9206 VZ |
4590 | if (print) |
4591 | _print_next_block(par_num++, | |
4592 | "MCP UMP TX"); | |
4593 | *global = true; | |
72fd0718 VZ |
4594 | break; |
4595 | case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: | |
c9ee9206 VZ |
4596 | if (print) |
4597 | _print_next_block(par_num++, | |
4598 | "MCP SCPAD"); | |
4599 | *global = true; | |
72fd0718 VZ |
4600 | break; |
4601 | } | |
4602 | ||
4603 | /* Clear the bit */ | |
4604 | sig &= ~cur_bit; | |
4605 | } | |
4606 | } | |
4607 | ||
4608 | return par_num; | |
4609 | } | |
4610 | ||
6bf07b8e YM |
4611 | static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, |
4612 | int par_num, bool print) | |
8736c826 VZ |
4613 | { |
4614 | int i = 0; | |
4615 | u32 cur_bit = 0; | |
4616 | for (i = 0; sig; i++) { | |
4617 | cur_bit = ((u32)0x1 << i); | |
4618 | if (sig & cur_bit) { | |
4619 | switch (cur_bit) { | |
4620 | case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: | |
6bf07b8e | 4621 | if (print) { |
8736c826 | 4622 | _print_next_block(par_num++, "PGLUE_B"); |
6bf07b8e YM |
4623 | _print_parity(bp, |
4624 | PGLUE_B_REG_PGLUE_B_PRTY_STS); | |
4625 | } | |
8736c826 VZ |
4626 | break; |
4627 | case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: | |
6bf07b8e | 4628 | if (print) { |
8736c826 | 4629 | _print_next_block(par_num++, "ATC"); |
6bf07b8e YM |
4630 | _print_parity(bp, |
4631 | ATC_REG_ATC_PRTY_STS); | |
4632 | } | |
8736c826 VZ |
4633 | break; |
4634 | } | |
4635 | ||
4636 | /* Clear the bit */ | |
4637 | sig &= ~cur_bit; | |
4638 | } | |
4639 | } | |
4640 | ||
4641 | return par_num; | |
4642 | } | |
4643 | ||
1191cb83 ED |
4644 | static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, |
4645 | u32 *sig) | |
72fd0718 | 4646 | { |
8736c826 VZ |
4647 | if ((sig[0] & HW_PRTY_ASSERT_SET_0) || |
4648 | (sig[1] & HW_PRTY_ASSERT_SET_1) || | |
4649 | (sig[2] & HW_PRTY_ASSERT_SET_2) || | |
4650 | (sig[3] & HW_PRTY_ASSERT_SET_3) || | |
4651 | (sig[4] & HW_PRTY_ASSERT_SET_4)) { | |
72fd0718 | 4652 | int par_num = 0; |
51c1a580 MS |
4653 | DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" |
4654 | "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", | |
8736c826 VZ |
4655 | sig[0] & HW_PRTY_ASSERT_SET_0, |
4656 | sig[1] & HW_PRTY_ASSERT_SET_1, | |
4657 | sig[2] & HW_PRTY_ASSERT_SET_2, | |
4658 | sig[3] & HW_PRTY_ASSERT_SET_3, | |
4659 | sig[4] & HW_PRTY_ASSERT_SET_4); | |
c9ee9206 VZ |
4660 | if (print) |
4661 | netdev_err(bp->dev, | |
4662 | "Parity errors detected in blocks: "); | |
6bf07b8e | 4663 | par_num = bnx2x_check_blocks_with_parity0(bp, |
8736c826 | 4664 | sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); |
6bf07b8e | 4665 | par_num = bnx2x_check_blocks_with_parity1(bp, |
8736c826 | 4666 | sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); |
6bf07b8e | 4667 | par_num = bnx2x_check_blocks_with_parity2(bp, |
8736c826 | 4668 | sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); |
c9ee9206 | 4669 | par_num = bnx2x_check_blocks_with_parity3( |
8736c826 | 4670 | sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); |
6bf07b8e | 4671 | par_num = bnx2x_check_blocks_with_parity4(bp, |
8736c826 VZ |
4672 | sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); |
4673 | ||
c9ee9206 VZ |
4674 | if (print) |
4675 | pr_cont("\n"); | |
8736c826 | 4676 | |
72fd0718 VZ |
4677 | return true; |
4678 | } else | |
4679 | return false; | |
4680 | } | |
4681 | ||
c9ee9206 VZ |
4682 | /** |
4683 | * bnx2x_chk_parity_attn - checks for parity attentions. | |
4684 | * | |
4685 | * @bp: driver handle | |
4686 | * @global: true if there was a global attention | |
4687 | * @print: show parity attention in syslog | |
4688 | */ | |
4689 | bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) | |
877e9aa4 | 4690 | { |
8736c826 | 4691 | struct attn_route attn = { {0} }; |
72fd0718 VZ |
4692 | int port = BP_PORT(bp); |
4693 | ||
4694 | attn.sig[0] = REG_RD(bp, | |
4695 | MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + | |
4696 | port*4); | |
4697 | attn.sig[1] = REG_RD(bp, | |
4698 | MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + | |
4699 | port*4); | |
4700 | attn.sig[2] = REG_RD(bp, | |
4701 | MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + | |
4702 | port*4); | |
4703 | attn.sig[3] = REG_RD(bp, | |
4704 | MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + | |
4705 | port*4); | |
4706 | ||
8736c826 VZ |
4707 | if (!CHIP_IS_E1x(bp)) |
4708 | attn.sig[4] = REG_RD(bp, | |
4709 | MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + | |
4710 | port*4); | |
4711 | ||
4712 | return bnx2x_parity_attn(bp, global, print, attn.sig); | |
72fd0718 VZ |
4713 | } |
4714 | ||
1191cb83 | 4715 | static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) |
f2e0899f DK |
4716 | { |
4717 | u32 val; | |
4718 | if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { | |
4719 | ||
4720 | val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); | |
4721 | BNX2X_ERR("PGLUE hw attention 0x%x\n", val); | |
4722 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) | |
51c1a580 | 4723 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); |
f2e0899f | 4724 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) |
51c1a580 | 4725 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); |
f2e0899f | 4726 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) |
51c1a580 | 4727 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); |
f2e0899f | 4728 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) |
51c1a580 | 4729 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); |
f2e0899f DK |
4730 | if (val & |
4731 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) | |
51c1a580 | 4732 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); |
f2e0899f DK |
4733 | if (val & |
4734 | PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) | |
51c1a580 | 4735 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); |
f2e0899f | 4736 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) |
51c1a580 | 4737 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); |
f2e0899f | 4738 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) |
51c1a580 | 4739 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); |
f2e0899f | 4740 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) |
51c1a580 | 4741 | BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); |
f2e0899f DK |
4742 | } |
4743 | if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { | |
4744 | val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); | |
4745 | BNX2X_ERR("ATC hw attention 0x%x\n", val); | |
4746 | if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) | |
4747 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); | |
4748 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) | |
51c1a580 | 4749 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); |
f2e0899f | 4750 | if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) |
51c1a580 | 4751 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); |
f2e0899f | 4752 | if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) |
51c1a580 | 4753 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); |
f2e0899f DK |
4754 | if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) |
4755 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); | |
4756 | if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) | |
51c1a580 | 4757 | BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); |
f2e0899f DK |
4758 | } |
4759 | ||
4760 | if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4761 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { | |
4762 | BNX2X_ERR("FATAL parity attention set4 0x%x\n", | |
4763 | (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | | |
4764 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); | |
4765 | } | |
f2e0899f DK |
4766 | } |
4767 | ||
72fd0718 VZ |
4768 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) |
4769 | { | |
4770 | struct attn_route attn, *group_mask; | |
34f80b04 | 4771 | int port = BP_PORT(bp); |
877e9aa4 | 4772 | int index; |
a2fbb9ea ET |
4773 | u32 reg_addr; |
4774 | u32 val; | |
3fcaf2e5 | 4775 | u32 aeu_mask; |
c9ee9206 | 4776 | bool global = false; |
a2fbb9ea ET |
4777 | |
4778 | /* need to take HW lock because MCP or other port might also | |
4779 | try to handle this event */ | |
4a37fb66 | 4780 | bnx2x_acquire_alr(bp); |
a2fbb9ea | 4781 | |
c9ee9206 VZ |
4782 | if (bnx2x_chk_parity_attn(bp, &global, true)) { |
4783 | #ifndef BNX2X_STOP_ON_ERROR | |
72fd0718 | 4784 | bp->recovery_state = BNX2X_RECOVERY_INIT; |
7be08a72 | 4785 | schedule_delayed_work(&bp->sp_rtnl_task, 0); |
72fd0718 VZ |
4786 | /* Disable HW interrupts */ |
4787 | bnx2x_int_disable(bp); | |
72fd0718 VZ |
4788 | /* In case of parity errors don't handle attentions so that |
4789 | * other function would "see" parity errors. | |
4790 | */ | |
c9ee9206 VZ |
4791 | #else |
4792 | bnx2x_panic(); | |
4793 | #endif | |
4794 | bnx2x_release_alr(bp); | |
72fd0718 VZ |
4795 | return; |
4796 | } | |
4797 | ||
a2fbb9ea ET |
4798 | attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); |
4799 | attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); | |
4800 | attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); | |
4801 | attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); | |
619c5cb6 | 4802 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
4803 | attn.sig[4] = |
4804 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); | |
4805 | else | |
4806 | attn.sig[4] = 0; | |
4807 | ||
4808 | DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", | |
4809 | attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); | |
a2fbb9ea ET |
4810 | |
4811 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { | |
4812 | if (deasserted & (1 << index)) { | |
72fd0718 | 4813 | group_mask = &bp->attn_group[index]; |
a2fbb9ea | 4814 | |
51c1a580 | 4815 | DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", |
f2e0899f DK |
4816 | index, |
4817 | group_mask->sig[0], group_mask->sig[1], | |
4818 | group_mask->sig[2], group_mask->sig[3], | |
4819 | group_mask->sig[4]); | |
a2fbb9ea | 4820 | |
f2e0899f DK |
4821 | bnx2x_attn_int_deasserted4(bp, |
4822 | attn.sig[4] & group_mask->sig[4]); | |
877e9aa4 | 4823 | bnx2x_attn_int_deasserted3(bp, |
72fd0718 | 4824 | attn.sig[3] & group_mask->sig[3]); |
877e9aa4 | 4825 | bnx2x_attn_int_deasserted1(bp, |
72fd0718 | 4826 | attn.sig[1] & group_mask->sig[1]); |
877e9aa4 | 4827 | bnx2x_attn_int_deasserted2(bp, |
72fd0718 | 4828 | attn.sig[2] & group_mask->sig[2]); |
877e9aa4 | 4829 | bnx2x_attn_int_deasserted0(bp, |
72fd0718 | 4830 | attn.sig[0] & group_mask->sig[0]); |
a2fbb9ea ET |
4831 | } |
4832 | } | |
4833 | ||
4a37fb66 | 4834 | bnx2x_release_alr(bp); |
a2fbb9ea | 4835 | |
f2e0899f DK |
4836 | if (bp->common.int_block == INT_BLOCK_HC) |
4837 | reg_addr = (HC_REG_COMMAND_REG + port*32 + | |
4838 | COMMAND_REG_ATTN_BITS_CLR); | |
4839 | else | |
4840 | reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); | |
a2fbb9ea ET |
4841 | |
4842 | val = ~deasserted; | |
f2e0899f DK |
4843 | DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, |
4844 | (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); | |
5c862848 | 4845 | REG_WR(bp, reg_addr, val); |
a2fbb9ea | 4846 | |
a2fbb9ea | 4847 | if (~bp->attn_state & deasserted) |
3fcaf2e5 | 4848 | BNX2X_ERR("IGU ERROR\n"); |
a2fbb9ea ET |
4849 | |
4850 | reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
4851 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
4852 | ||
3fcaf2e5 EG |
4853 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); |
4854 | aeu_mask = REG_RD(bp, reg_addr); | |
4855 | ||
4856 | DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", | |
4857 | aeu_mask, deasserted); | |
72fd0718 | 4858 | aeu_mask |= (deasserted & 0x3ff); |
3fcaf2e5 | 4859 | DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); |
a2fbb9ea | 4860 | |
3fcaf2e5 EG |
4861 | REG_WR(bp, reg_addr, aeu_mask); |
4862 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); | |
a2fbb9ea ET |
4863 | |
4864 | DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); | |
4865 | bp->attn_state &= ~deasserted; | |
4866 | DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); | |
4867 | } | |
4868 | ||
4869 | static void bnx2x_attn_int(struct bnx2x *bp) | |
4870 | { | |
4871 | /* read local copy of bits */ | |
68d59484 EG |
4872 | u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. |
4873 | attn_bits); | |
4874 | u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. | |
4875 | attn_bits_ack); | |
a2fbb9ea ET |
4876 | u32 attn_state = bp->attn_state; |
4877 | ||
4878 | /* look for changed bits */ | |
4879 | u32 asserted = attn_bits & ~attn_ack & ~attn_state; | |
4880 | u32 deasserted = ~attn_bits & attn_ack & attn_state; | |
4881 | ||
4882 | DP(NETIF_MSG_HW, | |
4883 | "attn_bits %x attn_ack %x asserted %x deasserted %x\n", | |
4884 | attn_bits, attn_ack, asserted, deasserted); | |
4885 | ||
4886 | if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) | |
34f80b04 | 4887 | BNX2X_ERR("BAD attention state\n"); |
a2fbb9ea ET |
4888 | |
4889 | /* handle bits that were raised */ | |
4890 | if (asserted) | |
4891 | bnx2x_attn_int_asserted(bp, asserted); | |
4892 | ||
4893 | if (deasserted) | |
4894 | bnx2x_attn_int_deasserted(bp, deasserted); | |
4895 | } | |
4896 | ||
619c5cb6 VZ |
4897 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, |
4898 | u16 index, u8 op, u8 update) | |
4899 | { | |
dc1ba591 AE |
4900 | u32 igu_addr = bp->igu_base_addr; |
4901 | igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; | |
619c5cb6 VZ |
4902 | bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, |
4903 | igu_addr); | |
4904 | } | |
4905 | ||
1191cb83 | 4906 | static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) |
523224a3 DK |
4907 | { |
4908 | /* No memory barriers */ | |
4909 | storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); | |
4910 | mmiowb(); /* keep prod updates ordered */ | |
4911 | } | |
4912 | ||
523224a3 DK |
4913 | static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, |
4914 | union event_ring_elem *elem) | |
4915 | { | |
619c5cb6 VZ |
4916 | u8 err = elem->message.error; |
4917 | ||
523224a3 | 4918 | if (!bp->cnic_eth_dev.starting_cid || |
c3a8ce61 VZ |
4919 | (cid < bp->cnic_eth_dev.starting_cid && |
4920 | cid != bp->cnic_eth_dev.iscsi_l2_cid)) | |
523224a3 DK |
4921 | return 1; |
4922 | ||
4923 | DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); | |
4924 | ||
619c5cb6 VZ |
4925 | if (unlikely(err)) { |
4926 | ||
523224a3 DK |
4927 | BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", |
4928 | cid); | |
823e1d90 | 4929 | bnx2x_panic_dump(bp, false); |
523224a3 | 4930 | } |
619c5cb6 | 4931 | bnx2x_cnic_cfc_comp(bp, cid, err); |
523224a3 DK |
4932 | return 0; |
4933 | } | |
523224a3 | 4934 | |
1191cb83 | 4935 | static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
4936 | { |
4937 | struct bnx2x_mcast_ramrod_params rparam; | |
4938 | int rc; | |
4939 | ||
4940 | memset(&rparam, 0, sizeof(rparam)); | |
4941 | ||
4942 | rparam.mcast_obj = &bp->mcast_obj; | |
4943 | ||
4944 | netif_addr_lock_bh(bp->dev); | |
4945 | ||
4946 | /* Clear pending state for the last command */ | |
4947 | bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); | |
4948 | ||
4949 | /* If there are pending mcast commands - send them */ | |
4950 | if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { | |
4951 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); | |
4952 | if (rc < 0) | |
4953 | BNX2X_ERR("Failed to send pending mcast commands: %d\n", | |
4954 | rc); | |
4955 | } | |
4956 | ||
4957 | netif_addr_unlock_bh(bp->dev); | |
4958 | } | |
4959 | ||
1191cb83 ED |
4960 | static void bnx2x_handle_classification_eqe(struct bnx2x *bp, |
4961 | union event_ring_elem *elem) | |
619c5cb6 VZ |
4962 | { |
4963 | unsigned long ramrod_flags = 0; | |
4964 | int rc = 0; | |
4965 | u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK; | |
4966 | struct bnx2x_vlan_mac_obj *vlan_mac_obj; | |
4967 | ||
4968 | /* Always push next commands out, don't wait here */ | |
4969 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
4970 | ||
86564c3f YM |
4971 | switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo) |
4972 | >> BNX2X_SWCID_SHIFT) { | |
619c5cb6 | 4973 | case BNX2X_FILTER_MAC_PENDING: |
51c1a580 | 4974 | DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); |
55c11941 | 4975 | if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) |
619c5cb6 VZ |
4976 | vlan_mac_obj = &bp->iscsi_l2_mac_obj; |
4977 | else | |
15192a8c | 4978 | vlan_mac_obj = &bp->sp_objs[cid].mac_obj; |
619c5cb6 VZ |
4979 | |
4980 | break; | |
619c5cb6 | 4981 | case BNX2X_FILTER_MCAST_PENDING: |
51c1a580 | 4982 | DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); |
619c5cb6 VZ |
4983 | /* This is only relevant for 57710 where multicast MACs are |
4984 | * configured as unicast MACs using the same ramrod. | |
4985 | */ | |
4986 | bnx2x_handle_mcast_eqe(bp); | |
4987 | return; | |
4988 | default: | |
4989 | BNX2X_ERR("Unsupported classification command: %d\n", | |
4990 | elem->message.data.eth_event.echo); | |
4991 | return; | |
4992 | } | |
4993 | ||
4994 | rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); | |
4995 | ||
4996 | if (rc < 0) | |
4997 | BNX2X_ERR("Failed to schedule new commands: %d\n", rc); | |
4998 | else if (rc > 0) | |
4999 | DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); | |
619c5cb6 VZ |
5000 | } |
5001 | ||
619c5cb6 | 5002 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); |
619c5cb6 | 5003 | |
1191cb83 | 5004 | static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) |
619c5cb6 VZ |
5005 | { |
5006 | netif_addr_lock_bh(bp->dev); | |
5007 | ||
5008 | clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5009 | ||
5010 | /* Send rx_mode command again if was requested */ | |
5011 | if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) | |
5012 | bnx2x_set_storm_rx_mode(bp); | |
619c5cb6 VZ |
5013 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, |
5014 | &bp->sp_state)) | |
5015 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
5016 | else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, | |
5017 | &bp->sp_state)) | |
5018 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
619c5cb6 VZ |
5019 | |
5020 | netif_addr_unlock_bh(bp->dev); | |
5021 | } | |
5022 | ||
1191cb83 | 5023 | static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, |
a3348722 BW |
5024 | union event_ring_elem *elem) |
5025 | { | |
5026 | if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { | |
5027 | DP(BNX2X_MSG_SP, | |
5028 | "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", | |
5029 | elem->message.data.vif_list_event.func_bit_map); | |
5030 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, | |
5031 | elem->message.data.vif_list_event.func_bit_map); | |
5032 | } else if (elem->message.data.vif_list_event.echo == | |
5033 | VIF_LIST_RULE_SET) { | |
5034 | DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); | |
5035 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); | |
5036 | } | |
5037 | } | |
5038 | ||
5039 | /* called with rtnl_lock */ | |
1191cb83 | 5040 | static void bnx2x_after_function_update(struct bnx2x *bp) |
a3348722 BW |
5041 | { |
5042 | int q, rc; | |
5043 | struct bnx2x_fastpath *fp; | |
5044 | struct bnx2x_queue_state_params queue_params = {NULL}; | |
5045 | struct bnx2x_queue_update_params *q_update_params = | |
5046 | &queue_params.params.update; | |
5047 | ||
2de67439 | 5048 | /* Send Q update command with afex vlan removal values for all Qs */ |
a3348722 BW |
5049 | queue_params.cmd = BNX2X_Q_CMD_UPDATE; |
5050 | ||
5051 | /* set silent vlan removal values according to vlan mode */ | |
5052 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, | |
5053 | &q_update_params->update_flags); | |
5054 | __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, | |
5055 | &q_update_params->update_flags); | |
5056 | __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5057 | ||
5058 | /* in access mode mark mask and value are 0 to strip all vlans */ | |
5059 | if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { | |
5060 | q_update_params->silent_removal_value = 0; | |
5061 | q_update_params->silent_removal_mask = 0; | |
5062 | } else { | |
5063 | q_update_params->silent_removal_value = | |
5064 | (bp->afex_def_vlan_tag & VLAN_VID_MASK); | |
5065 | q_update_params->silent_removal_mask = VLAN_VID_MASK; | |
5066 | } | |
5067 | ||
5068 | for_each_eth_queue(bp, q) { | |
5069 | /* Set the appropriate Queue object */ | |
5070 | fp = &bp->fp[q]; | |
15192a8c | 5071 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5072 | |
5073 | /* send the ramrod */ | |
5074 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5075 | if (rc < 0) | |
5076 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5077 | q); | |
5078 | } | |
5079 | ||
fea75645 | 5080 | if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { |
65565884 | 5081 | fp = &bp->fp[FCOE_IDX(bp)]; |
15192a8c | 5082 | queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
a3348722 BW |
5083 | |
5084 | /* clear pending completion bit */ | |
5085 | __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); | |
5086 | ||
5087 | /* mark latest Q bit */ | |
5088 | smp_mb__before_clear_bit(); | |
5089 | set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); | |
5090 | smp_mb__after_clear_bit(); | |
5091 | ||
5092 | /* send Q update ramrod for FCoE Q */ | |
5093 | rc = bnx2x_queue_state_change(bp, &queue_params); | |
5094 | if (rc < 0) | |
5095 | BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", | |
5096 | q); | |
5097 | } else { | |
5098 | /* If no FCoE ring - ACK MCP now */ | |
5099 | bnx2x_link_report(bp); | |
5100 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5101 | } | |
a3348722 BW |
5102 | } |
5103 | ||
1191cb83 | 5104 | static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( |
619c5cb6 VZ |
5105 | struct bnx2x *bp, u32 cid) |
5106 | { | |
94f05b0f | 5107 | DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); |
55c11941 MS |
5108 | |
5109 | if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) | |
15192a8c | 5110 | return &bnx2x_fcoe_sp_obj(bp, q_obj); |
619c5cb6 | 5111 | else |
15192a8c | 5112 | return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; |
619c5cb6 VZ |
5113 | } |
5114 | ||
523224a3 DK |
5115 | static void bnx2x_eq_int(struct bnx2x *bp) |
5116 | { | |
5117 | u16 hw_cons, sw_cons, sw_prod; | |
5118 | union event_ring_elem *elem; | |
55c11941 | 5119 | u8 echo; |
523224a3 DK |
5120 | u32 cid; |
5121 | u8 opcode; | |
fd1fc79d | 5122 | int rc, spqe_cnt = 0; |
619c5cb6 VZ |
5123 | struct bnx2x_queue_sp_obj *q_obj; |
5124 | struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; | |
5125 | struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; | |
523224a3 DK |
5126 | |
5127 | hw_cons = le16_to_cpu(*bp->eq_cons_sb); | |
5128 | ||
5129 | /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. | |
16a5fd92 | 5130 | * when we get the next-page we need to adjust so the loop |
523224a3 DK |
5131 | * condition below will be met. The next element is the size of a |
5132 | * regular element and hence incrementing by 1 | |
5133 | */ | |
5134 | if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) | |
5135 | hw_cons++; | |
5136 | ||
25985edc | 5137 | /* This function may never run in parallel with itself for a |
523224a3 DK |
5138 | * specific bp, thus there is no need in "paired" read memory |
5139 | * barrier here. | |
5140 | */ | |
5141 | sw_cons = bp->eq_cons; | |
5142 | sw_prod = bp->eq_prod; | |
5143 | ||
d6cae238 | 5144 | DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", |
6e30dd4e | 5145 | hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); |
523224a3 DK |
5146 | |
5147 | for (; sw_cons != hw_cons; | |
5148 | sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { | |
5149 | ||
523224a3 DK |
5150 | elem = &bp->eq_ring[EQ_DESC(sw_cons)]; |
5151 | ||
fd1fc79d AE |
5152 | rc = bnx2x_iov_eq_sp_event(bp, elem); |
5153 | if (!rc) { | |
5154 | DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", | |
5155 | rc); | |
5156 | goto next_spqe; | |
5157 | } | |
523224a3 | 5158 | |
86564c3f YM |
5159 | /* elem CID originates from FW; actually LE */ |
5160 | cid = SW_CID((__force __le32) | |
5161 | elem->message.data.cfc_del_event.cid); | |
5162 | opcode = elem->message.opcode; | |
523224a3 DK |
5163 | |
5164 | /* handle eq element */ | |
5165 | switch (opcode) { | |
fd1fc79d AE |
5166 | case EVENT_RING_OPCODE_VF_PF_CHANNEL: |
5167 | DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n"); | |
5168 | bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event); | |
5169 | continue; | |
5170 | ||
523224a3 | 5171 | case EVENT_RING_OPCODE_STAT_QUERY: |
51c1a580 MS |
5172 | DP(BNX2X_MSG_SP | BNX2X_MSG_STATS, |
5173 | "got statistics comp event %d\n", | |
619c5cb6 | 5174 | bp->stats_comp++); |
523224a3 | 5175 | /* nothing to do with stats comp */ |
d6cae238 | 5176 | goto next_spqe; |
523224a3 DK |
5177 | |
5178 | case EVENT_RING_OPCODE_CFC_DEL: | |
5179 | /* handle according to cid range */ | |
5180 | /* | |
5181 | * we may want to verify here that the bp state is | |
5182 | * HALTING | |
5183 | */ | |
d6cae238 | 5184 | DP(BNX2X_MSG_SP, |
523224a3 | 5185 | "got delete ramrod for MULTI[%d]\n", cid); |
55c11941 MS |
5186 | |
5187 | if (CNIC_LOADED(bp) && | |
5188 | !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) | |
523224a3 | 5189 | goto next_spqe; |
55c11941 | 5190 | |
619c5cb6 VZ |
5191 | q_obj = bnx2x_cid_to_q_obj(bp, cid); |
5192 | ||
5193 | if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) | |
5194 | break; | |
5195 | ||
523224a3 | 5196 | goto next_spqe; |
e4901dde VZ |
5197 | |
5198 | case EVENT_RING_OPCODE_STOP_TRAFFIC: | |
51c1a580 | 5199 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); |
6debea87 DK |
5200 | if (f_obj->complete_cmd(bp, f_obj, |
5201 | BNX2X_F_CMD_TX_STOP)) | |
5202 | break; | |
e4901dde VZ |
5203 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); |
5204 | goto next_spqe; | |
619c5cb6 | 5205 | |
e4901dde | 5206 | case EVENT_RING_OPCODE_START_TRAFFIC: |
51c1a580 | 5207 | DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); |
6debea87 DK |
5208 | if (f_obj->complete_cmd(bp, f_obj, |
5209 | BNX2X_F_CMD_TX_START)) | |
5210 | break; | |
e4901dde VZ |
5211 | bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); |
5212 | goto next_spqe; | |
55c11941 | 5213 | |
a3348722 | 5214 | case EVENT_RING_OPCODE_FUNCTION_UPDATE: |
55c11941 MS |
5215 | echo = elem->message.data.function_update_event.echo; |
5216 | if (echo == SWITCH_UPDATE) { | |
5217 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, | |
5218 | "got FUNC_SWITCH_UPDATE ramrod\n"); | |
5219 | if (f_obj->complete_cmd( | |
5220 | bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) | |
5221 | break; | |
a3348722 | 5222 | |
55c11941 MS |
5223 | } else { |
5224 | DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, | |
5225 | "AFEX: ramrod completed FUNCTION_UPDATE\n"); | |
5226 | f_obj->complete_cmd(bp, f_obj, | |
5227 | BNX2X_F_CMD_AFEX_UPDATE); | |
5228 | ||
5229 | /* We will perform the Queues update from | |
5230 | * sp_rtnl task as all Queue SP operations | |
5231 | * should run under rtnl_lock. | |
5232 | */ | |
5233 | smp_mb__before_clear_bit(); | |
5234 | set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, | |
5235 | &bp->sp_rtnl_state); | |
5236 | smp_mb__after_clear_bit(); | |
5237 | ||
5238 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
5239 | } | |
a3348722 | 5240 | |
a3348722 BW |
5241 | goto next_spqe; |
5242 | ||
5243 | case EVENT_RING_OPCODE_AFEX_VIF_LISTS: | |
5244 | f_obj->complete_cmd(bp, f_obj, | |
5245 | BNX2X_F_CMD_AFEX_VIFLISTS); | |
5246 | bnx2x_after_afex_vif_lists(bp, elem); | |
5247 | goto next_spqe; | |
619c5cb6 | 5248 | case EVENT_RING_OPCODE_FUNCTION_START: |
51c1a580 MS |
5249 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5250 | "got FUNC_START ramrod\n"); | |
619c5cb6 VZ |
5251 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) |
5252 | break; | |
5253 | ||
5254 | goto next_spqe; | |
5255 | ||
5256 | case EVENT_RING_OPCODE_FUNCTION_STOP: | |
51c1a580 MS |
5257 | DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, |
5258 | "got FUNC_STOP ramrod\n"); | |
619c5cb6 VZ |
5259 | if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) |
5260 | break; | |
5261 | ||
5262 | goto next_spqe; | |
523224a3 DK |
5263 | } |
5264 | ||
5265 | switch (opcode | bp->state) { | |
619c5cb6 VZ |
5266 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | |
5267 | BNX2X_STATE_OPEN): | |
5268 | case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | | |
523224a3 | 5269 | BNX2X_STATE_OPENING_WAIT4_PORT): |
619c5cb6 VZ |
5270 | cid = elem->message.data.eth_event.echo & |
5271 | BNX2X_SWCID_MASK; | |
d6cae238 | 5272 | DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", |
619c5cb6 VZ |
5273 | cid); |
5274 | rss_raw->clear_pending(rss_raw); | |
523224a3 DK |
5275 | break; |
5276 | ||
619c5cb6 VZ |
5277 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): |
5278 | case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): | |
5279 | case (EVENT_RING_OPCODE_SET_MAC | | |
523224a3 | 5280 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
619c5cb6 VZ |
5281 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | |
5282 | BNX2X_STATE_OPEN): | |
5283 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5284 | BNX2X_STATE_DIAG): | |
5285 | case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | | |
5286 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5287 | DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n"); |
619c5cb6 | 5288 | bnx2x_handle_classification_eqe(bp, elem); |
523224a3 DK |
5289 | break; |
5290 | ||
619c5cb6 VZ |
5291 | case (EVENT_RING_OPCODE_MULTICAST_RULES | |
5292 | BNX2X_STATE_OPEN): | |
5293 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5294 | BNX2X_STATE_DIAG): | |
5295 | case (EVENT_RING_OPCODE_MULTICAST_RULES | | |
5296 | BNX2X_STATE_CLOSING_WAIT4_HALT): | |
d6cae238 | 5297 | DP(BNX2X_MSG_SP, "got mcast ramrod\n"); |
619c5cb6 | 5298 | bnx2x_handle_mcast_eqe(bp); |
523224a3 DK |
5299 | break; |
5300 | ||
619c5cb6 VZ |
5301 | case (EVENT_RING_OPCODE_FILTERS_RULES | |
5302 | BNX2X_STATE_OPEN): | |
5303 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
5304 | BNX2X_STATE_DIAG): | |
5305 | case (EVENT_RING_OPCODE_FILTERS_RULES | | |
523224a3 | 5306 | BNX2X_STATE_CLOSING_WAIT4_HALT): |
d6cae238 | 5307 | DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); |
619c5cb6 | 5308 | bnx2x_handle_rx_mode_eqe(bp); |
523224a3 DK |
5309 | break; |
5310 | default: | |
5311 | /* unknown event log error and continue */ | |
619c5cb6 VZ |
5312 | BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", |
5313 | elem->message.opcode, bp->state); | |
523224a3 DK |
5314 | } |
5315 | next_spqe: | |
5316 | spqe_cnt++; | |
5317 | } /* for */ | |
5318 | ||
8fe23fbd | 5319 | smp_mb__before_atomic_inc(); |
6e30dd4e | 5320 | atomic_add(spqe_cnt, &bp->eq_spq_left); |
523224a3 DK |
5321 | |
5322 | bp->eq_cons = sw_cons; | |
5323 | bp->eq_prod = sw_prod; | |
5324 | /* Make sure that above mem writes were issued towards the memory */ | |
5325 | smp_wmb(); | |
5326 | ||
5327 | /* update producer */ | |
5328 | bnx2x_update_eq_prod(bp, bp->eq_prod); | |
5329 | } | |
5330 | ||
a2fbb9ea ET |
5331 | static void bnx2x_sp_task(struct work_struct *work) |
5332 | { | |
1cf167f2 | 5333 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); |
a2fbb9ea | 5334 | |
fd1fc79d | 5335 | DP(BNX2X_MSG_SP, "sp task invoked\n"); |
a2fbb9ea | 5336 | |
16a5fd92 | 5337 | /* make sure the atomic interrupt_occurred has been written */ |
fd1fc79d AE |
5338 | smp_rmb(); |
5339 | if (atomic_read(&bp->interrupt_occurred)) { | |
a2fbb9ea | 5340 | |
fd1fc79d AE |
5341 | /* what work needs to be performed? */ |
5342 | u16 status = bnx2x_update_dsb_idx(bp); | |
cdaa7cb8 | 5343 | |
fd1fc79d AE |
5344 | DP(BNX2X_MSG_SP, "status %x\n", status); |
5345 | DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); | |
5346 | atomic_set(&bp->interrupt_occurred, 0); | |
5347 | ||
5348 | /* HW attentions */ | |
5349 | if (status & BNX2X_DEF_SB_ATT_IDX) { | |
5350 | bnx2x_attn_int(bp); | |
5351 | status &= ~BNX2X_DEF_SB_ATT_IDX; | |
5352 | } | |
5353 | ||
5354 | /* SP events: STAT_QUERY and others */ | |
5355 | if (status & BNX2X_DEF_SB_IDX) { | |
5356 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); | |
523224a3 | 5357 | |
55c11941 | 5358 | if (FCOE_INIT(bp) && |
fd1fc79d AE |
5359 | (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { |
5360 | /* Prevent local bottom-halves from running as | |
5361 | * we are going to change the local NAPI list. | |
5362 | */ | |
5363 | local_bh_disable(); | |
5364 | napi_schedule(&bnx2x_fcoe(bp, napi)); | |
5365 | local_bh_enable(); | |
5366 | } | |
5367 | ||
5368 | /* Handle EQ completions */ | |
5369 | bnx2x_eq_int(bp); | |
5370 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, | |
5371 | le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); | |
5372 | ||
5373 | status &= ~BNX2X_DEF_SB_IDX; | |
019dbb4c | 5374 | } |
55c11941 | 5375 | |
fd1fc79d AE |
5376 | /* if status is non zero then perhaps something went wrong */ |
5377 | if (unlikely(status)) | |
5378 | DP(BNX2X_MSG_SP, | |
5379 | "got an unknown interrupt! (status 0x%x)\n", status); | |
523224a3 | 5380 | |
fd1fc79d AE |
5381 | /* ack status block only if something was actually handled */ |
5382 | bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, | |
5383 | le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); | |
cdaa7cb8 VZ |
5384 | } |
5385 | ||
fd1fc79d AE |
5386 | /* must be called after the EQ processing (since eq leads to sriov |
5387 | * ramrod completion flows). | |
5388 | * This flow may have been scheduled by the arrival of a ramrod | |
5389 | * completion, or by the sriov code rescheduling itself. | |
5390 | */ | |
5391 | bnx2x_iov_sp_task(bp); | |
a3348722 BW |
5392 | |
5393 | /* afex - poll to check if VIFSET_ACK should be sent to MFW */ | |
5394 | if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, | |
5395 | &bp->sp_state)) { | |
5396 | bnx2x_link_report(bp); | |
5397 | bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); | |
5398 | } | |
a2fbb9ea ET |
5399 | } |
5400 | ||
9f6c9258 | 5401 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
a2fbb9ea ET |
5402 | { |
5403 | struct net_device *dev = dev_instance; | |
5404 | struct bnx2x *bp = netdev_priv(dev); | |
5405 | ||
523224a3 DK |
5406 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, |
5407 | IGU_INT_DISABLE, 0); | |
a2fbb9ea ET |
5408 | |
5409 | #ifdef BNX2X_STOP_ON_ERROR | |
5410 | if (unlikely(bp->panic)) | |
5411 | return IRQ_HANDLED; | |
5412 | #endif | |
5413 | ||
55c11941 | 5414 | if (CNIC_LOADED(bp)) { |
993ac7b5 MC |
5415 | struct cnic_ops *c_ops; |
5416 | ||
5417 | rcu_read_lock(); | |
5418 | c_ops = rcu_dereference(bp->cnic_ops); | |
5419 | if (c_ops) | |
5420 | c_ops->cnic_handler(bp->cnic_data, NULL); | |
5421 | rcu_read_unlock(); | |
5422 | } | |
55c11941 | 5423 | |
fd1fc79d AE |
5424 | /* schedule sp task to perform default status block work, ack |
5425 | * attentions and enable interrupts. | |
5426 | */ | |
5427 | bnx2x_schedule_sp_task(bp); | |
a2fbb9ea ET |
5428 | |
5429 | return IRQ_HANDLED; | |
5430 | } | |
5431 | ||
5432 | /* end of slow path */ | |
5433 | ||
619c5cb6 VZ |
5434 | void bnx2x_drv_pulse(struct bnx2x *bp) |
5435 | { | |
5436 | SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, | |
5437 | bp->fw_drv_pulse_wr_seq); | |
5438 | } | |
5439 | ||
a2fbb9ea ET |
5440 | static void bnx2x_timer(unsigned long data) |
5441 | { | |
5442 | struct bnx2x *bp = (struct bnx2x *) data; | |
5443 | ||
5444 | if (!netif_running(bp->dev)) | |
5445 | return; | |
5446 | ||
67c431a5 AE |
5447 | if (IS_PF(bp) && |
5448 | !BP_NOMCP(bp)) { | |
f2e0899f | 5449 | int mb_idx = BP_FW_MB_IDX(bp); |
4c868664 EG |
5450 | u16 drv_pulse; |
5451 | u16 mcp_pulse; | |
a2fbb9ea ET |
5452 | |
5453 | ++bp->fw_drv_pulse_wr_seq; | |
5454 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | |
a2fbb9ea | 5455 | drv_pulse = bp->fw_drv_pulse_wr_seq; |
619c5cb6 | 5456 | bnx2x_drv_pulse(bp); |
a2fbb9ea | 5457 | |
f2e0899f | 5458 | mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & |
a2fbb9ea ET |
5459 | MCP_PULSE_SEQ_MASK); |
5460 | /* The delta between driver pulse and mcp response | |
4c868664 EG |
5461 | * should not get too big. If the MFW is more than 5 pulses |
5462 | * behind, we should worry about it enough to generate an error | |
5463 | * log. | |
a2fbb9ea | 5464 | */ |
4c868664 EG |
5465 | if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5) |
5466 | BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n", | |
a2fbb9ea | 5467 | drv_pulse, mcp_pulse); |
a2fbb9ea ET |
5468 | } |
5469 | ||
f34d28ea | 5470 | if (bp->state == BNX2X_STATE_OPEN) |
bb2a0f7a | 5471 | bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); |
a2fbb9ea | 5472 | |
abc5a021 | 5473 | /* sample pf vf bulletin board for new posts from pf */ |
37173488 YM |
5474 | if (IS_VF(bp)) |
5475 | bnx2x_timer_sriov(bp); | |
78c3bcc5 | 5476 | |
a2fbb9ea ET |
5477 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
5478 | } | |
5479 | ||
5480 | /* end of Statistics */ | |
5481 | ||
5482 | /* nic init */ | |
5483 | ||
5484 | /* | |
5485 | * nic init service functions | |
5486 | */ | |
5487 | ||
1191cb83 | 5488 | static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
a2fbb9ea | 5489 | { |
523224a3 DK |
5490 | u32 i; |
5491 | if (!(len%4) && !(addr%4)) | |
5492 | for (i = 0; i < len; i += 4) | |
5493 | REG_WR(bp, addr + i, fill); | |
5494 | else | |
5495 | for (i = 0; i < len; i++) | |
5496 | REG_WR8(bp, addr + i, fill); | |
34f80b04 EG |
5497 | } |
5498 | ||
523224a3 | 5499 | /* helper: writes FP SP data to FW - data_size in dwords */ |
1191cb83 ED |
5500 | static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, |
5501 | int fw_sb_id, | |
5502 | u32 *sb_data_p, | |
5503 | u32 data_size) | |
34f80b04 | 5504 | { |
a2fbb9ea | 5505 | int index; |
523224a3 DK |
5506 | for (index = 0; index < data_size; index++) |
5507 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5508 | CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + | |
5509 | sizeof(u32)*index, | |
5510 | *(sb_data_p + index)); | |
5511 | } | |
a2fbb9ea | 5512 | |
1191cb83 | 5513 | static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) |
523224a3 DK |
5514 | { |
5515 | u32 *sb_data_p; | |
5516 | u32 data_size = 0; | |
f2e0899f | 5517 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 | 5518 | struct hc_status_block_data_e1x sb_data_e1x; |
a2fbb9ea | 5519 | |
523224a3 | 5520 | /* disable the function first */ |
619c5cb6 | 5521 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5522 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5523 | sb_data_e2.common.state = SB_DISABLED; |
f2e0899f DK |
5524 | sb_data_e2.common.p_func.vf_valid = false; |
5525 | sb_data_p = (u32 *)&sb_data_e2; | |
5526 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
5527 | } else { | |
5528 | memset(&sb_data_e1x, 0, | |
5529 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5530 | sb_data_e1x.common.state = SB_DISABLED; |
f2e0899f DK |
5531 | sb_data_e1x.common.p_func.vf_valid = false; |
5532 | sb_data_p = (u32 *)&sb_data_e1x; | |
5533 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
5534 | } | |
523224a3 | 5535 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
a2fbb9ea | 5536 | |
523224a3 DK |
5537 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + |
5538 | CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, | |
5539 | CSTORM_STATUS_BLOCK_SIZE); | |
5540 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5541 | CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, | |
5542 | CSTORM_SYNC_BLOCK_SIZE); | |
5543 | } | |
34f80b04 | 5544 | |
523224a3 | 5545 | /* helper: writes SP SB data to FW */ |
1191cb83 | 5546 | static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, |
523224a3 DK |
5547 | struct hc_sp_status_block_data *sp_sb_data) |
5548 | { | |
5549 | int func = BP_FUNC(bp); | |
5550 | int i; | |
5551 | for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) | |
5552 | REG_WR(bp, BAR_CSTRORM_INTMEM + | |
5553 | CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + | |
5554 | i*sizeof(u32), | |
5555 | *((u32 *)sp_sb_data + i)); | |
34f80b04 EG |
5556 | } |
5557 | ||
1191cb83 | 5558 | static void bnx2x_zero_sp_sb(struct bnx2x *bp) |
34f80b04 EG |
5559 | { |
5560 | int func = BP_FUNC(bp); | |
523224a3 DK |
5561 | struct hc_sp_status_block_data sp_sb_data; |
5562 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
a2fbb9ea | 5563 | |
619c5cb6 | 5564 | sp_sb_data.state = SB_DISABLED; |
523224a3 DK |
5565 | sp_sb_data.p_func.vf_valid = false; |
5566 | ||
5567 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); | |
5568 | ||
5569 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5570 | CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, | |
5571 | CSTORM_SP_STATUS_BLOCK_SIZE); | |
5572 | bnx2x_fill(bp, BAR_CSTRORM_INTMEM + | |
5573 | CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, | |
5574 | CSTORM_SP_SYNC_BLOCK_SIZE); | |
523224a3 DK |
5575 | } |
5576 | ||
1191cb83 | 5577 | static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, |
523224a3 DK |
5578 | int igu_sb_id, int igu_seg_id) |
5579 | { | |
5580 | hc_sm->igu_sb_id = igu_sb_id; | |
5581 | hc_sm->igu_seg_id = igu_seg_id; | |
5582 | hc_sm->timer_value = 0xFF; | |
5583 | hc_sm->time_to_expire = 0xFFFFFFFF; | |
a2fbb9ea ET |
5584 | } |
5585 | ||
150966ad | 5586 | /* allocates state machine ids. */ |
1191cb83 | 5587 | static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) |
150966ad AE |
5588 | { |
5589 | /* zero out state machine indices */ | |
5590 | /* rx indices */ | |
5591 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5592 | ||
5593 | /* tx indices */ | |
5594 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | |
5595 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | |
5596 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | |
5597 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | |
5598 | ||
5599 | /* map indices */ | |
5600 | /* rx indices */ | |
5601 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | |
5602 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5603 | ||
5604 | /* tx indices */ | |
5605 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | |
5606 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5607 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | |
5608 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5609 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | |
5610 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5611 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | |
5612 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | |
5613 | } | |
5614 | ||
b93288d5 | 5615 | void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
523224a3 | 5616 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
a2fbb9ea | 5617 | { |
523224a3 DK |
5618 | int igu_seg_id; |
5619 | ||
f2e0899f | 5620 | struct hc_status_block_data_e2 sb_data_e2; |
523224a3 DK |
5621 | struct hc_status_block_data_e1x sb_data_e1x; |
5622 | struct hc_status_block_sm *hc_sm_p; | |
523224a3 DK |
5623 | int data_size; |
5624 | u32 *sb_data_p; | |
5625 | ||
f2e0899f DK |
5626 | if (CHIP_INT_MODE_IS_BC(bp)) |
5627 | igu_seg_id = HC_SEG_ACCESS_NORM; | |
5628 | else | |
5629 | igu_seg_id = IGU_SEG_ACCESS_NORM; | |
523224a3 DK |
5630 | |
5631 | bnx2x_zero_fp_sb(bp, fw_sb_id); | |
5632 | ||
619c5cb6 | 5633 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f | 5634 | memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); |
619c5cb6 | 5635 | sb_data_e2.common.state = SB_ENABLED; |
f2e0899f DK |
5636 | sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); |
5637 | sb_data_e2.common.p_func.vf_id = vfid; | |
5638 | sb_data_e2.common.p_func.vf_valid = vf_valid; | |
5639 | sb_data_e2.common.p_func.vnic_id = BP_VN(bp); | |
5640 | sb_data_e2.common.same_igu_sb_1b = true; | |
5641 | sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); | |
5642 | sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); | |
5643 | hc_sm_p = sb_data_e2.common.state_machine; | |
f2e0899f DK |
5644 | sb_data_p = (u32 *)&sb_data_e2; |
5645 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | |
150966ad | 5646 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); |
f2e0899f DK |
5647 | } else { |
5648 | memset(&sb_data_e1x, 0, | |
5649 | sizeof(struct hc_status_block_data_e1x)); | |
619c5cb6 | 5650 | sb_data_e1x.common.state = SB_ENABLED; |
f2e0899f DK |
5651 | sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); |
5652 | sb_data_e1x.common.p_func.vf_id = 0xff; | |
5653 | sb_data_e1x.common.p_func.vf_valid = false; | |
5654 | sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); | |
5655 | sb_data_e1x.common.same_igu_sb_1b = true; | |
5656 | sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); | |
5657 | sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); | |
5658 | hc_sm_p = sb_data_e1x.common.state_machine; | |
f2e0899f DK |
5659 | sb_data_p = (u32 *)&sb_data_e1x; |
5660 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | |
150966ad | 5661 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); |
f2e0899f | 5662 | } |
523224a3 DK |
5663 | |
5664 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | |
5665 | igu_sb_id, igu_seg_id); | |
5666 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], | |
5667 | igu_sb_id, igu_seg_id); | |
5668 | ||
51c1a580 | 5669 | DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); |
523224a3 | 5670 | |
86564c3f | 5671 | /* write indices to HW - PCI guarantees endianity of regpairs */ |
523224a3 DK |
5672 | bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); |
5673 | } | |
5674 | ||
619c5cb6 | 5675 | static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, |
523224a3 DK |
5676 | u16 tx_usec, u16 rx_usec) |
5677 | { | |
6383c0b3 | 5678 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, |
523224a3 | 5679 | false, rx_usec); |
6383c0b3 AE |
5680 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, |
5681 | HC_INDEX_ETH_TX_CQ_CONS_COS0, false, | |
5682 | tx_usec); | |
5683 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5684 | HC_INDEX_ETH_TX_CQ_CONS_COS1, false, | |
5685 | tx_usec); | |
5686 | bnx2x_update_coalesce_sb_index(bp, fw_sb_id, | |
5687 | HC_INDEX_ETH_TX_CQ_CONS_COS2, false, | |
5688 | tx_usec); | |
523224a3 | 5689 | } |
f2e0899f | 5690 | |
523224a3 DK |
5691 | static void bnx2x_init_def_sb(struct bnx2x *bp) |
5692 | { | |
5693 | struct host_sp_status_block *def_sb = bp->def_status_blk; | |
5694 | dma_addr_t mapping = bp->def_status_blk_mapping; | |
5695 | int igu_sp_sb_index; | |
5696 | int igu_seg_id; | |
34f80b04 EG |
5697 | int port = BP_PORT(bp); |
5698 | int func = BP_FUNC(bp); | |
f2eaeb58 | 5699 | int reg_offset, reg_offset_en5; |
a2fbb9ea | 5700 | u64 section; |
523224a3 DK |
5701 | int index; |
5702 | struct hc_sp_status_block_data sp_sb_data; | |
5703 | memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); | |
5704 | ||
f2e0899f DK |
5705 | if (CHIP_INT_MODE_IS_BC(bp)) { |
5706 | igu_sp_sb_index = DEF_SB_IGU_ID; | |
5707 | igu_seg_id = HC_SEG_ACCESS_DEF; | |
5708 | } else { | |
5709 | igu_sp_sb_index = bp->igu_dsb_id; | |
5710 | igu_seg_id = IGU_SEG_ACCESS_DEF; | |
5711 | } | |
a2fbb9ea ET |
5712 | |
5713 | /* ATTN */ | |
523224a3 | 5714 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
a2fbb9ea | 5715 | atten_status_block); |
523224a3 | 5716 | def_sb->atten_status_block.status_block_id = igu_sp_sb_index; |
a2fbb9ea | 5717 | |
49d66772 ET |
5718 | bp->attn_state = 0; |
5719 | ||
a2fbb9ea ET |
5720 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
5721 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
f2eaeb58 DK |
5722 | reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : |
5723 | MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); | |
34f80b04 | 5724 | for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { |
523224a3 DK |
5725 | int sindex; |
5726 | /* take care of sig[0]..sig[4] */ | |
5727 | for (sindex = 0; sindex < 4; sindex++) | |
5728 | bp->attn_group[index].sig[sindex] = | |
5729 | REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); | |
f2e0899f | 5730 | |
619c5cb6 | 5731 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
5732 | /* |
5733 | * enable5 is separate from the rest of the registers, | |
5734 | * and therefore the address skip is 4 | |
5735 | * and not 16 between the different groups | |
5736 | */ | |
5737 | bp->attn_group[index].sig[4] = REG_RD(bp, | |
f2eaeb58 | 5738 | reg_offset_en5 + 0x4*index); |
f2e0899f DK |
5739 | else |
5740 | bp->attn_group[index].sig[4] = 0; | |
a2fbb9ea ET |
5741 | } |
5742 | ||
f2e0899f DK |
5743 | if (bp->common.int_block == INT_BLOCK_HC) { |
5744 | reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : | |
5745 | HC_REG_ATTN_MSG0_ADDR_L); | |
5746 | ||
5747 | REG_WR(bp, reg_offset, U64_LO(section)); | |
5748 | REG_WR(bp, reg_offset + 4, U64_HI(section)); | |
619c5cb6 | 5749 | } else if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5750 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); |
5751 | REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); | |
5752 | } | |
a2fbb9ea | 5753 | |
523224a3 DK |
5754 | section = ((u64)mapping) + offsetof(struct host_sp_status_block, |
5755 | sp_sb); | |
a2fbb9ea | 5756 | |
523224a3 | 5757 | bnx2x_zero_sp_sb(bp); |
a2fbb9ea | 5758 | |
86564c3f | 5759 | /* PCI guarantees endianity of regpairs */ |
619c5cb6 | 5760 | sp_sb_data.state = SB_ENABLED; |
523224a3 DK |
5761 | sp_sb_data.host_sb_addr.lo = U64_LO(section); |
5762 | sp_sb_data.host_sb_addr.hi = U64_HI(section); | |
5763 | sp_sb_data.igu_sb_id = igu_sp_sb_index; | |
5764 | sp_sb_data.igu_seg_id = igu_seg_id; | |
5765 | sp_sb_data.p_func.pf_id = func; | |
f2e0899f | 5766 | sp_sb_data.p_func.vnic_id = BP_VN(bp); |
523224a3 | 5767 | sp_sb_data.p_func.vf_id = 0xff; |
a2fbb9ea | 5768 | |
523224a3 | 5769 | bnx2x_wr_sp_sb_data(bp, &sp_sb_data); |
49d66772 | 5770 | |
523224a3 | 5771 | bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); |
a2fbb9ea ET |
5772 | } |
5773 | ||
9f6c9258 | 5774 | void bnx2x_update_coalesce(struct bnx2x *bp) |
a2fbb9ea | 5775 | { |
a2fbb9ea ET |
5776 | int i; |
5777 | ||
ec6ba945 | 5778 | for_each_eth_queue(bp, i) |
523224a3 | 5779 | bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, |
423cfa7e | 5780 | bp->tx_ticks, bp->rx_ticks); |
a2fbb9ea ET |
5781 | } |
5782 | ||
a2fbb9ea ET |
5783 | static void bnx2x_init_sp_ring(struct bnx2x *bp) |
5784 | { | |
a2fbb9ea | 5785 | spin_lock_init(&bp->spq_lock); |
6e30dd4e | 5786 | atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); |
a2fbb9ea | 5787 | |
a2fbb9ea | 5788 | bp->spq_prod_idx = 0; |
a2fbb9ea ET |
5789 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
5790 | bp->spq_prod_bd = bp->spq; | |
5791 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | |
a2fbb9ea ET |
5792 | } |
5793 | ||
523224a3 | 5794 | static void bnx2x_init_eq_ring(struct bnx2x *bp) |
a2fbb9ea ET |
5795 | { |
5796 | int i; | |
523224a3 DK |
5797 | for (i = 1; i <= NUM_EQ_PAGES; i++) { |
5798 | union event_ring_elem *elem = | |
5799 | &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; | |
a2fbb9ea | 5800 | |
523224a3 DK |
5801 | elem->next_page.addr.hi = |
5802 | cpu_to_le32(U64_HI(bp->eq_mapping + | |
5803 | BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); | |
5804 | elem->next_page.addr.lo = | |
5805 | cpu_to_le32(U64_LO(bp->eq_mapping + | |
5806 | BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); | |
a2fbb9ea | 5807 | } |
523224a3 DK |
5808 | bp->eq_cons = 0; |
5809 | bp->eq_prod = NUM_EQ_DESC; | |
5810 | bp->eq_cons_sb = BNX2X_EQ_INDEX; | |
16a5fd92 | 5811 | /* we want a warning message before it gets wrought... */ |
6e30dd4e VZ |
5812 | atomic_set(&bp->eq_spq_left, |
5813 | min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); | |
a2fbb9ea ET |
5814 | } |
5815 | ||
619c5cb6 | 5816 | /* called with netif_addr_lock_bh() */ |
924d75ab YM |
5817 | int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
5818 | unsigned long rx_mode_flags, | |
5819 | unsigned long rx_accept_flags, | |
5820 | unsigned long tx_accept_flags, | |
5821 | unsigned long ramrod_flags) | |
ab532cf3 | 5822 | { |
619c5cb6 VZ |
5823 | struct bnx2x_rx_mode_ramrod_params ramrod_param; |
5824 | int rc; | |
5825 | ||
5826 | memset(&ramrod_param, 0, sizeof(ramrod_param)); | |
5827 | ||
5828 | /* Prepare ramrod parameters */ | |
5829 | ramrod_param.cid = 0; | |
5830 | ramrod_param.cl_id = cl_id; | |
5831 | ramrod_param.rx_mode_obj = &bp->rx_mode_obj; | |
5832 | ramrod_param.func_id = BP_FUNC(bp); | |
ab532cf3 | 5833 | |
619c5cb6 VZ |
5834 | ramrod_param.pstate = &bp->sp_state; |
5835 | ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; | |
ab532cf3 | 5836 | |
619c5cb6 VZ |
5837 | ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); |
5838 | ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); | |
5839 | ||
5840 | set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); | |
5841 | ||
5842 | ramrod_param.ramrod_flags = ramrod_flags; | |
5843 | ramrod_param.rx_mode_flags = rx_mode_flags; | |
5844 | ||
5845 | ramrod_param.rx_accept_flags = rx_accept_flags; | |
5846 | ramrod_param.tx_accept_flags = tx_accept_flags; | |
5847 | ||
5848 | rc = bnx2x_config_rx_mode(bp, &ramrod_param); | |
5849 | if (rc < 0) { | |
5850 | BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); | |
924d75ab | 5851 | return rc; |
619c5cb6 | 5852 | } |
924d75ab YM |
5853 | |
5854 | return 0; | |
a2fbb9ea ET |
5855 | } |
5856 | ||
86564c3f YM |
5857 | static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, |
5858 | unsigned long *rx_accept_flags, | |
5859 | unsigned long *tx_accept_flags) | |
471de716 | 5860 | { |
924d75ab YM |
5861 | /* Clear the flags first */ |
5862 | *rx_accept_flags = 0; | |
5863 | *tx_accept_flags = 0; | |
619c5cb6 | 5864 | |
924d75ab | 5865 | switch (rx_mode) { |
619c5cb6 VZ |
5866 | case BNX2X_RX_MODE_NONE: |
5867 | /* | |
5868 | * 'drop all' supersedes any accept flags that may have been | |
5869 | * passed to the function. | |
5870 | */ | |
5871 | break; | |
5872 | case BNX2X_RX_MODE_NORMAL: | |
924d75ab YM |
5873 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
5874 | __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); | |
5875 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
5876 | |
5877 | /* internal switching mode */ | |
924d75ab YM |
5878 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
5879 | __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); | |
5880 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
5881 | |
5882 | break; | |
5883 | case BNX2X_RX_MODE_ALLMULTI: | |
924d75ab YM |
5884 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); |
5885 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
5886 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
5887 | |
5888 | /* internal switching mode */ | |
924d75ab YM |
5889 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
5890 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); | |
5891 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
5892 | |
5893 | break; | |
5894 | case BNX2X_RX_MODE_PROMISC: | |
16a5fd92 | 5895 | /* According to definition of SI mode, iface in promisc mode |
619c5cb6 VZ |
5896 | * should receive matched and unmatched (in resolution of port) |
5897 | * unicast packets. | |
5898 | */ | |
924d75ab YM |
5899 | __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); |
5900 | __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); | |
5901 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); | |
5902 | __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); | |
619c5cb6 VZ |
5903 | |
5904 | /* internal switching mode */ | |
924d75ab YM |
5905 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); |
5906 | __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); | |
619c5cb6 VZ |
5907 | |
5908 | if (IS_MF_SI(bp)) | |
924d75ab | 5909 | __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); |
619c5cb6 | 5910 | else |
924d75ab | 5911 | __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); |
619c5cb6 VZ |
5912 | |
5913 | break; | |
5914 | default: | |
924d75ab YM |
5915 | BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); |
5916 | return -EINVAL; | |
619c5cb6 | 5917 | } |
de832a55 | 5918 | |
924d75ab | 5919 | /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ |
619c5cb6 | 5920 | if (bp->rx_mode != BNX2X_RX_MODE_NONE) { |
924d75ab YM |
5921 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); |
5922 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); | |
34f80b04 EG |
5923 | } |
5924 | ||
924d75ab YM |
5925 | return 0; |
5926 | } | |
5927 | ||
5928 | /* called with netif_addr_lock_bh() */ | |
5929 | int bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |
5930 | { | |
5931 | unsigned long rx_mode_flags = 0, ramrod_flags = 0; | |
5932 | unsigned long rx_accept_flags = 0, tx_accept_flags = 0; | |
5933 | int rc; | |
5934 | ||
5935 | if (!NO_FCOE(bp)) | |
5936 | /* Configure rx_mode of FCoE Queue */ | |
5937 | __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); | |
5938 | ||
5939 | rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, | |
5940 | &tx_accept_flags); | |
5941 | if (rc) | |
5942 | return rc; | |
5943 | ||
619c5cb6 VZ |
5944 | __set_bit(RAMROD_RX, &ramrod_flags); |
5945 | __set_bit(RAMROD_TX, &ramrod_flags); | |
5946 | ||
924d75ab YM |
5947 | return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, |
5948 | rx_accept_flags, tx_accept_flags, | |
5949 | ramrod_flags); | |
619c5cb6 VZ |
5950 | } |
5951 | ||
5952 | static void bnx2x_init_internal_common(struct bnx2x *bp) | |
5953 | { | |
5954 | int i; | |
5955 | ||
0793f83f DK |
5956 | if (IS_MF_SI(bp)) |
5957 | /* | |
5958 | * In switch independent mode, the TSTORM needs to accept | |
5959 | * packets that failed classification, since approximate match | |
5960 | * mac addresses aren't written to NIG LLH | |
5961 | */ | |
5962 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5963 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2); | |
619c5cb6 VZ |
5964 | else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */ |
5965 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
5966 | TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0); | |
0793f83f | 5967 | |
523224a3 DK |
5968 | /* Zero this manually as its initialization is |
5969 | currently missing in the initTool */ | |
5970 | for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) | |
ca00392c | 5971 | REG_WR(bp, BAR_USTRORM_INTMEM + |
523224a3 | 5972 | USTORM_AGG_DATA_OFFSET + i * 4, 0); |
619c5cb6 | 5973 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
5974 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, |
5975 | CHIP_INT_MODE_IS_BC(bp) ? | |
5976 | HC_IGU_BC_MODE : HC_IGU_NBC_MODE); | |
5977 | } | |
523224a3 | 5978 | } |
8a1c38d1 | 5979 | |
471de716 EG |
5980 | static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) |
5981 | { | |
5982 | switch (load_code) { | |
5983 | case FW_MSG_CODE_DRV_LOAD_COMMON: | |
f2e0899f | 5984 | case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: |
471de716 EG |
5985 | bnx2x_init_internal_common(bp); |
5986 | /* no break */ | |
5987 | ||
5988 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
619c5cb6 | 5989 | /* nothing to do */ |
471de716 EG |
5990 | /* no break */ |
5991 | ||
5992 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
523224a3 DK |
5993 | /* internal memory per function is |
5994 | initialized inside bnx2x_pf_init */ | |
471de716 EG |
5995 | break; |
5996 | ||
5997 | default: | |
5998 | BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); | |
5999 | break; | |
6000 | } | |
6001 | } | |
6002 | ||
619c5cb6 | 6003 | static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) |
523224a3 | 6004 | { |
55c11941 | 6005 | return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 | 6006 | } |
523224a3 | 6007 | |
619c5cb6 VZ |
6008 | static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) |
6009 | { | |
55c11941 | 6010 | return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); |
619c5cb6 VZ |
6011 | } |
6012 | ||
1191cb83 | 6013 | static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) |
619c5cb6 VZ |
6014 | { |
6015 | if (CHIP_IS_E1x(fp->bp)) | |
6016 | return BP_L_ID(fp->bp) + fp->index; | |
6017 | else /* We want Client ID to be the same as IGU SB ID for 57712 */ | |
6018 | return bnx2x_fp_igu_sb_id(fp); | |
6019 | } | |
6020 | ||
6383c0b3 | 6021 | static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) |
619c5cb6 VZ |
6022 | { |
6023 | struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; | |
6383c0b3 | 6024 | u8 cos; |
619c5cb6 | 6025 | unsigned long q_type = 0; |
6383c0b3 | 6026 | u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; |
f233cafe | 6027 | fp->rx_queue = fp_idx; |
b3b83c3f | 6028 | fp->cid = fp_idx; |
619c5cb6 VZ |
6029 | fp->cl_id = bnx2x_fp_cl_id(fp); |
6030 | fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); | |
6031 | fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); | |
523224a3 | 6032 | /* qZone id equals to FW (per path) client id */ |
619c5cb6 VZ |
6033 | fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); |
6034 | ||
523224a3 | 6035 | /* init shortcut */ |
619c5cb6 | 6036 | fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); |
7a752993 | 6037 | |
16a5fd92 | 6038 | /* Setup SB indices */ |
523224a3 | 6039 | fp->rx_cons_sb = BNX2X_RX_SB_INDEX; |
523224a3 | 6040 | |
619c5cb6 VZ |
6041 | /* Configure Queue State object */ |
6042 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
6043 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
6383c0b3 AE |
6044 | |
6045 | BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); | |
6046 | ||
6047 | /* init tx data */ | |
6048 | for_each_cos_in_tx_queue(fp, cos) { | |
65565884 MS |
6049 | bnx2x_init_txdata(bp, fp->txdata_ptr[cos], |
6050 | CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), | |
6051 | FP_COS_TO_TXQ(fp, cos, bp), | |
6052 | BNX2X_TX_SB_INDEX_BASE + cos, fp); | |
6053 | cids[cos] = fp->txdata_ptr[cos]->cid; | |
6383c0b3 AE |
6054 | } |
6055 | ||
ad5afc89 AE |
6056 | /* nothing more for vf to do here */ |
6057 | if (IS_VF(bp)) | |
6058 | return; | |
6059 | ||
6060 | bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, | |
6061 | fp->fw_sb_id, fp->igu_sb_id); | |
6062 | bnx2x_update_fpsb_idx(fp); | |
15192a8c BW |
6063 | bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, |
6064 | fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), | |
6383c0b3 | 6065 | bnx2x_sp_mapping(bp, q_rdata), q_type); |
619c5cb6 VZ |
6066 | |
6067 | /** | |
6068 | * Configure classification DBs: Always enable Tx switching | |
6069 | */ | |
6070 | bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); | |
6071 | ||
ad5afc89 AE |
6072 | DP(NETIF_MSG_IFUP, |
6073 | "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", | |
6074 | fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
6075 | fp->igu_sb_id); | |
523224a3 DK |
6076 | } |
6077 | ||
1191cb83 ED |
6078 | static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) |
6079 | { | |
6080 | int i; | |
6081 | ||
6082 | for (i = 1; i <= NUM_TX_RINGS; i++) { | |
6083 | struct eth_tx_next_bd *tx_next_bd = | |
6084 | &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
6085 | ||
6086 | tx_next_bd->addr_hi = | |
6087 | cpu_to_le32(U64_HI(txdata->tx_desc_mapping + | |
6088 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6089 | tx_next_bd->addr_lo = | |
6090 | cpu_to_le32(U64_LO(txdata->tx_desc_mapping + | |
6091 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
6092 | } | |
6093 | ||
639d65b8 YM |
6094 | *txdata->tx_cons_sb = cpu_to_le16(0); |
6095 | ||
1191cb83 ED |
6096 | SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
6097 | txdata->tx_db.data.zero_fill1 = 0; | |
6098 | txdata->tx_db.data.prod = 0; | |
6099 | ||
6100 | txdata->tx_pkt_prod = 0; | |
6101 | txdata->tx_pkt_cons = 0; | |
6102 | txdata->tx_bd_prod = 0; | |
6103 | txdata->tx_bd_cons = 0; | |
6104 | txdata->tx_pkt = 0; | |
6105 | } | |
6106 | ||
55c11941 MS |
6107 | static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) |
6108 | { | |
6109 | int i; | |
6110 | ||
6111 | for_each_tx_queue_cnic(bp, i) | |
6112 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); | |
6113 | } | |
d76a6111 | 6114 | |
1191cb83 ED |
6115 | static void bnx2x_init_tx_rings(struct bnx2x *bp) |
6116 | { | |
6117 | int i; | |
6118 | u8 cos; | |
6119 | ||
55c11941 | 6120 | for_each_eth_queue(bp, i) |
1191cb83 | 6121 | for_each_cos_in_tx_queue(&bp->fp[i], cos) |
65565884 | 6122 | bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); |
1191cb83 ED |
6123 | } |
6124 | ||
55c11941 | 6125 | void bnx2x_nic_init_cnic(struct bnx2x *bp) |
a2fbb9ea | 6126 | { |
ec6ba945 VZ |
6127 | if (!NO_FCOE(bp)) |
6128 | bnx2x_init_fcoe_fp(bp); | |
523224a3 DK |
6129 | |
6130 | bnx2x_init_sb(bp, bp->cnic_sb_mapping, | |
6131 | BNX2X_VF_ID_INVALID, false, | |
619c5cb6 | 6132 | bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); |
523224a3 | 6133 | |
55c11941 MS |
6134 | /* ensure status block indices were read */ |
6135 | rmb(); | |
6136 | bnx2x_init_rx_rings_cnic(bp); | |
6137 | bnx2x_init_tx_rings_cnic(bp); | |
6138 | ||
6139 | /* flush all */ | |
6140 | mb(); | |
6141 | mmiowb(); | |
6142 | } | |
a2fbb9ea | 6143 | |
ecf01c22 | 6144 | void bnx2x_pre_irq_nic_init(struct bnx2x *bp) |
55c11941 MS |
6145 | { |
6146 | int i; | |
6147 | ||
ecf01c22 | 6148 | /* Setup NIC internals and enable interrupts */ |
55c11941 MS |
6149 | for_each_eth_queue(bp, i) |
6150 | bnx2x_init_eth_fp(bp, i); | |
ad5afc89 AE |
6151 | |
6152 | /* ensure status block indices were read */ | |
6153 | rmb(); | |
6154 | bnx2x_init_rx_rings(bp); | |
6155 | bnx2x_init_tx_rings(bp); | |
6156 | ||
ecf01c22 YM |
6157 | if (IS_PF(bp)) { |
6158 | /* Initialize MOD_ABS interrupts */ | |
6159 | bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, | |
6160 | bp->common.shmem_base, | |
6161 | bp->common.shmem2_base, BP_PORT(bp)); | |
ad5afc89 | 6162 | |
ecf01c22 YM |
6163 | /* initialize the default status block and sp ring */ |
6164 | bnx2x_init_def_sb(bp); | |
6165 | bnx2x_update_dsb_idx(bp); | |
6166 | bnx2x_init_sp_ring(bp); | |
3cdeec22 YM |
6167 | } else { |
6168 | bnx2x_memset_stats(bp); | |
ecf01c22 YM |
6169 | } |
6170 | } | |
16119785 | 6171 | |
ecf01c22 YM |
6172 | void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) |
6173 | { | |
523224a3 | 6174 | bnx2x_init_eq_ring(bp); |
471de716 | 6175 | bnx2x_init_internal(bp, load_code); |
523224a3 | 6176 | bnx2x_pf_init(bp); |
0ef00459 EG |
6177 | bnx2x_stats_init(bp); |
6178 | ||
0ef00459 EG |
6179 | /* flush all before enabling interrupts */ |
6180 | mb(); | |
6181 | mmiowb(); | |
6182 | ||
615f8fd9 | 6183 | bnx2x_int_enable(bp); |
eb8da205 EG |
6184 | |
6185 | /* Check for SPIO5 */ | |
6186 | bnx2x_attn_int_deasserted0(bp, | |
6187 | REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & | |
6188 | AEU_INPUTS_ATTN_BITS_SPIO5); | |
a2fbb9ea ET |
6189 | } |
6190 | ||
ecf01c22 | 6191 | /* gzip service functions */ |
a2fbb9ea ET |
6192 | static int bnx2x_gunzip_init(struct bnx2x *bp) |
6193 | { | |
1a983142 FT |
6194 | bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, |
6195 | &bp->gunzip_mapping, GFP_KERNEL); | |
a2fbb9ea ET |
6196 | if (bp->gunzip_buf == NULL) |
6197 | goto gunzip_nomem1; | |
6198 | ||
6199 | bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); | |
6200 | if (bp->strm == NULL) | |
6201 | goto gunzip_nomem2; | |
6202 | ||
7ab24bfd | 6203 | bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); |
a2fbb9ea ET |
6204 | if (bp->strm->workspace == NULL) |
6205 | goto gunzip_nomem3; | |
6206 | ||
6207 | return 0; | |
6208 | ||
6209 | gunzip_nomem3: | |
6210 | kfree(bp->strm); | |
6211 | bp->strm = NULL; | |
6212 | ||
6213 | gunzip_nomem2: | |
1a983142 FT |
6214 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6215 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6216 | bp->gunzip_buf = NULL; |
6217 | ||
6218 | gunzip_nomem1: | |
51c1a580 | 6219 | BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); |
a2fbb9ea ET |
6220 | return -ENOMEM; |
6221 | } | |
6222 | ||
6223 | static void bnx2x_gunzip_end(struct bnx2x *bp) | |
6224 | { | |
b3b83c3f | 6225 | if (bp->strm) { |
7ab24bfd | 6226 | vfree(bp->strm->workspace); |
b3b83c3f DK |
6227 | kfree(bp->strm); |
6228 | bp->strm = NULL; | |
6229 | } | |
a2fbb9ea ET |
6230 | |
6231 | if (bp->gunzip_buf) { | |
1a983142 FT |
6232 | dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, |
6233 | bp->gunzip_mapping); | |
a2fbb9ea ET |
6234 | bp->gunzip_buf = NULL; |
6235 | } | |
6236 | } | |
6237 | ||
94a78b79 | 6238 | static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) |
a2fbb9ea ET |
6239 | { |
6240 | int n, rc; | |
6241 | ||
6242 | /* check gzip header */ | |
94a78b79 VZ |
6243 | if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { |
6244 | BNX2X_ERR("Bad gzip header\n"); | |
a2fbb9ea | 6245 | return -EINVAL; |
94a78b79 | 6246 | } |
a2fbb9ea ET |
6247 | |
6248 | n = 10; | |
6249 | ||
34f80b04 | 6250 | #define FNAME 0x8 |
a2fbb9ea ET |
6251 | |
6252 | if (zbuf[3] & FNAME) | |
6253 | while ((zbuf[n++] != 0) && (n < len)); | |
6254 | ||
94a78b79 | 6255 | bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; |
a2fbb9ea ET |
6256 | bp->strm->avail_in = len - n; |
6257 | bp->strm->next_out = bp->gunzip_buf; | |
6258 | bp->strm->avail_out = FW_BUF_SIZE; | |
6259 | ||
6260 | rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); | |
6261 | if (rc != Z_OK) | |
6262 | return rc; | |
6263 | ||
6264 | rc = zlib_inflate(bp->strm, Z_FINISH); | |
6265 | if ((rc != Z_OK) && (rc != Z_STREAM_END)) | |
7995c64e JP |
6266 | netdev_err(bp->dev, "Firmware decompression error: %s\n", |
6267 | bp->strm->msg); | |
a2fbb9ea ET |
6268 | |
6269 | bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); | |
6270 | if (bp->gunzip_outlen & 0x3) | |
51c1a580 MS |
6271 | netdev_err(bp->dev, |
6272 | "Firmware decompression error: gunzip_outlen (%d) not aligned\n", | |
cdaa7cb8 | 6273 | bp->gunzip_outlen); |
a2fbb9ea ET |
6274 | bp->gunzip_outlen >>= 2; |
6275 | ||
6276 | zlib_inflateEnd(bp->strm); | |
6277 | ||
6278 | if (rc == Z_STREAM_END) | |
6279 | return 0; | |
6280 | ||
6281 | return rc; | |
6282 | } | |
6283 | ||
6284 | /* nic load/unload */ | |
6285 | ||
6286 | /* | |
34f80b04 | 6287 | * General service functions |
a2fbb9ea ET |
6288 | */ |
6289 | ||
6290 | /* send a NIG loopback debug packet */ | |
6291 | static void bnx2x_lb_pckt(struct bnx2x *bp) | |
6292 | { | |
a2fbb9ea | 6293 | u32 wb_write[3]; |
a2fbb9ea ET |
6294 | |
6295 | /* Ethernet source and destination addresses */ | |
a2fbb9ea ET |
6296 | wb_write[0] = 0x55555555; |
6297 | wb_write[1] = 0x55555555; | |
34f80b04 | 6298 | wb_write[2] = 0x20; /* SOP */ |
a2fbb9ea | 6299 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6300 | |
6301 | /* NON-IP protocol */ | |
a2fbb9ea ET |
6302 | wb_write[0] = 0x09000000; |
6303 | wb_write[1] = 0x55555555; | |
34f80b04 | 6304 | wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ |
a2fbb9ea | 6305 | REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); |
a2fbb9ea ET |
6306 | } |
6307 | ||
6308 | /* some of the internal memories | |
6309 | * are not directly readable from the driver | |
6310 | * to test them we send debug packets | |
6311 | */ | |
6312 | static int bnx2x_int_mem_test(struct bnx2x *bp) | |
6313 | { | |
6314 | int factor; | |
6315 | int count, i; | |
6316 | u32 val = 0; | |
6317 | ||
ad8d3948 | 6318 | if (CHIP_REV_IS_FPGA(bp)) |
a2fbb9ea | 6319 | factor = 120; |
ad8d3948 EG |
6320 | else if (CHIP_REV_IS_EMUL(bp)) |
6321 | factor = 200; | |
6322 | else | |
a2fbb9ea | 6323 | factor = 1; |
a2fbb9ea | 6324 | |
a2fbb9ea ET |
6325 | /* Disable inputs of parser neighbor blocks */ |
6326 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6327 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6328 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6329 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6330 | |
6331 | /* Write 0 to parser credits for CFC search request */ | |
6332 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6333 | ||
6334 | /* send Ethernet packet */ | |
6335 | bnx2x_lb_pckt(bp); | |
6336 | ||
6337 | /* TODO do i reset NIG statistic? */ | |
6338 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6339 | count = 1000 * factor; | |
6340 | while (count) { | |
34f80b04 | 6341 | |
a2fbb9ea ET |
6342 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6343 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6344 | if (val == 0x10) |
6345 | break; | |
6346 | ||
639d65b8 | 6347 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6348 | count--; |
6349 | } | |
6350 | if (val != 0x10) { | |
6351 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6352 | return -1; | |
6353 | } | |
6354 | ||
6355 | /* Wait until PRS register shows 1 packet */ | |
6356 | count = 1000 * factor; | |
6357 | while (count) { | |
6358 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
a2fbb9ea ET |
6359 | if (val == 1) |
6360 | break; | |
6361 | ||
639d65b8 | 6362 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6363 | count--; |
6364 | } | |
6365 | if (val != 0x1) { | |
6366 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6367 | return -2; | |
6368 | } | |
6369 | ||
6370 | /* Reset and init BRB, PRS */ | |
34f80b04 | 6371 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); |
a2fbb9ea | 6372 | msleep(50); |
34f80b04 | 6373 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); |
a2fbb9ea | 6374 | msleep(50); |
619c5cb6 VZ |
6375 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6376 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
a2fbb9ea ET |
6377 | |
6378 | DP(NETIF_MSG_HW, "part2\n"); | |
6379 | ||
6380 | /* Disable inputs of parser neighbor blocks */ | |
6381 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); | |
6382 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); | |
6383 | REG_WR(bp, CFC_REG_DEBUG0, 0x1); | |
3196a88a | 6384 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); |
a2fbb9ea ET |
6385 | |
6386 | /* Write 0 to parser credits for CFC search request */ | |
6387 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); | |
6388 | ||
6389 | /* send 10 Ethernet packets */ | |
6390 | for (i = 0; i < 10; i++) | |
6391 | bnx2x_lb_pckt(bp); | |
6392 | ||
6393 | /* Wait until NIG register shows 10 + 1 | |
6394 | packets of size 11*0x10 = 0xb0 */ | |
6395 | count = 1000 * factor; | |
6396 | while (count) { | |
34f80b04 | 6397 | |
a2fbb9ea ET |
6398 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); |
6399 | val = *bnx2x_sp(bp, wb_data[0]); | |
a2fbb9ea ET |
6400 | if (val == 0xb0) |
6401 | break; | |
6402 | ||
639d65b8 | 6403 | usleep_range(10000, 20000); |
a2fbb9ea ET |
6404 | count--; |
6405 | } | |
6406 | if (val != 0xb0) { | |
6407 | BNX2X_ERR("NIG timeout val = 0x%x\n", val); | |
6408 | return -3; | |
6409 | } | |
6410 | ||
6411 | /* Wait until PRS register shows 2 packets */ | |
6412 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6413 | if (val != 2) | |
6414 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6415 | ||
6416 | /* Write 1 to parser credits for CFC search request */ | |
6417 | REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); | |
6418 | ||
6419 | /* Wait until PRS register shows 3 packets */ | |
6420 | msleep(10 * factor); | |
6421 | /* Wait until NIG register shows 1 packet of size 0x10 */ | |
6422 | val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); | |
6423 | if (val != 3) | |
6424 | BNX2X_ERR("PRS timeout val = 0x%x\n", val); | |
6425 | ||
6426 | /* clear NIG EOP FIFO */ | |
6427 | for (i = 0; i < 11; i++) | |
6428 | REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); | |
6429 | val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); | |
6430 | if (val != 1) { | |
6431 | BNX2X_ERR("clear of NIG failed\n"); | |
6432 | return -4; | |
6433 | } | |
6434 | ||
6435 | /* Reset and init BRB, PRS, NIG */ | |
6436 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); | |
6437 | msleep(50); | |
6438 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); | |
6439 | msleep(50); | |
619c5cb6 VZ |
6440 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
6441 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); | |
55c11941 MS |
6442 | if (!CNIC_SUPPORT(bp)) |
6443 | /* set NIC mode */ | |
6444 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
a2fbb9ea ET |
6445 | |
6446 | /* Enable inputs of parser neighbor blocks */ | |
6447 | REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); | |
6448 | REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); | |
6449 | REG_WR(bp, CFC_REG_DEBUG0, 0x0); | |
3196a88a | 6450 | REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); |
a2fbb9ea ET |
6451 | |
6452 | DP(NETIF_MSG_HW, "done\n"); | |
6453 | ||
6454 | return 0; /* OK */ | |
6455 | } | |
6456 | ||
4a33bc03 | 6457 | static void bnx2x_enable_blocks_attention(struct bnx2x *bp) |
a2fbb9ea | 6458 | { |
b343d002 YM |
6459 | u32 val; |
6460 | ||
a2fbb9ea | 6461 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); |
619c5cb6 | 6462 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
6463 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); |
6464 | else | |
6465 | REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); | |
a2fbb9ea ET |
6466 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); |
6467 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
f2e0899f DK |
6468 | /* |
6469 | * mask read length error interrupts in brb for parser | |
6470 | * (parsing unit and 'checksum and crc' unit) | |
6471 | * these errors are legal (PU reads fixed length and CAC can cause | |
6472 | * read length error on truncated packets) | |
6473 | */ | |
6474 | REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); | |
a2fbb9ea ET |
6475 | REG_WR(bp, QM_REG_QM_INT_MASK, 0); |
6476 | REG_WR(bp, TM_REG_TM_INT_MASK, 0); | |
6477 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); | |
6478 | REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); | |
6479 | REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); | |
34f80b04 EG |
6480 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ |
6481 | /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6482 | REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); |
6483 | REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); | |
6484 | REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); | |
34f80b04 EG |
6485 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ |
6486 | /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ | |
a2fbb9ea ET |
6487 | REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); |
6488 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); | |
6489 | REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); | |
6490 | REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); | |
34f80b04 EG |
6491 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ |
6492 | /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ | |
f85582f8 | 6493 | |
b343d002 YM |
6494 | val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | |
6495 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | | |
6496 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; | |
6497 | if (!CHIP_IS_E1x(bp)) | |
6498 | val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | | |
6499 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; | |
6500 | REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); | |
6501 | ||
a2fbb9ea ET |
6502 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); |
6503 | REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); | |
6504 | REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); | |
34f80b04 | 6505 | /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ |
619c5cb6 VZ |
6506 | |
6507 | if (!CHIP_IS_E1x(bp)) | |
6508 | /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ | |
6509 | REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); | |
6510 | ||
a2fbb9ea ET |
6511 | REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); |
6512 | REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); | |
34f80b04 | 6513 | /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ |
4a33bc03 | 6514 | REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ |
a2fbb9ea ET |
6515 | } |
6516 | ||
81f75bbf EG |
6517 | static void bnx2x_reset_common(struct bnx2x *bp) |
6518 | { | |
619c5cb6 VZ |
6519 | u32 val = 0x1400; |
6520 | ||
81f75bbf EG |
6521 | /* reset_common */ |
6522 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6523 | 0xd3ffff7f); | |
619c5cb6 VZ |
6524 | |
6525 | if (CHIP_IS_E3(bp)) { | |
6526 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6527 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6528 | } | |
6529 | ||
6530 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); | |
6531 | } | |
6532 | ||
6533 | static void bnx2x_setup_dmae(struct bnx2x *bp) | |
6534 | { | |
6535 | bp->dmae_ready = 0; | |
6536 | spin_lock_init(&bp->dmae_lock); | |
81f75bbf EG |
6537 | } |
6538 | ||
573f2035 EG |
6539 | static void bnx2x_init_pxp(struct bnx2x *bp) |
6540 | { | |
6541 | u16 devctl; | |
6542 | int r_order, w_order; | |
6543 | ||
2a80eebc | 6544 | pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); |
573f2035 EG |
6545 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); |
6546 | w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | |
6547 | if (bp->mrrs == -1) | |
6548 | r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
6549 | else { | |
6550 | DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); | |
6551 | r_order = bp->mrrs; | |
6552 | } | |
6553 | ||
6554 | bnx2x_init_pxp_arb(bp, r_order, w_order); | |
6555 | } | |
fd4ef40d EG |
6556 | |
6557 | static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) | |
6558 | { | |
2145a920 | 6559 | int is_required; |
fd4ef40d | 6560 | u32 val; |
2145a920 | 6561 | int port; |
fd4ef40d | 6562 | |
2145a920 VZ |
6563 | if (BP_NOMCP(bp)) |
6564 | return; | |
6565 | ||
6566 | is_required = 0; | |
fd4ef40d EG |
6567 | val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & |
6568 | SHARED_HW_CFG_FAN_FAILURE_MASK; | |
6569 | ||
6570 | if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) | |
6571 | is_required = 1; | |
6572 | ||
6573 | /* | |
6574 | * The fan failure mechanism is usually related to the PHY type since | |
6575 | * the power consumption of the board is affected by the PHY. Currently, | |
6576 | * fan is required for most designs with SFX7101, BCM8727 and BCM8481. | |
6577 | */ | |
6578 | else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) | |
6579 | for (port = PORT_0; port < PORT_MAX; port++) { | |
fd4ef40d | 6580 | is_required |= |
d90d96ba YR |
6581 | bnx2x_fan_failure_det_req( |
6582 | bp, | |
6583 | bp->common.shmem_base, | |
a22f0788 | 6584 | bp->common.shmem2_base, |
d90d96ba | 6585 | port); |
fd4ef40d EG |
6586 | } |
6587 | ||
6588 | DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); | |
6589 | ||
6590 | if (is_required == 0) | |
6591 | return; | |
6592 | ||
6593 | /* Fan failure is indicated by SPIO 5 */ | |
d6d99a3f | 6594 | bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); |
fd4ef40d EG |
6595 | |
6596 | /* set to active low mode */ | |
6597 | val = REG_RD(bp, MISC_REG_SPIO_INT); | |
d6d99a3f | 6598 | val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); |
fd4ef40d EG |
6599 | REG_WR(bp, MISC_REG_SPIO_INT, val); |
6600 | ||
6601 | /* enable interrupt to signal the IGU */ | |
6602 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 6603 | val |= MISC_SPIO_SPIO5; |
fd4ef40d EG |
6604 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); |
6605 | } | |
6606 | ||
c9ee9206 | 6607 | void bnx2x_pf_disable(struct bnx2x *bp) |
f2e0899f DK |
6608 | { |
6609 | u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); | |
6610 | val &= ~IGU_PF_CONF_FUNC_EN; | |
6611 | ||
6612 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); | |
6613 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6614 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); | |
6615 | } | |
6616 | ||
1191cb83 | 6617 | static void bnx2x__common_init_phy(struct bnx2x *bp) |
619c5cb6 VZ |
6618 | { |
6619 | u32 shmem_base[2], shmem2_base[2]; | |
b884d95b YR |
6620 | /* Avoid common init in case MFW supports LFA */ |
6621 | if (SHMEM2_RD(bp, size) > | |
6622 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
6623 | return; | |
619c5cb6 VZ |
6624 | shmem_base[0] = bp->common.shmem_base; |
6625 | shmem2_base[0] = bp->common.shmem2_base; | |
6626 | if (!CHIP_IS_E1x(bp)) { | |
6627 | shmem_base[1] = | |
6628 | SHMEM2_RD(bp, other_shmem_base_addr); | |
6629 | shmem2_base[1] = | |
6630 | SHMEM2_RD(bp, other_shmem2_base_addr); | |
6631 | } | |
6632 | bnx2x_acquire_phy_lock(bp); | |
6633 | bnx2x_common_init_phy(bp, shmem_base, shmem2_base, | |
6634 | bp->common.chip_id); | |
6635 | bnx2x_release_phy_lock(bp); | |
6636 | } | |
6637 | ||
6638 | /** | |
6639 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | |
6640 | * | |
6641 | * @bp: driver handle | |
6642 | */ | |
6643 | static int bnx2x_init_hw_common(struct bnx2x *bp) | |
a2fbb9ea | 6644 | { |
619c5cb6 | 6645 | u32 val; |
a2fbb9ea | 6646 | |
51c1a580 | 6647 | DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); |
a2fbb9ea | 6648 | |
2031bd3a | 6649 | /* |
2de67439 | 6650 | * take the RESET lock to protect undi_unload flow from accessing |
2031bd3a DK |
6651 | * registers while we're resetting the chip |
6652 | */ | |
7a06a122 | 6653 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6654 | |
81f75bbf | 6655 | bnx2x_reset_common(bp); |
34f80b04 | 6656 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
a2fbb9ea | 6657 | |
619c5cb6 VZ |
6658 | val = 0xfffc; |
6659 | if (CHIP_IS_E3(bp)) { | |
6660 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; | |
6661 | val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; | |
6662 | } | |
6663 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | |
6664 | ||
7a06a122 | 6665 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
2031bd3a | 6666 | |
619c5cb6 | 6667 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
a2fbb9ea | 6668 | |
619c5cb6 VZ |
6669 | if (!CHIP_IS_E1x(bp)) { |
6670 | u8 abs_func_id; | |
f2e0899f DK |
6671 | |
6672 | /** | |
6673 | * 4-port mode or 2-port mode we need to turn of master-enable | |
6674 | * for everyone, after that, turn it back on for self. | |
6675 | * so, we disregard multi-function or not, and always disable | |
6676 | * for all functions on the given path, this means 0,2,4,6 for | |
6677 | * path 0 and 1,3,5,7 for path 1 | |
6678 | */ | |
619c5cb6 VZ |
6679 | for (abs_func_id = BP_PATH(bp); |
6680 | abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { | |
6681 | if (abs_func_id == BP_ABS_FUNC(bp)) { | |
f2e0899f DK |
6682 | REG_WR(bp, |
6683 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, | |
6684 | 1); | |
6685 | continue; | |
6686 | } | |
6687 | ||
619c5cb6 | 6688 | bnx2x_pretend_func(bp, abs_func_id); |
f2e0899f DK |
6689 | /* clear pf enable */ |
6690 | bnx2x_pf_disable(bp); | |
6691 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6692 | } | |
6693 | } | |
a2fbb9ea | 6694 | |
619c5cb6 | 6695 | bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); |
34f80b04 EG |
6696 | if (CHIP_IS_E1(bp)) { |
6697 | /* enable HW interrupt from PXP on USDM overflow | |
6698 | bit 16 on INT_MASK_0 */ | |
6699 | REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); | |
6700 | } | |
a2fbb9ea | 6701 | |
619c5cb6 | 6702 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
34f80b04 | 6703 | bnx2x_init_pxp(bp); |
a2fbb9ea ET |
6704 | |
6705 | #ifdef __BIG_ENDIAN | |
34f80b04 EG |
6706 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); |
6707 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | |
6708 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | |
6709 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | |
6710 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | |
8badd27a EG |
6711 | /* make sure this value is 0 */ |
6712 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | |
34f80b04 EG |
6713 | |
6714 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | |
6715 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | |
6716 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | |
6717 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | |
6718 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | |
a2fbb9ea ET |
6719 | #endif |
6720 | ||
523224a3 DK |
6721 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
6722 | ||
34f80b04 EG |
6723 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
6724 | REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); | |
a2fbb9ea | 6725 | |
34f80b04 EG |
6726 | /* let the HW do it's magic ... */ |
6727 | msleep(100); | |
6728 | /* finish PXP init */ | |
6729 | val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); | |
6730 | if (val != 1) { | |
6731 | BNX2X_ERR("PXP2 CFG failed\n"); | |
6732 | return -EBUSY; | |
6733 | } | |
6734 | val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); | |
6735 | if (val != 1) { | |
6736 | BNX2X_ERR("PXP2 RD_INIT failed\n"); | |
6737 | return -EBUSY; | |
6738 | } | |
a2fbb9ea | 6739 | |
f2e0899f DK |
6740 | /* Timers bug workaround E2 only. We need to set the entire ILT to |
6741 | * have entries with value "0" and valid bit on. | |
6742 | * This needs to be done by the first PF that is loaded in a path | |
6743 | * (i.e. common phase) | |
6744 | */ | |
619c5cb6 VZ |
6745 | if (!CHIP_IS_E1x(bp)) { |
6746 | /* In E2 there is a bug in the timers block that can cause function 6 / 7 | |
6747 | * (i.e. vnic3) to start even if it is marked as "scan-off". | |
6748 | * This occurs when a different function (func2,3) is being marked | |
6749 | * as "scan-off". Real-life scenario for example: if a driver is being | |
6750 | * load-unloaded while func6,7 are down. This will cause the timer to access | |
6751 | * the ilt, translate to a logical address and send a request to read/write. | |
6752 | * Since the ilt for the function that is down is not valid, this will cause | |
6753 | * a translation error which is unrecoverable. | |
6754 | * The Workaround is intended to make sure that when this happens nothing fatal | |
6755 | * will occur. The workaround: | |
6756 | * 1. First PF driver which loads on a path will: | |
6757 | * a. After taking the chip out of reset, by using pretend, | |
6758 | * it will write "0" to the following registers of | |
6759 | * the other vnics. | |
6760 | * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
6761 | * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); | |
6762 | * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); | |
6763 | * And for itself it will write '1' to | |
6764 | * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable | |
6765 | * dmae-operations (writing to pram for example.) | |
6766 | * note: can be done for only function 6,7 but cleaner this | |
6767 | * way. | |
6768 | * b. Write zero+valid to the entire ILT. | |
6769 | * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of | |
6770 | * VNIC3 (of that port). The range allocated will be the | |
6771 | * entire ILT. This is needed to prevent ILT range error. | |
6772 | * 2. Any PF driver load flow: | |
6773 | * a. ILT update with the physical addresses of the allocated | |
6774 | * logical pages. | |
6775 | * b. Wait 20msec. - note that this timeout is needed to make | |
6776 | * sure there are no requests in one of the PXP internal | |
6777 | * queues with "old" ILT addresses. | |
6778 | * c. PF enable in the PGLC. | |
6779 | * d. Clear the was_error of the PF in the PGLC. (could have | |
2de67439 | 6780 | * occurred while driver was down) |
619c5cb6 VZ |
6781 | * e. PF enable in the CFC (WEAK + STRONG) |
6782 | * f. Timers scan enable | |
6783 | * 3. PF driver unload flow: | |
6784 | * a. Clear the Timers scan_en. | |
6785 | * b. Polling for scan_on=0 for that PF. | |
6786 | * c. Clear the PF enable bit in the PXP. | |
6787 | * d. Clear the PF enable in the CFC (WEAK + STRONG) | |
6788 | * e. Write zero+valid to all ILT entries (The valid bit must | |
6789 | * stay set) | |
6790 | * f. If this is VNIC 3 of a port then also init | |
6791 | * first_timers_ilt_entry to zero and last_timers_ilt_entry | |
16a5fd92 | 6792 | * to the last entry in the ILT. |
619c5cb6 VZ |
6793 | * |
6794 | * Notes: | |
6795 | * Currently the PF error in the PGLC is non recoverable. | |
6796 | * In the future the there will be a recovery routine for this error. | |
6797 | * Currently attention is masked. | |
6798 | * Having an MCP lock on the load/unload process does not guarantee that | |
6799 | * there is no Timer disable during Func6/7 enable. This is because the | |
6800 | * Timers scan is currently being cleared by the MCP on FLR. | |
6801 | * Step 2.d can be done only for PF6/7 and the driver can also check if | |
6802 | * there is error before clearing it. But the flow above is simpler and | |
6803 | * more general. | |
6804 | * All ILT entries are written by zero+valid and not just PF6/7 | |
6805 | * ILT entries since in the future the ILT entries allocation for | |
6806 | * PF-s might be dynamic. | |
6807 | */ | |
f2e0899f DK |
6808 | struct ilt_client_info ilt_cli; |
6809 | struct bnx2x_ilt ilt; | |
6810 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
6811 | memset(&ilt, 0, sizeof(struct bnx2x_ilt)); | |
6812 | ||
b595076a | 6813 | /* initialize dummy TM client */ |
f2e0899f DK |
6814 | ilt_cli.start = 0; |
6815 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
6816 | ilt_cli.client_num = ILT_CLIENT_TM; | |
6817 | ||
6818 | /* Step 1: set zeroes to all ilt page entries with valid bit on | |
6819 | * Step 2: set the timers first/last ilt entry to point | |
6820 | * to the entire range to prevent ILT range error for 3rd/4th | |
2de67439 | 6821 | * vnic (this code assumes existence of the vnic) |
f2e0899f DK |
6822 | * |
6823 | * both steps performed by call to bnx2x_ilt_client_init_op() | |
6824 | * with dummy TM client | |
6825 | * | |
6826 | * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT | |
6827 | * and his brother are split registers | |
6828 | */ | |
6829 | bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); | |
6830 | bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); | |
6831 | bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); | |
6832 | ||
6833 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); | |
6834 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); | |
6835 | REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); | |
6836 | } | |
6837 | ||
34f80b04 EG |
6838 | REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); |
6839 | REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); | |
a2fbb9ea | 6840 | |
619c5cb6 | 6841 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
6842 | int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : |
6843 | (CHIP_REV_IS_FPGA(bp) ? 400 : 0); | |
619c5cb6 | 6844 | bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); |
f2e0899f | 6845 | |
619c5cb6 | 6846 | bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); |
f2e0899f DK |
6847 | |
6848 | /* let the HW do it's magic ... */ | |
6849 | do { | |
6850 | msleep(200); | |
6851 | val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); | |
6852 | } while (factor-- && (val != 1)); | |
6853 | ||
6854 | if (val != 1) { | |
6855 | BNX2X_ERR("ATC_INIT failed\n"); | |
6856 | return -EBUSY; | |
6857 | } | |
6858 | } | |
6859 | ||
619c5cb6 | 6860 | bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); |
a2fbb9ea | 6861 | |
b56e9670 AE |
6862 | bnx2x_iov_init_dmae(bp); |
6863 | ||
34f80b04 EG |
6864 | /* clean the DMAE memory */ |
6865 | bp->dmae_ready = 1; | |
619c5cb6 VZ |
6866 | bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); |
6867 | ||
6868 | bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); | |
6869 | ||
6870 | bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); | |
6871 | ||
6872 | bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); | |
a2fbb9ea | 6873 | |
619c5cb6 | 6874 | bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); |
a2fbb9ea | 6875 | |
34f80b04 EG |
6876 | bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); |
6877 | bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); | |
6878 | bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); | |
6879 | bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); | |
6880 | ||
619c5cb6 | 6881 | bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); |
37b091ba | 6882 | |
523224a3 DK |
6883 | /* QM queues pointers table */ |
6884 | bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); | |
6885 | ||
34f80b04 EG |
6886 | /* soft reset pulse */ |
6887 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | |
6888 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | |
a2fbb9ea | 6889 | |
55c11941 MS |
6890 | if (CNIC_SUPPORT(bp)) |
6891 | bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); | |
a2fbb9ea | 6892 | |
619c5cb6 | 6893 | bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); |
b9871bcf | 6894 | |
619c5cb6 | 6895 | if (!CHIP_REV_IS_SLOW(bp)) |
34f80b04 EG |
6896 | /* enable hw interrupt from doorbell Q */ |
6897 | REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); | |
a2fbb9ea | 6898 | |
619c5cb6 | 6899 | bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); |
f2e0899f | 6900 | |
619c5cb6 | 6901 | bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); |
26c8fa4d | 6902 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
619c5cb6 | 6903 | |
f2e0899f | 6904 | if (!CHIP_IS_E1(bp)) |
619c5cb6 | 6905 | REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); |
f85582f8 | 6906 | |
a3348722 BW |
6907 | if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { |
6908 | if (IS_MF_AFEX(bp)) { | |
6909 | /* configure that VNTag and VLAN headers must be | |
6910 | * received in afex mode | |
6911 | */ | |
6912 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); | |
6913 | REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); | |
6914 | REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); | |
6915 | REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); | |
6916 | REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); | |
6917 | } else { | |
6918 | /* Bit-map indicating which L2 hdrs may appear | |
6919 | * after the basic Ethernet header | |
6920 | */ | |
6921 | REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, | |
6922 | bp->path_has_ovlan ? 7 : 6); | |
6923 | } | |
6924 | } | |
a2fbb9ea | 6925 | |
619c5cb6 VZ |
6926 | bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); |
6927 | bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); | |
6928 | bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); | |
6929 | bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); | |
a2fbb9ea | 6930 | |
619c5cb6 VZ |
6931 | if (!CHIP_IS_E1x(bp)) { |
6932 | /* reset VFC memories */ | |
6933 | REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6934 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6935 | VFC_MEMORIES_RST_REG_RAM_RST); | |
6936 | REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, | |
6937 | VFC_MEMORIES_RST_REG_CAM_RST | | |
6938 | VFC_MEMORIES_RST_REG_RAM_RST); | |
a2fbb9ea | 6939 | |
619c5cb6 VZ |
6940 | msleep(20); |
6941 | } | |
a2fbb9ea | 6942 | |
619c5cb6 VZ |
6943 | bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); |
6944 | bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); | |
6945 | bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); | |
6946 | bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); | |
f2e0899f | 6947 | |
34f80b04 EG |
6948 | /* sync semi rtc */ |
6949 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, | |
6950 | 0x80000000); | |
6951 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | |
6952 | 0x80000000); | |
a2fbb9ea | 6953 | |
619c5cb6 VZ |
6954 | bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); |
6955 | bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); | |
6956 | bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); | |
a2fbb9ea | 6957 | |
a3348722 BW |
6958 | if (!CHIP_IS_E1x(bp)) { |
6959 | if (IS_MF_AFEX(bp)) { | |
6960 | /* configure that VNTag and VLAN headers must be | |
6961 | * sent in afex mode | |
6962 | */ | |
6963 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); | |
6964 | REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); | |
6965 | REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); | |
6966 | REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); | |
6967 | REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); | |
6968 | } else { | |
6969 | REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, | |
6970 | bp->path_has_ovlan ? 7 : 6); | |
6971 | } | |
6972 | } | |
f2e0899f | 6973 | |
34f80b04 | 6974 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
f85582f8 | 6975 | |
619c5cb6 VZ |
6976 | bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); |
6977 | ||
55c11941 MS |
6978 | if (CNIC_SUPPORT(bp)) { |
6979 | REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); | |
6980 | REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); | |
6981 | REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); | |
6982 | REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); | |
6983 | REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); | |
6984 | REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); | |
6985 | REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); | |
6986 | REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); | |
6987 | REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); | |
6988 | REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); | |
6989 | } | |
34f80b04 | 6990 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
a2fbb9ea | 6991 | |
34f80b04 EG |
6992 | if (sizeof(union cdu_context) != 1024) |
6993 | /* we currently assume that a context is 1024 bytes */ | |
51c1a580 MS |
6994 | dev_alert(&bp->pdev->dev, |
6995 | "please adjust the size of cdu_context(%ld)\n", | |
6996 | (long)sizeof(union cdu_context)); | |
a2fbb9ea | 6997 | |
619c5cb6 | 6998 | bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); |
34f80b04 EG |
6999 | val = (4 << 24) + (0 << 12) + 1024; |
7000 | REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); | |
a2fbb9ea | 7001 | |
619c5cb6 | 7002 | bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); |
34f80b04 | 7003 | REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); |
8d9c5f34 EG |
7004 | /* enable context validation interrupt from CFC */ |
7005 | REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); | |
7006 | ||
7007 | /* set the thresholds to prevent CFC/CDU race */ | |
7008 | REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); | |
a2fbb9ea | 7009 | |
619c5cb6 | 7010 | bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); |
f2e0899f | 7011 | |
619c5cb6 | 7012 | if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) |
f2e0899f DK |
7013 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); |
7014 | ||
619c5cb6 VZ |
7015 | bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); |
7016 | bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); | |
a2fbb9ea | 7017 | |
34f80b04 EG |
7018 | /* Reset PCIE errors for debug */ |
7019 | REG_WR(bp, 0x2814, 0xffffffff); | |
7020 | REG_WR(bp, 0x3820, 0xffffffff); | |
a2fbb9ea | 7021 | |
619c5cb6 | 7022 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7023 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, |
7024 | (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | | |
7025 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); | |
7026 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, | |
7027 | (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | | |
7028 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | | |
7029 | PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); | |
7030 | REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, | |
7031 | (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | | |
7032 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | | |
7033 | PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); | |
7034 | } | |
7035 | ||
619c5cb6 | 7036 | bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); |
f2e0899f | 7037 | if (!CHIP_IS_E1(bp)) { |
619c5cb6 VZ |
7038 | /* in E3 this done in per-port section */ |
7039 | if (!CHIP_IS_E3(bp)) | |
7040 | REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
f2e0899f | 7041 | } |
619c5cb6 VZ |
7042 | if (CHIP_IS_E1H(bp)) |
7043 | /* not applicable for E2 (and above ...) */ | |
7044 | REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); | |
34f80b04 EG |
7045 | |
7046 | if (CHIP_REV_IS_SLOW(bp)) | |
7047 | msleep(200); | |
7048 | ||
7049 | /* finish CFC init */ | |
7050 | val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); | |
7051 | if (val != 1) { | |
7052 | BNX2X_ERR("CFC LL_INIT failed\n"); | |
7053 | return -EBUSY; | |
7054 | } | |
7055 | val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); | |
7056 | if (val != 1) { | |
7057 | BNX2X_ERR("CFC AC_INIT failed\n"); | |
7058 | return -EBUSY; | |
7059 | } | |
7060 | val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); | |
7061 | if (val != 1) { | |
7062 | BNX2X_ERR("CFC CAM_INIT failed\n"); | |
7063 | return -EBUSY; | |
7064 | } | |
7065 | REG_WR(bp, CFC_REG_DEBUG0, 0); | |
f1410647 | 7066 | |
f2e0899f DK |
7067 | if (CHIP_IS_E1(bp)) { |
7068 | /* read NIG statistic | |
7069 | to see if this is our first up since powerup */ | |
7070 | bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); | |
7071 | val = *bnx2x_sp(bp, wb_data[0]); | |
34f80b04 | 7072 | |
f2e0899f DK |
7073 | /* do internal memory self test */ |
7074 | if ((val == 0) && bnx2x_int_mem_test(bp)) { | |
7075 | BNX2X_ERR("internal mem self test failed\n"); | |
7076 | return -EBUSY; | |
7077 | } | |
34f80b04 EG |
7078 | } |
7079 | ||
fd4ef40d EG |
7080 | bnx2x_setup_fan_failure_detection(bp); |
7081 | ||
34f80b04 EG |
7082 | /* clear PXP2 attentions */ |
7083 | REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); | |
a2fbb9ea | 7084 | |
4a33bc03 | 7085 | bnx2x_enable_blocks_attention(bp); |
c9ee9206 | 7086 | bnx2x_enable_blocks_parity(bp); |
a2fbb9ea | 7087 | |
6bbca910 | 7088 | if (!BP_NOMCP(bp)) { |
619c5cb6 VZ |
7089 | if (CHIP_IS_E1x(bp)) |
7090 | bnx2x__common_init_phy(bp); | |
6bbca910 YR |
7091 | } else |
7092 | BNX2X_ERR("Bootcode is missing - can not initialize link\n"); | |
7093 | ||
34f80b04 EG |
7094 | return 0; |
7095 | } | |
a2fbb9ea | 7096 | |
619c5cb6 VZ |
7097 | /** |
7098 | * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. | |
7099 | * | |
7100 | * @bp: driver handle | |
7101 | */ | |
7102 | static int bnx2x_init_hw_common_chip(struct bnx2x *bp) | |
7103 | { | |
7104 | int rc = bnx2x_init_hw_common(bp); | |
7105 | ||
7106 | if (rc) | |
7107 | return rc; | |
7108 | ||
7109 | /* In E2 2-PORT mode, same ext phy is used for the two paths */ | |
7110 | if (!BP_NOMCP(bp)) | |
7111 | bnx2x__common_init_phy(bp); | |
7112 | ||
7113 | return 0; | |
7114 | } | |
7115 | ||
523224a3 | 7116 | static int bnx2x_init_hw_port(struct bnx2x *bp) |
34f80b04 EG |
7117 | { |
7118 | int port = BP_PORT(bp); | |
619c5cb6 | 7119 | int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; |
1c06328c | 7120 | u32 low, high; |
34f80b04 | 7121 | u32 val; |
a2fbb9ea | 7122 | |
51c1a580 | 7123 | DP(NETIF_MSG_HW, "starting port init port %d\n", port); |
34f80b04 EG |
7124 | |
7125 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); | |
a2fbb9ea | 7126 | |
619c5cb6 VZ |
7127 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); |
7128 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); | |
7129 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
ca00392c | 7130 | |
f2e0899f DK |
7131 | /* Timers bug workaround: disables the pf_master bit in pglue at |
7132 | * common phase, we need to enable it here before any dmae access are | |
7133 | * attempted. Therefore we manually added the enable-master to the | |
7134 | * port phase (it also happens in the function phase) | |
7135 | */ | |
619c5cb6 | 7136 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7137 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); |
7138 | ||
619c5cb6 VZ |
7139 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7140 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7141 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); | |
7142 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7143 | ||
7144 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7145 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7146 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7147 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
a2fbb9ea | 7148 | |
523224a3 DK |
7149 | /* QM cid (connection) count */ |
7150 | bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); | |
a2fbb9ea | 7151 | |
55c11941 MS |
7152 | if (CNIC_SUPPORT(bp)) { |
7153 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7154 | REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); | |
7155 | REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); | |
7156 | } | |
cdaa7cb8 | 7157 | |
619c5cb6 | 7158 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); |
f2e0899f | 7159 | |
2b674047 DK |
7160 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
7161 | ||
f2e0899f | 7162 | if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { |
619c5cb6 VZ |
7163 | |
7164 | if (IS_MF(bp)) | |
7165 | low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); | |
7166 | else if (bp->dev->mtu > 4096) { | |
7167 | if (bp->flags & ONE_PORT_FLAG) | |
7168 | low = 160; | |
7169 | else { | |
7170 | val = bp->dev->mtu; | |
7171 | /* (24*1024 + val*4)/256 */ | |
7172 | low = 96 + (val/64) + | |
7173 | ((val % 64) ? 1 : 0); | |
7174 | } | |
7175 | } else | |
7176 | low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); | |
7177 | high = low + 56; /* 14*1024/256 */ | |
f2e0899f DK |
7178 | REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); |
7179 | REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); | |
1c06328c | 7180 | } |
1c06328c | 7181 | |
619c5cb6 VZ |
7182 | if (CHIP_MODE_IS_4_PORT(bp)) |
7183 | REG_WR(bp, (BP_PORT(bp) ? | |
7184 | BRB1_REG_MAC_GUARANTIED_1 : | |
7185 | BRB1_REG_MAC_GUARANTIED_0), 40); | |
1c06328c | 7186 | |
619c5cb6 | 7187 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); |
a3348722 BW |
7188 | if (CHIP_IS_E3B0(bp)) { |
7189 | if (IS_MF_AFEX(bp)) { | |
7190 | /* configure headers for AFEX mode */ | |
7191 | REG_WR(bp, BP_PORT(bp) ? | |
7192 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7193 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); | |
7194 | REG_WR(bp, BP_PORT(bp) ? | |
7195 | PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : | |
7196 | PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); | |
7197 | REG_WR(bp, BP_PORT(bp) ? | |
7198 | PRS_REG_MUST_HAVE_HDRS_PORT_1 : | |
7199 | PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); | |
7200 | } else { | |
7201 | /* Ovlan exists only if we are in multi-function + | |
7202 | * switch-dependent mode, in switch-independent there | |
7203 | * is no ovlan headers | |
7204 | */ | |
7205 | REG_WR(bp, BP_PORT(bp) ? | |
7206 | PRS_REG_HDRS_AFTER_BASIC_PORT_1 : | |
7207 | PRS_REG_HDRS_AFTER_BASIC_PORT_0, | |
7208 | (bp->path_has_ovlan ? 7 : 6)); | |
7209 | } | |
7210 | } | |
356e2385 | 7211 | |
619c5cb6 VZ |
7212 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); |
7213 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7214 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7215 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
356e2385 | 7216 | |
619c5cb6 VZ |
7217 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); |
7218 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7219 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7220 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
34f80b04 | 7221 | |
619c5cb6 VZ |
7222 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); |
7223 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
a2fbb9ea | 7224 | |
619c5cb6 VZ |
7225 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); |
7226 | ||
7227 | if (CHIP_IS_E1x(bp)) { | |
f2e0899f DK |
7228 | /* configure PBF to work without PAUSE mtu 9000 */ |
7229 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); | |
a2fbb9ea | 7230 | |
f2e0899f DK |
7231 | /* update threshold */ |
7232 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); | |
7233 | /* update init credit */ | |
7234 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); | |
a2fbb9ea | 7235 | |
f2e0899f DK |
7236 | /* probe changes */ |
7237 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); | |
7238 | udelay(50); | |
7239 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); | |
7240 | } | |
a2fbb9ea | 7241 | |
55c11941 MS |
7242 | if (CNIC_SUPPORT(bp)) |
7243 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7244 | ||
619c5cb6 VZ |
7245 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
7246 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); | |
34f80b04 EG |
7247 | |
7248 | if (CHIP_IS_E1(bp)) { | |
7249 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7250 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7251 | } | |
619c5cb6 | 7252 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
34f80b04 | 7253 | |
619c5cb6 | 7254 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7255 | |
619c5cb6 | 7256 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
34f80b04 | 7257 | /* init aeu_mask_attn_func_0/1: |
16a5fd92 YM |
7258 | * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use |
7259 | * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF | |
34f80b04 | 7260 | * bits 4-7 are used for "per vn group attention" */ |
e4901dde VZ |
7261 | val = IS_MF(bp) ? 0xF7 : 0x7; |
7262 | /* Enable DCBX attention for all but E1 */ | |
7263 | val |= CHIP_IS_E1(bp) ? 0 : 0x10; | |
7264 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); | |
34f80b04 | 7265 | |
619c5cb6 VZ |
7266 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); |
7267 | ||
7268 | if (!CHIP_IS_E1x(bp)) { | |
7269 | /* Bit-map indicating which L2 hdrs may appear after the | |
7270 | * basic Ethernet header | |
7271 | */ | |
a3348722 BW |
7272 | if (IS_MF_AFEX(bp)) |
7273 | REG_WR(bp, BP_PORT(bp) ? | |
7274 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7275 | NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); | |
7276 | else | |
7277 | REG_WR(bp, BP_PORT(bp) ? | |
7278 | NIG_REG_P1_HDRS_AFTER_BASIC : | |
7279 | NIG_REG_P0_HDRS_AFTER_BASIC, | |
7280 | IS_MF_SD(bp) ? 7 : 6); | |
619c5cb6 VZ |
7281 | |
7282 | if (CHIP_IS_E3(bp)) | |
7283 | REG_WR(bp, BP_PORT(bp) ? | |
7284 | NIG_REG_LLH1_MF_MODE : | |
7285 | NIG_REG_LLH_MF_MODE, IS_MF(bp)); | |
7286 | } | |
7287 | if (!CHIP_IS_E3(bp)) | |
7288 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); | |
34f80b04 | 7289 | |
f2e0899f | 7290 | if (!CHIP_IS_E1(bp)) { |
fb3bff17 | 7291 | /* 0x2 disable mf_ov, 0x1 enable */ |
34f80b04 | 7292 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, |
0793f83f | 7293 | (IS_MF_SD(bp) ? 0x1 : 0x2)); |
34f80b04 | 7294 | |
619c5cb6 | 7295 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7296 | val = 0; |
7297 | switch (bp->mf_mode) { | |
7298 | case MULTI_FUNCTION_SD: | |
7299 | val = 1; | |
7300 | break; | |
7301 | case MULTI_FUNCTION_SI: | |
a3348722 | 7302 | case MULTI_FUNCTION_AFEX: |
f2e0899f DK |
7303 | val = 2; |
7304 | break; | |
7305 | } | |
7306 | ||
7307 | REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : | |
7308 | NIG_REG_LLH0_CLS_TYPE), val); | |
7309 | } | |
1c06328c EG |
7310 | { |
7311 | REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); | |
7312 | REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); | |
7313 | REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); | |
7314 | } | |
34f80b04 EG |
7315 | } |
7316 | ||
619c5cb6 VZ |
7317 | /* If SPIO5 is set to generate interrupts, enable it for this port */ |
7318 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | |
d6d99a3f | 7319 | if (val & MISC_SPIO_SPIO5) { |
4d295db0 EG |
7320 | u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
7321 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | |
7322 | val = REG_RD(bp, reg_addr); | |
f1410647 | 7323 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; |
4d295db0 | 7324 | REG_WR(bp, reg_addr, val); |
f1410647 | 7325 | } |
a2fbb9ea | 7326 | |
34f80b04 EG |
7327 | return 0; |
7328 | } | |
7329 | ||
34f80b04 EG |
7330 | static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) |
7331 | { | |
7332 | int reg; | |
32d68de1 | 7333 | u32 wb_write[2]; |
34f80b04 | 7334 | |
f2e0899f | 7335 | if (CHIP_IS_E1(bp)) |
34f80b04 | 7336 | reg = PXP2_REG_RQ_ONCHIP_AT + index*8; |
f2e0899f DK |
7337 | else |
7338 | reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; | |
34f80b04 | 7339 | |
32d68de1 YM |
7340 | wb_write[0] = ONCHIP_ADDR1(addr); |
7341 | wb_write[1] = ONCHIP_ADDR2(addr); | |
7342 | REG_WR_DMAE(bp, reg, wb_write, 2); | |
34f80b04 EG |
7343 | } |
7344 | ||
b56e9670 | 7345 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) |
1191cb83 ED |
7346 | { |
7347 | u32 data, ctl, cnt = 100; | |
7348 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
7349 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
7350 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
7351 | u32 sb_bit = 1 << (idu_sb_id%32); | |
b56e9670 | 7352 | u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; |
1191cb83 ED |
7353 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; |
7354 | ||
7355 | /* Not supported in BC mode */ | |
7356 | if (CHIP_INT_MODE_IS_BC(bp)) | |
7357 | return; | |
7358 | ||
7359 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
7360 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
7361 | IGU_REGULAR_CLEANUP_SET | | |
7362 | IGU_REGULAR_BCLEANUP; | |
7363 | ||
7364 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
7365 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
7366 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
7367 | ||
7368 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7369 | data, igu_addr_data); | |
7370 | REG_WR(bp, igu_addr_data, data); | |
7371 | mmiowb(); | |
7372 | barrier(); | |
7373 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
7374 | ctl, igu_addr_ctl); | |
7375 | REG_WR(bp, igu_addr_ctl, ctl); | |
7376 | mmiowb(); | |
7377 | barrier(); | |
7378 | ||
7379 | /* wait for clean up to finish */ | |
7380 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
7381 | msleep(20); | |
7382 | ||
1191cb83 ED |
7383 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { |
7384 | DP(NETIF_MSG_HW, | |
7385 | "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
7386 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
7387 | } | |
7388 | } | |
7389 | ||
7390 | static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) | |
f2e0899f | 7391 | { |
619c5cb6 | 7392 | bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); |
f2e0899f DK |
7393 | } |
7394 | ||
1191cb83 | 7395 | static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) |
f2e0899f DK |
7396 | { |
7397 | u32 i, base = FUNC_ILT_BASE(func); | |
7398 | for (i = base; i < base + ILT_PER_FUNC; i++) | |
7399 | bnx2x_ilt_wr(bp, i, 0); | |
7400 | } | |
7401 | ||
910cc727 | 7402 | static void bnx2x_init_searcher(struct bnx2x *bp) |
55c11941 MS |
7403 | { |
7404 | int port = BP_PORT(bp); | |
7405 | bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); | |
7406 | /* T1 hash bits value determines the T1 number of entries */ | |
7407 | REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); | |
7408 | } | |
7409 | ||
7410 | static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) | |
7411 | { | |
7412 | int rc; | |
7413 | struct bnx2x_func_state_params func_params = {NULL}; | |
7414 | struct bnx2x_func_switch_update_params *switch_update_params = | |
7415 | &func_params.params.switch_update; | |
7416 | ||
7417 | /* Prepare parameters for function state transitions */ | |
7418 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
7419 | __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); | |
7420 | ||
7421 | func_params.f_obj = &bp->func_obj; | |
7422 | func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; | |
7423 | ||
7424 | /* Function parameters */ | |
7425 | switch_update_params->suspend = suspend; | |
7426 | ||
7427 | rc = bnx2x_func_state_change(bp, &func_params); | |
7428 | ||
7429 | return rc; | |
7430 | } | |
7431 | ||
910cc727 | 7432 | static int bnx2x_reset_nic_mode(struct bnx2x *bp) |
55c11941 MS |
7433 | { |
7434 | int rc, i, port = BP_PORT(bp); | |
7435 | int vlan_en = 0, mac_en[NUM_MACS]; | |
7436 | ||
55c11941 MS |
7437 | /* Close input from network */ |
7438 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7439 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
7440 | } else { | |
7441 | vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7442 | NIG_REG_LLH0_FUNC_EN); | |
7443 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7444 | NIG_REG_LLH0_FUNC_EN, 0); | |
7445 | for (i = 0; i < NUM_MACS; i++) { | |
7446 | mac_en[i] = REG_RD(bp, port ? | |
7447 | (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7448 | 4 * i) : | |
7449 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + | |
7450 | 4 * i)); | |
7451 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7452 | 4 * i) : | |
7453 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); | |
7454 | } | |
7455 | } | |
7456 | ||
7457 | /* Close BMC to host */ | |
7458 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7459 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); | |
7460 | ||
7461 | /* Suspend Tx switching to the PF. Completion of this ramrod | |
7462 | * further guarantees that all the packets of that PF / child | |
7463 | * VFs in BRB were processed by the Parser, so it is safe to | |
7464 | * change the NIC_MODE register. | |
7465 | */ | |
7466 | rc = bnx2x_func_switch_update(bp, 1); | |
7467 | if (rc) { | |
7468 | BNX2X_ERR("Can't suspend tx-switching!\n"); | |
7469 | return rc; | |
7470 | } | |
7471 | ||
7472 | /* Change NIC_MODE register */ | |
7473 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7474 | ||
7475 | /* Open input from network */ | |
7476 | if (bp->mf_mode == SINGLE_FUNCTION) { | |
7477 | bnx2x_set_rx_filter(&bp->link_params, 1); | |
7478 | } else { | |
7479 | REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : | |
7480 | NIG_REG_LLH0_FUNC_EN, vlan_en); | |
7481 | for (i = 0; i < NUM_MACS; i++) { | |
7482 | REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + | |
7483 | 4 * i) : | |
7484 | (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), | |
7485 | mac_en[i]); | |
7486 | } | |
7487 | } | |
7488 | ||
7489 | /* Enable BMC to host */ | |
7490 | REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : | |
7491 | NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); | |
7492 | ||
7493 | /* Resume Tx switching to the PF */ | |
7494 | rc = bnx2x_func_switch_update(bp, 0); | |
7495 | if (rc) { | |
7496 | BNX2X_ERR("Can't resume tx-switching!\n"); | |
7497 | return rc; | |
7498 | } | |
7499 | ||
7500 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7501 | return 0; | |
7502 | } | |
7503 | ||
7504 | int bnx2x_init_hw_func_cnic(struct bnx2x *bp) | |
7505 | { | |
7506 | int rc; | |
7507 | ||
7508 | bnx2x_ilt_init_op_cnic(bp, INITOP_SET); | |
7509 | ||
7510 | if (CONFIGURE_NIC_MODE(bp)) { | |
16a5fd92 | 7511 | /* Configure searcher as part of function hw init */ |
55c11941 MS |
7512 | bnx2x_init_searcher(bp); |
7513 | ||
7514 | /* Reset NIC mode */ | |
7515 | rc = bnx2x_reset_nic_mode(bp); | |
7516 | if (rc) | |
7517 | BNX2X_ERR("Can't change NIC mode!\n"); | |
7518 | return rc; | |
7519 | } | |
7520 | ||
7521 | return 0; | |
7522 | } | |
7523 | ||
523224a3 | 7524 | static int bnx2x_init_hw_func(struct bnx2x *bp) |
34f80b04 EG |
7525 | { |
7526 | int port = BP_PORT(bp); | |
7527 | int func = BP_FUNC(bp); | |
619c5cb6 | 7528 | int init_phase = PHASE_PF0 + func; |
523224a3 DK |
7529 | struct bnx2x_ilt *ilt = BP_ILT(bp); |
7530 | u16 cdu_ilt_start; | |
8badd27a | 7531 | u32 addr, val; |
f4a66897 | 7532 | u32 main_mem_base, main_mem_size, main_mem_prty_clr; |
89db4ad8 | 7533 | int i, main_mem_width, rc; |
34f80b04 | 7534 | |
51c1a580 | 7535 | DP(NETIF_MSG_HW, "starting func init func %d\n", func); |
34f80b04 | 7536 | |
619c5cb6 | 7537 | /* FLR cleanup - hmmm */ |
89db4ad8 AE |
7538 | if (!CHIP_IS_E1x(bp)) { |
7539 | rc = bnx2x_pf_flr_clnup(bp); | |
04c46736 YM |
7540 | if (rc) { |
7541 | bnx2x_fw_dump(bp); | |
89db4ad8 | 7542 | return rc; |
04c46736 | 7543 | } |
89db4ad8 | 7544 | } |
619c5cb6 | 7545 | |
8badd27a | 7546 | /* set MSI reconfigure capability */ |
f2e0899f DK |
7547 | if (bp->common.int_block == INT_BLOCK_HC) { |
7548 | addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); | |
7549 | val = REG_RD(bp, addr); | |
7550 | val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; | |
7551 | REG_WR(bp, addr, val); | |
7552 | } | |
8badd27a | 7553 | |
619c5cb6 VZ |
7554 | bnx2x_init_block(bp, BLOCK_PXP, init_phase); |
7555 | bnx2x_init_block(bp, BLOCK_PXP2, init_phase); | |
7556 | ||
523224a3 DK |
7557 | ilt = BP_ILT(bp); |
7558 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
37b091ba | 7559 | |
290ca2bb AE |
7560 | if (IS_SRIOV(bp)) |
7561 | cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; | |
7562 | cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); | |
7563 | ||
7564 | /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes | |
7565 | * those of the VFs, so start line should be reset | |
7566 | */ | |
7567 | cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; | |
523224a3 | 7568 | for (i = 0; i < L2_ILT_LINES(bp); i++) { |
a052997e | 7569 | ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; |
523224a3 | 7570 | ilt->lines[cdu_ilt_start + i].page_mapping = |
a052997e MS |
7571 | bp->context[i].cxt_mapping; |
7572 | ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; | |
37b091ba | 7573 | } |
290ca2bb | 7574 | |
523224a3 | 7575 | bnx2x_ilt_init_op(bp, INITOP_SET); |
f85582f8 | 7576 | |
55c11941 MS |
7577 | if (!CONFIGURE_NIC_MODE(bp)) { |
7578 | bnx2x_init_searcher(bp); | |
7579 | REG_WR(bp, PRS_REG_NIC_MODE, 0); | |
7580 | DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); | |
7581 | } else { | |
7582 | /* Set NIC mode */ | |
7583 | REG_WR(bp, PRS_REG_NIC_MODE, 1); | |
6bf07b8e | 7584 | DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); |
55c11941 | 7585 | } |
37b091ba | 7586 | |
619c5cb6 | 7587 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7588 | u32 pf_conf = IGU_PF_CONF_FUNC_EN; |
7589 | ||
7590 | /* Turn on a single ISR mode in IGU if driver is going to use | |
7591 | * INT#x or MSI | |
7592 | */ | |
7593 | if (!(bp->flags & USING_MSIX_FLAG)) | |
7594 | pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; | |
7595 | /* | |
7596 | * Timers workaround bug: function init part. | |
7597 | * Need to wait 20msec after initializing ILT, | |
7598 | * needed to make sure there are no requests in | |
7599 | * one of the PXP internal queues with "old" ILT addresses | |
7600 | */ | |
7601 | msleep(20); | |
7602 | /* | |
7603 | * Master enable - Due to WB DMAE writes performed before this | |
7604 | * register is re-initialized as part of the regular function | |
7605 | * init | |
7606 | */ | |
7607 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); | |
7608 | /* Enable the function in IGU */ | |
7609 | REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); | |
7610 | } | |
7611 | ||
523224a3 | 7612 | bp->dmae_ready = 1; |
34f80b04 | 7613 | |
619c5cb6 | 7614 | bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); |
523224a3 | 7615 | |
619c5cb6 | 7616 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7617 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); |
7618 | ||
619c5cb6 VZ |
7619 | bnx2x_init_block(bp, BLOCK_ATC, init_phase); |
7620 | bnx2x_init_block(bp, BLOCK_DMAE, init_phase); | |
7621 | bnx2x_init_block(bp, BLOCK_NIG, init_phase); | |
7622 | bnx2x_init_block(bp, BLOCK_SRC, init_phase); | |
7623 | bnx2x_init_block(bp, BLOCK_MISC, init_phase); | |
7624 | bnx2x_init_block(bp, BLOCK_TCM, init_phase); | |
7625 | bnx2x_init_block(bp, BLOCK_UCM, init_phase); | |
7626 | bnx2x_init_block(bp, BLOCK_CCM, init_phase); | |
7627 | bnx2x_init_block(bp, BLOCK_XCM, init_phase); | |
7628 | bnx2x_init_block(bp, BLOCK_TSEM, init_phase); | |
7629 | bnx2x_init_block(bp, BLOCK_USEM, init_phase); | |
7630 | bnx2x_init_block(bp, BLOCK_CSEM, init_phase); | |
7631 | bnx2x_init_block(bp, BLOCK_XSEM, init_phase); | |
7632 | ||
7633 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7634 | REG_WR(bp, QM_REG_PF_EN, 1); |
7635 | ||
619c5cb6 VZ |
7636 | if (!CHIP_IS_E1x(bp)) { |
7637 | REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7638 | REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7639 | REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7640 | REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); | |
7641 | } | |
7642 | bnx2x_init_block(bp, BLOCK_QM, init_phase); | |
7643 | ||
7644 | bnx2x_init_block(bp, BLOCK_TM, init_phase); | |
7645 | bnx2x_init_block(bp, BLOCK_DORQ, init_phase); | |
c19d65c9 | 7646 | REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ |
b56e9670 AE |
7647 | |
7648 | bnx2x_iov_init_dq(bp); | |
7649 | ||
619c5cb6 VZ |
7650 | bnx2x_init_block(bp, BLOCK_BRB1, init_phase); |
7651 | bnx2x_init_block(bp, BLOCK_PRS, init_phase); | |
7652 | bnx2x_init_block(bp, BLOCK_TSDM, init_phase); | |
7653 | bnx2x_init_block(bp, BLOCK_CSDM, init_phase); | |
7654 | bnx2x_init_block(bp, BLOCK_USDM, init_phase); | |
7655 | bnx2x_init_block(bp, BLOCK_XSDM, init_phase); | |
7656 | bnx2x_init_block(bp, BLOCK_UPB, init_phase); | |
7657 | bnx2x_init_block(bp, BLOCK_XPB, init_phase); | |
7658 | bnx2x_init_block(bp, BLOCK_PBF, init_phase); | |
7659 | if (!CHIP_IS_E1x(bp)) | |
f2e0899f DK |
7660 | REG_WR(bp, PBF_REG_DISABLE_PF, 0); |
7661 | ||
619c5cb6 | 7662 | bnx2x_init_block(bp, BLOCK_CDU, init_phase); |
523224a3 | 7663 | |
619c5cb6 | 7664 | bnx2x_init_block(bp, BLOCK_CFC, init_phase); |
34f80b04 | 7665 | |
619c5cb6 | 7666 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
7667 | REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); |
7668 | ||
fb3bff17 | 7669 | if (IS_MF(bp)) { |
34f80b04 | 7670 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); |
fb3bff17 | 7671 | REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov); |
34f80b04 EG |
7672 | } |
7673 | ||
619c5cb6 | 7674 | bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); |
523224a3 | 7675 | |
34f80b04 | 7676 | /* HC init per function */ |
f2e0899f DK |
7677 | if (bp->common.int_block == INT_BLOCK_HC) { |
7678 | if (CHIP_IS_E1H(bp)) { | |
7679 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); | |
7680 | ||
7681 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
7682 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
7683 | } | |
619c5cb6 | 7684 | bnx2x_init_block(bp, BLOCK_HC, init_phase); |
f2e0899f DK |
7685 | |
7686 | } else { | |
7687 | int num_segs, sb_idx, prod_offset; | |
7688 | ||
34f80b04 EG |
7689 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); |
7690 | ||
619c5cb6 | 7691 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7692 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); |
7693 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
7694 | } | |
7695 | ||
619c5cb6 | 7696 | bnx2x_init_block(bp, BLOCK_IGU, init_phase); |
f2e0899f | 7697 | |
619c5cb6 | 7698 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
7699 | int dsb_idx = 0; |
7700 | /** | |
7701 | * Producer memory: | |
7702 | * E2 mode: address 0-135 match to the mapping memory; | |
7703 | * 136 - PF0 default prod; 137 - PF1 default prod; | |
7704 | * 138 - PF2 default prod; 139 - PF3 default prod; | |
7705 | * 140 - PF0 attn prod; 141 - PF1 attn prod; | |
7706 | * 142 - PF2 attn prod; 143 - PF3 attn prod; | |
7707 | * 144-147 reserved. | |
7708 | * | |
7709 | * E1.5 mode - In backward compatible mode; | |
7710 | * for non default SB; each even line in the memory | |
7711 | * holds the U producer and each odd line hold | |
7712 | * the C producer. The first 128 producers are for | |
7713 | * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 | |
7714 | * producers are for the DSB for each PF. | |
7715 | * Each PF has five segments: (the order inside each | |
7716 | * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; | |
7717 | * 132-135 C prods; 136-139 X prods; 140-143 T prods; | |
7718 | * 144-147 attn prods; | |
7719 | */ | |
7720 | /* non-default-status-blocks */ | |
7721 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7722 | IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; | |
7723 | for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { | |
7724 | prod_offset = (bp->igu_base_sb + sb_idx) * | |
7725 | num_segs; | |
7726 | ||
7727 | for (i = 0; i < num_segs; i++) { | |
7728 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7729 | (prod_offset + i) * 4; | |
7730 | REG_WR(bp, addr, 0); | |
7731 | } | |
7732 | /* send consumer update with value 0 */ | |
7733 | bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, | |
7734 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7735 | bnx2x_igu_clear_sb(bp, | |
7736 | bp->igu_base_sb + sb_idx); | |
7737 | } | |
7738 | ||
7739 | /* default-status-blocks */ | |
7740 | num_segs = CHIP_INT_MODE_IS_BC(bp) ? | |
7741 | IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; | |
7742 | ||
7743 | if (CHIP_MODE_IS_4_PORT(bp)) | |
7744 | dsb_idx = BP_FUNC(bp); | |
7745 | else | |
3395a033 | 7746 | dsb_idx = BP_VN(bp); |
f2e0899f DK |
7747 | |
7748 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | |
7749 | IGU_BC_BASE_DSB_PROD + dsb_idx : | |
7750 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | |
7751 | ||
3395a033 DK |
7752 | /* |
7753 | * igu prods come in chunks of E1HVN_MAX (4) - | |
7754 | * does not matters what is the current chip mode | |
7755 | */ | |
f2e0899f DK |
7756 | for (i = 0; i < (num_segs * E1HVN_MAX); |
7757 | i += E1HVN_MAX) { | |
7758 | addr = IGU_REG_PROD_CONS_MEMORY + | |
7759 | (prod_offset + i)*4; | |
7760 | REG_WR(bp, addr, 0); | |
7761 | } | |
7762 | /* send consumer update with 0 */ | |
7763 | if (CHIP_INT_MODE_IS_BC(bp)) { | |
7764 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7765 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7766 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7767 | CSTORM_ID, 0, IGU_INT_NOP, 1); | |
7768 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7769 | XSTORM_ID, 0, IGU_INT_NOP, 1); | |
7770 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7771 | TSTORM_ID, 0, IGU_INT_NOP, 1); | |
7772 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7773 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7774 | } else { | |
7775 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7776 | USTORM_ID, 0, IGU_INT_NOP, 1); | |
7777 | bnx2x_ack_sb(bp, bp->igu_dsb_id, | |
7778 | ATTENTION_ID, 0, IGU_INT_NOP, 1); | |
7779 | } | |
7780 | bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); | |
7781 | ||
16a5fd92 | 7782 | /* !!! These should become driver const once |
f2e0899f DK |
7783 | rf-tool supports split-68 const */ |
7784 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); | |
7785 | REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); | |
7786 | REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); | |
7787 | REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); | |
7788 | REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); | |
7789 | REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); | |
7790 | } | |
34f80b04 | 7791 | } |
34f80b04 | 7792 | |
c14423fe | 7793 | /* Reset PCIE errors for debug */ |
a2fbb9ea ET |
7794 | REG_WR(bp, 0x2114, 0xffffffff); |
7795 | REG_WR(bp, 0x2120, 0xffffffff); | |
523224a3 | 7796 | |
f4a66897 VZ |
7797 | if (CHIP_IS_E1x(bp)) { |
7798 | main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ | |
7799 | main_mem_base = HC_REG_MAIN_MEMORY + | |
7800 | BP_PORT(bp) * (main_mem_size * 4); | |
7801 | main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; | |
7802 | main_mem_width = 8; | |
7803 | ||
7804 | val = REG_RD(bp, main_mem_prty_clr); | |
7805 | if (val) | |
51c1a580 MS |
7806 | DP(NETIF_MSG_HW, |
7807 | "Hmmm... Parity errors in HC block during function init (0x%x)!\n", | |
7808 | val); | |
f4a66897 VZ |
7809 | |
7810 | /* Clear "false" parity errors in MSI-X table */ | |
7811 | for (i = main_mem_base; | |
7812 | i < main_mem_base + main_mem_size * 4; | |
7813 | i += main_mem_width) { | |
7814 | bnx2x_read_dmae(bp, i, main_mem_width / 4); | |
7815 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), | |
7816 | i, main_mem_width / 4); | |
7817 | } | |
7818 | /* Clear HC parity attention */ | |
7819 | REG_RD(bp, main_mem_prty_clr); | |
7820 | } | |
7821 | ||
619c5cb6 VZ |
7822 | #ifdef BNX2X_STOP_ON_ERROR |
7823 | /* Enable STORMs SP logging */ | |
7824 | REG_WR8(bp, BAR_USTRORM_INTMEM + | |
7825 | USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7826 | REG_WR8(bp, BAR_TSTRORM_INTMEM + | |
7827 | TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7828 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
7829 | CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7830 | REG_WR8(bp, BAR_XSTRORM_INTMEM + | |
7831 | XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); | |
7832 | #endif | |
7833 | ||
b7737c9b | 7834 | bnx2x_phy_probe(&bp->link_params); |
f85582f8 | 7835 | |
34f80b04 EG |
7836 | return 0; |
7837 | } | |
7838 | ||
55c11941 MS |
7839 | void bnx2x_free_mem_cnic(struct bnx2x *bp) |
7840 | { | |
7841 | bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); | |
7842 | ||
7843 | if (!CHIP_IS_E1x(bp)) | |
7844 | BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, | |
7845 | sizeof(struct host_hc_status_block_e2)); | |
7846 | else | |
7847 | BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, | |
7848 | sizeof(struct host_hc_status_block_e1x)); | |
7849 | ||
7850 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); | |
7851 | } | |
7852 | ||
9f6c9258 | 7853 | void bnx2x_free_mem(struct bnx2x *bp) |
a2fbb9ea | 7854 | { |
a052997e MS |
7855 | int i; |
7856 | ||
619c5cb6 VZ |
7857 | BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, |
7858 | bp->fw_stats_data_sz + bp->fw_stats_req_sz); | |
7859 | ||
b4cddbd6 AE |
7860 | if (IS_VF(bp)) |
7861 | return; | |
7862 | ||
7863 | BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, | |
7864 | sizeof(struct host_sp_status_block)); | |
7865 | ||
a2fbb9ea | 7866 | BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, |
34f80b04 | 7867 | sizeof(struct bnx2x_slowpath)); |
a2fbb9ea | 7868 | |
a052997e MS |
7869 | for (i = 0; i < L2_ILT_LINES(bp); i++) |
7870 | BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, | |
7871 | bp->context[i].size); | |
523224a3 DK |
7872 | bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); |
7873 | ||
7874 | BNX2X_FREE(bp->ilt->lines); | |
f85582f8 | 7875 | |
7a9b2557 | 7876 | BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); |
a2fbb9ea | 7877 | |
523224a3 DK |
7878 | BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, |
7879 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
580d9d08 | 7880 | |
05952246 YM |
7881 | BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); |
7882 | ||
580d9d08 | 7883 | bnx2x_iov_free_mem(bp); |
619c5cb6 VZ |
7884 | } |
7885 | ||
55c11941 | 7886 | int bnx2x_alloc_mem_cnic(struct bnx2x *bp) |
a2fbb9ea | 7887 | { |
619c5cb6 VZ |
7888 | if (!CHIP_IS_E1x(bp)) |
7889 | /* size = the status block + ramrod buffers */ | |
f2e0899f DK |
7890 | BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping, |
7891 | sizeof(struct host_hc_status_block_e2)); | |
7892 | else | |
55c11941 MS |
7893 | BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, |
7894 | &bp->cnic_sb_mapping, | |
7895 | sizeof(struct | |
7896 | host_hc_status_block_e1x)); | |
8badd27a | 7897 | |
2f7a3122 | 7898 | if (CONFIGURE_NIC_MODE(bp) && !bp->t2) |
16a5fd92 | 7899 | /* allocate searcher T2 table, as it wasn't allocated before */ |
55c11941 MS |
7900 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); |
7901 | ||
7902 | /* write address to which L5 should insert its values */ | |
7903 | bp->cnic_eth_dev.addr_drv_info_to_mcp = | |
7904 | &bp->slowpath->drv_info_to_mcp; | |
7905 | ||
7906 | if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) | |
7907 | goto alloc_mem_err; | |
7908 | ||
7909 | return 0; | |
7910 | ||
7911 | alloc_mem_err: | |
7912 | bnx2x_free_mem_cnic(bp); | |
7913 | BNX2X_ERR("Can't allocate memory\n"); | |
7914 | return -ENOMEM; | |
7915 | } | |
7916 | ||
7917 | int bnx2x_alloc_mem(struct bnx2x *bp) | |
7918 | { | |
7919 | int i, allocated, context_size; | |
a2fbb9ea | 7920 | |
2f7a3122 | 7921 | if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) |
55c11941 MS |
7922 | /* allocate searcher T2 table */ |
7923 | BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ); | |
8badd27a | 7924 | |
523224a3 DK |
7925 | BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, |
7926 | sizeof(struct host_sp_status_block)); | |
a2fbb9ea | 7927 | |
523224a3 DK |
7928 | BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, |
7929 | sizeof(struct bnx2x_slowpath)); | |
a2fbb9ea | 7930 | |
a052997e MS |
7931 | /* Allocate memory for CDU context: |
7932 | * This memory is allocated separately and not in the generic ILT | |
7933 | * functions because CDU differs in few aspects: | |
7934 | * 1. There are multiple entities allocating memory for context - | |
7935 | * 'regular' driver, CNIC and SRIOV driver. Each separately controls | |
7936 | * its own ILT lines. | |
7937 | * 2. Since CDU page-size is not a single 4KB page (which is the case | |
7938 | * for the other ILT clients), to be efficient we want to support | |
7939 | * allocation of sub-page-size in the last entry. | |
7940 | * 3. Context pointers are used by the driver to pass to FW / update | |
7941 | * the context (for the other ILT clients the pointers are used just to | |
7942 | * free the memory during unload). | |
7943 | */ | |
7944 | context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); | |
65abd74d | 7945 | |
a052997e MS |
7946 | for (i = 0, allocated = 0; allocated < context_size; i++) { |
7947 | bp->context[i].size = min(CDU_ILT_PAGE_SZ, | |
7948 | (context_size - allocated)); | |
7949 | BNX2X_PCI_ALLOC(bp->context[i].vcxt, | |
7950 | &bp->context[i].cxt_mapping, | |
7951 | bp->context[i].size); | |
7952 | allocated += bp->context[i].size; | |
7953 | } | |
523224a3 | 7954 | BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES); |
65abd74d | 7955 | |
523224a3 DK |
7956 | if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) |
7957 | goto alloc_mem_err; | |
65abd74d | 7958 | |
67c431a5 AE |
7959 | if (bnx2x_iov_alloc_mem(bp)) |
7960 | goto alloc_mem_err; | |
7961 | ||
9f6c9258 DK |
7962 | /* Slow path ring */ |
7963 | BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); | |
65abd74d | 7964 | |
523224a3 DK |
7965 | /* EQ */ |
7966 | BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping, | |
7967 | BCM_PAGE_SIZE * NUM_EQ_PAGES); | |
ab532cf3 | 7968 | |
9f6c9258 | 7969 | return 0; |
e1510706 | 7970 | |
9f6c9258 DK |
7971 | alloc_mem_err: |
7972 | bnx2x_free_mem(bp); | |
51c1a580 | 7973 | BNX2X_ERR("Can't allocate memory\n"); |
9f6c9258 | 7974 | return -ENOMEM; |
65abd74d YG |
7975 | } |
7976 | ||
a2fbb9ea ET |
7977 | /* |
7978 | * Init service functions | |
7979 | */ | |
a2fbb9ea | 7980 | |
619c5cb6 VZ |
7981 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, |
7982 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
7983 | int mac_type, unsigned long *ramrod_flags) | |
a2fbb9ea | 7984 | { |
619c5cb6 VZ |
7985 | int rc; |
7986 | struct bnx2x_vlan_mac_ramrod_params ramrod_param; | |
a2fbb9ea | 7987 | |
619c5cb6 | 7988 | memset(&ramrod_param, 0, sizeof(ramrod_param)); |
a2fbb9ea | 7989 | |
619c5cb6 VZ |
7990 | /* Fill general parameters */ |
7991 | ramrod_param.vlan_mac_obj = obj; | |
7992 | ramrod_param.ramrod_flags = *ramrod_flags; | |
a2fbb9ea | 7993 | |
619c5cb6 VZ |
7994 | /* Fill a user request section if needed */ |
7995 | if (!test_bit(RAMROD_CONT, ramrod_flags)) { | |
7996 | memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); | |
a2fbb9ea | 7997 | |
619c5cb6 | 7998 | __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); |
e3553b29 | 7999 | |
619c5cb6 VZ |
8000 | /* Set the command: ADD or DEL */ |
8001 | if (set) | |
8002 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; | |
8003 | else | |
8004 | ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; | |
a2fbb9ea ET |
8005 | } |
8006 | ||
619c5cb6 | 8007 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7b5342d9 YM |
8008 | |
8009 | if (rc == -EEXIST) { | |
8010 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | |
8011 | /* do not treat adding same MAC as error */ | |
8012 | rc = 0; | |
8013 | } else if (rc < 0) | |
619c5cb6 | 8014 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
7b5342d9 | 8015 | |
619c5cb6 | 8016 | return rc; |
a2fbb9ea ET |
8017 | } |
8018 | ||
619c5cb6 VZ |
8019 | int bnx2x_del_all_macs(struct bnx2x *bp, |
8020 | struct bnx2x_vlan_mac_obj *mac_obj, | |
8021 | int mac_type, bool wait_for_comp) | |
e665bfda | 8022 | { |
619c5cb6 VZ |
8023 | int rc; |
8024 | unsigned long ramrod_flags = 0, vlan_mac_flags = 0; | |
0793f83f | 8025 | |
619c5cb6 VZ |
8026 | /* Wait for completion of requested */ |
8027 | if (wait_for_comp) | |
8028 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
0793f83f | 8029 | |
619c5cb6 VZ |
8030 | /* Set the mac type of addresses we want to clear */ |
8031 | __set_bit(mac_type, &vlan_mac_flags); | |
0793f83f | 8032 | |
619c5cb6 VZ |
8033 | rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); |
8034 | if (rc < 0) | |
8035 | BNX2X_ERR("Failed to delete MACs: %d\n", rc); | |
0793f83f | 8036 | |
619c5cb6 | 8037 | return rc; |
0793f83f DK |
8038 | } |
8039 | ||
619c5cb6 | 8040 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) |
523224a3 | 8041 | { |
a3348722 BW |
8042 | if (is_zero_ether_addr(bp->dev->dev_addr) && |
8043 | (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) { | |
51c1a580 MS |
8044 | DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN, |
8045 | "Ignoring Zero MAC for STORAGE SD mode\n"); | |
614c76df DK |
8046 | return 0; |
8047 | } | |
614c76df | 8048 | |
f8f4f61a DK |
8049 | if (IS_PF(bp)) { |
8050 | unsigned long ramrod_flags = 0; | |
0793f83f | 8051 | |
f8f4f61a DK |
8052 | DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); |
8053 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
8054 | return bnx2x_set_mac_one(bp, bp->dev->dev_addr, | |
8055 | &bp->sp_objs->mac_obj, set, | |
8056 | BNX2X_ETH_MAC, &ramrod_flags); | |
8057 | } else { /* vf */ | |
8058 | return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, | |
8059 | bp->fp->index, true); | |
8060 | } | |
e665bfda | 8061 | } |
6e30dd4e | 8062 | |
619c5cb6 | 8063 | int bnx2x_setup_leading(struct bnx2x *bp) |
ec6ba945 | 8064 | { |
60cad4e6 AE |
8065 | if (IS_PF(bp)) |
8066 | return bnx2x_setup_queue(bp, &bp->fp[0], true); | |
8067 | else /* VF */ | |
8068 | return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); | |
993ac7b5 | 8069 | } |
a2fbb9ea | 8070 | |
d6214d7a | 8071 | /** |
e8920674 | 8072 | * bnx2x_set_int_mode - configure interrupt mode |
d6214d7a | 8073 | * |
e8920674 | 8074 | * @bp: driver handle |
d6214d7a | 8075 | * |
e8920674 | 8076 | * In case of MSI-X it will also try to enable MSI-X. |
d6214d7a | 8077 | */ |
1ab4434c | 8078 | int bnx2x_set_int_mode(struct bnx2x *bp) |
ca00392c | 8079 | { |
1ab4434c AE |
8080 | int rc = 0; |
8081 | ||
60cad4e6 AE |
8082 | if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { |
8083 | BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); | |
1ab4434c | 8084 | return -EINVAL; |
60cad4e6 | 8085 | } |
1ab4434c | 8086 | |
9ee3d37b | 8087 | switch (int_mode) { |
1ab4434c AE |
8088 | case BNX2X_INT_MODE_MSIX: |
8089 | /* attempt to enable msix */ | |
8090 | rc = bnx2x_enable_msix(bp); | |
8091 | ||
8092 | /* msix attained */ | |
8093 | if (!rc) | |
8094 | return 0; | |
8095 | ||
8096 | /* vfs use only msix */ | |
8097 | if (rc && IS_VF(bp)) | |
8098 | return rc; | |
8099 | ||
8100 | /* failed to enable multiple MSI-X */ | |
8101 | BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", | |
8102 | bp->num_queues, | |
8103 | 1 + bp->num_cnic_queues); | |
8104 | ||
8105 | /* falling through... */ | |
8106 | case BNX2X_INT_MODE_MSI: | |
d6214d7a | 8107 | bnx2x_enable_msi(bp); |
1ab4434c | 8108 | |
d6214d7a | 8109 | /* falling through... */ |
1ab4434c | 8110 | case BNX2X_INT_MODE_INTX: |
55c11941 MS |
8111 | bp->num_ethernet_queues = 1; |
8112 | bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; | |
51c1a580 | 8113 | BNX2X_DEV_INFO("set number of queues to 1\n"); |
ca00392c | 8114 | break; |
d6214d7a | 8115 | default: |
1ab4434c AE |
8116 | BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); |
8117 | return -EINVAL; | |
9f6c9258 | 8118 | } |
1ab4434c | 8119 | return 0; |
a2fbb9ea ET |
8120 | } |
8121 | ||
1ab4434c | 8122 | /* must be called prior to any HW initializations */ |
c2bff63f DK |
8123 | static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) |
8124 | { | |
290ca2bb AE |
8125 | if (IS_SRIOV(bp)) |
8126 | return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; | |
c2bff63f DK |
8127 | return L2_ILT_LINES(bp); |
8128 | } | |
8129 | ||
523224a3 DK |
8130 | void bnx2x_ilt_set_info(struct bnx2x *bp) |
8131 | { | |
8132 | struct ilt_client_info *ilt_client; | |
8133 | struct bnx2x_ilt *ilt = BP_ILT(bp); | |
8134 | u16 line = 0; | |
8135 | ||
8136 | ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); | |
8137 | DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); | |
8138 | ||
8139 | /* CDU */ | |
8140 | ilt_client = &ilt->clients[ILT_CLIENT_CDU]; | |
8141 | ilt_client->client_num = ILT_CLIENT_CDU; | |
8142 | ilt_client->page_size = CDU_ILT_PAGE_SZ; | |
8143 | ilt_client->flags = ILT_CLIENT_SKIP_MEM; | |
8144 | ilt_client->start = line; | |
619c5cb6 | 8145 | line += bnx2x_cid_ilt_lines(bp); |
55c11941 MS |
8146 | |
8147 | if (CNIC_SUPPORT(bp)) | |
8148 | line += CNIC_ILT_LINES; | |
523224a3 DK |
8149 | ilt_client->end = line - 1; |
8150 | ||
51c1a580 | 8151 | DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", |
523224a3 DK |
8152 | ilt_client->start, |
8153 | ilt_client->end, | |
8154 | ilt_client->page_size, | |
8155 | ilt_client->flags, | |
8156 | ilog2(ilt_client->page_size >> 12)); | |
8157 | ||
8158 | /* QM */ | |
8159 | if (QM_INIT(bp->qm_cid_count)) { | |
8160 | ilt_client = &ilt->clients[ILT_CLIENT_QM]; | |
8161 | ilt_client->client_num = ILT_CLIENT_QM; | |
8162 | ilt_client->page_size = QM_ILT_PAGE_SZ; | |
8163 | ilt_client->flags = 0; | |
8164 | ilt_client->start = line; | |
8165 | ||
8166 | /* 4 bytes for each cid */ | |
8167 | line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, | |
8168 | QM_ILT_PAGE_SZ); | |
8169 | ||
8170 | ilt_client->end = line - 1; | |
8171 | ||
51c1a580 MS |
8172 | DP(NETIF_MSG_IFUP, |
8173 | "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
523224a3 DK |
8174 | ilt_client->start, |
8175 | ilt_client->end, | |
8176 | ilt_client->page_size, | |
8177 | ilt_client->flags, | |
8178 | ilog2(ilt_client->page_size >> 12)); | |
523224a3 | 8179 | } |
523224a3 | 8180 | |
55c11941 MS |
8181 | if (CNIC_SUPPORT(bp)) { |
8182 | /* SRC */ | |
8183 | ilt_client = &ilt->clients[ILT_CLIENT_SRC]; | |
8184 | ilt_client->client_num = ILT_CLIENT_SRC; | |
8185 | ilt_client->page_size = SRC_ILT_PAGE_SZ; | |
8186 | ilt_client->flags = 0; | |
8187 | ilt_client->start = line; | |
8188 | line += SRC_ILT_LINES; | |
8189 | ilt_client->end = line - 1; | |
523224a3 | 8190 | |
55c11941 MS |
8191 | DP(NETIF_MSG_IFUP, |
8192 | "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8193 | ilt_client->start, | |
8194 | ilt_client->end, | |
8195 | ilt_client->page_size, | |
8196 | ilt_client->flags, | |
8197 | ilog2(ilt_client->page_size >> 12)); | |
9f6c9258 | 8198 | |
55c11941 MS |
8199 | /* TM */ |
8200 | ilt_client = &ilt->clients[ILT_CLIENT_TM]; | |
8201 | ilt_client->client_num = ILT_CLIENT_TM; | |
8202 | ilt_client->page_size = TM_ILT_PAGE_SZ; | |
8203 | ilt_client->flags = 0; | |
8204 | ilt_client->start = line; | |
8205 | line += TM_ILT_LINES; | |
8206 | ilt_client->end = line - 1; | |
523224a3 | 8207 | |
55c11941 MS |
8208 | DP(NETIF_MSG_IFUP, |
8209 | "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", | |
8210 | ilt_client->start, | |
8211 | ilt_client->end, | |
8212 | ilt_client->page_size, | |
8213 | ilt_client->flags, | |
8214 | ilog2(ilt_client->page_size >> 12)); | |
8215 | } | |
9f6c9258 | 8216 | |
619c5cb6 | 8217 | BUG_ON(line > ILT_MAX_LINES); |
523224a3 | 8218 | } |
f85582f8 | 8219 | |
619c5cb6 VZ |
8220 | /** |
8221 | * bnx2x_pf_q_prep_init - prepare INIT transition parameters | |
8222 | * | |
8223 | * @bp: driver handle | |
8224 | * @fp: pointer to fastpath | |
8225 | * @init_params: pointer to parameters structure | |
8226 | * | |
8227 | * parameters configured: | |
8228 | * - HC configuration | |
8229 | * - Queue's CDU context | |
8230 | */ | |
1191cb83 | 8231 | static void bnx2x_pf_q_prep_init(struct bnx2x *bp, |
619c5cb6 | 8232 | struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) |
a2fbb9ea | 8233 | { |
6383c0b3 | 8234 | u8 cos; |
a052997e MS |
8235 | int cxt_index, cxt_offset; |
8236 | ||
619c5cb6 VZ |
8237 | /* FCoE Queue uses Default SB, thus has no HC capabilities */ |
8238 | if (!IS_FCOE_FP(fp)) { | |
8239 | __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); | |
8240 | __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); | |
8241 | ||
16a5fd92 | 8242 | /* If HC is supported, enable host coalescing in the transition |
619c5cb6 VZ |
8243 | * to INIT state. |
8244 | */ | |
8245 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); | |
8246 | __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); | |
8247 | ||
8248 | /* HC rate */ | |
8249 | init_params->rx.hc_rate = bp->rx_ticks ? | |
8250 | (1000000 / bp->rx_ticks) : 0; | |
8251 | init_params->tx.hc_rate = bp->tx_ticks ? | |
8252 | (1000000 / bp->tx_ticks) : 0; | |
8253 | ||
8254 | /* FW SB ID */ | |
8255 | init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = | |
8256 | fp->fw_sb_id; | |
8257 | ||
8258 | /* | |
8259 | * CQ index among the SB indices: FCoE clients uses the default | |
8260 | * SB, therefore it's different. | |
8261 | */ | |
6383c0b3 AE |
8262 | init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; |
8263 | init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; | |
619c5cb6 VZ |
8264 | } |
8265 | ||
6383c0b3 AE |
8266 | /* set maximum number of COSs supported by this queue */ |
8267 | init_params->max_cos = fp->max_cos; | |
8268 | ||
51c1a580 | 8269 | DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", |
6383c0b3 AE |
8270 | fp->index, init_params->max_cos); |
8271 | ||
8272 | /* set the context pointers queue object */ | |
a052997e | 8273 | for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { |
65565884 MS |
8274 | cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; |
8275 | cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * | |
a052997e | 8276 | ILT_PAGE_CIDS); |
6383c0b3 | 8277 | init_params->cxts[cos] = |
a052997e MS |
8278 | &bp->context[cxt_index].vcxt[cxt_offset].eth; |
8279 | } | |
619c5cb6 VZ |
8280 | } |
8281 | ||
910cc727 | 8282 | static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
6383c0b3 AE |
8283 | struct bnx2x_queue_state_params *q_params, |
8284 | struct bnx2x_queue_setup_tx_only_params *tx_only_params, | |
8285 | int tx_index, bool leading) | |
8286 | { | |
8287 | memset(tx_only_params, 0, sizeof(*tx_only_params)); | |
8288 | ||
8289 | /* Set the command */ | |
8290 | q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; | |
8291 | ||
8292 | /* Set tx-only QUEUE flags: don't zero statistics */ | |
8293 | tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); | |
8294 | ||
8295 | /* choose the index of the cid to send the slow path on */ | |
8296 | tx_only_params->cid_index = tx_index; | |
8297 | ||
8298 | /* Set general TX_ONLY_SETUP parameters */ | |
8299 | bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); | |
8300 | ||
8301 | /* Set Tx TX_ONLY_SETUP parameters */ | |
8302 | bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); | |
8303 | ||
51c1a580 MS |
8304 | DP(NETIF_MSG_IFUP, |
8305 | "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", | |
6383c0b3 AE |
8306 | tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], |
8307 | q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, | |
8308 | tx_only_params->gen_params.spcl_id, tx_only_params->flags); | |
8309 | ||
8310 | /* send the ramrod */ | |
8311 | return bnx2x_queue_state_change(bp, q_params); | |
8312 | } | |
8313 | ||
619c5cb6 VZ |
8314 | /** |
8315 | * bnx2x_setup_queue - setup queue | |
8316 | * | |
8317 | * @bp: driver handle | |
8318 | * @fp: pointer to fastpath | |
8319 | * @leading: is leading | |
8320 | * | |
8321 | * This function performs 2 steps in a Queue state machine | |
8322 | * actually: 1) RESET->INIT 2) INIT->SETUP | |
8323 | */ | |
8324 | ||
8325 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
8326 | bool leading) | |
8327 | { | |
3b603066 | 8328 | struct bnx2x_queue_state_params q_params = {NULL}; |
619c5cb6 VZ |
8329 | struct bnx2x_queue_setup_params *setup_params = |
8330 | &q_params.params.setup; | |
6383c0b3 AE |
8331 | struct bnx2x_queue_setup_tx_only_params *tx_only_params = |
8332 | &q_params.params.tx_only; | |
a2fbb9ea | 8333 | int rc; |
6383c0b3 AE |
8334 | u8 tx_index; |
8335 | ||
51c1a580 | 8336 | DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); |
a2fbb9ea | 8337 | |
ec6ba945 VZ |
8338 | /* reset IGU state skip FCoE L2 queue */ |
8339 | if (!IS_FCOE_FP(fp)) | |
8340 | bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, | |
523224a3 | 8341 | IGU_INT_ENABLE, 0); |
a2fbb9ea | 8342 | |
15192a8c | 8343 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8344 | /* We want to wait for completion in this context */ |
8345 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8346 | |
619c5cb6 VZ |
8347 | /* Prepare the INIT parameters */ |
8348 | bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); | |
ec6ba945 | 8349 | |
619c5cb6 VZ |
8350 | /* Set the command */ |
8351 | q_params.cmd = BNX2X_Q_CMD_INIT; | |
8352 | ||
8353 | /* Change the state to INIT */ | |
8354 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8355 | if (rc) { | |
6383c0b3 | 8356 | BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); |
619c5cb6 VZ |
8357 | return rc; |
8358 | } | |
ec6ba945 | 8359 | |
51c1a580 | 8360 | DP(NETIF_MSG_IFUP, "init complete\n"); |
6383c0b3 | 8361 | |
619c5cb6 VZ |
8362 | /* Now move the Queue to the SETUP state... */ |
8363 | memset(setup_params, 0, sizeof(*setup_params)); | |
a2fbb9ea | 8364 | |
619c5cb6 VZ |
8365 | /* Set QUEUE flags */ |
8366 | setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); | |
523224a3 | 8367 | |
619c5cb6 | 8368 | /* Set general SETUP parameters */ |
6383c0b3 AE |
8369 | bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, |
8370 | FIRST_TX_COS_INDEX); | |
619c5cb6 | 8371 | |
6383c0b3 | 8372 | bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, |
619c5cb6 VZ |
8373 | &setup_params->rxq_params); |
8374 | ||
6383c0b3 AE |
8375 | bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, |
8376 | FIRST_TX_COS_INDEX); | |
619c5cb6 VZ |
8377 | |
8378 | /* Set the command */ | |
8379 | q_params.cmd = BNX2X_Q_CMD_SETUP; | |
8380 | ||
55c11941 MS |
8381 | if (IS_FCOE_FP(fp)) |
8382 | bp->fcoe_init = true; | |
8383 | ||
619c5cb6 VZ |
8384 | /* Change the state to SETUP */ |
8385 | rc = bnx2x_queue_state_change(bp, &q_params); | |
6383c0b3 AE |
8386 | if (rc) { |
8387 | BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); | |
8388 | return rc; | |
8389 | } | |
8390 | ||
8391 | /* loop through the relevant tx-only indices */ | |
8392 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8393 | tx_index < fp->max_cos; | |
8394 | tx_index++) { | |
8395 | ||
8396 | /* prepare and send tx-only ramrod*/ | |
8397 | rc = bnx2x_setup_tx_only(bp, fp, &q_params, | |
8398 | tx_only_params, tx_index, leading); | |
8399 | if (rc) { | |
8400 | BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", | |
8401 | fp->index, tx_index); | |
8402 | return rc; | |
8403 | } | |
8404 | } | |
523224a3 | 8405 | |
34f80b04 | 8406 | return rc; |
a2fbb9ea ET |
8407 | } |
8408 | ||
619c5cb6 | 8409 | static int bnx2x_stop_queue(struct bnx2x *bp, int index) |
a2fbb9ea | 8410 | { |
619c5cb6 | 8411 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
6383c0b3 | 8412 | struct bnx2x_fp_txdata *txdata; |
3b603066 | 8413 | struct bnx2x_queue_state_params q_params = {NULL}; |
6383c0b3 AE |
8414 | int rc, tx_index; |
8415 | ||
51c1a580 | 8416 | DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); |
a2fbb9ea | 8417 | |
15192a8c | 8418 | q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; |
619c5cb6 VZ |
8419 | /* We want to wait for completion in this context */ |
8420 | __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); | |
a2fbb9ea | 8421 | |
6383c0b3 AE |
8422 | /* close tx-only connections */ |
8423 | for (tx_index = FIRST_TX_ONLY_COS_INDEX; | |
8424 | tx_index < fp->max_cos; | |
8425 | tx_index++){ | |
8426 | ||
8427 | /* ascertain this is a normal queue*/ | |
65565884 | 8428 | txdata = fp->txdata_ptr[tx_index]; |
6383c0b3 | 8429 | |
51c1a580 | 8430 | DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", |
6383c0b3 AE |
8431 | txdata->txq_index); |
8432 | ||
8433 | /* send halt terminate on tx-only connection */ | |
8434 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; | |
8435 | memset(&q_params.params.terminate, 0, | |
8436 | sizeof(q_params.params.terminate)); | |
8437 | q_params.params.terminate.cid_index = tx_index; | |
8438 | ||
8439 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8440 | if (rc) | |
8441 | return rc; | |
8442 | ||
8443 | /* send halt terminate on tx-only connection */ | |
8444 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; | |
8445 | memset(&q_params.params.cfc_del, 0, | |
8446 | sizeof(q_params.params.cfc_del)); | |
8447 | q_params.params.cfc_del.cid_index = tx_index; | |
8448 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8449 | if (rc) | |
8450 | return rc; | |
8451 | } | |
8452 | /* Stop the primary connection: */ | |
8453 | /* ...halt the connection */ | |
619c5cb6 VZ |
8454 | q_params.cmd = BNX2X_Q_CMD_HALT; |
8455 | rc = bnx2x_queue_state_change(bp, &q_params); | |
8456 | if (rc) | |
da5a662a | 8457 | return rc; |
a2fbb9ea | 8458 | |
6383c0b3 | 8459 | /* ...terminate the connection */ |
619c5cb6 | 8460 | q_params.cmd = BNX2X_Q_CMD_TERMINATE; |
6383c0b3 AE |
8461 | memset(&q_params.params.terminate, 0, |
8462 | sizeof(q_params.params.terminate)); | |
8463 | q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 VZ |
8464 | rc = bnx2x_queue_state_change(bp, &q_params); |
8465 | if (rc) | |
523224a3 | 8466 | return rc; |
6383c0b3 | 8467 | /* ...delete cfc entry */ |
619c5cb6 | 8468 | q_params.cmd = BNX2X_Q_CMD_CFC_DEL; |
6383c0b3 AE |
8469 | memset(&q_params.params.cfc_del, 0, |
8470 | sizeof(q_params.params.cfc_del)); | |
8471 | q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; | |
619c5cb6 | 8472 | return bnx2x_queue_state_change(bp, &q_params); |
523224a3 DK |
8473 | } |
8474 | ||
34f80b04 EG |
8475 | static void bnx2x_reset_func(struct bnx2x *bp) |
8476 | { | |
8477 | int port = BP_PORT(bp); | |
8478 | int func = BP_FUNC(bp); | |
f2e0899f | 8479 | int i; |
523224a3 DK |
8480 | |
8481 | /* Disable the function in the FW */ | |
8482 | REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); | |
8483 | REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); | |
8484 | REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); | |
8485 | REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); | |
8486 | ||
8487 | /* FP SBs */ | |
ec6ba945 | 8488 | for_each_eth_queue(bp, i) { |
523224a3 | 8489 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
619c5cb6 | 8490 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
6383c0b3 AE |
8491 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), |
8492 | SB_DISABLED); | |
523224a3 DK |
8493 | } |
8494 | ||
55c11941 MS |
8495 | if (CNIC_LOADED(bp)) |
8496 | /* CNIC SB */ | |
8497 | REG_WR8(bp, BAR_CSTRORM_INTMEM + | |
8498 | CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET | |
8499 | (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); | |
8500 | ||
523224a3 | 8501 | /* SP SB */ |
619c5cb6 | 8502 | REG_WR8(bp, BAR_CSTRORM_INTMEM + |
2de67439 YM |
8503 | CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), |
8504 | SB_DISABLED); | |
523224a3 DK |
8505 | |
8506 | for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) | |
8507 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), | |
8508 | 0); | |
34f80b04 EG |
8509 | |
8510 | /* Configure IGU */ | |
f2e0899f DK |
8511 | if (bp->common.int_block == INT_BLOCK_HC) { |
8512 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); | |
8513 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); | |
8514 | } else { | |
8515 | REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); | |
8516 | REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
8517 | } | |
34f80b04 | 8518 | |
55c11941 MS |
8519 | if (CNIC_LOADED(bp)) { |
8520 | /* Disable Timer scan */ | |
8521 | REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); | |
8522 | /* | |
8523 | * Wait for at least 10ms and up to 2 second for the timers | |
8524 | * scan to complete | |
8525 | */ | |
8526 | for (i = 0; i < 200; i++) { | |
639d65b8 | 8527 | usleep_range(10000, 20000); |
55c11941 MS |
8528 | if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) |
8529 | break; | |
8530 | } | |
37b091ba | 8531 | } |
34f80b04 | 8532 | /* Clear ILT */ |
f2e0899f DK |
8533 | bnx2x_clear_func_ilt(bp, func); |
8534 | ||
8535 | /* Timers workaround bug for E2: if this is vnic-3, | |
8536 | * we need to set the entire ilt range for this timers. | |
8537 | */ | |
619c5cb6 | 8538 | if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { |
f2e0899f DK |
8539 | struct ilt_client_info ilt_cli; |
8540 | /* use dummy TM client */ | |
8541 | memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); | |
8542 | ilt_cli.start = 0; | |
8543 | ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; | |
8544 | ilt_cli.client_num = ILT_CLIENT_TM; | |
8545 | ||
8546 | bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); | |
8547 | } | |
8548 | ||
8549 | /* this assumes that reset_port() called before reset_func()*/ | |
619c5cb6 | 8550 | if (!CHIP_IS_E1x(bp)) |
f2e0899f | 8551 | bnx2x_pf_disable(bp); |
523224a3 DK |
8552 | |
8553 | bp->dmae_ready = 0; | |
34f80b04 EG |
8554 | } |
8555 | ||
8556 | static void bnx2x_reset_port(struct bnx2x *bp) | |
8557 | { | |
8558 | int port = BP_PORT(bp); | |
8559 | u32 val; | |
8560 | ||
619c5cb6 VZ |
8561 | /* Reset physical Link */ |
8562 | bnx2x__link_reset(bp); | |
8563 | ||
34f80b04 EG |
8564 | REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); |
8565 | ||
8566 | /* Do not rcv packets to BRB */ | |
8567 | REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); | |
8568 | /* Do not direct rcv packets that are not for MCP to the BRB */ | |
8569 | REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : | |
8570 | NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); | |
8571 | ||
8572 | /* Configure AEU */ | |
8573 | REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); | |
8574 | ||
8575 | msleep(100); | |
8576 | /* Check for BRB port occupancy */ | |
8577 | val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); | |
8578 | if (val) | |
8579 | DP(NETIF_MSG_IFDOWN, | |
33471629 | 8580 | "BRB1 is not empty %d blocks are occupied\n", val); |
34f80b04 EG |
8581 | |
8582 | /* TODO: Close Doorbell port? */ | |
8583 | } | |
8584 | ||
1191cb83 | 8585 | static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) |
34f80b04 | 8586 | { |
3b603066 | 8587 | struct bnx2x_func_state_params func_params = {NULL}; |
34f80b04 | 8588 | |
619c5cb6 VZ |
8589 | /* Prepare parameters for function state transitions */ |
8590 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
34f80b04 | 8591 | |
619c5cb6 VZ |
8592 | func_params.f_obj = &bp->func_obj; |
8593 | func_params.cmd = BNX2X_F_CMD_HW_RESET; | |
34f80b04 | 8594 | |
619c5cb6 | 8595 | func_params.params.hw_init.load_phase = load_code; |
49d66772 | 8596 | |
619c5cb6 | 8597 | return bnx2x_func_state_change(bp, &func_params); |
34f80b04 EG |
8598 | } |
8599 | ||
1191cb83 | 8600 | static int bnx2x_func_stop(struct bnx2x *bp) |
ec6ba945 | 8601 | { |
3b603066 | 8602 | struct bnx2x_func_state_params func_params = {NULL}; |
619c5cb6 | 8603 | int rc; |
228241eb | 8604 | |
619c5cb6 VZ |
8605 | /* Prepare parameters for function state transitions */ |
8606 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
8607 | func_params.f_obj = &bp->func_obj; | |
8608 | func_params.cmd = BNX2X_F_CMD_STOP; | |
da5a662a | 8609 | |
619c5cb6 VZ |
8610 | /* |
8611 | * Try to stop the function the 'good way'. If fails (in case | |
8612 | * of a parity error during bnx2x_chip_cleanup()) and we are | |
8613 | * not in a debug mode, perform a state transaction in order to | |
8614 | * enable further HW_RESET transaction. | |
8615 | */ | |
8616 | rc = bnx2x_func_state_change(bp, &func_params); | |
8617 | if (rc) { | |
34f80b04 | 8618 | #ifdef BNX2X_STOP_ON_ERROR |
619c5cb6 | 8619 | return rc; |
34f80b04 | 8620 | #else |
51c1a580 | 8621 | BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); |
619c5cb6 VZ |
8622 | __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); |
8623 | return bnx2x_func_state_change(bp, &func_params); | |
34f80b04 | 8624 | #endif |
228241eb | 8625 | } |
a2fbb9ea | 8626 | |
619c5cb6 VZ |
8627 | return 0; |
8628 | } | |
523224a3 | 8629 | |
619c5cb6 VZ |
8630 | /** |
8631 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
8632 | * | |
8633 | * @bp: driver handle | |
8634 | * @unload_mode: requested function's unload mode | |
8635 | * | |
8636 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
8637 | */ | |
8638 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |
8639 | { | |
8640 | u32 reset_code = 0; | |
8641 | int port = BP_PORT(bp); | |
3101c2bc | 8642 | |
619c5cb6 | 8643 | /* Select the UNLOAD request mode */ |
65abd74d YG |
8644 | if (unload_mode == UNLOAD_NORMAL) |
8645 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
8646 | ||
7d0446c2 | 8647 | else if (bp->flags & NO_WOL_FLAG) |
65abd74d | 8648 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
65abd74d | 8649 | |
7d0446c2 | 8650 | else if (bp->wol) { |
65abd74d YG |
8651 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
8652 | u8 *mac_addr = bp->dev->dev_addr; | |
29ed74c3 | 8653 | struct pci_dev *pdev = bp->pdev; |
65abd74d | 8654 | u32 val; |
f9977903 DK |
8655 | u16 pmc; |
8656 | ||
65abd74d | 8657 | /* The mac address is written to entries 1-4 to |
f9977903 DK |
8658 | * preserve entry 0 which is used by the PMF |
8659 | */ | |
3395a033 | 8660 | u8 entry = (BP_VN(bp) + 1)*8; |
65abd74d YG |
8661 | |
8662 | val = (mac_addr[0] << 8) | mac_addr[1]; | |
8663 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | |
8664 | ||
8665 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | |
8666 | (mac_addr[4] << 8) | mac_addr[5]; | |
8667 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); | |
8668 | ||
f9977903 | 8669 | /* Enable the PME and clear the status */ |
29ed74c3 | 8670 | pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); |
f9977903 | 8671 | pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; |
29ed74c3 | 8672 | pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); |
f9977903 | 8673 | |
65abd74d YG |
8674 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
8675 | ||
8676 | } else | |
8677 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | |
da5a662a | 8678 | |
619c5cb6 VZ |
8679 | /* Send the request to the MCP */ |
8680 | if (!BP_NOMCP(bp)) | |
8681 | reset_code = bnx2x_fw_command(bp, reset_code, 0); | |
8682 | else { | |
8683 | int path = BP_PATH(bp); | |
8684 | ||
51c1a580 | 8685 | DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8686 | path, load_count[path][0], load_count[path][1], |
8687 | load_count[path][2]); | |
8688 | load_count[path][0]--; | |
8689 | load_count[path][1 + port]--; | |
51c1a580 | 8690 | DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", |
619c5cb6 VZ |
8691 | path, load_count[path][0], load_count[path][1], |
8692 | load_count[path][2]); | |
8693 | if (load_count[path][0] == 0) | |
8694 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; | |
8695 | else if (load_count[path][1 + port] == 0) | |
8696 | reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; | |
8697 | else | |
8698 | reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; | |
8699 | } | |
8700 | ||
8701 | return reset_code; | |
8702 | } | |
8703 | ||
8704 | /** | |
8705 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
8706 | * | |
8707 | * @bp: driver handle | |
5d07d868 | 8708 | * @keep_link: true iff link should be kept up |
619c5cb6 | 8709 | */ |
5d07d868 | 8710 | void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) |
619c5cb6 | 8711 | { |
5d07d868 YM |
8712 | u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; |
8713 | ||
619c5cb6 VZ |
8714 | /* Report UNLOAD_DONE to MCP */ |
8715 | if (!BP_NOMCP(bp)) | |
5d07d868 | 8716 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); |
619c5cb6 VZ |
8717 | } |
8718 | ||
1191cb83 | 8719 | static int bnx2x_func_wait_started(struct bnx2x *bp) |
6debea87 DK |
8720 | { |
8721 | int tout = 50; | |
8722 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | |
8723 | ||
8724 | if (!bp->port.pmf) | |
8725 | return 0; | |
8726 | ||
8727 | /* | |
8728 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 8729 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 | 8730 | * 1. Sync IRS for default SB |
16a5fd92 YM |
8731 | * 2. Sync SP queue - this guarantees us that attention handling started |
8732 | * 3. Wait, that TX disable/enable transaction completes | |
6debea87 | 8733 | * |
16a5fd92 YM |
8734 | * 1+2 guarantee that if DCBx attention was scheduled it already changed |
8735 | * pending bit of transaction from STARTED-->TX_STOPPED, if we already | |
8736 | * received completion for the transaction the state is TX_STOPPED. | |
6debea87 DK |
8737 | * State will return to STARTED after completion of TX_STOPPED-->STARTED |
8738 | * transaction. | |
8739 | */ | |
8740 | ||
8741 | /* make sure default SB ISR is done */ | |
8742 | if (msix) | |
8743 | synchronize_irq(bp->msix_table[0].vector); | |
8744 | else | |
8745 | synchronize_irq(bp->pdev->irq); | |
8746 | ||
8747 | flush_workqueue(bnx2x_wq); | |
8748 | ||
8749 | while (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8750 | BNX2X_F_STATE_STARTED && tout--) | |
8751 | msleep(20); | |
8752 | ||
8753 | if (bnx2x_func_get_state(bp, &bp->func_obj) != | |
8754 | BNX2X_F_STATE_STARTED) { | |
8755 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 | 8756 | BNX2X_ERR("Wrong function state\n"); |
6debea87 DK |
8757 | return -EBUSY; |
8758 | #else | |
8759 | /* | |
8760 | * Failed to complete the transaction in a "good way" | |
8761 | * Force both transactions with CLR bit | |
8762 | */ | |
3b603066 | 8763 | struct bnx2x_func_state_params func_params = {NULL}; |
6debea87 | 8764 | |
51c1a580 | 8765 | DP(NETIF_MSG_IFDOWN, |
6bf07b8e | 8766 | "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n"); |
6debea87 DK |
8767 | |
8768 | func_params.f_obj = &bp->func_obj; | |
8769 | __set_bit(RAMROD_DRV_CLR_ONLY, | |
8770 | &func_params.ramrod_flags); | |
8771 | ||
8772 | /* STARTED-->TX_ST0PPED */ | |
8773 | func_params.cmd = BNX2X_F_CMD_TX_STOP; | |
8774 | bnx2x_func_state_change(bp, &func_params); | |
8775 | ||
8776 | /* TX_ST0PPED-->STARTED */ | |
8777 | func_params.cmd = BNX2X_F_CMD_TX_START; | |
8778 | return bnx2x_func_state_change(bp, &func_params); | |
8779 | #endif | |
8780 | } | |
8781 | ||
8782 | return 0; | |
8783 | } | |
8784 | ||
5d07d868 | 8785 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) |
619c5cb6 VZ |
8786 | { |
8787 | int port = BP_PORT(bp); | |
6383c0b3 AE |
8788 | int i, rc = 0; |
8789 | u8 cos; | |
3b603066 | 8790 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 VZ |
8791 | u32 reset_code; |
8792 | ||
8793 | /* Wait until tx fastpath tasks complete */ | |
8794 | for_each_tx_queue(bp, i) { | |
8795 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
8796 | ||
6383c0b3 | 8797 | for_each_cos_in_tx_queue(fp, cos) |
65565884 | 8798 | rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); |
619c5cb6 VZ |
8799 | #ifdef BNX2X_STOP_ON_ERROR |
8800 | if (rc) | |
8801 | return; | |
8802 | #endif | |
8803 | } | |
8804 | ||
8805 | /* Give HW time to discard old tx messages */ | |
0926d499 | 8806 | usleep_range(1000, 2000); |
619c5cb6 VZ |
8807 | |
8808 | /* Clean all ETH MACs */ | |
15192a8c BW |
8809 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, |
8810 | false); | |
619c5cb6 VZ |
8811 | if (rc < 0) |
8812 | BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); | |
8813 | ||
8814 | /* Clean up UC list */ | |
15192a8c | 8815 | rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, |
619c5cb6 VZ |
8816 | true); |
8817 | if (rc < 0) | |
51c1a580 MS |
8818 | BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", |
8819 | rc); | |
619c5cb6 VZ |
8820 | |
8821 | /* Disable LLH */ | |
8822 | if (!CHIP_IS_E1(bp)) | |
8823 | REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); | |
8824 | ||
8825 | /* Set "drop all" (stop Rx). | |
8826 | * We need to take a netif_addr_lock() here in order to prevent | |
8827 | * a race between the completion code and this code. | |
8828 | */ | |
8829 | netif_addr_lock_bh(bp->dev); | |
8830 | /* Schedule the rx_mode command */ | |
8831 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
8832 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8833 | else | |
8834 | bnx2x_set_storm_rx_mode(bp); | |
8835 | ||
8836 | /* Cleanup multicast configuration */ | |
8837 | rparam.mcast_obj = &bp->mcast_obj; | |
8838 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
8839 | if (rc < 0) | |
8840 | BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); | |
8841 | ||
8842 | netif_addr_unlock_bh(bp->dev); | |
8843 | ||
f1929b01 | 8844 | bnx2x_iov_chip_cleanup(bp); |
619c5cb6 | 8845 | |
6debea87 DK |
8846 | /* |
8847 | * Send the UNLOAD_REQUEST to the MCP. This will return if | |
8848 | * this function should perform FUNC, PORT or COMMON HW | |
8849 | * reset. | |
8850 | */ | |
8851 | reset_code = bnx2x_send_unload_req(bp, unload_mode); | |
8852 | ||
8853 | /* | |
8854 | * (assumption: No Attention from MCP at this stage) | |
16a5fd92 | 8855 | * PMF probably in the middle of TX disable/enable transaction |
6debea87 DK |
8856 | */ |
8857 | rc = bnx2x_func_wait_started(bp); | |
8858 | if (rc) { | |
8859 | BNX2X_ERR("bnx2x_func_wait_started failed\n"); | |
8860 | #ifdef BNX2X_STOP_ON_ERROR | |
8861 | return; | |
8862 | #endif | |
8863 | } | |
8864 | ||
34f80b04 | 8865 | /* Close multi and leading connections |
619c5cb6 VZ |
8866 | * Completions for ramrods are collected in a synchronous way |
8867 | */ | |
55c11941 | 8868 | for_each_eth_queue(bp, i) |
619c5cb6 | 8869 | if (bnx2x_stop_queue(bp, i)) |
523224a3 DK |
8870 | #ifdef BNX2X_STOP_ON_ERROR |
8871 | return; | |
8872 | #else | |
228241eb | 8873 | goto unload_error; |
523224a3 | 8874 | #endif |
55c11941 MS |
8875 | |
8876 | if (CNIC_LOADED(bp)) { | |
8877 | for_each_cnic_queue(bp, i) | |
8878 | if (bnx2x_stop_queue(bp, i)) | |
8879 | #ifdef BNX2X_STOP_ON_ERROR | |
8880 | return; | |
8881 | #else | |
8882 | goto unload_error; | |
8883 | #endif | |
8884 | } | |
8885 | ||
619c5cb6 VZ |
8886 | /* If SP settings didn't get completed so far - something |
8887 | * very wrong has happen. | |
8888 | */ | |
8889 | if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) | |
8890 | BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); | |
a2fbb9ea | 8891 | |
619c5cb6 VZ |
8892 | #ifndef BNX2X_STOP_ON_ERROR |
8893 | unload_error: | |
8894 | #endif | |
523224a3 | 8895 | rc = bnx2x_func_stop(bp); |
da5a662a | 8896 | if (rc) { |
523224a3 | 8897 | BNX2X_ERR("Function stop failed!\n"); |
da5a662a | 8898 | #ifdef BNX2X_STOP_ON_ERROR |
523224a3 | 8899 | return; |
523224a3 | 8900 | #endif |
34f80b04 | 8901 | } |
a2fbb9ea | 8902 | |
523224a3 DK |
8903 | /* Disable HW interrupts, NAPI */ |
8904 | bnx2x_netif_stop(bp, 1); | |
26614ba5 MS |
8905 | /* Delete all NAPI objects */ |
8906 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
8907 | if (CNIC_LOADED(bp)) |
8908 | bnx2x_del_all_napi_cnic(bp); | |
523224a3 DK |
8909 | |
8910 | /* Release IRQs */ | |
d6214d7a | 8911 | bnx2x_free_irq(bp); |
523224a3 | 8912 | |
a2fbb9ea | 8913 | /* Reset the chip */ |
619c5cb6 VZ |
8914 | rc = bnx2x_reset_hw(bp, reset_code); |
8915 | if (rc) | |
8916 | BNX2X_ERR("HW_RESET failed\n"); | |
a2fbb9ea | 8917 | |
619c5cb6 | 8918 | /* Report UNLOAD_DONE to MCP */ |
5d07d868 | 8919 | bnx2x_send_unload_done(bp, keep_link); |
72fd0718 VZ |
8920 | } |
8921 | ||
9f6c9258 | 8922 | void bnx2x_disable_close_the_gate(struct bnx2x *bp) |
72fd0718 VZ |
8923 | { |
8924 | u32 val; | |
8925 | ||
51c1a580 | 8926 | DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); |
72fd0718 VZ |
8927 | |
8928 | if (CHIP_IS_E1(bp)) { | |
8929 | int port = BP_PORT(bp); | |
8930 | u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | |
8931 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | |
8932 | ||
8933 | val = REG_RD(bp, addr); | |
8934 | val &= ~(0x300); | |
8935 | REG_WR(bp, addr, val); | |
619c5cb6 | 8936 | } else { |
72fd0718 VZ |
8937 | val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); |
8938 | val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | | |
8939 | MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); | |
8940 | REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); | |
8941 | } | |
8942 | } | |
8943 | ||
72fd0718 VZ |
8944 | /* Close gates #2, #3 and #4: */ |
8945 | static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) | |
8946 | { | |
c9ee9206 | 8947 | u32 val; |
72fd0718 VZ |
8948 | |
8949 | /* Gates #2 and #4a are closed/opened for "not E1" only */ | |
8950 | if (!CHIP_IS_E1(bp)) { | |
8951 | /* #4 */ | |
c9ee9206 | 8952 | REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); |
72fd0718 | 8953 | /* #2 */ |
c9ee9206 | 8954 | REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); |
72fd0718 VZ |
8955 | } |
8956 | ||
8957 | /* #3 */ | |
c9ee9206 VZ |
8958 | if (CHIP_IS_E1x(bp)) { |
8959 | /* Prevent interrupts from HC on both ports */ | |
8960 | val = REG_RD(bp, HC_REG_CONFIG_1); | |
8961 | REG_WR(bp, HC_REG_CONFIG_1, | |
8962 | (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : | |
8963 | (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); | |
8964 | ||
8965 | val = REG_RD(bp, HC_REG_CONFIG_0); | |
8966 | REG_WR(bp, HC_REG_CONFIG_0, | |
8967 | (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : | |
8968 | (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); | |
8969 | } else { | |
d82603c6 | 8970 | /* Prevent incoming interrupts in IGU */ |
c9ee9206 VZ |
8971 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
8972 | ||
8973 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, | |
8974 | (!close) ? | |
8975 | (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : | |
8976 | (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); | |
8977 | } | |
72fd0718 | 8978 | |
51c1a580 | 8979 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", |
72fd0718 VZ |
8980 | close ? "closing" : "opening"); |
8981 | mmiowb(); | |
8982 | } | |
8983 | ||
8984 | #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ | |
8985 | ||
8986 | static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) | |
8987 | { | |
8988 | /* Do some magic... */ | |
8989 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); | |
8990 | *magic_val = val & SHARED_MF_CLP_MAGIC; | |
8991 | MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); | |
8992 | } | |
8993 | ||
e8920674 DK |
8994 | /** |
8995 | * bnx2x_clp_reset_done - restore the value of the `magic' bit. | |
72fd0718 | 8996 | * |
e8920674 DK |
8997 | * @bp: driver handle |
8998 | * @magic_val: old value of the `magic' bit. | |
72fd0718 VZ |
8999 | */ |
9000 | static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) | |
9001 | { | |
9002 | /* Restore the `magic' bit value... */ | |
72fd0718 VZ |
9003 | u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); |
9004 | MF_CFG_WR(bp, shared_mf_config.clp_mb, | |
9005 | (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); | |
9006 | } | |
9007 | ||
f85582f8 | 9008 | /** |
e8920674 | 9009 | * bnx2x_reset_mcp_prep - prepare for MCP reset. |
72fd0718 | 9010 | * |
e8920674 DK |
9011 | * @bp: driver handle |
9012 | * @magic_val: old value of 'magic' bit. | |
9013 | * | |
9014 | * Takes care of CLP configurations. | |
72fd0718 VZ |
9015 | */ |
9016 | static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) | |
9017 | { | |
9018 | u32 shmem; | |
9019 | u32 validity_offset; | |
9020 | ||
51c1a580 | 9021 | DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); |
72fd0718 VZ |
9022 | |
9023 | /* Set `magic' bit in order to save MF config */ | |
9024 | if (!CHIP_IS_E1(bp)) | |
9025 | bnx2x_clp_reset_prep(bp, magic_val); | |
9026 | ||
9027 | /* Get shmem offset */ | |
9028 | shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
c55e771b BW |
9029 | validity_offset = |
9030 | offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); | |
72fd0718 VZ |
9031 | |
9032 | /* Clear validity map flags */ | |
9033 | if (shmem > 0) | |
9034 | REG_WR(bp, shmem + validity_offset, 0); | |
9035 | } | |
9036 | ||
9037 | #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ | |
9038 | #define MCP_ONE_TIMEOUT 100 /* 100 ms */ | |
9039 | ||
e8920674 DK |
9040 | /** |
9041 | * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT | |
72fd0718 | 9042 | * |
e8920674 | 9043 | * @bp: driver handle |
72fd0718 | 9044 | */ |
1191cb83 | 9045 | static void bnx2x_mcp_wait_one(struct bnx2x *bp) |
72fd0718 VZ |
9046 | { |
9047 | /* special handling for emulation and FPGA, | |
9048 | wait 10 times longer */ | |
9049 | if (CHIP_REV_IS_SLOW(bp)) | |
9050 | msleep(MCP_ONE_TIMEOUT*10); | |
9051 | else | |
9052 | msleep(MCP_ONE_TIMEOUT); | |
9053 | } | |
9054 | ||
1b6e2ceb DK |
9055 | /* |
9056 | * initializes bp->common.shmem_base and waits for validity signature to appear | |
9057 | */ | |
9058 | static int bnx2x_init_shmem(struct bnx2x *bp) | |
72fd0718 | 9059 | { |
1b6e2ceb DK |
9060 | int cnt = 0; |
9061 | u32 val = 0; | |
72fd0718 | 9062 | |
1b6e2ceb DK |
9063 | do { |
9064 | bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); | |
9065 | if (bp->common.shmem_base) { | |
9066 | val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); | |
9067 | if (val & SHR_MEM_VALIDITY_MB) | |
9068 | return 0; | |
9069 | } | |
72fd0718 | 9070 | |
1b6e2ceb | 9071 | bnx2x_mcp_wait_one(bp); |
72fd0718 | 9072 | |
1b6e2ceb | 9073 | } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); |
72fd0718 | 9074 | |
1b6e2ceb | 9075 | BNX2X_ERR("BAD MCP validity signature\n"); |
72fd0718 | 9076 | |
1b6e2ceb DK |
9077 | return -ENODEV; |
9078 | } | |
72fd0718 | 9079 | |
1b6e2ceb DK |
9080 | static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) |
9081 | { | |
9082 | int rc = bnx2x_init_shmem(bp); | |
72fd0718 | 9083 | |
72fd0718 VZ |
9084 | /* Restore the `magic' bit value */ |
9085 | if (!CHIP_IS_E1(bp)) | |
9086 | bnx2x_clp_reset_done(bp, magic_val); | |
9087 | ||
9088 | return rc; | |
9089 | } | |
9090 | ||
9091 | static void bnx2x_pxp_prep(struct bnx2x *bp) | |
9092 | { | |
9093 | if (!CHIP_IS_E1(bp)) { | |
9094 | REG_WR(bp, PXP2_REG_RD_START_INIT, 0); | |
9095 | REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); | |
72fd0718 VZ |
9096 | mmiowb(); |
9097 | } | |
9098 | } | |
9099 | ||
9100 | /* | |
9101 | * Reset the whole chip except for: | |
9102 | * - PCIE core | |
9103 | * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by | |
9104 | * one reset bit) | |
9105 | * - IGU | |
9106 | * - MISC (including AEU) | |
9107 | * - GRC | |
9108 | * - RBCN, RBCP | |
9109 | */ | |
c9ee9206 | 9110 | static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) |
72fd0718 VZ |
9111 | { |
9112 | u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; | |
8736c826 | 9113 | u32 global_bits2, stay_reset2; |
c9ee9206 VZ |
9114 | |
9115 | /* | |
9116 | * Bits that have to be set in reset_mask2 if we want to reset 'global' | |
9117 | * (per chip) blocks. | |
9118 | */ | |
9119 | global_bits2 = | |
9120 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | | |
9121 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; | |
72fd0718 | 9122 | |
c55e771b BW |
9123 | /* Don't reset the following blocks. |
9124 | * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be | |
9125 | * reset, as in 4 port device they might still be owned | |
9126 | * by the MCP (there is only one leader per path). | |
9127 | */ | |
72fd0718 VZ |
9128 | not_reset_mask1 = |
9129 | MISC_REGISTERS_RESET_REG_1_RST_HC | | |
9130 | MISC_REGISTERS_RESET_REG_1_RST_PXPV | | |
9131 | MISC_REGISTERS_RESET_REG_1_RST_PXP; | |
9132 | ||
9133 | not_reset_mask2 = | |
c9ee9206 | 9134 | MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | |
72fd0718 VZ |
9135 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | |
9136 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | | |
9137 | MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | | |
9138 | MISC_REGISTERS_RESET_REG_2_RST_RBCN | | |
9139 | MISC_REGISTERS_RESET_REG_2_RST_GRC | | |
9140 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | | |
8736c826 VZ |
9141 | MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | |
9142 | MISC_REGISTERS_RESET_REG_2_RST_ATC | | |
c55e771b BW |
9143 | MISC_REGISTERS_RESET_REG_2_PGLC | |
9144 | MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | | |
9145 | MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | | |
9146 | MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | | |
9147 | MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | | |
9148 | MISC_REGISTERS_RESET_REG_2_UMAC0 | | |
9149 | MISC_REGISTERS_RESET_REG_2_UMAC1; | |
72fd0718 | 9150 | |
8736c826 VZ |
9151 | /* |
9152 | * Keep the following blocks in reset: | |
9153 | * - all xxMACs are handled by the bnx2x_link code. | |
9154 | */ | |
9155 | stay_reset2 = | |
8736c826 VZ |
9156 | MISC_REGISTERS_RESET_REG_2_XMAC | |
9157 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; | |
9158 | ||
9159 | /* Full reset masks according to the chip */ | |
72fd0718 VZ |
9160 | reset_mask1 = 0xffffffff; |
9161 | ||
9162 | if (CHIP_IS_E1(bp)) | |
9163 | reset_mask2 = 0xffff; | |
8736c826 | 9164 | else if (CHIP_IS_E1H(bp)) |
72fd0718 | 9165 | reset_mask2 = 0x1ffff; |
8736c826 VZ |
9166 | else if (CHIP_IS_E2(bp)) |
9167 | reset_mask2 = 0xfffff; | |
9168 | else /* CHIP_IS_E3 */ | |
9169 | reset_mask2 = 0x3ffffff; | |
c9ee9206 VZ |
9170 | |
9171 | /* Don't reset global blocks unless we need to */ | |
9172 | if (!global) | |
9173 | reset_mask2 &= ~global_bits2; | |
9174 | ||
9175 | /* | |
9176 | * In case of attention in the QM, we need to reset PXP | |
9177 | * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM | |
9178 | * because otherwise QM reset would release 'close the gates' shortly | |
9179 | * before resetting the PXP, then the PSWRQ would send a write | |
9180 | * request to PGLUE. Then when PXP is reset, PGLUE would try to | |
9181 | * read the payload data from PSWWR, but PSWWR would not | |
9182 | * respond. The write queue in PGLUE would stuck, dmae commands | |
9183 | * would not return. Therefore it's important to reset the second | |
9184 | * reset register (containing the | |
9185 | * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the | |
9186 | * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM | |
9187 | * bit). | |
9188 | */ | |
72fd0718 VZ |
9189 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
9190 | reset_mask2 & (~not_reset_mask2)); | |
9191 | ||
c9ee9206 VZ |
9192 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, |
9193 | reset_mask1 & (~not_reset_mask1)); | |
9194 | ||
72fd0718 VZ |
9195 | barrier(); |
9196 | mmiowb(); | |
9197 | ||
8736c826 VZ |
9198 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
9199 | reset_mask2 & (~stay_reset2)); | |
9200 | ||
9201 | barrier(); | |
9202 | mmiowb(); | |
9203 | ||
c9ee9206 | 9204 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); |
72fd0718 VZ |
9205 | mmiowb(); |
9206 | } | |
9207 | ||
c9ee9206 VZ |
9208 | /** |
9209 | * bnx2x_er_poll_igu_vq - poll for pending writes bit. | |
9210 | * It should get cleared in no more than 1s. | |
9211 | * | |
9212 | * @bp: driver handle | |
9213 | * | |
9214 | * It should get cleared in no more than 1s. Returns 0 if | |
9215 | * pending writes bit gets cleared. | |
9216 | */ | |
9217 | static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) | |
9218 | { | |
9219 | u32 cnt = 1000; | |
9220 | u32 pend_bits = 0; | |
9221 | ||
9222 | do { | |
9223 | pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); | |
9224 | ||
9225 | if (pend_bits == 0) | |
9226 | break; | |
9227 | ||
0926d499 | 9228 | usleep_range(1000, 2000); |
c9ee9206 VZ |
9229 | } while (cnt-- > 0); |
9230 | ||
9231 | if (cnt <= 0) { | |
9232 | BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", | |
9233 | pend_bits); | |
9234 | return -EBUSY; | |
9235 | } | |
9236 | ||
9237 | return 0; | |
9238 | } | |
9239 | ||
9240 | static int bnx2x_process_kill(struct bnx2x *bp, bool global) | |
72fd0718 VZ |
9241 | { |
9242 | int cnt = 1000; | |
9243 | u32 val = 0; | |
9244 | u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; | |
2de67439 | 9245 | u32 tags_63_32 = 0; |
72fd0718 VZ |
9246 | |
9247 | /* Empty the Tetris buffer, wait for 1s */ | |
9248 | do { | |
9249 | sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); | |
9250 | blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); | |
9251 | port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); | |
9252 | port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); | |
9253 | pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); | |
c55e771b BW |
9254 | if (CHIP_IS_E3(bp)) |
9255 | tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); | |
9256 | ||
72fd0718 VZ |
9257 | if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && |
9258 | ((port_is_idle_0 & 0x1) == 0x1) && | |
9259 | ((port_is_idle_1 & 0x1) == 0x1) && | |
c55e771b BW |
9260 | (pgl_exp_rom2 == 0xffffffff) && |
9261 | (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) | |
72fd0718 | 9262 | break; |
0926d499 | 9263 | usleep_range(1000, 2000); |
72fd0718 VZ |
9264 | } while (cnt-- > 0); |
9265 | ||
9266 | if (cnt <= 0) { | |
51c1a580 MS |
9267 | BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); |
9268 | BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", | |
72fd0718 VZ |
9269 | sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, |
9270 | pgl_exp_rom2); | |
9271 | return -EAGAIN; | |
9272 | } | |
9273 | ||
9274 | barrier(); | |
9275 | ||
9276 | /* Close gates #2, #3 and #4 */ | |
9277 | bnx2x_set_234_gates(bp, true); | |
9278 | ||
c9ee9206 VZ |
9279 | /* Poll for IGU VQs for 57712 and newer chips */ |
9280 | if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) | |
9281 | return -EAGAIN; | |
9282 | ||
72fd0718 VZ |
9283 | /* TBD: Indicate that "process kill" is in progress to MCP */ |
9284 | ||
9285 | /* Clear "unprepared" bit */ | |
9286 | REG_WR(bp, MISC_REG_UNPREPARED, 0); | |
9287 | barrier(); | |
9288 | ||
9289 | /* Make sure all is written to the chip before the reset */ | |
9290 | mmiowb(); | |
9291 | ||
9292 | /* Wait for 1ms to empty GLUE and PCI-E core queues, | |
9293 | * PSWHST, GRC and PSWRD Tetris buffer. | |
9294 | */ | |
0926d499 | 9295 | usleep_range(1000, 2000); |
72fd0718 VZ |
9296 | |
9297 | /* Prepare to chip reset: */ | |
9298 | /* MCP */ | |
c9ee9206 VZ |
9299 | if (global) |
9300 | bnx2x_reset_mcp_prep(bp, &val); | |
72fd0718 VZ |
9301 | |
9302 | /* PXP */ | |
9303 | bnx2x_pxp_prep(bp); | |
9304 | barrier(); | |
9305 | ||
9306 | /* reset the chip */ | |
c9ee9206 | 9307 | bnx2x_process_kill_chip_reset(bp, global); |
72fd0718 VZ |
9308 | barrier(); |
9309 | ||
9310 | /* Recover after reset: */ | |
9311 | /* MCP */ | |
c9ee9206 | 9312 | if (global && bnx2x_reset_mcp_comp(bp, val)) |
72fd0718 VZ |
9313 | return -EAGAIN; |
9314 | ||
c9ee9206 VZ |
9315 | /* TBD: Add resetting the NO_MCP mode DB here */ |
9316 | ||
72fd0718 VZ |
9317 | /* Open the gates #2, #3 and #4 */ |
9318 | bnx2x_set_234_gates(bp, false); | |
9319 | ||
9320 | /* TBD: IGU/AEU preparation bring back the AEU/IGU to a | |
9321 | * reset state, re-enable attentions. */ | |
9322 | ||
a2fbb9ea ET |
9323 | return 0; |
9324 | } | |
9325 | ||
910cc727 | 9326 | static int bnx2x_leader_reset(struct bnx2x *bp) |
72fd0718 VZ |
9327 | { |
9328 | int rc = 0; | |
c9ee9206 | 9329 | bool global = bnx2x_reset_is_global(bp); |
95c6c616 AE |
9330 | u32 load_code; |
9331 | ||
9332 | /* if not going to reset MCP - load "fake" driver to reset HW while | |
9333 | * driver is owner of the HW | |
9334 | */ | |
9335 | if (!global && !BP_NOMCP(bp)) { | |
5d07d868 YM |
9336 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, |
9337 | DRV_MSG_CODE_LOAD_REQ_WITH_LFA); | |
95c6c616 AE |
9338 | if (!load_code) { |
9339 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9340 | rc = -EAGAIN; | |
9341 | goto exit_leader_reset; | |
9342 | } | |
9343 | if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && | |
9344 | (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { | |
9345 | BNX2X_ERR("MCP unexpected resp, aborting\n"); | |
9346 | rc = -EAGAIN; | |
9347 | goto exit_leader_reset2; | |
9348 | } | |
9349 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); | |
9350 | if (!load_code) { | |
9351 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9352 | rc = -EAGAIN; | |
9353 | goto exit_leader_reset2; | |
9354 | } | |
9355 | } | |
c9ee9206 | 9356 | |
72fd0718 | 9357 | /* Try to recover after the failure */ |
c9ee9206 | 9358 | if (bnx2x_process_kill(bp, global)) { |
51c1a580 MS |
9359 | BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", |
9360 | BP_PATH(bp)); | |
72fd0718 | 9361 | rc = -EAGAIN; |
95c6c616 | 9362 | goto exit_leader_reset2; |
72fd0718 VZ |
9363 | } |
9364 | ||
c9ee9206 VZ |
9365 | /* |
9366 | * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver | |
9367 | * state. | |
9368 | */ | |
72fd0718 | 9369 | bnx2x_set_reset_done(bp); |
c9ee9206 VZ |
9370 | if (global) |
9371 | bnx2x_clear_reset_global(bp); | |
72fd0718 | 9372 | |
95c6c616 AE |
9373 | exit_leader_reset2: |
9374 | /* unload "fake driver" if it was loaded */ | |
9375 | if (!global && !BP_NOMCP(bp)) { | |
9376 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); | |
9377 | bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); | |
9378 | } | |
72fd0718 VZ |
9379 | exit_leader_reset: |
9380 | bp->is_leader = 0; | |
c9ee9206 VZ |
9381 | bnx2x_release_leader_lock(bp); |
9382 | smp_mb(); | |
72fd0718 VZ |
9383 | return rc; |
9384 | } | |
9385 | ||
1191cb83 | 9386 | static void bnx2x_recovery_failed(struct bnx2x *bp) |
c9ee9206 VZ |
9387 | { |
9388 | netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); | |
9389 | ||
9390 | /* Disconnect this device */ | |
9391 | netif_device_detach(bp->dev); | |
9392 | ||
9393 | /* | |
9394 | * Block ifup for all function on this engine until "process kill" | |
9395 | * or power cycle. | |
9396 | */ | |
9397 | bnx2x_set_reset_in_progress(bp); | |
9398 | ||
9399 | /* Shut down the power */ | |
9400 | bnx2x_set_power_state(bp, PCI_D3hot); | |
9401 | ||
9402 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
9403 | ||
9404 | smp_mb(); | |
9405 | } | |
9406 | ||
9407 | /* | |
9408 | * Assumption: runs under rtnl lock. This together with the fact | |
6383c0b3 | 9409 | * that it's called only from bnx2x_sp_rtnl() ensure that it |
72fd0718 VZ |
9410 | * will never be called when netif_running(bp->dev) is false. |
9411 | */ | |
9412 | static void bnx2x_parity_recover(struct bnx2x *bp) | |
9413 | { | |
c9ee9206 | 9414 | bool global = false; |
7a752993 | 9415 | u32 error_recovered, error_unrecovered; |
95c6c616 | 9416 | bool is_parity; |
c9ee9206 | 9417 | |
72fd0718 VZ |
9418 | DP(NETIF_MSG_HW, "Handling parity\n"); |
9419 | while (1) { | |
9420 | switch (bp->recovery_state) { | |
9421 | case BNX2X_RECOVERY_INIT: | |
9422 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); | |
95c6c616 AE |
9423 | is_parity = bnx2x_chk_parity_attn(bp, &global, false); |
9424 | WARN_ON(!is_parity); | |
c9ee9206 | 9425 | |
72fd0718 | 9426 | /* Try to get a LEADER_LOCK HW lock */ |
c9ee9206 VZ |
9427 | if (bnx2x_trylock_leader_lock(bp)) { |
9428 | bnx2x_set_reset_in_progress(bp); | |
9429 | /* | |
9430 | * Check if there is a global attention and if | |
9431 | * there was a global attention, set the global | |
9432 | * reset bit. | |
9433 | */ | |
9434 | ||
9435 | if (global) | |
9436 | bnx2x_set_reset_global(bp); | |
9437 | ||
72fd0718 | 9438 | bp->is_leader = 1; |
c9ee9206 | 9439 | } |
72fd0718 VZ |
9440 | |
9441 | /* Stop the driver */ | |
9442 | /* If interface has been removed - break */ | |
5d07d868 | 9443 | if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) |
72fd0718 VZ |
9444 | return; |
9445 | ||
9446 | bp->recovery_state = BNX2X_RECOVERY_WAIT; | |
c9ee9206 | 9447 | |
c9ee9206 VZ |
9448 | /* Ensure "is_leader", MCP command sequence and |
9449 | * "recovery_state" update values are seen on other | |
9450 | * CPUs. | |
72fd0718 | 9451 | */ |
c9ee9206 | 9452 | smp_mb(); |
72fd0718 VZ |
9453 | break; |
9454 | ||
9455 | case BNX2X_RECOVERY_WAIT: | |
9456 | DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); | |
9457 | if (bp->is_leader) { | |
c9ee9206 | 9458 | int other_engine = BP_PATH(bp) ? 0 : 1; |
889b9af3 AE |
9459 | bool other_load_status = |
9460 | bnx2x_get_load_status(bp, other_engine); | |
9461 | bool load_status = | |
9462 | bnx2x_get_load_status(bp, BP_PATH(bp)); | |
c9ee9206 VZ |
9463 | global = bnx2x_reset_is_global(bp); |
9464 | ||
9465 | /* | |
9466 | * In case of a parity in a global block, let | |
9467 | * the first leader that performs a | |
9468 | * leader_reset() reset the global blocks in | |
9469 | * order to clear global attentions. Otherwise | |
16a5fd92 | 9470 | * the gates will remain closed for that |
c9ee9206 VZ |
9471 | * engine. |
9472 | */ | |
889b9af3 AE |
9473 | if (load_status || |
9474 | (global && other_load_status)) { | |
72fd0718 VZ |
9475 | /* Wait until all other functions get |
9476 | * down. | |
9477 | */ | |
7be08a72 | 9478 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9479 | HZ/10); |
9480 | return; | |
9481 | } else { | |
9482 | /* If all other functions got down - | |
9483 | * try to bring the chip back to | |
9484 | * normal. In any case it's an exit | |
9485 | * point for a leader. | |
9486 | */ | |
c9ee9206 VZ |
9487 | if (bnx2x_leader_reset(bp)) { |
9488 | bnx2x_recovery_failed(bp); | |
72fd0718 VZ |
9489 | return; |
9490 | } | |
9491 | ||
c9ee9206 VZ |
9492 | /* If we are here, means that the |
9493 | * leader has succeeded and doesn't | |
9494 | * want to be a leader any more. Try | |
9495 | * to continue as a none-leader. | |
9496 | */ | |
9497 | break; | |
72fd0718 VZ |
9498 | } |
9499 | } else { /* non-leader */ | |
c9ee9206 | 9500 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { |
72fd0718 VZ |
9501 | /* Try to get a LEADER_LOCK HW lock as |
9502 | * long as a former leader may have | |
9503 | * been unloaded by the user or | |
9504 | * released a leadership by another | |
9505 | * reason. | |
9506 | */ | |
c9ee9206 | 9507 | if (bnx2x_trylock_leader_lock(bp)) { |
72fd0718 VZ |
9508 | /* I'm a leader now! Restart a |
9509 | * switch case. | |
9510 | */ | |
9511 | bp->is_leader = 1; | |
9512 | break; | |
9513 | } | |
9514 | ||
7be08a72 | 9515 | schedule_delayed_work(&bp->sp_rtnl_task, |
72fd0718 VZ |
9516 | HZ/10); |
9517 | return; | |
9518 | ||
c9ee9206 VZ |
9519 | } else { |
9520 | /* | |
9521 | * If there was a global attention, wait | |
9522 | * for it to be cleared. | |
9523 | */ | |
9524 | if (bnx2x_reset_is_global(bp)) { | |
9525 | schedule_delayed_work( | |
7be08a72 AE |
9526 | &bp->sp_rtnl_task, |
9527 | HZ/10); | |
c9ee9206 VZ |
9528 | return; |
9529 | } | |
9530 | ||
7a752993 AE |
9531 | error_recovered = |
9532 | bp->eth_stats.recoverable_error; | |
9533 | error_unrecovered = | |
9534 | bp->eth_stats.unrecoverable_error; | |
95c6c616 AE |
9535 | bp->recovery_state = |
9536 | BNX2X_RECOVERY_NIC_LOADING; | |
9537 | if (bnx2x_nic_load(bp, LOAD_NORMAL)) { | |
7a752993 | 9538 | error_unrecovered++; |
95c6c616 | 9539 | netdev_err(bp->dev, |
51c1a580 | 9540 | "Recovery failed. Power cycle needed\n"); |
95c6c616 AE |
9541 | /* Disconnect this device */ |
9542 | netif_device_detach(bp->dev); | |
9543 | /* Shut down the power */ | |
9544 | bnx2x_set_power_state( | |
9545 | bp, PCI_D3hot); | |
9546 | smp_mb(); | |
9547 | } else { | |
c9ee9206 VZ |
9548 | bp->recovery_state = |
9549 | BNX2X_RECOVERY_DONE; | |
7a752993 | 9550 | error_recovered++; |
c9ee9206 VZ |
9551 | smp_mb(); |
9552 | } | |
7a752993 AE |
9553 | bp->eth_stats.recoverable_error = |
9554 | error_recovered; | |
9555 | bp->eth_stats.unrecoverable_error = | |
9556 | error_unrecovered; | |
c9ee9206 | 9557 | |
72fd0718 VZ |
9558 | return; |
9559 | } | |
9560 | } | |
9561 | default: | |
9562 | return; | |
9563 | } | |
9564 | } | |
9565 | } | |
9566 | ||
56ad3152 MS |
9567 | static int bnx2x_close(struct net_device *dev); |
9568 | ||
72fd0718 VZ |
9569 | /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is |
9570 | * scheduled on a general queue in order to prevent a dead lock. | |
9571 | */ | |
7be08a72 | 9572 | static void bnx2x_sp_rtnl_task(struct work_struct *work) |
34f80b04 | 9573 | { |
7be08a72 | 9574 | struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); |
34f80b04 EG |
9575 | |
9576 | rtnl_lock(); | |
9577 | ||
8395be5e AE |
9578 | if (!netif_running(bp->dev)) { |
9579 | rtnl_unlock(); | |
9580 | return; | |
9581 | } | |
7be08a72 | 9582 | |
6bf07b8e | 9583 | if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { |
7be08a72 | 9584 | #ifdef BNX2X_STOP_ON_ERROR |
6bf07b8e YM |
9585 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" |
9586 | "you will need to reboot when done\n"); | |
9587 | goto sp_rtnl_not_reset; | |
7be08a72 | 9588 | #endif |
7be08a72 | 9589 | /* |
b1fb8740 VZ |
9590 | * Clear all pending SP commands as we are going to reset the |
9591 | * function anyway. | |
7be08a72 | 9592 | */ |
b1fb8740 VZ |
9593 | bp->sp_rtnl_state = 0; |
9594 | smp_mb(); | |
9595 | ||
72fd0718 | 9596 | bnx2x_parity_recover(bp); |
b1fb8740 | 9597 | |
8395be5e AE |
9598 | rtnl_unlock(); |
9599 | return; | |
b1fb8740 VZ |
9600 | } |
9601 | ||
9602 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { | |
6bf07b8e YM |
9603 | #ifdef BNX2X_STOP_ON_ERROR |
9604 | BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" | |
9605 | "you will need to reboot when done\n"); | |
9606 | goto sp_rtnl_not_reset; | |
9607 | #endif | |
9608 | ||
b1fb8740 VZ |
9609 | /* |
9610 | * Clear all pending SP commands as we are going to reset the | |
9611 | * function anyway. | |
9612 | */ | |
9613 | bp->sp_rtnl_state = 0; | |
9614 | smp_mb(); | |
9615 | ||
5d07d868 | 9616 | bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); |
72fd0718 | 9617 | bnx2x_nic_load(bp, LOAD_NORMAL); |
b1fb8740 | 9618 | |
8395be5e AE |
9619 | rtnl_unlock(); |
9620 | return; | |
72fd0718 | 9621 | } |
b1fb8740 VZ |
9622 | #ifdef BNX2X_STOP_ON_ERROR |
9623 | sp_rtnl_not_reset: | |
9624 | #endif | |
9625 | if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) | |
9626 | bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); | |
a3348722 BW |
9627 | if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) |
9628 | bnx2x_after_function_update(bp); | |
8304859a AE |
9629 | /* |
9630 | * in case of fan failure we need to reset id if the "stop on error" | |
9631 | * debug flag is set, since we trying to prevent permanent overheating | |
9632 | * damage | |
9633 | */ | |
9634 | if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { | |
51c1a580 | 9635 | DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); |
8304859a AE |
9636 | netif_device_detach(bp->dev); |
9637 | bnx2x_close(bp->dev); | |
8395be5e AE |
9638 | rtnl_unlock(); |
9639 | return; | |
8304859a AE |
9640 | } |
9641 | ||
381ac16b AE |
9642 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { |
9643 | DP(BNX2X_MSG_SP, | |
9644 | "sending set mcast vf pf channel message from rtnl sp-task\n"); | |
9645 | bnx2x_vfpf_set_mcast(bp->dev); | |
9646 | } | |
78c3bcc5 AE |
9647 | if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, |
9648 | &bp->sp_rtnl_state)){ | |
9649 | if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) { | |
9650 | bnx2x_tx_disable(bp); | |
9651 | BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); | |
9652 | } | |
9653 | } | |
381ac16b | 9654 | |
8b09be5f YM |
9655 | if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { |
9656 | DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); | |
9657 | bnx2x_set_rx_mode_inner(bp); | |
381ac16b AE |
9658 | } |
9659 | ||
3ec9f9ca AE |
9660 | if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, |
9661 | &bp->sp_rtnl_state)) | |
9662 | bnx2x_pf_set_vfs_vlan(bp); | |
9663 | ||
07b4eb3b DK |
9664 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) |
9665 | bnx2x_dcbx_stop_hw_tx(bp); | |
9666 | ||
9667 | if (test_and_clear_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state)) | |
9668 | bnx2x_dcbx_resume_hw_tx(bp); | |
9669 | ||
8395be5e AE |
9670 | /* work which needs rtnl lock not-taken (as it takes the lock itself and |
9671 | * can be called from other contexts as well) | |
9672 | */ | |
34f80b04 | 9673 | rtnl_unlock(); |
8395be5e | 9674 | |
6411280a | 9675 | /* enable SR-IOV if applicable */ |
8395be5e | 9676 | if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, |
3c76feff AE |
9677 | &bp->sp_rtnl_state)) { |
9678 | bnx2x_disable_sriov(bp); | |
6411280a | 9679 | bnx2x_enable_sriov(bp); |
3c76feff | 9680 | } |
34f80b04 EG |
9681 | } |
9682 | ||
3deb8167 YR |
9683 | static void bnx2x_period_task(struct work_struct *work) |
9684 | { | |
9685 | struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); | |
9686 | ||
9687 | if (!netif_running(bp->dev)) | |
9688 | goto period_task_exit; | |
9689 | ||
9690 | if (CHIP_REV_IS_SLOW(bp)) { | |
9691 | BNX2X_ERR("period task called on emulation, ignoring\n"); | |
9692 | goto period_task_exit; | |
9693 | } | |
9694 | ||
9695 | bnx2x_acquire_phy_lock(bp); | |
9696 | /* | |
9697 | * The barrier is needed to ensure the ordering between the writing to | |
9698 | * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and | |
9699 | * the reading here. | |
9700 | */ | |
9701 | smp_mb(); | |
9702 | if (bp->port.pmf) { | |
9703 | bnx2x_period_func(&bp->link_params, &bp->link_vars); | |
9704 | ||
9705 | /* Re-queue task in 1 sec */ | |
9706 | queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); | |
9707 | } | |
9708 | ||
9709 | bnx2x_release_phy_lock(bp); | |
9710 | period_task_exit: | |
9711 | return; | |
9712 | } | |
9713 | ||
a2fbb9ea ET |
9714 | /* |
9715 | * Init service functions | |
9716 | */ | |
9717 | ||
b56e9670 | 9718 | u32 bnx2x_get_pretend_reg(struct bnx2x *bp) |
f2e0899f DK |
9719 | { |
9720 | u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; | |
9721 | u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; | |
9722 | return base + (BP_ABS_FUNC(bp)) * stride; | |
f1ef27ef EG |
9723 | } |
9724 | ||
1ef1d45a BW |
9725 | static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, |
9726 | struct bnx2x_mac_vals *vals) | |
34f80b04 | 9727 | { |
452427b0 YM |
9728 | u32 val, base_addr, offset, mask, reset_reg; |
9729 | bool mac_stopped = false; | |
9730 | u8 port = BP_PORT(bp); | |
34f80b04 | 9731 | |
1ef1d45a BW |
9732 | /* reset addresses as they also mark which values were changed */ |
9733 | vals->bmac_addr = 0; | |
9734 | vals->umac_addr = 0; | |
9735 | vals->xmac_addr = 0; | |
9736 | vals->emac_addr = 0; | |
9737 | ||
452427b0 | 9738 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); |
f16da43b | 9739 | |
452427b0 YM |
9740 | if (!CHIP_IS_E3(bp)) { |
9741 | val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); | |
9742 | mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; | |
9743 | if ((mask & reset_reg) && val) { | |
9744 | u32 wb_data[2]; | |
9745 | BNX2X_DEV_INFO("Disable bmac Rx\n"); | |
9746 | base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM | |
9747 | : NIG_REG_INGRESS_BMAC0_MEM; | |
9748 | offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL | |
9749 | : BIGMAC_REGISTER_BMAC_CONTROL; | |
7a06a122 | 9750 | |
452427b0 YM |
9751 | /* |
9752 | * use rd/wr since we cannot use dmae. This is safe | |
9753 | * since MCP won't access the bus due to the request | |
9754 | * to unload, and no function on the path can be | |
9755 | * loaded at this time. | |
9756 | */ | |
9757 | wb_data[0] = REG_RD(bp, base_addr + offset); | |
9758 | wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); | |
1ef1d45a BW |
9759 | vals->bmac_addr = base_addr + offset; |
9760 | vals->bmac_val[0] = wb_data[0]; | |
9761 | vals->bmac_val[1] = wb_data[1]; | |
452427b0 | 9762 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
1ef1d45a BW |
9763 | REG_WR(bp, vals->bmac_addr, wb_data[0]); |
9764 | REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); | |
452427b0 YM |
9765 | } |
9766 | BNX2X_DEV_INFO("Disable emac Rx\n"); | |
1ef1d45a BW |
9767 | vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; |
9768 | vals->emac_val = REG_RD(bp, vals->emac_addr); | |
9769 | REG_WR(bp, vals->emac_addr, 0); | |
452427b0 YM |
9770 | mac_stopped = true; |
9771 | } else { | |
9772 | if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { | |
9773 | BNX2X_DEV_INFO("Disable xmac Rx\n"); | |
9774 | base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
9775 | val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); | |
9776 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9777 | val & ~(1 << 1)); | |
9778 | REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, | |
9779 | val | (1 << 1)); | |
1ef1d45a BW |
9780 | vals->xmac_addr = base_addr + XMAC_REG_CTRL; |
9781 | vals->xmac_val = REG_RD(bp, vals->xmac_addr); | |
9782 | REG_WR(bp, vals->xmac_addr, 0); | |
452427b0 YM |
9783 | mac_stopped = true; |
9784 | } | |
9785 | mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; | |
9786 | if (mask & reset_reg) { | |
9787 | BNX2X_DEV_INFO("Disable umac Rx\n"); | |
9788 | base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1ef1d45a BW |
9789 | vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG; |
9790 | vals->umac_val = REG_RD(bp, vals->umac_addr); | |
9791 | REG_WR(bp, vals->umac_addr, 0); | |
452427b0 YM |
9792 | mac_stopped = true; |
9793 | } | |
9794 | } | |
9795 | ||
9796 | if (mac_stopped) | |
9797 | msleep(20); | |
452427b0 YM |
9798 | } |
9799 | ||
9800 | #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) | |
9801 | #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) | |
9802 | #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) | |
9803 | #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) | |
9804 | ||
1dd06ae8 | 9805 | static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc) |
452427b0 YM |
9806 | { |
9807 | u16 rcq, bd; | |
9808 | u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port)); | |
9809 | ||
9810 | rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; | |
9811 | bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; | |
9812 | ||
9813 | tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); | |
9814 | REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg); | |
9815 | ||
9816 | BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", | |
9817 | port, bd, rcq); | |
9818 | } | |
9819 | ||
0329aba1 | 9820 | static int bnx2x_prev_mcp_done(struct bnx2x *bp) |
452427b0 | 9821 | { |
5d07d868 YM |
9822 | u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, |
9823 | DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); | |
452427b0 YM |
9824 | if (!rc) { |
9825 | BNX2X_ERR("MCP response failure, aborting\n"); | |
9826 | return -EBUSY; | |
9827 | } | |
9828 | ||
9829 | return 0; | |
9830 | } | |
9831 | ||
c63da990 BW |
9832 | static struct bnx2x_prev_path_list * |
9833 | bnx2x_prev_path_get_entry(struct bnx2x *bp) | |
9834 | { | |
9835 | struct bnx2x_prev_path_list *tmp_list; | |
9836 | ||
9837 | list_for_each_entry(tmp_list, &bnx2x_prev_list, list) | |
9838 | if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && | |
9839 | bp->pdev->bus->number == tmp_list->bus && | |
9840 | BP_PATH(bp) == tmp_list->path) | |
9841 | return tmp_list; | |
9842 | ||
9843 | return NULL; | |
9844 | } | |
9845 | ||
7fa6f340 YM |
9846 | static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) |
9847 | { | |
9848 | struct bnx2x_prev_path_list *tmp_list; | |
9849 | int rc; | |
9850 | ||
9851 | rc = down_interruptible(&bnx2x_prev_sem); | |
9852 | if (rc) { | |
9853 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9854 | return rc; | |
9855 | } | |
9856 | ||
9857 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
9858 | if (tmp_list) { | |
9859 | tmp_list->aer = 1; | |
9860 | rc = 0; | |
9861 | } else { | |
9862 | BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", | |
9863 | BP_PATH(bp)); | |
9864 | } | |
9865 | ||
9866 | up(&bnx2x_prev_sem); | |
9867 | ||
9868 | return rc; | |
9869 | } | |
9870 | ||
0329aba1 | 9871 | static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) |
452427b0 YM |
9872 | { |
9873 | struct bnx2x_prev_path_list *tmp_list; | |
9874 | int rc = false; | |
9875 | ||
9876 | if (down_trylock(&bnx2x_prev_sem)) | |
9877 | return false; | |
9878 | ||
7fa6f340 YM |
9879 | tmp_list = bnx2x_prev_path_get_entry(bp); |
9880 | if (tmp_list) { | |
9881 | if (tmp_list->aer) { | |
9882 | DP(NETIF_MSG_HW, "Path %d was marked by AER\n", | |
9883 | BP_PATH(bp)); | |
9884 | } else { | |
452427b0 YM |
9885 | rc = true; |
9886 | BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", | |
9887 | BP_PATH(bp)); | |
452427b0 YM |
9888 | } |
9889 | } | |
9890 | ||
9891 | up(&bnx2x_prev_sem); | |
9892 | ||
9893 | return rc; | |
9894 | } | |
9895 | ||
178135c1 DK |
9896 | bool bnx2x_port_after_undi(struct bnx2x *bp) |
9897 | { | |
9898 | struct bnx2x_prev_path_list *entry; | |
9899 | bool val; | |
9900 | ||
9901 | down(&bnx2x_prev_sem); | |
9902 | ||
9903 | entry = bnx2x_prev_path_get_entry(bp); | |
9904 | val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); | |
9905 | ||
9906 | up(&bnx2x_prev_sem); | |
9907 | ||
9908 | return val; | |
9909 | } | |
9910 | ||
c63da990 | 9911 | static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) |
452427b0 YM |
9912 | { |
9913 | struct bnx2x_prev_path_list *tmp_list; | |
9914 | int rc; | |
9915 | ||
7fa6f340 YM |
9916 | rc = down_interruptible(&bnx2x_prev_sem); |
9917 | if (rc) { | |
9918 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9919 | return rc; | |
9920 | } | |
9921 | ||
9922 | /* Check whether the entry for this path already exists */ | |
9923 | tmp_list = bnx2x_prev_path_get_entry(bp); | |
9924 | if (tmp_list) { | |
9925 | if (!tmp_list->aer) { | |
9926 | BNX2X_ERR("Re-Marking the path.\n"); | |
9927 | } else { | |
9928 | DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", | |
9929 | BP_PATH(bp)); | |
9930 | tmp_list->aer = 0; | |
9931 | } | |
9932 | up(&bnx2x_prev_sem); | |
9933 | return 0; | |
9934 | } | |
9935 | up(&bnx2x_prev_sem); | |
9936 | ||
9937 | /* Create an entry for this path and add it */ | |
ea4b3857 | 9938 | tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); |
452427b0 YM |
9939 | if (!tmp_list) { |
9940 | BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); | |
9941 | return -ENOMEM; | |
9942 | } | |
9943 | ||
9944 | tmp_list->bus = bp->pdev->bus->number; | |
9945 | tmp_list->slot = PCI_SLOT(bp->pdev->devfn); | |
9946 | tmp_list->path = BP_PATH(bp); | |
7fa6f340 | 9947 | tmp_list->aer = 0; |
c63da990 | 9948 | tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; |
452427b0 YM |
9949 | |
9950 | rc = down_interruptible(&bnx2x_prev_sem); | |
9951 | if (rc) { | |
9952 | BNX2X_ERR("Received %d when tried to take lock\n", rc); | |
9953 | kfree(tmp_list); | |
9954 | } else { | |
7fa6f340 YM |
9955 | DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", |
9956 | BP_PATH(bp)); | |
452427b0 YM |
9957 | list_add(&tmp_list->list, &bnx2x_prev_list); |
9958 | up(&bnx2x_prev_sem); | |
9959 | } | |
9960 | ||
9961 | return rc; | |
9962 | } | |
9963 | ||
0329aba1 | 9964 | static int bnx2x_do_flr(struct bnx2x *bp) |
452427b0 | 9965 | { |
452427b0 YM |
9966 | struct pci_dev *dev = bp->pdev; |
9967 | ||
8eee694c YM |
9968 | if (CHIP_IS_E1x(bp)) { |
9969 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); | |
9970 | return -EINVAL; | |
9971 | } | |
9972 | ||
9973 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ | |
9974 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | |
9975 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | |
9976 | bp->common.bc_ver); | |
9977 | return -EINVAL; | |
9978 | } | |
452427b0 | 9979 | |
8903b9eb CL |
9980 | if (!pci_wait_for_pending_transaction(dev)) |
9981 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); | |
452427b0 | 9982 | |
8eee694c | 9983 | BNX2X_DEV_INFO("Initiating FLR\n"); |
452427b0 YM |
9984 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
9985 | ||
9986 | return 0; | |
9987 | } | |
9988 | ||
0329aba1 | 9989 | static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) |
452427b0 YM |
9990 | { |
9991 | int rc; | |
9992 | ||
9993 | BNX2X_DEV_INFO("Uncommon unload Flow\n"); | |
9994 | ||
9995 | /* Test if previous unload process was already finished for this path */ | |
9996 | if (bnx2x_prev_is_path_marked(bp)) | |
9997 | return bnx2x_prev_mcp_done(bp); | |
9998 | ||
04c46736 YM |
9999 | BNX2X_DEV_INFO("Path is unmarked\n"); |
10000 | ||
452427b0 YM |
10001 | /* If function has FLR capabilities, and existing FW version matches |
10002 | * the one required, then FLR will be sufficient to clean any residue | |
10003 | * left by previous driver | |
10004 | */ | |
ad5afc89 | 10005 | rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION); |
8eee694c YM |
10006 | |
10007 | if (!rc) { | |
10008 | /* fw version is good */ | |
10009 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); | |
10010 | rc = bnx2x_do_flr(bp); | |
10011 | } | |
10012 | ||
10013 | if (!rc) { | |
10014 | /* FLR was performed */ | |
10015 | BNX2X_DEV_INFO("FLR successful\n"); | |
10016 | return 0; | |
10017 | } | |
10018 | ||
10019 | BNX2X_DEV_INFO("Could not FLR\n"); | |
452427b0 YM |
10020 | |
10021 | /* Close the MCP request, return failure*/ | |
10022 | rc = bnx2x_prev_mcp_done(bp); | |
10023 | if (!rc) | |
10024 | rc = BNX2X_PREV_WAIT_NEEDED; | |
10025 | ||
10026 | return rc; | |
10027 | } | |
10028 | ||
0329aba1 | 10029 | static int bnx2x_prev_unload_common(struct bnx2x *bp) |
452427b0 YM |
10030 | { |
10031 | u32 reset_reg, tmp_reg = 0, rc; | |
c63da990 | 10032 | bool prev_undi = false; |
1ef1d45a BW |
10033 | struct bnx2x_mac_vals mac_vals; |
10034 | ||
452427b0 YM |
10035 | /* It is possible a previous function received 'common' answer, |
10036 | * but hasn't loaded yet, therefore creating a scenario of | |
10037 | * multiple functions receiving 'common' on the same path. | |
10038 | */ | |
10039 | BNX2X_DEV_INFO("Common unload Flow\n"); | |
10040 | ||
1ef1d45a BW |
10041 | memset(&mac_vals, 0, sizeof(mac_vals)); |
10042 | ||
452427b0 YM |
10043 | if (bnx2x_prev_is_path_marked(bp)) |
10044 | return bnx2x_prev_mcp_done(bp); | |
10045 | ||
10046 | reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); | |
10047 | ||
10048 | /* Reset should be performed after BRB is emptied */ | |
10049 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { | |
10050 | u32 timer_count = 1000; | |
452427b0 YM |
10051 | |
10052 | /* Close the MAC Rx to prevent BRB from filling up */ | |
1ef1d45a BW |
10053 | bnx2x_prev_unload_close_mac(bp, &mac_vals); |
10054 | ||
10055 | /* close LLH filters towards the BRB */ | |
10056 | bnx2x_set_rx_filter(&bp->link_params, 0); | |
452427b0 YM |
10057 | |
10058 | /* Check if the UNDI driver was previously loaded | |
34f80b04 EG |
10059 | * UNDI driver initializes CID offset for normal bell to 0x7 |
10060 | */ | |
452427b0 YM |
10061 | if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { |
10062 | tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | |
10063 | if (tmp_reg == 0x7) { | |
10064 | BNX2X_DEV_INFO("UNDI previously loaded\n"); | |
10065 | prev_undi = true; | |
10066 | /* clear the UNDI indication */ | |
10067 | REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); | |
a74801c5 YM |
10068 | /* clear possible idle check errors */ |
10069 | REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); | |
34f80b04 | 10070 | } |
452427b0 | 10071 | } |
d46f7c4d DK |
10072 | if (!CHIP_IS_E1x(bp)) |
10073 | /* block FW from writing to host */ | |
10074 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); | |
10075 | ||
452427b0 YM |
10076 | /* wait until BRB is empty */ |
10077 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); | |
10078 | while (timer_count) { | |
10079 | u32 prev_brb = tmp_reg; | |
34f80b04 | 10080 | |
452427b0 YM |
10081 | tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); |
10082 | if (!tmp_reg) | |
10083 | break; | |
619c5cb6 | 10084 | |
452427b0 | 10085 | BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); |
619c5cb6 | 10086 | |
452427b0 YM |
10087 | /* reset timer as long as BRB actually gets emptied */ |
10088 | if (prev_brb > tmp_reg) | |
10089 | timer_count = 1000; | |
10090 | else | |
10091 | timer_count--; | |
da5a662a | 10092 | |
452427b0 YM |
10093 | /* If UNDI resides in memory, manually increment it */ |
10094 | if (prev_undi) | |
10095 | bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1); | |
da5a662a | 10096 | |
452427b0 | 10097 | udelay(10); |
7a06a122 | 10098 | } |
452427b0 YM |
10099 | |
10100 | if (!timer_count) | |
10101 | BNX2X_ERR("Failed to empty BRB, hope for the best\n"); | |
34f80b04 | 10102 | } |
f16da43b | 10103 | |
452427b0 YM |
10104 | /* No packets are in the pipeline, path is ready for reset */ |
10105 | bnx2x_reset_common(bp); | |
10106 | ||
1ef1d45a BW |
10107 | if (mac_vals.xmac_addr) |
10108 | REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); | |
10109 | if (mac_vals.umac_addr) | |
10110 | REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val); | |
10111 | if (mac_vals.emac_addr) | |
10112 | REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); | |
10113 | if (mac_vals.bmac_addr) { | |
10114 | REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); | |
10115 | REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); | |
10116 | } | |
10117 | ||
c63da990 | 10118 | rc = bnx2x_prev_mark_path(bp, prev_undi); |
452427b0 YM |
10119 | if (rc) { |
10120 | bnx2x_prev_mcp_done(bp); | |
10121 | return rc; | |
10122 | } | |
10123 | ||
10124 | return bnx2x_prev_mcp_done(bp); | |
10125 | } | |
10126 | ||
24f06716 AE |
10127 | /* previous driver DMAE transaction may have occurred when pre-boot stage ended |
10128 | * and boot began, or when kdump kernel was loaded. Either case would invalidate | |
10129 | * the addresses of the transaction, resulting in was-error bit set in the pci | |
10130 | * causing all hw-to-host pcie transactions to timeout. If this happened we want | |
10131 | * to clear the interrupt which detected this from the pglueb and the was done | |
10132 | * bit | |
10133 | */ | |
0329aba1 | 10134 | static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp) |
24f06716 | 10135 | { |
4a25417c AE |
10136 | if (!CHIP_IS_E1x(bp)) { |
10137 | u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS); | |
10138 | if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { | |
04c46736 YM |
10139 | DP(BNX2X_MSG_SP, |
10140 | "'was error' bit was found to be set in pglueb upon startup. Clearing\n"); | |
4a25417c AE |
10141 | REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, |
10142 | 1 << BP_FUNC(bp)); | |
10143 | } | |
24f06716 AE |
10144 | } |
10145 | } | |
10146 | ||
0329aba1 | 10147 | static int bnx2x_prev_unload(struct bnx2x *bp) |
452427b0 YM |
10148 | { |
10149 | int time_counter = 10; | |
10150 | u32 rc, fw, hw_lock_reg, hw_lock_val; | |
10151 | BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); | |
10152 | ||
24f06716 AE |
10153 | /* clear hw from errors which may have resulted from an interrupted |
10154 | * dmae transaction. | |
10155 | */ | |
10156 | bnx2x_prev_interrupted_dmae(bp); | |
10157 | ||
10158 | /* Release previously held locks */ | |
452427b0 YM |
10159 | hw_lock_reg = (BP_FUNC(bp) <= 5) ? |
10160 | (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : | |
10161 | (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); | |
10162 | ||
3cdeec22 | 10163 | hw_lock_val = REG_RD(bp, hw_lock_reg); |
452427b0 YM |
10164 | if (hw_lock_val) { |
10165 | if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { | |
10166 | BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); | |
10167 | REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, | |
10168 | (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); | |
10169 | } | |
10170 | ||
10171 | BNX2X_DEV_INFO("Release Previously held hw lock\n"); | |
10172 | REG_WR(bp, hw_lock_reg, 0xffffffff); | |
10173 | } else | |
10174 | BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); | |
10175 | ||
10176 | if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { | |
10177 | BNX2X_DEV_INFO("Release previously held alr\n"); | |
3cdeec22 | 10178 | bnx2x_release_alr(bp); |
452427b0 YM |
10179 | } |
10180 | ||
452427b0 | 10181 | do { |
7fa6f340 | 10182 | int aer = 0; |
452427b0 YM |
10183 | /* Lock MCP using an unload request */ |
10184 | fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); | |
10185 | if (!fw) { | |
10186 | BNX2X_ERR("MCP response failure, aborting\n"); | |
10187 | rc = -EBUSY; | |
10188 | break; | |
10189 | } | |
10190 | ||
7fa6f340 YM |
10191 | rc = down_interruptible(&bnx2x_prev_sem); |
10192 | if (rc) { | |
10193 | BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", | |
10194 | rc); | |
10195 | } else { | |
10196 | /* If Path is marked by EEH, ignore unload status */ | |
10197 | aer = !!(bnx2x_prev_path_get_entry(bp) && | |
10198 | bnx2x_prev_path_get_entry(bp)->aer); | |
60cde81f | 10199 | up(&bnx2x_prev_sem); |
7fa6f340 | 10200 | } |
7fa6f340 YM |
10201 | |
10202 | if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { | |
452427b0 YM |
10203 | rc = bnx2x_prev_unload_common(bp); |
10204 | break; | |
10205 | } | |
10206 | ||
16a5fd92 | 10207 | /* non-common reply from MCP might require looping */ |
452427b0 YM |
10208 | rc = bnx2x_prev_unload_uncommon(bp); |
10209 | if (rc != BNX2X_PREV_WAIT_NEEDED) | |
10210 | break; | |
10211 | ||
10212 | msleep(20); | |
10213 | } while (--time_counter); | |
10214 | ||
10215 | if (!time_counter || rc) { | |
10216 | BNX2X_ERR("Failed unloading previous driver, aborting\n"); | |
10217 | rc = -EBUSY; | |
10218 | } | |
10219 | ||
c63da990 | 10220 | /* Mark function if its port was used to boot from SAN */ |
178135c1 | 10221 | if (bnx2x_port_after_undi(bp)) |
c63da990 BW |
10222 | bp->link_params.feature_config_flags |= |
10223 | FEATURE_CONFIG_BOOT_FROM_SAN; | |
10224 | ||
452427b0 YM |
10225 | BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); |
10226 | ||
10227 | return rc; | |
34f80b04 EG |
10228 | } |
10229 | ||
0329aba1 | 10230 | static void bnx2x_get_common_hwinfo(struct bnx2x *bp) |
34f80b04 | 10231 | { |
1d187b34 | 10232 | u32 val, val2, val3, val4, id, boot_mode; |
72ce58c3 | 10233 | u16 pmc; |
34f80b04 EG |
10234 | |
10235 | /* Get the chip revision id and number. */ | |
10236 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | |
10237 | val = REG_RD(bp, MISC_REG_CHIP_NUM); | |
10238 | id = ((val & 0xffff) << 16); | |
10239 | val = REG_RD(bp, MISC_REG_CHIP_REV); | |
10240 | id |= ((val & 0xf) << 12); | |
f22fdf25 YM |
10241 | |
10242 | /* Metal is read from PCI regs, but we can't access >=0x400 from | |
10243 | * the configuration space (so we need to reg_rd) | |
10244 | */ | |
10245 | val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); | |
10246 | id |= (((val >> 24) & 0xf) << 4); | |
5a40e08e | 10247 | val = REG_RD(bp, MISC_REG_BOND_ID); |
34f80b04 EG |
10248 | id |= (val & 0xf); |
10249 | bp->common.chip_id = id; | |
523224a3 | 10250 | |
7e8e02df BW |
10251 | /* force 57811 according to MISC register */ |
10252 | if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { | |
10253 | if (CHIP_IS_57810(bp)) | |
10254 | bp->common.chip_id = (CHIP_NUM_57811 << 16) | | |
10255 | (bp->common.chip_id & 0x0000FFFF); | |
10256 | else if (CHIP_IS_57810_MF(bp)) | |
10257 | bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | | |
10258 | (bp->common.chip_id & 0x0000FFFF); | |
10259 | bp->common.chip_id |= 0x1; | |
10260 | } | |
10261 | ||
523224a3 DK |
10262 | /* Set doorbell size */ |
10263 | bp->db_size = (1 << BNX2X_DB_SHIFT); | |
10264 | ||
619c5cb6 | 10265 | if (!CHIP_IS_E1x(bp)) { |
f2e0899f DK |
10266 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); |
10267 | if ((val & 1) == 0) | |
10268 | val = REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
10269 | else | |
10270 | val = (val >> 1) & 1; | |
10271 | BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : | |
10272 | "2_PORT_MODE"); | |
10273 | bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : | |
10274 | CHIP_2_PORT_MODE; | |
10275 | ||
10276 | if (CHIP_MODE_IS_4_PORT(bp)) | |
10277 | bp->pfid = (bp->pf_num >> 1); /* 0..3 */ | |
10278 | else | |
10279 | bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ | |
10280 | } else { | |
10281 | bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ | |
10282 | bp->pfid = bp->pf_num; /* 0..7 */ | |
10283 | } | |
10284 | ||
51c1a580 MS |
10285 | BNX2X_DEV_INFO("pf_id: %x", bp->pfid); |
10286 | ||
f2e0899f DK |
10287 | bp->link_params.chip_id = bp->common.chip_id; |
10288 | BNX2X_DEV_INFO("chip ID is 0x%x\n", id); | |
523224a3 | 10289 | |
1c06328c EG |
10290 | val = (REG_RD(bp, 0x2874) & 0x55); |
10291 | if ((bp->common.chip_id & 0x1) || | |
10292 | (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { | |
10293 | bp->flags |= ONE_PORT_FLAG; | |
10294 | BNX2X_DEV_INFO("single port device\n"); | |
10295 | } | |
10296 | ||
34f80b04 | 10297 | val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); |
754a2f52 | 10298 | bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << |
34f80b04 EG |
10299 | (val & MCPR_NVM_CFG4_FLASH_SIZE)); |
10300 | BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", | |
10301 | bp->common.flash_size, bp->common.flash_size); | |
10302 | ||
1b6e2ceb DK |
10303 | bnx2x_init_shmem(bp); |
10304 | ||
f2e0899f DK |
10305 | bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? |
10306 | MISC_REG_GENERIC_CR_1 : | |
10307 | MISC_REG_GENERIC_CR_0)); | |
1b6e2ceb | 10308 | |
34f80b04 | 10309 | bp->link_params.shmem_base = bp->common.shmem_base; |
a22f0788 | 10310 | bp->link_params.shmem2_base = bp->common.shmem2_base; |
b884d95b YR |
10311 | if (SHMEM2_RD(bp, size) > |
10312 | (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) | |
10313 | bp->link_params.lfa_base = | |
10314 | REG_RD(bp, bp->common.shmem2_base + | |
10315 | (u32)offsetof(struct shmem2_region, | |
10316 | lfa_host_addr[BP_PORT(bp)])); | |
10317 | else | |
10318 | bp->link_params.lfa_base = 0; | |
2691d51d EG |
10319 | BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", |
10320 | bp->common.shmem_base, bp->common.shmem2_base); | |
34f80b04 | 10321 | |
f2e0899f | 10322 | if (!bp->common.shmem_base) { |
34f80b04 EG |
10323 | BNX2X_DEV_INFO("MCP not active\n"); |
10324 | bp->flags |= NO_MCP_FLAG; | |
10325 | return; | |
10326 | } | |
10327 | ||
34f80b04 | 10328 | bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
35b19ba5 | 10329 | BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); |
34f80b04 EG |
10330 | |
10331 | bp->link_params.hw_led_mode = ((bp->common.hw_config & | |
10332 | SHARED_HW_CFG_LED_MODE_MASK) >> | |
10333 | SHARED_HW_CFG_LED_MODE_SHIFT); | |
10334 | ||
c2c8b03e EG |
10335 | bp->link_params.feature_config_flags = 0; |
10336 | val = SHMEM_RD(bp, dev_info.shared_feature_config.config); | |
10337 | if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) | |
10338 | bp->link_params.feature_config_flags |= | |
10339 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10340 | else | |
10341 | bp->link_params.feature_config_flags &= | |
10342 | ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; | |
10343 | ||
34f80b04 EG |
10344 | val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; |
10345 | bp->common.bc_ver = val; | |
10346 | BNX2X_DEV_INFO("bc_ver %X\n", val); | |
10347 | if (val < BNX2X_BC_VER) { | |
10348 | /* for now only warn | |
10349 | * later we might need to enforce this */ | |
51c1a580 MS |
10350 | BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", |
10351 | BNX2X_BC_VER, val); | |
34f80b04 | 10352 | } |
4d295db0 | 10353 | bp->link_params.feature_config_flags |= |
a22f0788 | 10354 | (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? |
f85582f8 DK |
10355 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; |
10356 | ||
a22f0788 YR |
10357 | bp->link_params.feature_config_flags |= |
10358 | (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? | |
10359 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; | |
a3348722 BW |
10360 | bp->link_params.feature_config_flags |= |
10361 | (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? | |
10362 | FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; | |
85242eea YR |
10363 | bp->link_params.feature_config_flags |= |
10364 | (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? | |
10365 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; | |
55386fe8 YR |
10366 | |
10367 | bp->link_params.feature_config_flags |= | |
10368 | (val >= REQ_BC_VER_4_MT_SUPPORTED) ? | |
10369 | FEATURE_CONFIG_MT_SUPPORT : 0; | |
10370 | ||
0e898dd7 BW |
10371 | bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? |
10372 | BC_SUPPORTS_PFC_STATS : 0; | |
85242eea | 10373 | |
2e499d3c BW |
10374 | bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? |
10375 | BC_SUPPORTS_FCOE_FEATURES : 0; | |
10376 | ||
9876879f BW |
10377 | bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? |
10378 | BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; | |
a6d3a5ba BW |
10379 | |
10380 | bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? | |
10381 | BC_SUPPORTS_RMMOD_CMD : 0; | |
10382 | ||
1d187b34 BW |
10383 | boot_mode = SHMEM_RD(bp, |
10384 | dev_info.port_feature_config[BP_PORT(bp)].mba_config) & | |
10385 | PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; | |
10386 | switch (boot_mode) { | |
10387 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: | |
10388 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; | |
10389 | break; | |
10390 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: | |
10391 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; | |
10392 | break; | |
10393 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: | |
10394 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; | |
10395 | break; | |
10396 | case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: | |
10397 | bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; | |
10398 | break; | |
10399 | } | |
10400 | ||
29ed74c3 | 10401 | pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); |
f9a3ebbe DK |
10402 | bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; |
10403 | ||
72ce58c3 | 10404 | BNX2X_DEV_INFO("%sWoL capable\n", |
f5372251 | 10405 | (bp->flags & NO_WOL_FLAG) ? "not " : ""); |
34f80b04 EG |
10406 | |
10407 | val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); | |
10408 | val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); | |
10409 | val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); | |
10410 | val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); | |
10411 | ||
cdaa7cb8 VZ |
10412 | dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", |
10413 | val, val2, val3, val4); | |
34f80b04 EG |
10414 | } |
10415 | ||
f2e0899f DK |
10416 | #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) |
10417 | #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) | |
10418 | ||
0329aba1 | 10419 | static int bnx2x_get_igu_cam_info(struct bnx2x *bp) |
f2e0899f DK |
10420 | { |
10421 | int pfid = BP_FUNC(bp); | |
f2e0899f DK |
10422 | int igu_sb_id; |
10423 | u32 val; | |
6383c0b3 | 10424 | u8 fid, igu_sb_cnt = 0; |
f2e0899f DK |
10425 | |
10426 | bp->igu_base_sb = 0xff; | |
f2e0899f | 10427 | if (CHIP_INT_MODE_IS_BC(bp)) { |
3395a033 | 10428 | int vn = BP_VN(bp); |
6383c0b3 | 10429 | igu_sb_cnt = bp->igu_sb_cnt; |
f2e0899f DK |
10430 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
10431 | FP_SB_MAX_E1x; | |
10432 | ||
10433 | bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + | |
10434 | (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); | |
10435 | ||
9b341bb1 | 10436 | return 0; |
f2e0899f DK |
10437 | } |
10438 | ||
10439 | /* IGU in normal mode - read CAM */ | |
10440 | for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; | |
10441 | igu_sb_id++) { | |
10442 | val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); | |
10443 | if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) | |
10444 | continue; | |
10445 | fid = IGU_FID(val); | |
10446 | if ((fid & IGU_FID_ENCODE_IS_PF)) { | |
10447 | if ((fid & IGU_FID_PF_NUM_MASK) != pfid) | |
10448 | continue; | |
10449 | if (IGU_VEC(val) == 0) | |
10450 | /* default status block */ | |
10451 | bp->igu_dsb_id = igu_sb_id; | |
10452 | else { | |
10453 | if (bp->igu_base_sb == 0xff) | |
10454 | bp->igu_base_sb = igu_sb_id; | |
6383c0b3 | 10455 | igu_sb_cnt++; |
f2e0899f DK |
10456 | } |
10457 | } | |
10458 | } | |
619c5cb6 | 10459 | |
6383c0b3 | 10460 | #ifdef CONFIG_PCI_MSI |
185d4c8b AE |
10461 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
10462 | * optional that number of CAM entries will not be equal to the value | |
10463 | * advertised in PCI. | |
10464 | * Driver should use the minimal value of both as the actual status | |
10465 | * block count | |
619c5cb6 | 10466 | */ |
185d4c8b | 10467 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
6383c0b3 | 10468 | #endif |
619c5cb6 | 10469 | |
9b341bb1 | 10470 | if (igu_sb_cnt == 0) { |
f2e0899f | 10471 | BNX2X_ERR("CAM configuration error\n"); |
9b341bb1 BW |
10472 | return -EINVAL; |
10473 | } | |
10474 | ||
10475 | return 0; | |
f2e0899f DK |
10476 | } |
10477 | ||
1dd06ae8 | 10478 | static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) |
a2fbb9ea | 10479 | { |
a22f0788 YR |
10480 | int cfg_size = 0, idx, port = BP_PORT(bp); |
10481 | ||
10482 | /* Aggregation of supported attributes of all external phys */ | |
10483 | bp->port.supported[0] = 0; | |
10484 | bp->port.supported[1] = 0; | |
b7737c9b YR |
10485 | switch (bp->link_params.num_phys) { |
10486 | case 1: | |
a22f0788 YR |
10487 | bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; |
10488 | cfg_size = 1; | |
10489 | break; | |
b7737c9b | 10490 | case 2: |
a22f0788 YR |
10491 | bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; |
10492 | cfg_size = 1; | |
10493 | break; | |
10494 | case 3: | |
10495 | if (bp->link_params.multi_phy_config & | |
10496 | PORT_HW_CFG_PHY_SWAPPED_ENABLED) { | |
10497 | bp->port.supported[1] = | |
10498 | bp->link_params.phy[EXT_PHY1].supported; | |
10499 | bp->port.supported[0] = | |
10500 | bp->link_params.phy[EXT_PHY2].supported; | |
10501 | } else { | |
10502 | bp->port.supported[0] = | |
10503 | bp->link_params.phy[EXT_PHY1].supported; | |
10504 | bp->port.supported[1] = | |
10505 | bp->link_params.phy[EXT_PHY2].supported; | |
10506 | } | |
10507 | cfg_size = 2; | |
10508 | break; | |
b7737c9b | 10509 | } |
a2fbb9ea | 10510 | |
a22f0788 | 10511 | if (!(bp->port.supported[0] || bp->port.supported[1])) { |
51c1a580 | 10512 | BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", |
b7737c9b | 10513 | SHMEM_RD(bp, |
a22f0788 YR |
10514 | dev_info.port_hw_config[port].external_phy_config), |
10515 | SHMEM_RD(bp, | |
10516 | dev_info.port_hw_config[port].external_phy_config2)); | |
a2fbb9ea | 10517 | return; |
f85582f8 | 10518 | } |
a2fbb9ea | 10519 | |
619c5cb6 VZ |
10520 | if (CHIP_IS_E3(bp)) |
10521 | bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); | |
10522 | else { | |
10523 | switch (switch_cfg) { | |
10524 | case SWITCH_CFG_1G: | |
10525 | bp->port.phy_addr = REG_RD( | |
10526 | bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); | |
10527 | break; | |
10528 | case SWITCH_CFG_10G: | |
10529 | bp->port.phy_addr = REG_RD( | |
10530 | bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); | |
10531 | break; | |
10532 | default: | |
10533 | BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", | |
10534 | bp->port.link_config[0]); | |
10535 | return; | |
10536 | } | |
a2fbb9ea | 10537 | } |
619c5cb6 | 10538 | BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); |
a22f0788 YR |
10539 | /* mask what we support according to speed_cap_mask per configuration */ |
10540 | for (idx = 0; idx < cfg_size; idx++) { | |
10541 | if (!(bp->link_params.speed_cap_mask[idx] & | |
c18487ee | 10542 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) |
a22f0788 | 10543 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; |
a2fbb9ea | 10544 | |
a22f0788 | 10545 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10546 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) |
a22f0788 | 10547 | bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; |
a2fbb9ea | 10548 | |
a22f0788 | 10549 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10550 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) |
a22f0788 | 10551 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; |
a2fbb9ea | 10552 | |
a22f0788 | 10553 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10554 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) |
a22f0788 | 10555 | bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; |
a2fbb9ea | 10556 | |
a22f0788 | 10557 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10558 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) |
a22f0788 | 10559 | bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | |
f85582f8 | 10560 | SUPPORTED_1000baseT_Full); |
a2fbb9ea | 10561 | |
a22f0788 | 10562 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10563 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
a22f0788 | 10564 | bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; |
a2fbb9ea | 10565 | |
a22f0788 | 10566 | if (!(bp->link_params.speed_cap_mask[idx] & |
c18487ee | 10567 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
a22f0788 | 10568 | bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; |
b8e0d884 YR |
10569 | |
10570 | if (!(bp->link_params.speed_cap_mask[idx] & | |
10571 | PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) | |
10572 | bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; | |
a22f0788 | 10573 | } |
a2fbb9ea | 10574 | |
a22f0788 YR |
10575 | BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], |
10576 | bp->port.supported[1]); | |
a2fbb9ea ET |
10577 | } |
10578 | ||
0329aba1 | 10579 | static void bnx2x_link_settings_requested(struct bnx2x *bp) |
a2fbb9ea | 10580 | { |
a22f0788 YR |
10581 | u32 link_config, idx, cfg_size = 0; |
10582 | bp->port.advertising[0] = 0; | |
10583 | bp->port.advertising[1] = 0; | |
10584 | switch (bp->link_params.num_phys) { | |
10585 | case 1: | |
10586 | case 2: | |
10587 | cfg_size = 1; | |
10588 | break; | |
10589 | case 3: | |
10590 | cfg_size = 2; | |
10591 | break; | |
10592 | } | |
10593 | for (idx = 0; idx < cfg_size; idx++) { | |
10594 | bp->link_params.req_duplex[idx] = DUPLEX_FULL; | |
10595 | link_config = bp->port.link_config[idx]; | |
10596 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
f85582f8 | 10597 | case PORT_FEATURE_LINK_SPEED_AUTO: |
a22f0788 YR |
10598 | if (bp->port.supported[idx] & SUPPORTED_Autoneg) { |
10599 | bp->link_params.req_line_speed[idx] = | |
10600 | SPEED_AUTO_NEG; | |
10601 | bp->port.advertising[idx] |= | |
10602 | bp->port.supported[idx]; | |
10bd1f24 MY |
10603 | if (bp->link_params.phy[EXT_PHY1].type == |
10604 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) | |
10605 | bp->port.advertising[idx] |= | |
10606 | (SUPPORTED_100baseT_Half | | |
10607 | SUPPORTED_100baseT_Full); | |
f85582f8 DK |
10608 | } else { |
10609 | /* force 10G, no AN */ | |
a22f0788 YR |
10610 | bp->link_params.req_line_speed[idx] = |
10611 | SPEED_10000; | |
10612 | bp->port.advertising[idx] |= | |
10613 | (ADVERTISED_10000baseT_Full | | |
f85582f8 | 10614 | ADVERTISED_FIBRE); |
a22f0788 | 10615 | continue; |
f85582f8 DK |
10616 | } |
10617 | break; | |
a2fbb9ea | 10618 | |
f85582f8 | 10619 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
a22f0788 YR |
10620 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { |
10621 | bp->link_params.req_line_speed[idx] = | |
10622 | SPEED_10; | |
10623 | bp->port.advertising[idx] |= | |
10624 | (ADVERTISED_10baseT_Full | | |
f85582f8 DK |
10625 | ADVERTISED_TP); |
10626 | } else { | |
51c1a580 | 10627 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 | 10628 | link_config, |
a22f0788 | 10629 | bp->link_params.speed_cap_mask[idx]); |
f85582f8 DK |
10630 | return; |
10631 | } | |
10632 | break; | |
a2fbb9ea | 10633 | |
f85582f8 | 10634 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
a22f0788 YR |
10635 | if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { |
10636 | bp->link_params.req_line_speed[idx] = | |
10637 | SPEED_10; | |
10638 | bp->link_params.req_duplex[idx] = | |
10639 | DUPLEX_HALF; | |
10640 | bp->port.advertising[idx] |= | |
10641 | (ADVERTISED_10baseT_Half | | |
f85582f8 DK |
10642 | ADVERTISED_TP); |
10643 | } else { | |
51c1a580 | 10644 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10645 | link_config, |
10646 | bp->link_params.speed_cap_mask[idx]); | |
10647 | return; | |
10648 | } | |
10649 | break; | |
a2fbb9ea | 10650 | |
f85582f8 DK |
10651 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
10652 | if (bp->port.supported[idx] & | |
10653 | SUPPORTED_100baseT_Full) { | |
a22f0788 YR |
10654 | bp->link_params.req_line_speed[idx] = |
10655 | SPEED_100; | |
10656 | bp->port.advertising[idx] |= | |
10657 | (ADVERTISED_100baseT_Full | | |
f85582f8 DK |
10658 | ADVERTISED_TP); |
10659 | } else { | |
51c1a580 | 10660 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
f85582f8 DK |
10661 | link_config, |
10662 | bp->link_params.speed_cap_mask[idx]); | |
10663 | return; | |
10664 | } | |
10665 | break; | |
a2fbb9ea | 10666 | |
f85582f8 DK |
10667 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
10668 | if (bp->port.supported[idx] & | |
10669 | SUPPORTED_100baseT_Half) { | |
10670 | bp->link_params.req_line_speed[idx] = | |
10671 | SPEED_100; | |
10672 | bp->link_params.req_duplex[idx] = | |
10673 | DUPLEX_HALF; | |
a22f0788 YR |
10674 | bp->port.advertising[idx] |= |
10675 | (ADVERTISED_100baseT_Half | | |
f85582f8 DK |
10676 | ADVERTISED_TP); |
10677 | } else { | |
51c1a580 | 10678 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10679 | link_config, |
10680 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10681 | return; |
10682 | } | |
10683 | break; | |
a2fbb9ea | 10684 | |
f85582f8 | 10685 | case PORT_FEATURE_LINK_SPEED_1G: |
a22f0788 YR |
10686 | if (bp->port.supported[idx] & |
10687 | SUPPORTED_1000baseT_Full) { | |
10688 | bp->link_params.req_line_speed[idx] = | |
10689 | SPEED_1000; | |
10690 | bp->port.advertising[idx] |= | |
10691 | (ADVERTISED_1000baseT_Full | | |
f85582f8 DK |
10692 | ADVERTISED_TP); |
10693 | } else { | |
51c1a580 | 10694 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 YR |
10695 | link_config, |
10696 | bp->link_params.speed_cap_mask[idx]); | |
f85582f8 DK |
10697 | return; |
10698 | } | |
10699 | break; | |
a2fbb9ea | 10700 | |
f85582f8 | 10701 | case PORT_FEATURE_LINK_SPEED_2_5G: |
a22f0788 YR |
10702 | if (bp->port.supported[idx] & |
10703 | SUPPORTED_2500baseX_Full) { | |
10704 | bp->link_params.req_line_speed[idx] = | |
10705 | SPEED_2500; | |
10706 | bp->port.advertising[idx] |= | |
10707 | (ADVERTISED_2500baseX_Full | | |
34f80b04 | 10708 | ADVERTISED_TP); |
f85582f8 | 10709 | } else { |
51c1a580 | 10710 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10711 | link_config, |
f85582f8 DK |
10712 | bp->link_params.speed_cap_mask[idx]); |
10713 | return; | |
10714 | } | |
10715 | break; | |
a2fbb9ea | 10716 | |
f85582f8 | 10717 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
a22f0788 YR |
10718 | if (bp->port.supported[idx] & |
10719 | SUPPORTED_10000baseT_Full) { | |
10720 | bp->link_params.req_line_speed[idx] = | |
10721 | SPEED_10000; | |
10722 | bp->port.advertising[idx] |= | |
10723 | (ADVERTISED_10000baseT_Full | | |
34f80b04 | 10724 | ADVERTISED_FIBRE); |
f85582f8 | 10725 | } else { |
51c1a580 | 10726 | BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", |
a22f0788 | 10727 | link_config, |
f85582f8 DK |
10728 | bp->link_params.speed_cap_mask[idx]); |
10729 | return; | |
10730 | } | |
10731 | break; | |
3c9ada22 YR |
10732 | case PORT_FEATURE_LINK_SPEED_20G: |
10733 | bp->link_params.req_line_speed[idx] = SPEED_20000; | |
a2fbb9ea | 10734 | |
3c9ada22 | 10735 | break; |
f85582f8 | 10736 | default: |
51c1a580 | 10737 | BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", |
754a2f52 | 10738 | link_config); |
f85582f8 DK |
10739 | bp->link_params.req_line_speed[idx] = |
10740 | SPEED_AUTO_NEG; | |
10741 | bp->port.advertising[idx] = | |
10742 | bp->port.supported[idx]; | |
10743 | break; | |
10744 | } | |
a2fbb9ea | 10745 | |
a22f0788 | 10746 | bp->link_params.req_flow_ctrl[idx] = (link_config & |
34f80b04 | 10747 | PORT_FEATURE_FLOW_CONTROL_MASK); |
cd1dfce2 YM |
10748 | if (bp->link_params.req_flow_ctrl[idx] == |
10749 | BNX2X_FLOW_CTRL_AUTO) { | |
10750 | if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) | |
10751 | bp->link_params.req_flow_ctrl[idx] = | |
10752 | BNX2X_FLOW_CTRL_NONE; | |
10753 | else | |
10754 | bnx2x_set_requested_fc(bp); | |
a22f0788 | 10755 | } |
a2fbb9ea | 10756 | |
51c1a580 | 10757 | BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", |
a22f0788 YR |
10758 | bp->link_params.req_line_speed[idx], |
10759 | bp->link_params.req_duplex[idx], | |
10760 | bp->link_params.req_flow_ctrl[idx], | |
10761 | bp->port.advertising[idx]); | |
10762 | } | |
a2fbb9ea ET |
10763 | } |
10764 | ||
0329aba1 | 10765 | static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) |
e665bfda | 10766 | { |
86564c3f YM |
10767 | __be16 mac_hi_be = cpu_to_be16(mac_hi); |
10768 | __be32 mac_lo_be = cpu_to_be32(mac_lo); | |
10769 | memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); | |
10770 | memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); | |
e665bfda MC |
10771 | } |
10772 | ||
0329aba1 | 10773 | static void bnx2x_get_port_hwinfo(struct bnx2x *bp) |
a2fbb9ea | 10774 | { |
34f80b04 | 10775 | int port = BP_PORT(bp); |
589abe3a | 10776 | u32 config; |
c8c60d88 | 10777 | u32 ext_phy_type, ext_phy_config, eee_mode; |
a2fbb9ea | 10778 | |
c18487ee | 10779 | bp->link_params.bp = bp; |
34f80b04 | 10780 | bp->link_params.port = port; |
c18487ee | 10781 | |
c18487ee | 10782 | bp->link_params.lane_config = |
a2fbb9ea | 10783 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
4d295db0 | 10784 | |
a22f0788 | 10785 | bp->link_params.speed_cap_mask[0] = |
a2fbb9ea | 10786 | SHMEM_RD(bp, |
b0261926 YR |
10787 | dev_info.port_hw_config[port].speed_capability_mask) & |
10788 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 YR |
10789 | bp->link_params.speed_cap_mask[1] = |
10790 | SHMEM_RD(bp, | |
b0261926 YR |
10791 | dev_info.port_hw_config[port].speed_capability_mask2) & |
10792 | PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; | |
a22f0788 | 10793 | bp->port.link_config[0] = |
a2fbb9ea ET |
10794 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
10795 | ||
a22f0788 YR |
10796 | bp->port.link_config[1] = |
10797 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); | |
c2c8b03e | 10798 | |
a22f0788 YR |
10799 | bp->link_params.multi_phy_config = |
10800 | SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); | |
3ce2c3f9 EG |
10801 | /* If the device is capable of WoL, set the default state according |
10802 | * to the HW | |
10803 | */ | |
4d295db0 | 10804 | config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); |
3ce2c3f9 EG |
10805 | bp->wol = (!(bp->flags & NO_WOL_FLAG) && |
10806 | (config & PORT_FEATURE_WOL_ENABLED)); | |
10807 | ||
4ba7699b YM |
10808 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == |
10809 | PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) | |
10810 | bp->flags |= NO_ISCSI_FLAG; | |
10811 | if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == | |
10812 | PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) | |
10813 | bp->flags |= NO_FCOE_FLAG; | |
10814 | ||
51c1a580 | 10815 | BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", |
c18487ee | 10816 | bp->link_params.lane_config, |
a22f0788 YR |
10817 | bp->link_params.speed_cap_mask[0], |
10818 | bp->port.link_config[0]); | |
a2fbb9ea | 10819 | |
a22f0788 | 10820 | bp->link_params.switch_cfg = (bp->port.link_config[0] & |
f85582f8 | 10821 | PORT_FEATURE_CONNECTED_SWITCH_MASK); |
b7737c9b | 10822 | bnx2x_phy_probe(&bp->link_params); |
c18487ee | 10823 | bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); |
a2fbb9ea ET |
10824 | |
10825 | bnx2x_link_settings_requested(bp); | |
10826 | ||
01cd4528 EG |
10827 | /* |
10828 | * If connected directly, work with the internal PHY, otherwise, work | |
10829 | * with the external PHY | |
10830 | */ | |
b7737c9b YR |
10831 | ext_phy_config = |
10832 | SHMEM_RD(bp, | |
10833 | dev_info.port_hw_config[port].external_phy_config); | |
10834 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
01cd4528 | 10835 | if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) |
b7737c9b | 10836 | bp->mdio.prtad = bp->port.phy_addr; |
01cd4528 EG |
10837 | |
10838 | else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | |
10839 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
10840 | bp->mdio.prtad = | |
b7737c9b | 10841 | XGXS_EXT_PHY_ADDR(ext_phy_config); |
5866df6d | 10842 | |
c8c60d88 YM |
10843 | /* Configure link feature according to nvram value */ |
10844 | eee_mode = (((SHMEM_RD(bp, dev_info. | |
10845 | port_feature_config[port].eee_power_mode)) & | |
10846 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
10847 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
10848 | if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { | |
10849 | bp->link_params.eee_mode = EEE_MODE_ADV_LPI | | |
10850 | EEE_MODE_ENABLE_LPI | | |
10851 | EEE_MODE_OUTPUT_TIME; | |
10852 | } else { | |
10853 | bp->link_params.eee_mode = 0; | |
10854 | } | |
0793f83f | 10855 | } |
01cd4528 | 10856 | |
b306f5ed | 10857 | void bnx2x_get_iscsi_info(struct bnx2x *bp) |
2ba45142 | 10858 | { |
9e62e912 | 10859 | u32 no_flags = NO_ISCSI_FLAG; |
bf61ee14 | 10860 | int port = BP_PORT(bp); |
2ba45142 | 10861 | u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
bf61ee14 | 10862 | drv_lic_key[port].max_iscsi_conn); |
2ba45142 | 10863 | |
55c11941 MS |
10864 | if (!CNIC_SUPPORT(bp)) { |
10865 | bp->flags |= no_flags; | |
10866 | return; | |
10867 | } | |
10868 | ||
b306f5ed | 10869 | /* Get the number of maximum allowed iSCSI connections */ |
2ba45142 VZ |
10870 | bp->cnic_eth_dev.max_iscsi_conn = |
10871 | (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> | |
10872 | BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; | |
10873 | ||
b306f5ed DK |
10874 | BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", |
10875 | bp->cnic_eth_dev.max_iscsi_conn); | |
10876 | ||
10877 | /* | |
10878 | * If maximum allowed number of connections is zero - | |
10879 | * disable the feature. | |
10880 | */ | |
10881 | if (!bp->cnic_eth_dev.max_iscsi_conn) | |
9e62e912 | 10882 | bp->flags |= no_flags; |
b306f5ed DK |
10883 | } |
10884 | ||
0329aba1 | 10885 | static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) |
9e62e912 DK |
10886 | { |
10887 | /* Port info */ | |
10888 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10889 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); | |
10890 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10891 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); | |
10892 | ||
10893 | /* Node info */ | |
10894 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10895 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); | |
10896 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10897 | MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); | |
10898 | } | |
86800194 DK |
10899 | |
10900 | static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) | |
10901 | { | |
10902 | u8 count = 0; | |
10903 | ||
10904 | if (IS_MF(bp)) { | |
10905 | u8 fid; | |
10906 | ||
10907 | /* iterate over absolute function ids for this path: */ | |
10908 | for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { | |
10909 | if (IS_MF_SD(bp)) { | |
10910 | u32 cfg = MF_CFG_RD(bp, | |
10911 | func_mf_config[fid].config); | |
10912 | ||
10913 | if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && | |
10914 | ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == | |
10915 | FUNC_MF_CFG_PROTOCOL_FCOE)) | |
10916 | count++; | |
10917 | } else { | |
10918 | u32 cfg = MF_CFG_RD(bp, | |
10919 | func_ext_config[fid]. | |
10920 | func_cfg); | |
10921 | ||
10922 | if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && | |
10923 | (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) | |
10924 | count++; | |
10925 | } | |
10926 | } | |
10927 | } else { /* SF */ | |
10928 | int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; | |
10929 | ||
10930 | for (port = 0; port < port_cnt; port++) { | |
10931 | u32 lic = SHMEM_RD(bp, | |
10932 | drv_lic_key[port].max_fcoe_conn) ^ | |
10933 | FW_ENCODE_32BIT_PATTERN; | |
10934 | if (lic) | |
10935 | count++; | |
10936 | } | |
10937 | } | |
10938 | ||
10939 | return count; | |
10940 | } | |
10941 | ||
0329aba1 | 10942 | static void bnx2x_get_fcoe_info(struct bnx2x *bp) |
b306f5ed DK |
10943 | { |
10944 | int port = BP_PORT(bp); | |
10945 | int func = BP_ABS_FUNC(bp); | |
b306f5ed DK |
10946 | u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, |
10947 | drv_lic_key[port].max_fcoe_conn); | |
86800194 | 10948 | u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); |
b306f5ed | 10949 | |
55c11941 MS |
10950 | if (!CNIC_SUPPORT(bp)) { |
10951 | bp->flags |= NO_FCOE_FLAG; | |
10952 | return; | |
10953 | } | |
10954 | ||
b306f5ed | 10955 | /* Get the number of maximum allowed FCoE connections */ |
2ba45142 VZ |
10956 | bp->cnic_eth_dev.max_fcoe_conn = |
10957 | (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> | |
10958 | BNX2X_MAX_FCOE_INIT_CONN_SHIFT; | |
10959 | ||
0eb43b4b BPG |
10960 | /* Calculate the number of maximum allowed FCoE tasks */ |
10961 | bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; | |
86800194 DK |
10962 | |
10963 | /* check if FCoE resources must be shared between different functions */ | |
10964 | if (num_fcoe_func) | |
10965 | bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; | |
0eb43b4b | 10966 | |
bf61ee14 VZ |
10967 | /* Read the WWN: */ |
10968 | if (!IS_MF(bp)) { | |
10969 | /* Port info */ | |
10970 | bp->cnic_eth_dev.fcoe_wwn_port_name_hi = | |
10971 | SHMEM_RD(bp, | |
2de67439 | 10972 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
10973 | fcoe_wwn_port_name_upper); |
10974 | bp->cnic_eth_dev.fcoe_wwn_port_name_lo = | |
10975 | SHMEM_RD(bp, | |
2de67439 | 10976 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
10977 | fcoe_wwn_port_name_lower); |
10978 | ||
10979 | /* Node info */ | |
10980 | bp->cnic_eth_dev.fcoe_wwn_node_name_hi = | |
10981 | SHMEM_RD(bp, | |
2de67439 | 10982 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
10983 | fcoe_wwn_node_name_upper); |
10984 | bp->cnic_eth_dev.fcoe_wwn_node_name_lo = | |
10985 | SHMEM_RD(bp, | |
2de67439 | 10986 | dev_info.port_hw_config[port]. |
bf61ee14 VZ |
10987 | fcoe_wwn_node_name_lower); |
10988 | } else if (!IS_MF_SD(bp)) { | |
bf61ee14 VZ |
10989 | /* |
10990 | * Read the WWN info only if the FCoE feature is enabled for | |
10991 | * this function. | |
10992 | */ | |
7b5342d9 | 10993 | if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) |
9e62e912 DK |
10994 | bnx2x_get_ext_wwn_info(bp, func); |
10995 | ||
382e513a | 10996 | } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) { |
9e62e912 | 10997 | bnx2x_get_ext_wwn_info(bp, func); |
382e513a | 10998 | } |
bf61ee14 | 10999 | |
b306f5ed | 11000 | BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); |
2ba45142 | 11001 | |
bf61ee14 VZ |
11002 | /* |
11003 | * If maximum allowed number of connections is zero - | |
2ba45142 VZ |
11004 | * disable the feature. |
11005 | */ | |
2ba45142 VZ |
11006 | if (!bp->cnic_eth_dev.max_fcoe_conn) |
11007 | bp->flags |= NO_FCOE_FLAG; | |
11008 | } | |
b306f5ed | 11009 | |
0329aba1 | 11010 | static void bnx2x_get_cnic_info(struct bnx2x *bp) |
b306f5ed DK |
11011 | { |
11012 | /* | |
11013 | * iSCSI may be dynamically disabled but reading | |
11014 | * info here we will decrease memory usage by driver | |
11015 | * if the feature is disabled for good | |
11016 | */ | |
11017 | bnx2x_get_iscsi_info(bp); | |
11018 | bnx2x_get_fcoe_info(bp); | |
11019 | } | |
2ba45142 | 11020 | |
0329aba1 | 11021 | static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) |
0793f83f DK |
11022 | { |
11023 | u32 val, val2; | |
11024 | int func = BP_ABS_FUNC(bp); | |
11025 | int port = BP_PORT(bp); | |
2ba45142 VZ |
11026 | u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; |
11027 | u8 *fip_mac = bp->fip_mac; | |
0793f83f | 11028 | |
55c11941 MS |
11029 | if (IS_MF(bp)) { |
11030 | /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or | |
2ba45142 | 11031 | * FCoE MAC then the appropriate feature should be disabled. |
55c11941 MS |
11032 | * In non SD mode features configuration comes from struct |
11033 | * func_ext_config. | |
2ba45142 | 11034 | */ |
55c11941 | 11035 | if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) { |
0793f83f DK |
11036 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); |
11037 | if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { | |
11038 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11039 | iscsi_mac_addr_upper); |
0793f83f | 11040 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11041 | iscsi_mac_addr_lower); |
2ba45142 | 11042 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
55c11941 MS |
11043 | BNX2X_DEV_INFO |
11044 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11045 | } else { | |
2ba45142 | 11046 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
55c11941 | 11047 | } |
2ba45142 VZ |
11048 | |
11049 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { | |
11050 | val2 = MF_CFG_RD(bp, func_ext_config[func]. | |
55c11941 | 11051 | fcoe_mac_addr_upper); |
2ba45142 | 11052 | val = MF_CFG_RD(bp, func_ext_config[func]. |
55c11941 | 11053 | fcoe_mac_addr_lower); |
2ba45142 | 11054 | bnx2x_set_mac_buf(fip_mac, val, val2); |
55c11941 MS |
11055 | BNX2X_DEV_INFO |
11056 | ("Read FCoE L2 MAC: %pM\n", fip_mac); | |
11057 | } else { | |
2ba45142 | 11058 | bp->flags |= NO_FCOE_FLAG; |
55c11941 | 11059 | } |
a3348722 BW |
11060 | |
11061 | bp->mf_ext_config = cfg; | |
11062 | ||
9e62e912 | 11063 | } else { /* SD MODE */ |
55c11941 MS |
11064 | if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { |
11065 | /* use primary mac as iscsi mac */ | |
11066 | memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); | |
11067 | ||
11068 | BNX2X_DEV_INFO("SD ISCSI MODE\n"); | |
11069 | BNX2X_DEV_INFO | |
11070 | ("Read iSCSI MAC: %pM\n", iscsi_mac); | |
11071 | } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { | |
11072 | /* use primary mac as fip mac */ | |
11073 | memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); | |
11074 | BNX2X_DEV_INFO("SD FCoE MODE\n"); | |
11075 | BNX2X_DEV_INFO | |
11076 | ("Read FIP MAC: %pM\n", fip_mac); | |
614c76df | 11077 | } |
0793f83f | 11078 | } |
a3348722 | 11079 | |
82594f8f YM |
11080 | /* If this is a storage-only interface, use SAN mac as |
11081 | * primary MAC. Notice that for SD this is already the case, | |
11082 | * as the SAN mac was copied from the primary MAC. | |
11083 | */ | |
11084 | if (IS_MF_FCOE_AFEX(bp)) | |
a3348722 | 11085 | memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); |
0793f83f | 11086 | } else { |
0793f83f | 11087 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11088 | iscsi_mac_upper); |
0793f83f | 11089 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11090 | iscsi_mac_lower); |
2ba45142 | 11091 | bnx2x_set_mac_buf(iscsi_mac, val, val2); |
c03bd39c VZ |
11092 | |
11093 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. | |
55c11941 | 11094 | fcoe_fip_mac_upper); |
c03bd39c | 11095 | val = SHMEM_RD(bp, dev_info.port_hw_config[port]. |
55c11941 | 11096 | fcoe_fip_mac_lower); |
c03bd39c | 11097 | bnx2x_set_mac_buf(fip_mac, val, val2); |
0793f83f DK |
11098 | } |
11099 | ||
55c11941 | 11100 | /* Disable iSCSI OOO if MAC configuration is invalid. */ |
426b9241 | 11101 | if (!is_valid_ether_addr(iscsi_mac)) { |
55c11941 | 11102 | bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; |
426b9241 DK |
11103 | memset(iscsi_mac, 0, ETH_ALEN); |
11104 | } | |
11105 | ||
55c11941 | 11106 | /* Disable FCoE if MAC configuration is invalid. */ |
426b9241 DK |
11107 | if (!is_valid_ether_addr(fip_mac)) { |
11108 | bp->flags |= NO_FCOE_FLAG; | |
11109 | memset(bp->fip_mac, 0, ETH_ALEN); | |
11110 | } | |
55c11941 MS |
11111 | } |
11112 | ||
0329aba1 | 11113 | static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) |
55c11941 MS |
11114 | { |
11115 | u32 val, val2; | |
11116 | int func = BP_ABS_FUNC(bp); | |
11117 | int port = BP_PORT(bp); | |
11118 | ||
11119 | /* Zero primary MAC configuration */ | |
11120 | memset(bp->dev->dev_addr, 0, ETH_ALEN); | |
11121 | ||
11122 | if (BP_NOMCP(bp)) { | |
11123 | BNX2X_ERROR("warning: random MAC workaround active\n"); | |
11124 | eth_hw_addr_random(bp->dev); | |
11125 | } else if (IS_MF(bp)) { | |
11126 | val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); | |
11127 | val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); | |
11128 | if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && | |
11129 | (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) | |
11130 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11131 | ||
11132 | if (CNIC_SUPPORT(bp)) | |
11133 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11134 | } else { | |
11135 | /* in SF read MACs from port configuration */ | |
11136 | val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); | |
11137 | val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); | |
11138 | bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); | |
11139 | ||
11140 | if (CNIC_SUPPORT(bp)) | |
11141 | bnx2x_get_cnic_mac_hwinfo(bp); | |
11142 | } | |
11143 | ||
11144 | memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); | |
619c5cb6 | 11145 | |
614c76df | 11146 | if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) |
619c5cb6 | 11147 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11148 | "bad Ethernet MAC address configuration: %pM\n" |
11149 | "change it manually before bringing up the appropriate network interface\n", | |
0f9dad10 | 11150 | bp->dev->dev_addr); |
7964211d | 11151 | } |
51c1a580 | 11152 | |
0329aba1 | 11153 | static bool bnx2x_get_dropless_info(struct bnx2x *bp) |
7964211d YM |
11154 | { |
11155 | int tmp; | |
11156 | u32 cfg; | |
51c1a580 | 11157 | |
aeeddb8b YM |
11158 | if (IS_VF(bp)) |
11159 | return 0; | |
11160 | ||
7964211d YM |
11161 | if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { |
11162 | /* Take function: tmp = func */ | |
11163 | tmp = BP_ABS_FUNC(bp); | |
11164 | cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); | |
11165 | cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); | |
11166 | } else { | |
11167 | /* Take port: tmp = port */ | |
11168 | tmp = BP_PORT(bp); | |
11169 | cfg = SHMEM_RD(bp, | |
11170 | dev_info.port_hw_config[tmp].generic_features); | |
11171 | cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); | |
11172 | } | |
11173 | return cfg; | |
34f80b04 EG |
11174 | } |
11175 | ||
0329aba1 | 11176 | static int bnx2x_get_hwinfo(struct bnx2x *bp) |
34f80b04 | 11177 | { |
0793f83f | 11178 | int /*abs*/func = BP_ABS_FUNC(bp); |
b8ee8328 | 11179 | int vn; |
0793f83f | 11180 | u32 val = 0; |
34f80b04 | 11181 | int rc = 0; |
a2fbb9ea | 11182 | |
34f80b04 | 11183 | bnx2x_get_common_hwinfo(bp); |
a2fbb9ea | 11184 | |
6383c0b3 AE |
11185 | /* |
11186 | * initialize IGU parameters | |
11187 | */ | |
f2e0899f DK |
11188 | if (CHIP_IS_E1x(bp)) { |
11189 | bp->common.int_block = INT_BLOCK_HC; | |
11190 | ||
11191 | bp->igu_dsb_id = DEF_SB_IGU_ID; | |
11192 | bp->igu_base_sb = 0; | |
f2e0899f DK |
11193 | } else { |
11194 | bp->common.int_block = INT_BLOCK_IGU; | |
7a06a122 | 11195 | |
16a5fd92 | 11196 | /* do not allow device reset during IGU info processing */ |
7a06a122 DK |
11197 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
11198 | ||
f2e0899f | 11199 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
619c5cb6 VZ |
11200 | |
11201 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | |
11202 | int tout = 5000; | |
11203 | ||
11204 | BNX2X_DEV_INFO("FORCING Normal Mode\n"); | |
11205 | ||
11206 | val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); | |
11207 | REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); | |
11208 | REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); | |
11209 | ||
11210 | while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11211 | tout--; | |
0926d499 | 11212 | usleep_range(1000, 2000); |
619c5cb6 VZ |
11213 | } |
11214 | ||
11215 | if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { | |
11216 | dev_err(&bp->pdev->dev, | |
11217 | "FORCING Normal Mode failed!!!\n"); | |
9b341bb1 BW |
11218 | bnx2x_release_hw_lock(bp, |
11219 | HW_LOCK_RESOURCE_RESET); | |
619c5cb6 VZ |
11220 | return -EPERM; |
11221 | } | |
11222 | } | |
11223 | ||
f2e0899f | 11224 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
619c5cb6 | 11225 | BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); |
f2e0899f DK |
11226 | bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; |
11227 | } else | |
619c5cb6 | 11228 | BNX2X_DEV_INFO("IGU Normal Mode\n"); |
523224a3 | 11229 | |
9b341bb1 | 11230 | rc = bnx2x_get_igu_cam_info(bp); |
7a06a122 | 11231 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
9b341bb1 BW |
11232 | if (rc) |
11233 | return rc; | |
f2e0899f | 11234 | } |
619c5cb6 VZ |
11235 | |
11236 | /* | |
11237 | * set base FW non-default (fast path) status block id, this value is | |
11238 | * used to initialize the fw_sb_id saved on the fp/queue structure to | |
11239 | * determine the id used by the FW. | |
11240 | */ | |
11241 | if (CHIP_IS_E1x(bp)) | |
11242 | bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); | |
11243 | else /* | |
11244 | * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of | |
11245 | * the same queue are indicated on the same IGU SB). So we prefer | |
11246 | * FW and IGU SBs to be the same value. | |
11247 | */ | |
11248 | bp->base_fw_ndsb = bp->igu_base_sb; | |
11249 | ||
11250 | BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" | |
11251 | "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, | |
11252 | bp->igu_sb_cnt, bp->base_fw_ndsb); | |
f2e0899f DK |
11253 | |
11254 | /* | |
11255 | * Initialize MF configuration | |
11256 | */ | |
523224a3 | 11257 | |
fb3bff17 DK |
11258 | bp->mf_ov = 0; |
11259 | bp->mf_mode = 0; | |
3395a033 | 11260 | vn = BP_VN(bp); |
0793f83f | 11261 | |
f2e0899f | 11262 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
619c5cb6 VZ |
11263 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
11264 | bp->common.shmem2_base, SHMEM2_RD(bp, size), | |
11265 | (u32)offsetof(struct shmem2_region, mf_cfg_addr)); | |
11266 | ||
f2e0899f DK |
11267 | if (SHMEM2_HAS(bp, mf_cfg_addr)) |
11268 | bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); | |
11269 | else | |
11270 | bp->common.mf_cfg_base = bp->common.shmem_base + | |
523224a3 DK |
11271 | offsetof(struct shmem_region, func_mb) + |
11272 | E1H_FUNC_MAX * sizeof(struct drv_func_mb); | |
0793f83f DK |
11273 | /* |
11274 | * get mf configuration: | |
16a5fd92 | 11275 | * 1. Existence of MF configuration |
0793f83f DK |
11276 | * 2. MAC address must be legal (check only upper bytes) |
11277 | * for Switch-Independent mode; | |
11278 | * OVLAN must be legal for Switch-Dependent mode | |
11279 | * 3. SF_MODE configures specific MF mode | |
11280 | */ | |
11281 | if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
11282 | /* get mf configuration */ | |
11283 | val = SHMEM_RD(bp, | |
11284 | dev_info.shared_feature_config.config); | |
11285 | val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; | |
11286 | ||
11287 | switch (val) { | |
11288 | case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: | |
11289 | val = MF_CFG_RD(bp, func_mf_config[func]. | |
11290 | mac_upper); | |
11291 | /* check for legal mac (upper bytes)*/ | |
11292 | if (val != 0xffff) { | |
11293 | bp->mf_mode = MULTI_FUNCTION_SI; | |
11294 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11295 | func_mf_config[func].config); | |
11296 | } else | |
51c1a580 | 11297 | BNX2X_DEV_INFO("illegal MAC address for SI\n"); |
0793f83f | 11298 | break; |
a3348722 BW |
11299 | case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: |
11300 | if ((!CHIP_IS_E1x(bp)) && | |
11301 | (MF_CFG_RD(bp, func_mf_config[func]. | |
11302 | mac_upper) != 0xffff) && | |
11303 | (SHMEM2_HAS(bp, | |
11304 | afex_driver_support))) { | |
11305 | bp->mf_mode = MULTI_FUNCTION_AFEX; | |
11306 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11307 | func_mf_config[func].config); | |
11308 | } else { | |
11309 | BNX2X_DEV_INFO("can not configure afex mode\n"); | |
11310 | } | |
11311 | break; | |
0793f83f DK |
11312 | case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: |
11313 | /* get OV configuration */ | |
11314 | val = MF_CFG_RD(bp, | |
11315 | func_mf_config[FUNC_0].e1hov_tag); | |
11316 | val &= FUNC_MF_CFG_E1HOV_TAG_MASK; | |
11317 | ||
11318 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { | |
11319 | bp->mf_mode = MULTI_FUNCTION_SD; | |
11320 | bp->mf_config[vn] = MF_CFG_RD(bp, | |
11321 | func_mf_config[func].config); | |
11322 | } else | |
754a2f52 | 11323 | BNX2X_DEV_INFO("illegal OV for SD\n"); |
0793f83f | 11324 | break; |
3786b942 AE |
11325 | case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: |
11326 | bp->mf_config[vn] = 0; | |
11327 | break; | |
0793f83f DK |
11328 | default: |
11329 | /* Unknown configuration: reset mf_config */ | |
11330 | bp->mf_config[vn] = 0; | |
51c1a580 | 11331 | BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); |
0793f83f DK |
11332 | } |
11333 | } | |
a2fbb9ea | 11334 | |
2691d51d | 11335 | BNX2X_DEV_INFO("%s function mode\n", |
fb3bff17 | 11336 | IS_MF(bp) ? "multi" : "single"); |
2691d51d | 11337 | |
0793f83f DK |
11338 | switch (bp->mf_mode) { |
11339 | case MULTI_FUNCTION_SD: | |
11340 | val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & | |
11341 | FUNC_MF_CFG_E1HOV_TAG_MASK; | |
2691d51d | 11342 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { |
fb3bff17 | 11343 | bp->mf_ov = val; |
619c5cb6 VZ |
11344 | bp->path_has_ovlan = true; |
11345 | ||
51c1a580 MS |
11346 | BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", |
11347 | func, bp->mf_ov, bp->mf_ov); | |
2691d51d | 11348 | } else { |
619c5cb6 | 11349 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11350 | "No valid MF OV for func %d, aborting\n", |
11351 | func); | |
619c5cb6 | 11352 | return -EPERM; |
34f80b04 | 11353 | } |
0793f83f | 11354 | break; |
a3348722 BW |
11355 | case MULTI_FUNCTION_AFEX: |
11356 | BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); | |
11357 | break; | |
0793f83f | 11358 | case MULTI_FUNCTION_SI: |
51c1a580 MS |
11359 | BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", |
11360 | func); | |
0793f83f DK |
11361 | break; |
11362 | default: | |
11363 | if (vn) { | |
619c5cb6 | 11364 | dev_err(&bp->pdev->dev, |
51c1a580 MS |
11365 | "VN %d is in a single function mode, aborting\n", |
11366 | vn); | |
619c5cb6 | 11367 | return -EPERM; |
2691d51d | 11368 | } |
0793f83f | 11369 | break; |
34f80b04 | 11370 | } |
0793f83f | 11371 | |
619c5cb6 VZ |
11372 | /* check if other port on the path needs ovlan: |
11373 | * Since MF configuration is shared between ports | |
11374 | * Possible mixed modes are only | |
11375 | * {SF, SI} {SF, SD} {SD, SF} {SI, SF} | |
11376 | */ | |
11377 | if (CHIP_MODE_IS_4_PORT(bp) && | |
11378 | !bp->path_has_ovlan && | |
11379 | !IS_MF(bp) && | |
11380 | bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { | |
11381 | u8 other_port = !BP_PORT(bp); | |
11382 | u8 other_func = BP_PATH(bp) + 2*other_port; | |
11383 | val = MF_CFG_RD(bp, | |
11384 | func_mf_config[other_func].e1hov_tag); | |
11385 | if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) | |
11386 | bp->path_has_ovlan = true; | |
11387 | } | |
34f80b04 | 11388 | } |
a2fbb9ea | 11389 | |
f2e0899f DK |
11390 | /* adjust igu_sb_cnt to MF for E1x */ |
11391 | if (CHIP_IS_E1x(bp) && IS_MF(bp)) | |
523224a3 DK |
11392 | bp->igu_sb_cnt /= E1HVN_MAX; |
11393 | ||
619c5cb6 VZ |
11394 | /* port info */ |
11395 | bnx2x_get_port_hwinfo(bp); | |
f2e0899f | 11396 | |
0793f83f DK |
11397 | /* Get MAC addresses */ |
11398 | bnx2x_get_mac_hwinfo(bp); | |
a2fbb9ea | 11399 | |
2ba45142 | 11400 | bnx2x_get_cnic_info(bp); |
2ba45142 | 11401 | |
34f80b04 EG |
11402 | return rc; |
11403 | } | |
11404 | ||
0329aba1 | 11405 | static void bnx2x_read_fwinfo(struct bnx2x *bp) |
34f24c7f VZ |
11406 | { |
11407 | int cnt, i, block_end, rodi; | |
fcdf95cb | 11408 | char vpd_start[BNX2X_VPD_LEN+1]; |
34f24c7f VZ |
11409 | char str_id_reg[VENDOR_ID_LEN+1]; |
11410 | char str_id_cap[VENDOR_ID_LEN+1]; | |
fcdf95cb BW |
11411 | char *vpd_data; |
11412 | char *vpd_extended_data = NULL; | |
34f24c7f VZ |
11413 | u8 len; |
11414 | ||
fcdf95cb | 11415 | cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); |
34f24c7f VZ |
11416 | memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); |
11417 | ||
11418 | if (cnt < BNX2X_VPD_LEN) | |
11419 | goto out_not_found; | |
11420 | ||
fcdf95cb BW |
11421 | /* VPD RO tag should be first tag after identifier string, hence |
11422 | * we should be able to find it in first BNX2X_VPD_LEN chars | |
11423 | */ | |
11424 | i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN, | |
34f24c7f VZ |
11425 | PCI_VPD_LRDT_RO_DATA); |
11426 | if (i < 0) | |
11427 | goto out_not_found; | |
11428 | ||
34f24c7f | 11429 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + |
fcdf95cb | 11430 | pci_vpd_lrdt_size(&vpd_start[i]); |
34f24c7f VZ |
11431 | |
11432 | i += PCI_VPD_LRDT_TAG_SIZE; | |
11433 | ||
fcdf95cb BW |
11434 | if (block_end > BNX2X_VPD_LEN) { |
11435 | vpd_extended_data = kmalloc(block_end, GFP_KERNEL); | |
11436 | if (vpd_extended_data == NULL) | |
11437 | goto out_not_found; | |
11438 | ||
11439 | /* read rest of vpd image into vpd_extended_data */ | |
11440 | memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN); | |
11441 | cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, | |
11442 | block_end - BNX2X_VPD_LEN, | |
11443 | vpd_extended_data + BNX2X_VPD_LEN); | |
11444 | if (cnt < (block_end - BNX2X_VPD_LEN)) | |
11445 | goto out_not_found; | |
11446 | vpd_data = vpd_extended_data; | |
11447 | } else | |
11448 | vpd_data = vpd_start; | |
11449 | ||
11450 | /* now vpd_data holds full vpd content in both cases */ | |
34f24c7f VZ |
11451 | |
11452 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11453 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
11454 | if (rodi < 0) | |
11455 | goto out_not_found; | |
11456 | ||
11457 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11458 | ||
11459 | if (len != VENDOR_ID_LEN) | |
11460 | goto out_not_found; | |
11461 | ||
11462 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11463 | ||
11464 | /* vendor specific info */ | |
11465 | snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); | |
11466 | snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL); | |
11467 | if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) || | |
11468 | !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) { | |
11469 | ||
11470 | rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end, | |
11471 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
11472 | if (rodi >= 0) { | |
11473 | len = pci_vpd_info_field_size(&vpd_data[rodi]); | |
11474 | ||
11475 | rodi += PCI_VPD_INFO_FLD_HDR_SIZE; | |
11476 | ||
11477 | if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) { | |
11478 | memcpy(bp->fw_ver, &vpd_data[rodi], len); | |
11479 | bp->fw_ver[len] = ' '; | |
11480 | } | |
11481 | } | |
fcdf95cb | 11482 | kfree(vpd_extended_data); |
34f24c7f VZ |
11483 | return; |
11484 | } | |
11485 | out_not_found: | |
fcdf95cb | 11486 | kfree(vpd_extended_data); |
34f24c7f VZ |
11487 | return; |
11488 | } | |
11489 | ||
0329aba1 | 11490 | static void bnx2x_set_modes_bitmap(struct bnx2x *bp) |
619c5cb6 VZ |
11491 | { |
11492 | u32 flags = 0; | |
11493 | ||
11494 | if (CHIP_REV_IS_FPGA(bp)) | |
11495 | SET_FLAGS(flags, MODE_FPGA); | |
11496 | else if (CHIP_REV_IS_EMUL(bp)) | |
11497 | SET_FLAGS(flags, MODE_EMUL); | |
11498 | else | |
11499 | SET_FLAGS(flags, MODE_ASIC); | |
11500 | ||
11501 | if (CHIP_MODE_IS_4_PORT(bp)) | |
11502 | SET_FLAGS(flags, MODE_PORT4); | |
11503 | else | |
11504 | SET_FLAGS(flags, MODE_PORT2); | |
11505 | ||
11506 | if (CHIP_IS_E2(bp)) | |
11507 | SET_FLAGS(flags, MODE_E2); | |
11508 | else if (CHIP_IS_E3(bp)) { | |
11509 | SET_FLAGS(flags, MODE_E3); | |
11510 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
11511 | SET_FLAGS(flags, MODE_E3_A0); | |
6383c0b3 AE |
11512 | else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ |
11513 | SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); | |
619c5cb6 VZ |
11514 | } |
11515 | ||
11516 | if (IS_MF(bp)) { | |
11517 | SET_FLAGS(flags, MODE_MF); | |
11518 | switch (bp->mf_mode) { | |
11519 | case MULTI_FUNCTION_SD: | |
11520 | SET_FLAGS(flags, MODE_MF_SD); | |
11521 | break; | |
11522 | case MULTI_FUNCTION_SI: | |
11523 | SET_FLAGS(flags, MODE_MF_SI); | |
11524 | break; | |
a3348722 BW |
11525 | case MULTI_FUNCTION_AFEX: |
11526 | SET_FLAGS(flags, MODE_MF_AFEX); | |
11527 | break; | |
619c5cb6 VZ |
11528 | } |
11529 | } else | |
11530 | SET_FLAGS(flags, MODE_SF); | |
11531 | ||
11532 | #if defined(__LITTLE_ENDIAN) | |
11533 | SET_FLAGS(flags, MODE_LITTLE_ENDIAN); | |
11534 | #else /*(__BIG_ENDIAN)*/ | |
11535 | SET_FLAGS(flags, MODE_BIG_ENDIAN); | |
11536 | #endif | |
11537 | INIT_MODE_FLAGS(bp) = flags; | |
11538 | } | |
11539 | ||
0329aba1 | 11540 | static int bnx2x_init_bp(struct bnx2x *bp) |
34f80b04 | 11541 | { |
f2e0899f | 11542 | int func; |
34f80b04 EG |
11543 | int rc; |
11544 | ||
34f80b04 | 11545 | mutex_init(&bp->port.phy_mutex); |
c4ff7cbf | 11546 | mutex_init(&bp->fw_mb_mutex); |
bb7e95c8 | 11547 | spin_lock_init(&bp->stats_lock); |
507393eb | 11548 | sema_init(&bp->stats_sema, 1); |
55c11941 | 11549 | |
1cf167f2 | 11550 | INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); |
7be08a72 | 11551 | INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); |
3deb8167 | 11552 | INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); |
1ab4434c AE |
11553 | if (IS_PF(bp)) { |
11554 | rc = bnx2x_get_hwinfo(bp); | |
11555 | if (rc) | |
11556 | return rc; | |
11557 | } else { | |
e09b74d0 | 11558 | eth_zero_addr(bp->dev->dev_addr); |
1ab4434c | 11559 | } |
34f80b04 | 11560 | |
619c5cb6 VZ |
11561 | bnx2x_set_modes_bitmap(bp); |
11562 | ||
11563 | rc = bnx2x_alloc_mem_bp(bp); | |
11564 | if (rc) | |
11565 | return rc; | |
523224a3 | 11566 | |
34f24c7f | 11567 | bnx2x_read_fwinfo(bp); |
f2e0899f DK |
11568 | |
11569 | func = BP_FUNC(bp); | |
11570 | ||
34f80b04 | 11571 | /* need to reset chip if undi was active */ |
1ab4434c | 11572 | if (IS_PF(bp) && !BP_NOMCP(bp)) { |
452427b0 YM |
11573 | /* init fw_seq */ |
11574 | bp->fw_seq = | |
11575 | SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | |
11576 | DRV_MSG_SEQ_NUMBER_MASK; | |
11577 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | |
11578 | ||
11579 | bnx2x_prev_unload(bp); | |
11580 | } | |
11581 | ||
34f80b04 | 11582 | if (CHIP_REV_IS_FPGA(bp)) |
cdaa7cb8 | 11583 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
34f80b04 EG |
11584 | |
11585 | if (BP_NOMCP(bp) && (func == 0)) | |
51c1a580 | 11586 | dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); |
34f80b04 | 11587 | |
614c76df | 11588 | bp->disable_tpa = disable_tpa; |
a3348722 | 11589 | bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp); |
614c76df | 11590 | |
7a9b2557 | 11591 | /* Set TPA flags */ |
614c76df | 11592 | if (bp->disable_tpa) { |
621b4d66 | 11593 | bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
11594 | bp->dev->features &= ~NETIF_F_LRO; |
11595 | } else { | |
621b4d66 | 11596 | bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG); |
7a9b2557 VZ |
11597 | bp->dev->features |= NETIF_F_LRO; |
11598 | } | |
11599 | ||
a18f5128 EG |
11600 | if (CHIP_IS_E1(bp)) |
11601 | bp->dropless_fc = 0; | |
11602 | else | |
7964211d | 11603 | bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); |
a18f5128 | 11604 | |
8d5726c4 | 11605 | bp->mrrs = mrrs; |
7a9b2557 | 11606 | |
a3348722 | 11607 | bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL; |
1ab4434c AE |
11608 | if (IS_VF(bp)) |
11609 | bp->rx_ring_size = MAX_RX_AVAIL; | |
34f80b04 | 11610 | |
7d323bfd | 11611 | /* make sure that the numbers are in the right granularity */ |
523224a3 DK |
11612 | bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; |
11613 | bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; | |
34f80b04 | 11614 | |
fc543637 | 11615 | bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; |
34f80b04 EG |
11616 | |
11617 | init_timer(&bp->timer); | |
11618 | bp->timer.expires = jiffies + bp->current_interval; | |
11619 | bp->timer.data = (unsigned long) bp; | |
11620 | bp->timer.function = bnx2x_timer; | |
11621 | ||
0370cf90 BW |
11622 | if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && |
11623 | SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && | |
11624 | SHMEM2_RD(bp, dcbx_lldp_params_offset) && | |
11625 | SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { | |
11626 | bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); | |
11627 | bnx2x_dcbx_init_params(bp); | |
11628 | } else { | |
11629 | bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); | |
11630 | } | |
e4901dde | 11631 | |
619c5cb6 VZ |
11632 | if (CHIP_IS_E1x(bp)) |
11633 | bp->cnic_base_cl_id = FP_SB_MAX_E1x; | |
11634 | else | |
11635 | bp->cnic_base_cl_id = FP_SB_MAX_E2; | |
619c5cb6 | 11636 | |
6383c0b3 | 11637 | /* multiple tx priority */ |
1ab4434c AE |
11638 | if (IS_VF(bp)) |
11639 | bp->max_cos = 1; | |
11640 | else if (CHIP_IS_E1x(bp)) | |
6383c0b3 | 11641 | bp->max_cos = BNX2X_MULTI_TX_COS_E1X; |
1ab4434c | 11642 | else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) |
6383c0b3 | 11643 | bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; |
1ab4434c | 11644 | else if (CHIP_IS_E3B0(bp)) |
6383c0b3 | 11645 | bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; |
1ab4434c AE |
11646 | else |
11647 | BNX2X_ERR("unknown chip %x revision %x\n", | |
11648 | CHIP_NUM(bp), CHIP_REV(bp)); | |
11649 | BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); | |
6383c0b3 | 11650 | |
55c11941 MS |
11651 | /* We need at least one default status block for slow-path events, |
11652 | * second status block for the L2 queue, and a third status block for | |
16a5fd92 | 11653 | * CNIC if supported. |
55c11941 | 11654 | */ |
60cad4e6 AE |
11655 | if (IS_VF(bp)) |
11656 | bp->min_msix_vec_cnt = 1; | |
11657 | else if (CNIC_SUPPORT(bp)) | |
55c11941 | 11658 | bp->min_msix_vec_cnt = 3; |
60cad4e6 | 11659 | else /* PF w/o cnic */ |
55c11941 MS |
11660 | bp->min_msix_vec_cnt = 2; |
11661 | BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); | |
11662 | ||
5bb680d6 MS |
11663 | bp->dump_preset_idx = 1; |
11664 | ||
34f80b04 | 11665 | return rc; |
a2fbb9ea ET |
11666 | } |
11667 | ||
de0c62db DK |
11668 | /**************************************************************************** |
11669 | * General service functions | |
11670 | ****************************************************************************/ | |
a2fbb9ea | 11671 | |
619c5cb6 VZ |
11672 | /* |
11673 | * net_device service functions | |
11674 | */ | |
11675 | ||
bb2a0f7a | 11676 | /* called with rtnl_lock */ |
a2fbb9ea ET |
11677 | static int bnx2x_open(struct net_device *dev) |
11678 | { | |
11679 | struct bnx2x *bp = netdev_priv(dev); | |
c9ee9206 VZ |
11680 | bool global = false; |
11681 | int other_engine = BP_PATH(bp) ? 0 : 1; | |
889b9af3 | 11682 | bool other_load_status, load_status; |
8395be5e | 11683 | int rc; |
a2fbb9ea | 11684 | |
1355b704 MY |
11685 | bp->stats_init = true; |
11686 | ||
6eccabb3 EG |
11687 | netif_carrier_off(dev); |
11688 | ||
a2fbb9ea ET |
11689 | bnx2x_set_power_state(bp, PCI_D0); |
11690 | ||
ad5afc89 | 11691 | /* If parity had happen during the unload, then attentions |
c9ee9206 VZ |
11692 | * and/or RECOVERY_IN_PROGRES may still be set. In this case we |
11693 | * want the first function loaded on the current engine to | |
11694 | * complete the recovery. | |
ad5afc89 | 11695 | * Parity recovery is only relevant for PF driver. |
c9ee9206 | 11696 | */ |
ad5afc89 AE |
11697 | if (IS_PF(bp)) { |
11698 | other_load_status = bnx2x_get_load_status(bp, other_engine); | |
11699 | load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); | |
11700 | if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || | |
11701 | bnx2x_chk_parity_attn(bp, &global, true)) { | |
11702 | do { | |
11703 | /* If there are attentions and they are in a | |
11704 | * global blocks, set the GLOBAL_RESET bit | |
11705 | * regardless whether it will be this function | |
11706 | * that will complete the recovery or not. | |
11707 | */ | |
11708 | if (global) | |
11709 | bnx2x_set_reset_global(bp); | |
72fd0718 | 11710 | |
ad5afc89 AE |
11711 | /* Only the first function on the current |
11712 | * engine should try to recover in open. In case | |
11713 | * of attentions in global blocks only the first | |
11714 | * in the chip should try to recover. | |
11715 | */ | |
11716 | if ((!load_status && | |
11717 | (!global || !other_load_status)) && | |
11718 | bnx2x_trylock_leader_lock(bp) && | |
11719 | !bnx2x_leader_reset(bp)) { | |
11720 | netdev_info(bp->dev, | |
11721 | "Recovered in open\n"); | |
11722 | break; | |
11723 | } | |
72fd0718 | 11724 | |
ad5afc89 AE |
11725 | /* recovery has failed... */ |
11726 | bnx2x_set_power_state(bp, PCI_D3hot); | |
11727 | bp->recovery_state = BNX2X_RECOVERY_FAILED; | |
72fd0718 | 11728 | |
ad5afc89 AE |
11729 | BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" |
11730 | "If you still see this message after a few retries then power cycle is required.\n"); | |
72fd0718 | 11731 | |
ad5afc89 AE |
11732 | return -EAGAIN; |
11733 | } while (0); | |
11734 | } | |
11735 | } | |
72fd0718 VZ |
11736 | |
11737 | bp->recovery_state = BNX2X_RECOVERY_DONE; | |
8395be5e AE |
11738 | rc = bnx2x_nic_load(bp, LOAD_OPEN); |
11739 | if (rc) | |
11740 | return rc; | |
11741 | return bnx2x_open_epilog(bp); | |
a2fbb9ea ET |
11742 | } |
11743 | ||
bb2a0f7a | 11744 | /* called with rtnl_lock */ |
56ad3152 | 11745 | static int bnx2x_close(struct net_device *dev) |
a2fbb9ea | 11746 | { |
a2fbb9ea ET |
11747 | struct bnx2x *bp = netdev_priv(dev); |
11748 | ||
11749 | /* Unload the driver, release IRQs */ | |
5d07d868 | 11750 | bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); |
c9ee9206 | 11751 | |
a2fbb9ea ET |
11752 | return 0; |
11753 | } | |
11754 | ||
1191cb83 ED |
11755 | static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, |
11756 | struct bnx2x_mcast_ramrod_params *p) | |
6e30dd4e | 11757 | { |
619c5cb6 VZ |
11758 | int mc_count = netdev_mc_count(bp->dev); |
11759 | struct bnx2x_mcast_list_elem *mc_mac = | |
11760 | kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC); | |
11761 | struct netdev_hw_addr *ha; | |
6e30dd4e | 11762 | |
619c5cb6 VZ |
11763 | if (!mc_mac) |
11764 | return -ENOMEM; | |
6e30dd4e | 11765 | |
619c5cb6 | 11766 | INIT_LIST_HEAD(&p->mcast_list); |
6e30dd4e | 11767 | |
619c5cb6 VZ |
11768 | netdev_for_each_mc_addr(ha, bp->dev) { |
11769 | mc_mac->mac = bnx2x_mc_addr(ha); | |
11770 | list_add_tail(&mc_mac->link, &p->mcast_list); | |
11771 | mc_mac++; | |
6e30dd4e | 11772 | } |
619c5cb6 VZ |
11773 | |
11774 | p->mcast_list_len = mc_count; | |
11775 | ||
11776 | return 0; | |
6e30dd4e VZ |
11777 | } |
11778 | ||
1191cb83 | 11779 | static void bnx2x_free_mcast_macs_list( |
619c5cb6 VZ |
11780 | struct bnx2x_mcast_ramrod_params *p) |
11781 | { | |
11782 | struct bnx2x_mcast_list_elem *mc_mac = | |
11783 | list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem, | |
11784 | link); | |
11785 | ||
11786 | WARN_ON(!mc_mac); | |
11787 | kfree(mc_mac); | |
11788 | } | |
11789 | ||
11790 | /** | |
11791 | * bnx2x_set_uc_list - configure a new unicast MACs list. | |
11792 | * | |
11793 | * @bp: driver handle | |
6e30dd4e | 11794 | * |
619c5cb6 | 11795 | * We will use zero (0) as a MAC type for these MACs. |
6e30dd4e | 11796 | */ |
1191cb83 | 11797 | static int bnx2x_set_uc_list(struct bnx2x *bp) |
6e30dd4e | 11798 | { |
619c5cb6 | 11799 | int rc; |
6e30dd4e | 11800 | struct net_device *dev = bp->dev; |
6e30dd4e | 11801 | struct netdev_hw_addr *ha; |
15192a8c | 11802 | struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; |
619c5cb6 | 11803 | unsigned long ramrod_flags = 0; |
6e30dd4e | 11804 | |
619c5cb6 VZ |
11805 | /* First schedule a cleanup up of old configuration */ |
11806 | rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); | |
11807 | if (rc < 0) { | |
11808 | BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); | |
11809 | return rc; | |
11810 | } | |
6e30dd4e VZ |
11811 | |
11812 | netdev_for_each_uc_addr(ha, dev) { | |
619c5cb6 VZ |
11813 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
11814 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
7b5342d9 YM |
11815 | if (rc == -EEXIST) { |
11816 | DP(BNX2X_MSG_SP, | |
11817 | "Failed to schedule ADD operations: %d\n", rc); | |
11818 | /* do not treat adding same MAC as error */ | |
11819 | rc = 0; | |
11820 | ||
11821 | } else if (rc < 0) { | |
11822 | ||
619c5cb6 VZ |
11823 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
11824 | rc); | |
11825 | return rc; | |
6e30dd4e VZ |
11826 | } |
11827 | } | |
11828 | ||
619c5cb6 VZ |
11829 | /* Execute the pending commands */ |
11830 | __set_bit(RAMROD_CONT, &ramrod_flags); | |
11831 | return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, | |
11832 | BNX2X_UC_LIST_MAC, &ramrod_flags); | |
6e30dd4e VZ |
11833 | } |
11834 | ||
1191cb83 | 11835 | static int bnx2x_set_mc_list(struct bnx2x *bp) |
6e30dd4e | 11836 | { |
619c5cb6 | 11837 | struct net_device *dev = bp->dev; |
3b603066 | 11838 | struct bnx2x_mcast_ramrod_params rparam = {NULL}; |
619c5cb6 | 11839 | int rc = 0; |
6e30dd4e | 11840 | |
619c5cb6 | 11841 | rparam.mcast_obj = &bp->mcast_obj; |
6e30dd4e | 11842 | |
619c5cb6 VZ |
11843 | /* first, clear all configured multicast MACs */ |
11844 | rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); | |
11845 | if (rc < 0) { | |
51c1a580 | 11846 | BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); |
619c5cb6 VZ |
11847 | return rc; |
11848 | } | |
6e30dd4e | 11849 | |
619c5cb6 VZ |
11850 | /* then, configure a new MACs list */ |
11851 | if (netdev_mc_count(dev)) { | |
11852 | rc = bnx2x_init_mcast_macs_list(bp, &rparam); | |
11853 | if (rc) { | |
51c1a580 MS |
11854 | BNX2X_ERR("Failed to create multicast MACs list: %d\n", |
11855 | rc); | |
619c5cb6 VZ |
11856 | return rc; |
11857 | } | |
6e30dd4e | 11858 | |
619c5cb6 VZ |
11859 | /* Now add the new MACs */ |
11860 | rc = bnx2x_config_mcast(bp, &rparam, | |
11861 | BNX2X_MCAST_CMD_ADD); | |
11862 | if (rc < 0) | |
51c1a580 MS |
11863 | BNX2X_ERR("Failed to set a new multicast configuration: %d\n", |
11864 | rc); | |
6e30dd4e | 11865 | |
619c5cb6 VZ |
11866 | bnx2x_free_mcast_macs_list(&rparam); |
11867 | } | |
6e30dd4e | 11868 | |
619c5cb6 | 11869 | return rc; |
6e30dd4e VZ |
11870 | } |
11871 | ||
619c5cb6 | 11872 | /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ |
9f6c9258 | 11873 | void bnx2x_set_rx_mode(struct net_device *dev) |
34f80b04 EG |
11874 | { |
11875 | struct bnx2x *bp = netdev_priv(dev); | |
34f80b04 EG |
11876 | |
11877 | if (bp->state != BNX2X_STATE_OPEN) { | |
11878 | DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); | |
11879 | return; | |
8b09be5f YM |
11880 | } else { |
11881 | /* Schedule an SP task to handle rest of change */ | |
11882 | DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n"); | |
11883 | smp_mb__before_clear_bit(); | |
11884 | set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state); | |
11885 | smp_mb__after_clear_bit(); | |
11886 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
34f80b04 | 11887 | } |
8b09be5f YM |
11888 | } |
11889 | ||
11890 | void bnx2x_set_rx_mode_inner(struct bnx2x *bp) | |
11891 | { | |
11892 | u32 rx_mode = BNX2X_RX_MODE_NORMAL; | |
34f80b04 | 11893 | |
619c5cb6 | 11894 | DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); |
34f80b04 | 11895 | |
8b09be5f YM |
11896 | netif_addr_lock_bh(bp->dev); |
11897 | ||
11898 | if (bp->dev->flags & IFF_PROMISC) { | |
34f80b04 | 11899 | rx_mode = BNX2X_RX_MODE_PROMISC; |
8b09be5f YM |
11900 | } else if ((bp->dev->flags & IFF_ALLMULTI) || |
11901 | ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && | |
11902 | CHIP_IS_E1(bp))) { | |
34f80b04 | 11903 | rx_mode = BNX2X_RX_MODE_ALLMULTI; |
8b09be5f | 11904 | } else { |
381ac16b AE |
11905 | if (IS_PF(bp)) { |
11906 | /* some multicasts */ | |
11907 | if (bnx2x_set_mc_list(bp) < 0) | |
11908 | rx_mode = BNX2X_RX_MODE_ALLMULTI; | |
34f80b04 | 11909 | |
8b09be5f YM |
11910 | /* release bh lock, as bnx2x_set_uc_list might sleep */ |
11911 | netif_addr_unlock_bh(bp->dev); | |
381ac16b AE |
11912 | if (bnx2x_set_uc_list(bp) < 0) |
11913 | rx_mode = BNX2X_RX_MODE_PROMISC; | |
8b09be5f | 11914 | netif_addr_lock_bh(bp->dev); |
381ac16b AE |
11915 | } else { |
11916 | /* configuring mcast to a vf involves sleeping (when we | |
8b09be5f | 11917 | * wait for the pf's response). |
381ac16b AE |
11918 | */ |
11919 | smp_mb__before_clear_bit(); | |
11920 | set_bit(BNX2X_SP_RTNL_VFPF_MCAST, | |
11921 | &bp->sp_rtnl_state); | |
11922 | smp_mb__after_clear_bit(); | |
11923 | schedule_delayed_work(&bp->sp_rtnl_task, 0); | |
11924 | } | |
34f80b04 EG |
11925 | } |
11926 | ||
11927 | bp->rx_mode = rx_mode; | |
614c76df DK |
11928 | /* handle ISCSI SD mode */ |
11929 | if (IS_MF_ISCSI_SD(bp)) | |
11930 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
619c5cb6 VZ |
11931 | |
11932 | /* Schedule the rx_mode command */ | |
11933 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { | |
11934 | set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); | |
8b09be5f | 11935 | netif_addr_unlock_bh(bp->dev); |
619c5cb6 VZ |
11936 | return; |
11937 | } | |
11938 | ||
381ac16b AE |
11939 | if (IS_PF(bp)) { |
11940 | bnx2x_set_storm_rx_mode(bp); | |
8b09be5f | 11941 | netif_addr_unlock_bh(bp->dev); |
381ac16b | 11942 | } else { |
8b09be5f YM |
11943 | /* VF will need to request the PF to make this change, and so |
11944 | * the VF needs to release the bottom-half lock prior to the | |
11945 | * request (as it will likely require sleep on the VF side) | |
381ac16b | 11946 | */ |
8b09be5f YM |
11947 | netif_addr_unlock_bh(bp->dev); |
11948 | bnx2x_vfpf_storm_rx_mode(bp); | |
381ac16b | 11949 | } |
34f80b04 EG |
11950 | } |
11951 | ||
c18487ee | 11952 | /* called with rtnl_lock */ |
01cd4528 EG |
11953 | static int bnx2x_mdio_read(struct net_device *netdev, int prtad, |
11954 | int devad, u16 addr) | |
a2fbb9ea | 11955 | { |
01cd4528 EG |
11956 | struct bnx2x *bp = netdev_priv(netdev); |
11957 | u16 value; | |
11958 | int rc; | |
a2fbb9ea | 11959 | |
01cd4528 EG |
11960 | DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", |
11961 | prtad, devad, addr); | |
a2fbb9ea | 11962 | |
01cd4528 EG |
11963 | /* The HW expects different devad if CL22 is used */ |
11964 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
c18487ee | 11965 | |
01cd4528 | 11966 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11967 | rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); |
01cd4528 EG |
11968 | bnx2x_release_phy_lock(bp); |
11969 | DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); | |
a2fbb9ea | 11970 | |
01cd4528 EG |
11971 | if (!rc) |
11972 | rc = value; | |
11973 | return rc; | |
11974 | } | |
a2fbb9ea | 11975 | |
01cd4528 EG |
11976 | /* called with rtnl_lock */ |
11977 | static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, | |
11978 | u16 addr, u16 value) | |
11979 | { | |
11980 | struct bnx2x *bp = netdev_priv(netdev); | |
01cd4528 EG |
11981 | int rc; |
11982 | ||
51c1a580 MS |
11983 | DP(NETIF_MSG_LINK, |
11984 | "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", | |
11985 | prtad, devad, addr, value); | |
01cd4528 | 11986 | |
01cd4528 EG |
11987 | /* The HW expects different devad if CL22 is used */ |
11988 | devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; | |
a2fbb9ea | 11989 | |
01cd4528 | 11990 | bnx2x_acquire_phy_lock(bp); |
e10bc84d | 11991 | rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); |
01cd4528 EG |
11992 | bnx2x_release_phy_lock(bp); |
11993 | return rc; | |
11994 | } | |
c18487ee | 11995 | |
01cd4528 EG |
11996 | /* called with rtnl_lock */ |
11997 | static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
11998 | { | |
11999 | struct bnx2x *bp = netdev_priv(dev); | |
12000 | struct mii_ioctl_data *mdio = if_mii(ifr); | |
a2fbb9ea | 12001 | |
01cd4528 EG |
12002 | DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", |
12003 | mdio->phy_id, mdio->reg_num, mdio->val_in); | |
a2fbb9ea | 12004 | |
01cd4528 EG |
12005 | if (!netif_running(dev)) |
12006 | return -EAGAIN; | |
12007 | ||
12008 | return mdio_mii_ioctl(&bp->mdio, mdio, cmd); | |
a2fbb9ea ET |
12009 | } |
12010 | ||
257ddbda | 12011 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a2fbb9ea ET |
12012 | static void poll_bnx2x(struct net_device *dev) |
12013 | { | |
12014 | struct bnx2x *bp = netdev_priv(dev); | |
14a15d61 | 12015 | int i; |
a2fbb9ea | 12016 | |
14a15d61 MS |
12017 | for_each_eth_queue(bp, i) { |
12018 | struct bnx2x_fastpath *fp = &bp->fp[i]; | |
12019 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); | |
12020 | } | |
a2fbb9ea ET |
12021 | } |
12022 | #endif | |
12023 | ||
614c76df DK |
12024 | static int bnx2x_validate_addr(struct net_device *dev) |
12025 | { | |
12026 | struct bnx2x *bp = netdev_priv(dev); | |
12027 | ||
e09b74d0 AE |
12028 | /* query the bulletin board for mac address configured by the PF */ |
12029 | if (IS_VF(bp)) | |
12030 | bnx2x_sample_bulletin(bp); | |
12031 | ||
51c1a580 MS |
12032 | if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) { |
12033 | BNX2X_ERR("Non-valid Ethernet address\n"); | |
614c76df | 12034 | return -EADDRNOTAVAIL; |
51c1a580 | 12035 | } |
614c76df DK |
12036 | return 0; |
12037 | } | |
12038 | ||
c64213cd SH |
12039 | static const struct net_device_ops bnx2x_netdev_ops = { |
12040 | .ndo_open = bnx2x_open, | |
12041 | .ndo_stop = bnx2x_close, | |
12042 | .ndo_start_xmit = bnx2x_start_xmit, | |
8307fa3e | 12043 | .ndo_select_queue = bnx2x_select_queue, |
6e30dd4e | 12044 | .ndo_set_rx_mode = bnx2x_set_rx_mode, |
c64213cd | 12045 | .ndo_set_mac_address = bnx2x_change_mac_addr, |
614c76df | 12046 | .ndo_validate_addr = bnx2x_validate_addr, |
c64213cd SH |
12047 | .ndo_do_ioctl = bnx2x_ioctl, |
12048 | .ndo_change_mtu = bnx2x_change_mtu, | |
66371c44 MM |
12049 | .ndo_fix_features = bnx2x_fix_features, |
12050 | .ndo_set_features = bnx2x_set_features, | |
c64213cd | 12051 | .ndo_tx_timeout = bnx2x_tx_timeout, |
257ddbda | 12052 | #ifdef CONFIG_NET_POLL_CONTROLLER |
c64213cd SH |
12053 | .ndo_poll_controller = poll_bnx2x, |
12054 | #endif | |
6383c0b3 | 12055 | .ndo_setup_tc = bnx2x_setup_tc, |
6411280a | 12056 | #ifdef CONFIG_BNX2X_SRIOV |
abc5a021 | 12057 | .ndo_set_vf_mac = bnx2x_set_vf_mac, |
3cdeec22 | 12058 | .ndo_set_vf_vlan = bnx2x_set_vf_vlan, |
3ec9f9ca | 12059 | .ndo_get_vf_config = bnx2x_get_vf_config, |
6411280a | 12060 | #endif |
55c11941 | 12061 | #ifdef NETDEV_FCOE_WWNN |
bf61ee14 VZ |
12062 | .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, |
12063 | #endif | |
8f20aa57 | 12064 | |
e0d1095a | 12065 | #ifdef CONFIG_NET_RX_BUSY_POLL |
8b80cda5 | 12066 | .ndo_busy_poll = bnx2x_low_latency_recv, |
8f20aa57 | 12067 | #endif |
c64213cd SH |
12068 | }; |
12069 | ||
1191cb83 | 12070 | static int bnx2x_set_coherency_mask(struct bnx2x *bp) |
619c5cb6 VZ |
12071 | { |
12072 | struct device *dev = &bp->pdev->dev; | |
12073 | ||
12074 | if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { | |
12075 | bp->flags |= USING_DAC_FLAG; | |
12076 | if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { | |
51c1a580 | 12077 | dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); |
619c5cb6 VZ |
12078 | return -EIO; |
12079 | } | |
12080 | } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { | |
12081 | dev_err(dev, "System does not support DMA, aborting\n"); | |
12082 | return -EIO; | |
12083 | } | |
12084 | ||
12085 | return 0; | |
12086 | } | |
12087 | ||
1ab4434c AE |
12088 | static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, |
12089 | struct net_device *dev, unsigned long board_type) | |
a2fbb9ea | 12090 | { |
a2fbb9ea | 12091 | int rc; |
c22610d0 | 12092 | u32 pci_cfg_dword; |
65087cfe AE |
12093 | bool chip_is_e1x = (board_type == BCM57710 || |
12094 | board_type == BCM57711 || | |
12095 | board_type == BCM57711E); | |
a2fbb9ea ET |
12096 | |
12097 | SET_NETDEV_DEV(dev, &pdev->dev); | |
a2fbb9ea | 12098 | |
34f80b04 EG |
12099 | bp->dev = dev; |
12100 | bp->pdev = pdev; | |
a2fbb9ea ET |
12101 | |
12102 | rc = pci_enable_device(pdev); | |
12103 | if (rc) { | |
cdaa7cb8 VZ |
12104 | dev_err(&bp->pdev->dev, |
12105 | "Cannot enable PCI device, aborting\n"); | |
a2fbb9ea ET |
12106 | goto err_out; |
12107 | } | |
12108 | ||
12109 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
cdaa7cb8 VZ |
12110 | dev_err(&bp->pdev->dev, |
12111 | "Cannot find PCI device base address, aborting\n"); | |
a2fbb9ea ET |
12112 | rc = -ENODEV; |
12113 | goto err_out_disable; | |
12114 | } | |
12115 | ||
1ab4434c AE |
12116 | if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { |
12117 | dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); | |
a2fbb9ea ET |
12118 | rc = -ENODEV; |
12119 | goto err_out_disable; | |
12120 | } | |
12121 | ||
092a5fc9 YR |
12122 | pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); |
12123 | if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == | |
12124 | PCICFG_REVESION_ID_ERROR_VAL) { | |
12125 | pr_err("PCI device error, probably due to fan failure, aborting\n"); | |
12126 | rc = -ENODEV; | |
12127 | goto err_out_disable; | |
12128 | } | |
12129 | ||
34f80b04 EG |
12130 | if (atomic_read(&pdev->enable_cnt) == 1) { |
12131 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | |
12132 | if (rc) { | |
cdaa7cb8 VZ |
12133 | dev_err(&bp->pdev->dev, |
12134 | "Cannot obtain PCI resources, aborting\n"); | |
34f80b04 EG |
12135 | goto err_out_disable; |
12136 | } | |
a2fbb9ea | 12137 | |
34f80b04 EG |
12138 | pci_set_master(pdev); |
12139 | pci_save_state(pdev); | |
12140 | } | |
a2fbb9ea | 12141 | |
1ab4434c | 12142 | if (IS_PF(bp)) { |
29ed74c3 | 12143 | if (!pdev->pm_cap) { |
1ab4434c AE |
12144 | dev_err(&bp->pdev->dev, |
12145 | "Cannot find power management capability, aborting\n"); | |
12146 | rc = -EIO; | |
12147 | goto err_out_release; | |
12148 | } | |
a2fbb9ea ET |
12149 | } |
12150 | ||
77c98e6a | 12151 | if (!pci_is_pcie(pdev)) { |
51c1a580 | 12152 | dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); |
a2fbb9ea ET |
12153 | rc = -EIO; |
12154 | goto err_out_release; | |
12155 | } | |
12156 | ||
619c5cb6 VZ |
12157 | rc = bnx2x_set_coherency_mask(bp); |
12158 | if (rc) | |
a2fbb9ea | 12159 | goto err_out_release; |
a2fbb9ea | 12160 | |
34f80b04 EG |
12161 | dev->mem_start = pci_resource_start(pdev, 0); |
12162 | dev->base_addr = dev->mem_start; | |
12163 | dev->mem_end = pci_resource_end(pdev, 0); | |
a2fbb9ea ET |
12164 | |
12165 | dev->irq = pdev->irq; | |
12166 | ||
275f165f | 12167 | bp->regview = pci_ioremap_bar(pdev, 0); |
a2fbb9ea | 12168 | if (!bp->regview) { |
cdaa7cb8 VZ |
12169 | dev_err(&bp->pdev->dev, |
12170 | "Cannot map register space, aborting\n"); | |
a2fbb9ea ET |
12171 | rc = -ENOMEM; |
12172 | goto err_out_release; | |
12173 | } | |
12174 | ||
c22610d0 AE |
12175 | /* In E1/E1H use pci device function given by kernel. |
12176 | * In E2/E3 read physical function from ME register since these chips | |
12177 | * support Physical Device Assignment where kernel BDF maybe arbitrary | |
12178 | * (depending on hypervisor). | |
12179 | */ | |
2de67439 | 12180 | if (chip_is_e1x) { |
c22610d0 | 12181 | bp->pf_num = PCI_FUNC(pdev->devfn); |
2de67439 YM |
12182 | } else { |
12183 | /* chip is E2/3*/ | |
c22610d0 AE |
12184 | pci_read_config_dword(bp->pdev, |
12185 | PCICFG_ME_REGISTER, &pci_cfg_dword); | |
12186 | bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> | |
2de67439 | 12187 | ME_REG_ABS_PF_NUM_SHIFT); |
c22610d0 | 12188 | } |
51c1a580 | 12189 | BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); |
c22610d0 | 12190 | |
34f80b04 EG |
12191 | /* clean indirect addresses */ |
12192 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | |
12193 | PCICFG_VENDOR_ID_OFFSET); | |
a5c53dbc DK |
12194 | /* |
12195 | * Clean the following indirect addresses for all functions since it | |
9f0096a1 DK |
12196 | * is not used by the driver. |
12197 | */ | |
1ab4434c AE |
12198 | if (IS_PF(bp)) { |
12199 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | |
12200 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | |
12201 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | |
12202 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | |
12203 | ||
12204 | if (chip_is_e1x) { | |
12205 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | |
12206 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | |
12207 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | |
12208 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | |
12209 | } | |
a5c53dbc | 12210 | |
1ab4434c AE |
12211 | /* Enable internal target-read (in case we are probed after PF |
12212 | * FLR). Must be done prior to any BAR read access. Only for | |
12213 | * 57712 and up | |
12214 | */ | |
12215 | if (!chip_is_e1x) | |
12216 | REG_WR(bp, | |
12217 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
a5c53dbc | 12218 | } |
a2fbb9ea | 12219 | |
34f80b04 | 12220 | dev->watchdog_timeo = TX_TIMEOUT; |
a2fbb9ea | 12221 | |
c64213cd | 12222 | dev->netdev_ops = &bnx2x_netdev_ops; |
005a07ba | 12223 | bnx2x_set_ethtool_ops(bp, dev); |
5316bc0b | 12224 | |
01789349 JP |
12225 | dev->priv_flags |= IFF_UNICAST_FLT; |
12226 | ||
66371c44 | 12227 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
621b4d66 DK |
12228 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | |
12229 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | | |
f646968f | 12230 | NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; |
a848ade4 | 12231 | if (!CHIP_IS_E1x(bp)) { |
65bc0cfe | 12232 | dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; |
a848ade4 DK |
12233 | dev->hw_enc_features = |
12234 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | | |
12235 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | | |
65bc0cfe | 12236 | NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL; |
a848ade4 | 12237 | } |
66371c44 MM |
12238 | |
12239 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
12240 | NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; | |
12241 | ||
f646968f | 12242 | dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; |
5316bc0b | 12243 | if (bp->flags & USING_DAC_FLAG) |
66371c44 | 12244 | dev->features |= NETIF_F_HIGHDMA; |
a2fbb9ea | 12245 | |
538dd2e3 MB |
12246 | /* Add Loopback capability to the device */ |
12247 | dev->hw_features |= NETIF_F_LOOPBACK; | |
12248 | ||
98507672 | 12249 | #ifdef BCM_DCBNL |
785b9b1a SR |
12250 | dev->dcbnl_ops = &bnx2x_dcbnl_ops; |
12251 | #endif | |
12252 | ||
01cd4528 EG |
12253 | /* get_port_hwinfo() will set prtad and mmds properly */ |
12254 | bp->mdio.prtad = MDIO_PRTAD_NONE; | |
12255 | bp->mdio.mmds = 0; | |
12256 | bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
12257 | bp->mdio.dev = dev; | |
12258 | bp->mdio.mdio_read = bnx2x_mdio_read; | |
12259 | bp->mdio.mdio_write = bnx2x_mdio_write; | |
12260 | ||
a2fbb9ea ET |
12261 | return 0; |
12262 | ||
a2fbb9ea | 12263 | err_out_release: |
34f80b04 EG |
12264 | if (atomic_read(&pdev->enable_cnt) == 1) |
12265 | pci_release_regions(pdev); | |
a2fbb9ea ET |
12266 | |
12267 | err_out_disable: | |
12268 | pci_disable_device(pdev); | |
12269 | pci_set_drvdata(pdev, NULL); | |
12270 | ||
12271 | err_out: | |
12272 | return rc; | |
12273 | } | |
12274 | ||
ca1ee4b2 DK |
12275 | static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, |
12276 | enum bnx2x_pci_bus_speed *speed) | |
25047950 | 12277 | { |
ca1ee4b2 | 12278 | u32 link_speed, val = 0; |
25047950 | 12279 | |
1ab4434c | 12280 | pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val); |
37f9ce62 | 12281 | *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; |
25047950 | 12282 | |
ca1ee4b2 DK |
12283 | link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; |
12284 | ||
12285 | switch (link_speed) { | |
12286 | case 3: | |
12287 | *speed = BNX2X_PCI_LINK_SPEED_8000; | |
12288 | break; | |
12289 | case 2: | |
12290 | *speed = BNX2X_PCI_LINK_SPEED_5000; | |
12291 | break; | |
12292 | default: | |
12293 | *speed = BNX2X_PCI_LINK_SPEED_2500; | |
12294 | } | |
25047950 | 12295 | } |
37f9ce62 | 12296 | |
6891dd25 | 12297 | static int bnx2x_check_firmware(struct bnx2x *bp) |
94a78b79 | 12298 | { |
37f9ce62 | 12299 | const struct firmware *firmware = bp->firmware; |
94a78b79 VZ |
12300 | struct bnx2x_fw_file_hdr *fw_hdr; |
12301 | struct bnx2x_fw_file_section *sections; | |
94a78b79 | 12302 | u32 offset, len, num_ops; |
86564c3f | 12303 | __be16 *ops_offsets; |
94a78b79 | 12304 | int i; |
37f9ce62 | 12305 | const u8 *fw_ver; |
94a78b79 | 12306 | |
51c1a580 MS |
12307 | if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { |
12308 | BNX2X_ERR("Wrong FW size\n"); | |
94a78b79 | 12309 | return -EINVAL; |
51c1a580 | 12310 | } |
94a78b79 VZ |
12311 | |
12312 | fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; | |
12313 | sections = (struct bnx2x_fw_file_section *)fw_hdr; | |
12314 | ||
12315 | /* Make sure none of the offsets and sizes make us read beyond | |
12316 | * the end of the firmware data */ | |
12317 | for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { | |
12318 | offset = be32_to_cpu(sections[i].offset); | |
12319 | len = be32_to_cpu(sections[i].len); | |
12320 | if (offset + len > firmware->size) { | |
51c1a580 | 12321 | BNX2X_ERR("Section %d length is out of bounds\n", i); |
94a78b79 VZ |
12322 | return -EINVAL; |
12323 | } | |
12324 | } | |
12325 | ||
12326 | /* Likewise for the init_ops offsets */ | |
12327 | offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); | |
86564c3f | 12328 | ops_offsets = (__force __be16 *)(firmware->data + offset); |
94a78b79 VZ |
12329 | num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); |
12330 | ||
12331 | for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { | |
12332 | if (be16_to_cpu(ops_offsets[i]) > num_ops) { | |
51c1a580 | 12333 | BNX2X_ERR("Section offset %d is out of bounds\n", i); |
94a78b79 VZ |
12334 | return -EINVAL; |
12335 | } | |
12336 | } | |
12337 | ||
12338 | /* Check FW version */ | |
12339 | offset = be32_to_cpu(fw_hdr->fw_version.offset); | |
12340 | fw_ver = firmware->data + offset; | |
12341 | if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) || | |
12342 | (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || | |
12343 | (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || | |
12344 | (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { | |
51c1a580 MS |
12345 | BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", |
12346 | fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], | |
12347 | BCM_5710_FW_MAJOR_VERSION, | |
94a78b79 VZ |
12348 | BCM_5710_FW_MINOR_VERSION, |
12349 | BCM_5710_FW_REVISION_VERSION, | |
12350 | BCM_5710_FW_ENGINEERING_VERSION); | |
ab6ad5a4 | 12351 | return -EINVAL; |
94a78b79 VZ |
12352 | } |
12353 | ||
12354 | return 0; | |
12355 | } | |
12356 | ||
1191cb83 | 12357 | static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12358 | { |
ab6ad5a4 EG |
12359 | const __be32 *source = (const __be32 *)_source; |
12360 | u32 *target = (u32 *)_target; | |
94a78b79 | 12361 | u32 i; |
94a78b79 VZ |
12362 | |
12363 | for (i = 0; i < n/4; i++) | |
12364 | target[i] = be32_to_cpu(source[i]); | |
12365 | } | |
12366 | ||
12367 | /* | |
12368 | Ops array is stored in the following format: | |
12369 | {op(8bit), offset(24bit, big endian), data(32bit, big endian)} | |
12370 | */ | |
1191cb83 | 12371 | static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12372 | { |
ab6ad5a4 EG |
12373 | const __be32 *source = (const __be32 *)_source; |
12374 | struct raw_op *target = (struct raw_op *)_target; | |
94a78b79 | 12375 | u32 i, j, tmp; |
94a78b79 | 12376 | |
ab6ad5a4 | 12377 | for (i = 0, j = 0; i < n/8; i++, j += 2) { |
94a78b79 VZ |
12378 | tmp = be32_to_cpu(source[j]); |
12379 | target[i].op = (tmp >> 24) & 0xff; | |
cdaa7cb8 VZ |
12380 | target[i].offset = tmp & 0xffffff; |
12381 | target[i].raw_data = be32_to_cpu(source[j + 1]); | |
94a78b79 VZ |
12382 | } |
12383 | } | |
ab6ad5a4 | 12384 | |
1aa8b471 | 12385 | /* IRO array is stored in the following format: |
523224a3 DK |
12386 | * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } |
12387 | */ | |
1191cb83 | 12388 | static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) |
523224a3 DK |
12389 | { |
12390 | const __be32 *source = (const __be32 *)_source; | |
12391 | struct iro *target = (struct iro *)_target; | |
12392 | u32 i, j, tmp; | |
12393 | ||
12394 | for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { | |
12395 | target[i].base = be32_to_cpu(source[j]); | |
12396 | j++; | |
12397 | tmp = be32_to_cpu(source[j]); | |
12398 | target[i].m1 = (tmp >> 16) & 0xffff; | |
12399 | target[i].m2 = tmp & 0xffff; | |
12400 | j++; | |
12401 | tmp = be32_to_cpu(source[j]); | |
12402 | target[i].m3 = (tmp >> 16) & 0xffff; | |
12403 | target[i].size = tmp & 0xffff; | |
12404 | j++; | |
12405 | } | |
12406 | } | |
12407 | ||
1191cb83 | 12408 | static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) |
94a78b79 | 12409 | { |
ab6ad5a4 EG |
12410 | const __be16 *source = (const __be16 *)_source; |
12411 | u16 *target = (u16 *)_target; | |
94a78b79 | 12412 | u32 i; |
94a78b79 VZ |
12413 | |
12414 | for (i = 0; i < n/2; i++) | |
12415 | target[i] = be16_to_cpu(source[i]); | |
12416 | } | |
12417 | ||
7995c64e JP |
12418 | #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ |
12419 | do { \ | |
12420 | u32 len = be32_to_cpu(fw_hdr->arr.len); \ | |
12421 | bp->arr = kmalloc(len, GFP_KERNEL); \ | |
e404decb | 12422 | if (!bp->arr) \ |
7995c64e | 12423 | goto lbl; \ |
7995c64e JP |
12424 | func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ |
12425 | (u8 *)bp->arr, len); \ | |
12426 | } while (0) | |
94a78b79 | 12427 | |
3b603066 | 12428 | static int bnx2x_init_firmware(struct bnx2x *bp) |
94a78b79 | 12429 | { |
c0ea452e | 12430 | const char *fw_file_name; |
94a78b79 | 12431 | struct bnx2x_fw_file_hdr *fw_hdr; |
45229b42 | 12432 | int rc; |
94a78b79 | 12433 | |
c0ea452e MS |
12434 | if (bp->firmware) |
12435 | return 0; | |
94a78b79 | 12436 | |
c0ea452e MS |
12437 | if (CHIP_IS_E1(bp)) |
12438 | fw_file_name = FW_FILE_NAME_E1; | |
12439 | else if (CHIP_IS_E1H(bp)) | |
12440 | fw_file_name = FW_FILE_NAME_E1H; | |
12441 | else if (!CHIP_IS_E1x(bp)) | |
12442 | fw_file_name = FW_FILE_NAME_E2; | |
12443 | else { | |
12444 | BNX2X_ERR("Unsupported chip revision\n"); | |
12445 | return -EINVAL; | |
12446 | } | |
12447 | BNX2X_DEV_INFO("Loading %s\n", fw_file_name); | |
94a78b79 | 12448 | |
c0ea452e MS |
12449 | rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); |
12450 | if (rc) { | |
12451 | BNX2X_ERR("Can't load firmware file %s\n", | |
12452 | fw_file_name); | |
12453 | goto request_firmware_exit; | |
12454 | } | |
eb2afd4a | 12455 | |
c0ea452e MS |
12456 | rc = bnx2x_check_firmware(bp); |
12457 | if (rc) { | |
12458 | BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); | |
12459 | goto request_firmware_exit; | |
94a78b79 VZ |
12460 | } |
12461 | ||
12462 | fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; | |
12463 | ||
12464 | /* Initialize the pointers to the init arrays */ | |
12465 | /* Blob */ | |
12466 | BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); | |
12467 | ||
12468 | /* Opcodes */ | |
12469 | BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); | |
12470 | ||
12471 | /* Offsets */ | |
ab6ad5a4 EG |
12472 | BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, |
12473 | be16_to_cpu_n); | |
94a78b79 VZ |
12474 | |
12475 | /* STORMs firmware */ | |
573f2035 EG |
12476 | INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + |
12477 | be32_to_cpu(fw_hdr->tsem_int_table_data.offset); | |
12478 | INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12479 | be32_to_cpu(fw_hdr->tsem_pram_data.offset); | |
12480 | INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12481 | be32_to_cpu(fw_hdr->usem_int_table_data.offset); | |
12482 | INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + | |
12483 | be32_to_cpu(fw_hdr->usem_pram_data.offset); | |
12484 | INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12485 | be32_to_cpu(fw_hdr->xsem_int_table_data.offset); | |
12486 | INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12487 | be32_to_cpu(fw_hdr->xsem_pram_data.offset); | |
12488 | INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + | |
12489 | be32_to_cpu(fw_hdr->csem_int_table_data.offset); | |
12490 | INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + | |
12491 | be32_to_cpu(fw_hdr->csem_pram_data.offset); | |
523224a3 DK |
12492 | /* IRO */ |
12493 | BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); | |
94a78b79 VZ |
12494 | |
12495 | return 0; | |
ab6ad5a4 | 12496 | |
523224a3 DK |
12497 | iro_alloc_err: |
12498 | kfree(bp->init_ops_offsets); | |
94a78b79 VZ |
12499 | init_offsets_alloc_err: |
12500 | kfree(bp->init_ops); | |
12501 | init_ops_alloc_err: | |
12502 | kfree(bp->init_data); | |
12503 | request_firmware_exit: | |
12504 | release_firmware(bp->firmware); | |
127d0a19 | 12505 | bp->firmware = NULL; |
94a78b79 VZ |
12506 | |
12507 | return rc; | |
12508 | } | |
12509 | ||
619c5cb6 VZ |
12510 | static void bnx2x_release_firmware(struct bnx2x *bp) |
12511 | { | |
12512 | kfree(bp->init_ops_offsets); | |
12513 | kfree(bp->init_ops); | |
12514 | kfree(bp->init_data); | |
12515 | release_firmware(bp->firmware); | |
eb2afd4a | 12516 | bp->firmware = NULL; |
619c5cb6 VZ |
12517 | } |
12518 | ||
619c5cb6 VZ |
12519 | static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { |
12520 | .init_hw_cmn_chip = bnx2x_init_hw_common_chip, | |
12521 | .init_hw_cmn = bnx2x_init_hw_common, | |
12522 | .init_hw_port = bnx2x_init_hw_port, | |
12523 | .init_hw_func = bnx2x_init_hw_func, | |
12524 | ||
12525 | .reset_hw_cmn = bnx2x_reset_common, | |
12526 | .reset_hw_port = bnx2x_reset_port, | |
12527 | .reset_hw_func = bnx2x_reset_func, | |
12528 | ||
12529 | .gunzip_init = bnx2x_gunzip_init, | |
12530 | .gunzip_end = bnx2x_gunzip_end, | |
12531 | ||
12532 | .init_fw = bnx2x_init_firmware, | |
12533 | .release_fw = bnx2x_release_firmware, | |
12534 | }; | |
12535 | ||
12536 | void bnx2x__init_func_obj(struct bnx2x *bp) | |
12537 | { | |
12538 | /* Prepare DMAE related driver resources */ | |
12539 | bnx2x_setup_dmae(bp); | |
12540 | ||
12541 | bnx2x_init_func_obj(bp, &bp->func_obj, | |
12542 | bnx2x_sp(bp, func_rdata), | |
12543 | bnx2x_sp_mapping(bp, func_rdata), | |
a3348722 BW |
12544 | bnx2x_sp(bp, func_afex_rdata), |
12545 | bnx2x_sp_mapping(bp, func_afex_rdata), | |
619c5cb6 VZ |
12546 | &bnx2x_func_sp_drv); |
12547 | } | |
12548 | ||
12549 | /* must be called after sriov-enable */ | |
1191cb83 | 12550 | static int bnx2x_set_qm_cid_count(struct bnx2x *bp) |
523224a3 | 12551 | { |
37ae41a9 | 12552 | int cid_count = BNX2X_L2_MAX_CID(bp); |
94a78b79 | 12553 | |
290ca2bb AE |
12554 | if (IS_SRIOV(bp)) |
12555 | cid_count += BNX2X_VF_CIDS; | |
12556 | ||
55c11941 MS |
12557 | if (CNIC_SUPPORT(bp)) |
12558 | cid_count += CNIC_CID_MAX; | |
290ca2bb | 12559 | |
523224a3 DK |
12560 | return roundup(cid_count, QM_CID_ROUND); |
12561 | } | |
f85582f8 | 12562 | |
619c5cb6 | 12563 | /** |
6383c0b3 | 12564 | * bnx2x_get_num_none_def_sbs - return the number of none default SBs |
619c5cb6 VZ |
12565 | * |
12566 | * @dev: pci device | |
12567 | * | |
12568 | */ | |
60cad4e6 | 12569 | static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt) |
619c5cb6 | 12570 | { |
ae2104be | 12571 | int index; |
1ab4434c | 12572 | u16 control = 0; |
619c5cb6 | 12573 | |
6383c0b3 AE |
12574 | /* |
12575 | * If MSI-X is not supported - return number of SBs needed to support | |
12576 | * one fast path queue: one FP queue + SB for CNIC | |
12577 | */ | |
ae2104be | 12578 | if (!pdev->msix_cap) { |
1ab4434c | 12579 | dev_info(&pdev->dev, "no msix capability found\n"); |
55c11941 | 12580 | return 1 + cnic_cnt; |
1ab4434c AE |
12581 | } |
12582 | dev_info(&pdev->dev, "msix capability found\n"); | |
619c5cb6 | 12583 | |
6383c0b3 AE |
12584 | /* |
12585 | * The value in the PCI configuration space is the index of the last | |
12586 | * entry, namely one less than the actual size of the table, which is | |
12587 | * exactly what we want to return from this function: number of all SBs | |
12588 | * without the default SB. | |
1ab4434c | 12589 | * For VFs there is no default SB, then we return (index+1). |
6383c0b3 | 12590 | */ |
ae2104be | 12591 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control); |
619c5cb6 | 12592 | |
1ab4434c | 12593 | index = control & PCI_MSIX_FLAGS_QSIZE; |
4bd9b0ff | 12594 | |
60cad4e6 | 12595 | return index; |
1ab4434c | 12596 | } |
523224a3 | 12597 | |
1ab4434c AE |
12598 | static int set_max_cos_est(int chip_id) |
12599 | { | |
12600 | switch (chip_id) { | |
f2e0899f DK |
12601 | case BCM57710: |
12602 | case BCM57711: | |
12603 | case BCM57711E: | |
1ab4434c | 12604 | return BNX2X_MULTI_TX_COS_E1X; |
f2e0899f | 12605 | case BCM57712: |
619c5cb6 | 12606 | case BCM57712_MF: |
1ab4434c AE |
12607 | case BCM57712_VF: |
12608 | return BNX2X_MULTI_TX_COS_E2_E3A0; | |
619c5cb6 VZ |
12609 | case BCM57800: |
12610 | case BCM57800_MF: | |
1ab4434c | 12611 | case BCM57800_VF: |
619c5cb6 VZ |
12612 | case BCM57810: |
12613 | case BCM57810_MF: | |
c3def943 YM |
12614 | case BCM57840_4_10: |
12615 | case BCM57840_2_20: | |
1ab4434c | 12616 | case BCM57840_O: |
c3def943 | 12617 | case BCM57840_MFO: |
1ab4434c | 12618 | case BCM57810_VF: |
619c5cb6 | 12619 | case BCM57840_MF: |
1ab4434c | 12620 | case BCM57840_VF: |
7e8e02df BW |
12621 | case BCM57811: |
12622 | case BCM57811_MF: | |
1ab4434c AE |
12623 | case BCM57811_VF: |
12624 | return BNX2X_MULTI_TX_COS_E3B0; | |
12625 | return 1; | |
f2e0899f | 12626 | default: |
1ab4434c | 12627 | pr_err("Unknown board_type (%d), aborting\n", chip_id); |
870634b0 | 12628 | return -ENODEV; |
f2e0899f | 12629 | } |
1ab4434c | 12630 | } |
f2e0899f | 12631 | |
1ab4434c AE |
12632 | static int set_is_vf(int chip_id) |
12633 | { | |
12634 | switch (chip_id) { | |
12635 | case BCM57712_VF: | |
12636 | case BCM57800_VF: | |
12637 | case BCM57810_VF: | |
12638 | case BCM57840_VF: | |
12639 | case BCM57811_VF: | |
12640 | return true; | |
12641 | default: | |
12642 | return false; | |
12643 | } | |
12644 | } | |
6383c0b3 | 12645 | |
1ab4434c AE |
12646 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); |
12647 | ||
12648 | static int bnx2x_init_one(struct pci_dev *pdev, | |
12649 | const struct pci_device_id *ent) | |
12650 | { | |
12651 | struct net_device *dev = NULL; | |
12652 | struct bnx2x *bp; | |
ca1ee4b2 DK |
12653 | int pcie_width; |
12654 | enum bnx2x_pci_bus_speed pcie_speed; | |
1ab4434c AE |
12655 | int rc, max_non_def_sbs; |
12656 | int rx_count, tx_count, rss_count, doorbell_size; | |
12657 | int max_cos_est; | |
12658 | bool is_vf; | |
12659 | int cnic_cnt; | |
12660 | ||
12661 | /* An estimated maximum supported CoS number according to the chip | |
12662 | * version. | |
12663 | * We will try to roughly estimate the maximum number of CoSes this chip | |
12664 | * may support in order to minimize the memory allocated for Tx | |
12665 | * netdev_queue's. This number will be accurately calculated during the | |
12666 | * initialization of bp->max_cos based on the chip versions AND chip | |
12667 | * revision in the bnx2x_init_bp(). | |
12668 | */ | |
12669 | max_cos_est = set_max_cos_est(ent->driver_data); | |
12670 | if (max_cos_est < 0) | |
12671 | return max_cos_est; | |
12672 | is_vf = set_is_vf(ent->driver_data); | |
12673 | cnic_cnt = is_vf ? 0 : 1; | |
12674 | ||
60cad4e6 AE |
12675 | max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt); |
12676 | ||
12677 | /* add another SB for VF as it has no default SB */ | |
12678 | max_non_def_sbs += is_vf ? 1 : 0; | |
6383c0b3 AE |
12679 | |
12680 | /* Maximum number of RSS queues: one IGU SB goes to CNIC */ | |
60cad4e6 | 12681 | rss_count = max_non_def_sbs - cnic_cnt; |
1ab4434c AE |
12682 | |
12683 | if (rss_count < 1) | |
12684 | return -EINVAL; | |
6383c0b3 AE |
12685 | |
12686 | /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ | |
55c11941 | 12687 | rx_count = rss_count + cnic_cnt; |
6383c0b3 | 12688 | |
1ab4434c | 12689 | /* Maximum number of netdev Tx queues: |
37ae41a9 | 12690 | * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 |
6383c0b3 | 12691 | */ |
55c11941 | 12692 | tx_count = rss_count * max_cos_est + cnic_cnt; |
f85582f8 | 12693 | |
a2fbb9ea | 12694 | /* dev zeroed in init_etherdev */ |
6383c0b3 | 12695 | dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); |
41de8d4c | 12696 | if (!dev) |
a2fbb9ea ET |
12697 | return -ENOMEM; |
12698 | ||
a2fbb9ea | 12699 | bp = netdev_priv(dev); |
a2fbb9ea | 12700 | |
1ab4434c AE |
12701 | bp->flags = 0; |
12702 | if (is_vf) | |
12703 | bp->flags |= IS_VF_FLAG; | |
12704 | ||
6383c0b3 | 12705 | bp->igu_sb_cnt = max_non_def_sbs; |
1ab4434c | 12706 | bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; |
6383c0b3 | 12707 | bp->msg_enable = debug; |
55c11941 | 12708 | bp->cnic_support = cnic_cnt; |
4bd9b0ff | 12709 | bp->cnic_probe = bnx2x_cnic_probe; |
55c11941 | 12710 | |
6383c0b3 | 12711 | pci_set_drvdata(pdev, dev); |
523224a3 | 12712 | |
1ab4434c | 12713 | rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); |
a2fbb9ea ET |
12714 | if (rc < 0) { |
12715 | free_netdev(dev); | |
12716 | return rc; | |
12717 | } | |
12718 | ||
1ab4434c AE |
12719 | BNX2X_DEV_INFO("This is a %s function\n", |
12720 | IS_PF(bp) ? "physical" : "virtual"); | |
55c11941 | 12721 | BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); |
1ab4434c | 12722 | BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); |
60aa0509 | 12723 | BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", |
2de67439 | 12724 | tx_count, rx_count); |
60aa0509 | 12725 | |
34f80b04 | 12726 | rc = bnx2x_init_bp(bp); |
693fc0d1 EG |
12727 | if (rc) |
12728 | goto init_one_exit; | |
12729 | ||
1ab4434c AE |
12730 | /* Map doorbells here as we need the real value of bp->max_cos which |
12731 | * is initialized in bnx2x_init_bp() to determine the number of | |
12732 | * l2 connections. | |
6383c0b3 | 12733 | */ |
1ab4434c | 12734 | if (IS_VF(bp)) { |
1d6f3cd8 | 12735 | bp->doorbells = bnx2x_vf_doorbells(bp); |
6411280a AE |
12736 | rc = bnx2x_vf_pci_alloc(bp); |
12737 | if (rc) | |
12738 | goto init_one_exit; | |
1ab4434c AE |
12739 | } else { |
12740 | doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); | |
12741 | if (doorbell_size > pci_resource_len(pdev, 2)) { | |
12742 | dev_err(&bp->pdev->dev, | |
12743 | "Cannot map doorbells, bar size too small, aborting\n"); | |
12744 | rc = -ENOMEM; | |
12745 | goto init_one_exit; | |
12746 | } | |
12747 | bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), | |
12748 | doorbell_size); | |
37ae41a9 | 12749 | } |
6383c0b3 AE |
12750 | if (!bp->doorbells) { |
12751 | dev_err(&bp->pdev->dev, | |
12752 | "Cannot map doorbell space, aborting\n"); | |
12753 | rc = -ENOMEM; | |
12754 | goto init_one_exit; | |
12755 | } | |
12756 | ||
be1f1ffa AE |
12757 | if (IS_VF(bp)) { |
12758 | rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); | |
12759 | if (rc) | |
12760 | goto init_one_exit; | |
12761 | } | |
12762 | ||
3c76feff AE |
12763 | /* Enable SRIOV if capability found in configuration space */ |
12764 | rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); | |
290ca2bb AE |
12765 | if (rc) |
12766 | goto init_one_exit; | |
12767 | ||
523224a3 | 12768 | /* calc qm_cid_count */ |
6383c0b3 | 12769 | bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); |
1ab4434c | 12770 | BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); |
523224a3 | 12771 | |
55c11941 | 12772 | /* disable FCOE L2 queue for E1x*/ |
62ac0dc9 | 12773 | if (CHIP_IS_E1x(bp)) |
ec6ba945 VZ |
12774 | bp->flags |= NO_FCOE_FLAG; |
12775 | ||
0e8d2ec5 MS |
12776 | /* Set bp->num_queues for MSI-X mode*/ |
12777 | bnx2x_set_num_queues(bp); | |
12778 | ||
25985edc | 12779 | /* Configure interrupt mode: try to enable MSI-X/MSI if |
0e8d2ec5 | 12780 | * needed. |
d6214d7a | 12781 | */ |
1ab4434c AE |
12782 | rc = bnx2x_set_int_mode(bp); |
12783 | if (rc) { | |
12784 | dev_err(&pdev->dev, "Cannot set interrupts\n"); | |
12785 | goto init_one_exit; | |
12786 | } | |
04c46736 | 12787 | BNX2X_DEV_INFO("set interrupts successfully\n"); |
d6214d7a | 12788 | |
1ab4434c | 12789 | /* register the net device */ |
b340007f VZ |
12790 | rc = register_netdev(dev); |
12791 | if (rc) { | |
12792 | dev_err(&pdev->dev, "Cannot register net device\n"); | |
12793 | goto init_one_exit; | |
12794 | } | |
1ab4434c | 12795 | BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); |
b340007f | 12796 | |
ec6ba945 VZ |
12797 | if (!NO_FCOE(bp)) { |
12798 | /* Add storage MAC address */ | |
12799 | rtnl_lock(); | |
12800 | dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
12801 | rtnl_unlock(); | |
12802 | } | |
ec6ba945 | 12803 | |
37f9ce62 | 12804 | bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); |
1ab4434c AE |
12805 | BNX2X_DEV_INFO("got pcie width %d and speed %d\n", |
12806 | pcie_width, pcie_speed); | |
d6214d7a | 12807 | |
ca1ee4b2 DK |
12808 | BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", |
12809 | board_info[ent->driver_data].name, | |
12810 | (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), | |
12811 | pcie_width, | |
12812 | pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" : | |
12813 | pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" : | |
12814 | pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" : | |
12815 | "Unknown", | |
12816 | dev->base_addr, bp->pdev->irq, dev->dev_addr); | |
c016201c | 12817 | |
a2fbb9ea | 12818 | return 0; |
34f80b04 EG |
12819 | |
12820 | init_one_exit: | |
12821 | if (bp->regview) | |
12822 | iounmap(bp->regview); | |
12823 | ||
1ab4434c | 12824 | if (IS_PF(bp) && bp->doorbells) |
34f80b04 EG |
12825 | iounmap(bp->doorbells); |
12826 | ||
12827 | free_netdev(dev); | |
12828 | ||
12829 | if (atomic_read(&pdev->enable_cnt) == 1) | |
12830 | pci_release_regions(pdev); | |
12831 | ||
12832 | pci_disable_device(pdev); | |
12833 | pci_set_drvdata(pdev, NULL); | |
12834 | ||
12835 | return rc; | |
a2fbb9ea ET |
12836 | } |
12837 | ||
b030ed2f YM |
12838 | static void __bnx2x_remove(struct pci_dev *pdev, |
12839 | struct net_device *dev, | |
12840 | struct bnx2x *bp, | |
12841 | bool remove_netdev) | |
a2fbb9ea | 12842 | { |
ec6ba945 VZ |
12843 | /* Delete storage MAC address */ |
12844 | if (!NO_FCOE(bp)) { | |
12845 | rtnl_lock(); | |
12846 | dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); | |
12847 | rtnl_unlock(); | |
12848 | } | |
ec6ba945 | 12849 | |
98507672 SR |
12850 | #ifdef BCM_DCBNL |
12851 | /* Delete app tlvs from dcbnl */ | |
12852 | bnx2x_dcbnl_update_applist(bp, true); | |
12853 | #endif | |
12854 | ||
a6d3a5ba BW |
12855 | if (IS_PF(bp) && |
12856 | !BP_NOMCP(bp) && | |
12857 | (bp->flags & BC_SUPPORTS_RMMOD_CMD)) | |
12858 | bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); | |
12859 | ||
b030ed2f YM |
12860 | /* Close the interface - either directly or implicitly */ |
12861 | if (remove_netdev) { | |
12862 | unregister_netdev(dev); | |
12863 | } else { | |
12864 | rtnl_lock(); | |
6ef5a92c | 12865 | dev_close(dev); |
b030ed2f YM |
12866 | rtnl_unlock(); |
12867 | } | |
a2fbb9ea | 12868 | |
78c3bcc5 AE |
12869 | bnx2x_iov_remove_one(bp); |
12870 | ||
084d6cbb | 12871 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
1ab4434c AE |
12872 | if (IS_PF(bp)) |
12873 | bnx2x_set_power_state(bp, PCI_D0); | |
084d6cbb | 12874 | |
d6214d7a DK |
12875 | /* Disable MSI/MSI-X */ |
12876 | bnx2x_disable_msi(bp); | |
f85582f8 | 12877 | |
084d6cbb | 12878 | /* Power off */ |
1ab4434c AE |
12879 | if (IS_PF(bp)) |
12880 | bnx2x_set_power_state(bp, PCI_D3hot); | |
084d6cbb | 12881 | |
72fd0718 | 12882 | /* Make sure RESET task is not scheduled before continuing */ |
7be08a72 | 12883 | cancel_delayed_work_sync(&bp->sp_rtnl_task); |
290ca2bb | 12884 | |
4513f925 AE |
12885 | /* send message via vfpf channel to release the resources of this vf */ |
12886 | if (IS_VF(bp)) | |
12887 | bnx2x_vfpf_release(bp); | |
72fd0718 | 12888 | |
b030ed2f YM |
12889 | /* Assumes no further PCIe PM changes will occur */ |
12890 | if (system_state == SYSTEM_POWER_OFF) { | |
12891 | pci_wake_from_d3(pdev, bp->wol); | |
12892 | pci_set_power_state(pdev, PCI_D3hot); | |
12893 | } | |
12894 | ||
a2fbb9ea ET |
12895 | if (bp->regview) |
12896 | iounmap(bp->regview); | |
12897 | ||
1ab4434c AE |
12898 | /* for vf doorbells are part of the regview and were unmapped along with |
12899 | * it. FW is only loaded by PF. | |
12900 | */ | |
12901 | if (IS_PF(bp)) { | |
12902 | if (bp->doorbells) | |
12903 | iounmap(bp->doorbells); | |
eb2afd4a | 12904 | |
1ab4434c AE |
12905 | bnx2x_release_firmware(bp); |
12906 | } | |
523224a3 DK |
12907 | bnx2x_free_mem_bp(bp); |
12908 | ||
b030ed2f YM |
12909 | if (remove_netdev) |
12910 | free_netdev(dev); | |
34f80b04 EG |
12911 | |
12912 | if (atomic_read(&pdev->enable_cnt) == 1) | |
12913 | pci_release_regions(pdev); | |
12914 | ||
a2fbb9ea ET |
12915 | pci_disable_device(pdev); |
12916 | pci_set_drvdata(pdev, NULL); | |
12917 | } | |
12918 | ||
b030ed2f YM |
12919 | static void bnx2x_remove_one(struct pci_dev *pdev) |
12920 | { | |
12921 | struct net_device *dev = pci_get_drvdata(pdev); | |
12922 | struct bnx2x *bp; | |
12923 | ||
12924 | if (!dev) { | |
12925 | dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); | |
12926 | return; | |
12927 | } | |
12928 | bp = netdev_priv(dev); | |
12929 | ||
12930 | __bnx2x_remove(pdev, dev, bp, true); | |
12931 | } | |
12932 | ||
f8ef6e44 YG |
12933 | static int bnx2x_eeh_nic_unload(struct bnx2x *bp) |
12934 | { | |
7fa6f340 | 12935 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; |
f8ef6e44 YG |
12936 | |
12937 | bp->rx_mode = BNX2X_RX_MODE_NONE; | |
12938 | ||
55c11941 MS |
12939 | if (CNIC_LOADED(bp)) |
12940 | bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); | |
12941 | ||
619c5cb6 VZ |
12942 | /* Stop Tx */ |
12943 | bnx2x_tx_disable(bp); | |
26614ba5 MS |
12944 | /* Delete all NAPI objects */ |
12945 | bnx2x_del_all_napi(bp); | |
55c11941 MS |
12946 | if (CNIC_LOADED(bp)) |
12947 | bnx2x_del_all_napi_cnic(bp); | |
7fa6f340 | 12948 | netdev_reset_tc(bp->dev); |
f8ef6e44 YG |
12949 | |
12950 | del_timer_sync(&bp->timer); | |
7fa6f340 YM |
12951 | cancel_delayed_work(&bp->sp_task); |
12952 | cancel_delayed_work(&bp->period_task); | |
619c5cb6 | 12953 | |
7fa6f340 YM |
12954 | spin_lock_bh(&bp->stats_lock); |
12955 | bp->stats_state = STATS_STATE_DISABLED; | |
12956 | spin_unlock_bh(&bp->stats_lock); | |
f8ef6e44 | 12957 | |
7fa6f340 | 12958 | bnx2x_save_statistics(bp); |
f8ef6e44 | 12959 | |
619c5cb6 VZ |
12960 | netif_carrier_off(bp->dev); |
12961 | ||
f8ef6e44 YG |
12962 | return 0; |
12963 | } | |
12964 | ||
493adb1f WX |
12965 | /** |
12966 | * bnx2x_io_error_detected - called when PCI error is detected | |
12967 | * @pdev: Pointer to PCI device | |
12968 | * @state: The current pci connection state | |
12969 | * | |
12970 | * This function is called after a PCI bus error affecting | |
12971 | * this device has been detected. | |
12972 | */ | |
12973 | static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, | |
12974 | pci_channel_state_t state) | |
12975 | { | |
12976 | struct net_device *dev = pci_get_drvdata(pdev); | |
12977 | struct bnx2x *bp = netdev_priv(dev); | |
12978 | ||
12979 | rtnl_lock(); | |
12980 | ||
7fa6f340 YM |
12981 | BNX2X_ERR("IO error detected\n"); |
12982 | ||
493adb1f WX |
12983 | netif_device_detach(dev); |
12984 | ||
07ce50e4 DN |
12985 | if (state == pci_channel_io_perm_failure) { |
12986 | rtnl_unlock(); | |
12987 | return PCI_ERS_RESULT_DISCONNECT; | |
12988 | } | |
12989 | ||
493adb1f | 12990 | if (netif_running(dev)) |
f8ef6e44 | 12991 | bnx2x_eeh_nic_unload(bp); |
493adb1f | 12992 | |
7fa6f340 YM |
12993 | bnx2x_prev_path_mark_eeh(bp); |
12994 | ||
493adb1f WX |
12995 | pci_disable_device(pdev); |
12996 | ||
12997 | rtnl_unlock(); | |
12998 | ||
12999 | /* Request a slot reset */ | |
13000 | return PCI_ERS_RESULT_NEED_RESET; | |
13001 | } | |
13002 | ||
13003 | /** | |
13004 | * bnx2x_io_slot_reset - called after the PCI bus has been reset | |
13005 | * @pdev: Pointer to PCI device | |
13006 | * | |
13007 | * Restart the card from scratch, as if from a cold-boot. | |
13008 | */ | |
13009 | static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) | |
13010 | { | |
13011 | struct net_device *dev = pci_get_drvdata(pdev); | |
13012 | struct bnx2x *bp = netdev_priv(dev); | |
7fa6f340 | 13013 | int i; |
493adb1f WX |
13014 | |
13015 | rtnl_lock(); | |
7fa6f340 | 13016 | BNX2X_ERR("IO slot reset initializing...\n"); |
493adb1f WX |
13017 | if (pci_enable_device(pdev)) { |
13018 | dev_err(&pdev->dev, | |
13019 | "Cannot re-enable PCI device after reset\n"); | |
13020 | rtnl_unlock(); | |
13021 | return PCI_ERS_RESULT_DISCONNECT; | |
13022 | } | |
13023 | ||
13024 | pci_set_master(pdev); | |
13025 | pci_restore_state(pdev); | |
70632d0a | 13026 | pci_save_state(pdev); |
493adb1f WX |
13027 | |
13028 | if (netif_running(dev)) | |
13029 | bnx2x_set_power_state(bp, PCI_D0); | |
13030 | ||
7fa6f340 YM |
13031 | if (netif_running(dev)) { |
13032 | BNX2X_ERR("IO slot reset --> driver unload\n"); | |
e68072ef YM |
13033 | |
13034 | /* MCP should have been reset; Need to wait for validity */ | |
13035 | bnx2x_init_shmem(bp); | |
13036 | ||
7fa6f340 YM |
13037 | if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { |
13038 | u32 v; | |
13039 | ||
13040 | v = SHMEM2_RD(bp, | |
13041 | drv_capabilities_flag[BP_FW_MB_IDX(bp)]); | |
13042 | SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], | |
13043 | v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); | |
13044 | } | |
13045 | bnx2x_drain_tx_queues(bp); | |
13046 | bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); | |
13047 | bnx2x_netif_stop(bp, 1); | |
13048 | bnx2x_free_irq(bp); | |
13049 | ||
13050 | /* Report UNLOAD_DONE to MCP */ | |
13051 | bnx2x_send_unload_done(bp, true); | |
13052 | ||
13053 | bp->sp_state = 0; | |
13054 | bp->port.pmf = 0; | |
13055 | ||
13056 | bnx2x_prev_unload(bp); | |
13057 | ||
16a5fd92 | 13058 | /* We should have reseted the engine, so It's fair to |
7fa6f340 YM |
13059 | * assume the FW will no longer write to the bnx2x driver. |
13060 | */ | |
13061 | bnx2x_squeeze_objects(bp); | |
13062 | bnx2x_free_skbs(bp); | |
13063 | for_each_rx_queue(bp, i) | |
13064 | bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); | |
13065 | bnx2x_free_fp_mem(bp); | |
13066 | bnx2x_free_mem(bp); | |
13067 | ||
13068 | bp->state = BNX2X_STATE_CLOSED; | |
13069 | } | |
13070 | ||
493adb1f WX |
13071 | rtnl_unlock(); |
13072 | ||
13073 | return PCI_ERS_RESULT_RECOVERED; | |
13074 | } | |
13075 | ||
13076 | /** | |
13077 | * bnx2x_io_resume - called when traffic can start flowing again | |
13078 | * @pdev: Pointer to PCI device | |
13079 | * | |
13080 | * This callback is called when the error recovery driver tells us that | |
13081 | * its OK to resume normal operation. | |
13082 | */ | |
13083 | static void bnx2x_io_resume(struct pci_dev *pdev) | |
13084 | { | |
13085 | struct net_device *dev = pci_get_drvdata(pdev); | |
13086 | struct bnx2x *bp = netdev_priv(dev); | |
13087 | ||
72fd0718 | 13088 | if (bp->recovery_state != BNX2X_RECOVERY_DONE) { |
51c1a580 | 13089 | netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); |
72fd0718 VZ |
13090 | return; |
13091 | } | |
13092 | ||
493adb1f WX |
13093 | rtnl_lock(); |
13094 | ||
7fa6f340 YM |
13095 | bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & |
13096 | DRV_MSG_SEQ_NUMBER_MASK; | |
13097 | ||
493adb1f | 13098 | if (netif_running(dev)) |
f8ef6e44 | 13099 | bnx2x_nic_load(bp, LOAD_NORMAL); |
493adb1f WX |
13100 | |
13101 | netif_device_attach(dev); | |
13102 | ||
13103 | rtnl_unlock(); | |
13104 | } | |
13105 | ||
3646f0e5 | 13106 | static const struct pci_error_handlers bnx2x_err_handler = { |
493adb1f | 13107 | .error_detected = bnx2x_io_error_detected, |
356e2385 EG |
13108 | .slot_reset = bnx2x_io_slot_reset, |
13109 | .resume = bnx2x_io_resume, | |
493adb1f WX |
13110 | }; |
13111 | ||
b030ed2f YM |
13112 | static void bnx2x_shutdown(struct pci_dev *pdev) |
13113 | { | |
13114 | struct net_device *dev = pci_get_drvdata(pdev); | |
13115 | struct bnx2x *bp; | |
13116 | ||
13117 | if (!dev) | |
13118 | return; | |
13119 | ||
13120 | bp = netdev_priv(dev); | |
13121 | if (!bp) | |
13122 | return; | |
13123 | ||
13124 | rtnl_lock(); | |
13125 | netif_device_detach(dev); | |
13126 | rtnl_unlock(); | |
13127 | ||
13128 | /* Don't remove the netdevice, as there are scenarios which will cause | |
13129 | * the kernel to hang, e.g., when trying to remove bnx2i while the | |
13130 | * rootfs is mounted from SAN. | |
13131 | */ | |
13132 | __bnx2x_remove(pdev, dev, bp, false); | |
13133 | } | |
13134 | ||
a2fbb9ea | 13135 | static struct pci_driver bnx2x_pci_driver = { |
493adb1f WX |
13136 | .name = DRV_MODULE_NAME, |
13137 | .id_table = bnx2x_pci_tbl, | |
13138 | .probe = bnx2x_init_one, | |
0329aba1 | 13139 | .remove = bnx2x_remove_one, |
493adb1f WX |
13140 | .suspend = bnx2x_suspend, |
13141 | .resume = bnx2x_resume, | |
13142 | .err_handler = &bnx2x_err_handler, | |
3c76feff AE |
13143 | #ifdef CONFIG_BNX2X_SRIOV |
13144 | .sriov_configure = bnx2x_sriov_configure, | |
13145 | #endif | |
b030ed2f | 13146 | .shutdown = bnx2x_shutdown, |
a2fbb9ea ET |
13147 | }; |
13148 | ||
13149 | static int __init bnx2x_init(void) | |
13150 | { | |
dd21ca6d SG |
13151 | int ret; |
13152 | ||
7995c64e | 13153 | pr_info("%s", version); |
938cf541 | 13154 | |
1cf167f2 EG |
13155 | bnx2x_wq = create_singlethread_workqueue("bnx2x"); |
13156 | if (bnx2x_wq == NULL) { | |
7995c64e | 13157 | pr_err("Cannot create workqueue\n"); |
1cf167f2 EG |
13158 | return -ENOMEM; |
13159 | } | |
13160 | ||
dd21ca6d SG |
13161 | ret = pci_register_driver(&bnx2x_pci_driver); |
13162 | if (ret) { | |
7995c64e | 13163 | pr_err("Cannot register driver\n"); |
dd21ca6d SG |
13164 | destroy_workqueue(bnx2x_wq); |
13165 | } | |
13166 | return ret; | |
a2fbb9ea ET |
13167 | } |
13168 | ||
13169 | static void __exit bnx2x_cleanup(void) | |
13170 | { | |
452427b0 | 13171 | struct list_head *pos, *q; |
d76a6111 | 13172 | |
a2fbb9ea | 13173 | pci_unregister_driver(&bnx2x_pci_driver); |
1cf167f2 EG |
13174 | |
13175 | destroy_workqueue(bnx2x_wq); | |
452427b0 | 13176 | |
16a5fd92 | 13177 | /* Free globally allocated resources */ |
452427b0 YM |
13178 | list_for_each_safe(pos, q, &bnx2x_prev_list) { |
13179 | struct bnx2x_prev_path_list *tmp = | |
13180 | list_entry(pos, struct bnx2x_prev_path_list, list); | |
13181 | list_del(pos); | |
13182 | kfree(tmp); | |
13183 | } | |
a2fbb9ea ET |
13184 | } |
13185 | ||
3deb8167 YR |
13186 | void bnx2x_notify_link_changed(struct bnx2x *bp) |
13187 | { | |
13188 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); | |
13189 | } | |
13190 | ||
a2fbb9ea ET |
13191 | module_init(bnx2x_init); |
13192 | module_exit(bnx2x_cleanup); | |
13193 | ||
619c5cb6 VZ |
13194 | /** |
13195 | * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). | |
13196 | * | |
13197 | * @bp: driver handle | |
13198 | * @set: set or clear the CAM entry | |
13199 | * | |
16a5fd92 | 13200 | * This function will wait until the ramrod completion returns. |
619c5cb6 VZ |
13201 | * Return 0 if success, -ENODEV if ramrod doesn't return. |
13202 | */ | |
1191cb83 | 13203 | static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) |
619c5cb6 VZ |
13204 | { |
13205 | unsigned long ramrod_flags = 0; | |
13206 | ||
13207 | __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); | |
13208 | return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, | |
13209 | &bp->iscsi_l2_mac_obj, true, | |
13210 | BNX2X_ISCSI_ETH_MAC, &ramrod_flags); | |
13211 | } | |
993ac7b5 MC |
13212 | |
13213 | /* count denotes the number of new completions we have seen */ | |
13214 | static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) | |
13215 | { | |
13216 | struct eth_spe *spe; | |
a052997e | 13217 | int cxt_index, cxt_offset; |
993ac7b5 MC |
13218 | |
13219 | #ifdef BNX2X_STOP_ON_ERROR | |
13220 | if (unlikely(bp->panic)) | |
13221 | return; | |
13222 | #endif | |
13223 | ||
13224 | spin_lock_bh(&bp->spq_lock); | |
c2bff63f | 13225 | BUG_ON(bp->cnic_spq_pending < count); |
993ac7b5 MC |
13226 | bp->cnic_spq_pending -= count; |
13227 | ||
c2bff63f DK |
13228 | for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { |
13229 | u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) | |
13230 | & SPE_HDR_CONN_TYPE) >> | |
13231 | SPE_HDR_CONN_TYPE_SHIFT; | |
619c5cb6 VZ |
13232 | u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) |
13233 | >> SPE_HDR_CMD_ID_SHIFT) & 0xff; | |
c2bff63f DK |
13234 | |
13235 | /* Set validation for iSCSI L2 client before sending SETUP | |
13236 | * ramrod | |
13237 | */ | |
13238 | if (type == ETH_CONNECTION_TYPE) { | |
a052997e | 13239 | if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { |
37ae41a9 | 13240 | cxt_index = BNX2X_ISCSI_ETH_CID(bp) / |
a052997e | 13241 | ILT_PAGE_CIDS; |
37ae41a9 | 13242 | cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - |
a052997e MS |
13243 | (cxt_index * ILT_PAGE_CIDS); |
13244 | bnx2x_set_ctx_validation(bp, | |
13245 | &bp->context[cxt_index]. | |
13246 | vcxt[cxt_offset].eth, | |
37ae41a9 | 13247 | BNX2X_ISCSI_ETH_CID(bp)); |
a052997e | 13248 | } |
c2bff63f DK |
13249 | } |
13250 | ||
619c5cb6 VZ |
13251 | /* |
13252 | * There may be not more than 8 L2, not more than 8 L5 SPEs | |
13253 | * and in the air. We also check that number of outstanding | |
6e30dd4e VZ |
13254 | * COMMON ramrods is not more than the EQ and SPQ can |
13255 | * accommodate. | |
c2bff63f | 13256 | */ |
6e30dd4e VZ |
13257 | if (type == ETH_CONNECTION_TYPE) { |
13258 | if (!atomic_read(&bp->cq_spq_left)) | |
13259 | break; | |
13260 | else | |
13261 | atomic_dec(&bp->cq_spq_left); | |
13262 | } else if (type == NONE_CONNECTION_TYPE) { | |
13263 | if (!atomic_read(&bp->eq_spq_left)) | |
c2bff63f DK |
13264 | break; |
13265 | else | |
6e30dd4e | 13266 | atomic_dec(&bp->eq_spq_left); |
ec6ba945 VZ |
13267 | } else if ((type == ISCSI_CONNECTION_TYPE) || |
13268 | (type == FCOE_CONNECTION_TYPE)) { | |
c2bff63f DK |
13269 | if (bp->cnic_spq_pending >= |
13270 | bp->cnic_eth_dev.max_kwqe_pending) | |
13271 | break; | |
13272 | else | |
13273 | bp->cnic_spq_pending++; | |
13274 | } else { | |
13275 | BNX2X_ERR("Unknown SPE type: %d\n", type); | |
13276 | bnx2x_panic(); | |
993ac7b5 | 13277 | break; |
c2bff63f | 13278 | } |
993ac7b5 MC |
13279 | |
13280 | spe = bnx2x_sp_get_next(bp); | |
13281 | *spe = *bp->cnic_kwq_cons; | |
13282 | ||
51c1a580 | 13283 | DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", |
993ac7b5 MC |
13284 | bp->cnic_spq_pending, bp->cnic_kwq_pending, count); |
13285 | ||
13286 | if (bp->cnic_kwq_cons == bp->cnic_kwq_last) | |
13287 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
13288 | else | |
13289 | bp->cnic_kwq_cons++; | |
13290 | } | |
13291 | bnx2x_sp_prod_update(bp); | |
13292 | spin_unlock_bh(&bp->spq_lock); | |
13293 | } | |
13294 | ||
13295 | static int bnx2x_cnic_sp_queue(struct net_device *dev, | |
13296 | struct kwqe_16 *kwqes[], u32 count) | |
13297 | { | |
13298 | struct bnx2x *bp = netdev_priv(dev); | |
13299 | int i; | |
13300 | ||
13301 | #ifdef BNX2X_STOP_ON_ERROR | |
51c1a580 MS |
13302 | if (unlikely(bp->panic)) { |
13303 | BNX2X_ERR("Can't post to SP queue while panic\n"); | |
993ac7b5 | 13304 | return -EIO; |
51c1a580 | 13305 | } |
993ac7b5 MC |
13306 | #endif |
13307 | ||
95c6c616 AE |
13308 | if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && |
13309 | (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { | |
51c1a580 | 13310 | BNX2X_ERR("Handling parity error recovery. Try again later\n"); |
95c6c616 AE |
13311 | return -EAGAIN; |
13312 | } | |
13313 | ||
993ac7b5 MC |
13314 | spin_lock_bh(&bp->spq_lock); |
13315 | ||
13316 | for (i = 0; i < count; i++) { | |
13317 | struct eth_spe *spe = (struct eth_spe *)kwqes[i]; | |
13318 | ||
13319 | if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) | |
13320 | break; | |
13321 | ||
13322 | *bp->cnic_kwq_prod = *spe; | |
13323 | ||
13324 | bp->cnic_kwq_pending++; | |
13325 | ||
51c1a580 | 13326 | DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", |
993ac7b5 | 13327 | spe->hdr.conn_and_cmd_data, spe->hdr.type, |
523224a3 DK |
13328 | spe->data.update_data_addr.hi, |
13329 | spe->data.update_data_addr.lo, | |
993ac7b5 MC |
13330 | bp->cnic_kwq_pending); |
13331 | ||
13332 | if (bp->cnic_kwq_prod == bp->cnic_kwq_last) | |
13333 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
13334 | else | |
13335 | bp->cnic_kwq_prod++; | |
13336 | } | |
13337 | ||
13338 | spin_unlock_bh(&bp->spq_lock); | |
13339 | ||
13340 | if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) | |
13341 | bnx2x_cnic_sp_post(bp, 0); | |
13342 | ||
13343 | return i; | |
13344 | } | |
13345 | ||
13346 | static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
13347 | { | |
13348 | struct cnic_ops *c_ops; | |
13349 | int rc = 0; | |
13350 | ||
13351 | mutex_lock(&bp->cnic_mutex); | |
13707f9e ED |
13352 | c_ops = rcu_dereference_protected(bp->cnic_ops, |
13353 | lockdep_is_held(&bp->cnic_mutex)); | |
993ac7b5 MC |
13354 | if (c_ops) |
13355 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
13356 | mutex_unlock(&bp->cnic_mutex); | |
13357 | ||
13358 | return rc; | |
13359 | } | |
13360 | ||
13361 | static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) | |
13362 | { | |
13363 | struct cnic_ops *c_ops; | |
13364 | int rc = 0; | |
13365 | ||
13366 | rcu_read_lock(); | |
13367 | c_ops = rcu_dereference(bp->cnic_ops); | |
13368 | if (c_ops) | |
13369 | rc = c_ops->cnic_ctl(bp->cnic_data, ctl); | |
13370 | rcu_read_unlock(); | |
13371 | ||
13372 | return rc; | |
13373 | } | |
13374 | ||
13375 | /* | |
13376 | * for commands that have no data | |
13377 | */ | |
9f6c9258 | 13378 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) |
993ac7b5 MC |
13379 | { |
13380 | struct cnic_ctl_info ctl = {0}; | |
13381 | ||
13382 | ctl.cmd = cmd; | |
13383 | ||
13384 | return bnx2x_cnic_ctl_send(bp, &ctl); | |
13385 | } | |
13386 | ||
619c5cb6 | 13387 | static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) |
993ac7b5 | 13388 | { |
619c5cb6 | 13389 | struct cnic_ctl_info ctl = {0}; |
993ac7b5 MC |
13390 | |
13391 | /* first we tell CNIC and only then we count this as a completion */ | |
13392 | ctl.cmd = CNIC_CTL_COMPLETION_CMD; | |
13393 | ctl.data.comp.cid = cid; | |
619c5cb6 | 13394 | ctl.data.comp.error = err; |
993ac7b5 MC |
13395 | |
13396 | bnx2x_cnic_ctl_send_bh(bp, &ctl); | |
c2bff63f | 13397 | bnx2x_cnic_sp_post(bp, 0); |
993ac7b5 MC |
13398 | } |
13399 | ||
619c5cb6 VZ |
13400 | /* Called with netif_addr_lock_bh() taken. |
13401 | * Sets an rx_mode config for an iSCSI ETH client. | |
13402 | * Doesn't block. | |
13403 | * Completion should be checked outside. | |
13404 | */ | |
13405 | static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) | |
13406 | { | |
13407 | unsigned long accept_flags = 0, ramrod_flags = 0; | |
13408 | u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
13409 | int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; | |
13410 | ||
13411 | if (start) { | |
13412 | /* Start accepting on iSCSI L2 ring. Accept all multicasts | |
13413 | * because it's the only way for UIO Queue to accept | |
13414 | * multicasts (in non-promiscuous mode only one Queue per | |
13415 | * function will receive multicast packets (leading in our | |
13416 | * case). | |
13417 | */ | |
13418 | __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); | |
13419 | __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); | |
13420 | __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); | |
13421 | __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); | |
13422 | ||
13423 | /* Clear STOP_PENDING bit if START is requested */ | |
13424 | clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); | |
13425 | ||
13426 | sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; | |
13427 | } else | |
13428 | /* Clear START_PENDING bit if STOP is requested */ | |
13429 | clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); | |
13430 | ||
13431 | if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) | |
13432 | set_bit(sched_state, &bp->sp_state); | |
13433 | else { | |
13434 | __set_bit(RAMROD_RX, &ramrod_flags); | |
13435 | bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, | |
13436 | ramrod_flags); | |
13437 | } | |
13438 | } | |
13439 | ||
993ac7b5 MC |
13440 | static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) |
13441 | { | |
13442 | struct bnx2x *bp = netdev_priv(dev); | |
13443 | int rc = 0; | |
13444 | ||
13445 | switch (ctl->cmd) { | |
13446 | case DRV_CTL_CTXTBL_WR_CMD: { | |
13447 | u32 index = ctl->data.io.offset; | |
13448 | dma_addr_t addr = ctl->data.io.dma_addr; | |
13449 | ||
13450 | bnx2x_ilt_wr(bp, index, addr); | |
13451 | break; | |
13452 | } | |
13453 | ||
c2bff63f DK |
13454 | case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { |
13455 | int count = ctl->data.credit.credit_count; | |
993ac7b5 MC |
13456 | |
13457 | bnx2x_cnic_sp_post(bp, count); | |
13458 | break; | |
13459 | } | |
13460 | ||
13461 | /* rtnl_lock is held. */ | |
13462 | case DRV_CTL_START_L2_CMD: { | |
619c5cb6 VZ |
13463 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; |
13464 | unsigned long sp_bits = 0; | |
13465 | ||
13466 | /* Configure the iSCSI classification object */ | |
13467 | bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, | |
13468 | cp->iscsi_l2_client_id, | |
13469 | cp->iscsi_l2_cid, BP_FUNC(bp), | |
13470 | bnx2x_sp(bp, mac_rdata), | |
13471 | bnx2x_sp_mapping(bp, mac_rdata), | |
13472 | BNX2X_FILTER_MAC_PENDING, | |
13473 | &bp->sp_state, BNX2X_OBJ_TYPE_RX, | |
13474 | &bp->macs_pool); | |
ec6ba945 | 13475 | |
523224a3 | 13476 | /* Set iSCSI MAC address */ |
619c5cb6 VZ |
13477 | rc = bnx2x_set_iscsi_eth_mac_addr(bp); |
13478 | if (rc) | |
13479 | break; | |
523224a3 DK |
13480 | |
13481 | mmiowb(); | |
13482 | barrier(); | |
13483 | ||
619c5cb6 VZ |
13484 | /* Start accepting on iSCSI L2 ring */ |
13485 | ||
13486 | netif_addr_lock_bh(dev); | |
13487 | bnx2x_set_iscsi_eth_rx_mode(bp, true); | |
13488 | netif_addr_unlock_bh(dev); | |
13489 | ||
13490 | /* bits to wait on */ | |
13491 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
13492 | __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); | |
13493 | ||
13494 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
13495 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 | 13496 | |
993ac7b5 MC |
13497 | break; |
13498 | } | |
13499 | ||
13500 | /* rtnl_lock is held. */ | |
13501 | case DRV_CTL_STOP_L2_CMD: { | |
619c5cb6 | 13502 | unsigned long sp_bits = 0; |
993ac7b5 | 13503 | |
523224a3 | 13504 | /* Stop accepting on iSCSI L2 ring */ |
619c5cb6 VZ |
13505 | netif_addr_lock_bh(dev); |
13506 | bnx2x_set_iscsi_eth_rx_mode(bp, false); | |
13507 | netif_addr_unlock_bh(dev); | |
13508 | ||
13509 | /* bits to wait on */ | |
13510 | __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); | |
13511 | __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); | |
13512 | ||
13513 | if (!bnx2x_wait_sp_comp(bp, sp_bits)) | |
13514 | BNX2X_ERR("rx_mode completion timed out!\n"); | |
523224a3 DK |
13515 | |
13516 | mmiowb(); | |
13517 | barrier(); | |
13518 | ||
13519 | /* Unset iSCSI L2 MAC */ | |
619c5cb6 VZ |
13520 | rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, |
13521 | BNX2X_ISCSI_ETH_MAC, true); | |
993ac7b5 MC |
13522 | break; |
13523 | } | |
c2bff63f DK |
13524 | case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { |
13525 | int count = ctl->data.credit.credit_count; | |
13526 | ||
13527 | smp_mb__before_atomic_inc(); | |
6e30dd4e | 13528 | atomic_add(count, &bp->cq_spq_left); |
c2bff63f DK |
13529 | smp_mb__after_atomic_inc(); |
13530 | break; | |
13531 | } | |
1d187b34 | 13532 | case DRV_CTL_ULP_REGISTER_CMD: { |
2e499d3c | 13533 | int ulp_type = ctl->data.register_data.ulp_type; |
1d187b34 BW |
13534 | |
13535 | if (CHIP_IS_E3(bp)) { | |
13536 | int idx = BP_FW_MB_IDX(bp); | |
2e499d3c BW |
13537 | u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); |
13538 | int path = BP_PATH(bp); | |
13539 | int port = BP_PORT(bp); | |
13540 | int i; | |
13541 | u32 scratch_offset; | |
13542 | u32 *host_addr; | |
1d187b34 | 13543 | |
2e499d3c | 13544 | /* first write capability to shmem2 */ |
1d187b34 BW |
13545 | if (ulp_type == CNIC_ULP_ISCSI) |
13546 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
13547 | else if (ulp_type == CNIC_ULP_FCOE) | |
13548 | cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
13549 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
2e499d3c BW |
13550 | |
13551 | if ((ulp_type != CNIC_ULP_FCOE) || | |
13552 | (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || | |
13553 | (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) | |
13554 | break; | |
13555 | ||
13556 | /* if reached here - should write fcoe capabilities */ | |
13557 | scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); | |
13558 | if (!scratch_offset) | |
13559 | break; | |
13560 | scratch_offset += offsetof(struct glob_ncsi_oem_data, | |
13561 | fcoe_features[path][port]); | |
13562 | host_addr = (u32 *) &(ctl->data.register_data. | |
13563 | fcoe_features); | |
13564 | for (i = 0; i < sizeof(struct fcoe_capabilities); | |
13565 | i += 4) | |
13566 | REG_WR(bp, scratch_offset + i, | |
13567 | *(host_addr + i/4)); | |
1d187b34 BW |
13568 | } |
13569 | break; | |
13570 | } | |
2e499d3c | 13571 | |
1d187b34 BW |
13572 | case DRV_CTL_ULP_UNREGISTER_CMD: { |
13573 | int ulp_type = ctl->data.ulp_type; | |
13574 | ||
13575 | if (CHIP_IS_E3(bp)) { | |
13576 | int idx = BP_FW_MB_IDX(bp); | |
13577 | u32 cap; | |
13578 | ||
13579 | cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); | |
13580 | if (ulp_type == CNIC_ULP_ISCSI) | |
13581 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; | |
13582 | else if (ulp_type == CNIC_ULP_FCOE) | |
13583 | cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; | |
13584 | SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); | |
13585 | } | |
13586 | break; | |
13587 | } | |
993ac7b5 MC |
13588 | |
13589 | default: | |
13590 | BNX2X_ERR("unknown command %x\n", ctl->cmd); | |
13591 | rc = -EINVAL; | |
13592 | } | |
13593 | ||
13594 | return rc; | |
13595 | } | |
13596 | ||
9f6c9258 | 13597 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) |
993ac7b5 MC |
13598 | { |
13599 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13600 | ||
13601 | if (bp->flags & USING_MSIX_FLAG) { | |
13602 | cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; | |
13603 | cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; | |
13604 | cp->irq_arr[0].vector = bp->msix_table[1].vector; | |
13605 | } else { | |
13606 | cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; | |
13607 | cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; | |
13608 | } | |
619c5cb6 | 13609 | if (!CHIP_IS_E1x(bp)) |
f2e0899f DK |
13610 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; |
13611 | else | |
13612 | cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; | |
13613 | ||
619c5cb6 VZ |
13614 | cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); |
13615 | cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); | |
993ac7b5 MC |
13616 | cp->irq_arr[1].status_blk = bp->def_status_blk; |
13617 | cp->irq_arr[1].status_blk_num = DEF_SB_ID; | |
523224a3 | 13618 | cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; |
993ac7b5 MC |
13619 | |
13620 | cp->num_irq = 2; | |
13621 | } | |
13622 | ||
37ae41a9 MS |
13623 | void bnx2x_setup_cnic_info(struct bnx2x *bp) |
13624 | { | |
13625 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13626 | ||
37ae41a9 MS |
13627 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
13628 | bnx2x_cid_ilt_lines(bp); | |
13629 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; | |
13630 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); | |
13631 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); | |
13632 | ||
f78afb35 MC |
13633 | DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n", |
13634 | BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, | |
13635 | cp->iscsi_l2_cid); | |
13636 | ||
37ae41a9 MS |
13637 | if (NO_ISCSI_OOO(bp)) |
13638 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
13639 | } | |
13640 | ||
993ac7b5 MC |
13641 | static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, |
13642 | void *data) | |
13643 | { | |
13644 | struct bnx2x *bp = netdev_priv(dev); | |
13645 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
55c11941 MS |
13646 | int rc; |
13647 | ||
13648 | DP(NETIF_MSG_IFUP, "Register_cnic called\n"); | |
993ac7b5 | 13649 | |
51c1a580 MS |
13650 | if (ops == NULL) { |
13651 | BNX2X_ERR("NULL ops received\n"); | |
993ac7b5 | 13652 | return -EINVAL; |
51c1a580 | 13653 | } |
993ac7b5 | 13654 | |
55c11941 MS |
13655 | if (!CNIC_SUPPORT(bp)) { |
13656 | BNX2X_ERR("Can't register CNIC when not supported\n"); | |
13657 | return -EOPNOTSUPP; | |
13658 | } | |
13659 | ||
13660 | if (!CNIC_LOADED(bp)) { | |
13661 | rc = bnx2x_load_cnic(bp); | |
13662 | if (rc) { | |
13663 | BNX2X_ERR("CNIC-related load failed\n"); | |
13664 | return rc; | |
13665 | } | |
55c11941 MS |
13666 | } |
13667 | ||
13668 | bp->cnic_enabled = true; | |
13669 | ||
993ac7b5 MC |
13670 | bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); |
13671 | if (!bp->cnic_kwq) | |
13672 | return -ENOMEM; | |
13673 | ||
13674 | bp->cnic_kwq_cons = bp->cnic_kwq; | |
13675 | bp->cnic_kwq_prod = bp->cnic_kwq; | |
13676 | bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; | |
13677 | ||
13678 | bp->cnic_spq_pending = 0; | |
13679 | bp->cnic_kwq_pending = 0; | |
13680 | ||
13681 | bp->cnic_data = data; | |
13682 | ||
13683 | cp->num_irq = 0; | |
619c5cb6 | 13684 | cp->drv_state |= CNIC_DRV_STATE_REGD; |
523224a3 | 13685 | cp->iro_arr = bp->iro_arr; |
993ac7b5 | 13686 | |
993ac7b5 | 13687 | bnx2x_setup_cnic_irq_info(bp); |
c2bff63f | 13688 | |
993ac7b5 MC |
13689 | rcu_assign_pointer(bp->cnic_ops, ops); |
13690 | ||
13691 | return 0; | |
13692 | } | |
13693 | ||
13694 | static int bnx2x_unregister_cnic(struct net_device *dev) | |
13695 | { | |
13696 | struct bnx2x *bp = netdev_priv(dev); | |
13697 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13698 | ||
13699 | mutex_lock(&bp->cnic_mutex); | |
993ac7b5 | 13700 | cp->drv_state = 0; |
2cfa5a04 | 13701 | RCU_INIT_POINTER(bp->cnic_ops, NULL); |
993ac7b5 MC |
13702 | mutex_unlock(&bp->cnic_mutex); |
13703 | synchronize_rcu(); | |
fea75645 | 13704 | bp->cnic_enabled = false; |
993ac7b5 MC |
13705 | kfree(bp->cnic_kwq); |
13706 | bp->cnic_kwq = NULL; | |
13707 | ||
13708 | return 0; | |
13709 | } | |
13710 | ||
13711 | struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) | |
13712 | { | |
13713 | struct bnx2x *bp = netdev_priv(dev); | |
13714 | struct cnic_eth_dev *cp = &bp->cnic_eth_dev; | |
13715 | ||
2ba45142 VZ |
13716 | /* If both iSCSI and FCoE are disabled - return NULL in |
13717 | * order to indicate CNIC that it should not try to work | |
13718 | * with this device. | |
13719 | */ | |
13720 | if (NO_ISCSI(bp) && NO_FCOE(bp)) | |
13721 | return NULL; | |
13722 | ||
993ac7b5 MC |
13723 | cp->drv_owner = THIS_MODULE; |
13724 | cp->chip_id = CHIP_ID(bp); | |
13725 | cp->pdev = bp->pdev; | |
13726 | cp->io_base = bp->regview; | |
13727 | cp->io_base2 = bp->doorbells; | |
13728 | cp->max_kwqe_pending = 8; | |
523224a3 | 13729 | cp->ctx_blk_size = CDU_ILT_PAGE_SZ; |
c2bff63f DK |
13730 | cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + |
13731 | bnx2x_cid_ilt_lines(bp); | |
993ac7b5 | 13732 | cp->ctx_tbl_len = CNIC_ILT_LINES; |
c2bff63f | 13733 | cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; |
993ac7b5 MC |
13734 | cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; |
13735 | cp->drv_ctl = bnx2x_drv_ctl; | |
13736 | cp->drv_register_cnic = bnx2x_register_cnic; | |
13737 | cp->drv_unregister_cnic = bnx2x_unregister_cnic; | |
37ae41a9 | 13738 | cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); |
619c5cb6 VZ |
13739 | cp->iscsi_l2_client_id = |
13740 | bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); | |
37ae41a9 | 13741 | cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); |
c2bff63f | 13742 | |
2ba45142 VZ |
13743 | if (NO_ISCSI_OOO(bp)) |
13744 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; | |
13745 | ||
13746 | if (NO_ISCSI(bp)) | |
13747 | cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; | |
13748 | ||
13749 | if (NO_FCOE(bp)) | |
13750 | cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; | |
13751 | ||
51c1a580 MS |
13752 | BNX2X_DEV_INFO( |
13753 | "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", | |
c2bff63f DK |
13754 | cp->ctx_blk_size, |
13755 | cp->ctx_tbl_offset, | |
13756 | cp->ctx_tbl_len, | |
13757 | cp->starting_cid); | |
993ac7b5 MC |
13758 | return cp; |
13759 | } | |
993ac7b5 | 13760 | |
6411280a | 13761 | u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) |
9b176b6b | 13762 | { |
6411280a AE |
13763 | struct bnx2x *bp = fp->bp; |
13764 | u32 offset = BAR_USTRORM_INTMEM; | |
abc5a021 | 13765 | |
6411280a AE |
13766 | if (IS_VF(bp)) |
13767 | return bnx2x_vf_ustorm_prods_offset(bp, fp); | |
13768 | else if (!CHIP_IS_E1x(bp)) | |
13769 | offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
13770 | else | |
13771 | offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
8d9ac297 | 13772 | |
6411280a | 13773 | return offset; |
8d9ac297 | 13774 | } |
381ac16b | 13775 | |
6411280a AE |
13776 | /* called only on E1H or E2. |
13777 | * When pretending to be PF, the pretend value is the function number 0...7 | |
13778 | * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID | |
13779 | * combination | |
13780 | */ | |
13781 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) | |
381ac16b | 13782 | { |
6411280a | 13783 | u32 pretend_reg; |
381ac16b | 13784 | |
23826850 | 13785 | if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) |
6411280a | 13786 | return -1; |
381ac16b | 13787 | |
6411280a AE |
13788 | /* get my own pretend register */ |
13789 | pretend_reg = bnx2x_get_pretend_reg(bp); | |
13790 | REG_WR(bp, pretend_reg, pretend_func_val); | |
13791 | REG_RD(bp, pretend_reg); | |
381ac16b AE |
13792 | return 0; |
13793 | } |