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bnx2x: support classification config query
[thirdparty/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
34f80b04 1/* bnx2x_main.c: Broadcom Everest network driver.
a2fbb9ea 2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 13 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 14 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 15 *
16 */
17
f1deab50
JP		 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
a2fbb9ea
ET		 20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/device.h> /* for dev_info() */
24#include <linux/timer.h>
25#include <linux/errno.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
a2fbb9ea
ET		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/dma-mapping.h>
35#include <linux/bitops.h>
36#include <linux/irq.h>
37#include <linux/delay.h>
38#include <asm/byteorder.h>
39#include <linux/time.h>
40#include <linux/ethtool.h>
41#include <linux/mii.h>
01789349 42#include <linux/if.h>
0c6671b0 43#include <linux/if_vlan.h>
a2fbb9ea 44#include <net/ip.h>
619c5cb6 45#include <net/ipv6.h>
a2fbb9ea
ET		 46#include <net/tcp.h>
47#include <net/checksum.h>
34f80b04 48#include <net/ip6_checksum.h>
a2fbb9ea
ET		 49#include <linux/workqueue.h>
50#include <linux/crc32.h>
34f80b04 51#include <linux/crc32c.h>
a2fbb9ea
ET		 52#include <linux/prefetch.h>
53#include <linux/zlib.h>
a2fbb9ea 54#include <linux/io.h>
45229b42 55#include <linux/stringify.h>
7ab24bfd 56#include <linux/vmalloc.h>
a2fbb9ea 57
a2fbb9ea
ET		 58#include "bnx2x.h"
59#include "bnx2x_init.h"
94a78b79 60#include "bnx2x_init_ops.h"
9f6c9258 61#include "bnx2x_cmn.h"
e4901dde 62#include "bnx2x_dcb.h"
042181f5 63#include "bnx2x_sp.h"
a2fbb9ea 64
94a78b79
VZ		 65#include <linux/firmware.h>
66#include "bnx2x_fw_file_hdr.h"
67/* FW files */
45229b42
BH		 68#define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 73#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 75#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 76
34f80b04
EG		 77/* Time in jiffies before concluding the transmitter is hung */
78#define TX_TIMEOUT (5*HZ)
a2fbb9ea 79
53a10565 80static char version[] __devinitdata =
619c5cb6 81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
83
24e3fcef 84MODULE_AUTHOR("Eliezer Tamir");
f2e0899f 85MODULE_DESCRIPTION("Broadcom NetXtreme II "
619c5cb6
VZ		 86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
a2fbb9ea
ET		 89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 91MODULE_FIRMWARE(FW_FILE_NAME_E1);
92MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 93MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 94
555f6c78
EG		 95static int multi_mode = 1;
96module_param(multi_mode, int, 0);
ca00392c
EG		 97MODULE_PARM_DESC(multi_mode, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
99
d6214d7a 100int num_queues;
54b9ddaa
VZ		 101module_param(num_queues, int, 0);
102MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
555f6c78 104
19680c48 105static int disable_tpa;
19680c48 106module_param(disable_tpa, int, 0);
9898f86d 107MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 108
9ee3d37b
DK		 109#define INT_MODE_INTx 1
110#define INT_MODE_MSI 2
8badd27a
EG		 111static int int_mode;
112module_param(int_mode, int, 0);
619c5cb6 113MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 114 "(1 INT#x; 2 MSI)");
8badd27a 115
a18f5128
EG		 116static int dropless_fc;
117module_param(dropless_fc, int, 0);
118MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
119
9898f86d 120static int poll;
a2fbb9ea 121module_param(poll, int, 0);
9898f86d 122MODULE_PARM_DESC(poll, " Use polling (for debug)");
8d5726c4
EG		 123
124static int mrrs = -1;
125module_param(mrrs, int, 0);
126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
127
9898f86d 128static int debug;
a2fbb9ea 129module_param(debug, int, 0);
9898f86d
EG		 130MODULE_PARM_DESC(debug, " Default debug msglevel");
131
a2fbb9ea 132
619c5cb6
VZ		 133
134struct workqueue_struct *bnx2x_wq;
ec6ba945 135
a2fbb9ea
ET		 136enum bnx2x_board_type {
137 BCM57710 = 0,
619c5cb6
VZ		 138 BCM57711,
139 BCM57711E,
140 BCM57712,
141 BCM57712_MF,
142 BCM57800,
143 BCM57800_MF,
144 BCM57810,
145 BCM57810_MF,
146 BCM57840,
147 BCM57840_MF
a2fbb9ea
ET		 148};
149
34f80b04 150/* indexed by board_type, above */
53a10565 151static struct {
a2fbb9ea
ET		 152 char *name;
153} board_info[] __devinitdata = {
619c5cb6
VZ		 154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
165 "Ethernet Multi Function"}
a2fbb9ea
ET		 166};
167
619c5cb6
VZ		 168#ifndef PCI_DEVICE_ID_NX2_57710
169#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
170#endif
171#ifndef PCI_DEVICE_ID_NX2_57711
172#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
173#endif
174#ifndef PCI_DEVICE_ID_NX2_57711E
175#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
176#endif
177#ifndef PCI_DEVICE_ID_NX2_57712
178#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
179#endif
180#ifndef PCI_DEVICE_ID_NX2_57712_MF
181#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
182#endif
183#ifndef PCI_DEVICE_ID_NX2_57800
184#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
185#endif
186#ifndef PCI_DEVICE_ID_NX2_57800_MF
187#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
188#endif
189#ifndef PCI_DEVICE_ID_NX2_57810
190#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
191#endif
192#ifndef PCI_DEVICE_ID_NX2_57810_MF
193#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
194#endif
195#ifndef PCI_DEVICE_ID_NX2_57840
196#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
197#endif
198#ifndef PCI_DEVICE_ID_NX2_57840_MF
199#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
200#endif
a3aa1884 201static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
e4ed7113
EG		 202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6
VZ		 206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
a2fbb9ea
ET		 213 { 0 }
214};
215
216MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
217
218/****************************************************************************
219* General service functions
220****************************************************************************/
221
619c5cb6
VZ		 222static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
223 u32 addr, dma_addr_t mapping)
224{
225 REG_WR(bp, addr, U64_LO(mapping));
226 REG_WR(bp, addr + 4, U64_HI(mapping));
227}
228
229static inline void storm_memset_spq_addr(struct bnx2x *bp,
230 dma_addr_t mapping, u16 abs_fid)
231{
232 u32 addr = XSEM_REG_FAST_MEMORY +
233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
234
235 __storm_memset_dma_mapping(bp, addr, mapping);
236}
237
238static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
239 u16 pf_id)
523224a3 240{
619c5cb6
VZ		 241 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
242 pf_id);
243 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
244 pf_id);
245 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
246 pf_id);
247 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
248 pf_id);
523224a3
DK		 249}
250
619c5cb6
VZ		 251static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
252 u8 enable)
253{
254 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
255 enable);
256 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
257 enable);
258 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
259 enable);
260 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
261 enable);
262}
523224a3
DK		 263
264static inline void storm_memset_eq_data(struct bnx2x *bp,
265 struct event_ring_data *eq_data,
266 u16 pfid)
267{
268 size_t size = sizeof(struct event_ring_data);
269
270 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
271
272 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
273}
274
275static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
276 u16 pfid)
277{
278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
279 REG_WR16(bp, addr, eq_prod);
280}
281
a2fbb9ea
ET		 282/* used only at init
283 * locking is done by mcp
284 */
8d96286a 285static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 286{
287 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
288 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
289 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
290 PCICFG_VENDOR_ID_OFFSET);
291}
292
a2fbb9ea
ET		 293static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
294{
295 u32 val;
296
297 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
298 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
299 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
300 PCICFG_VENDOR_ID_OFFSET);
301
302 return val;
303}
a2fbb9ea 304
f2e0899f
DK		 305#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
306#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
307#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
308#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
309#define DMAE_DP_DST_NONE "dst_addr [none]"
310
8d96286a 311static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
312 int msglvl)
f2e0899f
DK		 313{
314 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
315
316 switch (dmae->opcode & DMAE_COMMAND_DST) {
317 case DMAE_CMD_DST_PCI:
318 if (src_type == DMAE_CMD_SRC_PCI)
319 DP(msglvl, "DMAE: opcode 0x%08x\n"
320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
321 "comp_addr [%x:%08x], comp_val 0x%08x\n",
322 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
323 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
324 dmae->comp_addr_hi, dmae->comp_addr_lo,
325 dmae->comp_val);
326 else
327 DP(msglvl, "DMAE: opcode 0x%08x\n"
328 "src [%08x], len [%d*4], dst [%x:%08x]\n"
329 "comp_addr [%x:%08x], comp_val 0x%08x\n",
330 dmae->opcode, dmae->src_addr_lo >> 2,
331 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
332 dmae->comp_addr_hi, dmae->comp_addr_lo,
333 dmae->comp_val);
334 break;
335 case DMAE_CMD_DST_GRC:
336 if (src_type == DMAE_CMD_SRC_PCI)
337 DP(msglvl, "DMAE: opcode 0x%08x\n"
338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
339 "comp_addr [%x:%08x], comp_val 0x%08x\n",
340 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
341 dmae->len, dmae->dst_addr_lo >> 2,
342 dmae->comp_addr_hi, dmae->comp_addr_lo,
343 dmae->comp_val);
344 else
345 DP(msglvl, "DMAE: opcode 0x%08x\n"
346 "src [%08x], len [%d*4], dst [%08x]\n"
347 "comp_addr [%x:%08x], comp_val 0x%08x\n",
348 dmae->opcode, dmae->src_addr_lo >> 2,
349 dmae->len, dmae->dst_addr_lo >> 2,
350 dmae->comp_addr_hi, dmae->comp_addr_lo,
351 dmae->comp_val);
352 break;
353 default:
354 if (src_type == DMAE_CMD_SRC_PCI)
355 DP(msglvl, "DMAE: opcode 0x%08x\n"
f1deab50
JP		 356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
357 "comp_addr [%x:%08x] comp_val 0x%08x\n",
f2e0899f
DK		 358 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
359 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
360 dmae->comp_val);
361 else
362 DP(msglvl, "DMAE: opcode 0x%08x\n"
f1deab50
JP		 363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
364 "comp_addr [%x:%08x] comp_val 0x%08x\n",
f2e0899f
DK		 365 dmae->opcode, dmae->src_addr_lo >> 2,
366 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
367 dmae->comp_val);
368 break;
369 }
370
371}
372
a2fbb9ea 373/* copy command into DMAE command memory and set DMAE command go */
6c719d00 374void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 375{
376 u32 cmd_offset;
377 int i;
378
379 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
380 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
381 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
382
ad8d3948
EG		 383 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
384 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 385 }
386 REG_WR(bp, dmae_reg_go_c[idx], 1);
387}
388
f2e0899f 389u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 390{
f2e0899f
DK		 391 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
392 DMAE_CMD_C_ENABLE);
393}
ad8d3948 394
f2e0899f
DK		 395u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
396{
397 return opcode & ~DMAE_CMD_SRC_RESET;
398}
ad8d3948 399
f2e0899f
DK		 400u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
401 bool with_comp, u8 comp_type)
402{
403 u32 opcode = 0;
404
405 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
406 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 407
f2e0899f
DK		 408 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
409
410 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 411 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
412 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 413 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 414
a2fbb9ea 415#ifdef __BIG_ENDIAN
f2e0899f 416 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 417#else
f2e0899f 418 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 419#endif
f2e0899f
DK		 420 if (with_comp)
421 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
422 return opcode;
423}
424
8d96286a 425static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
426 struct dmae_command *dmae,
427 u8 src_type, u8 dst_type)
f2e0899f
DK		 428{
429 memset(dmae, 0, sizeof(struct dmae_command));
430
431 /* set the opcode */
432 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
433 true, DMAE_COMP_PCI);
434
435 /* fill in the completion parameters */
436 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
438 dmae->comp_val = DMAE_COMP_VAL;
439}
440
441/* issue a dmae command over the init-channel and wailt for completion */
8d96286a 442static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
443 struct dmae_command *dmae)
f2e0899f
DK		 444{
445 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
5e374b5a 446 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 447 int rc = 0;
448
449 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
a2fbb9ea
ET		 450 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
451 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
a2fbb9ea 452
619c5cb6
VZ		 453 /*
454 * Lock the dmae channel. Disable BHs to prevent a dead-lock
455 * as long as this code is called both from syscall context and
456 * from ndo_set_rx_mode() flow that may be called from BH.
457 */
6e30dd4e 458 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 459
f2e0899f 460 /* reset completion */
a2fbb9ea
ET		 461 *wb_comp = 0;
462
f2e0899f
DK		 463 /* post the command on the channel used for initializations */
464 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 465
f2e0899f 466 /* wait for completion */
a2fbb9ea 467 udelay(5);
f2e0899f 468 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948
EG		 469 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
470
ad8d3948 471 if (!cnt) {
c3eefaf6 472 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 473 rc = DMAE_TIMEOUT;
474 goto unlock;
a2fbb9ea 475 }
ad8d3948 476 cnt--;
f2e0899f 477 udelay(50);
a2fbb9ea 478 }
f2e0899f
DK		 479 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
480 BNX2X_ERR("DMAE PCI error!\n");
481 rc = DMAE_PCI_ERROR;
482 }
483
484 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
485 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
486 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
ad8d3948 487
f2e0899f 488unlock:
6e30dd4e 489 spin_unlock_bh(&bp->dmae_lock);
f2e0899f
DK		 490 return rc;
491}
492
493void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
494 u32 len32)
495{
496 struct dmae_command dmae;
497
498 if (!bp->dmae_ready) {
499 u32 *data = bnx2x_sp(bp, wb_data[0]);
500
501 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
502 " using indirect\n", dst_addr, len32);
503 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
504 return;
505 }
506
507 /* set opcode and fixed command fields */
508 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
509
510 /* fill in addresses and len */
511 dmae.src_addr_lo = U64_LO(dma_addr);
512 dmae.src_addr_hi = U64_HI(dma_addr);
513 dmae.dst_addr_lo = dst_addr >> 2;
514 dmae.dst_addr_hi = 0;
515 dmae.len = len32;
516
517 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
518
519 /* issue the command and wait for completion */
520 bnx2x_issue_dmae_with_comp(bp, &dmae);
a2fbb9ea
ET		 521}
522
c18487ee 523void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 524{
5ff7b6d4 525 struct dmae_command dmae;
ad8d3948
EG		 526
527 if (!bp->dmae_ready) {
528 u32 *data = bnx2x_sp(bp, wb_data[0]);
529 int i;
530
531 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
532 " using indirect\n", src_addr, len32);
533 for (i = 0; i < len32; i++)
534 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
535 return;
536 }
537
f2e0899f
DK		 538 /* set opcode and fixed command fields */
539 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 540
f2e0899f 541 /* fill in addresses and len */
5ff7b6d4
EG		 542 dmae.src_addr_lo = src_addr >> 2;
543 dmae.src_addr_hi = 0;
544 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
545 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
546 dmae.len = len32;
ad8d3948 547
f2e0899f 548 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
ad8d3948 549
f2e0899f
DK		 550 /* issue the command and wait for completion */
551 bnx2x_issue_dmae_with_comp(bp, &dmae);
ad8d3948
EG		 552}
553
8d96286a 554static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
555 u32 addr, u32 len)
573f2035 556{
02e3c6cb 557 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 558 int offset = 0;
559
02e3c6cb 560 while (len > dmae_wr_max) {
573f2035 561 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 562 addr + offset, dmae_wr_max);
563 offset += dmae_wr_max * 4;
564 len -= dmae_wr_max;
573f2035
EG		 565 }
566
567 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
568}
569
ad8d3948
EG		 570/* used only for slowpath so not inlined */
571static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
572{
573 u32 wb_write[2];
574
575 wb_write[0] = val_hi;
576 wb_write[1] = val_lo;
577 REG_WR_DMAE(bp, reg, wb_write, 2);
a2fbb9ea 578}
a2fbb9ea 579
ad8d3948
EG		 580#ifdef USE_WB_RD
581static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
582{
583 u32 wb_data[2];
584
585 REG_RD_DMAE(bp, reg, wb_data, 2);
586
587 return HILO_U64(wb_data[0], wb_data[1]);
588}
589#endif
590
a2fbb9ea
ET		 591static int bnx2x_mc_assert(struct bnx2x *bp)
592{
a2fbb9ea 593 char last_idx;
34f80b04
EG		 594 int i, rc = 0;
595 u32 row0, row1, row2, row3;
596
597 /* XSTORM */
598 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
599 XSTORM_ASSERT_LIST_INDEX_OFFSET);
600 if (last_idx)
601 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
602
603 /* print the asserts */
604 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
605
606 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
607 XSTORM_ASSERT_LIST_OFFSET(i));
608 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
609 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
610 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
611 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
612 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
613 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
614
615 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
616 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
617 " 0x%08x 0x%08x 0x%08x\n",
618 i, row3, row2, row1, row0);
619 rc++;
620 } else {
621 break;
622 }
623 }
624
625 /* TSTORM */
626 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
627 TSTORM_ASSERT_LIST_INDEX_OFFSET);
628 if (last_idx)
629 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
630
631 /* print the asserts */
632 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
633
634 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
635 TSTORM_ASSERT_LIST_OFFSET(i));
636 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
637 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
638 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
640 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
641 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
642
643 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
644 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
645 " 0x%08x 0x%08x 0x%08x\n",
646 i, row3, row2, row1, row0);
647 rc++;
648 } else {
649 break;
650 }
651 }
652
653 /* CSTORM */
654 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
655 CSTORM_ASSERT_LIST_INDEX_OFFSET);
656 if (last_idx)
657 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
658
659 /* print the asserts */
660 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
661
662 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
663 CSTORM_ASSERT_LIST_OFFSET(i));
664 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
665 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
666 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
667 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
668 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
669 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
670
671 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
672 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
673 " 0x%08x 0x%08x 0x%08x\n",
674 i, row3, row2, row1, row0);
675 rc++;
676 } else {
677 break;
678 }
679 }
680
681 /* USTORM */
682 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
683 USTORM_ASSERT_LIST_INDEX_OFFSET);
684 if (last_idx)
685 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686
687 /* print the asserts */
688 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689
690 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
691 USTORM_ASSERT_LIST_OFFSET(i));
692 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i) + 4);
694 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_OFFSET(i) + 8);
696 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
697 USTORM_ASSERT_LIST_OFFSET(i) + 12);
698
699 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
700 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
701 " 0x%08x 0x%08x 0x%08x\n",
702 i, row3, row2, row1, row0);
703 rc++;
704 } else {
705 break;
a2fbb9ea
ET		 706 }
707 }
34f80b04 708
a2fbb9ea
ET		 709 return rc;
710}
c14423fe 711
7a25cc73 712void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 713{
7a25cc73 714 u32 addr, val;
a2fbb9ea 715 u32 mark, offset;
4781bfad 716 __be32 data[9];
a2fbb9ea 717 int word;
f2e0899f 718 u32 trace_shmem_base;
2145a920
VZ		 719 if (BP_NOMCP(bp)) {
720 BNX2X_ERR("NO MCP - can not dump\n");
721 return;
722 }
7a25cc73
DK		 723 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
724 (bp->common.bc_ver & 0xff0000) >> 16,
725 (bp->common.bc_ver & 0xff00) >> 8,
726 (bp->common.bc_ver & 0xff));
727
728 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
729 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
730 printk("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 731
f2e0899f
DK		 732 if (BP_PATH(bp) == 0)
733 trace_shmem_base = bp->common.shmem_base;
734 else
735 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
736 addr = trace_shmem_base - 0x0800 + 4;
cdaa7cb8 737 mark = REG_RD(bp, addr);
f2e0899f
DK		 738 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
739 + ((mark + 0x3) & ~0x3) - 0x08000000;
7a25cc73 740 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 741
7a25cc73 742 printk("%s", lvl);
f2e0899f 743 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 744 for (word = 0; word < 8; word++)
cdaa7cb8 745 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 746 data[8] = 0x0;
7995c64e 747 pr_cont("%s", (char *)data);
a2fbb9ea 748 }
cdaa7cb8 749 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 750 for (word = 0; word < 8; word++)
cdaa7cb8 751 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 752 data[8] = 0x0;
7995c64e 753 pr_cont("%s", (char *)data);
a2fbb9ea 754 }
7a25cc73
DK		 755 printk("%s" "end of fw dump\n", lvl);
756}
757
758static inline void bnx2x_fw_dump(struct bnx2x *bp)
759{
760 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 761}
762
6c719d00 763void bnx2x_panic_dump(struct bnx2x *bp)
a2fbb9ea
ET		 764{
765 int i;
523224a3
DK		 766 u16 j;
767 struct hc_sp_status_block_data sp_sb_data;
768 int func = BP_FUNC(bp);
769#ifdef BNX2X_STOP_ON_ERROR
770 u16 start = 0, end = 0;
6383c0b3 771 u8 cos;
523224a3 772#endif
a2fbb9ea 773
66e855f3
YG		 774 bp->stats_state = STATS_STATE_DISABLED;
775 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
776
a2fbb9ea
ET		 777 BNX2X_ERR("begin crash dump -----------------\n");
778
8440d2b6
EG		 779 /* Indices */
780 /* Common */
523224a3 781 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
619c5cb6
VZ		 782 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
783 bp->def_idx, bp->def_att_idx, bp->attn_state,
784 bp->spq_prod_idx, bp->stats_counter);
523224a3
DK		 785 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
786 bp->def_status_blk->atten_status_block.attn_bits,
787 bp->def_status_blk->atten_status_block.attn_bits_ack,
788 bp->def_status_blk->atten_status_block.status_block_id,
789 bp->def_status_blk->atten_status_block.attn_bits_index);
790 BNX2X_ERR(" def (");
791 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
792 pr_cont("0x%x%s",
f1deab50
JP		 793 bp->def_status_blk->sp_sb.index_values[i],
794 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
523224a3
DK		 795
796 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
797 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
798 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
799 i*sizeof(u32));
800
f1deab50 801 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
523224a3
DK		 802 sp_sb_data.igu_sb_id,
803 sp_sb_data.igu_seg_id,
804 sp_sb_data.p_func.pf_id,
805 sp_sb_data.p_func.vnic_id,
806 sp_sb_data.p_func.vf_id,
619c5cb6
VZ		 807 sp_sb_data.p_func.vf_valid,
808 sp_sb_data.state);
523224a3 809
8440d2b6 810
ec6ba945 811 for_each_eth_queue(bp, i) {
a2fbb9ea 812 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 813 int loop;
f2e0899f 814 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 815 struct hc_status_block_data_e1x sb_data_e1x;
816 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 817 CHIP_IS_E1x(bp) ?
818 sb_data_e1x.common.state_machine :
819 sb_data_e2.common.state_machine;
523224a3 820 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 821 CHIP_IS_E1x(bp) ?
822 sb_data_e1x.index_data :
823 sb_data_e2.index_data;
6383c0b3 824 u8 data_size, cos;
523224a3 825 u32 *sb_data_p;
6383c0b3 826 struct bnx2x_fp_txdata txdata;
523224a3
DK		 827
828 /* Rx */
cdaa7cb8 829 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
523224a3 830 " rx_comp_prod(0x%x)"
cdaa7cb8 831 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 832 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 833 fp->rx_comp_prod,
66e855f3 834 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
cdaa7cb8 835 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
523224a3 836 " fp_hc_idx(0x%x)\n",
8440d2b6 837 fp->rx_sge_prod, fp->last_max_sge,
523224a3 838 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 839
523224a3 840 /* Tx */
6383c0b3
AE		 841 for_each_cos_in_tx_queue(fp, cos)
842 {
843 txdata = fp->txdata[cos];
844 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
845 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
846 " *tx_cons_sb(0x%x)\n",
847 i, txdata.tx_pkt_prod,
848 txdata.tx_pkt_cons, txdata.tx_bd_prod,
849 txdata.tx_bd_cons,
850 le16_to_cpu(*txdata.tx_cons_sb));
851 }
523224a3 852
619c5cb6
VZ		 853 loop = CHIP_IS_E1x(bp) ?
854 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 855
856 /* host sb data */
857
ec6ba945
VZ		 858#ifdef BCM_CNIC
859 if (IS_FCOE_FP(fp))
860 continue;
861#endif
523224a3
DK		 862 BNX2X_ERR(" run indexes (");
863 for (j = 0; j < HC_SB_MAX_SM; j++)
864 pr_cont("0x%x%s",
865 fp->sb_running_index[j],
866 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
867
868 BNX2X_ERR(" indexes (");
869 for (j = 0; j < loop; j++)
870 pr_cont("0x%x%s",
871 fp->sb_index_values[j],
872 (j == loop - 1) ? ")" : " ");
873 /* fw sb data */
619c5cb6
VZ		 874 data_size = CHIP_IS_E1x(bp) ?
875 sizeof(struct hc_status_block_data_e1x) :
876 sizeof(struct hc_status_block_data_e2);
523224a3 877 data_size /= sizeof(u32);
619c5cb6
VZ		 878 sb_data_p = CHIP_IS_E1x(bp) ?
879 (u32 *)&sb_data_e1x :
880 (u32 *)&sb_data_e2;
523224a3
DK		 881 /* copy sb data in here */
882 for (j = 0; j < data_size; j++)
883 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
884 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
885 j * sizeof(u32));
886
619c5cb6
VZ		 887 if (!CHIP_IS_E1x(bp)) {
888 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
889 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
890 "state(0x%x)\n",
f2e0899f
DK		 891 sb_data_e2.common.p_func.pf_id,
892 sb_data_e2.common.p_func.vf_id,
893 sb_data_e2.common.p_func.vf_valid,
894 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 895 sb_data_e2.common.same_igu_sb_1b,
896 sb_data_e2.common.state);
f2e0899f 897 } else {
619c5cb6
VZ		 898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
900 "state(0x%x)\n",
f2e0899f
DK		 901 sb_data_e1x.common.p_func.pf_id,
902 sb_data_e1x.common.p_func.vf_id,
903 sb_data_e1x.common.p_func.vf_valid,
904 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 905 sb_data_e1x.common.same_igu_sb_1b,
906 sb_data_e1x.common.state);
f2e0899f 907 }
523224a3
DK		 908
909 /* SB_SMs data */
910 for (j = 0; j < HC_SB_MAX_SM; j++) {
911 pr_cont("SM[%d] __flags (0x%x) "
912 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
913 "time_to_expire (0x%x) "
914 "timer_value(0x%x)\n", j,
915 hc_sm_p[j].__flags,
916 hc_sm_p[j].igu_sb_id,
917 hc_sm_p[j].igu_seg_id,
918 hc_sm_p[j].time_to_expire,
919 hc_sm_p[j].timer_value);
920 }
921
922 /* Indecies data */
923 for (j = 0; j < loop; j++) {
924 pr_cont("INDEX[%d] flags (0x%x) "
925 "timeout (0x%x)\n", j,
926 hc_index_p[j].flags,
927 hc_index_p[j].timeout);
928 }
8440d2b6 929 }
a2fbb9ea 930
523224a3 931#ifdef BNX2X_STOP_ON_ERROR
8440d2b6
EG		 932 /* Rings */
933 /* Rx */
ec6ba945 934 for_each_rx_queue(bp, i) {
8440d2b6 935 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea
ET		 936
937 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
938 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 939 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 940 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
941 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
942
c3eefaf6
EG		 943 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
944 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
a2fbb9ea
ET		 945 }
946
3196a88a
EG		 947 start = RX_SGE(fp->rx_sge_prod);
948 end = RX_SGE(fp->last_max_sge);
8440d2b6 949 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 950 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
951 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
952
c3eefaf6
EG		 953 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
954 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 955 }
956
a2fbb9ea
ET		 957 start = RCQ_BD(fp->rx_comp_cons - 10);
958 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 959 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 960 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
961
c3eefaf6
EG		 962 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
963 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 964 }
965 }
966
8440d2b6 967 /* Tx */
ec6ba945 968 for_each_tx_queue(bp, i) {
8440d2b6 969 struct bnx2x_fastpath *fp = &bp->fp[i];
6383c0b3
AE		 970 for_each_cos_in_tx_queue(fp, cos) {
971 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
972
973 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
974 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
975 for (j = start; j != end; j = TX_BD(j + 1)) {
976 struct sw_tx_bd *sw_bd =
977 &txdata->tx_buf_ring[j];
978
979 BNX2X_ERR("fp%d: txdata %d, "
980 "packet[%x]=[%p,%x]\n",
981 i, cos, j, sw_bd->skb,
982 sw_bd->first_bd);
983 }
8440d2b6 984
6383c0b3
AE		 985 start = TX_BD(txdata->tx_bd_cons - 10);
986 end = TX_BD(txdata->tx_bd_cons + 254);
987 for (j = start; j != end; j = TX_BD(j + 1)) {
988 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 989
6383c0b3
AE		 990 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
991 "[%x:%x:%x:%x]\n",
992 i, cos, j, tx_bd[0], tx_bd[1],
993 tx_bd[2], tx_bd[3]);
994 }
8440d2b6
EG		 995 }
996 }
523224a3 997#endif
34f80b04 998 bnx2x_fw_dump(bp);
a2fbb9ea
ET		 999 bnx2x_mc_assert(bp);
1000 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1001}
1002
619c5cb6
VZ		 1003/*
1004 * FLR Support for E2
1005 *
1006 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1007 * initialization.
1008 */
1009#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1010#define FLR_WAIT_INTERAVAL 50 /* usec */
1011#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1012
1013struct pbf_pN_buf_regs {
1014 int pN;
1015 u32 init_crd;
1016 u32 crd;
1017 u32 crd_freed;
1018};
1019
1020struct pbf_pN_cmd_regs {
1021 int pN;
1022 u32 lines_occup;
1023 u32 lines_freed;
1024};
1025
1026static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1027 struct pbf_pN_buf_regs *regs,
1028 u32 poll_count)
1029{
1030 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1031 u32 cur_cnt = poll_count;
1032
1033 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1034 crd = crd_start = REG_RD(bp, regs->crd);
1035 init_crd = REG_RD(bp, regs->init_crd);
1036
1037 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1038 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1039 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1040
1041 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1042 (init_crd - crd_start))) {
1043 if (cur_cnt--) {
1044 udelay(FLR_WAIT_INTERAVAL);
1045 crd = REG_RD(bp, regs->crd);
1046 crd_freed = REG_RD(bp, regs->crd_freed);
1047 } else {
1048 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1049 regs->pN);
1050 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1051 regs->pN, crd);
1052 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1053 regs->pN, crd_freed);
1054 break;
1055 }
1056 }
1057 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1058 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1059}
1060
1061static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1062 struct pbf_pN_cmd_regs *regs,
1063 u32 poll_count)
1064{
1065 u32 occup, to_free, freed, freed_start;
1066 u32 cur_cnt = poll_count;
1067
1068 occup = to_free = REG_RD(bp, regs->lines_occup);
1069 freed = freed_start = REG_RD(bp, regs->lines_freed);
1070
1071 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1072 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1073
1074 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1075 if (cur_cnt--) {
1076 udelay(FLR_WAIT_INTERAVAL);
1077 occup = REG_RD(bp, regs->lines_occup);
1078 freed = REG_RD(bp, regs->lines_freed);
1079 } else {
1080 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1081 regs->pN);
1082 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1083 regs->pN, occup);
1084 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1085 regs->pN, freed);
1086 break;
1087 }
1088 }
1089 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1090 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1091}
1092
1093static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1094 u32 expected, u32 poll_count)
1095{
1096 u32 cur_cnt = poll_count;
1097 u32 val;
1098
1099 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1100 udelay(FLR_WAIT_INTERAVAL);
1101
1102 return val;
1103}
1104
1105static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1106 char *msg, u32 poll_cnt)
1107{
1108 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1109 if (val != 0) {
1110 BNX2X_ERR("%s usage count=%d\n", msg, val);
1111 return 1;
1112 }
1113 return 0;
1114}
1115
1116static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1117{
1118 /* adjust polling timeout */
1119 if (CHIP_REV_IS_EMUL(bp))
1120 return FLR_POLL_CNT * 2000;
1121
1122 if (CHIP_REV_IS_FPGA(bp))
1123 return FLR_POLL_CNT * 120;
1124
1125 return FLR_POLL_CNT;
1126}
1127
1128static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1129{
1130 struct pbf_pN_cmd_regs cmd_regs[] = {
1131 {0, (CHIP_IS_E3B0(bp)) ?
1132 PBF_REG_TQ_OCCUPANCY_Q0 :
1133 PBF_REG_P0_TQ_OCCUPANCY,
1134 (CHIP_IS_E3B0(bp)) ?
1135 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1136 PBF_REG_P0_TQ_LINES_FREED_CNT},
1137 {1, (CHIP_IS_E3B0(bp)) ?
1138 PBF_REG_TQ_OCCUPANCY_Q1 :
1139 PBF_REG_P1_TQ_OCCUPANCY,
1140 (CHIP_IS_E3B0(bp)) ?
1141 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1142 PBF_REG_P1_TQ_LINES_FREED_CNT},
1143 {4, (CHIP_IS_E3B0(bp)) ?
1144 PBF_REG_TQ_OCCUPANCY_LB_Q :
1145 PBF_REG_P4_TQ_OCCUPANCY,
1146 (CHIP_IS_E3B0(bp)) ?
1147 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1148 PBF_REG_P4_TQ_LINES_FREED_CNT}
1149 };
1150
1151 struct pbf_pN_buf_regs buf_regs[] = {
1152 {0, (CHIP_IS_E3B0(bp)) ?
1153 PBF_REG_INIT_CRD_Q0 :
1154 PBF_REG_P0_INIT_CRD ,
1155 (CHIP_IS_E3B0(bp)) ?
1156 PBF_REG_CREDIT_Q0 :
1157 PBF_REG_P0_CREDIT,
1158 (CHIP_IS_E3B0(bp)) ?
1159 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1160 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1161 {1, (CHIP_IS_E3B0(bp)) ?
1162 PBF_REG_INIT_CRD_Q1 :
1163 PBF_REG_P1_INIT_CRD,
1164 (CHIP_IS_E3B0(bp)) ?
1165 PBF_REG_CREDIT_Q1 :
1166 PBF_REG_P1_CREDIT,
1167 (CHIP_IS_E3B0(bp)) ?
1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1169 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1170 {4, (CHIP_IS_E3B0(bp)) ?
1171 PBF_REG_INIT_CRD_LB_Q :
1172 PBF_REG_P4_INIT_CRD,
1173 (CHIP_IS_E3B0(bp)) ?
1174 PBF_REG_CREDIT_LB_Q :
1175 PBF_REG_P4_CREDIT,
1176 (CHIP_IS_E3B0(bp)) ?
1177 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1178 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1179 };
1180
1181 int i;
1182
1183 /* Verify the command queues are flushed P0, P1, P4 */
1184 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1185 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1186
1187
1188 /* Verify the transmission buffers are flushed P0, P1, P4 */
1189 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1190 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1191}
1192
1193#define OP_GEN_PARAM(param) \
1194 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1195
1196#define OP_GEN_TYPE(type) \
1197 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1198
1199#define OP_GEN_AGG_VECT(index) \
1200 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1201
1202
1203static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1204 u32 poll_cnt)
1205{
1206 struct sdm_op_gen op_gen = {0};
1207
1208 u32 comp_addr = BAR_CSTRORM_INTMEM +
1209 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1210 int ret = 0;
1211
1212 if (REG_RD(bp, comp_addr)) {
1213 BNX2X_ERR("Cleanup complete is not 0\n");
1214 return 1;
1215 }
1216
1217 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1218 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1219 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1220 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1221
1222 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1223 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1224
1225 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1226 BNX2X_ERR("FW final cleanup did not succeed\n");
1227 ret = 1;
1228 }
1229 /* Zero completion for nxt FLR */
1230 REG_WR(bp, comp_addr, 0);
1231
1232 return ret;
1233}
1234
1235static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1236{
1237 int pos;
1238 u16 status;
1239
77c98e6a 1240 pos = pci_pcie_cap(dev);
619c5cb6
VZ		 1241 if (!pos)
1242 return false;
1243
1244 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1245 return status & PCI_EXP_DEVSTA_TRPND;
1246}
1247
1248/* PF FLR specific routines
1249*/
1250static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1251{
1252
1253 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 CFC_REG_NUM_LCIDS_INSIDE_PF,
1256 "CFC PF usage counter timed out",
1257 poll_cnt))
1258 return 1;
1259
1260
1261 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1262 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1263 DORQ_REG_PF_USAGE_CNT,
1264 "DQ PF usage counter timed out",
1265 poll_cnt))
1266 return 1;
1267
1268 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1269 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1270 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1271 "QM PF usage counter timed out",
1272 poll_cnt))
1273 return 1;
1274
1275 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1276 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1277 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1278 "Timers VNIC usage counter timed out",
1279 poll_cnt))
1280 return 1;
1281 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1282 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1283 "Timers NUM_SCANS usage counter timed out",
1284 poll_cnt))
1285 return 1;
1286
1287 /* Wait DMAE PF usage counter to zero */
1288 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1289 dmae_reg_go_c[INIT_DMAE_C(bp)],
1290 "DMAE dommand register timed out",
1291 poll_cnt))
1292 return 1;
1293
1294 return 0;
1295}
1296
1297static void bnx2x_hw_enable_status(struct bnx2x *bp)
1298{
1299 u32 val;
1300
1301 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1302 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1303
1304 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1305 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1306
1307 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1308 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1309
1310 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1311 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1312
1313 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1314 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1315
1316 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1317 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1318
1319 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1320 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1321
1322 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1323 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1324 val);
1325}
1326
1327static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1328{
1329 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1330
1331 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1332
1333 /* Re-enable PF target read access */
1334 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1335
1336 /* Poll HW usage counters */
1337 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1338 return -EBUSY;
1339
1340 /* Zero the igu 'trailing edge' and 'leading edge' */
1341
1342 /* Send the FW cleanup command */
1343 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1344 return -EBUSY;
1345
1346 /* ATC cleanup */
1347
1348 /* Verify TX hw is flushed */
1349 bnx2x_tx_hw_flushed(bp, poll_cnt);
1350
1351 /* Wait 100ms (not adjusted according to platform) */
1352 msleep(100);
1353
1354 /* Verify no pending pci transactions */
1355 if (bnx2x_is_pcie_pending(bp->pdev))
1356 BNX2X_ERR("PCIE Transactions still pending\n");
1357
1358 /* Debug */
1359 bnx2x_hw_enable_status(bp);
1360
1361 /*
1362 * Master enable - Due to WB DMAE writes performed before this
1363 * register is re-initialized as part of the regular function init
1364 */
1365 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1366
1367 return 0;
1368}
1369
f2e0899f 1370static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1371{
34f80b04 1372 int port = BP_PORT(bp);
a2fbb9ea
ET		 1373 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1374 u32 val = REG_RD(bp, addr);
1375 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1376 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
a2fbb9ea
ET		 1377
1378 if (msix) {
8badd27a
EG		 1379 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1380 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1381 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1382 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
8badd27a
EG		 1383 } else if (msi) {
1384 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1385 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1387 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1388 } else {
1389 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1391 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1393
a0fd065c
DK		 1394 if (!CHIP_IS_E1(bp)) {
1395 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1396 val, port, addr);
615f8fd9 1397
a0fd065c 1398 REG_WR(bp, addr, val);
615f8fd9 1399
a0fd065c
DK		 1400 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1401 }
a2fbb9ea
ET		 1402 }
1403
a0fd065c
DK		 1404 if (CHIP_IS_E1(bp))
1405 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1406
8badd27a
EG		 1407 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1408 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1409
1410 REG_WR(bp, addr, val);
37dbbf32
EG		 1411 /*
1412 * Ensure that HC_CONFIG is written before leading/trailing edge config
1413 */
1414 mmiowb();
1415 barrier();
34f80b04 1416
f2e0899f 1417 if (!CHIP_IS_E1(bp)) {
34f80b04 1418 /* init leading/trailing edge */
fb3bff17 1419 if (IS_MF(bp)) {
3395a033 1420 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1421 if (bp->port.pmf)
4acac6a5
EG		 1422 /* enable nig and gpio3 attention */
1423 val |= 0x1100;
34f80b04
EG		 1424 } else
1425 val = 0xffff;
1426
1427 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1428 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1429 }
37dbbf32
EG		 1430
1431 /* Make sure that interrupts are indeed enabled from here on */
1432 mmiowb();
a2fbb9ea
ET		 1433}
1434
f2e0899f
DK		 1435static void bnx2x_igu_int_enable(struct bnx2x *bp)
1436{
1437 u32 val;
1438 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1439 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1440
1441 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1442
1443 if (msix) {
1444 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1445 IGU_PF_CONF_SINGLE_ISR_EN);
1446 val |= (IGU_PF_CONF_FUNC_EN |
1447 IGU_PF_CONF_MSI_MSIX_EN |
1448 IGU_PF_CONF_ATTN_BIT_EN);
1449 } else if (msi) {
1450 val &= ~IGU_PF_CONF_INT_LINE_EN;
1451 val |= (IGU_PF_CONF_FUNC_EN |
1452 IGU_PF_CONF_MSI_MSIX_EN |
1453 IGU_PF_CONF_ATTN_BIT_EN |
1454 IGU_PF_CONF_SINGLE_ISR_EN);
1455 } else {
1456 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1457 val |= (IGU_PF_CONF_FUNC_EN |
1458 IGU_PF_CONF_INT_LINE_EN |
1459 IGU_PF_CONF_ATTN_BIT_EN |
1460 IGU_PF_CONF_SINGLE_ISR_EN);
1461 }
1462
1463 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1464 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1465
1466 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1467
1468 barrier();
1469
1470 /* init leading/trailing edge */
1471 if (IS_MF(bp)) {
3395a033 1472 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1473 if (bp->port.pmf)
1474 /* enable nig and gpio3 attention */
1475 val |= 0x1100;
1476 } else
1477 val = 0xffff;
1478
1479 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1480 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1481
1482 /* Make sure that interrupts are indeed enabled from here on */
1483 mmiowb();
1484}
1485
1486void bnx2x_int_enable(struct bnx2x *bp)
1487{
1488 if (bp->common.int_block == INT_BLOCK_HC)
1489 bnx2x_hc_int_enable(bp);
1490 else
1491 bnx2x_igu_int_enable(bp);
1492}
1493
1494static void bnx2x_hc_int_disable(struct bnx2x *bp)
a2fbb9ea 1495{
34f80b04 1496 int port = BP_PORT(bp);
a2fbb9ea
ET		 1497 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1498 u32 val = REG_RD(bp, addr);
1499
a0fd065c
DK		 1500 /*
1501 * in E1 we must use only PCI configuration space to disable
1502 * MSI/MSIX capablility
1503 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1504 */
1505 if (CHIP_IS_E1(bp)) {
1506 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1507 * Use mask register to prevent from HC sending interrupts
1508 * after we exit the function
1509 */
1510 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1511
1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1513 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1514 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1515 } else
1516 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1517 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1518 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1519 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1520
1521 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1522 val, port, addr);
1523
8badd27a
EG		 1524 /* flush all outstanding writes */
1525 mmiowb();
1526
a2fbb9ea
ET		 1527 REG_WR(bp, addr, val);
1528 if (REG_RD(bp, addr) != val)
1529 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1530}
1531
f2e0899f
DK		 1532static void bnx2x_igu_int_disable(struct bnx2x *bp)
1533{
1534 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1535
1536 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1537 IGU_PF_CONF_INT_LINE_EN |
1538 IGU_PF_CONF_ATTN_BIT_EN);
1539
1540 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1541
1542 /* flush all outstanding writes */
1543 mmiowb();
1544
1545 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1546 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1547 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1548}
1549
6383c0b3 1550void bnx2x_int_disable(struct bnx2x *bp)
f2e0899f
DK		 1551{
1552 if (bp->common.int_block == INT_BLOCK_HC)
1553 bnx2x_hc_int_disable(bp);
1554 else
1555 bnx2x_igu_int_disable(bp);
1556}
1557
9f6c9258 1558void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1559{
a2fbb9ea 1560 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1561 int i, offset;
a2fbb9ea 1562
f8ef6e44
YG		 1563 if (disable_hw)
1564 /* prevent the HW from sending interrupts */
1565 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1566
1567 /* make sure all ISRs are done */
1568 if (msix) {
8badd27a
EG		 1569 synchronize_irq(bp->msix_table[0].vector);
1570 offset = 1;
37b091ba
MC		 1571#ifdef BCM_CNIC
1572 offset++;
1573#endif
ec6ba945 1574 for_each_eth_queue(bp, i)
754a2f52 1575 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1576 } else
1577 synchronize_irq(bp->pdev->irq);
1578
1579 /* make sure sp_task is not running */
1cf167f2 1580 cancel_delayed_work(&bp->sp_task);
3deb8167 1581 cancel_delayed_work(&bp->period_task);
1cf167f2 1582 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1583}
1584
34f80b04 1585/* fast path */
a2fbb9ea
ET		 1586
1587/*
34f80b04 1588 * General service functions
a2fbb9ea
ET		 1589 */
1590
72fd0718
VZ		 1591/* Return true if succeeded to acquire the lock */
1592static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1593{
1594 u32 lock_status;
1595 u32 resource_bit = (1 << resource);
1596 int func = BP_FUNC(bp);
1597 u32 hw_lock_control_reg;
1598
1599 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1600
1601 /* Validating that the resource is within range */
1602 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1603 DP(NETIF_MSG_HW,
1604 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1605 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1606 return false;
72fd0718
VZ		 1607 }
1608
1609 if (func <= 5)
1610 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1611 else
1612 hw_lock_control_reg =
1613 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1614
1615 /* Try to acquire the lock */
1616 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1617 lock_status = REG_RD(bp, hw_lock_control_reg);
1618 if (lock_status & resource_bit)
1619 return true;
1620
1621 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1622 return false;
1623}
1624
c9ee9206
VZ		 1625/**
1626 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1627 *
1628 * @bp: driver handle
1629 *
1630 * Returns the recovery leader resource id according to the engine this function
1631 * belongs to. Currently only only 2 engines is supported.
1632 */
1633static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1634{
1635 if (BP_PATH(bp))
1636 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1637 else
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1639}
1640
1641/**
1642 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1643 *
1644 * @bp: driver handle
1645 *
1646 * Tries to aquire a leader lock for cuurent engine.
1647 */
1648static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1649{
1650 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1651}
1652
993ac7b5 1653#ifdef BCM_CNIC
619c5cb6 1654static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
993ac7b5 1655#endif
3196a88a 1656
619c5cb6 1657void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1658{
1659 struct bnx2x *bp = fp->bp;
1660 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1661 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6
VZ		 1662 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1663 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
a2fbb9ea 1664
34f80b04 1665 DP(BNX2X_MSG_SP,
a2fbb9ea 1666 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1667 fp->index, cid, command, bp->state,
34f80b04 1668 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1669
619c5cb6
VZ		 1670 switch (command) {
1671 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1672 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1673 drv_cmd = BNX2X_Q_CMD_UPDATE;
1674 break;
d6cae238 1675
619c5cb6 1676 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1677 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1678 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1679 break;
1680
6383c0b3
AE		 1681 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1682 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1683 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1684 break;
1685
619c5cb6 1686 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1687 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1688 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1689 break;
1690
619c5cb6 1691 case (RAMROD_CMD_ID_ETH_TERMINATE):
d6cae238 1692 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
619c5cb6 1693 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1694 break;
1695
619c5cb6 1696 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1697 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1698 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1699 break;
619c5cb6
VZ		 1700
1701 default:
1702 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1703 command, fp->index);
1704 return;
523224a3 1705 }
3196a88a 1706
619c5cb6
VZ		 1707 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1708 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1709 /* q_obj->complete_cmd() failure means that this was
1710 * an unexpected completion.
1711 *
1712 * In this case we don't want to increase the bp->spq_left
1713 * because apparently we haven't sent this command the first
1714 * place.
1715 */
1716#ifdef BNX2X_STOP_ON_ERROR
1717 bnx2x_panic();
1718#else
1719 return;
1720#endif
1721
8fe23fbd 1722 smp_mb__before_atomic_inc();
6e30dd4e 1723 atomic_inc(&bp->cq_spq_left);
619c5cb6
VZ		 1724 /* push the change in bp->spq_left and towards the memory */
1725 smp_mb__after_atomic_inc();
49d66772 1726
d6cae238
VZ		 1727 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1728
523224a3 1729 return;
a2fbb9ea
ET		 1730}
1731
619c5cb6
VZ		 1732void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1733 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1734{
1735 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1736
1737 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1738 start);
1739}
1740
9f6c9258 1741irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1742{
555f6c78 1743 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1744 u16 status = bnx2x_ack_int(bp);
34f80b04 1745 u16 mask;
ca00392c 1746 int i;
6383c0b3 1747 u8 cos;
a2fbb9ea 1748
34f80b04 1749 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1750 if (unlikely(status == 0)) {
1751 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1752 return IRQ_NONE;
1753 }
f5372251 1754 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1755
3196a88a
EG		 1756#ifdef BNX2X_STOP_ON_ERROR
1757 if (unlikely(bp->panic))
1758 return IRQ_HANDLED;
1759#endif
1760
ec6ba945 1761 for_each_eth_queue(bp, i) {
ca00392c 1762 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1763
6383c0b3 1764 mask = 0x2 << (fp->index + CNIC_PRESENT);
ca00392c 1765 if (status & mask) {
619c5cb6 1766 /* Handle Rx or Tx according to SB id */
54b9ddaa 1767 prefetch(fp->rx_cons_sb);
6383c0b3
AE		 1768 for_each_cos_in_tx_queue(fp, cos)
1769 prefetch(fp->txdata[cos].tx_cons_sb);
523224a3 1770 prefetch(&fp->sb_running_index[SM_RX_ID]);
54b9ddaa 1771 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1772 status &= ~mask;
1773 }
a2fbb9ea
ET		 1774 }
1775
993ac7b5 1776#ifdef BCM_CNIC
523224a3 1777 mask = 0x2;
993ac7b5
MC		 1778 if (status & (mask | 0x1)) {
1779 struct cnic_ops *c_ops = NULL;
1780
619c5cb6
VZ		 1781 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1782 rcu_read_lock();
1783 c_ops = rcu_dereference(bp->cnic_ops);
1784 if (c_ops)
1785 c_ops->cnic_handler(bp->cnic_data, NULL);
1786 rcu_read_unlock();
1787 }
993ac7b5
MC		 1788
1789 status &= ~mask;
1790 }
1791#endif
a2fbb9ea 1792
34f80b04 1793 if (unlikely(status & 0x1)) {
1cf167f2 1794 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 1795
1796 status &= ~0x1;
1797 if (!status)
1798 return IRQ_HANDLED;
1799 }
1800
cdaa7cb8
VZ		 1801 if (unlikely(status))
1802 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1803 status);
a2fbb9ea 1804
c18487ee 1805 return IRQ_HANDLED;
a2fbb9ea
ET		 1806}
1807
c18487ee
YR		 1808/* Link */
1809
1810/*
1811 * General service functions
1812 */
a2fbb9ea 1813
9f6c9258 1814int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1815{
1816 u32 lock_status;
1817 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1818 int func = BP_FUNC(bp);
1819 u32 hw_lock_control_reg;
c18487ee 1820 int cnt;
a2fbb9ea 1821
c18487ee
YR		 1822 /* Validating that the resource is within range */
1823 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1824 DP(NETIF_MSG_HW,
1825 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1826 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1827 return -EINVAL;
1828 }
a2fbb9ea 1829
4a37fb66
YG		 1830 if (func <= 5) {
1831 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1832 } else {
1833 hw_lock_control_reg =
1834 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1835 }
1836
c18487ee 1837 /* Validating that the resource is not already taken */
4a37fb66 1838 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1839 if (lock_status & resource_bit) {
1840 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1841 lock_status, resource_bit);
1842 return -EEXIST;
1843 }
a2fbb9ea 1844
46230476
EG		 1845 /* Try for 5 second every 5ms */
1846 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 1847 /* Try to acquire the lock */
4a37fb66
YG		 1848 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1849 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1850 if (lock_status & resource_bit)
1851 return 0;
a2fbb9ea 1852
c18487ee 1853 msleep(5);
a2fbb9ea 1854 }
c18487ee
YR		 1855 DP(NETIF_MSG_HW, "Timeout\n");
1856 return -EAGAIN;
1857}
a2fbb9ea 1858
c9ee9206
VZ		 1859int bnx2x_release_leader_lock(struct bnx2x *bp)
1860{
1861 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1862}
1863
9f6c9258 1864int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1865{
1866 u32 lock_status;
1867 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1868 int func = BP_FUNC(bp);
1869 u32 hw_lock_control_reg;
a2fbb9ea 1870
72fd0718
VZ		 1871 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1872
c18487ee
YR		 1873 /* Validating that the resource is within range */
1874 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1875 DP(NETIF_MSG_HW,
1876 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1877 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1878 return -EINVAL;
1879 }
1880
4a37fb66
YG		 1881 if (func <= 5) {
1882 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1883 } else {
1884 hw_lock_control_reg =
1885 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1886 }
1887
c18487ee 1888 /* Validating that the resource is currently taken */
4a37fb66 1889 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 1890 if (!(lock_status & resource_bit)) {
1891 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1892 lock_status, resource_bit);
1893 return -EFAULT;
a2fbb9ea
ET		 1894 }
1895
9f6c9258
DK		 1896 REG_WR(bp, hw_lock_control_reg, resource_bit);
1897 return 0;
c18487ee 1898}
a2fbb9ea 1899
9f6c9258 1900
4acac6a5
EG		 1901int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1902{
1903 /* The GPIO should be swapped if swap register is set and active */
1904 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1905 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1906 int gpio_shift = gpio_num +
1907 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1908 u32 gpio_mask = (1 << gpio_shift);
1909 u32 gpio_reg;
1910 int value;
1911
1912 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1913 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1914 return -EINVAL;
1915 }
1916
1917 /* read GPIO value */
1918 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1919
1920 /* get the requested pin value */
1921 if ((gpio_reg & gpio_mask) == gpio_mask)
1922 value = 1;
1923 else
1924 value = 0;
1925
1926 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1927
1928 return value;
1929}
1930
17de50b7 1931int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 1932{
1933 /* The GPIO should be swapped if swap register is set and active */
1934 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 1935 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 1936 int gpio_shift = gpio_num +
1937 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1938 u32 gpio_mask = (1 << gpio_shift);
1939 u32 gpio_reg;
a2fbb9ea 1940
c18487ee
YR		 1941 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1942 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1943 return -EINVAL;
1944 }
a2fbb9ea 1945
4a37fb66 1946 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 1947 /* read GPIO and mask except the float bits */
1948 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 1949
c18487ee
YR		 1950 switch (mode) {
1951 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1952 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1953 gpio_num, gpio_shift);
1954 /* clear FLOAT and set CLR */
1955 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1956 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1957 break;
a2fbb9ea 1958
c18487ee
YR		 1959 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1960 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1961 gpio_num, gpio_shift);
1962 /* clear FLOAT and set SET */
1963 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1964 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1965 break;
a2fbb9ea 1966
17de50b7 1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
c18487ee
YR		 1968 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1969 gpio_num, gpio_shift);
1970 /* set FLOAT */
1971 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1972 break;
a2fbb9ea 1973
c18487ee
YR		 1974 default:
1975 break;
a2fbb9ea
ET		 1976 }
1977
c18487ee 1978 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 1979 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 1980
c18487ee 1981 return 0;
a2fbb9ea
ET		 1982}
1983
0d40f0d4
YR		 1984int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1985{
1986 u32 gpio_reg = 0;
1987 int rc = 0;
1988
1989 /* Any port swapping should be handled by caller. */
1990
1991 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1992 /* read GPIO and mask except the float bits */
1993 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1997
1998 switch (mode) {
1999 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2000 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2001 /* set CLR */
2002 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2003 break;
2004
2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2006 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2007 /* set SET */
2008 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2009 break;
2010
2011 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2012 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2013 /* set FLOAT */
2014 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2015 break;
2016
2017 default:
2018 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2019 rc = -EINVAL;
2020 break;
2021 }
2022
2023 if (rc == 0)
2024 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2025
2026 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2027
2028 return rc;
2029}
2030
4acac6a5
EG		 2031int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032{
2033 /* The GPIO should be swapped if swap register is set and active */
2034 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2035 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2036 int gpio_shift = gpio_num +
2037 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2038 u32 gpio_mask = (1 << gpio_shift);
2039 u32 gpio_reg;
2040
2041 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2042 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2043 return -EINVAL;
2044 }
2045
2046 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2047 /* read GPIO int */
2048 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2049
2050 switch (mode) {
2051 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2052 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2053 "output low\n", gpio_num, gpio_shift);
2054 /* clear SET and set CLR */
2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2057 break;
2058
2059 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2060 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2061 "output high\n", gpio_num, gpio_shift);
2062 /* clear CLR and set SET */
2063 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2064 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2065 break;
2066
2067 default:
2068 break;
2069 }
2070
2071 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2072 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2073
2074 return 0;
2075}
2076
c18487ee 2077static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
a2fbb9ea 2078{
c18487ee
YR		 2079 u32 spio_mask = (1 << spio_num);
2080 u32 spio_reg;
a2fbb9ea 2081
c18487ee
YR		 2082 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2083 (spio_num > MISC_REGISTERS_SPIO_7)) {
2084 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2085 return -EINVAL;
a2fbb9ea
ET		 2086 }
2087
4a37fb66 2088 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee
YR		 2089 /* read SPIO and mask except the float bits */
2090 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
a2fbb9ea 2091
c18487ee 2092 switch (mode) {
6378c025 2093 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
c18487ee
YR		 2094 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2095 /* clear FLOAT and set CLR */
2096 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2097 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2098 break;
a2fbb9ea 2099
6378c025 2100 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
c18487ee
YR		 2101 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2102 /* clear FLOAT and set SET */
2103 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2104 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2105 break;
a2fbb9ea 2106
c18487ee
YR		 2107 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2108 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2109 /* set FLOAT */
2110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2111 break;
a2fbb9ea 2112
c18487ee
YR		 2113 default:
2114 break;
a2fbb9ea
ET		 2115 }
2116
c18487ee 2117 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2118 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2119
a2fbb9ea
ET		 2120 return 0;
2121}
2122
9f6c9258 2123void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2124{
a22f0788 2125 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
ad33ea3a
EG		 2126 switch (bp->link_vars.ieee_fc &
2127 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2128 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
a22f0788 2129 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2130 ADVERTISED_Pause);
c18487ee 2131 break;
356e2385 2132
c18487ee 2133 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2134 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2135 ADVERTISED_Pause);
c18487ee 2136 break;
356e2385 2137
c18487ee 2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2139 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2140 break;
356e2385 2141
c18487ee 2142 default:
a22f0788 2143 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
f85582f8 2144 ADVERTISED_Pause);
c18487ee
YR		 2145 break;
2146 }
2147}
f1410647 2148
9f6c9258 2149u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
c18487ee 2150{
19680c48
EG		 2151 if (!BP_NOMCP(bp)) {
2152 u8 rc;
a22f0788
YR		 2153 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2154 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1cb0c788
YR		 2155 /*
2156 * Initialize link parameters structure variables
2157 * It is recommended to turn off RX FC for jumbo frames
2158 * for better performance
2159 */
2160 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
c0700f90 2161 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
8c99e7b0 2162 else
c0700f90 2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
a2fbb9ea 2164
4a37fb66 2165 bnx2x_acquire_phy_lock(bp);
b5bf9068 2166
a22f0788 2167 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2168 struct link_params *lp = &bp->link_params;
2169 lp->loopback_mode = LOOPBACK_XGXS;
2170 /* do PHY loopback at 10G speed, if possible */
2171 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2172 if (lp->speed_cap_mask[cfx_idx] &
2173 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2174 lp->req_line_speed[cfx_idx] =
2175 SPEED_10000;
2176 else
2177 lp->req_line_speed[cfx_idx] =
2178 SPEED_1000;
2179 }
a22f0788 2180 }
b5bf9068 2181
19680c48 2182 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2183
4a37fb66 2184 bnx2x_release_phy_lock(bp);
a2fbb9ea 2185
3c96c68b
EG		 2186 bnx2x_calc_fc_adv(bp);
2187
b5bf9068
EG		 2188 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2189 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2190 bnx2x_link_report(bp);
3deb8167
YR		 2191 } else
2192 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2193 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2194 return rc;
2195 }
f5372251 2196 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2197 return -EINVAL;
a2fbb9ea
ET		 2198}
2199
9f6c9258 2200void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2201{
19680c48 2202 if (!BP_NOMCP(bp)) {
4a37fb66 2203 bnx2x_acquire_phy_lock(bp);
54c2fb78 2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
19680c48 2205 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2206 bnx2x_release_phy_lock(bp);
a2fbb9ea 2207
19680c48
EG		 2208 bnx2x_calc_fc_adv(bp);
2209 } else
f5372251 2210 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2211}
a2fbb9ea 2212
c18487ee
YR		 2213static void bnx2x__link_reset(struct bnx2x *bp)
2214{
19680c48 2215 if (!BP_NOMCP(bp)) {
4a37fb66 2216 bnx2x_acquire_phy_lock(bp);
589abe3a 2217 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
4a37fb66 2218 bnx2x_release_phy_lock(bp);
19680c48 2219 } else
f5372251 2220 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2221}
a2fbb9ea 2222
a22f0788 2223u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2224{
2145a920 2225 u8 rc = 0;
a2fbb9ea 2226
2145a920
VZ		 2227 if (!BP_NOMCP(bp)) {
2228 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2229 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2230 is_serdes);
2145a920
VZ		 2231 bnx2x_release_phy_lock(bp);
2232 } else
2233 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2234
c18487ee
YR		 2235 return rc;
2236}
a2fbb9ea 2237
8a1c38d1 2238static void bnx2x_init_port_minmax(struct bnx2x *bp)
34f80b04 2239{
8a1c38d1
EG		 2240 u32 r_param = bp->link_vars.line_speed / 8;
2241 u32 fair_periodic_timeout_usec;
2242 u32 t_fair;
34f80b04 2243
8a1c38d1
EG		 2244 memset(&(bp->cmng.rs_vars), 0,
2245 sizeof(struct rate_shaping_vars_per_port));
2246 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
34f80b04 2247
8a1c38d1
EG		 2248 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2249 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
34f80b04 2250
8a1c38d1
EG		 2251 /* this is the threshold below which no timer arming will occur
2252 1.25 coefficient is for the threshold to be a little bigger
2253 than the real time, to compensate for timer in-accuracy */
2254 bp->cmng.rs_vars.rs_threshold =
34f80b04
EG		 2255 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2256
8a1c38d1
EG		 2257 /* resolution of fairness timer */
2258 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2259 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2260 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
34f80b04 2261
8a1c38d1
EG		 2262 /* this is the threshold below which we won't arm the timer anymore */
2263 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
34f80b04 2264
8a1c38d1
EG		 2265 /* we multiply by 1e3/8 to get bytes/msec.
2266 We don't want the credits to pass a credit
2267 of the t_fair*FAIR_MEM (algorithm resolution) */
2268 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2269 /* since each tick is 4 usec */
2270 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
34f80b04
EG		 2271}
2272
2691d51d
EG		 2273/* Calculates the sum of vn_min_rates.
2274 It's needed for further normalizing of the min_rates.
2275 Returns:
2276 sum of vn_min_rates.
2277 or
2278 0 - if all the min_rates are 0.
2279 In the later case fainess algorithm should be deactivated.
2280 If not all min_rates are zero then those that are zeroes will be set to 1.
2281 */
2282static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2283{
2284 int all_zero = 1;
2691d51d
EG		 2285 int vn;
2286
2287 bp->vn_weight_sum = 0;
3395a033 2288 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2289 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2290 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2291 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2292
2293 /* Skip hidden vns */
2294 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2295 continue;
2296
2297 /* If min rate is zero - set it to 1 */
2298 if (!vn_min_rate)
2299 vn_min_rate = DEF_MIN_RATE;
2300 else
2301 all_zero = 0;
2302
2303 bp->vn_weight_sum += vn_min_rate;
2304 }
2305
30ae438b
DK		 2306 /* if ETS or all min rates are zeros - disable fairness */
2307 if (BNX2X_IS_ETS_ENABLED(bp)) {
2308 bp->cmng.flags.cmng_enables &=
2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2310 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2311 } else if (all_zero) {
b015e3d1
EG		 2312 bp->cmng.flags.cmng_enables &=
2313 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2314 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2315 " fairness will be disabled\n");
2316 } else
2317 bp->cmng.flags.cmng_enables |=
2318 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2319}
2320
f2e0899f 2321static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
34f80b04
EG		 2322{
2323 struct rate_shaping_vars_per_vn m_rs_vn;
2324 struct fairness_vars_per_vn m_fair_vn;
f2e0899f 2325 u32 vn_cfg = bp->mf_config[vn];
3395a033 2326 int func = func_by_vn(bp, vn);
34f80b04
EG		 2327 u16 vn_min_rate, vn_max_rate;
2328 int i;
2329
2330 /* If function is hidden - set min and max to zeroes */
2331 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2332 vn_min_rate = 0;
2333 vn_max_rate = 0;
2334
2335 } else {
faa6fcbb
DK		 2336 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2337
34f80b04
EG		 2338 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2339 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
faa6fcbb
DK		 2340 /* If fairness is enabled (not all min rates are zeroes) and
2341 if current min rate is zero - set it to 1.
2342 This is a requirement of the algorithm. */
f2e0899f 2343 if (bp->vn_weight_sum && (vn_min_rate == 0))
34f80b04 2344 vn_min_rate = DEF_MIN_RATE;
faa6fcbb
DK		 2345
2346 if (IS_MF_SI(bp))
2347 /* maxCfg in percents of linkspeed */
2348 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2349 else
2350 /* maxCfg is absolute in 100Mb units */
2351 vn_max_rate = maxCfg * 100;
34f80b04 2352 }
f85582f8 2353
8a1c38d1 2354 DP(NETIF_MSG_IFUP,
b015e3d1 2355 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
8a1c38d1 2356 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
34f80b04
EG		 2357
2358 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2359 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2360
2361 /* global vn counter - maximal Mbps for this vn */
2362 m_rs_vn.vn_counter.rate = vn_max_rate;
2363
2364 /* quota - number of bytes transmitted in this period */
2365 m_rs_vn.vn_counter.quota =
2366 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2367
8a1c38d1 2368 if (bp->vn_weight_sum) {
34f80b04
EG		 2369 /* credit for each period of the fairness algorithm:
2370 number of bytes in T_FAIR (the vn share the port rate).
8a1c38d1
EG		 2371 vn_weight_sum should not be larger than 10000, thus
2372 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2373 than zero */
34f80b04 2374 m_fair_vn.vn_credit_delta =
cdaa7cb8
VZ		 2375 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2376 (8 * bp->vn_weight_sum))),
ff80ee02
DK		 2377 (bp->cmng.fair_vars.fair_threshold +
2378 MIN_ABOVE_THRESH));
cdaa7cb8 2379 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
34f80b04
EG		 2380 m_fair_vn.vn_credit_delta);
2381 }
2382
34f80b04
EG		 2383 /* Store it to internal memory */
2384 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2385 REG_WR(bp, BAR_XSTRORM_INTMEM +
2386 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2387 ((u32 *)(&m_rs_vn))[i]);
2388
2389 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2390 REG_WR(bp, BAR_XSTRORM_INTMEM +
2391 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2392 ((u32 *)(&m_fair_vn))[i]);
2393}
f85582f8 2394
523224a3
DK		 2395static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2396{
2397 if (CHIP_REV_IS_SLOW(bp))
2398 return CMNG_FNS_NONE;
fb3bff17 2399 if (IS_MF(bp))
523224a3
DK		 2400 return CMNG_FNS_MINMAX;
2401
2402 return CMNG_FNS_NONE;
2403}
2404
2ae17f66 2405void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2406{
0793f83f 2407 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2408
2409 if (BP_NOMCP(bp))
2410 return; /* what should be the default bvalue in this case */
2411
0793f83f
DK		 2412 /* For 2 port configuration the absolute function number formula
2413 * is:
2414 * abs_func = 2 * vn + BP_PORT + BP_PATH
2415 *
2416 * and there are 4 functions per port
2417 *
2418 * For 4 port configuration it is
2419 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2420 *
2421 * and there are 2 functions per port
2422 */
3395a033 2423 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2424 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2425
2426 if (func >= E1H_FUNC_MAX)
2427 break;
2428
f2e0899f 2429 bp->mf_config[vn] =
523224a3
DK		 2430 MF_CFG_RD(bp, func_mf_config[func].config);
2431 }
2432}
2433
2434static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2435{
2436
2437 if (cmng_type == CMNG_FNS_MINMAX) {
2438 int vn;
2439
2440 /* clear cmng_enables */
2441 bp->cmng.flags.cmng_enables = 0;
2442
2443 /* read mf conf from shmem */
2444 if (read_cfg)
2445 bnx2x_read_mf_cfg(bp);
2446
2447 /* Init rate shaping and fairness contexts */
2448 bnx2x_init_port_minmax(bp);
2449
2450 /* vn_weight_sum and enable fairness if not 0 */
2451 bnx2x_calc_vn_weight_sum(bp);
2452
2453 /* calculate and set min-max rate for each vn */
c4154f25 2454 if (bp->port.pmf)
3395a033 2455 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
c4154f25 2456 bnx2x_init_vn_minmax(bp, vn);
523224a3
DK		 2457
2458 /* always enable rate shaping and fairness */
2459 bp->cmng.flags.cmng_enables |=
2460 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2461 if (!bp->vn_weight_sum)
2462 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2463 " fairness will be disabled\n");
2464 return;
2465 }
2466
2467 /* rate shaping and fairness are disabled */
2468 DP(NETIF_MSG_IFUP,
2469 "rate shaping and fairness are disabled\n");
2470}
34f80b04 2471
c18487ee
YR		 2472/* This function is called upon link interrupt */
2473static void bnx2x_link_attn(struct bnx2x *bp)
2474{
bb2a0f7a
YG		 2475 /* Make sure that we are synced with the current statistics */
2476 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2477
c18487ee 2478 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2479
bb2a0f7a
YG		 2480 if (bp->link_vars.link_up) {
2481
1c06328c 2482 /* dropless flow control */
f2e0899f 2483 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1c06328c
EG		 2484 int port = BP_PORT(bp);
2485 u32 pause_enabled = 0;
2486
2487 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2488 pause_enabled = 1;
2489
2490 REG_WR(bp, BAR_USTRORM_INTMEM +
ca00392c 2491 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
1c06328c
EG		 2492 pause_enabled);
2493 }
2494
619c5cb6 2495 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2496 struct host_port_stats *pstats;
2497
2498 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2499 /* reset old mac stats */
bb2a0f7a
YG		 2500 memset(&(pstats->mac_stx[0]), 0,
2501 sizeof(struct mac_stx));
2502 }
f34d28ea 2503 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2504 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2505 }
2506
f2e0899f
DK		 2507 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2508 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
8a1c38d1 2509
f2e0899f
DK		 2510 if (cmng_fns != CMNG_FNS_NONE) {
2511 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2512 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2513 } else
2514 /* rate shaping and fairness are disabled */
2515 DP(NETIF_MSG_IFUP,
2516 "single function mode without fairness\n");
34f80b04 2517 }
9fdc3e95 2518
2ae17f66
VZ		 2519 __bnx2x_link_report(bp);
2520
9fdc3e95
DK		 2521 if (IS_MF(bp))
2522 bnx2x_link_sync_notify(bp);
c18487ee 2523}
a2fbb9ea 2524
9f6c9258 2525void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2526{
2ae17f66 2527 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2528 return;
a2fbb9ea 2529
00253a8c
DK		 2530 /* read updated dcb configuration */
2531 bnx2x_dcbx_pmf_update(bp);
2532
c18487ee 2533 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2534
bb2a0f7a
YG		 2535 if (bp->link_vars.link_up)
2536 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2537 else
2538 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2539
c18487ee
YR		 2540 /* indicate link status */
2541 bnx2x_link_report(bp);
a2fbb9ea 2542}
a2fbb9ea 2543
34f80b04
EG		 2544static void bnx2x_pmf_update(struct bnx2x *bp)
2545{
2546 int port = BP_PORT(bp);
2547 u32 val;
2548
2549 bp->port.pmf = 1;
2550 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2551
3deb8167
YR		 2552 /*
2553 * We need the mb() to ensure the ordering between the writing to
2554 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2555 */
2556 smp_mb();
2557
2558 /* queue a periodic task */
2559 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2560
ef01854e
DK		 2561 bnx2x_dcbx_pmf_update(bp);
2562
34f80b04 2563 /* enable nig attention */
3395a033 2564 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2565 if (bp->common.int_block == INT_BLOCK_HC) {
2566 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2567 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2568 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2569 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2570 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2571 }
bb2a0f7a
YG		 2572
2573 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2574}
2575
c18487ee 2576/* end of Link */
a2fbb9ea
ET		 2577
2578/* slow path */
2579
2580/*
2581 * General service functions
2582 */
2583
2691d51d 2584/* send the MCP a request, block until there is a reply */
a22f0788 2585u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 2586{
f2e0899f 2587 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 2588 u32 seq;
2691d51d
EG		 2589 u32 rc = 0;
2590 u32 cnt = 1;
2591 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2592
c4ff7cbf 2593 mutex_lock(&bp->fw_mb_mutex);
a5971d43 2594 seq = ++bp->fw_seq;
f2e0899f
DK		 2595 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2596 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2597
754a2f52
DK		 2598 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2599 (command | seq), param);
2691d51d
EG		 2600
2601 do {
2602 /* let the FW do it's magic ... */
2603 msleep(delay);
2604
f2e0899f 2605 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 2606
c4ff7cbf
EG		 2607 /* Give the FW up to 5 second (500*10ms) */
2608 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 2609
2610 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2611 cnt*delay, rc, seq);
2612
2613 /* is this a reply to our command? */
2614 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2615 rc &= FW_MSG_CODE_MASK;
2616 else {
2617 /* FW BUG! */
2618 BNX2X_ERR("FW failed to respond!\n");
2619 bnx2x_fw_dump(bp);
2620 rc = 0;
2621 }
c4ff7cbf 2622 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 2623
2624 return rc;
2625}
2626
ec6ba945 2627
619c5cb6
VZ		 2628void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2629{
2630 if (CHIP_IS_E1x(bp)) {
2631 struct tstorm_eth_function_common_config tcfg = {0};
2632
2633 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2634 }
2635
2636 /* Enable the function in the FW */
2637 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2638 storm_memset_func_en(bp, p->func_id, 1);
2639
2640 /* spq */
2641 if (p->func_flgs & FUNC_FLG_SPQ) {
2642 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2643 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2644 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2645 }
2646}
2647
6383c0b3
AE		 2648/**
2649 * bnx2x_get_tx_only_flags - Return common flags
2650 *
2651 * @bp device handle
2652 * @fp queue handle
2653 * @zero_stats TRUE if statistics zeroing is needed
2654 *
2655 * Return the flags that are common for the Tx-only and not normal connections.
2656 */
2657static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2658 struct bnx2x_fastpath *fp,
2659 bool zero_stats)
28912902 2660{
619c5cb6
VZ		 2661 unsigned long flags = 0;
2662
2663 /* PF driver will always initialize the Queue to an ACTIVE state */
2664 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 2665
6383c0b3
AE		 2666 /* tx only connections collect statistics (on the same index as the
2667 * parent connection). The statistics are zeroed when the parent
2668 * connection is initialized.
2669 */
50f0a562
BW		 2670
2671 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2672 if (zero_stats)
2673 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2674
6383c0b3
AE		 2675
2676 return flags;
2677}
2678
2679static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2680 struct bnx2x_fastpath *fp,
2681 bool leading)
2682{
2683 unsigned long flags = 0;
2684
619c5cb6
VZ		 2685 /* calculate other queue flags */
2686 if (IS_MF_SD(bp))
2687 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 2688
619c5cb6
VZ		 2689 if (IS_FCOE_FP(fp))
2690 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
523224a3 2691
f5219d8e 2692 if (!fp->disable_tpa) {
619c5cb6 2693 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e
VZ		 2694 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2695 }
619c5cb6 2696
619c5cb6
VZ		 2697 if (leading) {
2698 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2699 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2700 }
523224a3 2701
619c5cb6
VZ		 2702 /* Always set HW VLAN stripping */
2703 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 2704
6383c0b3
AE		 2705
2706 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 2707}
2708
619c5cb6 2709static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 2710 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2711 u8 cos)
619c5cb6
VZ		 2712{
2713 gen_init->stat_id = bnx2x_stats_id(fp);
2714 gen_init->spcl_id = fp->cl_id;
2715
2716 /* Always use mini-jumbo MTU for FCoE L2 ring */
2717 if (IS_FCOE_FP(fp))
2718 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2719 else
2720 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 2721
2722 gen_init->cos = cos;
619c5cb6
VZ		 2723}
2724
2725static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 2726 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 2727 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 2728{
619c5cb6 2729 u8 max_sge = 0;
523224a3
DK		 2730 u16 sge_sz = 0;
2731 u16 tpa_agg_size = 0;
2732
523224a3 2733 if (!fp->disable_tpa) {
dfacf138
DK		 2734 pause->sge_th_lo = SGE_TH_LO(bp);
2735 pause->sge_th_hi = SGE_TH_HI(bp);
2736
2737 /* validate SGE ring has enough to cross high threshold */
2738 WARN_ON(bp->dropless_fc &&
2739 pause->sge_th_hi + FW_PREFETCH_CNT >
2740 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2741
523224a3
DK		 2742 tpa_agg_size = min_t(u32,
2743 (min_t(u32, 8, MAX_SKB_FRAGS) *
2744 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2745 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2746 SGE_PAGE_SHIFT;
2747 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2748 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2749 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2750 0xffff);
2751 }
2752
2753 /* pause - not for e1 */
2754 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 2755 pause->bd_th_lo = BD_TH_LO(bp);
2756 pause->bd_th_hi = BD_TH_HI(bp);
2757
2758 pause->rcq_th_lo = RCQ_TH_LO(bp);
2759 pause->rcq_th_hi = RCQ_TH_HI(bp);
2760 /*
2761 * validate that rings have enough entries to cross
2762 * high thresholds
2763 */
2764 WARN_ON(bp->dropless_fc &&
2765 pause->bd_th_hi + FW_PREFETCH_CNT >
2766 bp->rx_ring_size);
2767 WARN_ON(bp->dropless_fc &&
2768 pause->rcq_th_hi + FW_PREFETCH_CNT >
2769 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 2770
523224a3
DK		 2771 pause->pri_map = 1;
2772 }
2773
2774 /* rxq setup */
523224a3
DK		 2775 rxq_init->dscr_map = fp->rx_desc_mapping;
2776 rxq_init->sge_map = fp->rx_sge_mapping;
2777 rxq_init->rcq_map = fp->rx_comp_mapping;
2778 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 2779
619c5cb6
VZ		 2780 /* This should be a maximum number of data bytes that may be
2781 * placed on the BD (not including paddings).
2782 */
e52fcb24
ED		 2783 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2784 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 2785
523224a3 2786 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 2787 rxq_init->tpa_agg_sz = tpa_agg_size;
2788 rxq_init->sge_buf_sz = sge_sz;
2789 rxq_init->max_sges_pkt = max_sge;
619c5cb6
VZ		 2790 rxq_init->rss_engine_id = BP_FUNC(bp);
2791
2792 /* Maximum number or simultaneous TPA aggregation for this Queue.
2793 *
2794 * For PF Clients it should be the maximum avaliable number.
2795 * VF driver(s) may want to define it to a smaller value.
2796 */
dfacf138 2797 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 2798
523224a3
DK		 2799 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2800 rxq_init->fw_sb_id = fp->fw_sb_id;
2801
ec6ba945
VZ		 2802 if (IS_FCOE_FP(fp))
2803 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2804 else
6383c0b3 2805 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
523224a3
DK		 2806}
2807
619c5cb6 2808static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 2809 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2810 u8 cos)
523224a3 2811{
6383c0b3
AE		 2812 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2813 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 2814 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2815 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 2816
619c5cb6
VZ		 2817 /*
2818 * set the tss leading client id for TX classfication ==
2819 * leading RSS client id
2820 */
2821 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2822
ec6ba945
VZ		 2823 if (IS_FCOE_FP(fp)) {
2824 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2825 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2826 }
523224a3
DK		 2827}
2828
8d96286a 2829static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 2830{
2831 struct bnx2x_func_init_params func_init = {0};
523224a3
DK		 2832 struct event_ring_data eq_data = { {0} };
2833 u16 flags;
2834
619c5cb6 2835 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2836 /* reset IGU PF statistics: MSIX + ATTN */
2837 /* PF */
2838 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2839 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2840 (CHIP_MODE_IS_4_PORT(bp) ?
2841 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2842 /* ATTN */
2843 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2844 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2845 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2846 (CHIP_MODE_IS_4_PORT(bp) ?
2847 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2848 }
2849
523224a3
DK		 2850 /* function setup flags */
2851 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2852
619c5cb6
VZ		 2853 /* This flag is relevant for E1x only.
2854 * E2 doesn't have a TPA configuration in a function level.
523224a3 2855 */
619c5cb6 2856 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
523224a3
DK		 2857
2858 func_init.func_flgs = flags;
2859 func_init.pf_id = BP_FUNC(bp);
2860 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 2861 func_init.spq_map = bp->spq_mapping;
2862 func_init.spq_prod = bp->spq_prod_idx;
2863
2864 bnx2x_func_init(bp, &func_init);
2865
2866 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2867
2868 /*
619c5cb6
VZ		 2869 * Congestion management values depend on the link rate
2870 * There is no active link so initial link rate is set to 10 Gbps.
2871 * When the link comes up The congestion management values are
2872 * re-calculated according to the actual link rate.
2873 */
523224a3
DK		 2874 bp->link_vars.line_speed = SPEED_10000;
2875 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2876
2877 /* Only the PMF sets the HW */
2878 if (bp->port.pmf)
2879 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2880
523224a3
DK		 2881 /* init Event Queue */
2882 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2883 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2884 eq_data.producer = bp->eq_prod;
2885 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2886 eq_data.sb_id = DEF_SB_ID;
2887 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2888}
2889
2890
2891static void bnx2x_e1h_disable(struct bnx2x *bp)
2892{
2893 int port = BP_PORT(bp);
2894
619c5cb6 2895 bnx2x_tx_disable(bp);
523224a3
DK		 2896
2897 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 2898}
2899
2900static void bnx2x_e1h_enable(struct bnx2x *bp)
2901{
2902 int port = BP_PORT(bp);
2903
2904 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2905
2906 /* Tx queue should be only reenabled */
2907 netif_tx_wake_all_queues(bp->dev);
2908
2909 /*
2910 * Should not call netif_carrier_on since it will be called if the link
2911 * is up when checking for link state
2912 */
2913}
2914
0793f83f
DK		 2915/* called due to MCP event (on pmf):
2916 * reread new bandwidth configuration
2917 * configure FW
2918 * notify others function about the change
2919 */
2920static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2921{
2922 if (bp->link_vars.link_up) {
2923 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2924 bnx2x_link_sync_notify(bp);
2925 }
2926 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2927}
2928
2929static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2930{
2931 bnx2x_config_mf_bw(bp);
2932 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2933}
2934
523224a3
DK		 2935static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2936{
2937 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2938
2939 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2940
2941 /*
2942 * This is the only place besides the function initialization
2943 * where the bp->flags can change so it is done without any
2944 * locks
2945 */
f2e0899f 2946 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
523224a3
DK		 2947 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2948 bp->flags |= MF_FUNC_DIS;
2949
2950 bnx2x_e1h_disable(bp);
2951 } else {
2952 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2953 bp->flags &= ~MF_FUNC_DIS;
2954
2955 bnx2x_e1h_enable(bp);
2956 }
2957 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2958 }
2959 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
0793f83f 2960 bnx2x_config_mf_bw(bp);
523224a3
DK		 2961 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2962 }
2963
2964 /* Report results to MCP */
2965 if (dcc_event)
2966 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2967 else
2968 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2969}
2970
2971/* must be called under the spq lock */
2972static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2973{
2974 struct eth_spe *next_spe = bp->spq_prod_bd;
2975
2976 if (bp->spq_prod_bd == bp->spq_last_bd) {
2977 bp->spq_prod_bd = bp->spq;
2978 bp->spq_prod_idx = 0;
2979 DP(NETIF_MSG_TIMER, "end of spq\n");
2980 } else {
2981 bp->spq_prod_bd++;
2982 bp->spq_prod_idx++;
2983 }
2984 return next_spe;
2985}
2986
2987/* must be called under the spq lock */
28912902
MC		 2988static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2989{
2990 int func = BP_FUNC(bp);
2991
53e51e2f
VZ		 2992 /*
2993 * Make sure that BD data is updated before writing the producer:
2994 * BD data is written to the memory, the producer is read from the
2995 * memory, thus we need a full memory barrier to ensure the ordering.
2996 */
2997 mb();
28912902 2998
523224a3 2999 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
f85582f8 3000 bp->spq_prod_idx);
28912902
MC		 3001 mmiowb();
3002}
3003
619c5cb6
VZ		 3004/**
3005 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3006 *
3007 * @cmd: command to check
3008 * @cmd_type: command type
3009 */
3010static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3011{
3012 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3013 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3014 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3015 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3016 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3017 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3018 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3019 return true;
3020 else
3021 return false;
3022
3023}
3024
3025
3026/**
3027 * bnx2x_sp_post - place a single command on an SP ring
3028 *
3029 * @bp: driver handle
3030 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3031 * @cid: SW CID the command is related to
3032 * @data_hi: command private data address (high 32 bits)
3033 * @data_lo: command private data address (low 32 bits)
3034 * @cmd_type: command type (e.g. NONE, ETH)
3035 *
3036 * SP data is handled as if it's always an address pair, thus data fields are
3037 * not swapped to little endian in upper functions. Instead this function swaps
3038 * data as if it's two u32 fields.
3039 */
9f6c9258 3040int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3041 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3042{
28912902 3043 struct eth_spe *spe;
523224a3 3044 u16 type;
619c5cb6 3045 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3046
a2fbb9ea
ET		 3047#ifdef BNX2X_STOP_ON_ERROR
3048 if (unlikely(bp->panic))
3049 return -EIO;
3050#endif
3051
34f80b04 3052 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3053
6e30dd4e
VZ		 3054 if (common) {
3055 if (!atomic_read(&bp->eq_spq_left)) {
3056 BNX2X_ERR("BUG! EQ ring full!\n");
3057 spin_unlock_bh(&bp->spq_lock);
3058 bnx2x_panic();
3059 return -EBUSY;
3060 }
3061 } else if (!atomic_read(&bp->cq_spq_left)) {
3062 BNX2X_ERR("BUG! SPQ ring full!\n");
3063 spin_unlock_bh(&bp->spq_lock);
3064 bnx2x_panic();
3065 return -EBUSY;
a2fbb9ea 3066 }
f1410647 3067
28912902
MC		 3068 spe = bnx2x_sp_get_next(bp);
3069
a2fbb9ea 3070 /* CID needs port number to be encoded int it */
28912902 3071 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3072 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3073 HW_CID(bp, cid));
523224a3 3074
619c5cb6 3075 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
a2fbb9ea 3076
523224a3
DK		 3077 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3078 SPE_HDR_FUNCTION_ID);
a2fbb9ea 3079
523224a3
DK		 3080 spe->hdr.type = cpu_to_le16(type);
3081
3082 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3083 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3084
d6cae238
VZ		 3085 /*
3086 * It's ok if the actual decrement is issued towards the memory
3087 * somewhere between the spin_lock and spin_unlock. Thus no
3088 * more explict memory barrier is needed.
3089 */
3090 if (common)
3091 atomic_dec(&bp->eq_spq_left);
3092 else
3093 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3094
a2fbb9ea 3095
cdaa7cb8 3096 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
d6cae238
VZ		 3097 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3098 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3099 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3100 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3101 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3102 HW_CID(bp, cid), data_hi, data_lo, type,
3103 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3104
28912902 3105 bnx2x_sp_prod_update(bp);
34f80b04 3106 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3107 return 0;
3108}
3109
3110/* acquire split MCP access lock register */
4a37fb66 3111static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3112{
72fd0718 3113 u32 j, val;
34f80b04 3114 int rc = 0;
a2fbb9ea
ET		 3115
3116 might_sleep();
72fd0718 3117 for (j = 0; j < 1000; j++) {
a2fbb9ea
ET		 3118 val = (1UL << 31);
3119 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3120 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3121 if (val & (1L << 31))
3122 break;
3123
3124 msleep(5);
3125 }
a2fbb9ea 3126 if (!(val & (1L << 31))) {
19680c48 3127 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3128 rc = -EBUSY;
3129 }
3130
3131 return rc;
3132}
3133
4a37fb66
YG		 3134/* release split MCP access lock register */
3135static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3136{
72fd0718 3137 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
a2fbb9ea
ET		 3138}
3139
523224a3
DK		 3140#define BNX2X_DEF_SB_ATT_IDX 0x0001
3141#define BNX2X_DEF_SB_IDX 0x0002
3142
a2fbb9ea
ET		 3143static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3144{
523224a3 3145 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3146 u16 rc = 0;
3147
3148 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3149 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3150 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3151 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3152 }
523224a3
DK		 3153
3154 if (bp->def_idx != def_sb->sp_sb.running_index) {
3155 bp->def_idx = def_sb->sp_sb.running_index;
3156 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3157 }
523224a3
DK		 3158
3159 /* Do not reorder: indecies reading should complete before handling */
3160 barrier();
a2fbb9ea
ET		 3161 return rc;
3162}
3163
3164/*
3165 * slow path service functions
3166 */
3167
3168static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3169{
34f80b04 3170 int port = BP_PORT(bp);
a2fbb9ea
ET		 3171 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3172 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 3173 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3174 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 3175 u32 aeu_mask;
87942b46 3176 u32 nig_mask = 0;
f2e0899f 3177 u32 reg_addr;
a2fbb9ea 3178
a2fbb9ea
ET		 3179 if (bp->attn_state & asserted)
3180 BNX2X_ERR("IGU ERROR\n");
3181
3fcaf2e5
EG		 3182 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3183 aeu_mask = REG_RD(bp, aeu_addr);
3184
a2fbb9ea 3185 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 3186 aeu_mask, asserted);
72fd0718 3187 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 3188 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 3189
3fcaf2e5
EG		 3190 REG_WR(bp, aeu_addr, aeu_mask);
3191 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 3192
3fcaf2e5 3193 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 3194 bp->attn_state |= asserted;
3fcaf2e5 3195 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 3196
3197 if (asserted & ATTN_HARD_WIRED_MASK) {
3198 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 3199
a5e9a7cf
EG		 3200 bnx2x_acquire_phy_lock(bp);
3201
877e9aa4 3202 /* save nig interrupt mask */
87942b46 3203 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 3204
361c391e
YR		 3205 /* If nig_mask is not set, no need to call the update
3206 * function.
3207 */
3208 if (nig_mask) {
3209 REG_WR(bp, nig_int_mask_addr, 0);
3210
3211 bnx2x_link_attn(bp);
3212 }
a2fbb9ea
ET		 3213
3214 /* handle unicore attn? */
3215 }
3216 if (asserted & ATTN_SW_TIMER_4_FUNC)
3217 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3218
3219 if (asserted & GPIO_2_FUNC)
3220 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3221
3222 if (asserted & GPIO_3_FUNC)
3223 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3224
3225 if (asserted & GPIO_4_FUNC)
3226 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3227
3228 if (port == 0) {
3229 if (asserted & ATTN_GENERAL_ATTN_1) {
3230 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3231 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3232 }
3233 if (asserted & ATTN_GENERAL_ATTN_2) {
3234 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3235 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3236 }
3237 if (asserted & ATTN_GENERAL_ATTN_3) {
3238 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3239 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3240 }
3241 } else {
3242 if (asserted & ATTN_GENERAL_ATTN_4) {
3243 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3244 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3245 }
3246 if (asserted & ATTN_GENERAL_ATTN_5) {
3247 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3248 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3249 }
3250 if (asserted & ATTN_GENERAL_ATTN_6) {
3251 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3252 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3253 }
3254 }
3255
3256 } /* if hardwired */
3257
f2e0899f
DK		 3258 if (bp->common.int_block == INT_BLOCK_HC)
3259 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3260 COMMAND_REG_ATTN_BITS_SET);
3261 else
3262 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3263
3264 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3265 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3266 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 3267
3268 /* now set back the mask */
a5e9a7cf 3269 if (asserted & ATTN_NIG_FOR_FUNC) {
87942b46 3270 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 3271 bnx2x_release_phy_lock(bp);
3272 }
a2fbb9ea
ET		 3273}
3274
fd4ef40d
EG		 3275static inline void bnx2x_fan_failure(struct bnx2x *bp)
3276{
3277 int port = BP_PORT(bp);
b7737c9b 3278 u32 ext_phy_config;
fd4ef40d 3279 /* mark the failure */
b7737c9b
YR		 3280 ext_phy_config =
3281 SHMEM_RD(bp,
3282 dev_info.port_hw_config[port].external_phy_config);
3283
3284 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3285 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 3286 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 3287 ext_phy_config);
fd4ef40d
EG		 3288
3289 /* log the failure */
cdaa7cb8
VZ		 3290 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3291 " the driver to shutdown the card to prevent permanent"
3292 " damage. Please contact OEM Support for assistance\n");
8304859a
AE		 3293
3294 /*
3295 * Scheudle device reset (unload)
3296 * This is due to some boards consuming sufficient power when driver is
3297 * up to overheat if fan fails.
3298 */
3299 smp_mb__before_clear_bit();
3300 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3301 smp_mb__after_clear_bit();
3302 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3303
fd4ef40d 3304}
ab6ad5a4 3305
877e9aa4 3306static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 3307{
34f80b04 3308 int port = BP_PORT(bp);
877e9aa4 3309 int reg_offset;
d90d96ba 3310 u32 val;
877e9aa4 3311
34f80b04
EG		 3312 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3313 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 3314
34f80b04 3315 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 3316
3317 val = REG_RD(bp, reg_offset);
3318 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3319 REG_WR(bp, reg_offset, val);
3320
3321 BNX2X_ERR("SPIO5 hw attention\n");
3322
fd4ef40d 3323 /* Fan failure attention */
d90d96ba 3324 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 3325 bnx2x_fan_failure(bp);
877e9aa4 3326 }
34f80b04 3327
3deb8167 3328 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 3329 bnx2x_acquire_phy_lock(bp);
3330 bnx2x_handle_module_detect_int(&bp->link_params);
3331 bnx2x_release_phy_lock(bp);
3332 }
3333
34f80b04
EG		 3334 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3335
3336 val = REG_RD(bp, reg_offset);
3337 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3338 REG_WR(bp, reg_offset, val);
3339
3340 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
0fc5d009 3341 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
34f80b04
EG		 3342 bnx2x_panic();
3343 }
877e9aa4
ET		 3344}
3345
3346static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3347{
3348 u32 val;
3349
0626b899 3350 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 3351
3352 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3353 BNX2X_ERR("DB hw attention 0x%x\n", val);
3354 /* DORQ discard attention */
3355 if (val & 0x2)
3356 BNX2X_ERR("FATAL error from DORQ\n");
3357 }
34f80b04
EG		 3358
3359 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3360
3361 int port = BP_PORT(bp);
3362 int reg_offset;
3363
3364 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3365 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3366
3367 val = REG_RD(bp, reg_offset);
3368 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3369 REG_WR(bp, reg_offset, val);
3370
3371 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
0fc5d009 3372 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
34f80b04
EG		 3373 bnx2x_panic();
3374 }
877e9aa4
ET		 3375}
3376
3377static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3378{
3379 u32 val;
3380
3381 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3382
3383 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3384 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3385 /* CFC error attention */
3386 if (val & 0x2)
3387 BNX2X_ERR("FATAL error from CFC\n");
3388 }
3389
3390 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 3391 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 3392 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 3393 /* RQ_USDMDP_FIFO_OVERFLOW */
3394 if (val & 0x18000)
3395 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 3396
3397 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3398 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3399 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3400 }
877e9aa4 3401 }
34f80b04
EG		 3402
3403 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3404
3405 int port = BP_PORT(bp);
3406 int reg_offset;
3407
3408 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3409 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3410
3411 val = REG_RD(bp, reg_offset);
3412 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3413 REG_WR(bp, reg_offset, val);
3414
3415 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
0fc5d009 3416 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
34f80b04
EG		 3417 bnx2x_panic();
3418 }
877e9aa4
ET		 3419}
3420
3421static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3422{
34f80b04
EG		 3423 u32 val;
3424
877e9aa4
ET		 3425 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3426
34f80b04
EG		 3427 if (attn & BNX2X_PMF_LINK_ASSERT) {
3428 int func = BP_FUNC(bp);
3429
3430 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
f2e0899f
DK		 3431 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3432 func_mf_config[BP_ABS_FUNC(bp)].config);
3433 val = SHMEM_RD(bp,
3434 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2691d51d
EG		 3435 if (val & DRV_STATUS_DCC_EVENT_MASK)
3436 bnx2x_dcc_event(bp,
3437 (val & DRV_STATUS_DCC_EVENT_MASK));
0793f83f
DK		 3438
3439 if (val & DRV_STATUS_SET_MF_BW)
3440 bnx2x_set_mf_bw(bp);
3441
2691d51d 3442 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 3443 bnx2x_pmf_update(bp);
3444
e4901dde 3445 if (bp->port.pmf &&
785b9b1a
SR		 3446 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3447 bp->dcbx_enabled > 0)
e4901dde
VZ		 3448 /* start dcbx state machine */
3449 bnx2x_dcbx_set_params(bp,
3450 BNX2X_DCBX_STATE_NEG_RECEIVED);
3deb8167
YR		 3451 if (bp->link_vars.periodic_flags &
3452 PERIODIC_FLAGS_LINK_EVENT) {
3453 /* sync with link */
3454 bnx2x_acquire_phy_lock(bp);
3455 bp->link_vars.periodic_flags &=
3456 ~PERIODIC_FLAGS_LINK_EVENT;
3457 bnx2x_release_phy_lock(bp);
3458 if (IS_MF(bp))
3459 bnx2x_link_sync_notify(bp);
3460 bnx2x_link_report(bp);
3461 }
3462 /* Always call it here: bnx2x_link_report() will
3463 * prevent the link indication duplication.
3464 */
3465 bnx2x__link_status_update(bp);
34f80b04 3466 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 3467
3468 BNX2X_ERR("MC assert!\n");
d6cae238 3469 bnx2x_mc_assert(bp);
877e9aa4
ET		 3470 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3471 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3472 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3473 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3474 bnx2x_panic();
3475
3476 } else if (attn & BNX2X_MCP_ASSERT) {
3477
3478 BNX2X_ERR("MCP assert!\n");
3479 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 3480 bnx2x_fw_dump(bp);
877e9aa4
ET		 3481
3482 } else
3483 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3484 }
3485
3486 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 3487 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3488 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 3489 val = CHIP_IS_E1(bp) ? 0 :
3490 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 3491 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3492 }
3493 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 3494 val = CHIP_IS_E1(bp) ? 0 :
3495 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 3496 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3497 }
877e9aa4 3498 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 3499 }
3500}
3501
c9ee9206
VZ		 3502/*
3503 * Bits map:
3504 * 0-7 - Engine0 load counter.
3505 * 8-15 - Engine1 load counter.
3506 * 16 - Engine0 RESET_IN_PROGRESS bit.
3507 * 17 - Engine1 RESET_IN_PROGRESS bit.
3508 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3509 * on the engine
3510 * 19 - Engine1 ONE_IS_LOADED.
3511 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3512 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3513 * just the one belonging to its engine).
3514 *
3515 */
3516#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3517
3518#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3519#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3520#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3521#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3522#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3523#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3524#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3525
3526/*
3527 * Set the GLOBAL_RESET bit.
3528 *
3529 * Should be run under rtnl lock
3530 */
3531void bnx2x_set_reset_global(struct bnx2x *bp)
3532{
3533 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3534
3535 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3536 barrier();
3537 mmiowb();
3538}
3539
3540/*
3541 * Clear the GLOBAL_RESET bit.
3542 *
3543 * Should be run under rtnl lock
3544 */
3545static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3546{
3547 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3548
3549 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3550 barrier();
3551 mmiowb();
3552}
f85582f8 3553
72fd0718 3554/*
c9ee9206
VZ		 3555 * Checks the GLOBAL_RESET bit.
3556 *
72fd0718
VZ		 3557 * should be run under rtnl lock
3558 */
c9ee9206
VZ		 3559static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3560{
3561 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3562
3563 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3564 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3565}
3566
3567/*
3568 * Clear RESET_IN_PROGRESS bit for the current engine.
3569 *
3570 * Should be run under rtnl lock
3571 */
72fd0718
VZ		 3572static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3573{
c9ee9206
VZ		 3574 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3575 u32 bit = BP_PATH(bp) ?
3576 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3577
3578 /* Clear the bit */
3579 val &= ~bit;
3580 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3581 barrier();
3582 mmiowb();
3583}
3584
3585/*
c9ee9206
VZ		 3586 * Set RESET_IN_PROGRESS for the current engine.
3587 *
72fd0718
VZ		 3588 * should be run under rtnl lock
3589 */
c9ee9206 3590void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 3591{
c9ee9206
VZ		 3592 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3593 u32 bit = BP_PATH(bp) ?
3594 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3595
3596 /* Set the bit */
3597 val |= bit;
3598 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3599 barrier();
3600 mmiowb();
3601}
3602
3603/*
c9ee9206 3604 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 3605 * should be run under rtnl lock
3606 */
c9ee9206 3607bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 3608{
c9ee9206
VZ		 3609 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3610 u32 bit = engine ?
3611 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3612
3613 /* return false if bit is set */
3614 return (val & bit) ? false : true;
72fd0718
VZ		 3615}
3616
3617/*
c9ee9206
VZ		 3618 * Increment the load counter for the current engine.
3619 *
72fd0718
VZ		 3620 * should be run under rtnl lock
3621 */
c9ee9206 3622void bnx2x_inc_load_cnt(struct bnx2x *bp)
72fd0718 3623{
c9ee9206
VZ		 3624 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3625 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3626 BNX2X_PATH0_LOAD_CNT_MASK;
3627 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3628 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3629
3630 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3631
c9ee9206
VZ		 3632 /* get the current counter value */
3633 val1 = (val & mask) >> shift;
3634
3635 /* increment... */
3636 val1++;
3637
3638 /* clear the old value */
3639 val &= ~mask;
3640
3641 /* set the new one */
3642 val |= ((val1 << shift) & mask);
3643
3644 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3645 barrier();
3646 mmiowb();
3647}
3648
c9ee9206
VZ		 3649/**
3650 * bnx2x_dec_load_cnt - decrement the load counter
3651 *
3652 * @bp: driver handle
3653 *
3654 * Should be run under rtnl lock.
3655 * Decrements the load counter for the current engine. Returns
3656 * the new counter value.
72fd0718 3657 */
9f6c9258 3658u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
72fd0718 3659{
c9ee9206
VZ		 3660 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3661 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3662 BNX2X_PATH0_LOAD_CNT_MASK;
3663 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3664 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718
VZ		 3665
3666 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3667
c9ee9206
VZ		 3668 /* get the current counter value */
3669 val1 = (val & mask) >> shift;
3670
3671 /* decrement... */
3672 val1--;
3673
3674 /* clear the old value */
3675 val &= ~mask;
3676
3677 /* set the new one */
3678 val |= ((val1 << shift) & mask);
3679
3680 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
72fd0718
VZ		 3681 barrier();
3682 mmiowb();
3683
3684 return val1;
3685}
3686
3687/*
c9ee9206
VZ		 3688 * Read the load counter for the current engine.
3689 *
72fd0718
VZ		 3690 * should be run under rtnl lock
3691 */
c9ee9206 3692static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
72fd0718 3693{
c9ee9206
VZ		 3694 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3695 BNX2X_PATH0_LOAD_CNT_MASK);
3696 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3697 BNX2X_PATH0_LOAD_CNT_SHIFT);
3698 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3699
3700 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3701
3702 val = (val & mask) >> shift;
3703
3704 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3705
3706 return val;
72fd0718
VZ		 3707}
3708
c9ee9206
VZ		 3709/*
3710 * Reset the load counter for the current engine.
3711 *
3712 * should be run under rtnl lock
3713 */
72fd0718
VZ		 3714static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3715{
c9ee9206
VZ		 3716 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3717 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3718 BNX2X_PATH0_LOAD_CNT_MASK);
3719
3720 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
72fd0718
VZ		 3721}
3722
3723static inline void _print_next_block(int idx, const char *blk)
3724{
f1deab50 3725 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 3726}
3727
c9ee9206
VZ		 3728static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3729 bool print)
72fd0718
VZ		 3730{
3731 int i = 0;
3732 u32 cur_bit = 0;
3733 for (i = 0; sig; i++) {
3734 cur_bit = ((u32)0x1 << i);
3735 if (sig & cur_bit) {
3736 switch (cur_bit) {
3737 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
c9ee9206
VZ		 3738 if (print)
3739 _print_next_block(par_num++, "BRB");
72fd0718
VZ		 3740 break;
3741 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
c9ee9206
VZ		 3742 if (print)
3743 _print_next_block(par_num++, "PARSER");
72fd0718
VZ		 3744 break;
3745 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
c9ee9206
VZ		 3746 if (print)
3747 _print_next_block(par_num++, "TSDM");
72fd0718
VZ		 3748 break;
3749 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
c9ee9206
VZ		 3750 if (print)
3751 _print_next_block(par_num++,
3752 "SEARCHER");
3753 break;
3754 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3755 if (print)
3756 _print_next_block(par_num++, "TCM");
72fd0718
VZ		 3757 break;
3758 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
c9ee9206
VZ		 3759 if (print)
3760 _print_next_block(par_num++, "TSEMI");
3761 break;
3762 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3763 if (print)
3764 _print_next_block(par_num++, "XPB");
72fd0718
VZ		 3765 break;
3766 }
3767
3768 /* Clear the bit */
3769 sig &= ~cur_bit;
3770 }
3771 }
3772
3773 return par_num;
3774}
3775
c9ee9206
VZ		 3776static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3777 bool *global, bool print)
72fd0718
VZ		 3778{
3779 int i = 0;
3780 u32 cur_bit = 0;
3781 for (i = 0; sig; i++) {
3782 cur_bit = ((u32)0x1 << i);
3783 if (sig & cur_bit) {
3784 switch (cur_bit) {
c9ee9206
VZ		 3785 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3786 if (print)
3787 _print_next_block(par_num++, "PBF");
72fd0718
VZ		 3788 break;
3789 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
c9ee9206
VZ		 3790 if (print)
3791 _print_next_block(par_num++, "QM");
3792 break;
3793 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3794 if (print)
3795 _print_next_block(par_num++, "TM");
72fd0718
VZ		 3796 break;
3797 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
c9ee9206
VZ		 3798 if (print)
3799 _print_next_block(par_num++, "XSDM");
3800 break;
3801 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3802 if (print)
3803 _print_next_block(par_num++, "XCM");
72fd0718
VZ		 3804 break;
3805 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
c9ee9206
VZ		 3806 if (print)
3807 _print_next_block(par_num++, "XSEMI");
72fd0718
VZ		 3808 break;
3809 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
c9ee9206
VZ		 3810 if (print)
3811 _print_next_block(par_num++,
3812 "DOORBELLQ");
3813 break;
3814 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3815 if (print)
3816 _print_next_block(par_num++, "NIG");
72fd0718
VZ		 3817 break;
3818 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206
VZ		 3819 if (print)
3820 _print_next_block(par_num++,
3821 "VAUX PCI CORE");
3822 *global = true;
72fd0718
VZ		 3823 break;
3824 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
c9ee9206
VZ		 3825 if (print)
3826 _print_next_block(par_num++, "DEBUG");
72fd0718
VZ		 3827 break;
3828 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
c9ee9206
VZ		 3829 if (print)
3830 _print_next_block(par_num++, "USDM");
72fd0718 3831 break;
8736c826
VZ		 3832 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3833 if (print)
3834 _print_next_block(par_num++, "UCM");
3835 break;
72fd0718 3836 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
c9ee9206
VZ		 3837 if (print)
3838 _print_next_block(par_num++, "USEMI");
72fd0718
VZ		 3839 break;
3840 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
c9ee9206
VZ		 3841 if (print)
3842 _print_next_block(par_num++, "UPB");
72fd0718
VZ		 3843 break;
3844 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
c9ee9206
VZ		 3845 if (print)
3846 _print_next_block(par_num++, "CSDM");
72fd0718 3847 break;
8736c826
VZ		 3848 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3849 if (print)
3850 _print_next_block(par_num++, "CCM");
3851 break;
72fd0718
VZ		 3852 }
3853
3854 /* Clear the bit */
3855 sig &= ~cur_bit;
3856 }
3857 }
3858
3859 return par_num;
3860}
3861
c9ee9206
VZ		 3862static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3863 bool print)
72fd0718
VZ		 3864{
3865 int i = 0;
3866 u32 cur_bit = 0;
3867 for (i = 0; sig; i++) {
3868 cur_bit = ((u32)0x1 << i);
3869 if (sig & cur_bit) {
3870 switch (cur_bit) {
3871 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
c9ee9206
VZ		 3872 if (print)
3873 _print_next_block(par_num++, "CSEMI");
72fd0718
VZ		 3874 break;
3875 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
c9ee9206
VZ		 3876 if (print)
3877 _print_next_block(par_num++, "PXP");
72fd0718
VZ		 3878 break;
3879 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
c9ee9206
VZ		 3880 if (print)
3881 _print_next_block(par_num++,
72fd0718
VZ		 3882 "PXPPCICLOCKCLIENT");
3883 break;
3884 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
c9ee9206
VZ		 3885 if (print)
3886 _print_next_block(par_num++, "CFC");
72fd0718
VZ		 3887 break;
3888 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
c9ee9206
VZ		 3889 if (print)
3890 _print_next_block(par_num++, "CDU");
3891 break;
3892 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3893 if (print)
3894 _print_next_block(par_num++, "DMAE");
72fd0718
VZ		 3895 break;
3896 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
c9ee9206
VZ		 3897 if (print)
3898 _print_next_block(par_num++, "IGU");
72fd0718
VZ		 3899 break;
3900 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
c9ee9206
VZ		 3901 if (print)
3902 _print_next_block(par_num++, "MISC");
72fd0718
VZ		 3903 break;
3904 }
3905
3906 /* Clear the bit */
3907 sig &= ~cur_bit;
3908 }
3909 }
3910
3911 return par_num;
3912}
3913
c9ee9206
VZ		 3914static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3915 bool *global, bool print)
72fd0718
VZ		 3916{
3917 int i = 0;
3918 u32 cur_bit = 0;
3919 for (i = 0; sig; i++) {
3920 cur_bit = ((u32)0x1 << i);
3921 if (sig & cur_bit) {
3922 switch (cur_bit) {
3923 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206
VZ		 3924 if (print)
3925 _print_next_block(par_num++, "MCP ROM");
3926 *global = true;
72fd0718
VZ		 3927 break;
3928 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206
VZ		 3929 if (print)
3930 _print_next_block(par_num++,
3931 "MCP UMP RX");
3932 *global = true;
72fd0718
VZ		 3933 break;
3934 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206
VZ		 3935 if (print)
3936 _print_next_block(par_num++,
3937 "MCP UMP TX");
3938 *global = true;
72fd0718
VZ		 3939 break;
3940 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
c9ee9206
VZ		 3941 if (print)
3942 _print_next_block(par_num++,
3943 "MCP SCPAD");
3944 *global = true;
72fd0718
VZ		 3945 break;
3946 }
3947
3948 /* Clear the bit */
3949 sig &= ~cur_bit;
3950 }
3951 }
3952
3953 return par_num;
3954}
3955
8736c826
VZ		 3956static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3957 bool print)
3958{
3959 int i = 0;
3960 u32 cur_bit = 0;
3961 for (i = 0; sig; i++) {
3962 cur_bit = ((u32)0x1 << i);
3963 if (sig & cur_bit) {
3964 switch (cur_bit) {
3965 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3966 if (print)
3967 _print_next_block(par_num++, "PGLUE_B");
3968 break;
3969 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3970 if (print)
3971 _print_next_block(par_num++, "ATC");
3972 break;
3973 }
3974
3975 /* Clear the bit */
3976 sig &= ~cur_bit;
3977 }
3978 }
3979
3980 return par_num;
3981}
3982
c9ee9206 3983static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
8736c826 3984 u32 *sig)
72fd0718 3985{
8736c826
VZ		 3986 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3987 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3988 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3989 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3990 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718
VZ		 3991 int par_num = 0;
3992 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
8736c826
VZ		 3993 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
3994 "[4]:0x%08x\n",
3995 sig[0] & HW_PRTY_ASSERT_SET_0,
3996 sig[1] & HW_PRTY_ASSERT_SET_1,
3997 sig[2] & HW_PRTY_ASSERT_SET_2,
3998 sig[3] & HW_PRTY_ASSERT_SET_3,
3999 sig[4] & HW_PRTY_ASSERT_SET_4);
c9ee9206
VZ		 4000 if (print)
4001 netdev_err(bp->dev,
4002 "Parity errors detected in blocks: ");
4003 par_num = bnx2x_check_blocks_with_parity0(
8736c826 4004 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
c9ee9206 4005 par_num = bnx2x_check_blocks_with_parity1(
8736c826 4006 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
c9ee9206 4007 par_num = bnx2x_check_blocks_with_parity2(
8736c826 4008 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
c9ee9206 4009 par_num = bnx2x_check_blocks_with_parity3(
8736c826
VZ		 4010 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4011 par_num = bnx2x_check_blocks_with_parity4(
4012 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4013
c9ee9206
VZ		 4014 if (print)
4015 pr_cont("\n");
8736c826 4016
72fd0718
VZ		 4017 return true;
4018 } else
4019 return false;
4020}
4021
c9ee9206
VZ		 4022/**
4023 * bnx2x_chk_parity_attn - checks for parity attentions.
4024 *
4025 * @bp: driver handle
4026 * @global: true if there was a global attention
4027 * @print: show parity attention in syslog
4028 */
4029bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 4030{
8736c826 4031 struct attn_route attn = { {0} };
72fd0718
VZ		 4032 int port = BP_PORT(bp);
4033
4034 attn.sig[0] = REG_RD(bp,
4035 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4036 port*4);
4037 attn.sig[1] = REG_RD(bp,
4038 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4039 port*4);
4040 attn.sig[2] = REG_RD(bp,
4041 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4042 port*4);
4043 attn.sig[3] = REG_RD(bp,
4044 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4045 port*4);
4046
8736c826
VZ		 4047 if (!CHIP_IS_E1x(bp))
4048 attn.sig[4] = REG_RD(bp,
4049 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4050 port*4);
4051
4052 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 4053}
4054
f2e0899f
DK		 4055
4056static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4057{
4058 u32 val;
4059 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4060
4061 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4062 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4063 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4064 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4065 "ADDRESS_ERROR\n");
4066 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4067 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4068 "INCORRECT_RCV_BEHAVIOR\n");
4069 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4070 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4071 "WAS_ERROR_ATTN\n");
4072 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4073 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4074 "VF_LENGTH_VIOLATION_ATTN\n");
4075 if (val &
4076 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4077 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4078 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4079 if (val &
4080 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4081 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4082 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4083 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4084 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4085 "TCPL_ERROR_ATTN\n");
4086 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4087 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4088 "TCPL_IN_TWO_RCBS_ATTN\n");
4089 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4090 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4091 "CSSNOOP_FIFO_OVERFLOW\n");
4092 }
4093 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4094 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4095 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4096 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4097 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4098 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4099 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4100 "_ATC_TCPL_TO_NOT_PEND\n");
4101 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4102 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4103 "ATC_GPA_MULTIPLE_HITS\n");
4104 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4105 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4106 "ATC_RCPL_TO_EMPTY_CNT\n");
4107 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4108 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4109 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4110 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4111 "ATC_IREQ_LESS_THAN_STU\n");
4112 }
4113
4114 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4115 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4116 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4117 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4118 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4119 }
4120
4121}
4122
72fd0718
VZ		 4123static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4124{
4125 struct attn_route attn, *group_mask;
34f80b04 4126 int port = BP_PORT(bp);
877e9aa4 4127 int index;
a2fbb9ea
ET		 4128 u32 reg_addr;
4129 u32 val;
3fcaf2e5 4130 u32 aeu_mask;
c9ee9206 4131 bool global = false;
a2fbb9ea
ET		 4132
4133 /* need to take HW lock because MCP or other port might also
4134 try to handle this event */
4a37fb66 4135 bnx2x_acquire_alr(bp);
a2fbb9ea 4136
c9ee9206
VZ		 4137 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4138#ifndef BNX2X_STOP_ON_ERROR
72fd0718 4139 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 4140 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 4141 /* Disable HW interrupts */
4142 bnx2x_int_disable(bp);
72fd0718
VZ		 4143 /* In case of parity errors don't handle attentions so that
4144 * other function would "see" parity errors.
4145 */
c9ee9206
VZ		 4146#else
4147 bnx2x_panic();
4148#endif
4149 bnx2x_release_alr(bp);
72fd0718
VZ		 4150 return;
4151 }
4152
a2fbb9ea
ET		 4153 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4154 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4155 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4156 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 4157 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4158 attn.sig[4] =
4159 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4160 else
4161 attn.sig[4] = 0;
4162
4163 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4164 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 4165
4166 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4167 if (deasserted & (1 << index)) {
72fd0718 4168 group_mask = &bp->attn_group[index];
a2fbb9ea 4169
f2e0899f
DK		 4170 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4171 "%08x %08x %08x\n",
4172 index,
4173 group_mask->sig[0], group_mask->sig[1],
4174 group_mask->sig[2], group_mask->sig[3],
4175 group_mask->sig[4]);
a2fbb9ea 4176
f2e0899f
DK		 4177 bnx2x_attn_int_deasserted4(bp,
4178 attn.sig[4] & group_mask->sig[4]);
877e9aa4 4179 bnx2x_attn_int_deasserted3(bp,
72fd0718 4180 attn.sig[3] & group_mask->sig[3]);
877e9aa4 4181 bnx2x_attn_int_deasserted1(bp,
72fd0718 4182 attn.sig[1] & group_mask->sig[1]);
877e9aa4 4183 bnx2x_attn_int_deasserted2(bp,
72fd0718 4184 attn.sig[2] & group_mask->sig[2]);
877e9aa4 4185 bnx2x_attn_int_deasserted0(bp,
72fd0718 4186 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 4187 }
4188 }
4189
4a37fb66 4190 bnx2x_release_alr(bp);
a2fbb9ea 4191
f2e0899f
DK		 4192 if (bp->common.int_block == INT_BLOCK_HC)
4193 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4194 COMMAND_REG_ATTN_BITS_CLR);
4195 else
4196 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 4197
4198 val = ~deasserted;
f2e0899f
DK		 4199 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4200 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 4201 REG_WR(bp, reg_addr, val);
a2fbb9ea 4202
a2fbb9ea 4203 if (~bp->attn_state & deasserted)
3fcaf2e5 4204 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 4205
4206 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4207 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4208
3fcaf2e5
EG		 4209 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4210 aeu_mask = REG_RD(bp, reg_addr);
4211
4212 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4213 aeu_mask, deasserted);
72fd0718 4214 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 4215 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4216
3fcaf2e5
EG		 4217 REG_WR(bp, reg_addr, aeu_mask);
4218 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 4219
4220 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4221 bp->attn_state &= ~deasserted;
4222 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4223}
4224
4225static void bnx2x_attn_int(struct bnx2x *bp)
4226{
4227 /* read local copy of bits */
68d59484
EG		 4228 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4229 attn_bits);
4230 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4231 attn_bits_ack);
a2fbb9ea
ET		 4232 u32 attn_state = bp->attn_state;
4233
4234 /* look for changed bits */
4235 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4236 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4237
4238 DP(NETIF_MSG_HW,
4239 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4240 attn_bits, attn_ack, asserted, deasserted);
4241
4242 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 4243 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 4244
4245 /* handle bits that were raised */
4246 if (asserted)
4247 bnx2x_attn_int_asserted(bp, asserted);
4248
4249 if (deasserted)
4250 bnx2x_attn_int_deasserted(bp, deasserted);
4251}
4252
619c5cb6
VZ		 4253void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4254 u16 index, u8 op, u8 update)
4255{
4256 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4257
4258 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4259 igu_addr);
4260}
4261
523224a3
DK		 4262static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4263{
4264 /* No memory barriers */
4265 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4266 mmiowb(); /* keep prod updates ordered */
4267}
4268
4269#ifdef BCM_CNIC
4270static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4271 union event_ring_elem *elem)
4272{
619c5cb6
VZ		 4273 u8 err = elem->message.error;
4274
523224a3 4275 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 4276 (cid < bp->cnic_eth_dev.starting_cid &&
4277 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 4278 return 1;
4279
4280 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4281
619c5cb6
VZ		 4282 if (unlikely(err)) {
4283
523224a3
DK		 4284 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4285 cid);
4286 bnx2x_panic_dump(bp);
4287 }
619c5cb6 4288 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 4289 return 0;
4290}
4291#endif
4292
619c5cb6
VZ		 4293static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4294{
4295 struct bnx2x_mcast_ramrod_params rparam;
4296 int rc;
4297
4298 memset(&rparam, 0, sizeof(rparam));
4299
4300 rparam.mcast_obj = &bp->mcast_obj;
4301
4302 netif_addr_lock_bh(bp->dev);
4303
4304 /* Clear pending state for the last command */
4305 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4306
4307 /* If there are pending mcast commands - send them */
4308 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4309 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4310 if (rc < 0)
4311 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4312 rc);
4313 }
4314
4315 netif_addr_unlock_bh(bp->dev);
4316}
4317
4318static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4319 union event_ring_elem *elem)
4320{
4321 unsigned long ramrod_flags = 0;
4322 int rc = 0;
4323 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4324 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4325
4326 /* Always push next commands out, don't wait here */
4327 __set_bit(RAMROD_CONT, &ramrod_flags);
4328
4329 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4330 case BNX2X_FILTER_MAC_PENDING:
4331#ifdef BCM_CNIC
4332 if (cid == BNX2X_ISCSI_ETH_CID)
4333 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4334 else
4335#endif
4336 vlan_mac_obj = &bp->fp[cid].mac_obj;
4337
4338 break;
619c5cb6
VZ		 4339 case BNX2X_FILTER_MCAST_PENDING:
4340 /* This is only relevant for 57710 where multicast MACs are
4341 * configured as unicast MACs using the same ramrod.
4342 */
4343 bnx2x_handle_mcast_eqe(bp);
4344 return;
4345 default:
4346 BNX2X_ERR("Unsupported classification command: %d\n",
4347 elem->message.data.eth_event.echo);
4348 return;
4349 }
4350
4351 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4352
4353 if (rc < 0)
4354 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4355 else if (rc > 0)
4356 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4357
4358}
4359
4360#ifdef BCM_CNIC
4361static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4362#endif
4363
4364static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4365{
4366 netif_addr_lock_bh(bp->dev);
4367
4368 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4369
4370 /* Send rx_mode command again if was requested */
4371 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4372 bnx2x_set_storm_rx_mode(bp);
4373#ifdef BCM_CNIC
4374 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4375 &bp->sp_state))
4376 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4377 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4378 &bp->sp_state))
4379 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4380#endif
4381
4382 netif_addr_unlock_bh(bp->dev);
4383}
4384
4385static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4386 struct bnx2x *bp, u32 cid)
4387{
94f05b0f 4388 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
619c5cb6
VZ		 4389#ifdef BCM_CNIC
4390 if (cid == BNX2X_FCOE_ETH_CID)
4391 return &bnx2x_fcoe(bp, q_obj);
4392 else
4393#endif
6383c0b3 4394 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
619c5cb6
VZ		 4395}
4396
523224a3
DK		 4397static void bnx2x_eq_int(struct bnx2x *bp)
4398{
4399 u16 hw_cons, sw_cons, sw_prod;
4400 union event_ring_elem *elem;
4401 u32 cid;
4402 u8 opcode;
4403 int spqe_cnt = 0;
619c5cb6
VZ		 4404 struct bnx2x_queue_sp_obj *q_obj;
4405 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4406 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 4407
4408 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4409
4410 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4411 * when we get the the next-page we nned to adjust so the loop
4412 * condition below will be met. The next element is the size of a
4413 * regular element and hence incrementing by 1
4414 */
4415 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4416 hw_cons++;
4417
25985edc 4418 /* This function may never run in parallel with itself for a
523224a3
DK		 4419 * specific bp, thus there is no need in "paired" read memory
4420 * barrier here.
4421 */
4422 sw_cons = bp->eq_cons;
4423 sw_prod = bp->eq_prod;
4424
d6cae238 4425 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 4426 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 4427
4428 for (; sw_cons != hw_cons;
4429 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4430
4431
4432 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4433
4434 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4435 opcode = elem->message.opcode;
4436
4437
4438 /* handle eq element */
4439 switch (opcode) {
4440 case EVENT_RING_OPCODE_STAT_QUERY:
619c5cb6
VZ		 4441 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4442 bp->stats_comp++);
523224a3 4443 /* nothing to do with stats comp */
d6cae238 4444 goto next_spqe;
523224a3
DK		 4445
4446 case EVENT_RING_OPCODE_CFC_DEL:
4447 /* handle according to cid range */
4448 /*
4449 * we may want to verify here that the bp state is
4450 * HALTING
4451 */
d6cae238 4452 DP(BNX2X_MSG_SP,
523224a3
DK		 4453 "got delete ramrod for MULTI[%d]\n", cid);
4454#ifdef BCM_CNIC
4455 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4456 goto next_spqe;
4457#endif
619c5cb6
VZ		 4458 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4459
4460 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4461 break;
4462
4463
523224a3
DK		 4464
4465 goto next_spqe;
e4901dde
VZ		 4466
4467 case EVENT_RING_OPCODE_STOP_TRAFFIC:
d6cae238 4468 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
6debea87
DK		 4469 if (f_obj->complete_cmd(bp, f_obj,
4470 BNX2X_F_CMD_TX_STOP))
4471 break;
e4901dde
VZ		 4472 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4473 goto next_spqe;
619c5cb6 4474
e4901dde 4475 case EVENT_RING_OPCODE_START_TRAFFIC:
d6cae238 4476 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
6debea87
DK		 4477 if (f_obj->complete_cmd(bp, f_obj,
4478 BNX2X_F_CMD_TX_START))
4479 break;
e4901dde
VZ		 4480 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4481 goto next_spqe;
619c5cb6 4482 case EVENT_RING_OPCODE_FUNCTION_START:
d6cae238 4483 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
619c5cb6
VZ		 4484 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4485 break;
4486
4487 goto next_spqe;
4488
4489 case EVENT_RING_OPCODE_FUNCTION_STOP:
d6cae238 4490 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 4491 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4492 break;
4493
4494 goto next_spqe;
523224a3
DK		 4495 }
4496
4497 switch (opcode | bp->state) {
619c5cb6
VZ		 4498 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4499 BNX2X_STATE_OPEN):
4500 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 4501 BNX2X_STATE_OPENING_WAIT4_PORT):
619c5cb6
VZ		 4502 cid = elem->message.data.eth_event.echo &
4503 BNX2X_SWCID_MASK;
d6cae238 4504 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
619c5cb6
VZ		 4505 cid);
4506 rss_raw->clear_pending(rss_raw);
523224a3
DK		 4507 break;
4508
619c5cb6
VZ		 4509 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4510 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4511 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 4512 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 4513 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4514 BNX2X_STATE_OPEN):
4515 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4516 BNX2X_STATE_DIAG):
4517 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4518 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4519 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
619c5cb6 4520 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 4521 break;
4522
619c5cb6
VZ		 4523 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4524 BNX2X_STATE_OPEN):
4525 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4526 BNX2X_STATE_DIAG):
4527 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4528 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4529 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 4530 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 4531 break;
4532
619c5cb6
VZ		 4533 case (EVENT_RING_OPCODE_FILTERS_RULES |
4534 BNX2X_STATE_OPEN):
4535 case (EVENT_RING_OPCODE_FILTERS_RULES |
4536 BNX2X_STATE_DIAG):
4537 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 4538 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 4539 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 4540 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 4541 break;
4542 default:
4543 /* unknown event log error and continue */
619c5cb6
VZ		 4544 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4545 elem->message.opcode, bp->state);
523224a3
DK		 4546 }
4547next_spqe:
4548 spqe_cnt++;
4549 } /* for */
4550
8fe23fbd 4551 smp_mb__before_atomic_inc();
6e30dd4e 4552 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 4553
4554 bp->eq_cons = sw_cons;
4555 bp->eq_prod = sw_prod;
4556 /* Make sure that above mem writes were issued towards the memory */
4557 smp_wmb();
4558
4559 /* update producer */
4560 bnx2x_update_eq_prod(bp, bp->eq_prod);
4561}
4562
a2fbb9ea
ET		 4563static void bnx2x_sp_task(struct work_struct *work)
4564{
1cf167f2 4565 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea
ET		 4566 u16 status;
4567
a2fbb9ea 4568 status = bnx2x_update_dsb_idx(bp);
34f80b04
EG		 4569/* if (status == 0) */
4570/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
a2fbb9ea 4571
cdaa7cb8 4572 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
a2fbb9ea 4573
877e9aa4 4574 /* HW attentions */
523224a3 4575 if (status & BNX2X_DEF_SB_ATT_IDX) {
a2fbb9ea 4576 bnx2x_attn_int(bp);
523224a3 4577 status &= ~BNX2X_DEF_SB_ATT_IDX;
cdaa7cb8
VZ		 4578 }
4579
523224a3
DK		 4580 /* SP events: STAT_QUERY and others */
4581 if (status & BNX2X_DEF_SB_IDX) {
ec6ba945
VZ		 4582#ifdef BCM_CNIC
4583 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 4584
ec6ba945 4585 if ((!NO_FCOE(bp)) &&
019dbb4c
VZ		 4586 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4587 /*
4588 * Prevent local bottom-halves from running as
4589 * we are going to change the local NAPI list.
4590 */
4591 local_bh_disable();
ec6ba945 4592 napi_schedule(&bnx2x_fcoe(bp, napi));
019dbb4c
VZ		 4593 local_bh_enable();
4594 }
ec6ba945 4595#endif
523224a3
DK		 4596 /* Handle EQ completions */
4597 bnx2x_eq_int(bp);
4598
4599 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4600 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4601
4602 status &= ~BNX2X_DEF_SB_IDX;
cdaa7cb8
VZ		 4603 }
4604
4605 if (unlikely(status))
4606 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4607 status);
a2fbb9ea 4608
523224a3
DK		 4609 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4610 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
a2fbb9ea
ET		 4611}
4612
9f6c9258 4613irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 4614{
4615 struct net_device *dev = dev_instance;
4616 struct bnx2x *bp = netdev_priv(dev);
4617
523224a3
DK		 4618 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4619 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 4620
4621#ifdef BNX2X_STOP_ON_ERROR
4622 if (unlikely(bp->panic))
4623 return IRQ_HANDLED;
4624#endif
4625
993ac7b5
MC		 4626#ifdef BCM_CNIC
4627 {
4628 struct cnic_ops *c_ops;
4629
4630 rcu_read_lock();
4631 c_ops = rcu_dereference(bp->cnic_ops);
4632 if (c_ops)
4633 c_ops->cnic_handler(bp->cnic_data, NULL);
4634 rcu_read_unlock();
4635 }
4636#endif
1cf167f2 4637 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
a2fbb9ea
ET		 4638
4639 return IRQ_HANDLED;
4640}
4641
4642/* end of slow path */
4643
619c5cb6
VZ		 4644
4645void bnx2x_drv_pulse(struct bnx2x *bp)
4646{
4647 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4648 bp->fw_drv_pulse_wr_seq);
4649}
4650
4651
a2fbb9ea
ET		 4652static void bnx2x_timer(unsigned long data)
4653{
6383c0b3 4654 u8 cos;
a2fbb9ea
ET		 4655 struct bnx2x *bp = (struct bnx2x *) data;
4656
4657 if (!netif_running(bp->dev))
4658 return;
4659
a2fbb9ea
ET		 4660 if (poll) {
4661 struct bnx2x_fastpath *fp = &bp->fp[0];
a2fbb9ea 4662
6383c0b3
AE		 4663 for_each_cos_in_tx_queue(fp, cos)
4664 bnx2x_tx_int(bp, &fp->txdata[cos]);
b8ee8328 4665 bnx2x_rx_int(fp, 1000);
a2fbb9ea
ET		 4666 }
4667
34f80b04 4668 if (!BP_NOMCP(bp)) {
f2e0899f 4669 int mb_idx = BP_FW_MB_IDX(bp);
a2fbb9ea
ET		 4670 u32 drv_pulse;
4671 u32 mcp_pulse;
4672
4673 ++bp->fw_drv_pulse_wr_seq;
4674 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4675 /* TBD - add SYSTEM_TIME */
4676 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 4677 bnx2x_drv_pulse(bp);
a2fbb9ea 4678
f2e0899f 4679 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 4680 MCP_PULSE_SEQ_MASK);
4681 /* The delta between driver pulse and mcp response
4682 * should be 1 (before mcp response) or 0 (after mcp response)
4683 */
4684 if ((drv_pulse != mcp_pulse) &&
4685 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4686 /* someone lost a heartbeat... */
4687 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4688 drv_pulse, mcp_pulse);
4689 }
4690 }
4691
f34d28ea 4692 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 4693 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 4694
a2fbb9ea
ET		 4695 mod_timer(&bp->timer, jiffies + bp->current_interval);
4696}
4697
4698/* end of Statistics */
4699
4700/* nic init */
4701
4702/*
4703 * nic init service functions
4704 */
4705
523224a3 4706static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 4707{
523224a3
DK		 4708 u32 i;
4709 if (!(len%4) && !(addr%4))
4710 for (i = 0; i < len; i += 4)
4711 REG_WR(bp, addr + i, fill);
4712 else
4713 for (i = 0; i < len; i++)
4714 REG_WR8(bp, addr + i, fill);
34f80b04 4715
34f80b04
EG		 4716}
4717
523224a3
DK		 4718/* helper: writes FP SP data to FW - data_size in dwords */
4719static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4720 int fw_sb_id,
4721 u32 *sb_data_p,
4722 u32 data_size)
34f80b04 4723{
a2fbb9ea 4724 int index;
523224a3
DK		 4725 for (index = 0; index < data_size; index++)
4726 REG_WR(bp, BAR_CSTRORM_INTMEM +
4727 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4728 sizeof(u32)*index,
4729 *(sb_data_p + index));
4730}
a2fbb9ea 4731
523224a3
DK		 4732static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4733{
4734 u32 *sb_data_p;
4735 u32 data_size = 0;
f2e0899f 4736 struct hc_status_block_data_e2 sb_data_e2;
523224a3 4737 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 4738
523224a3 4739 /* disable the function first */
619c5cb6 4740 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4741 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4742 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 4743 sb_data_e2.common.p_func.vf_valid = false;
4744 sb_data_p = (u32 *)&sb_data_e2;
4745 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4746 } else {
4747 memset(&sb_data_e1x, 0,
4748 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4749 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 4750 sb_data_e1x.common.p_func.vf_valid = false;
4751 sb_data_p = (u32 *)&sb_data_e1x;
4752 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4753 }
523224a3 4754 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 4755
523224a3
DK		 4756 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4757 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4758 CSTORM_STATUS_BLOCK_SIZE);
4759 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4760 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4761 CSTORM_SYNC_BLOCK_SIZE);
4762}
34f80b04 4763
523224a3
DK		 4764/* helper: writes SP SB data to FW */
4765static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4766 struct hc_sp_status_block_data *sp_sb_data)
4767{
4768 int func = BP_FUNC(bp);
4769 int i;
4770 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4771 REG_WR(bp, BAR_CSTRORM_INTMEM +
4772 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4773 i*sizeof(u32),
4774 *((u32 *)sp_sb_data + i));
34f80b04
EG		 4775}
4776
523224a3 4777static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 4778{
4779 int func = BP_FUNC(bp);
523224a3
DK		 4780 struct hc_sp_status_block_data sp_sb_data;
4781 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 4782
619c5cb6 4783 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 4784 sp_sb_data.p_func.vf_valid = false;
4785
4786 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4787
4788 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4789 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4790 CSTORM_SP_STATUS_BLOCK_SIZE);
4791 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4792 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4793 CSTORM_SP_SYNC_BLOCK_SIZE);
4794
4795}
4796
4797
4798static inline
4799void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4800 int igu_sb_id, int igu_seg_id)
4801{
4802 hc_sm->igu_sb_id = igu_sb_id;
4803 hc_sm->igu_seg_id = igu_seg_id;
4804 hc_sm->timer_value = 0xFF;
4805 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 4806}
4807
150966ad
AE		 4808
4809/* allocates state machine ids. */
4810static inline
4811void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4812{
4813 /* zero out state machine indices */
4814 /* rx indices */
4815 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4816
4817 /* tx indices */
4818 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4819 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4820 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4821 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4822
4823 /* map indices */
4824 /* rx indices */
4825 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4826 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4827
4828 /* tx indices */
4829 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4830 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4831 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4832 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4833 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4834 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4835 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4836 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4837}
4838
8d96286a 4839static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 4840 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 4841{
523224a3
DK		 4842 int igu_seg_id;
4843
f2e0899f 4844 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 4845 struct hc_status_block_data_e1x sb_data_e1x;
4846 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 4847 int data_size;
4848 u32 *sb_data_p;
4849
f2e0899f
DK		 4850 if (CHIP_INT_MODE_IS_BC(bp))
4851 igu_seg_id = HC_SEG_ACCESS_NORM;
4852 else
4853 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 4854
4855 bnx2x_zero_fp_sb(bp, fw_sb_id);
4856
619c5cb6 4857 if (!CHIP_IS_E1x(bp)) {
f2e0899f 4858 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 4859 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 4860 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4861 sb_data_e2.common.p_func.vf_id = vfid;
4862 sb_data_e2.common.p_func.vf_valid = vf_valid;
4863 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4864 sb_data_e2.common.same_igu_sb_1b = true;
4865 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4866 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4867 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 4868 sb_data_p = (u32 *)&sb_data_e2;
4869 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 4870 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 4871 } else {
4872 memset(&sb_data_e1x, 0,
4873 sizeof(struct hc_status_block_data_e1x));
619c5cb6 4874 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 4875 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4876 sb_data_e1x.common.p_func.vf_id = 0xff;
4877 sb_data_e1x.common.p_func.vf_valid = false;
4878 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4879 sb_data_e1x.common.same_igu_sb_1b = true;
4880 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4881 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4882 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 4883 sb_data_p = (u32 *)&sb_data_e1x;
4884 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 4885 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 4886 }
523224a3
DK		 4887
4888 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4889 igu_sb_id, igu_seg_id);
4890 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4891 igu_sb_id, igu_seg_id);
4892
4893 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4894
4895 /* write indecies to HW */
4896 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4897}
4898
619c5cb6 4899static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 4900 u16 tx_usec, u16 rx_usec)
4901{
6383c0b3 4902 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 4903 false, rx_usec);
6383c0b3
AE		 4904 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4905 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4906 tx_usec);
4907 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4908 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4909 tx_usec);
4910 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4911 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4912 tx_usec);
523224a3 4913}
f2e0899f 4914
523224a3
DK		 4915static void bnx2x_init_def_sb(struct bnx2x *bp)
4916{
4917 struct host_sp_status_block *def_sb = bp->def_status_blk;
4918 dma_addr_t mapping = bp->def_status_blk_mapping;
4919 int igu_sp_sb_index;
4920 int igu_seg_id;
34f80b04
EG		 4921 int port = BP_PORT(bp);
4922 int func = BP_FUNC(bp);
f2eaeb58 4923 int reg_offset, reg_offset_en5;
a2fbb9ea 4924 u64 section;
523224a3
DK		 4925 int index;
4926 struct hc_sp_status_block_data sp_sb_data;
4927 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4928
f2e0899f
DK		 4929 if (CHIP_INT_MODE_IS_BC(bp)) {
4930 igu_sp_sb_index = DEF_SB_IGU_ID;
4931 igu_seg_id = HC_SEG_ACCESS_DEF;
4932 } else {
4933 igu_sp_sb_index = bp->igu_dsb_id;
4934 igu_seg_id = IGU_SEG_ACCESS_DEF;
4935 }
a2fbb9ea
ET		 4936
4937 /* ATTN */
523224a3 4938 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 4939 atten_status_block);
523224a3 4940 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 4941
49d66772
ET		 4942 bp->attn_state = 0;
4943
a2fbb9ea
ET		 4944 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4945 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 4946 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
4947 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 4948 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 4949 int sindex;
4950 /* take care of sig[0]..sig[4] */
4951 for (sindex = 0; sindex < 4; sindex++)
4952 bp->attn_group[index].sig[sindex] =
4953 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 4954
619c5cb6 4955 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 4956 /*
4957 * enable5 is separate from the rest of the registers,
4958 * and therefore the address skip is 4
4959 * and not 16 between the different groups
4960 */
4961 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 4962 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 4963 else
4964 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 4965 }
4966
f2e0899f
DK		 4967 if (bp->common.int_block == INT_BLOCK_HC) {
4968 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4969 HC_REG_ATTN_MSG0_ADDR_L);
4970
4971 REG_WR(bp, reg_offset, U64_LO(section));
4972 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 4973 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4974 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4975 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4976 }
a2fbb9ea 4977
523224a3
DK		 4978 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4979 sp_sb);
a2fbb9ea 4980
523224a3 4981 bnx2x_zero_sp_sb(bp);
a2fbb9ea 4982
619c5cb6 4983 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 4984 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4985 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4986 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4987 sp_sb_data.igu_seg_id = igu_seg_id;
4988 sp_sb_data.p_func.pf_id = func;
f2e0899f 4989 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 4990 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 4991
523224a3 4992 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 4993
523224a3 4994 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 4995}
4996
9f6c9258 4997void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 4998{
a2fbb9ea
ET		 4999 int i;
5000
ec6ba945 5001 for_each_eth_queue(bp, i)
523224a3 5002 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 5003 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 5004}
5005
a2fbb9ea
ET		 5006static void bnx2x_init_sp_ring(struct bnx2x *bp)
5007{
a2fbb9ea 5008 spin_lock_init(&bp->spq_lock);
6e30dd4e 5009 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 5010
a2fbb9ea 5011 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 5012 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5013 bp->spq_prod_bd = bp->spq;
5014 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 5015}
5016
523224a3 5017static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 5018{
5019 int i;
523224a3
DK		 5020 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5021 union event_ring_elem *elem =
5022 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 5023
523224a3
DK		 5024 elem->next_page.addr.hi =
5025 cpu_to_le32(U64_HI(bp->eq_mapping +
5026 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5027 elem->next_page.addr.lo =
5028 cpu_to_le32(U64_LO(bp->eq_mapping +
5029 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 5030 }
523224a3
DK		 5031 bp->eq_cons = 0;
5032 bp->eq_prod = NUM_EQ_DESC;
5033 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6e30dd4e
VZ		 5034 /* we want a warning message before it gets rought... */
5035 atomic_set(&bp->eq_spq_left,
5036 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 5037}
5038
619c5cb6
VZ		 5039
5040/* called with netif_addr_lock_bh() */
5041void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5042 unsigned long rx_mode_flags,
5043 unsigned long rx_accept_flags,
5044 unsigned long tx_accept_flags,
5045 unsigned long ramrod_flags)
ab532cf3 5046{
619c5cb6
VZ		 5047 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5048 int rc;
5049
5050 memset(&ramrod_param, 0, sizeof(ramrod_param));
5051
5052 /* Prepare ramrod parameters */
5053 ramrod_param.cid = 0;
5054 ramrod_param.cl_id = cl_id;
5055 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5056 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 5057
619c5cb6
VZ		 5058 ramrod_param.pstate = &bp->sp_state;
5059 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 5060
619c5cb6
VZ		 5061 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5062 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5063
5064 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5065
5066 ramrod_param.ramrod_flags = ramrod_flags;
5067 ramrod_param.rx_mode_flags = rx_mode_flags;
5068
5069 ramrod_param.rx_accept_flags = rx_accept_flags;
5070 ramrod_param.tx_accept_flags = tx_accept_flags;
5071
5072 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5073 if (rc < 0) {
5074 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5075 return;
5076 }
a2fbb9ea
ET		 5077}
5078
619c5cb6
VZ		 5079/* called with netif_addr_lock_bh() */
5080void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
471de716 5081{
619c5cb6
VZ		 5082 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5083 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
471de716 5084
619c5cb6
VZ		 5085#ifdef BCM_CNIC
5086 if (!NO_FCOE(bp))
5087
5088 /* Configure rx_mode of FCoE Queue */
5089 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5090#endif
5091
5092 switch (bp->rx_mode) {
5093 case BNX2X_RX_MODE_NONE:
5094 /*
5095 * 'drop all' supersedes any accept flags that may have been
5096 * passed to the function.
5097 */
5098 break;
5099 case BNX2X_RX_MODE_NORMAL:
5100 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5101 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5102 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5103
5104 /* internal switching mode */
5105 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5106 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5107 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5108
5109 break;
5110 case BNX2X_RX_MODE_ALLMULTI:
5111 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5112 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5113 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5114
5115 /* internal switching mode */
5116 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5117 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5118 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5119
5120 break;
5121 case BNX2X_RX_MODE_PROMISC:
5122 /* According to deffinition of SI mode, iface in promisc mode
5123 * should receive matched and unmatched (in resolution of port)
5124 * unicast packets.
5125 */
5126 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5127 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5128 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5129 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5130
5131 /* internal switching mode */
5132 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5133 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5134
5135 if (IS_MF_SI(bp))
5136 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5137 else
5138 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5139
5140 break;
5141 default:
5142 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5143 return;
5144 }
de832a55 5145
619c5cb6
VZ		 5146 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5147 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5148 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
34f80b04
EG		 5149 }
5150
619c5cb6
VZ		 5151 __set_bit(RAMROD_RX, &ramrod_flags);
5152 __set_bit(RAMROD_TX, &ramrod_flags);
5153
5154 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5155 tx_accept_flags, ramrod_flags);
5156}
5157
5158static void bnx2x_init_internal_common(struct bnx2x *bp)
5159{
5160 int i;
5161
0793f83f
DK		 5162 if (IS_MF_SI(bp))
5163 /*
5164 * In switch independent mode, the TSTORM needs to accept
5165 * packets that failed classification, since approximate match
5166 * mac addresses aren't written to NIG LLH
5167 */
5168 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5169 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
619c5cb6
VZ		 5170 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5171 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5172 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
0793f83f 5173
523224a3
DK		 5174 /* Zero this manually as its initialization is
5175 currently missing in the initTool */
5176 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 5177 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 5178 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 5179 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 5180 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5181 CHIP_INT_MODE_IS_BC(bp) ?
5182 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5183 }
523224a3 5184}
8a1c38d1 5185
471de716
EG		 5186static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5187{
5188 switch (load_code) {
5189 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 5190 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 5191 bnx2x_init_internal_common(bp);
5192 /* no break */
5193
5194 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 5195 /* nothing to do */
471de716
EG		 5196 /* no break */
5197
5198 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 5199 /* internal memory per function is
5200 initialized inside bnx2x_pf_init */
471de716
EG		 5201 break;
5202
5203 default:
5204 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5205 break;
5206 }
5207}
5208
619c5cb6 5209static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 5210{
6383c0b3 5211 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
619c5cb6 5212}
523224a3 5213
619c5cb6
VZ		 5214static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5215{
6383c0b3 5216 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
619c5cb6
VZ		 5217}
5218
5219static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5220{
5221 if (CHIP_IS_E1x(fp->bp))
5222 return BP_L_ID(fp->bp) + fp->index;
5223 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5224 return bnx2x_fp_igu_sb_id(fp);
5225}
5226
6383c0b3 5227static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 5228{
5229 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 5230 u8 cos;
619c5cb6 5231 unsigned long q_type = 0;
6383c0b3 5232 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 5233 fp->rx_queue = fp_idx;
b3b83c3f 5234 fp->cid = fp_idx;
619c5cb6
VZ		 5235 fp->cl_id = bnx2x_fp_cl_id(fp);
5236 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5237 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 5238 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 5239 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5240
523224a3 5241 /* init shortcut */
619c5cb6 5242 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
523224a3
DK		 5243 /* Setup SB indicies */
5244 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 5245
619c5cb6
VZ		 5246 /* Configure Queue State object */
5247 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5248 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 5249
5250 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5251
5252 /* init tx data */
5253 for_each_cos_in_tx_queue(fp, cos) {
5254 bnx2x_init_txdata(bp, &fp->txdata[cos],
5255 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5256 FP_COS_TO_TXQ(fp, cos),
5257 BNX2X_TX_SB_INDEX_BASE + cos);
5258 cids[cos] = fp->txdata[cos].cid;
5259 }
5260
5261 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5262 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5263 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 5264
5265 /**
5266 * Configure classification DBs: Always enable Tx switching
5267 */
5268 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5269
523224a3
DK		 5270 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5271 "cl_id %d fw_sb %d igu_sb %d\n",
619c5cb6 5272 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
523224a3
DK		 5273 fp->igu_sb_id);
5274 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5275 fp->fw_sb_id, fp->igu_sb_id);
5276
5277 bnx2x_update_fpsb_idx(fp);
5278}
5279
9f6c9258 5280void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
a2fbb9ea
ET		 5281{
5282 int i;
5283
ec6ba945 5284 for_each_eth_queue(bp, i)
6383c0b3 5285 bnx2x_init_eth_fp(bp, i);
37b091ba 5286#ifdef BCM_CNIC
ec6ba945
VZ		 5287 if (!NO_FCOE(bp))
5288 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 5289
5290 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5291 BNX2X_VF_ID_INVALID, false,
619c5cb6 5292 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 5293
37b091ba 5294#endif
a2fbb9ea 5295
020c7e3f
YR		 5296 /* Initialize MOD_ABS interrupts */
5297 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5298 bp->common.shmem_base, bp->common.shmem2_base,
5299 BP_PORT(bp));
16119785
EG		 5300 /* ensure status block indices were read */
5301 rmb();
5302
523224a3 5303 bnx2x_init_def_sb(bp);
5c862848 5304 bnx2x_update_dsb_idx(bp);
a2fbb9ea 5305 bnx2x_init_rx_rings(bp);
523224a3 5306 bnx2x_init_tx_rings(bp);
a2fbb9ea 5307 bnx2x_init_sp_ring(bp);
523224a3 5308 bnx2x_init_eq_ring(bp);
471de716 5309 bnx2x_init_internal(bp, load_code);
523224a3 5310 bnx2x_pf_init(bp);
0ef00459
EG		 5311 bnx2x_stats_init(bp);
5312
0ef00459
EG		 5313 /* flush all before enabling interrupts */
5314 mb();
5315 mmiowb();
5316
615f8fd9 5317 bnx2x_int_enable(bp);
eb8da205
EG		 5318
5319 /* Check for SPIO5 */
5320 bnx2x_attn_int_deasserted0(bp,
5321 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5322 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 5323}
5324
5325/* end of nic init */
5326
5327/*
5328 * gzip service functions
5329 */
5330
5331static int bnx2x_gunzip_init(struct bnx2x *bp)
5332{
1a983142
FT		 5333 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5334 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 5335 if (bp->gunzip_buf == NULL)
5336 goto gunzip_nomem1;
5337
5338 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5339 if (bp->strm == NULL)
5340 goto gunzip_nomem2;
5341
7ab24bfd 5342 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 5343 if (bp->strm->workspace == NULL)
5344 goto gunzip_nomem3;
5345
5346 return 0;
5347
5348gunzip_nomem3:
5349 kfree(bp->strm);
5350 bp->strm = NULL;
5351
5352gunzip_nomem2:
1a983142
FT		 5353 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5354 bp->gunzip_mapping);
a2fbb9ea
ET		 5355 bp->gunzip_buf = NULL;
5356
5357gunzip_nomem1:
cdaa7cb8
VZ		 5358 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5359 " un-compression\n");
a2fbb9ea
ET		 5360 return -ENOMEM;
5361}
5362
5363static void bnx2x_gunzip_end(struct bnx2x *bp)
5364{
b3b83c3f 5365 if (bp->strm) {
7ab24bfd 5366 vfree(bp->strm->workspace);
b3b83c3f
DK		 5367 kfree(bp->strm);
5368 bp->strm = NULL;
5369 }
a2fbb9ea
ET		 5370
5371 if (bp->gunzip_buf) {
1a983142
FT		 5372 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5373 bp->gunzip_mapping);
a2fbb9ea
ET		 5374 bp->gunzip_buf = NULL;
5375 }
5376}
5377
94a78b79 5378static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 5379{
5380 int n, rc;
5381
5382 /* check gzip header */
94a78b79
VZ		 5383 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5384 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 5385 return -EINVAL;
94a78b79 5386 }
a2fbb9ea
ET		 5387
5388 n = 10;
5389
34f80b04 5390#define FNAME 0x8
a2fbb9ea
ET		 5391
5392 if (zbuf[3] & FNAME)
5393 while ((zbuf[n++] != 0) && (n < len));
5394
94a78b79 5395 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 5396 bp->strm->avail_in = len - n;
5397 bp->strm->next_out = bp->gunzip_buf;
5398 bp->strm->avail_out = FW_BUF_SIZE;
5399
5400 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5401 if (rc != Z_OK)
5402 return rc;
5403
5404 rc = zlib_inflate(bp->strm, Z_FINISH);
5405 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 5406 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5407 bp->strm->msg);
a2fbb9ea
ET		 5408
5409 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5410 if (bp->gunzip_outlen & 0x3)
cdaa7cb8
VZ		 5411 netdev_err(bp->dev, "Firmware decompression error:"
5412 " gunzip_outlen (%d) not aligned\n",
5413 bp->gunzip_outlen);
a2fbb9ea
ET		 5414 bp->gunzip_outlen >>= 2;
5415
5416 zlib_inflateEnd(bp->strm);
5417
5418 if (rc == Z_STREAM_END)
5419 return 0;
5420
5421 return rc;
5422}
5423
5424/* nic load/unload */
5425
5426/*
34f80b04 5427 * General service functions
a2fbb9ea
ET		 5428 */
5429
5430/* send a NIG loopback debug packet */
5431static void bnx2x_lb_pckt(struct bnx2x *bp)
5432{
a2fbb9ea 5433 u32 wb_write[3];
a2fbb9ea
ET		 5434
5435 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 5436 wb_write[0] = 0x55555555;
5437 wb_write[1] = 0x55555555;
34f80b04 5438 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 5439 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5440
5441 /* NON-IP protocol */
a2fbb9ea
ET		 5442 wb_write[0] = 0x09000000;
5443 wb_write[1] = 0x55555555;
34f80b04 5444 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 5445 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 5446}
5447
5448/* some of the internal memories
5449 * are not directly readable from the driver
5450 * to test them we send debug packets
5451 */
5452static int bnx2x_int_mem_test(struct bnx2x *bp)
5453{
5454 int factor;
5455 int count, i;
5456 u32 val = 0;
5457
ad8d3948 5458 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 5459 factor = 120;
ad8d3948
EG		 5460 else if (CHIP_REV_IS_EMUL(bp))
5461 factor = 200;
5462 else
a2fbb9ea 5463 factor = 1;
a2fbb9ea 5464
a2fbb9ea
ET		 5465 /* Disable inputs of parser neighbor blocks */
5466 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5467 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5468 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5469 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5470
5471 /* Write 0 to parser credits for CFC search request */
5472 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5473
5474 /* send Ethernet packet */
5475 bnx2x_lb_pckt(bp);
5476
5477 /* TODO do i reset NIG statistic? */
5478 /* Wait until NIG register shows 1 packet of size 0x10 */
5479 count = 1000 * factor;
5480 while (count) {
34f80b04 5481
a2fbb9ea
ET		 5482 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5483 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5484 if (val == 0x10)
5485 break;
5486
5487 msleep(10);
5488 count--;
5489 }
5490 if (val != 0x10) {
5491 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5492 return -1;
5493 }
5494
5495 /* Wait until PRS register shows 1 packet */
5496 count = 1000 * factor;
5497 while (count) {
5498 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 5499 if (val == 1)
5500 break;
5501
5502 msleep(10);
5503 count--;
5504 }
5505 if (val != 0x1) {
5506 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5507 return -2;
5508 }
5509
5510 /* Reset and init BRB, PRS */
34f80b04 5511 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 5512 msleep(50);
34f80b04 5513 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 5514 msleep(50);
619c5cb6
VZ		 5515 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5516 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 5517
5518 DP(NETIF_MSG_HW, "part2\n");
5519
5520 /* Disable inputs of parser neighbor blocks */
5521 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5522 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5523 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 5524 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 5525
5526 /* Write 0 to parser credits for CFC search request */
5527 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5528
5529 /* send 10 Ethernet packets */
5530 for (i = 0; i < 10; i++)
5531 bnx2x_lb_pckt(bp);
5532
5533 /* Wait until NIG register shows 10 + 1
5534 packets of size 11*0x10 = 0xb0 */
5535 count = 1000 * factor;
5536 while (count) {
34f80b04 5537
a2fbb9ea
ET		 5538 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5539 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 5540 if (val == 0xb0)
5541 break;
5542
5543 msleep(10);
5544 count--;
5545 }
5546 if (val != 0xb0) {
5547 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5548 return -3;
5549 }
5550
5551 /* Wait until PRS register shows 2 packets */
5552 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5553 if (val != 2)
5554 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5555
5556 /* Write 1 to parser credits for CFC search request */
5557 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5558
5559 /* Wait until PRS register shows 3 packets */
5560 msleep(10 * factor);
5561 /* Wait until NIG register shows 1 packet of size 0x10 */
5562 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5563 if (val != 3)
5564 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5565
5566 /* clear NIG EOP FIFO */
5567 for (i = 0; i < 11; i++)
5568 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5569 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5570 if (val != 1) {
5571 BNX2X_ERR("clear of NIG failed\n");
5572 return -4;
5573 }
5574
5575 /* Reset and init BRB, PRS, NIG */
5576 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5577 msleep(50);
5578 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5579 msleep(50);
619c5cb6
VZ		 5580 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5581 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
37b091ba 5582#ifndef BCM_CNIC
a2fbb9ea
ET		 5583 /* set NIC mode */
5584 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5585#endif
5586
5587 /* Enable inputs of parser neighbor blocks */
5588 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5589 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5590 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 5591 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 5592
5593 DP(NETIF_MSG_HW, "done\n");
5594
5595 return 0; /* OK */
5596}
5597
4a33bc03 5598static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea
ET		 5599{
5600 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 5601 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5602 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5603 else
5604 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 5605 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5606 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 5607 /*
5608 * mask read length error interrupts in brb for parser
5609 * (parsing unit and 'checksum and crc' unit)
5610 * these errors are legal (PU reads fixed length and CAC can cause
5611 * read length error on truncated packets)
5612 */
5613 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 5614 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5615 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5616 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5617 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5618 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 5619/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5620/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5621 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5622 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5623 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 5624/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5625/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 5626 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5627 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5628 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5629 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 5630/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5631/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 5632
34f80b04
EG		 5633 if (CHIP_REV_IS_FPGA(bp))
5634 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
619c5cb6 5635 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5636 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5637 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5638 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5639 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5640 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5641 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
34f80b04
EG		 5642 else
5643 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
a2fbb9ea
ET		 5644 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5645 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5646 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 5647/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 5648
5649 if (!CHIP_IS_E1x(bp))
5650 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5651 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5652
a2fbb9ea
ET		 5653 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5654 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 5655/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 5656 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 5657}
5658
81f75bbf
EG		 5659static void bnx2x_reset_common(struct bnx2x *bp)
5660{
619c5cb6
VZ		 5661 u32 val = 0x1400;
5662
81f75bbf
EG		 5663 /* reset_common */
5664 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5665 0xd3ffff7f);
619c5cb6
VZ		 5666
5667 if (CHIP_IS_E3(bp)) {
5668 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5669 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5670 }
5671
5672 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5673}
5674
5675static void bnx2x_setup_dmae(struct bnx2x *bp)
5676{
5677 bp->dmae_ready = 0;
5678 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 5679}
5680
573f2035
EG		 5681static void bnx2x_init_pxp(struct bnx2x *bp)
5682{
5683 u16 devctl;
5684 int r_order, w_order;
5685
5686 pci_read_config_word(bp->pdev,
b6c2f86e 5687 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 5688 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5689 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5690 if (bp->mrrs == -1)
5691 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5692 else {
5693 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5694 r_order = bp->mrrs;
5695 }
5696
5697 bnx2x_init_pxp_arb(bp, r_order, w_order);
5698}
fd4ef40d
EG		 5699
5700static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5701{
2145a920 5702 int is_required;
fd4ef40d 5703 u32 val;
2145a920 5704 int port;
fd4ef40d 5705
2145a920
VZ		 5706 if (BP_NOMCP(bp))
5707 return;
5708
5709 is_required = 0;
fd4ef40d
EG		 5710 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5711 SHARED_HW_CFG_FAN_FAILURE_MASK;
5712
5713 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5714 is_required = 1;
5715
5716 /*
5717 * The fan failure mechanism is usually related to the PHY type since
5718 * the power consumption of the board is affected by the PHY. Currently,
5719 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5720 */
5721 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5722 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 5723 is_required |=
d90d96ba
YR		 5724 bnx2x_fan_failure_det_req(
5725 bp,
5726 bp->common.shmem_base,
a22f0788 5727 bp->common.shmem2_base,
d90d96ba 5728 port);
fd4ef40d
EG		 5729 }
5730
5731 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5732
5733 if (is_required == 0)
5734 return;
5735
5736 /* Fan failure is indicated by SPIO 5 */
5737 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5738 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5739
5740 /* set to active low mode */
5741 val = REG_RD(bp, MISC_REG_SPIO_INT);
5742 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
cdaa7cb8 5743 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 5744 REG_WR(bp, MISC_REG_SPIO_INT, val);
5745
5746 /* enable interrupt to signal the IGU */
5747 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5748 val |= (1 << MISC_REGISTERS_SPIO_5);
5749 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5750}
5751
f2e0899f
DK		 5752static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5753{
5754 u32 offset = 0;
5755
5756 if (CHIP_IS_E1(bp))
5757 return;
5758 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5759 return;
5760
5761 switch (BP_ABS_FUNC(bp)) {
5762 case 0:
5763 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5764 break;
5765 case 1:
5766 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5767 break;
5768 case 2:
5769 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5770 break;
5771 case 3:
5772 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5773 break;
5774 case 4:
5775 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5776 break;
5777 case 5:
5778 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5779 break;
5780 case 6:
5781 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5782 break;
5783 case 7:
5784 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5785 break;
5786 default:
5787 return;
5788 }
5789
5790 REG_WR(bp, offset, pretend_func_num);
5791 REG_RD(bp, offset);
5792 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5793}
5794
c9ee9206 5795void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 5796{
5797 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5798 val &= ~IGU_PF_CONF_FUNC_EN;
5799
5800 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5801 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5802 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5803}
5804
619c5cb6
VZ		 5805static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5806{
5807 u32 shmem_base[2], shmem2_base[2];
5808 shmem_base[0] = bp->common.shmem_base;
5809 shmem2_base[0] = bp->common.shmem2_base;
5810 if (!CHIP_IS_E1x(bp)) {
5811 shmem_base[1] =
5812 SHMEM2_RD(bp, other_shmem_base_addr);
5813 shmem2_base[1] =
5814 SHMEM2_RD(bp, other_shmem2_base_addr);
5815 }
5816 bnx2x_acquire_phy_lock(bp);
5817 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5818 bp->common.chip_id);
5819 bnx2x_release_phy_lock(bp);
5820}
5821
5822/**
5823 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5824 *
5825 * @bp: driver handle
5826 */
5827static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 5828{
619c5cb6 5829 u32 val;
a2fbb9ea 5830
f2e0899f 5831 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 5832
2031bd3a
DK		 5833 /*
5834 * take the UNDI lock to protect undi_unload flow from accessing
5835 * registers while we're resetting the chip
5836 */
7a06a122 5837 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 5838
81f75bbf 5839 bnx2x_reset_common(bp);
34f80b04 5840 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 5841
619c5cb6
VZ		 5842 val = 0xfffc;
5843 if (CHIP_IS_E3(bp)) {
5844 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5845 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5846 }
5847 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5848
7a06a122 5849 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 5850
619c5cb6 5851 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 5852
619c5cb6
VZ		 5853 if (!CHIP_IS_E1x(bp)) {
5854 u8 abs_func_id;
f2e0899f
DK		 5855
5856 /**
5857 * 4-port mode or 2-port mode we need to turn of master-enable
5858 * for everyone, after that, turn it back on for self.
5859 * so, we disregard multi-function or not, and always disable
5860 * for all functions on the given path, this means 0,2,4,6 for
5861 * path 0 and 1,3,5,7 for path 1
5862 */
619c5cb6
VZ		 5863 for (abs_func_id = BP_PATH(bp);
5864 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5865 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 5866 REG_WR(bp,
5867 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5868 1);
5869 continue;
5870 }
5871
619c5cb6 5872 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 5873 /* clear pf enable */
5874 bnx2x_pf_disable(bp);
5875 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5876 }
5877 }
a2fbb9ea 5878
619c5cb6 5879 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 5880 if (CHIP_IS_E1(bp)) {
5881 /* enable HW interrupt from PXP on USDM overflow
5882 bit 16 on INT_MASK_0 */
5883 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5884 }
a2fbb9ea 5885
619c5cb6 5886 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 5887 bnx2x_init_pxp(bp);
a2fbb9ea
ET		 5888
5889#ifdef __BIG_ENDIAN
34f80b04
EG		 5890 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5891 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5892 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5893 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5894 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
8badd27a
EG		 5895 /* make sure this value is 0 */
5896 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
34f80b04
EG		 5897
5898/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5899 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5900 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5901 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5902 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
a2fbb9ea
ET		 5903#endif
5904
523224a3
DK		 5905 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5906
34f80b04
EG		 5907 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5908 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 5909
34f80b04
EG		 5910 /* let the HW do it's magic ... */
5911 msleep(100);
5912 /* finish PXP init */
5913 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5914 if (val != 1) {
5915 BNX2X_ERR("PXP2 CFG failed\n");
5916 return -EBUSY;
5917 }
5918 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5919 if (val != 1) {
5920 BNX2X_ERR("PXP2 RD_INIT failed\n");
5921 return -EBUSY;
5922 }
a2fbb9ea 5923
f2e0899f
DK		 5924 /* Timers bug workaround E2 only. We need to set the entire ILT to
5925 * have entries with value "0" and valid bit on.
5926 * This needs to be done by the first PF that is loaded in a path
5927 * (i.e. common phase)
5928 */
619c5cb6
VZ		 5929 if (!CHIP_IS_E1x(bp)) {
5930/* In E2 there is a bug in the timers block that can cause function 6 / 7
5931 * (i.e. vnic3) to start even if it is marked as "scan-off".
5932 * This occurs when a different function (func2,3) is being marked
5933 * as "scan-off". Real-life scenario for example: if a driver is being
5934 * load-unloaded while func6,7 are down. This will cause the timer to access
5935 * the ilt, translate to a logical address and send a request to read/write.
5936 * Since the ilt for the function that is down is not valid, this will cause
5937 * a translation error which is unrecoverable.
5938 * The Workaround is intended to make sure that when this happens nothing fatal
5939 * will occur. The workaround:
5940 * 1. First PF driver which loads on a path will:
5941 * a. After taking the chip out of reset, by using pretend,
5942 * it will write "0" to the following registers of
5943 * the other vnics.
5944 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5945 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5946 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5947 * And for itself it will write '1' to
5948 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5949 * dmae-operations (writing to pram for example.)
5950 * note: can be done for only function 6,7 but cleaner this
5951 * way.
5952 * b. Write zero+valid to the entire ILT.
5953 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5954 * VNIC3 (of that port). The range allocated will be the
5955 * entire ILT. This is needed to prevent ILT range error.
5956 * 2. Any PF driver load flow:
5957 * a. ILT update with the physical addresses of the allocated
5958 * logical pages.
5959 * b. Wait 20msec. - note that this timeout is needed to make
5960 * sure there are no requests in one of the PXP internal
5961 * queues with "old" ILT addresses.
5962 * c. PF enable in the PGLC.
5963 * d. Clear the was_error of the PF in the PGLC. (could have
5964 * occured while driver was down)
5965 * e. PF enable in the CFC (WEAK + STRONG)
5966 * f. Timers scan enable
5967 * 3. PF driver unload flow:
5968 * a. Clear the Timers scan_en.
5969 * b. Polling for scan_on=0 for that PF.
5970 * c. Clear the PF enable bit in the PXP.
5971 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5972 * e. Write zero+valid to all ILT entries (The valid bit must
5973 * stay set)
5974 * f. If this is VNIC 3 of a port then also init
5975 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5976 * to the last enrty in the ILT.
5977 *
5978 * Notes:
5979 * Currently the PF error in the PGLC is non recoverable.
5980 * In the future the there will be a recovery routine for this error.
5981 * Currently attention is masked.
5982 * Having an MCP lock on the load/unload process does not guarantee that
5983 * there is no Timer disable during Func6/7 enable. This is because the
5984 * Timers scan is currently being cleared by the MCP on FLR.
5985 * Step 2.d can be done only for PF6/7 and the driver can also check if
5986 * there is error before clearing it. But the flow above is simpler and
5987 * more general.
5988 * All ILT entries are written by zero+valid and not just PF6/7
5989 * ILT entries since in the future the ILT entries allocation for
5990 * PF-s might be dynamic.
5991 */
f2e0899f
DK		 5992 struct ilt_client_info ilt_cli;
5993 struct bnx2x_ilt ilt;
5994 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5995 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5996
b595076a 5997 /* initialize dummy TM client */
f2e0899f
DK		 5998 ilt_cli.start = 0;
5999 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6000 ilt_cli.client_num = ILT_CLIENT_TM;
6001
6002 /* Step 1: set zeroes to all ilt page entries with valid bit on
6003 * Step 2: set the timers first/last ilt entry to point
6004 * to the entire range to prevent ILT range error for 3rd/4th
619c5cb6 6005 * vnic (this code assumes existance of the vnic)
f2e0899f
DK		 6006 *
6007 * both steps performed by call to bnx2x_ilt_client_init_op()
6008 * with dummy TM client
6009 *
6010 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6011 * and his brother are split registers
6012 */
6013 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6014 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6015 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6016
6017 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6018 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6019 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6020 }
6021
6022
34f80b04
EG		 6023 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6024 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 6025
619c5cb6 6026 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6027 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6028 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 6029 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 6030
619c5cb6 6031 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 6032
6033 /* let the HW do it's magic ... */
6034 do {
6035 msleep(200);
6036 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6037 } while (factor-- && (val != 1));
6038
6039 if (val != 1) {
6040 BNX2X_ERR("ATC_INIT failed\n");
6041 return -EBUSY;
6042 }
6043 }
6044
619c5cb6 6045 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 6046
34f80b04
EG		 6047 /* clean the DMAE memory */
6048 bp->dmae_ready = 1;
619c5cb6
VZ		 6049 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6050
6051 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6052
6053 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6054
6055 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 6056
619c5cb6 6057 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 6058
34f80b04
EG		 6059 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6060 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6061 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6062 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6063
619c5cb6 6064 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 6065
f85582f8 6066
523224a3
DK		 6067 /* QM queues pointers table */
6068 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6069
34f80b04
EG		 6070 /* soft reset pulse */
6071 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6072 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 6073
37b091ba 6074#ifdef BCM_CNIC
619c5cb6 6075 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 6076#endif
a2fbb9ea 6077
619c5cb6 6078 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
523224a3 6079 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
619c5cb6 6080 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 6081 /* enable hw interrupt from doorbell Q */
6082 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 6083
619c5cb6 6084 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 6085
619c5cb6 6086 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 6087 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 6088
f2e0899f 6089 if (!CHIP_IS_E1(bp))
619c5cb6 6090 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 6091
619c5cb6
VZ		 6092 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6093 /* Bit-map indicating which L2 hdrs may appear
6094 * after the basic Ethernet header
6095 */
6096 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6097 bp->path_has_ovlan ? 7 : 6);
a2fbb9ea 6098
619c5cb6
VZ		 6099 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6100 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6101 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6102 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 6103
619c5cb6
VZ		 6104 if (!CHIP_IS_E1x(bp)) {
6105 /* reset VFC memories */
6106 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6107 VFC_MEMORIES_RST_REG_CAM_RST |
6108 VFC_MEMORIES_RST_REG_RAM_RST);
6109 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6110 VFC_MEMORIES_RST_REG_CAM_RST |
6111 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 6112
619c5cb6
VZ		 6113 msleep(20);
6114 }
a2fbb9ea 6115
619c5cb6
VZ		 6116 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6117 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6118 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6119 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 6120
34f80b04
EG		 6121 /* sync semi rtc */
6122 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6123 0x80000000);
6124 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6125 0x80000000);
a2fbb9ea 6126
619c5cb6
VZ		 6127 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6128 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6129 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 6130
619c5cb6
VZ		 6131 if (!CHIP_IS_E1x(bp))
6132 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6133 bp->path_has_ovlan ? 7 : 6);
f2e0899f 6134
34f80b04 6135 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 6136
619c5cb6
VZ		 6137 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6138
37b091ba
MC		 6139#ifdef BCM_CNIC
6140 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6141 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6142 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6143 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6144 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6145 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6146 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6147 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6148 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6149 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6150#endif
34f80b04 6151 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 6152
34f80b04
EG		 6153 if (sizeof(union cdu_context) != 1024)
6154 /* we currently assume that a context is 1024 bytes */
cdaa7cb8
VZ		 6155 dev_alert(&bp->pdev->dev, "please adjust the size "
6156 "of cdu_context(%ld)\n",
7995c64e 6157 (long)sizeof(union cdu_context));
a2fbb9ea 6158
619c5cb6 6159 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 6160 val = (4 << 24) + (0 << 12) + 1024;
6161 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 6162
619c5cb6 6163 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 6164 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 6165 /* enable context validation interrupt from CFC */
6166 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6167
6168 /* set the thresholds to prevent CFC/CDU race */
6169 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 6170
619c5cb6 6171 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 6172
619c5cb6 6173 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 6174 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6175
619c5cb6
VZ		 6176 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6177 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 6178
34f80b04
EG		 6179 /* Reset PCIE errors for debug */
6180 REG_WR(bp, 0x2814, 0xffffffff);
6181 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 6182
619c5cb6 6183 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6184 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6185 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6186 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6187 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6188 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6189 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6190 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6191 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6192 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6193 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6194 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6195 }
6196
619c5cb6 6197 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 6198 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 6199 /* in E3 this done in per-port section */
6200 if (!CHIP_IS_E3(bp))
6201 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 6202 }
619c5cb6
VZ		 6203 if (CHIP_IS_E1H(bp))
6204 /* not applicable for E2 (and above ...) */
6205 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 6206
6207 if (CHIP_REV_IS_SLOW(bp))
6208 msleep(200);
6209
6210 /* finish CFC init */
6211 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6212 if (val != 1) {
6213 BNX2X_ERR("CFC LL_INIT failed\n");
6214 return -EBUSY;
6215 }
6216 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6217 if (val != 1) {
6218 BNX2X_ERR("CFC AC_INIT failed\n");
6219 return -EBUSY;
6220 }
6221 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6222 if (val != 1) {
6223 BNX2X_ERR("CFC CAM_INIT failed\n");
6224 return -EBUSY;
6225 }
6226 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 6227
f2e0899f
DK		 6228 if (CHIP_IS_E1(bp)) {
6229 /* read NIG statistic
6230 to see if this is our first up since powerup */
6231 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6232 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 6233
f2e0899f
DK		 6234 /* do internal memory self test */
6235 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6236 BNX2X_ERR("internal mem self test failed\n");
6237 return -EBUSY;
6238 }
34f80b04
EG		 6239 }
6240
fd4ef40d
EG		 6241 bnx2x_setup_fan_failure_detection(bp);
6242
34f80b04
EG		 6243 /* clear PXP2 attentions */
6244 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 6245
4a33bc03 6246 bnx2x_enable_blocks_attention(bp);
c9ee9206 6247 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 6248
6bbca910 6249 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 6250 if (CHIP_IS_E1x(bp))
6251 bnx2x__common_init_phy(bp);
6bbca910
YR		 6252 } else
6253 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6254
34f80b04
EG		 6255 return 0;
6256}
a2fbb9ea 6257
619c5cb6
VZ		 6258/**
6259 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6260 *
6261 * @bp: driver handle
6262 */
6263static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6264{
6265 int rc = bnx2x_init_hw_common(bp);
6266
6267 if (rc)
6268 return rc;
6269
6270 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6271 if (!BP_NOMCP(bp))
6272 bnx2x__common_init_phy(bp);
6273
6274 return 0;
6275}
6276
523224a3 6277static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 6278{
6279 int port = BP_PORT(bp);
619c5cb6 6280 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 6281 u32 low, high;
34f80b04 6282 u32 val;
a2fbb9ea 6283
619c5cb6
VZ		 6284 bnx2x__link_reset(bp);
6285
cdaa7cb8 6286 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
34f80b04
EG		 6287
6288 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 6289
619c5cb6
VZ		 6290 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6291 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6292 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 6293
f2e0899f
DK		 6294 /* Timers bug workaround: disables the pf_master bit in pglue at
6295 * common phase, we need to enable it here before any dmae access are
6296 * attempted. Therefore we manually added the enable-master to the
6297 * port phase (it also happens in the function phase)
6298 */
619c5cb6 6299 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6300 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6301
619c5cb6
VZ		 6302 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6303 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6304 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6305 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6306
6307 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6308 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6309 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6310 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 6311
523224a3
DK		 6312 /* QM cid (connection) count */
6313 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 6314
523224a3 6315#ifdef BCM_CNIC
619c5cb6 6316 bnx2x_init_block(bp, BLOCK_TM, init_phase);
37b091ba
MC		 6317 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6318 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
a2fbb9ea 6319#endif
cdaa7cb8 6320
619c5cb6 6321 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f
DK		 6322
6323 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 6324 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6325
6326 if (IS_MF(bp))
6327 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6328 else if (bp->dev->mtu > 4096) {
6329 if (bp->flags & ONE_PORT_FLAG)
6330 low = 160;
6331 else {
6332 val = bp->dev->mtu;
6333 /* (24*1024 + val*4)/256 */
6334 low = 96 + (val/64) +
6335 ((val % 64) ? 1 : 0);
6336 }
6337 } else
6338 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6339 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 6340 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6341 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 6342 }
1c06328c 6343
619c5cb6
VZ		 6344 if (CHIP_MODE_IS_4_PORT(bp))
6345 REG_WR(bp, (BP_PORT(bp) ?
6346 BRB1_REG_MAC_GUARANTIED_1 :
6347 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 6348
ca00392c 6349
619c5cb6
VZ		 6350 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6351 if (CHIP_IS_E3B0(bp))
6352 /* Ovlan exists only if we are in multi-function +
6353 * switch-dependent mode, in switch-independent there
6354 * is no ovlan headers
6355 */
6356 REG_WR(bp, BP_PORT(bp) ?
6357 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6358 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6359 (bp->path_has_ovlan ? 7 : 6));
356e2385 6360
619c5cb6
VZ		 6361 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6362 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6363 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6364 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 6365
619c5cb6
VZ		 6366 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6367 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6368 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6369 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 6370
619c5cb6
VZ		 6371 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6372 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 6373
619c5cb6
VZ		 6374 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6375
6376 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6377 /* configure PBF to work without PAUSE mtu 9000 */
6378 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 6379
f2e0899f
DK		 6380 /* update threshold */
6381 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6382 /* update init credit */
6383 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 6384
f2e0899f
DK		 6385 /* probe changes */
6386 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6387 udelay(50);
6388 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6389 }
a2fbb9ea 6390
37b091ba 6391#ifdef BCM_CNIC
619c5cb6 6392 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
a2fbb9ea 6393#endif
619c5cb6
VZ		 6394 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6395 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 6396
6397 if (CHIP_IS_E1(bp)) {
6398 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6399 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6400 }
619c5cb6 6401 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 6402
619c5cb6 6403 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6404
619c5cb6 6405 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04
EG		 6406 /* init aeu_mask_attn_func_0/1:
6407 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6408 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6409 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 6410 val = IS_MF(bp) ? 0xF7 : 0x7;
6411 /* Enable DCBX attention for all but E1 */
6412 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6413 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 6414
619c5cb6
VZ		 6415 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6416
6417 if (!CHIP_IS_E1x(bp)) {
6418 /* Bit-map indicating which L2 hdrs may appear after the
6419 * basic Ethernet header
6420 */
6421 REG_WR(bp, BP_PORT(bp) ?
6422 NIG_REG_P1_HDRS_AFTER_BASIC :
6423 NIG_REG_P0_HDRS_AFTER_BASIC,
6424 IS_MF_SD(bp) ? 7 : 6);
6425
6426 if (CHIP_IS_E3(bp))
6427 REG_WR(bp, BP_PORT(bp) ?
6428 NIG_REG_LLH1_MF_MODE :
6429 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6430 }
6431 if (!CHIP_IS_E3(bp))
6432 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 6433
f2e0899f 6434 if (!CHIP_IS_E1(bp)) {
fb3bff17 6435 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 6436 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 6437 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 6438
619c5cb6 6439 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6440 val = 0;
6441 switch (bp->mf_mode) {
6442 case MULTI_FUNCTION_SD:
6443 val = 1;
6444 break;
6445 case MULTI_FUNCTION_SI:
6446 val = 2;
6447 break;
6448 }
6449
6450 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6451 NIG_REG_LLH0_CLS_TYPE), val);
6452 }
1c06328c
EG		 6453 {
6454 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6455 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6456 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6457 }
34f80b04
EG		 6458 }
6459
619c5cb6
VZ		 6460
6461 /* If SPIO5 is set to generate interrupts, enable it for this port */
6462 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6463 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
4d295db0
EG		 6464 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6465 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6466 val = REG_RD(bp, reg_addr);
f1410647 6467 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 6468 REG_WR(bp, reg_addr, val);
f1410647 6469 }
a2fbb9ea 6470
34f80b04
EG		 6471 return 0;
6472}
6473
34f80b04
EG		 6474static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6475{
6476 int reg;
6477
f2e0899f 6478 if (CHIP_IS_E1(bp))
34f80b04 6479 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 6480 else
6481 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04
EG		 6482
6483 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6484}
6485
f2e0899f
DK		 6486static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6487{
619c5cb6 6488 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 6489}
6490
6491static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6492{
6493 u32 i, base = FUNC_ILT_BASE(func);
6494 for (i = base; i < base + ILT_PER_FUNC; i++)
6495 bnx2x_ilt_wr(bp, i, 0);
6496}
6497
523224a3 6498static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 6499{
6500 int port = BP_PORT(bp);
6501 int func = BP_FUNC(bp);
619c5cb6 6502 int init_phase = PHASE_PF0 + func;
523224a3
DK		 6503 struct bnx2x_ilt *ilt = BP_ILT(bp);
6504 u16 cdu_ilt_start;
8badd27a 6505 u32 addr, val;
f4a66897
VZ		 6506 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6507 int i, main_mem_width;
34f80b04 6508
cdaa7cb8 6509 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
34f80b04 6510
619c5cb6
VZ		 6511 /* FLR cleanup - hmmm */
6512 if (!CHIP_IS_E1x(bp))
6513 bnx2x_pf_flr_clnup(bp);
6514
8badd27a 6515 /* set MSI reconfigure capability */
f2e0899f
DK		 6516 if (bp->common.int_block == INT_BLOCK_HC) {
6517 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6518 val = REG_RD(bp, addr);
6519 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6520 REG_WR(bp, addr, val);
6521 }
8badd27a 6522
619c5cb6
VZ		 6523 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6524 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6525
523224a3
DK		 6526 ilt = BP_ILT(bp);
6527 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 6528
523224a3
DK		 6529 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6530 ilt->lines[cdu_ilt_start + i].page =
6531 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6532 ilt->lines[cdu_ilt_start + i].page_mapping =
6533 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6534 /* cdu ilt pages are allocated manually so there's no need to
6535 set the size */
37b091ba 6536 }
523224a3 6537 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 6538
523224a3
DK		 6539#ifdef BCM_CNIC
6540 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
37b091ba 6541
523224a3
DK		 6542 /* T1 hash bits value determines the T1 number of entries */
6543 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6544#endif
37b091ba 6545
523224a3
DK		 6546#ifndef BCM_CNIC
6547 /* set NIC mode */
6548 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6549#endif /* BCM_CNIC */
37b091ba 6550
619c5cb6 6551 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6552 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6553
6554 /* Turn on a single ISR mode in IGU if driver is going to use
6555 * INT#x or MSI
6556 */
6557 if (!(bp->flags & USING_MSIX_FLAG))
6558 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6559 /*
6560 * Timers workaround bug: function init part.
6561 * Need to wait 20msec after initializing ILT,
6562 * needed to make sure there are no requests in
6563 * one of the PXP internal queues with "old" ILT addresses
6564 */
6565 msleep(20);
6566 /*
6567 * Master enable - Due to WB DMAE writes performed before this
6568 * register is re-initialized as part of the regular function
6569 * init
6570 */
6571 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6572 /* Enable the function in IGU */
6573 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6574 }
6575
523224a3 6576 bp->dmae_ready = 1;
34f80b04 6577
619c5cb6 6578 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 6579
619c5cb6 6580 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6581 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6582
619c5cb6
VZ		 6583 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6584 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6585 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6586 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6587 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6588 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6589 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6590 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6591 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6592 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6593 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6594 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6595 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6596
6597 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6598 REG_WR(bp, QM_REG_PF_EN, 1);
6599
619c5cb6
VZ		 6600 if (!CHIP_IS_E1x(bp)) {
6601 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6602 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6603 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6604 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6605 }
6606 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6607
6608 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6609 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6610 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6611 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6612 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6613 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6614 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6615 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6616 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6617 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6618 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6619 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6620 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6621
619c5cb6 6622 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 6623
619c5cb6 6624 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 6625
619c5cb6 6626 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6627 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6628
fb3bff17 6629 if (IS_MF(bp)) {
34f80b04 6630 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
fb3bff17 6631 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
34f80b04
EG		 6632 }
6633
619c5cb6 6634 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 6635
34f80b04 6636 /* HC init per function */
f2e0899f
DK		 6637 if (bp->common.int_block == INT_BLOCK_HC) {
6638 if (CHIP_IS_E1H(bp)) {
6639 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6640
6641 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6642 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6643 }
619c5cb6 6644 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 6645
6646 } else {
6647 int num_segs, sb_idx, prod_offset;
6648
34f80b04
EG		 6649 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6650
619c5cb6 6651 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6652 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6653 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6654 }
6655
619c5cb6 6656 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 6657
619c5cb6 6658 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6659 int dsb_idx = 0;
6660 /**
6661 * Producer memory:
6662 * E2 mode: address 0-135 match to the mapping memory;
6663 * 136 - PF0 default prod; 137 - PF1 default prod;
6664 * 138 - PF2 default prod; 139 - PF3 default prod;
6665 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6666 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6667 * 144-147 reserved.
6668 *
6669 * E1.5 mode - In backward compatible mode;
6670 * for non default SB; each even line in the memory
6671 * holds the U producer and each odd line hold
6672 * the C producer. The first 128 producers are for
6673 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6674 * producers are for the DSB for each PF.
6675 * Each PF has five segments: (the order inside each
6676 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6677 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6678 * 144-147 attn prods;
6679 */
6680 /* non-default-status-blocks */
6681 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6682 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6683 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6684 prod_offset = (bp->igu_base_sb + sb_idx) *
6685 num_segs;
6686
6687 for (i = 0; i < num_segs; i++) {
6688 addr = IGU_REG_PROD_CONS_MEMORY +
6689 (prod_offset + i) * 4;
6690 REG_WR(bp, addr, 0);
6691 }
6692 /* send consumer update with value 0 */
6693 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6694 USTORM_ID, 0, IGU_INT_NOP, 1);
6695 bnx2x_igu_clear_sb(bp,
6696 bp->igu_base_sb + sb_idx);
6697 }
6698
6699 /* default-status-blocks */
6700 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6701 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6702
6703 if (CHIP_MODE_IS_4_PORT(bp))
6704 dsb_idx = BP_FUNC(bp);
6705 else
3395a033 6706 dsb_idx = BP_VN(bp);
f2e0899f
DK		 6707
6708 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6709 IGU_BC_BASE_DSB_PROD + dsb_idx :
6710 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6711
3395a033
DK		 6712 /*
6713 * igu prods come in chunks of E1HVN_MAX (4) -
6714 * does not matters what is the current chip mode
6715 */
f2e0899f
DK		 6716 for (i = 0; i < (num_segs * E1HVN_MAX);
6717 i += E1HVN_MAX) {
6718 addr = IGU_REG_PROD_CONS_MEMORY +
6719 (prod_offset + i)*4;
6720 REG_WR(bp, addr, 0);
6721 }
6722 /* send consumer update with 0 */
6723 if (CHIP_INT_MODE_IS_BC(bp)) {
6724 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6725 USTORM_ID, 0, IGU_INT_NOP, 1);
6726 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6727 CSTORM_ID, 0, IGU_INT_NOP, 1);
6728 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6729 XSTORM_ID, 0, IGU_INT_NOP, 1);
6730 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6731 TSTORM_ID, 0, IGU_INT_NOP, 1);
6732 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6733 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6734 } else {
6735 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6736 USTORM_ID, 0, IGU_INT_NOP, 1);
6737 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6738 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6739 }
6740 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6741
6742 /* !!! these should become driver const once
6743 rf-tool supports split-68 const */
6744 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6745 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6746 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6747 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6748 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6749 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6750 }
34f80b04 6751 }
34f80b04 6752
c14423fe 6753 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 6754 REG_WR(bp, 0x2114, 0xffffffff);
6755 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 6756
f4a66897
VZ		 6757 if (CHIP_IS_E1x(bp)) {
6758 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6759 main_mem_base = HC_REG_MAIN_MEMORY +
6760 BP_PORT(bp) * (main_mem_size * 4);
6761 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6762 main_mem_width = 8;
6763
6764 val = REG_RD(bp, main_mem_prty_clr);
6765 if (val)
6766 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6767 "block during "
6768 "function init (0x%x)!\n", val);
6769
6770 /* Clear "false" parity errors in MSI-X table */
6771 for (i = main_mem_base;
6772 i < main_mem_base + main_mem_size * 4;
6773 i += main_mem_width) {
6774 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6775 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6776 i, main_mem_width / 4);
6777 }
6778 /* Clear HC parity attention */
6779 REG_RD(bp, main_mem_prty_clr);
6780 }
6781
619c5cb6
VZ		 6782#ifdef BNX2X_STOP_ON_ERROR
6783 /* Enable STORMs SP logging */
6784 REG_WR8(bp, BAR_USTRORM_INTMEM +
6785 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6786 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6787 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6788 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6789 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6790 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6791 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6792#endif
6793
b7737c9b 6794 bnx2x_phy_probe(&bp->link_params);
f85582f8 6795
34f80b04
EG		 6796 return 0;
6797}
6798
a2fbb9ea 6799
9f6c9258 6800void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 6801{
a2fbb9ea 6802 /* fastpath */
b3b83c3f 6803 bnx2x_free_fp_mem(bp);
a2fbb9ea
ET		 6804 /* end of fastpath */
6805
6806 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
523224a3 6807 sizeof(struct host_sp_status_block));
a2fbb9ea 6808
619c5cb6
VZ		 6809 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6810 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6811
a2fbb9ea 6812 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 6813 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6814
523224a3
DK		 6815 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6816 bp->context.size);
6817
6818 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6819
6820 BNX2X_FREE(bp->ilt->lines);
f85582f8 6821
37b091ba 6822#ifdef BCM_CNIC
619c5cb6 6823 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6824 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6825 sizeof(struct host_hc_status_block_e2));
6826 else
6827 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6828 sizeof(struct host_hc_status_block_e1x));
f85582f8 6829
523224a3 6830 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
a2fbb9ea 6831#endif
f85582f8 6832
7a9b2557 6833 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 6834
523224a3
DK		 6835 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6836 BCM_PAGE_SIZE * NUM_EQ_PAGES);
619c5cb6
VZ		 6837}
6838
6839static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6840{
6841 int num_groups;
50f0a562 6842 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
619c5cb6 6843
50f0a562
BW		 6844 /* number of queues for statistics is number of eth queues + FCoE */
6845 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
619c5cb6
VZ		 6846
6847 /* Total number of FW statistics requests =
50f0a562
BW		 6848 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
6849 * num of queues
6850 */
6851 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
523224a3 6852
619c5cb6
VZ		 6853
6854 /* Request is built from stats_query_header and an array of
6855 * stats_query_cmd_group each of which contains
6856 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6857 * configured in the stats_query_header.
6858 */
50f0a562
BW		 6859 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
6860 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
619c5cb6
VZ		 6861
6862 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6863 num_groups * sizeof(struct stats_query_cmd_group);
6864
6865 /* Data for statistics requests + stats_conter
6866 *
6867 * stats_counter holds per-STORM counters that are incremented
6868 * when STORM has finished with the current request.
50f0a562
BW		 6869 *
6870 * memory for FCoE offloaded statistics are counted anyway,
6871 * even if they will not be sent.
619c5cb6
VZ		 6872 */
6873 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6874 sizeof(struct per_pf_stats) +
50f0a562 6875 sizeof(struct fcoe_statistics_params) +
619c5cb6
VZ		 6876 sizeof(struct per_queue_stats) * num_queue_stats +
6877 sizeof(struct stats_counter);
6878
6879 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6880 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6881
6882 /* Set shortcuts */
6883 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6884 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6885
6886 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6887 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6888
6889 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6890 bp->fw_stats_req_sz;
6891 return 0;
6892
6893alloc_mem_err:
6894 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6895 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6896 return -ENOMEM;
a2fbb9ea
ET		 6897}
6898
f2e0899f 6899
9f6c9258 6900int bnx2x_alloc_mem(struct bnx2x *bp)
a2fbb9ea 6901{
523224a3 6902#ifdef BCM_CNIC
619c5cb6
VZ		 6903 if (!CHIP_IS_E1x(bp))
6904 /* size = the status block + ramrod buffers */
f2e0899f
DK		 6905 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6906 sizeof(struct host_hc_status_block_e2));
6907 else
6908 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6909 sizeof(struct host_hc_status_block_e1x));
8badd27a 6910
523224a3
DK		 6911 /* allocate searcher T2 table */
6912 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6913#endif
a2fbb9ea 6914
8badd27a 6915
523224a3
DK		 6916 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6917 sizeof(struct host_sp_status_block));
a2fbb9ea 6918
523224a3
DK		 6919 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6920 sizeof(struct bnx2x_slowpath));
a2fbb9ea 6921
619c5cb6
VZ		 6922 /* Allocated memory for FW statistics */
6923 if (bnx2x_alloc_fw_stats_mem(bp))
6924 goto alloc_mem_err;
6925
6383c0b3 6926 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
f85582f8 6927
523224a3
DK		 6928 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6929 bp->context.size);
65abd74d 6930
523224a3 6931 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
65abd74d 6932
523224a3
DK		 6933 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6934 goto alloc_mem_err;
65abd74d 6935
9f6c9258
DK		 6936 /* Slow path ring */
6937 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
65abd74d 6938
523224a3
DK		 6939 /* EQ */
6940 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6941 BCM_PAGE_SIZE * NUM_EQ_PAGES);
ab532cf3 6942
b3b83c3f
DK		 6943
6944 /* fastpath */
6945 /* need to be done at the end, since it's self adjusting to amount
6946 * of memory available for RSS queues
6947 */
6948 if (bnx2x_alloc_fp_mem(bp))
6949 goto alloc_mem_err;
9f6c9258 6950 return 0;
e1510706 6951
9f6c9258
DK		 6952alloc_mem_err:
6953 bnx2x_free_mem(bp);
6954 return -ENOMEM;
65abd74d
YG		 6955}
6956
a2fbb9ea
ET		 6957/*
6958 * Init service functions
6959 */
a2fbb9ea 6960
619c5cb6
VZ		 6961int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6962 struct bnx2x_vlan_mac_obj *obj, bool set,
6963 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 6964{
619c5cb6
VZ		 6965 int rc;
6966 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 6967
619c5cb6 6968 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 6969
619c5cb6
VZ		 6970 /* Fill general parameters */
6971 ramrod_param.vlan_mac_obj = obj;
6972 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 6973
619c5cb6
VZ		 6974 /* Fill a user request section if needed */
6975 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6976 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 6977
619c5cb6 6978 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 6979
619c5cb6
VZ		 6980 /* Set the command: ADD or DEL */
6981 if (set)
6982 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6983 else
6984 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 6985 }
6986
619c5cb6
VZ		 6987 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6988 if (rc < 0)
6989 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6990 return rc;
a2fbb9ea
ET		 6991}
6992
619c5cb6
VZ		 6993int bnx2x_del_all_macs(struct bnx2x *bp,
6994 struct bnx2x_vlan_mac_obj *mac_obj,
6995 int mac_type, bool wait_for_comp)
e665bfda 6996{
619c5cb6
VZ		 6997 int rc;
6998 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 6999
619c5cb6
VZ		 7000 /* Wait for completion of requested */
7001 if (wait_for_comp)
7002 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 7003
619c5cb6
VZ		 7004 /* Set the mac type of addresses we want to clear */
7005 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 7006
619c5cb6
VZ		 7007 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7008 if (rc < 0)
7009 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 7010
619c5cb6 7011 return rc;
0793f83f
DK		 7012}
7013
619c5cb6 7014int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 7015{
619c5cb6 7016 unsigned long ramrod_flags = 0;
e665bfda 7017
614c76df
DK		 7018#ifdef BCM_CNIC
7019 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) {
7020 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n");
7021 return 0;
7022 }
7023#endif
7024
619c5cb6 7025 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
0793f83f 7026
619c5cb6
VZ		 7027 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7028 /* Eth MAC is set on RSS leading client (fp[0]) */
7029 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7030 BNX2X_ETH_MAC, &ramrod_flags);
e665bfda 7031}
6e30dd4e 7032
619c5cb6 7033int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 7034{
619c5cb6 7035 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
993ac7b5 7036}
a2fbb9ea 7037
d6214d7a 7038/**
e8920674 7039 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 7040 *
e8920674 7041 * @bp: driver handle
d6214d7a 7042 *
e8920674 7043 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 7044 */
9ee3d37b 7045static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 7046{
9ee3d37b 7047 switch (int_mode) {
d6214d7a
DK		 7048 case INT_MODE_MSI:
7049 bnx2x_enable_msi(bp);
7050 /* falling through... */
7051 case INT_MODE_INTx:
6383c0b3 7052 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7053 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
ca00392c 7054 break;
d6214d7a
DK		 7055 default:
7056 /* Set number of queues according to bp->multi_mode value */
7057 bnx2x_set_num_queues(bp);
ca00392c 7058
d6214d7a
DK		 7059 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7060 bp->num_queues);
ca00392c 7061
d6214d7a
DK		 7062 /* if we can't use MSI-X we only need one fp,
7063 * so try to enable MSI-X with the requested number of fp's
7064 * and fallback to MSI or legacy INTx with one fp
7065 */
9ee3d37b 7066 if (bnx2x_enable_msix(bp)) {
d6214d7a
DK		 7067 /* failed to enable MSI-X */
7068 if (bp->multi_mode)
7069 DP(NETIF_MSG_IFUP,
7070 "Multi requested but failed to "
7071 "enable MSI-X (%d), "
7072 "set number of queues to %d\n",
7073 bp->num_queues,
6383c0b3
AE		 7074 1 + NON_ETH_CONTEXT_USE);
7075 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
d6214d7a 7076
9ee3d37b 7077 /* Try to enable MSI */
d6214d7a
DK		 7078 if (!(bp->flags & DISABLE_MSI_FLAG))
7079 bnx2x_enable_msi(bp);
7080 }
9f6c9258
DK		 7081 break;
7082 }
a2fbb9ea
ET		 7083}
7084
c2bff63f
DK		 7085/* must be called prioir to any HW initializations */
7086static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7087{
7088 return L2_ILT_LINES(bp);
7089}
7090
523224a3
DK		 7091void bnx2x_ilt_set_info(struct bnx2x *bp)
7092{
7093 struct ilt_client_info *ilt_client;
7094 struct bnx2x_ilt *ilt = BP_ILT(bp);
7095 u16 line = 0;
7096
7097 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7098 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7099
7100 /* CDU */
7101 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7102 ilt_client->client_num = ILT_CLIENT_CDU;
7103 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7104 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7105 ilt_client->start = line;
619c5cb6 7106 line += bnx2x_cid_ilt_lines(bp);
523224a3
DK		 7107#ifdef BCM_CNIC
7108 line += CNIC_ILT_LINES;
7109#endif
7110 ilt_client->end = line - 1;
7111
7112 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7113 "flags 0x%x, hw psz %d\n",
7114 ilt_client->start,
7115 ilt_client->end,
7116 ilt_client->page_size,
7117 ilt_client->flags,
7118 ilog2(ilt_client->page_size >> 12));
7119
7120 /* QM */
7121 if (QM_INIT(bp->qm_cid_count)) {
7122 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7123 ilt_client->client_num = ILT_CLIENT_QM;
7124 ilt_client->page_size = QM_ILT_PAGE_SZ;
7125 ilt_client->flags = 0;
7126 ilt_client->start = line;
7127
7128 /* 4 bytes for each cid */
7129 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7130 QM_ILT_PAGE_SZ);
7131
7132 ilt_client->end = line - 1;
7133
7134 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7135 "flags 0x%x, hw psz %d\n",
7136 ilt_client->start,
7137 ilt_client->end,
7138 ilt_client->page_size,
7139 ilt_client->flags,
7140 ilog2(ilt_client->page_size >> 12));
7141
7142 }
7143 /* SRC */
7144 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7145#ifdef BCM_CNIC
7146 ilt_client->client_num = ILT_CLIENT_SRC;
7147 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7148 ilt_client->flags = 0;
7149 ilt_client->start = line;
7150 line += SRC_ILT_LINES;
7151 ilt_client->end = line - 1;
7152
7153 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7154 "flags 0x%x, hw psz %d\n",
7155 ilt_client->start,
7156 ilt_client->end,
7157 ilt_client->page_size,
7158 ilt_client->flags,
7159 ilog2(ilt_client->page_size >> 12));
7160
7161#else
7162 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7163#endif
9f6c9258 7164
523224a3
DK		 7165 /* TM */
7166 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7167#ifdef BCM_CNIC
7168 ilt_client->client_num = ILT_CLIENT_TM;
7169 ilt_client->page_size = TM_ILT_PAGE_SZ;
7170 ilt_client->flags = 0;
7171 ilt_client->start = line;
7172 line += TM_ILT_LINES;
7173 ilt_client->end = line - 1;
7174
7175 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7176 "flags 0x%x, hw psz %d\n",
7177 ilt_client->start,
7178 ilt_client->end,
7179 ilt_client->page_size,
7180 ilt_client->flags,
7181 ilog2(ilt_client->page_size >> 12));
9f6c9258 7182
523224a3
DK		 7183#else
7184 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7185#endif
619c5cb6 7186 BUG_ON(line > ILT_MAX_LINES);
523224a3 7187}
f85582f8 7188
619c5cb6
VZ		 7189/**
7190 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7191 *
7192 * @bp: driver handle
7193 * @fp: pointer to fastpath
7194 * @init_params: pointer to parameters structure
7195 *
7196 * parameters configured:
7197 * - HC configuration
7198 * - Queue's CDU context
7199 */
7200static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7201 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 7202{
6383c0b3
AE		 7203
7204 u8 cos;
619c5cb6
VZ		 7205 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7206 if (!IS_FCOE_FP(fp)) {
7207 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7208 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7209
7210 /* If HC is supporterd, enable host coalescing in the transition
7211 * to INIT state.
7212 */
7213 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7214 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7215
7216 /* HC rate */
7217 init_params->rx.hc_rate = bp->rx_ticks ?
7218 (1000000 / bp->rx_ticks) : 0;
7219 init_params->tx.hc_rate = bp->tx_ticks ?
7220 (1000000 / bp->tx_ticks) : 0;
7221
7222 /* FW SB ID */
7223 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7224 fp->fw_sb_id;
7225
7226 /*
7227 * CQ index among the SB indices: FCoE clients uses the default
7228 * SB, therefore it's different.
7229 */
6383c0b3
AE		 7230 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7231 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 7232 }
7233
6383c0b3
AE		 7234 /* set maximum number of COSs supported by this queue */
7235 init_params->max_cos = fp->max_cos;
7236
94f05b0f 7237 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 7238 fp->index, init_params->max_cos);
7239
7240 /* set the context pointers queue object */
7241 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7242 init_params->cxts[cos] =
7243 &bp->context.vcxt[fp->txdata[cos].cid].eth;
619c5cb6
VZ		 7244}
7245
6383c0b3
AE		 7246int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7247 struct bnx2x_queue_state_params *q_params,
7248 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7249 int tx_index, bool leading)
7250{
7251 memset(tx_only_params, 0, sizeof(*tx_only_params));
7252
7253 /* Set the command */
7254 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7255
7256 /* Set tx-only QUEUE flags: don't zero statistics */
7257 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7258
7259 /* choose the index of the cid to send the slow path on */
7260 tx_only_params->cid_index = tx_index;
7261
7262 /* Set general TX_ONLY_SETUP parameters */
7263 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7264
7265 /* Set Tx TX_ONLY_SETUP parameters */
7266 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7267
7268 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7269 "cos %d, primary cid %d, cid %d, "
94f05b0f 7270 "client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 7271 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7272 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7273 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7274
7275 /* send the ramrod */
7276 return bnx2x_queue_state_change(bp, q_params);
7277}
7278
7279
619c5cb6
VZ		 7280/**
7281 * bnx2x_setup_queue - setup queue
7282 *
7283 * @bp: driver handle
7284 * @fp: pointer to fastpath
7285 * @leading: is leading
7286 *
7287 * This function performs 2 steps in a Queue state machine
7288 * actually: 1) RESET->INIT 2) INIT->SETUP
7289 */
7290
7291int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7292 bool leading)
7293{
7294 struct bnx2x_queue_state_params q_params = {0};
7295 struct bnx2x_queue_setup_params *setup_params =
7296 &q_params.params.setup;
6383c0b3
AE		 7297 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7298 &q_params.params.tx_only;
a2fbb9ea 7299 int rc;
6383c0b3
AE		 7300 u8 tx_index;
7301
94f05b0f 7302 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index);
a2fbb9ea 7303
ec6ba945
VZ		 7304 /* reset IGU state skip FCoE L2 queue */
7305 if (!IS_FCOE_FP(fp))
7306 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 7307 IGU_INT_ENABLE, 0);
a2fbb9ea 7308
619c5cb6
VZ		 7309 q_params.q_obj = &fp->q_obj;
7310 /* We want to wait for completion in this context */
7311 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7312
619c5cb6
VZ		 7313 /* Prepare the INIT parameters */
7314 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 7315
619c5cb6
VZ		 7316 /* Set the command */
7317 q_params.cmd = BNX2X_Q_CMD_INIT;
7318
7319 /* Change the state to INIT */
7320 rc = bnx2x_queue_state_change(bp, &q_params);
7321 if (rc) {
6383c0b3 7322 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 7323 return rc;
7324 }
ec6ba945 7325
94f05b0f 7326 DP(BNX2X_MSG_SP, "init complete\n");
6383c0b3
AE		 7327
7328
619c5cb6
VZ		 7329 /* Now move the Queue to the SETUP state... */
7330 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 7331
619c5cb6
VZ		 7332 /* Set QUEUE flags */
7333 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 7334
619c5cb6 7335 /* Set general SETUP parameters */
6383c0b3
AE		 7336 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7337 FIRST_TX_COS_INDEX);
619c5cb6 7338
6383c0b3 7339 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 7340 &setup_params->rxq_params);
7341
6383c0b3
AE		 7342 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7343 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 7344
7345 /* Set the command */
7346 q_params.cmd = BNX2X_Q_CMD_SETUP;
7347
7348 /* Change the state to SETUP */
7349 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 7350 if (rc) {
7351 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7352 return rc;
7353 }
7354
7355 /* loop through the relevant tx-only indices */
7356 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7357 tx_index < fp->max_cos;
7358 tx_index++) {
7359
7360 /* prepare and send tx-only ramrod*/
7361 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7362 tx_only_params, tx_index, leading);
7363 if (rc) {
7364 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7365 fp->index, tx_index);
7366 return rc;
7367 }
7368 }
523224a3 7369
34f80b04 7370 return rc;
a2fbb9ea
ET		 7371}
7372
619c5cb6 7373static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 7374{
619c5cb6 7375 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 7376 struct bnx2x_fp_txdata *txdata;
619c5cb6 7377 struct bnx2x_queue_state_params q_params = {0};
6383c0b3
AE		 7378 int rc, tx_index;
7379
94f05b0f 7380 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 7381
619c5cb6
VZ		 7382 q_params.q_obj = &fp->q_obj;
7383 /* We want to wait for completion in this context */
7384 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 7385
6383c0b3
AE		 7386
7387 /* close tx-only connections */
7388 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7389 tx_index < fp->max_cos;
7390 tx_index++){
7391
7392 /* ascertain this is a normal queue*/
7393 txdata = &fp->txdata[tx_index];
7394
94f05b0f 7395 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n",
6383c0b3
AE		 7396 txdata->txq_index);
7397
7398 /* send halt terminate on tx-only connection */
7399 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7400 memset(&q_params.params.terminate, 0,
7401 sizeof(q_params.params.terminate));
7402 q_params.params.terminate.cid_index = tx_index;
7403
7404 rc = bnx2x_queue_state_change(bp, &q_params);
7405 if (rc)
7406 return rc;
7407
7408 /* send halt terminate on tx-only connection */
7409 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7410 memset(&q_params.params.cfc_del, 0,
7411 sizeof(q_params.params.cfc_del));
7412 q_params.params.cfc_del.cid_index = tx_index;
7413 rc = bnx2x_queue_state_change(bp, &q_params);
7414 if (rc)
7415 return rc;
7416 }
7417 /* Stop the primary connection: */
7418 /* ...halt the connection */
619c5cb6
VZ		 7419 q_params.cmd = BNX2X_Q_CMD_HALT;
7420 rc = bnx2x_queue_state_change(bp, &q_params);
7421 if (rc)
da5a662a 7422 return rc;
a2fbb9ea 7423
6383c0b3 7424 /* ...terminate the connection */
619c5cb6 7425 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 7426 memset(&q_params.params.terminate, 0,
7427 sizeof(q_params.params.terminate));
7428 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 7429 rc = bnx2x_queue_state_change(bp, &q_params);
7430 if (rc)
523224a3 7431 return rc;
6383c0b3 7432 /* ...delete cfc entry */
619c5cb6 7433 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 7434 memset(&q_params.params.cfc_del, 0,
7435 sizeof(q_params.params.cfc_del));
7436 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 7437 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 7438}
7439
7440
34f80b04
EG		 7441static void bnx2x_reset_func(struct bnx2x *bp)
7442{
7443 int port = BP_PORT(bp);
7444 int func = BP_FUNC(bp);
f2e0899f 7445 int i;
523224a3
DK		 7446
7447 /* Disable the function in the FW */
7448 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7449 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7450 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7451 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7452
7453 /* FP SBs */
ec6ba945 7454 for_each_eth_queue(bp, i) {
523224a3 7455 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 7456 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7457 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7458 SB_DISABLED);
523224a3
DK		 7459 }
7460
619c5cb6
VZ		 7461#ifdef BCM_CNIC
7462 /* CNIC SB */
7463 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7464 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7465 SB_DISABLED);
7466#endif
523224a3 7467 /* SP SB */
619c5cb6 7468 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 7469 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7470 SB_DISABLED);
523224a3
DK		 7471
7472 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7473 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7474 0);
34f80b04
EG		 7475
7476 /* Configure IGU */
f2e0899f
DK		 7477 if (bp->common.int_block == INT_BLOCK_HC) {
7478 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7479 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7480 } else {
7481 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7482 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7483 }
34f80b04 7484
37b091ba
MC		 7485#ifdef BCM_CNIC
7486 /* Disable Timer scan */
7487 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7488 /*
7489 * Wait for at least 10ms and up to 2 second for the timers scan to
7490 * complete
7491 */
7492 for (i = 0; i < 200; i++) {
7493 msleep(10);
7494 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7495 break;
7496 }
7497#endif
34f80b04 7498 /* Clear ILT */
f2e0899f
DK		 7499 bnx2x_clear_func_ilt(bp, func);
7500
7501 /* Timers workaround bug for E2: if this is vnic-3,
7502 * we need to set the entire ilt range for this timers.
7503 */
619c5cb6 7504 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 7505 struct ilt_client_info ilt_cli;
7506 /* use dummy TM client */
7507 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7508 ilt_cli.start = 0;
7509 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7510 ilt_cli.client_num = ILT_CLIENT_TM;
7511
7512 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7513 }
7514
7515 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 7516 if (!CHIP_IS_E1x(bp))
f2e0899f 7517 bnx2x_pf_disable(bp);
523224a3
DK		 7518
7519 bp->dmae_ready = 0;
34f80b04
EG		 7520}
7521
7522static void bnx2x_reset_port(struct bnx2x *bp)
7523{
7524 int port = BP_PORT(bp);
7525 u32 val;
7526
619c5cb6
VZ		 7527 /* Reset physical Link */
7528 bnx2x__link_reset(bp);
7529
34f80b04
EG		 7530 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7531
7532 /* Do not rcv packets to BRB */
7533 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7534 /* Do not direct rcv packets that are not for MCP to the BRB */
7535 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7536 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7537
7538 /* Configure AEU */
7539 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7540
7541 msleep(100);
7542 /* Check for BRB port occupancy */
7543 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7544 if (val)
7545 DP(NETIF_MSG_IFDOWN,
33471629 7546 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 7547
7548 /* TODO: Close Doorbell port? */
7549}
7550
619c5cb6 7551static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 7552{
619c5cb6 7553 struct bnx2x_func_state_params func_params = {0};
34f80b04 7554
619c5cb6
VZ		 7555 /* Prepare parameters for function state transitions */
7556 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 7557
619c5cb6
VZ		 7558 func_params.f_obj = &bp->func_obj;
7559 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 7560
619c5cb6 7561 func_params.params.hw_init.load_phase = load_code;
49d66772 7562
619c5cb6 7563 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 7564}
7565
619c5cb6 7566static inline int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 7567{
619c5cb6
VZ		 7568 struct bnx2x_func_state_params func_params = {0};
7569 int rc;
228241eb 7570
619c5cb6
VZ		 7571 /* Prepare parameters for function state transitions */
7572 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7573 func_params.f_obj = &bp->func_obj;
7574 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 7575
619c5cb6
VZ		 7576 /*
7577 * Try to stop the function the 'good way'. If fails (in case
7578 * of a parity error during bnx2x_chip_cleanup()) and we are
7579 * not in a debug mode, perform a state transaction in order to
7580 * enable further HW_RESET transaction.
7581 */
7582 rc = bnx2x_func_state_change(bp, &func_params);
7583 if (rc) {
34f80b04 7584#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 7585 return rc;
34f80b04 7586#else
619c5cb6
VZ		 7587 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7588 "transaction\n");
7589 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7590 return bnx2x_func_state_change(bp, &func_params);
34f80b04 7591#endif
228241eb 7592 }
a2fbb9ea 7593
619c5cb6
VZ		 7594 return 0;
7595}
523224a3 7596
619c5cb6
VZ		 7597/**
7598 * bnx2x_send_unload_req - request unload mode from the MCP.
7599 *
7600 * @bp: driver handle
7601 * @unload_mode: requested function's unload mode
7602 *
7603 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7604 */
7605u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7606{
7607 u32 reset_code = 0;
7608 int port = BP_PORT(bp);
3101c2bc 7609
619c5cb6 7610 /* Select the UNLOAD request mode */
65abd74d
YG		 7611 if (unload_mode == UNLOAD_NORMAL)
7612 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7613
7d0446c2 7614 else if (bp->flags & NO_WOL_FLAG)
65abd74d 7615 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 7616
7d0446c2 7617 else if (bp->wol) {
65abd74d
YG		 7618 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7619 u8 *mac_addr = bp->dev->dev_addr;
7620 u32 val;
f9977903
DK		 7621 u16 pmc;
7622
65abd74d 7623 /* The mac address is written to entries 1-4 to
f9977903
DK		 7624 * preserve entry 0 which is used by the PMF
7625 */
3395a033 7626 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 7627
7628 val = (mac_addr[0] << 8) | mac_addr[1];
7629 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7630
7631 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7632 (mac_addr[4] << 8) | mac_addr[5];
7633 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7634
f9977903
DK		 7635 /* Enable the PME and clear the status */
7636 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
7637 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
7638 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
7639
65abd74d
YG		 7640 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7641
7642 } else
7643 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 7644
619c5cb6
VZ		 7645 /* Send the request to the MCP */
7646 if (!BP_NOMCP(bp))
7647 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7648 else {
7649 int path = BP_PATH(bp);
7650
7651 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7652 "%d, %d, %d\n",
7653 path, load_count[path][0], load_count[path][1],
7654 load_count[path][2]);
7655 load_count[path][0]--;
7656 load_count[path][1 + port]--;
7657 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7658 "%d, %d, %d\n",
7659 path, load_count[path][0], load_count[path][1],
7660 load_count[path][2]);
7661 if (load_count[path][0] == 0)
7662 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7663 else if (load_count[path][1 + port] == 0)
7664 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7665 else
7666 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7667 }
7668
7669 return reset_code;
7670}
7671
7672/**
7673 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7674 *
7675 * @bp: driver handle
7676 */
7677void bnx2x_send_unload_done(struct bnx2x *bp)
7678{
7679 /* Report UNLOAD_DONE to MCP */
7680 if (!BP_NOMCP(bp))
7681 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7682}
7683
6debea87
DK		 7684static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7685{
7686 int tout = 50;
7687 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7688
7689 if (!bp->port.pmf)
7690 return 0;
7691
7692 /*
7693 * (assumption: No Attention from MCP at this stage)
7694 * PMF probably in the middle of TXdisable/enable transaction
7695 * 1. Sync IRS for default SB
7696 * 2. Sync SP queue - this guarantes us that attention handling started
7697 * 3. Wait, that TXdisable/enable transaction completes
7698 *
7699 * 1+2 guranty that if DCBx attention was scheduled it already changed
7700 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7701 * received complettion for the transaction the state is TX_STOPPED.
7702 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7703 * transaction.
7704 */
7705
7706 /* make sure default SB ISR is done */
7707 if (msix)
7708 synchronize_irq(bp->msix_table[0].vector);
7709 else
7710 synchronize_irq(bp->pdev->irq);
7711
7712 flush_workqueue(bnx2x_wq);
7713
7714 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7715 BNX2X_F_STATE_STARTED && tout--)
7716 msleep(20);
7717
7718 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7719 BNX2X_F_STATE_STARTED) {
7720#ifdef BNX2X_STOP_ON_ERROR
7721 return -EBUSY;
7722#else
7723 /*
7724 * Failed to complete the transaction in a "good way"
7725 * Force both transactions with CLR bit
7726 */
7727 struct bnx2x_func_state_params func_params = {0};
7728
7729 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7730 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7731
7732 func_params.f_obj = &bp->func_obj;
7733 __set_bit(RAMROD_DRV_CLR_ONLY,
7734 &func_params.ramrod_flags);
7735
7736 /* STARTED-->TX_ST0PPED */
7737 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7738 bnx2x_func_state_change(bp, &func_params);
7739
7740 /* TX_ST0PPED-->STARTED */
7741 func_params.cmd = BNX2X_F_CMD_TX_START;
7742 return bnx2x_func_state_change(bp, &func_params);
7743#endif
7744 }
7745
7746 return 0;
7747}
7748
619c5cb6
VZ		 7749void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7750{
7751 int port = BP_PORT(bp);
6383c0b3
AE		 7752 int i, rc = 0;
7753 u8 cos;
619c5cb6
VZ		 7754 struct bnx2x_mcast_ramrod_params rparam = {0};
7755 u32 reset_code;
7756
7757 /* Wait until tx fastpath tasks complete */
7758 for_each_tx_queue(bp, i) {
7759 struct bnx2x_fastpath *fp = &bp->fp[i];
7760
6383c0b3
AE		 7761 for_each_cos_in_tx_queue(fp, cos)
7762 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
619c5cb6
VZ		 7763#ifdef BNX2X_STOP_ON_ERROR
7764 if (rc)
7765 return;
7766#endif
7767 }
7768
7769 /* Give HW time to discard old tx messages */
7770 usleep_range(1000, 1000);
7771
7772 /* Clean all ETH MACs */
7773 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7774 if (rc < 0)
7775 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7776
7777 /* Clean up UC list */
7778 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7779 true);
7780 if (rc < 0)
7781 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7782 "%d\n", rc);
7783
7784 /* Disable LLH */
7785 if (!CHIP_IS_E1(bp))
7786 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7787
7788 /* Set "drop all" (stop Rx).
7789 * We need to take a netif_addr_lock() here in order to prevent
7790 * a race between the completion code and this code.
7791 */
7792 netif_addr_lock_bh(bp->dev);
7793 /* Schedule the rx_mode command */
7794 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7795 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7796 else
7797 bnx2x_set_storm_rx_mode(bp);
7798
7799 /* Cleanup multicast configuration */
7800 rparam.mcast_obj = &bp->mcast_obj;
7801 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7802 if (rc < 0)
7803 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7804
7805 netif_addr_unlock_bh(bp->dev);
7806
7807
6debea87
DK		 7808
7809 /*
7810 * Send the UNLOAD_REQUEST to the MCP. This will return if
7811 * this function should perform FUNC, PORT or COMMON HW
7812 * reset.
7813 */
7814 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7815
7816 /*
7817 * (assumption: No Attention from MCP at this stage)
7818 * PMF probably in the middle of TXdisable/enable transaction
7819 */
7820 rc = bnx2x_func_wait_started(bp);
7821 if (rc) {
7822 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7823#ifdef BNX2X_STOP_ON_ERROR
7824 return;
7825#endif
7826 }
7827
34f80b04 7828 /* Close multi and leading connections
619c5cb6
VZ		 7829 * Completions for ramrods are collected in a synchronous way
7830 */
523224a3 7831 for_each_queue(bp, i)
619c5cb6 7832 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 7833#ifdef BNX2X_STOP_ON_ERROR
7834 return;
7835#else
228241eb 7836 goto unload_error;
523224a3 7837#endif
619c5cb6
VZ		 7838 /* If SP settings didn't get completed so far - something
7839 * very wrong has happen.
7840 */
7841 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7842 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 7843
619c5cb6
VZ		 7844#ifndef BNX2X_STOP_ON_ERROR
7845unload_error:
7846#endif
523224a3 7847 rc = bnx2x_func_stop(bp);
da5a662a 7848 if (rc) {
523224a3 7849 BNX2X_ERR("Function stop failed!\n");
da5a662a 7850#ifdef BNX2X_STOP_ON_ERROR
523224a3 7851 return;
523224a3 7852#endif
34f80b04 7853 }
a2fbb9ea 7854
523224a3
DK		 7855 /* Disable HW interrupts, NAPI */
7856 bnx2x_netif_stop(bp, 1);
7857
7858 /* Release IRQs */
d6214d7a 7859 bnx2x_free_irq(bp);
523224a3 7860
a2fbb9ea 7861 /* Reset the chip */
619c5cb6
VZ		 7862 rc = bnx2x_reset_hw(bp, reset_code);
7863 if (rc)
7864 BNX2X_ERR("HW_RESET failed\n");
a2fbb9ea 7865
356e2385 7866
619c5cb6
VZ		 7867 /* Report UNLOAD_DONE to MCP */
7868 bnx2x_send_unload_done(bp);
72fd0718
VZ		 7869}
7870
9f6c9258 7871void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 7872{
7873 u32 val;
7874
7875 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7876
7877 if (CHIP_IS_E1(bp)) {
7878 int port = BP_PORT(bp);
7879 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7880 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7881
7882 val = REG_RD(bp, addr);
7883 val &= ~(0x300);
7884 REG_WR(bp, addr, val);
619c5cb6 7885 } else {
72fd0718
VZ		 7886 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7887 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7888 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7889 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7890 }
7891}
7892
72fd0718
VZ		 7893/* Close gates #2, #3 and #4: */
7894static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7895{
c9ee9206 7896 u32 val;
72fd0718
VZ		 7897
7898 /* Gates #2 and #4a are closed/opened for "not E1" only */
7899 if (!CHIP_IS_E1(bp)) {
7900 /* #4 */
c9ee9206 7901 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 7902 /* #2 */
c9ee9206 7903 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 7904 }
7905
7906 /* #3 */
c9ee9206
VZ		 7907 if (CHIP_IS_E1x(bp)) {
7908 /* Prevent interrupts from HC on both ports */
7909 val = REG_RD(bp, HC_REG_CONFIG_1);
7910 REG_WR(bp, HC_REG_CONFIG_1,
7911 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7912 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7913
7914 val = REG_RD(bp, HC_REG_CONFIG_0);
7915 REG_WR(bp, HC_REG_CONFIG_0,
7916 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7917 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7918 } else {
7919 /* Prevent incomming interrupts in IGU */
7920 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7921
7922 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7923 (!close) ?
7924 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7925 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7926 }
72fd0718
VZ		 7927
7928 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7929 close ? "closing" : "opening");
7930 mmiowb();
7931}
7932
7933#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7934
7935static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7936{
7937 /* Do some magic... */
7938 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7939 *magic_val = val & SHARED_MF_CLP_MAGIC;
7940 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7941}
7942
e8920674
DK		 7943/**
7944 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 7945 *
e8920674
DK		 7946 * @bp: driver handle
7947 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 7948 */
7949static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7950{
7951 /* Restore the `magic' bit value... */
72fd0718
VZ		 7952 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7953 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7954 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7955}
7956
f85582f8 7957/**
e8920674 7958 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 7959 *
e8920674
DK		 7960 * @bp: driver handle
7961 * @magic_val: old value of 'magic' bit.
7962 *
7963 * Takes care of CLP configurations.
72fd0718
VZ		 7964 */
7965static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7966{
7967 u32 shmem;
7968 u32 validity_offset;
7969
7970 DP(NETIF_MSG_HW, "Starting\n");
7971
7972 /* Set `magic' bit in order to save MF config */
7973 if (!CHIP_IS_E1(bp))
7974 bnx2x_clp_reset_prep(bp, magic_val);
7975
7976 /* Get shmem offset */
7977 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7978 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7979
7980 /* Clear validity map flags */
7981 if (shmem > 0)
7982 REG_WR(bp, shmem + validity_offset, 0);
7983}
7984
7985#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7986#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7987
e8920674
DK		 7988/**
7989 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 7990 *
e8920674 7991 * @bp: driver handle
72fd0718
VZ		 7992 */
7993static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7994{
7995 /* special handling for emulation and FPGA,
7996 wait 10 times longer */
7997 if (CHIP_REV_IS_SLOW(bp))
7998 msleep(MCP_ONE_TIMEOUT*10);
7999 else
8000 msleep(MCP_ONE_TIMEOUT);
8001}
8002
1b6e2ceb
DK		 8003/*
8004 * initializes bp->common.shmem_base and waits for validity signature to appear
8005 */
8006static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 8007{
1b6e2ceb
DK		 8008 int cnt = 0;
8009 u32 val = 0;
72fd0718 8010
1b6e2ceb
DK		 8011 do {
8012 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8013 if (bp->common.shmem_base) {
8014 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8015 if (val & SHR_MEM_VALIDITY_MB)
8016 return 0;
8017 }
72fd0718 8018
1b6e2ceb 8019 bnx2x_mcp_wait_one(bp);
72fd0718 8020
1b6e2ceb 8021 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 8022
1b6e2ceb 8023 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 8024
1b6e2ceb
DK		 8025 return -ENODEV;
8026}
72fd0718 8027
1b6e2ceb
DK		 8028static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8029{
8030 int rc = bnx2x_init_shmem(bp);
72fd0718 8031
72fd0718
VZ		 8032 /* Restore the `magic' bit value */
8033 if (!CHIP_IS_E1(bp))
8034 bnx2x_clp_reset_done(bp, magic_val);
8035
8036 return rc;
8037}
8038
8039static void bnx2x_pxp_prep(struct bnx2x *bp)
8040{
8041 if (!CHIP_IS_E1(bp)) {
8042 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8043 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 8044 mmiowb();
8045 }
8046}
8047
8048/*
8049 * Reset the whole chip except for:
8050 * - PCIE core
8051 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8052 * one reset bit)
8053 * - IGU
8054 * - MISC (including AEU)
8055 * - GRC
8056 * - RBCN, RBCP
8057 */
c9ee9206 8058static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 8059{
8060 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 8061 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 8062
8063 /*
8064 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8065 * (per chip) blocks.
8066 */
8067 global_bits2 =
8068 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8069 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 8070
8736c826 8071 /* Don't reset the following blocks */
72fd0718
VZ		 8072 not_reset_mask1 =
8073 MISC_REGISTERS_RESET_REG_1_RST_HC |
8074 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8075 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8076
8077 not_reset_mask2 =
c9ee9206 8078 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 8079 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8080 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8081 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8082 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8083 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8084 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 8085 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8086 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8087 MISC_REGISTERS_RESET_REG_2_PGLC;
72fd0718 8088
8736c826
VZ		 8089 /*
8090 * Keep the following blocks in reset:
8091 * - all xxMACs are handled by the bnx2x_link code.
8092 */
8093 stay_reset2 =
8094 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8095 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8096 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8097 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8098 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8099 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8100 MISC_REGISTERS_RESET_REG_2_XMAC |
8101 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8102
8103 /* Full reset masks according to the chip */
72fd0718
VZ		 8104 reset_mask1 = 0xffffffff;
8105
8106 if (CHIP_IS_E1(bp))
8107 reset_mask2 = 0xffff;
8736c826 8108 else if (CHIP_IS_E1H(bp))
72fd0718 8109 reset_mask2 = 0x1ffff;
8736c826
VZ		 8110 else if (CHIP_IS_E2(bp))
8111 reset_mask2 = 0xfffff;
8112 else /* CHIP_IS_E3 */
8113 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 8114
8115 /* Don't reset global blocks unless we need to */
8116 if (!global)
8117 reset_mask2 &= ~global_bits2;
8118
8119 /*
8120 * In case of attention in the QM, we need to reset PXP
8121 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8122 * because otherwise QM reset would release 'close the gates' shortly
8123 * before resetting the PXP, then the PSWRQ would send a write
8124 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8125 * read the payload data from PSWWR, but PSWWR would not
8126 * respond. The write queue in PGLUE would stuck, dmae commands
8127 * would not return. Therefore it's important to reset the second
8128 * reset register (containing the
8129 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8130 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8131 * bit).
8132 */
72fd0718
VZ		 8133 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8134 reset_mask2 & (~not_reset_mask2));
8135
c9ee9206
VZ		 8136 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8137 reset_mask1 & (~not_reset_mask1));
8138
72fd0718
VZ		 8139 barrier();
8140 mmiowb();
8141
8736c826
VZ		 8142 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8143 reset_mask2 & (~stay_reset2));
8144
8145 barrier();
8146 mmiowb();
8147
c9ee9206 8148 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 8149 mmiowb();
8150}
8151
c9ee9206
VZ		 8152/**
8153 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8154 * It should get cleared in no more than 1s.
8155 *
8156 * @bp: driver handle
8157 *
8158 * It should get cleared in no more than 1s. Returns 0 if
8159 * pending writes bit gets cleared.
8160 */
8161static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8162{
8163 u32 cnt = 1000;
8164 u32 pend_bits = 0;
8165
8166 do {
8167 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8168
8169 if (pend_bits == 0)
8170 break;
8171
8172 usleep_range(1000, 1000);
8173 } while (cnt-- > 0);
8174
8175 if (cnt <= 0) {
8176 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8177 pend_bits);
8178 return -EBUSY;
8179 }
8180
8181 return 0;
8182}
8183
8184static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 8185{
8186 int cnt = 1000;
8187 u32 val = 0;
8188 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8189
8190
8191 /* Empty the Tetris buffer, wait for 1s */
8192 do {
8193 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8194 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8195 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8196 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8197 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8198 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8199 ((port_is_idle_0 & 0x1) == 0x1) &&
8200 ((port_is_idle_1 & 0x1) == 0x1) &&
8201 (pgl_exp_rom2 == 0xffffffff))
8202 break;
c9ee9206 8203 usleep_range(1000, 1000);
72fd0718
VZ		 8204 } while (cnt-- > 0);
8205
8206 if (cnt <= 0) {
8207 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8208 " are still"
8209 " outstanding read requests after 1s!\n");
8210 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8211 " port_is_idle_0=0x%08x,"
8212 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8213 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8214 pgl_exp_rom2);
8215 return -EAGAIN;
8216 }
8217
8218 barrier();
8219
8220 /* Close gates #2, #3 and #4 */
8221 bnx2x_set_234_gates(bp, true);
8222
c9ee9206
VZ		 8223 /* Poll for IGU VQs for 57712 and newer chips */
8224 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8225 return -EAGAIN;
8226
8227
72fd0718
VZ		 8228 /* TBD: Indicate that "process kill" is in progress to MCP */
8229
8230 /* Clear "unprepared" bit */
8231 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8232 barrier();
8233
8234 /* Make sure all is written to the chip before the reset */
8235 mmiowb();
8236
8237 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8238 * PSWHST, GRC and PSWRD Tetris buffer.
8239 */
c9ee9206 8240 usleep_range(1000, 1000);
72fd0718
VZ		 8241
8242 /* Prepare to chip reset: */
8243 /* MCP */
c9ee9206
VZ		 8244 if (global)
8245 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 8246
8247 /* PXP */
8248 bnx2x_pxp_prep(bp);
8249 barrier();
8250
8251 /* reset the chip */
c9ee9206 8252 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 8253 barrier();
8254
8255 /* Recover after reset: */
8256 /* MCP */
c9ee9206 8257 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 8258 return -EAGAIN;
8259
c9ee9206
VZ		 8260 /* TBD: Add resetting the NO_MCP mode DB here */
8261
72fd0718
VZ		 8262 /* PXP */
8263 bnx2x_pxp_prep(bp);
8264
8265 /* Open the gates #2, #3 and #4 */
8266 bnx2x_set_234_gates(bp, false);
8267
8268 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8269 * reset state, re-enable attentions. */
8270
a2fbb9ea
ET		 8271 return 0;
8272}
8273
c9ee9206 8274int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 8275{
8276 int rc = 0;
c9ee9206
VZ		 8277 bool global = bnx2x_reset_is_global(bp);
8278
72fd0718 8279 /* Try to recover after the failure */
c9ee9206
VZ		 8280 if (bnx2x_process_kill(bp, global)) {
8281 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8282 "Aii!\n", BP_PATH(bp));
72fd0718
VZ		 8283 rc = -EAGAIN;
8284 goto exit_leader_reset;
8285 }
8286
c9ee9206
VZ		 8287 /*
8288 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8289 * state.
8290 */
72fd0718 8291 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 8292 if (global)
8293 bnx2x_clear_reset_global(bp);
72fd0718
VZ		 8294
8295exit_leader_reset:
8296 bp->is_leader = 0;
c9ee9206
VZ		 8297 bnx2x_release_leader_lock(bp);
8298 smp_mb();
72fd0718
VZ		 8299 return rc;
8300}
8301
c9ee9206
VZ		 8302static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8303{
8304 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8305
8306 /* Disconnect this device */
8307 netif_device_detach(bp->dev);
8308
8309 /*
8310 * Block ifup for all function on this engine until "process kill"
8311 * or power cycle.
8312 */
8313 bnx2x_set_reset_in_progress(bp);
8314
8315 /* Shut down the power */
8316 bnx2x_set_power_state(bp, PCI_D3hot);
8317
8318 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8319
8320 smp_mb();
8321}
8322
8323/*
8324 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 8325 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 8326 * will never be called when netif_running(bp->dev) is false.
8327 */
8328static void bnx2x_parity_recover(struct bnx2x *bp)
8329{
c9ee9206
VZ		 8330 bool global = false;
8331
72fd0718
VZ		 8332 DP(NETIF_MSG_HW, "Handling parity\n");
8333 while (1) {
8334 switch (bp->recovery_state) {
8335 case BNX2X_RECOVERY_INIT:
8336 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
c9ee9206
VZ		 8337 bnx2x_chk_parity_attn(bp, &global, false);
8338
72fd0718 8339 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 8340 if (bnx2x_trylock_leader_lock(bp)) {
8341 bnx2x_set_reset_in_progress(bp);
8342 /*
8343 * Check if there is a global attention and if
8344 * there was a global attention, set the global
8345 * reset bit.
8346 */
8347
8348 if (global)
8349 bnx2x_set_reset_global(bp);
8350
72fd0718 8351 bp->is_leader = 1;
c9ee9206 8352 }
72fd0718
VZ		 8353
8354 /* Stop the driver */
8355 /* If interface has been removed - break */
8356 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8357 return;
8358
8359 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206
VZ		 8360
8361 /*
8362 * Reset MCP command sequence number and MCP mail box
8363 * sequence as we are going to reset the MCP.
8364 */
8365 if (global) {
8366 bp->fw_seq = 0;
8367 bp->fw_drv_pulse_wr_seq = 0;
8368 }
8369
8370 /* Ensure "is_leader", MCP command sequence and
8371 * "recovery_state" update values are seen on other
8372 * CPUs.
72fd0718 8373 */
c9ee9206 8374 smp_mb();
72fd0718
VZ		 8375 break;
8376
8377 case BNX2X_RECOVERY_WAIT:
8378 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8379 if (bp->is_leader) {
c9ee9206
VZ		 8380 int other_engine = BP_PATH(bp) ? 0 : 1;
8381 u32 other_load_counter =
8382 bnx2x_get_load_cnt(bp, other_engine);
8383 u32 load_counter =
8384 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8385 global = bnx2x_reset_is_global(bp);
8386
8387 /*
8388 * In case of a parity in a global block, let
8389 * the first leader that performs a
8390 * leader_reset() reset the global blocks in
8391 * order to clear global attentions. Otherwise
8392 * the the gates will remain closed for that
8393 * engine.
8394 */
8395 if (load_counter ||
8396 (global && other_load_counter)) {
72fd0718
VZ		 8397 /* Wait until all other functions get
8398 * down.
8399 */
7be08a72 8400 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8401 HZ/10);
8402 return;
8403 } else {
8404 /* If all other functions got down -
8405 * try to bring the chip back to
8406 * normal. In any case it's an exit
8407 * point for a leader.
8408 */
c9ee9206
VZ		 8409 if (bnx2x_leader_reset(bp)) {
8410 bnx2x_recovery_failed(bp);
72fd0718
VZ		 8411 return;
8412 }
8413
c9ee9206
VZ		 8414 /* If we are here, means that the
8415 * leader has succeeded and doesn't
8416 * want to be a leader any more. Try
8417 * to continue as a none-leader.
8418 */
8419 break;
72fd0718
VZ		 8420 }
8421 } else { /* non-leader */
c9ee9206 8422 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 8423 /* Try to get a LEADER_LOCK HW lock as
8424 * long as a former leader may have
8425 * been unloaded by the user or
8426 * released a leadership by another
8427 * reason.
8428 */
c9ee9206 8429 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 8430 /* I'm a leader now! Restart a
8431 * switch case.
8432 */
8433 bp->is_leader = 1;
8434 break;
8435 }
8436
7be08a72 8437 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 8438 HZ/10);
8439 return;
8440
c9ee9206
VZ		 8441 } else {
8442 /*
8443 * If there was a global attention, wait
8444 * for it to be cleared.
8445 */
8446 if (bnx2x_reset_is_global(bp)) {
8447 schedule_delayed_work(
7be08a72
AE		 8448 &bp->sp_rtnl_task,
8449 HZ/10);
c9ee9206
VZ		 8450 return;
8451 }
8452
8453 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8454 bnx2x_recovery_failed(bp);
8455 else {
8456 bp->recovery_state =
8457 BNX2X_RECOVERY_DONE;
8458 smp_mb();
8459 }
8460
72fd0718
VZ		 8461 return;
8462 }
8463 }
8464 default:
8465 return;
8466 }
8467 }
8468}
8469
8470/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8471 * scheduled on a general queue in order to prevent a dead lock.
8472 */
7be08a72 8473static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 8474{
7be08a72 8475 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 8476
8477 rtnl_lock();
8478
8479 if (!netif_running(bp->dev))
7be08a72
AE		 8480 goto sp_rtnl_exit;
8481
8482 /* if stop on error is defined no recovery flows should be executed */
8483#ifdef BNX2X_STOP_ON_ERROR
8484 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8485 "so reset not done to allow debug dump,\n"
8486 "you will need to reboot when done\n");
b1fb8740 8487 goto sp_rtnl_not_reset;
7be08a72 8488#endif
34f80b04 8489
7be08a72
AE		 8490 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8491 /*
b1fb8740
VZ		 8492 * Clear all pending SP commands as we are going to reset the
8493 * function anyway.
7be08a72 8494 */
b1fb8740
VZ		 8495 bp->sp_rtnl_state = 0;
8496 smp_mb();
8497
72fd0718 8498 bnx2x_parity_recover(bp);
b1fb8740
VZ		 8499
8500 goto sp_rtnl_exit;
8501 }
8502
8503 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8504 /*
8505 * Clear all pending SP commands as we are going to reset the
8506 * function anyway.
8507 */
8508 bp->sp_rtnl_state = 0;
8509 smp_mb();
8510
72fd0718
VZ		 8511 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8512 bnx2x_nic_load(bp, LOAD_NORMAL);
b1fb8740
VZ		 8513
8514 goto sp_rtnl_exit;
72fd0718 8515 }
b1fb8740
VZ		 8516#ifdef BNX2X_STOP_ON_ERROR
8517sp_rtnl_not_reset:
8518#endif
8519 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8520 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
34f80b04 8521
8304859a
AE		 8522 /*
8523 * in case of fan failure we need to reset id if the "stop on error"
8524 * debug flag is set, since we trying to prevent permanent overheating
8525 * damage
8526 */
8527 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
5219e4c9 8528 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n");
8304859a
AE		 8529 netif_device_detach(bp->dev);
8530 bnx2x_close(bp->dev);
8531 }
8532
7be08a72 8533sp_rtnl_exit:
34f80b04
EG		 8534 rtnl_unlock();
8535}
8536
a2fbb9ea
ET		 8537/* end of nic load/unload */
8538
3deb8167
YR		 8539static void bnx2x_period_task(struct work_struct *work)
8540{
8541 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8542
8543 if (!netif_running(bp->dev))
8544 goto period_task_exit;
8545
8546 if (CHIP_REV_IS_SLOW(bp)) {
8547 BNX2X_ERR("period task called on emulation, ignoring\n");
8548 goto period_task_exit;
8549 }
8550
8551 bnx2x_acquire_phy_lock(bp);
8552 /*
8553 * The barrier is needed to ensure the ordering between the writing to
8554 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8555 * the reading here.
8556 */
8557 smp_mb();
8558 if (bp->port.pmf) {
8559 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8560
8561 /* Re-queue task in 1 sec */
8562 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8563 }
8564
8565 bnx2x_release_phy_lock(bp);
8566period_task_exit:
8567 return;
8568}
8569
a2fbb9ea
ET		 8570/*
8571 * Init service functions
8572 */
8573
8d96286a 8574static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 8575{
8576 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8577 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8578 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 8579}
8580
f2e0899f 8581static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
f1ef27ef 8582{
f2e0899f 8583 u32 reg = bnx2x_get_pretend_reg(bp);
f1ef27ef
EG		 8584
8585 /* Flush all outstanding writes */
8586 mmiowb();
8587
8588 /* Pretend to be function 0 */
8589 REG_WR(bp, reg, 0);
f2e0899f 8590 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
f1ef27ef
EG		 8591
8592 /* From now we are in the "like-E1" mode */
8593 bnx2x_int_disable(bp);
8594
8595 /* Flush all outstanding writes */
8596 mmiowb();
8597
f2e0899f
DK		 8598 /* Restore the original function */
8599 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8600 REG_RD(bp, reg);
f1ef27ef
EG		 8601}
8602
f2e0899f 8603static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
f1ef27ef 8604{
f2e0899f 8605 if (CHIP_IS_E1(bp))
f1ef27ef 8606 bnx2x_int_disable(bp);
f2e0899f
DK		 8607 else
8608 bnx2x_undi_int_disable_e1h(bp);
f1ef27ef
EG		 8609}
8610
34f80b04
EG		 8611static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8612{
8613 u32 val;
8614
8615 /* Check if there is any driver already loaded */
8616 val = REG_RD(bp, MISC_REG_UNPREPARED);
8617 if (val == 0x1) {
7a06a122
DK		 8618
8619 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8620 /*
8621 * Check if it is the UNDI driver
34f80b04
EG		 8622 * UNDI driver initializes CID offset for normal bell to 0x7
8623 */
8624 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8625 if (val == 0x7) {
8626 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
f2e0899f
DK		 8627 /* save our pf_num */
8628 int orig_pf_num = bp->pf_num;
619c5cb6
VZ		 8629 int port;
8630 u32 swap_en, swap_val, value;
34f80b04 8631
b4661739
EG		 8632 /* clear the UNDI indication */
8633 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8634
34f80b04
EG		 8635 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8636
8637 /* try unload UNDI on port 0 */
f2e0899f 8638 bp->pf_num = 0;
da5a662a 8639 bp->fw_seq =
f2e0899f 8640 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8641 DRV_MSG_SEQ_NUMBER_MASK);
a22f0788 8642 reset_code = bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8643
8644 /* if UNDI is loaded on the other port */
8645 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8646
da5a662a 8647 /* send "DONE" for previous unload */
a22f0788
YR		 8648 bnx2x_fw_command(bp,
8649 DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8650
8651 /* unload UNDI on port 1 */
f2e0899f 8652 bp->pf_num = 1;
da5a662a 8653 bp->fw_seq =
f2e0899f 8654 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a
VZ		 8655 DRV_MSG_SEQ_NUMBER_MASK);
8656 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8657
a22f0788 8658 bnx2x_fw_command(bp, reset_code, 0);
34f80b04
EG		 8659 }
8660
f2e0899f 8661 bnx2x_undi_int_disable(bp);
619c5cb6 8662 port = BP_PORT(bp);
da5a662a
VZ		 8663
8664 /* close input traffic and wait for it */
8665 /* Do not rcv packets to BRB */
619c5cb6
VZ		 8666 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8667 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
da5a662a
VZ		 8668 /* Do not direct rcv packets that are not for MCP to
8669 * the BRB */
619c5cb6
VZ		 8670 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8671 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
da5a662a 8672 /* clear AEU */
619c5cb6
VZ		 8673 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8674 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
da5a662a
VZ		 8675 msleep(10);
8676
8677 /* save NIG port swap info */
8678 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8679 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
34f80b04
EG		 8680 /* reset device */
8681 REG_WR(bp,
8682 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
da5a662a 8683 0xd3ffffff);
619c5cb6
VZ		 8684
8685 value = 0x1400;
8686 if (CHIP_IS_E3(bp)) {
8687 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8688 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8689 }
8690
34f80b04
EG		 8691 REG_WR(bp,
8692 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
619c5cb6
VZ		 8693 value);
8694
da5a662a
VZ		 8695 /* take the NIG out of reset and restore swap values */
8696 REG_WR(bp,
8697 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8698 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8699 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8700 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8701
8702 /* send unload done to the MCP */
a22f0788 8703 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
da5a662a
VZ		 8704
8705 /* restore our func and fw_seq */
f2e0899f 8706 bp->pf_num = orig_pf_num;
da5a662a 8707 bp->fw_seq =
f2e0899f 8708 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
da5a662a 8709 DRV_MSG_SEQ_NUMBER_MASK);
7a06a122
DK		 8710 }
8711
8712 /* now it's safe to release the lock */
8713 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
34f80b04
EG		 8714 }
8715}
8716
8717static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8718{
8719 u32 val, val2, val3, val4, id;
72ce58c3 8720 u16 pmc;
34f80b04
EG		 8721
8722 /* Get the chip revision id and number. */
8723 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8724 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8725 id = ((val & 0xffff) << 16);
8726 val = REG_RD(bp, MISC_REG_CHIP_REV);
8727 id |= ((val & 0xf) << 12);
8728 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8729 id |= ((val & 0xff) << 4);
5a40e08e 8730 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 8731 id |= (val & 0xf);
8732 bp->common.chip_id = id;
523224a3
DK		 8733
8734 /* Set doorbell size */
8735 bp->db_size = (1 << BNX2X_DB_SHIFT);
8736
619c5cb6 8737 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8738 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8739 if ((val & 1) == 0)
8740 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8741 else
8742 val = (val >> 1) & 1;
8743 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8744 "2_PORT_MODE");
8745 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8746 CHIP_2_PORT_MODE;
8747
8748 if (CHIP_MODE_IS_4_PORT(bp))
8749 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8750 else
8751 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8752 } else {
8753 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8754 bp->pfid = bp->pf_num; /* 0..7 */
8755 }
8756
f2e0899f
DK		 8757 bp->link_params.chip_id = bp->common.chip_id;
8758 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 8759
1c06328c
EG		 8760 val = (REG_RD(bp, 0x2874) & 0x55);
8761 if ((bp->common.chip_id & 0x1) ||
8762 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8763 bp->flags |= ONE_PORT_FLAG;
8764 BNX2X_DEV_INFO("single port device\n");
8765 }
8766
34f80b04 8767 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 8768 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 8769 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8770 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8771 bp->common.flash_size, bp->common.flash_size);
8772
1b6e2ceb
DK		 8773 bnx2x_init_shmem(bp);
8774
619c5cb6
VZ		 8775
8776
f2e0899f
DK		 8777 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8778 MISC_REG_GENERIC_CR_1 :
8779 MISC_REG_GENERIC_CR_0));
1b6e2ceb 8780
34f80b04 8781 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 8782 bp->link_params.shmem2_base = bp->common.shmem2_base;
2691d51d
EG		 8783 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8784 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 8785
f2e0899f 8786 if (!bp->common.shmem_base) {
34f80b04
EG		 8787 BNX2X_DEV_INFO("MCP not active\n");
8788 bp->flags |= NO_MCP_FLAG;
8789 return;
8790 }
8791
34f80b04 8792 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 8793 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 8794
8795 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8796 SHARED_HW_CFG_LED_MODE_MASK) >>
8797 SHARED_HW_CFG_LED_MODE_SHIFT);
8798
c2c8b03e
EG		 8799 bp->link_params.feature_config_flags = 0;
8800 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8801 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8802 bp->link_params.feature_config_flags |=
8803 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8804 else
8805 bp->link_params.feature_config_flags &=
8806 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8807
34f80b04
EG		 8808 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8809 bp->common.bc_ver = val;
8810 BNX2X_DEV_INFO("bc_ver %X\n", val);
8811 if (val < BNX2X_BC_VER) {
8812 /* for now only warn
8813 * later we might need to enforce this */
f2e0899f
DK		 8814 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8815 "please upgrade BC\n", BNX2X_BC_VER, val);
34f80b04 8816 }
4d295db0 8817 bp->link_params.feature_config_flags |=
a22f0788 8818 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 8819 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8820
a22f0788
YR		 8821 bp->link_params.feature_config_flags |=
8822 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8823 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
72ce58c3 8824
85242eea
YR		 8825 bp->link_params.feature_config_flags |=
8826 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8827 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
0e898dd7
BW		 8828 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
8829 BC_SUPPORTS_PFC_STATS : 0;
85242eea 8830
f9a3ebbe
DK		 8831 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8832 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8833
72ce58c3 8834 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 8835 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 8836
8837 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8838 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8839 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8840 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8841
cdaa7cb8
VZ		 8842 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8843 val, val2, val3, val4);
34f80b04
EG		 8844}
8845
f2e0899f
DK		 8846#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8847#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8848
8849static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8850{
8851 int pfid = BP_FUNC(bp);
f2e0899f
DK		 8852 int igu_sb_id;
8853 u32 val;
6383c0b3 8854 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 8855
8856 bp->igu_base_sb = 0xff;
f2e0899f 8857 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 8858 int vn = BP_VN(bp);
6383c0b3 8859 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 8860 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8861 FP_SB_MAX_E1x;
8862
8863 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8864 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8865
8866 return;
8867 }
8868
8869 /* IGU in normal mode - read CAM */
8870 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8871 igu_sb_id++) {
8872 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8873 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8874 continue;
8875 fid = IGU_FID(val);
8876 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8877 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8878 continue;
8879 if (IGU_VEC(val) == 0)
8880 /* default status block */
8881 bp->igu_dsb_id = igu_sb_id;
8882 else {
8883 if (bp->igu_base_sb == 0xff)
8884 bp->igu_base_sb = igu_sb_id;
6383c0b3 8885 igu_sb_cnt++;
f2e0899f
DK		 8886 }
8887 }
8888 }
619c5cb6 8889
6383c0b3
AE		 8890#ifdef CONFIG_PCI_MSI
8891 /*
8892 * It's expected that number of CAM entries for this functions is equal
8893 * to the number evaluated based on the MSI-X table size. We want a
8894 * harsh warning if these values are different!
619c5cb6 8895 */
6383c0b3
AE		 8896 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8897#endif
619c5cb6 8898
6383c0b3 8899 if (igu_sb_cnt == 0)
f2e0899f
DK		 8900 BNX2X_ERR("CAM configuration error\n");
8901}
8902
34f80b04
EG		 8903static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8904 u32 switch_cfg)
a2fbb9ea 8905{
a22f0788
YR		 8906 int cfg_size = 0, idx, port = BP_PORT(bp);
8907
8908 /* Aggregation of supported attributes of all external phys */
8909 bp->port.supported[0] = 0;
8910 bp->port.supported[1] = 0;
b7737c9b
YR		 8911 switch (bp->link_params.num_phys) {
8912 case 1:
a22f0788
YR		 8913 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8914 cfg_size = 1;
8915 break;
b7737c9b 8916 case 2:
a22f0788
YR		 8917 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8918 cfg_size = 1;
8919 break;
8920 case 3:
8921 if (bp->link_params.multi_phy_config &
8922 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8923 bp->port.supported[1] =
8924 bp->link_params.phy[EXT_PHY1].supported;
8925 bp->port.supported[0] =
8926 bp->link_params.phy[EXT_PHY2].supported;
8927 } else {
8928 bp->port.supported[0] =
8929 bp->link_params.phy[EXT_PHY1].supported;
8930 bp->port.supported[1] =
8931 bp->link_params.phy[EXT_PHY2].supported;
8932 }
8933 cfg_size = 2;
8934 break;
b7737c9b 8935 }
a2fbb9ea 8936
a22f0788 8937 if (!(bp->port.supported[0] || bp->port.supported[1])) {
b7737c9b 8938 BNX2X_ERR("NVRAM config error. BAD phy config."
a22f0788 8939 "PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 8940 SHMEM_RD(bp,
a22f0788
YR		 8941 dev_info.port_hw_config[port].external_phy_config),
8942 SHMEM_RD(bp,
8943 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 8944 return;
f85582f8 8945 }
a2fbb9ea 8946
619c5cb6
VZ		 8947 if (CHIP_IS_E3(bp))
8948 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8949 else {
8950 switch (switch_cfg) {
8951 case SWITCH_CFG_1G:
8952 bp->port.phy_addr = REG_RD(
8953 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8954 break;
8955 case SWITCH_CFG_10G:
8956 bp->port.phy_addr = REG_RD(
8957 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8958 break;
8959 default:
8960 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8961 bp->port.link_config[0]);
8962 return;
8963 }
a2fbb9ea 8964 }
619c5cb6 8965 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 8966 /* mask what we support according to speed_cap_mask per configuration */
8967 for (idx = 0; idx < cfg_size; idx++) {
8968 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8969 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 8970 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 8971
a22f0788 8972 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8973 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 8974 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 8975
a22f0788 8976 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8977 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 8978 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 8979
a22f0788 8980 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8981 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 8982 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 8983
a22f0788 8984 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8985 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 8986 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 8987 SUPPORTED_1000baseT_Full);
a2fbb9ea 8988
a22f0788 8989 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8990 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 8991 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 8992
a22f0788 8993 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 8994 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788
YR		 8995 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8996
8997 }
a2fbb9ea 8998
a22f0788
YR		 8999 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9000 bp->port.supported[1]);
a2fbb9ea
ET		 9001}
9002
34f80b04 9003static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 9004{
a22f0788
YR		 9005 u32 link_config, idx, cfg_size = 0;
9006 bp->port.advertising[0] = 0;
9007 bp->port.advertising[1] = 0;
9008 switch (bp->link_params.num_phys) {
9009 case 1:
9010 case 2:
9011 cfg_size = 1;
9012 break;
9013 case 3:
9014 cfg_size = 2;
9015 break;
9016 }
9017 for (idx = 0; idx < cfg_size; idx++) {
9018 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9019 link_config = bp->port.link_config[idx];
9020 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 9021 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 9022 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9023 bp->link_params.req_line_speed[idx] =
9024 SPEED_AUTO_NEG;
9025 bp->port.advertising[idx] |=
9026 bp->port.supported[idx];
f85582f8
DK		 9027 } else {
9028 /* force 10G, no AN */
a22f0788
YR		 9029 bp->link_params.req_line_speed[idx] =
9030 SPEED_10000;
9031 bp->port.advertising[idx] |=
9032 (ADVERTISED_10000baseT_Full |
f85582f8 9033 ADVERTISED_FIBRE);
a22f0788 9034 continue;
f85582f8
DK		 9035 }
9036 break;
a2fbb9ea 9037
f85582f8 9038 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 9039 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9040 bp->link_params.req_line_speed[idx] =
9041 SPEED_10;
9042 bp->port.advertising[idx] |=
9043 (ADVERTISED_10baseT_Full |
f85582f8
DK		 9044 ADVERTISED_TP);
9045 } else {
754a2f52 9046 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9047 "Invalid link_config 0x%x"
9048 " speed_cap_mask 0x%x\n",
9049 link_config,
a22f0788 9050 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9051 return;
9052 }
9053 break;
a2fbb9ea 9054
f85582f8 9055 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 9056 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9057 bp->link_params.req_line_speed[idx] =
9058 SPEED_10;
9059 bp->link_params.req_duplex[idx] =
9060 DUPLEX_HALF;
9061 bp->port.advertising[idx] |=
9062 (ADVERTISED_10baseT_Half |
f85582f8
DK		 9063 ADVERTISED_TP);
9064 } else {
754a2f52 9065 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9066 "Invalid link_config 0x%x"
9067 " speed_cap_mask 0x%x\n",
9068 link_config,
9069 bp->link_params.speed_cap_mask[idx]);
9070 return;
9071 }
9072 break;
a2fbb9ea 9073
f85582f8
DK		 9074 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9075 if (bp->port.supported[idx] &
9076 SUPPORTED_100baseT_Full) {
a22f0788
YR		 9077 bp->link_params.req_line_speed[idx] =
9078 SPEED_100;
9079 bp->port.advertising[idx] |=
9080 (ADVERTISED_100baseT_Full |
f85582f8
DK		 9081 ADVERTISED_TP);
9082 } else {
754a2f52 9083 BNX2X_ERR("NVRAM config error. "
f85582f8
DK		 9084 "Invalid link_config 0x%x"
9085 " speed_cap_mask 0x%x\n",
9086 link_config,
9087 bp->link_params.speed_cap_mask[idx]);
9088 return;
9089 }
9090 break;
a2fbb9ea 9091
f85582f8
DK		 9092 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9093 if (bp->port.supported[idx] &
9094 SUPPORTED_100baseT_Half) {
9095 bp->link_params.req_line_speed[idx] =
9096 SPEED_100;
9097 bp->link_params.req_duplex[idx] =
9098 DUPLEX_HALF;
a22f0788
YR		 9099 bp->port.advertising[idx] |=
9100 (ADVERTISED_100baseT_Half |
f85582f8
DK		 9101 ADVERTISED_TP);
9102 } else {
754a2f52 9103 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9104 "Invalid link_config 0x%x"
9105 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9106 link_config,
9107 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9108 return;
9109 }
9110 break;
a2fbb9ea 9111
f85582f8 9112 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 9113 if (bp->port.supported[idx] &
9114 SUPPORTED_1000baseT_Full) {
9115 bp->link_params.req_line_speed[idx] =
9116 SPEED_1000;
9117 bp->port.advertising[idx] |=
9118 (ADVERTISED_1000baseT_Full |
f85582f8
DK		 9119 ADVERTISED_TP);
9120 } else {
754a2f52 9121 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9122 "Invalid link_config 0x%x"
9123 " speed_cap_mask 0x%x\n",
a22f0788
YR		 9124 link_config,
9125 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 9126 return;
9127 }
9128 break;
a2fbb9ea 9129
f85582f8 9130 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 9131 if (bp->port.supported[idx] &
9132 SUPPORTED_2500baseX_Full) {
9133 bp->link_params.req_line_speed[idx] =
9134 SPEED_2500;
9135 bp->port.advertising[idx] |=
9136 (ADVERTISED_2500baseX_Full |
34f80b04 9137 ADVERTISED_TP);
f85582f8 9138 } else {
754a2f52 9139 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9140 "Invalid link_config 0x%x"
9141 " speed_cap_mask 0x%x\n",
a22f0788 9142 link_config,
f85582f8
DK		 9143 bp->link_params.speed_cap_mask[idx]);
9144 return;
9145 }
9146 break;
a2fbb9ea 9147
f85582f8 9148 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 9149 if (bp->port.supported[idx] &
9150 SUPPORTED_10000baseT_Full) {
9151 bp->link_params.req_line_speed[idx] =
9152 SPEED_10000;
9153 bp->port.advertising[idx] |=
9154 (ADVERTISED_10000baseT_Full |
34f80b04 9155 ADVERTISED_FIBRE);
f85582f8 9156 } else {
754a2f52 9157 BNX2X_ERR("NVRAM config error. "
cdaa7cb8
VZ		 9158 "Invalid link_config 0x%x"
9159 " speed_cap_mask 0x%x\n",
a22f0788 9160 link_config,
f85582f8
DK		 9161 bp->link_params.speed_cap_mask[idx]);
9162 return;
9163 }
9164 break;
3c9ada22
YR		 9165 case PORT_FEATURE_LINK_SPEED_20G:
9166 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 9167
3c9ada22 9168 break;
f85582f8 9169 default:
754a2f52
DK		 9170 BNX2X_ERR("NVRAM config error. "
9171 "BAD link speed link_config 0x%x\n",
9172 link_config);
f85582f8
DK		 9173 bp->link_params.req_line_speed[idx] =
9174 SPEED_AUTO_NEG;
9175 bp->port.advertising[idx] =
9176 bp->port.supported[idx];
9177 break;
9178 }
a2fbb9ea 9179
a22f0788 9180 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 9181 PORT_FEATURE_FLOW_CONTROL_MASK);
a22f0788
YR		 9182 if ((bp->link_params.req_flow_ctrl[idx] ==
9183 BNX2X_FLOW_CTRL_AUTO) &&
9184 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9185 bp->link_params.req_flow_ctrl[idx] =
9186 BNX2X_FLOW_CTRL_NONE;
9187 }
a2fbb9ea 9188
a22f0788
YR		 9189 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9190 " 0x%x advertising 0x%x\n",
9191 bp->link_params.req_line_speed[idx],
9192 bp->link_params.req_duplex[idx],
9193 bp->link_params.req_flow_ctrl[idx],
9194 bp->port.advertising[idx]);
9195 }
a2fbb9ea
ET		 9196}
9197
e665bfda
MC		 9198static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9199{
9200 mac_hi = cpu_to_be16(mac_hi);
9201 mac_lo = cpu_to_be32(mac_lo);
9202 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9203 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9204}
9205
34f80b04 9206static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 9207{
34f80b04 9208 int port = BP_PORT(bp);
589abe3a 9209 u32 config;
6f38ad93 9210 u32 ext_phy_type, ext_phy_config;
a2fbb9ea 9211
c18487ee 9212 bp->link_params.bp = bp;
34f80b04 9213 bp->link_params.port = port;
c18487ee 9214
c18487ee 9215 bp->link_params.lane_config =
a2fbb9ea 9216 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 9217
a22f0788 9218 bp->link_params.speed_cap_mask[0] =
a2fbb9ea
ET		 9219 SHMEM_RD(bp,
9220 dev_info.port_hw_config[port].speed_capability_mask);
a22f0788
YR		 9221 bp->link_params.speed_cap_mask[1] =
9222 SHMEM_RD(bp,
9223 dev_info.port_hw_config[port].speed_capability_mask2);
9224 bp->port.link_config[0] =
a2fbb9ea
ET		 9225 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9226
a22f0788
YR		 9227 bp->port.link_config[1] =
9228 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 9229
a22f0788
YR		 9230 bp->link_params.multi_phy_config =
9231 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 9232 /* If the device is capable of WoL, set the default state according
9233 * to the HW
9234 */
4d295db0 9235 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 9236 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9237 (config & PORT_FEATURE_WOL_ENABLED));
9238
f85582f8 9239 BNX2X_DEV_INFO("lane_config 0x%08x "
a22f0788 9240 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 9241 bp->link_params.lane_config,
a22f0788
YR		 9242 bp->link_params.speed_cap_mask[0],
9243 bp->port.link_config[0]);
a2fbb9ea 9244
a22f0788 9245 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 9246 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 9247 bnx2x_phy_probe(&bp->link_params);
c18487ee 9248 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 9249
9250 bnx2x_link_settings_requested(bp);
9251
01cd4528
EG		 9252 /*
9253 * If connected directly, work with the internal PHY, otherwise, work
9254 * with the external PHY
9255 */
b7737c9b
YR		 9256 ext_phy_config =
9257 SHMEM_RD(bp,
9258 dev_info.port_hw_config[port].external_phy_config);
9259 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 9260 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 9261 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 9262
9263 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9264 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9265 bp->mdio.prtad =
b7737c9b 9266 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d
YR		 9267
9268 /*
9269 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9270 * In MF mode, it is set to cover self test cases
9271 */
9272 if (IS_MF(bp))
9273 bp->port.need_hw_lock = 1;
9274 else
9275 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9276 bp->common.shmem_base,
9277 bp->common.shmem2_base);
0793f83f 9278}
01cd4528 9279
2ba45142 9280#ifdef BCM_CNIC
b306f5ed 9281void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 9282{
bf61ee14 9283 int port = BP_PORT(bp);
bf61ee14 9284
2ba45142 9285 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 9286 drv_lic_key[port].max_iscsi_conn);
2ba45142 9287
b306f5ed 9288 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 9289 bp->cnic_eth_dev.max_iscsi_conn =
9290 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9291 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9292
b306f5ed
DK		 9293 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9294 bp->cnic_eth_dev.max_iscsi_conn);
9295
9296 /*
9297 * If maximum allowed number of connections is zero -
9298 * disable the feature.
9299 */
9300 if (!bp->cnic_eth_dev.max_iscsi_conn)
9301 bp->flags |= NO_ISCSI_FLAG;
9302}
9303
9304static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
9305{
9306 int port = BP_PORT(bp);
9307 int func = BP_ABS_FUNC(bp);
9308
9309 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9310 drv_lic_key[port].max_fcoe_conn);
9311
9312 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 9313 bp->cnic_eth_dev.max_fcoe_conn =
9314 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9315 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9316
bf61ee14
VZ		 9317 /* Read the WWN: */
9318 if (!IS_MF(bp)) {
9319 /* Port info */
9320 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9321 SHMEM_RD(bp,
9322 dev_info.port_hw_config[port].
9323 fcoe_wwn_port_name_upper);
9324 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9325 SHMEM_RD(bp,
9326 dev_info.port_hw_config[port].
9327 fcoe_wwn_port_name_lower);
9328
9329 /* Node info */
9330 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9331 SHMEM_RD(bp,
9332 dev_info.port_hw_config[port].
9333 fcoe_wwn_node_name_upper);
9334 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9335 SHMEM_RD(bp,
9336 dev_info.port_hw_config[port].
9337 fcoe_wwn_node_name_lower);
9338 } else if (!IS_MF_SD(bp)) {
9339 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9340
9341 /*
9342 * Read the WWN info only if the FCoE feature is enabled for
9343 * this function.
9344 */
9345 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9346 /* Port info */
9347 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9348 MF_CFG_RD(bp, func_ext_config[func].
9349 fcoe_wwn_port_name_upper);
9350 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9351 MF_CFG_RD(bp, func_ext_config[func].
9352 fcoe_wwn_port_name_lower);
9353
9354 /* Node info */
9355 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9356 MF_CFG_RD(bp, func_ext_config[func].
9357 fcoe_wwn_node_name_upper);
9358 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9359 MF_CFG_RD(bp, func_ext_config[func].
9360 fcoe_wwn_node_name_lower);
9361 }
9362 }
9363
b306f5ed 9364 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 9365
bf61ee14
VZ		 9366 /*
9367 * If maximum allowed number of connections is zero -
2ba45142
VZ		 9368 * disable the feature.
9369 */
2ba45142
VZ		 9370 if (!bp->cnic_eth_dev.max_fcoe_conn)
9371 bp->flags |= NO_FCOE_FLAG;
9372}
b306f5ed
DK		 9373
9374static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9375{
9376 /*
9377 * iSCSI may be dynamically disabled but reading
9378 * info here we will decrease memory usage by driver
9379 * if the feature is disabled for good
9380 */
9381 bnx2x_get_iscsi_info(bp);
9382 bnx2x_get_fcoe_info(bp);
9383}
2ba45142
VZ		 9384#endif
9385
0793f83f
DK		 9386static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9387{
9388 u32 val, val2;
9389 int func = BP_ABS_FUNC(bp);
9390 int port = BP_PORT(bp);
2ba45142
VZ		 9391#ifdef BCM_CNIC
9392 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9393 u8 *fip_mac = bp->fip_mac;
9394#endif
0793f83f 9395
619c5cb6
VZ		 9396 /* Zero primary MAC configuration */
9397 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9398
0793f83f
DK		 9399 if (BP_NOMCP(bp)) {
9400 BNX2X_ERROR("warning: random MAC workaround active\n");
9401 random_ether_addr(bp->dev->dev_addr);
9402 } else if (IS_MF(bp)) {
9403 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9404 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9405 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9406 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9407 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
37b091ba
MC		 9408
9409#ifdef BCM_CNIC
614c76df
DK		 9410 /*
9411 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142
VZ		 9412 * FCoE MAC then the appropriate feature should be disabled.
9413 */
0793f83f
DK		 9414 if (IS_MF_SI(bp)) {
9415 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9416 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9417 val2 = MF_CFG_RD(bp, func_ext_config[func].
9418 iscsi_mac_addr_upper);
9419 val = MF_CFG_RD(bp, func_ext_config[func].
9420 iscsi_mac_addr_lower);
2ba45142 9421 bnx2x_set_mac_buf(iscsi_mac, val, val2);
0f9dad10
JP		 9422 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9423 iscsi_mac);
2ba45142
VZ		 9424 } else
9425 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9426
9427 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9428 val2 = MF_CFG_RD(bp, func_ext_config[func].
9429 fcoe_mac_addr_upper);
9430 val = MF_CFG_RD(bp, func_ext_config[func].
9431 fcoe_mac_addr_lower);
2ba45142 9432 bnx2x_set_mac_buf(fip_mac, val, val2);
614c76df 9433 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
0f9dad10 9434 fip_mac);
2ba45142 9435
2ba45142
VZ		 9436 } else
9437 bp->flags |= NO_FCOE_FLAG;
614c76df
DK		 9438 } else { /* SD mode */
9439 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp)) {
9440 /* use primary mac as iscsi mac */
9441 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
9442 /* Zero primary MAC configuration */
9443 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9444
9445 BNX2X_DEV_INFO("SD ISCSI MODE\n");
9446 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9447 iscsi_mac);
9448 }
0793f83f 9449 }
37b091ba 9450#endif
0793f83f
DK		 9451 } else {
9452 /* in SF read MACs from port configuration */
9453 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9454 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9455 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9456
9457#ifdef BCM_CNIC
9458 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9459 iscsi_mac_upper);
9460 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9461 iscsi_mac_lower);
2ba45142 9462 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 9463
9464 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9465 fcoe_fip_mac_upper);
9466 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9467 fcoe_fip_mac_lower);
9468 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 9469#endif
9470 }
9471
9472 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9473 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9474
ec6ba945 9475#ifdef BCM_CNIC
c03bd39c
VZ		 9476 /* Set the FCoE MAC in MF_SD mode */
9477 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9478 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
426b9241
DK		 9479
9480 /* Disable iSCSI if MAC configuration is
9481 * invalid.
9482 */
9483 if (!is_valid_ether_addr(iscsi_mac)) {
9484 bp->flags |= NO_ISCSI_FLAG;
9485 memset(iscsi_mac, 0, ETH_ALEN);
9486 }
9487
9488 /* Disable FCoE if MAC configuration is
9489 * invalid.
9490 */
9491 if (!is_valid_ether_addr(fip_mac)) {
9492 bp->flags |= NO_FCOE_FLAG;
9493 memset(bp->fip_mac, 0, ETH_ALEN);
9494 }
ec6ba945 9495#endif
619c5cb6 9496
614c76df 9497 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
619c5cb6
VZ		 9498 dev_err(&bp->pdev->dev,
9499 "bad Ethernet MAC address configuration: "
0f9dad10 9500 "%pM, change it manually before bringing up "
619c5cb6 9501 "the appropriate network interface\n",
0f9dad10 9502 bp->dev->dev_addr);
34f80b04
EG		 9503}
9504
9505static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9506{
0793f83f 9507 int /*abs*/func = BP_ABS_FUNC(bp);
b8ee8328 9508 int vn;
0793f83f 9509 u32 val = 0;
34f80b04 9510 int rc = 0;
a2fbb9ea 9511
34f80b04 9512 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 9513
6383c0b3
AE		 9514 /*
9515 * initialize IGU parameters
9516 */
f2e0899f
DK		 9517 if (CHIP_IS_E1x(bp)) {
9518 bp->common.int_block = INT_BLOCK_HC;
9519
9520 bp->igu_dsb_id = DEF_SB_IGU_ID;
9521 bp->igu_base_sb = 0;
f2e0899f
DK		 9522 } else {
9523 bp->common.int_block = INT_BLOCK_IGU;
7a06a122
DK		 9524
9525 /* do not allow device reset during IGU info preocessing */
9526 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9527
f2e0899f 9528 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 9529
9530 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9531 int tout = 5000;
9532
9533 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9534
9535 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9536 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9537 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9538
9539 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9540 tout--;
9541 usleep_range(1000, 1000);
9542 }
9543
9544 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9545 dev_err(&bp->pdev->dev,
9546 "FORCING Normal Mode failed!!!\n");
9547 return -EPERM;
9548 }
9549 }
9550
f2e0899f 9551 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 9552 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 9553 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9554 } else
619c5cb6 9555 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 9556
f2e0899f
DK		 9557 bnx2x_get_igu_cam_info(bp);
9558
7a06a122 9559 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
f2e0899f 9560 }
619c5cb6
VZ		 9561
9562 /*
9563 * set base FW non-default (fast path) status block id, this value is
9564 * used to initialize the fw_sb_id saved on the fp/queue structure to
9565 * determine the id used by the FW.
9566 */
9567 if (CHIP_IS_E1x(bp))
9568 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9569 else /*
9570 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9571 * the same queue are indicated on the same IGU SB). So we prefer
9572 * FW and IGU SBs to be the same value.
9573 */
9574 bp->base_fw_ndsb = bp->igu_base_sb;
9575
9576 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9577 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9578 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 9579
9580 /*
9581 * Initialize MF configuration
9582 */
523224a3 9583
fb3bff17
DK		 9584 bp->mf_ov = 0;
9585 bp->mf_mode = 0;
3395a033 9586 vn = BP_VN(bp);
0793f83f 9587
f2e0899f 9588 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 9589 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9590 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9591 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9592
f2e0899f
DK		 9593 if (SHMEM2_HAS(bp, mf_cfg_addr))
9594 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9595 else
9596 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 9597 offsetof(struct shmem_region, func_mb) +
9598 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 9599 /*
9600 * get mf configuration:
25985edc 9601 * 1. existence of MF configuration
0793f83f
DK		 9602 * 2. MAC address must be legal (check only upper bytes)
9603 * for Switch-Independent mode;
9604 * OVLAN must be legal for Switch-Dependent mode
9605 * 3. SF_MODE configures specific MF mode
9606 */
9607 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9608 /* get mf configuration */
9609 val = SHMEM_RD(bp,
9610 dev_info.shared_feature_config.config);
9611 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9612
9613 switch (val) {
9614 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9615 val = MF_CFG_RD(bp, func_mf_config[func].
9616 mac_upper);
9617 /* check for legal mac (upper bytes)*/
9618 if (val != 0xffff) {
9619 bp->mf_mode = MULTI_FUNCTION_SI;
9620 bp->mf_config[vn] = MF_CFG_RD(bp,
9621 func_mf_config[func].config);
9622 } else
619c5cb6
VZ		 9623 BNX2X_DEV_INFO("illegal MAC address "
9624 "for SI\n");
0793f83f
DK		 9625 break;
9626 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9627 /* get OV configuration */
9628 val = MF_CFG_RD(bp,
9629 func_mf_config[FUNC_0].e1hov_tag);
9630 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9631
9632 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9633 bp->mf_mode = MULTI_FUNCTION_SD;
9634 bp->mf_config[vn] = MF_CFG_RD(bp,
9635 func_mf_config[func].config);
9636 } else
754a2f52 9637 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f
DK		 9638 break;
9639 default:
9640 /* Unknown configuration: reset mf_config */
9641 bp->mf_config[vn] = 0;
754a2f52 9642 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
0793f83f
DK		 9643 }
9644 }
a2fbb9ea 9645
2691d51d 9646 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 9647 IS_MF(bp) ? "multi" : "single");
2691d51d 9648
0793f83f
DK		 9649 switch (bp->mf_mode) {
9650 case MULTI_FUNCTION_SD:
9651 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9652 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 9653 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 9654 bp->mf_ov = val;
619c5cb6
VZ		 9655 bp->path_has_ovlan = true;
9656
9657 BNX2X_DEV_INFO("MF OV for func %d is %d "
9658 "(0x%04x)\n", func, bp->mf_ov,
9659 bp->mf_ov);
2691d51d 9660 } else {
619c5cb6
VZ		 9661 dev_err(&bp->pdev->dev,
9662 "No valid MF OV for func %d, "
9663 "aborting\n", func);
9664 return -EPERM;
34f80b04 9665 }
0793f83f
DK		 9666 break;
9667 case MULTI_FUNCTION_SI:
9668 BNX2X_DEV_INFO("func %d is in MF "
9669 "switch-independent mode\n", func);
9670 break;
9671 default:
9672 if (vn) {
619c5cb6
VZ		 9673 dev_err(&bp->pdev->dev,
9674 "VN %d is in a single function mode, "
9675 "aborting\n", vn);
9676 return -EPERM;
2691d51d 9677 }
0793f83f 9678 break;
34f80b04 9679 }
0793f83f 9680
619c5cb6
VZ		 9681 /* check if other port on the path needs ovlan:
9682 * Since MF configuration is shared between ports
9683 * Possible mixed modes are only
9684 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9685 */
9686 if (CHIP_MODE_IS_4_PORT(bp) &&
9687 !bp->path_has_ovlan &&
9688 !IS_MF(bp) &&
9689 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9690 u8 other_port = !BP_PORT(bp);
9691 u8 other_func = BP_PATH(bp) + 2*other_port;
9692 val = MF_CFG_RD(bp,
9693 func_mf_config[other_func].e1hov_tag);
9694 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9695 bp->path_has_ovlan = true;
9696 }
34f80b04 9697 }
a2fbb9ea 9698
f2e0899f
DK		 9699 /* adjust igu_sb_cnt to MF for E1x */
9700 if (CHIP_IS_E1x(bp) && IS_MF(bp))
523224a3
DK		 9701 bp->igu_sb_cnt /= E1HVN_MAX;
9702
619c5cb6
VZ		 9703 /* port info */
9704 bnx2x_get_port_hwinfo(bp);
f2e0899f 9705
0793f83f
DK		 9706 /* Get MAC addresses */
9707 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 9708
2ba45142
VZ		 9709#ifdef BCM_CNIC
9710 bnx2x_get_cnic_info(bp);
9711#endif
9712
619c5cb6
VZ		 9713 /* Get current FW pulse sequence */
9714 if (!BP_NOMCP(bp)) {
9715 int mb_idx = BP_FW_MB_IDX(bp);
9716
9717 bp->fw_drv_pulse_wr_seq =
9718 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9719 DRV_PULSE_SEQ_MASK);
9720 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9721 }
9722
34f80b04
EG		 9723 return rc;
9724}
9725
34f24c7f
VZ		 9726static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9727{
9728 int cnt, i, block_end, rodi;
9729 char vpd_data[BNX2X_VPD_LEN+1];
9730 char str_id_reg[VENDOR_ID_LEN+1];
9731 char str_id_cap[VENDOR_ID_LEN+1];
9732 u8 len;
9733
9734 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9735 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9736
9737 if (cnt < BNX2X_VPD_LEN)
9738 goto out_not_found;
9739
9740 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9741 PCI_VPD_LRDT_RO_DATA);
9742 if (i < 0)
9743 goto out_not_found;
9744
9745
9746 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9747 pci_vpd_lrdt_size(&vpd_data[i]);
9748
9749 i += PCI_VPD_LRDT_TAG_SIZE;
9750
9751 if (block_end > BNX2X_VPD_LEN)
9752 goto out_not_found;
9753
9754 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9755 PCI_VPD_RO_KEYWORD_MFR_ID);
9756 if (rodi < 0)
9757 goto out_not_found;
9758
9759 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9760
9761 if (len != VENDOR_ID_LEN)
9762 goto out_not_found;
9763
9764 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9765
9766 /* vendor specific info */
9767 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9768 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9769 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9770 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9771
9772 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9773 PCI_VPD_RO_KEYWORD_VENDOR0);
9774 if (rodi >= 0) {
9775 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9776
9777 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9778
9779 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9780 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9781 bp->fw_ver[len] = ' ';
9782 }
9783 }
9784 return;
9785 }
9786out_not_found:
9787 return;
9788}
9789
619c5cb6
VZ		 9790static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9791{
9792 u32 flags = 0;
9793
9794 if (CHIP_REV_IS_FPGA(bp))
9795 SET_FLAGS(flags, MODE_FPGA);
9796 else if (CHIP_REV_IS_EMUL(bp))
9797 SET_FLAGS(flags, MODE_EMUL);
9798 else
9799 SET_FLAGS(flags, MODE_ASIC);
9800
9801 if (CHIP_MODE_IS_4_PORT(bp))
9802 SET_FLAGS(flags, MODE_PORT4);
9803 else
9804 SET_FLAGS(flags, MODE_PORT2);
9805
9806 if (CHIP_IS_E2(bp))
9807 SET_FLAGS(flags, MODE_E2);
9808 else if (CHIP_IS_E3(bp)) {
9809 SET_FLAGS(flags, MODE_E3);
9810 if (CHIP_REV(bp) == CHIP_REV_Ax)
9811 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 9812 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9813 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 9814 }
9815
9816 if (IS_MF(bp)) {
9817 SET_FLAGS(flags, MODE_MF);
9818 switch (bp->mf_mode) {
9819 case MULTI_FUNCTION_SD:
9820 SET_FLAGS(flags, MODE_MF_SD);
9821 break;
9822 case MULTI_FUNCTION_SI:
9823 SET_FLAGS(flags, MODE_MF_SI);
9824 break;
9825 }
9826 } else
9827 SET_FLAGS(flags, MODE_SF);
9828
9829#if defined(__LITTLE_ENDIAN)
9830 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9831#else /*(__BIG_ENDIAN)*/
9832 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9833#endif
9834 INIT_MODE_FLAGS(bp) = flags;
9835}
9836
34f80b04
EG		 9837static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9838{
f2e0899f 9839 int func;
87942b46 9840 int timer_interval;
34f80b04
EG		 9841 int rc;
9842
34f80b04 9843 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 9844 mutex_init(&bp->fw_mb_mutex);
bb7e95c8 9845 spin_lock_init(&bp->stats_lock);
993ac7b5
MC		 9846#ifdef BCM_CNIC
9847 mutex_init(&bp->cnic_mutex);
9848#endif
a2fbb9ea 9849
1cf167f2 9850 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 9851 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 9852 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
34f80b04 9853 rc = bnx2x_get_hwinfo(bp);
619c5cb6
VZ		 9854 if (rc)
9855 return rc;
34f80b04 9856
619c5cb6
VZ		 9857 bnx2x_set_modes_bitmap(bp);
9858
9859 rc = bnx2x_alloc_mem_bp(bp);
9860 if (rc)
9861 return rc;
523224a3 9862
34f24c7f 9863 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 9864
9865 func = BP_FUNC(bp);
9866
34f80b04
EG		 9867 /* need to reset chip if undi was active */
9868 if (!BP_NOMCP(bp))
9869 bnx2x_undi_unload(bp);
9870
0735f2fc
DK		 9871 /* init fw_seq after undi_unload! */
9872 if (!BP_NOMCP(bp)) {
9873 bp->fw_seq =
9874 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9875 DRV_MSG_SEQ_NUMBER_MASK);
9876 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9877 }
9878
34f80b04 9879 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 9880 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 9881
9882 if (BP_NOMCP(bp) && (func == 0))
cdaa7cb8
VZ		 9883 dev_err(&bp->pdev->dev, "MCP disabled, "
9884 "must load devices in order!\n");
34f80b04 9885
555f6c78 9886 bp->multi_mode = multi_mode;
555f6c78 9887
614c76df
DK		 9888 bp->disable_tpa = disable_tpa;
9889
9890#ifdef BCM_CNIC
9891 bp->disable_tpa |= IS_MF_ISCSI_SD(bp);
9892#endif
9893
7a9b2557 9894 /* Set TPA flags */
614c76df 9895 if (bp->disable_tpa) {
7a9b2557
VZ		 9896 bp->flags &= ~TPA_ENABLE_FLAG;
9897 bp->dev->features &= ~NETIF_F_LRO;
9898 } else {
9899 bp->flags |= TPA_ENABLE_FLAG;
9900 bp->dev->features |= NETIF_F_LRO;
9901 }
9902
a18f5128
EG		 9903 if (CHIP_IS_E1(bp))
9904 bp->dropless_fc = 0;
9905 else
9906 bp->dropless_fc = dropless_fc;
9907
8d5726c4 9908 bp->mrrs = mrrs;
7a9b2557 9909
34f80b04 9910 bp->tx_ring_size = MAX_TX_AVAIL;
34f80b04 9911
7d323bfd 9912 /* make sure that the numbers are in the right granularity */
523224a3
DK		 9913 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9914 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 9915
87942b46
EG		 9916 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9917 bp->current_interval = (poll ? poll : timer_interval);
34f80b04
EG		 9918
9919 init_timer(&bp->timer);
9920 bp->timer.expires = jiffies + bp->current_interval;
9921 bp->timer.data = (unsigned long) bp;
9922 bp->timer.function = bnx2x_timer;
9923
785b9b1a 9924 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
e4901dde
VZ		 9925 bnx2x_dcbx_init_params(bp);
9926
619c5cb6
VZ		 9927#ifdef BCM_CNIC
9928 if (CHIP_IS_E1x(bp))
9929 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9930 else
9931 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9932#endif
9933
6383c0b3
AE		 9934 /* multiple tx priority */
9935 if (CHIP_IS_E1x(bp))
9936 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9937 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9938 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9939 if (CHIP_IS_E3B0(bp))
9940 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9941
34f80b04 9942 return rc;
a2fbb9ea
ET		 9943}
9944
a2fbb9ea 9945
de0c62db
DK		 9946/****************************************************************************
9947* General service functions
9948****************************************************************************/
a2fbb9ea 9949
619c5cb6
VZ		 9950/*
9951 * net_device service functions
9952 */
9953
bb2a0f7a 9954/* called with rtnl_lock */
a2fbb9ea
ET		 9955static int bnx2x_open(struct net_device *dev)
9956{
9957 struct bnx2x *bp = netdev_priv(dev);
c9ee9206
VZ		 9958 bool global = false;
9959 int other_engine = BP_PATH(bp) ? 0 : 1;
9960 u32 other_load_counter, load_counter;
a2fbb9ea 9961
6eccabb3
EG		 9962 netif_carrier_off(dev);
9963
a2fbb9ea
ET		 9964 bnx2x_set_power_state(bp, PCI_D0);
9965
c9ee9206
VZ		 9966 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9967 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9968
9969 /*
9970 * If parity had happen during the unload, then attentions
9971 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9972 * want the first function loaded on the current engine to
9973 * complete the recovery.
9974 */
9975 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9976 bnx2x_chk_parity_attn(bp, &global, true))
72fd0718 9977 do {
c9ee9206
VZ		 9978 /*
9979 * If there are attentions and they are in a global
9980 * blocks, set the GLOBAL_RESET bit regardless whether
9981 * it will be this function that will complete the
9982 * recovery or not.
72fd0718 9983 */
c9ee9206
VZ		 9984 if (global)
9985 bnx2x_set_reset_global(bp);
72fd0718 9986
c9ee9206
VZ		 9987 /*
9988 * Only the first function on the current engine should
9989 * try to recover in open. In case of attentions in
9990 * global blocks only the first in the chip should try
9991 * to recover.
72fd0718 9992 */
c9ee9206
VZ		 9993 if ((!load_counter &&
9994 (!global || !other_load_counter)) &&
9995 bnx2x_trylock_leader_lock(bp) &&
9996 !bnx2x_leader_reset(bp)) {
9997 netdev_info(bp->dev, "Recovered in open\n");
72fd0718
VZ		 9998 break;
9999 }
10000
c9ee9206 10001 /* recovery has failed... */
72fd0718 10002 bnx2x_set_power_state(bp, PCI_D3hot);
c9ee9206 10003 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 10004
c9ee9206 10005 netdev_err(bp->dev, "Recovery flow hasn't been properly"
72fd0718
VZ		 10006 " completed yet. Try again later. If u still see this"
10007 " message after a few retries then power cycle is"
c9ee9206 10008 " required.\n");
72fd0718
VZ		 10009
10010 return -EAGAIN;
10011 } while (0);
72fd0718
VZ		 10012
10013 bp->recovery_state = BNX2X_RECOVERY_DONE;
bb2a0f7a 10014 return bnx2x_nic_load(bp, LOAD_OPEN);
a2fbb9ea
ET		 10015}
10016
bb2a0f7a 10017/* called with rtnl_lock */
8304859a 10018int bnx2x_close(struct net_device *dev)
a2fbb9ea 10019{
a2fbb9ea
ET		 10020 struct bnx2x *bp = netdev_priv(dev);
10021
10022 /* Unload the driver, release IRQs */
bb2a0f7a 10023 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
c9ee9206
VZ		 10024
10025 /* Power off */
d3dbfee0 10026 bnx2x_set_power_state(bp, PCI_D3hot);
a2fbb9ea
ET		 10027
10028 return 0;
10029}
10030
619c5cb6
VZ		 10031static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
10032 struct bnx2x_mcast_ramrod_params *p)
6e30dd4e 10033{
619c5cb6
VZ		 10034 int mc_count = netdev_mc_count(bp->dev);
10035 struct bnx2x_mcast_list_elem *mc_mac =
10036 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
10037 struct netdev_hw_addr *ha;
6e30dd4e 10038
619c5cb6
VZ		 10039 if (!mc_mac)
10040 return -ENOMEM;
6e30dd4e 10041
619c5cb6 10042 INIT_LIST_HEAD(&p->mcast_list);
6e30dd4e 10043
619c5cb6
VZ		 10044 netdev_for_each_mc_addr(ha, bp->dev) {
10045 mc_mac->mac = bnx2x_mc_addr(ha);
10046 list_add_tail(&mc_mac->link, &p->mcast_list);
10047 mc_mac++;
6e30dd4e 10048 }
619c5cb6
VZ		 10049
10050 p->mcast_list_len = mc_count;
10051
10052 return 0;
6e30dd4e
VZ		 10053}
10054
619c5cb6
VZ		 10055static inline void bnx2x_free_mcast_macs_list(
10056 struct bnx2x_mcast_ramrod_params *p)
10057{
10058 struct bnx2x_mcast_list_elem *mc_mac =
10059 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10060 link);
10061
10062 WARN_ON(!mc_mac);
10063 kfree(mc_mac);
10064}
10065
10066/**
10067 * bnx2x_set_uc_list - configure a new unicast MACs list.
10068 *
10069 * @bp: driver handle
6e30dd4e 10070 *
619c5cb6 10071 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 10072 */
619c5cb6 10073static inline int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 10074{
619c5cb6 10075 int rc;
6e30dd4e 10076 struct net_device *dev = bp->dev;
6e30dd4e 10077 struct netdev_hw_addr *ha;
619c5cb6
VZ		 10078 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10079 unsigned long ramrod_flags = 0;
6e30dd4e 10080
619c5cb6
VZ		 10081 /* First schedule a cleanup up of old configuration */
10082 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10083 if (rc < 0) {
10084 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10085 return rc;
10086 }
6e30dd4e
VZ		 10087
10088 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 10089 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10090 BNX2X_UC_LIST_MAC, &ramrod_flags);
10091 if (rc < 0) {
10092 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10093 rc);
10094 return rc;
6e30dd4e
VZ		 10095 }
10096 }
10097
619c5cb6
VZ		 10098 /* Execute the pending commands */
10099 __set_bit(RAMROD_CONT, &ramrod_flags);
10100 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10101 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 10102}
10103
619c5cb6 10104static inline int bnx2x_set_mc_list(struct bnx2x *bp)
6e30dd4e 10105{
619c5cb6
VZ		 10106 struct net_device *dev = bp->dev;
10107 struct bnx2x_mcast_ramrod_params rparam = {0};
10108 int rc = 0;
6e30dd4e 10109
619c5cb6 10110 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 10111
619c5cb6
VZ		 10112 /* first, clear all configured multicast MACs */
10113 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10114 if (rc < 0) {
10115 BNX2X_ERR("Failed to clear multicast "
10116 "configuration: %d\n", rc);
10117 return rc;
10118 }
6e30dd4e 10119
619c5cb6
VZ		 10120 /* then, configure a new MACs list */
10121 if (netdev_mc_count(dev)) {
10122 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10123 if (rc) {
10124 BNX2X_ERR("Failed to create multicast MACs "
10125 "list: %d\n", rc);
10126 return rc;
10127 }
6e30dd4e 10128
619c5cb6
VZ		 10129 /* Now add the new MACs */
10130 rc = bnx2x_config_mcast(bp, &rparam,
10131 BNX2X_MCAST_CMD_ADD);
10132 if (rc < 0)
10133 BNX2X_ERR("Failed to set a new multicast "
10134 "configuration: %d\n", rc);
6e30dd4e 10135
619c5cb6
VZ		 10136 bnx2x_free_mcast_macs_list(&rparam);
10137 }
6e30dd4e 10138
619c5cb6 10139 return rc;
6e30dd4e
VZ		 10140}
10141
6e30dd4e 10142
619c5cb6 10143/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9f6c9258 10144void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 10145{
10146 struct bnx2x *bp = netdev_priv(dev);
10147 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04
EG		 10148
10149 if (bp->state != BNX2X_STATE_OPEN) {
10150 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10151 return;
10152 }
10153
619c5cb6 10154 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04
EG		 10155
10156 if (dev->flags & IFF_PROMISC)
10157 rx_mode = BNX2X_RX_MODE_PROMISC;
619c5cb6
VZ		 10158 else if ((dev->flags & IFF_ALLMULTI) ||
10159 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10160 CHIP_IS_E1(bp)))
34f80b04 10161 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6e30dd4e
VZ		 10162 else {
10163 /* some multicasts */
619c5cb6 10164 if (bnx2x_set_mc_list(bp) < 0)
6e30dd4e 10165 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 10166
619c5cb6 10167 if (bnx2x_set_uc_list(bp) < 0)
6e30dd4e 10168 rx_mode = BNX2X_RX_MODE_PROMISC;
34f80b04
EG		 10169 }
10170
10171 bp->rx_mode = rx_mode;
614c76df
DK		 10172#ifdef BCM_CNIC
10173 /* handle ISCSI SD mode */
10174 if (IS_MF_ISCSI_SD(bp))
10175 bp->rx_mode = BNX2X_RX_MODE_NONE;
10176#endif
619c5cb6
VZ		 10177
10178 /* Schedule the rx_mode command */
10179 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10180 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10181 return;
10182 }
10183
34f80b04
EG		 10184 bnx2x_set_storm_rx_mode(bp);
10185}
10186
c18487ee 10187/* called with rtnl_lock */
01cd4528
EG		 10188static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10189 int devad, u16 addr)
a2fbb9ea 10190{
01cd4528
EG		 10191 struct bnx2x *bp = netdev_priv(netdev);
10192 u16 value;
10193 int rc;
a2fbb9ea 10194
01cd4528
EG		 10195 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10196 prtad, devad, addr);
a2fbb9ea 10197
01cd4528
EG		 10198 /* The HW expects different devad if CL22 is used */
10199 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 10200
01cd4528 10201 bnx2x_acquire_phy_lock(bp);
e10bc84d 10202 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 10203 bnx2x_release_phy_lock(bp);
10204 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 10205
01cd4528
EG		 10206 if (!rc)
10207 rc = value;
10208 return rc;
10209}
a2fbb9ea 10210
01cd4528
EG		 10211/* called with rtnl_lock */
10212static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10213 u16 addr, u16 value)
10214{
10215 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 10216 int rc;
10217
10218 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10219 " value 0x%x\n", prtad, devad, addr, value);
10220
01cd4528
EG		 10221 /* The HW expects different devad if CL22 is used */
10222 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 10223
01cd4528 10224 bnx2x_acquire_phy_lock(bp);
e10bc84d 10225 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 10226 bnx2x_release_phy_lock(bp);
10227 return rc;
10228}
c18487ee 10229
01cd4528
EG		 10230/* called with rtnl_lock */
10231static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10232{
10233 struct bnx2x *bp = netdev_priv(dev);
10234 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 10235
01cd4528
EG		 10236 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10237 mdio->phy_id, mdio->reg_num, mdio->val_in);
a2fbb9ea 10238
01cd4528
EG		 10239 if (!netif_running(dev))
10240 return -EAGAIN;
10241
10242 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
a2fbb9ea
ET		 10243}
10244
257ddbda 10245#ifdef CONFIG_NET_POLL_CONTROLLER
a2fbb9ea
ET		 10246static void poll_bnx2x(struct net_device *dev)
10247{
10248 struct bnx2x *bp = netdev_priv(dev);
10249
10250 disable_irq(bp->pdev->irq);
10251 bnx2x_interrupt(bp->pdev->irq, dev);
10252 enable_irq(bp->pdev->irq);
10253}
10254#endif
10255
614c76df
DK		 10256static int bnx2x_validate_addr(struct net_device *dev)
10257{
10258 struct bnx2x *bp = netdev_priv(dev);
10259
10260 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr))
10261 return -EADDRNOTAVAIL;
10262 return 0;
10263}
10264
c64213cd
SH		 10265static const struct net_device_ops bnx2x_netdev_ops = {
10266 .ndo_open = bnx2x_open,
10267 .ndo_stop = bnx2x_close,
10268 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 10269 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 10270 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 10271 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 10272 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 10273 .ndo_do_ioctl = bnx2x_ioctl,
10274 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 10275 .ndo_fix_features = bnx2x_fix_features,
10276 .ndo_set_features = bnx2x_set_features,
c64213cd 10277 .ndo_tx_timeout = bnx2x_tx_timeout,
257ddbda 10278#ifdef CONFIG_NET_POLL_CONTROLLER
c64213cd
SH		 10279 .ndo_poll_controller = poll_bnx2x,
10280#endif
6383c0b3
AE		 10281 .ndo_setup_tc = bnx2x_setup_tc,
10282
bf61ee14
VZ		 10283#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10284 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10285#endif
c64213cd
SH		 10286};
10287
619c5cb6
VZ		 10288static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10289{
10290 struct device *dev = &bp->pdev->dev;
10291
10292 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10293 bp->flags |= USING_DAC_FLAG;
10294 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10295 dev_err(dev, "dma_set_coherent_mask failed, "
10296 "aborting\n");
10297 return -EIO;
10298 }
10299 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10300 dev_err(dev, "System does not support DMA, aborting\n");
10301 return -EIO;
10302 }
10303
10304 return 0;
10305}
10306
34f80b04 10307static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
619c5cb6
VZ		 10308 struct net_device *dev,
10309 unsigned long board_type)
a2fbb9ea
ET		 10310{
10311 struct bnx2x *bp;
10312 int rc;
10313
10314 SET_NETDEV_DEV(dev, &pdev->dev);
10315 bp = netdev_priv(dev);
10316
34f80b04
EG		 10317 bp->dev = dev;
10318 bp->pdev = pdev;
a2fbb9ea 10319 bp->flags = 0;
f2e0899f 10320 bp->pf_num = PCI_FUNC(pdev->devfn);
a2fbb9ea
ET		 10321
10322 rc = pci_enable_device(pdev);
10323 if (rc) {
cdaa7cb8
VZ		 10324 dev_err(&bp->pdev->dev,
10325 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 10326 goto err_out;
10327 }
10328
10329 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10330 dev_err(&bp->pdev->dev,
10331 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 10332 rc = -ENODEV;
10333 goto err_out_disable;
10334 }
10335
10336 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 10337 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10338 " base address, aborting\n");
a2fbb9ea
ET		 10339 rc = -ENODEV;
10340 goto err_out_disable;
10341 }
10342
34f80b04
EG		 10343 if (atomic_read(&pdev->enable_cnt) == 1) {
10344 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10345 if (rc) {
cdaa7cb8
VZ		 10346 dev_err(&bp->pdev->dev,
10347 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 10348 goto err_out_disable;
10349 }
a2fbb9ea 10350
34f80b04
EG		 10351 pci_set_master(pdev);
10352 pci_save_state(pdev);
10353 }
a2fbb9ea
ET		 10354
10355 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10356 if (bp->pm_cap == 0) {
cdaa7cb8
VZ		 10357 dev_err(&bp->pdev->dev,
10358 "Cannot find power management capability, aborting\n");
a2fbb9ea
ET		 10359 rc = -EIO;
10360 goto err_out_release;
10361 }
10362
77c98e6a
JM		 10363 if (!pci_is_pcie(pdev)) {
10364 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 10365 rc = -EIO;
10366 goto err_out_release;
10367 }
10368
619c5cb6
VZ		 10369 rc = bnx2x_set_coherency_mask(bp);
10370 if (rc)
a2fbb9ea 10371 goto err_out_release;
a2fbb9ea 10372
34f80b04
EG		 10373 dev->mem_start = pci_resource_start(pdev, 0);
10374 dev->base_addr = dev->mem_start;
10375 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 10376
10377 dev->irq = pdev->irq;
10378
275f165f 10379 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 10380 if (!bp->regview) {
cdaa7cb8
VZ		 10381 dev_err(&bp->pdev->dev,
10382 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 10383 rc = -ENOMEM;
10384 goto err_out_release;
10385 }
10386
a2fbb9ea
ET		 10387 bnx2x_set_power_state(bp, PCI_D0);
10388
34f80b04
EG		 10389 /* clean indirect addresses */
10390 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10391 PCICFG_VENDOR_ID_OFFSET);
a5c53dbc
DK		 10392 /*
10393 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 10394 * is not used by the driver.
10395 */
10396 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10397 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10398 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10399 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
a5c53dbc
DK		 10400
10401 if (CHIP_IS_E1x(bp)) {
10402 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10403 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10404 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10405 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10406 }
a2fbb9ea 10407
2189400b 10408 /*
619c5cb6 10409 * Enable internal target-read (in case we are probed after PF FLR).
2189400b 10410 * Must be done prior to any BAR read access. Only for 57712 and up
619c5cb6 10411 */
2189400b
SR		 10412 if (board_type != BCM57710 &&
10413 board_type != BCM57711 &&
10414 board_type != BCM57711E)
10415 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
619c5cb6 10416
72fd0718
VZ		 10417 /* Reset the load counter */
10418 bnx2x_clear_load_cnt(bp);
10419
34f80b04 10420 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 10421
c64213cd 10422 dev->netdev_ops = &bnx2x_netdev_ops;
de0c62db 10423 bnx2x_set_ethtool_ops(dev);
5316bc0b 10424
01789349
JP		 10425 dev->priv_flags |= IFF_UNICAST_FLT;
10426
66371c44 10427 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6e68c912
MS		 10428 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO |
10429 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
66371c44
MM		 10430
10431 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10432 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10433
10434 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
5316bc0b 10435 if (bp->flags & USING_DAC_FLAG)
66371c44 10436 dev->features |= NETIF_F_HIGHDMA;
a2fbb9ea 10437
538dd2e3
MB		 10438 /* Add Loopback capability to the device */
10439 dev->hw_features |= NETIF_F_LOOPBACK;
10440
98507672 10441#ifdef BCM_DCBNL
785b9b1a
SR		 10442 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10443#endif
10444
01cd4528
EG		 10445 /* get_port_hwinfo() will set prtad and mmds properly */
10446 bp->mdio.prtad = MDIO_PRTAD_NONE;
10447 bp->mdio.mmds = 0;
10448 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10449 bp->mdio.dev = dev;
10450 bp->mdio.mdio_read = bnx2x_mdio_read;
10451 bp->mdio.mdio_write = bnx2x_mdio_write;
10452
a2fbb9ea
ET		 10453 return 0;
10454
a2fbb9ea 10455err_out_release:
34f80b04
EG		 10456 if (atomic_read(&pdev->enable_cnt) == 1)
10457 pci_release_regions(pdev);
a2fbb9ea
ET		 10458
10459err_out_disable:
10460 pci_disable_device(pdev);
10461 pci_set_drvdata(pdev, NULL);
10462
10463err_out:
10464 return rc;
10465}
10466
37f9ce62
EG		 10467static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10468 int *width, int *speed)
25047950
ET		 10469{
10470 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10471
37f9ce62 10472 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
25047950 10473
37f9ce62
EG		 10474 /* return value of 1=2.5GHz 2=5GHz */
10475 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
25047950 10476}
37f9ce62 10477
6891dd25 10478static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 10479{
37f9ce62 10480 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 10481 struct bnx2x_fw_file_hdr *fw_hdr;
10482 struct bnx2x_fw_file_section *sections;
94a78b79 10483 u32 offset, len, num_ops;
37f9ce62 10484 u16 *ops_offsets;
94a78b79 10485 int i;
37f9ce62 10486 const u8 *fw_ver;
94a78b79
VZ		 10487
10488 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10489 return -EINVAL;
10490
10491 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10492 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10493
10494 /* Make sure none of the offsets and sizes make us read beyond
10495 * the end of the firmware data */
10496 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10497 offset = be32_to_cpu(sections[i].offset);
10498 len = be32_to_cpu(sections[i].len);
10499 if (offset + len > firmware->size) {
cdaa7cb8
VZ		 10500 dev_err(&bp->pdev->dev,
10501 "Section %d length is out of bounds\n", i);
94a78b79
VZ		 10502 return -EINVAL;
10503 }
10504 }
10505
10506 /* Likewise for the init_ops offsets */
10507 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10508 ops_offsets = (u16 *)(firmware->data + offset);
10509 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10510
10511 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10512 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
cdaa7cb8
VZ		 10513 dev_err(&bp->pdev->dev,
10514 "Section offset %d is out of bounds\n", i);
94a78b79
VZ		 10515 return -EINVAL;
10516 }
10517 }
10518
10519 /* Check FW version */
10520 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10521 fw_ver = firmware->data + offset;
10522 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10523 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10524 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10525 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
cdaa7cb8
VZ		 10526 dev_err(&bp->pdev->dev,
10527 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
94a78b79
VZ		 10528 fw_ver[0], fw_ver[1], fw_ver[2],
10529 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10530 BCM_5710_FW_MINOR_VERSION,
10531 BCM_5710_FW_REVISION_VERSION,
10532 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 10533 return -EINVAL;
94a78b79
VZ		 10534 }
10535
10536 return 0;
10537}
10538
ab6ad5a4 10539static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10540{
ab6ad5a4
EG		 10541 const __be32 *source = (const __be32 *)_source;
10542 u32 *target = (u32 *)_target;
94a78b79 10543 u32 i;
94a78b79
VZ		 10544
10545 for (i = 0; i < n/4; i++)
10546 target[i] = be32_to_cpu(source[i]);
10547}
10548
10549/*
10550 Ops array is stored in the following format:
10551 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10552 */
ab6ad5a4 10553static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 10554{
ab6ad5a4
EG		 10555 const __be32 *source = (const __be32 *)_source;
10556 struct raw_op *target = (struct raw_op *)_target;
94a78b79 10557 u32 i, j, tmp;
94a78b79 10558
ab6ad5a4 10559 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 10560 tmp = be32_to_cpu(source[j]);
10561 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 10562 target[i].offset = tmp & 0xffffff;
10563 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 10564 }
10565}
ab6ad5a4 10566
523224a3
DK		 10567/**
10568 * IRO array is stored in the following format:
10569 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10570 */
10571static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10572{
10573 const __be32 *source = (const __be32 *)_source;
10574 struct iro *target = (struct iro *)_target;
10575 u32 i, j, tmp;
10576
10577 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10578 target[i].base = be32_to_cpu(source[j]);
10579 j++;
10580 tmp = be32_to_cpu(source[j]);
10581 target[i].m1 = (tmp >> 16) & 0xffff;
10582 target[i].m2 = tmp & 0xffff;
10583 j++;
10584 tmp = be32_to_cpu(source[j]);
10585 target[i].m3 = (tmp >> 16) & 0xffff;
10586 target[i].size = tmp & 0xffff;
10587 j++;
10588 }
10589}
10590
ab6ad5a4 10591static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 10592{
ab6ad5a4
EG		 10593 const __be16 *source = (const __be16 *)_source;
10594 u16 *target = (u16 *)_target;
94a78b79 10595 u32 i;
94a78b79
VZ		 10596
10597 for (i = 0; i < n/2; i++)
10598 target[i] = be16_to_cpu(source[i]);
10599}
10600
7995c64e
JP		 10601#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10602do { \
10603 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10604 bp->arr = kmalloc(len, GFP_KERNEL); \
10605 if (!bp->arr) { \
10606 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10607 goto lbl; \
10608 } \
10609 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10610 (u8 *)bp->arr, len); \
10611} while (0)
94a78b79 10612
6891dd25 10613int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 10614{
94a78b79 10615 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 10616 int rc;
94a78b79 10617
94a78b79 10618
eb2afd4a
DK		 10619 if (!bp->firmware) {
10620 const char *fw_file_name;
94a78b79 10621
eb2afd4a
DK		 10622 if (CHIP_IS_E1(bp))
10623 fw_file_name = FW_FILE_NAME_E1;
10624 else if (CHIP_IS_E1H(bp))
10625 fw_file_name = FW_FILE_NAME_E1H;
10626 else if (!CHIP_IS_E1x(bp))
10627 fw_file_name = FW_FILE_NAME_E2;
10628 else {
10629 BNX2X_ERR("Unsupported chip revision\n");
10630 return -EINVAL;
10631 }
10632 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 10633
eb2afd4a
DK		 10634 rc = request_firmware(&bp->firmware, fw_file_name,
10635 &bp->pdev->dev);
10636 if (rc) {
10637 BNX2X_ERR("Can't load firmware file %s\n",
10638 fw_file_name);
10639 goto request_firmware_exit;
10640 }
10641
10642 rc = bnx2x_check_firmware(bp);
10643 if (rc) {
10644 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10645 goto request_firmware_exit;
10646 }
94a78b79
VZ		 10647 }
10648
10649 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10650
10651 /* Initialize the pointers to the init arrays */
10652 /* Blob */
10653 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10654
10655 /* Opcodes */
10656 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10657
10658 /* Offsets */
ab6ad5a4
EG		 10659 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10660 be16_to_cpu_n);
94a78b79
VZ		 10661
10662 /* STORMs firmware */
573f2035
EG		 10663 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10664 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10665 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10666 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10667 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10668 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10669 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10670 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10671 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10672 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10673 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10674 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10675 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10676 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10677 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10678 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 10679 /* IRO */
10680 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 10681
10682 return 0;
ab6ad5a4 10683
523224a3
DK		 10684iro_alloc_err:
10685 kfree(bp->init_ops_offsets);
94a78b79
VZ		 10686init_offsets_alloc_err:
10687 kfree(bp->init_ops);
10688init_ops_alloc_err:
10689 kfree(bp->init_data);
10690request_firmware_exit:
10691 release_firmware(bp->firmware);
10692
10693 return rc;
10694}
10695
619c5cb6
VZ		 10696static void bnx2x_release_firmware(struct bnx2x *bp)
10697{
10698 kfree(bp->init_ops_offsets);
10699 kfree(bp->init_ops);
10700 kfree(bp->init_data);
10701 release_firmware(bp->firmware);
eb2afd4a 10702 bp->firmware = NULL;
619c5cb6
VZ		 10703}
10704
10705
10706static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10707 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10708 .init_hw_cmn = bnx2x_init_hw_common,
10709 .init_hw_port = bnx2x_init_hw_port,
10710 .init_hw_func = bnx2x_init_hw_func,
10711
10712 .reset_hw_cmn = bnx2x_reset_common,
10713 .reset_hw_port = bnx2x_reset_port,
10714 .reset_hw_func = bnx2x_reset_func,
10715
10716 .gunzip_init = bnx2x_gunzip_init,
10717 .gunzip_end = bnx2x_gunzip_end,
10718
10719 .init_fw = bnx2x_init_firmware,
10720 .release_fw = bnx2x_release_firmware,
10721};
10722
10723void bnx2x__init_func_obj(struct bnx2x *bp)
10724{
10725 /* Prepare DMAE related driver resources */
10726 bnx2x_setup_dmae(bp);
10727
10728 bnx2x_init_func_obj(bp, &bp->func_obj,
10729 bnx2x_sp(bp, func_rdata),
10730 bnx2x_sp_mapping(bp, func_rdata),
10731 &bnx2x_func_sp_drv);
10732}
10733
10734/* must be called after sriov-enable */
6383c0b3 10735static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 10736{
6383c0b3 10737 int cid_count = BNX2X_L2_CID_COUNT(bp);
94a78b79 10738
523224a3
DK		 10739#ifdef BCM_CNIC
10740 cid_count += CNIC_CID_MAX;
10741#endif
10742 return roundup(cid_count, QM_CID_ROUND);
10743}
f85582f8 10744
619c5cb6 10745/**
6383c0b3 10746 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 10747 *
10748 * @dev: pci device
10749 *
10750 */
6383c0b3 10751static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
619c5cb6
VZ		 10752{
10753 int pos;
10754 u16 control;
10755
10756 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
6383c0b3
AE		 10757
10758 /*
10759 * If MSI-X is not supported - return number of SBs needed to support
10760 * one fast path queue: one FP queue + SB for CNIC
10761 */
619c5cb6 10762 if (!pos)
6383c0b3 10763 return 1 + CNIC_PRESENT;
619c5cb6 10764
6383c0b3
AE		 10765 /*
10766 * The value in the PCI configuration space is the index of the last
10767 * entry, namely one less than the actual size of the table, which is
10768 * exactly what we want to return from this function: number of all SBs
10769 * without the default SB.
10770 */
619c5cb6 10771 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
6383c0b3 10772 return control & PCI_MSIX_FLAGS_QSIZE;
619c5cb6
VZ		 10773}
10774
a2fbb9ea
ET		 10775static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10776 const struct pci_device_id *ent)
10777{
a2fbb9ea
ET		 10778 struct net_device *dev = NULL;
10779 struct bnx2x *bp;
37f9ce62 10780 int pcie_width, pcie_speed;
6383c0b3
AE		 10781 int rc, max_non_def_sbs;
10782 int rx_count, tx_count, rss_count;
10783 /*
10784 * An estimated maximum supported CoS number according to the chip
10785 * version.
10786 * We will try to roughly estimate the maximum number of CoSes this chip
10787 * may support in order to minimize the memory allocated for Tx
10788 * netdev_queue's. This number will be accurately calculated during the
10789 * initialization of bp->max_cos based on the chip versions AND chip
10790 * revision in the bnx2x_init_bp().
10791 */
10792 u8 max_cos_est = 0;
523224a3 10793
f2e0899f
DK		 10794 switch (ent->driver_data) {
10795 case BCM57710:
10796 case BCM57711:
10797 case BCM57711E:
6383c0b3
AE		 10798 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10799 break;
10800
f2e0899f 10801 case BCM57712:
619c5cb6 10802 case BCM57712_MF:
6383c0b3
AE		 10803 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10804 break;
10805
619c5cb6
VZ		 10806 case BCM57800:
10807 case BCM57800_MF:
10808 case BCM57810:
10809 case BCM57810_MF:
10810 case BCM57840:
10811 case BCM57840_MF:
6383c0b3 10812 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
f2e0899f 10813 break;
a2fbb9ea 10814
f2e0899f
DK		 10815 default:
10816 pr_err("Unknown board_type (%ld), aborting\n",
10817 ent->driver_data);
870634b0 10818 return -ENODEV;
f2e0899f
DK		 10819 }
10820
6383c0b3
AE		 10821 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10822
10823 /* !!! FIXME !!!
10824 * Do not allow the maximum SB count to grow above 16
10825 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10826 * We will use the FP_SB_MAX_E1x macro for this matter.
10827 */
10828 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10829
10830 WARN_ON(!max_non_def_sbs);
10831
10832 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10833 rss_count = max_non_def_sbs - CNIC_PRESENT;
10834
10835 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10836 rx_count = rss_count + FCOE_PRESENT;
10837
10838 /*
10839 * Maximum number of netdev Tx queues:
10840 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10841 */
10842 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
f85582f8 10843
a2fbb9ea 10844 /* dev zeroed in init_etherdev */
6383c0b3 10845 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
34f80b04 10846 if (!dev) {
cdaa7cb8 10847 dev_err(&pdev->dev, "Cannot allocate net device\n");
a2fbb9ea 10848 return -ENOMEM;
34f80b04 10849 }
a2fbb9ea 10850
a2fbb9ea 10851 bp = netdev_priv(dev);
a2fbb9ea 10852
6383c0b3
AE		 10853 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10854 tx_count, rx_count);
df4770de 10855
6383c0b3
AE		 10856 bp->igu_sb_cnt = max_non_def_sbs;
10857 bp->msg_enable = debug;
10858 pci_set_drvdata(pdev, dev);
523224a3 10859
619c5cb6 10860 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
a2fbb9ea
ET		 10861 if (rc < 0) {
10862 free_netdev(dev);
10863 return rc;
10864 }
10865
94f05b0f 10866 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs);
619c5cb6 10867
34f80b04 10868 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 10869 if (rc)
10870 goto init_one_exit;
10871
6383c0b3
AE		 10872 /*
10873 * Map doorbels here as we need the real value of bp->max_cos which
10874 * is initialized in bnx2x_init_bp().
10875 */
10876 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10877 min_t(u64, BNX2X_DB_SIZE(bp),
10878 pci_resource_len(pdev, 2)));
10879 if (!bp->doorbells) {
10880 dev_err(&bp->pdev->dev,
10881 "Cannot map doorbell space, aborting\n");
10882 rc = -ENOMEM;
10883 goto init_one_exit;
10884 }
10885
523224a3 10886 /* calc qm_cid_count */
6383c0b3 10887 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
523224a3 10888
ec6ba945 10889#ifdef BCM_CNIC
62ac0dc9
DK		 10890 /* disable FCOE L2 queue for E1x */
10891 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 10892 bp->flags |= NO_FCOE_FLAG;
10893
10894#endif
10895
25985edc 10896 /* Configure interrupt mode: try to enable MSI-X/MSI if
d6214d7a
DK		 10897 * needed, set bp->num_queues appropriately.
10898 */
10899 bnx2x_set_int_mode(bp);
10900
10901 /* Add all NAPI objects */
10902 bnx2x_add_all_napi(bp);
10903
b340007f
VZ		 10904 rc = register_netdev(dev);
10905 if (rc) {
10906 dev_err(&pdev->dev, "Cannot register net device\n");
10907 goto init_one_exit;
10908 }
10909
ec6ba945
VZ		 10910#ifdef BCM_CNIC
10911 if (!NO_FCOE(bp)) {
10912 /* Add storage MAC address */
10913 rtnl_lock();
10914 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10915 rtnl_unlock();
10916 }
10917#endif
10918
37f9ce62 10919 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
d6214d7a 10920
94f05b0f
JP		 10921 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
10922 board_info[ent->driver_data].name,
10923 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10924 pcie_width,
10925 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10926 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10927 "5GHz (Gen2)" : "2.5GHz",
10928 dev->base_addr, bp->pdev->irq, dev->dev_addr);
c016201c 10929
a2fbb9ea 10930 return 0;
34f80b04
EG		 10931
10932init_one_exit:
10933 if (bp->regview)
10934 iounmap(bp->regview);
10935
10936 if (bp->doorbells)
10937 iounmap(bp->doorbells);
10938
10939 free_netdev(dev);
10940
10941 if (atomic_read(&pdev->enable_cnt) == 1)
10942 pci_release_regions(pdev);
10943
10944 pci_disable_device(pdev);
10945 pci_set_drvdata(pdev, NULL);
10946
10947 return rc;
a2fbb9ea
ET		 10948}
10949
10950static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10951{
10952 struct net_device *dev = pci_get_drvdata(pdev);
228241eb
ET		 10953 struct bnx2x *bp;
10954
10955 if (!dev) {
cdaa7cb8 10956 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
228241eb
ET		 10957 return;
10958 }
228241eb 10959 bp = netdev_priv(dev);
a2fbb9ea 10960
ec6ba945
VZ		 10961#ifdef BCM_CNIC
10962 /* Delete storage MAC address */
10963 if (!NO_FCOE(bp)) {
10964 rtnl_lock();
10965 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10966 rtnl_unlock();
10967 }
10968#endif
10969
98507672
SR		 10970#ifdef BCM_DCBNL
10971 /* Delete app tlvs from dcbnl */
10972 bnx2x_dcbnl_update_applist(bp, true);
10973#endif
10974
a2fbb9ea
ET		 10975 unregister_netdev(dev);
10976
d6214d7a
DK		 10977 /* Delete all NAPI objects */
10978 bnx2x_del_all_napi(bp);
10979
084d6cbb
VZ		 10980 /* Power on: we can't let PCI layer write to us while we are in D3 */
10981 bnx2x_set_power_state(bp, PCI_D0);
10982
d6214d7a
DK		 10983 /* Disable MSI/MSI-X */
10984 bnx2x_disable_msi(bp);
f85582f8 10985
084d6cbb
VZ		 10986 /* Power off */
10987 bnx2x_set_power_state(bp, PCI_D3hot);
10988
72fd0718 10989 /* Make sure RESET task is not scheduled before continuing */
7be08a72 10990 cancel_delayed_work_sync(&bp->sp_rtnl_task);
72fd0718 10991
a2fbb9ea
ET		 10992 if (bp->regview)
10993 iounmap(bp->regview);
10994
10995 if (bp->doorbells)
10996 iounmap(bp->doorbells);
10997
eb2afd4a
DK		 10998 bnx2x_release_firmware(bp);
10999
523224a3
DK		 11000 bnx2x_free_mem_bp(bp);
11001
a2fbb9ea 11002 free_netdev(dev);
34f80b04
EG		 11003
11004 if (atomic_read(&pdev->enable_cnt) == 1)
11005 pci_release_regions(pdev);
11006
a2fbb9ea
ET		 11007 pci_disable_device(pdev);
11008 pci_set_drvdata(pdev, NULL);
11009}
11010
f8ef6e44
YG		 11011static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
11012{
11013 int i;
11014
11015 bp->state = BNX2X_STATE_ERROR;
11016
11017 bp->rx_mode = BNX2X_RX_MODE_NONE;
11018
619c5cb6
VZ		 11019#ifdef BCM_CNIC
11020 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
11021#endif
11022 /* Stop Tx */
11023 bnx2x_tx_disable(bp);
11024
f8ef6e44
YG		 11025 bnx2x_netif_stop(bp, 0);
11026
11027 del_timer_sync(&bp->timer);
619c5cb6
VZ		 11028
11029 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
f8ef6e44
YG		 11030
11031 /* Release IRQs */
d6214d7a 11032 bnx2x_free_irq(bp);
f8ef6e44 11033
f8ef6e44
YG		 11034 /* Free SKBs, SGEs, TPA pool and driver internals */
11035 bnx2x_free_skbs(bp);
523224a3 11036
ec6ba945 11037 for_each_rx_queue(bp, i)
f8ef6e44 11038 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
d6214d7a 11039
f8ef6e44
YG		 11040 bnx2x_free_mem(bp);
11041
11042 bp->state = BNX2X_STATE_CLOSED;
11043
619c5cb6
VZ		 11044 netif_carrier_off(bp->dev);
11045
f8ef6e44
YG		 11046 return 0;
11047}
11048
11049static void bnx2x_eeh_recover(struct bnx2x *bp)
11050{
11051 u32 val;
11052
11053 mutex_init(&bp->port.phy_mutex);
11054
11055 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
11056 bp->link_params.shmem_base = bp->common.shmem_base;
11057 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
11058
11059 if (!bp->common.shmem_base ||
11060 (bp->common.shmem_base < 0xA0000) ||
11061 (bp->common.shmem_base >= 0xC0000)) {
11062 BNX2X_DEV_INFO("MCP not active\n");
11063 bp->flags |= NO_MCP_FLAG;
11064 return;
11065 }
11066
11067 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
11068 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11069 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11070 BNX2X_ERR("BAD MCP validity signature\n");
11071
11072 if (!BP_NOMCP(bp)) {
f2e0899f
DK		 11073 bp->fw_seq =
11074 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11075 DRV_MSG_SEQ_NUMBER_MASK);
f8ef6e44
YG		 11076 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11077 }
11078}
11079
493adb1f
WX		 11080/**
11081 * bnx2x_io_error_detected - called when PCI error is detected
11082 * @pdev: Pointer to PCI device
11083 * @state: The current pci connection state
11084 *
11085 * This function is called after a PCI bus error affecting
11086 * this device has been detected.
11087 */
11088static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11089 pci_channel_state_t state)
11090{
11091 struct net_device *dev = pci_get_drvdata(pdev);
11092 struct bnx2x *bp = netdev_priv(dev);
11093
11094 rtnl_lock();
11095
11096 netif_device_detach(dev);
11097
07ce50e4
DN		 11098 if (state == pci_channel_io_perm_failure) {
11099 rtnl_unlock();
11100 return PCI_ERS_RESULT_DISCONNECT;
11101 }
11102
493adb1f 11103 if (netif_running(dev))
f8ef6e44 11104 bnx2x_eeh_nic_unload(bp);
493adb1f
WX		 11105
11106 pci_disable_device(pdev);
11107
11108 rtnl_unlock();
11109
11110 /* Request a slot reset */
11111 return PCI_ERS_RESULT_NEED_RESET;
11112}
11113
11114/**
11115 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11116 * @pdev: Pointer to PCI device
11117 *
11118 * Restart the card from scratch, as if from a cold-boot.
11119 */
11120static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11121{
11122 struct net_device *dev = pci_get_drvdata(pdev);
11123 struct bnx2x *bp = netdev_priv(dev);
11124
11125 rtnl_lock();
11126
11127 if (pci_enable_device(pdev)) {
11128 dev_err(&pdev->dev,
11129 "Cannot re-enable PCI device after reset\n");
11130 rtnl_unlock();
11131 return PCI_ERS_RESULT_DISCONNECT;
11132 }
11133
11134 pci_set_master(pdev);
11135 pci_restore_state(pdev);
11136
11137 if (netif_running(dev))
11138 bnx2x_set_power_state(bp, PCI_D0);
11139
11140 rtnl_unlock();
11141
11142 return PCI_ERS_RESULT_RECOVERED;
11143}
11144
11145/**
11146 * bnx2x_io_resume - called when traffic can start flowing again
11147 * @pdev: Pointer to PCI device
11148 *
11149 * This callback is called when the error recovery driver tells us that
11150 * its OK to resume normal operation.
11151 */
11152static void bnx2x_io_resume(struct pci_dev *pdev)
11153{
11154 struct net_device *dev = pci_get_drvdata(pdev);
11155 struct bnx2x *bp = netdev_priv(dev);
11156
72fd0718 11157 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
754a2f52
DK		 11158 netdev_err(bp->dev, "Handling parity error recovery. "
11159 "Try again later\n");
72fd0718
VZ		 11160 return;
11161 }
11162
493adb1f
WX		 11163 rtnl_lock();
11164
f8ef6e44
YG		 11165 bnx2x_eeh_recover(bp);
11166
493adb1f 11167 if (netif_running(dev))
f8ef6e44 11168 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 11169
11170 netif_device_attach(dev);
11171
11172 rtnl_unlock();
11173}
11174
11175static struct pci_error_handlers bnx2x_err_handler = {
11176 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 11177 .slot_reset = bnx2x_io_slot_reset,
11178 .resume = bnx2x_io_resume,
493adb1f
WX		 11179};
11180
a2fbb9ea 11181static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 11182 .name = DRV_MODULE_NAME,
11183 .id_table = bnx2x_pci_tbl,
11184 .probe = bnx2x_init_one,
11185 .remove = __devexit_p(bnx2x_remove_one),
11186 .suspend = bnx2x_suspend,
11187 .resume = bnx2x_resume,
11188 .err_handler = &bnx2x_err_handler,
a2fbb9ea
ET		 11189};
11190
11191static int __init bnx2x_init(void)
11192{
dd21ca6d
SG		 11193 int ret;
11194
7995c64e 11195 pr_info("%s", version);
938cf541 11196
1cf167f2
EG		 11197 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11198 if (bnx2x_wq == NULL) {
7995c64e 11199 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 11200 return -ENOMEM;
11201 }
11202
dd21ca6d
SG		 11203 ret = pci_register_driver(&bnx2x_pci_driver);
11204 if (ret) {
7995c64e 11205 pr_err("Cannot register driver\n");
dd21ca6d
SG		 11206 destroy_workqueue(bnx2x_wq);
11207 }
11208 return ret;
a2fbb9ea
ET		 11209}
11210
11211static void __exit bnx2x_cleanup(void)
11212{
11213 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 11214
11215 destroy_workqueue(bnx2x_wq);
a2fbb9ea
ET		 11216}
11217
3deb8167
YR		 11218void bnx2x_notify_link_changed(struct bnx2x *bp)
11219{
11220 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11221}
11222
a2fbb9ea
ET		 11223module_init(bnx2x_init);
11224module_exit(bnx2x_cleanup);
11225
993ac7b5 11226#ifdef BCM_CNIC
619c5cb6
VZ		 11227/**
11228 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11229 *
11230 * @bp: driver handle
11231 * @set: set or clear the CAM entry
11232 *
11233 * This function will wait until the ramdord completion returns.
11234 * Return 0 if success, -ENODEV if ramrod doesn't return.
11235 */
11236static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11237{
11238 unsigned long ramrod_flags = 0;
11239
11240 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11241 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11242 &bp->iscsi_l2_mac_obj, true,
11243 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11244}
993ac7b5
MC		 11245
11246/* count denotes the number of new completions we have seen */
11247static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11248{
11249 struct eth_spe *spe;
11250
11251#ifdef BNX2X_STOP_ON_ERROR
11252 if (unlikely(bp->panic))
11253 return;
11254#endif
11255
11256 spin_lock_bh(&bp->spq_lock);
c2bff63f 11257 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 11258 bp->cnic_spq_pending -= count;
11259
993ac7b5 11260
c2bff63f
DK		 11261 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11262 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11263 & SPE_HDR_CONN_TYPE) >>
11264 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 11265 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11266 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 11267
11268 /* Set validation for iSCSI L2 client before sending SETUP
11269 * ramrod
11270 */
11271 if (type == ETH_CONNECTION_TYPE) {
c2bff63f 11272 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
619c5cb6
VZ		 11273 bnx2x_set_ctx_validation(bp, &bp->context.
11274 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11275 BNX2X_ISCSI_ETH_CID);
c2bff63f
DK		 11276 }
11277
619c5cb6
VZ		 11278 /*
11279 * There may be not more than 8 L2, not more than 8 L5 SPEs
11280 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 11281 * COMMON ramrods is not more than the EQ and SPQ can
11282 * accommodate.
c2bff63f 11283 */
6e30dd4e
VZ		 11284 if (type == ETH_CONNECTION_TYPE) {
11285 if (!atomic_read(&bp->cq_spq_left))
11286 break;
11287 else
11288 atomic_dec(&bp->cq_spq_left);
11289 } else if (type == NONE_CONNECTION_TYPE) {
11290 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 11291 break;
11292 else
6e30dd4e 11293 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 11294 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11295 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 11296 if (bp->cnic_spq_pending >=
11297 bp->cnic_eth_dev.max_kwqe_pending)
11298 break;
11299 else
11300 bp->cnic_spq_pending++;
11301 } else {
11302 BNX2X_ERR("Unknown SPE type: %d\n", type);
11303 bnx2x_panic();
993ac7b5 11304 break;
c2bff63f 11305 }
993ac7b5
MC		 11306
11307 spe = bnx2x_sp_get_next(bp);
11308 *spe = *bp->cnic_kwq_cons;
11309
993ac7b5
MC		 11310 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11311 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11312
11313 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11314 bp->cnic_kwq_cons = bp->cnic_kwq;
11315 else
11316 bp->cnic_kwq_cons++;
11317 }
11318 bnx2x_sp_prod_update(bp);
11319 spin_unlock_bh(&bp->spq_lock);
11320}
11321
11322static int bnx2x_cnic_sp_queue(struct net_device *dev,
11323 struct kwqe_16 *kwqes[], u32 count)
11324{
11325 struct bnx2x *bp = netdev_priv(dev);
11326 int i;
11327
11328#ifdef BNX2X_STOP_ON_ERROR
11329 if (unlikely(bp->panic))
11330 return -EIO;
11331#endif
11332
11333 spin_lock_bh(&bp->spq_lock);
11334
11335 for (i = 0; i < count; i++) {
11336 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11337
11338 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11339 break;
11340
11341 *bp->cnic_kwq_prod = *spe;
11342
11343 bp->cnic_kwq_pending++;
11344
11345 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11346 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 11347 spe->data.update_data_addr.hi,
11348 spe->data.update_data_addr.lo,
993ac7b5
MC		 11349 bp->cnic_kwq_pending);
11350
11351 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11352 bp->cnic_kwq_prod = bp->cnic_kwq;
11353 else
11354 bp->cnic_kwq_prod++;
11355 }
11356
11357 spin_unlock_bh(&bp->spq_lock);
11358
11359 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11360 bnx2x_cnic_sp_post(bp, 0);
11361
11362 return i;
11363}
11364
11365static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11366{
11367 struct cnic_ops *c_ops;
11368 int rc = 0;
11369
11370 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 11371 c_ops = rcu_dereference_protected(bp->cnic_ops,
11372 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 11373 if (c_ops)
11374 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11375 mutex_unlock(&bp->cnic_mutex);
11376
11377 return rc;
11378}
11379
11380static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11381{
11382 struct cnic_ops *c_ops;
11383 int rc = 0;
11384
11385 rcu_read_lock();
11386 c_ops = rcu_dereference(bp->cnic_ops);
11387 if (c_ops)
11388 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11389 rcu_read_unlock();
11390
11391 return rc;
11392}
11393
11394/*
11395 * for commands that have no data
11396 */
9f6c9258 11397int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 11398{
11399 struct cnic_ctl_info ctl = {0};
11400
11401 ctl.cmd = cmd;
11402
11403 return bnx2x_cnic_ctl_send(bp, &ctl);
11404}
11405
619c5cb6 11406static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 11407{
619c5cb6 11408 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 11409
11410 /* first we tell CNIC and only then we count this as a completion */
11411 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11412 ctl.data.comp.cid = cid;
619c5cb6 11413 ctl.data.comp.error = err;
993ac7b5
MC		 11414
11415 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 11416 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 11417}
11418
619c5cb6
VZ		 11419
11420/* Called with netif_addr_lock_bh() taken.
11421 * Sets an rx_mode config for an iSCSI ETH client.
11422 * Doesn't block.
11423 * Completion should be checked outside.
11424 */
11425static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11426{
11427 unsigned long accept_flags = 0, ramrod_flags = 0;
11428 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11429 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11430
11431 if (start) {
11432 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11433 * because it's the only way for UIO Queue to accept
11434 * multicasts (in non-promiscuous mode only one Queue per
11435 * function will receive multicast packets (leading in our
11436 * case).
11437 */
11438 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11439 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11440 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11441 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11442
11443 /* Clear STOP_PENDING bit if START is requested */
11444 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11445
11446 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11447 } else
11448 /* Clear START_PENDING bit if STOP is requested */
11449 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11450
11451 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11452 set_bit(sched_state, &bp->sp_state);
11453 else {
11454 __set_bit(RAMROD_RX, &ramrod_flags);
11455 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11456 ramrod_flags);
11457 }
11458}
11459
11460
993ac7b5
MC		 11461static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11462{
11463 struct bnx2x *bp = netdev_priv(dev);
11464 int rc = 0;
11465
11466 switch (ctl->cmd) {
11467 case DRV_CTL_CTXTBL_WR_CMD: {
11468 u32 index = ctl->data.io.offset;
11469 dma_addr_t addr = ctl->data.io.dma_addr;
11470
11471 bnx2x_ilt_wr(bp, index, addr);
11472 break;
11473 }
11474
c2bff63f
DK		 11475 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11476 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 11477
11478 bnx2x_cnic_sp_post(bp, count);
11479 break;
11480 }
11481
11482 /* rtnl_lock is held. */
11483 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 11484 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11485 unsigned long sp_bits = 0;
11486
11487 /* Configure the iSCSI classification object */
11488 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11489 cp->iscsi_l2_client_id,
11490 cp->iscsi_l2_cid, BP_FUNC(bp),
11491 bnx2x_sp(bp, mac_rdata),
11492 bnx2x_sp_mapping(bp, mac_rdata),
11493 BNX2X_FILTER_MAC_PENDING,
11494 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11495 &bp->macs_pool);
ec6ba945 11496
523224a3 11497 /* Set iSCSI MAC address */
619c5cb6
VZ		 11498 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11499 if (rc)
11500 break;
523224a3
DK		 11501
11502 mmiowb();
11503 barrier();
11504
619c5cb6
VZ		 11505 /* Start accepting on iSCSI L2 ring */
11506
11507 netif_addr_lock_bh(dev);
11508 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11509 netif_addr_unlock_bh(dev);
11510
11511 /* bits to wait on */
11512 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11513 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11514
11515 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11516 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 11517
993ac7b5
MC		 11518 break;
11519 }
11520
11521 /* rtnl_lock is held. */
11522 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 11523 unsigned long sp_bits = 0;
993ac7b5 11524
523224a3 11525 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 11526 netif_addr_lock_bh(dev);
11527 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11528 netif_addr_unlock_bh(dev);
11529
11530 /* bits to wait on */
11531 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11532 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11533
11534 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11535 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 11536
11537 mmiowb();
11538 barrier();
11539
11540 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 11541 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11542 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 11543 break;
11544 }
c2bff63f
DK		 11545 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11546 int count = ctl->data.credit.credit_count;
11547
11548 smp_mb__before_atomic_inc();
6e30dd4e 11549 atomic_add(count, &bp->cq_spq_left);
c2bff63f
DK		 11550 smp_mb__after_atomic_inc();
11551 break;
11552 }
993ac7b5
MC		 11553
11554 default:
11555 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11556 rc = -EINVAL;
11557 }
11558
11559 return rc;
11560}
11561
9f6c9258 11562void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 11563{
11564 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11565
11566 if (bp->flags & USING_MSIX_FLAG) {
11567 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11568 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11569 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11570 } else {
11571 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11572 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11573 }
619c5cb6 11574 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 11575 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11576 else
11577 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11578
619c5cb6
VZ		 11579 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11580 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 11581 cp->irq_arr[1].status_blk = bp->def_status_blk;
11582 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 11583 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 11584
11585 cp->num_irq = 2;
11586}
11587
11588static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11589 void *data)
11590{
11591 struct bnx2x *bp = netdev_priv(dev);
11592 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11593
11594 if (ops == NULL)
11595 return -EINVAL;
11596
993ac7b5
MC		 11597 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11598 if (!bp->cnic_kwq)
11599 return -ENOMEM;
11600
11601 bp->cnic_kwq_cons = bp->cnic_kwq;
11602 bp->cnic_kwq_prod = bp->cnic_kwq;
11603 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11604
11605 bp->cnic_spq_pending = 0;
11606 bp->cnic_kwq_pending = 0;
11607
11608 bp->cnic_data = data;
11609
11610 cp->num_irq = 0;
619c5cb6 11611 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 11612 cp->iro_arr = bp->iro_arr;
993ac7b5 11613
993ac7b5 11614 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 11615
993ac7b5
MC		 11616 rcu_assign_pointer(bp->cnic_ops, ops);
11617
11618 return 0;
11619}
11620
11621static int bnx2x_unregister_cnic(struct net_device *dev)
11622{
11623 struct bnx2x *bp = netdev_priv(dev);
11624 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11625
11626 mutex_lock(&bp->cnic_mutex);
993ac7b5 11627 cp->drv_state = 0;
2cfa5a04 11628 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 11629 mutex_unlock(&bp->cnic_mutex);
11630 synchronize_rcu();
11631 kfree(bp->cnic_kwq);
11632 bp->cnic_kwq = NULL;
11633
11634 return 0;
11635}
11636
11637struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11638{
11639 struct bnx2x *bp = netdev_priv(dev);
11640 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11641
2ba45142
VZ		 11642 /* If both iSCSI and FCoE are disabled - return NULL in
11643 * order to indicate CNIC that it should not try to work
11644 * with this device.
11645 */
11646 if (NO_ISCSI(bp) && NO_FCOE(bp))
11647 return NULL;
11648
993ac7b5
MC		 11649 cp->drv_owner = THIS_MODULE;
11650 cp->chip_id = CHIP_ID(bp);
11651 cp->pdev = bp->pdev;
11652 cp->io_base = bp->regview;
11653 cp->io_base2 = bp->doorbells;
11654 cp->max_kwqe_pending = 8;
523224a3 11655 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 11656 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11657 bnx2x_cid_ilt_lines(bp);
993ac7b5 11658 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 11659 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 11660 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11661 cp->drv_ctl = bnx2x_drv_ctl;
11662 cp->drv_register_cnic = bnx2x_register_cnic;
11663 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
ec6ba945 11664 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
619c5cb6
VZ		 11665 cp->iscsi_l2_client_id =
11666 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
c2bff63f
DK		 11667 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11668
2ba45142
VZ		 11669 if (NO_ISCSI_OOO(bp))
11670 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11671
11672 if (NO_ISCSI(bp))
11673 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11674
11675 if (NO_FCOE(bp))
11676 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11677
c2bff63f
DK		 11678 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11679 "starting cid %d\n",
11680 cp->ctx_blk_size,
11681 cp->ctx_tbl_offset,
11682 cp->ctx_tbl_len,
11683 cp->starting_cid);
993ac7b5
MC		 11684 return cp;
11685}
11686EXPORT_SYMBOL(bnx2x_cnic_probe);
11687
11688#endif /* BCM_CNIC */
94a78b79 11689
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