]>
Commit | Line | Data |
---|---|---|
c0c050c5 MC |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
11f15ed3 | 3 | * Copyright (c) 2014-2016 Broadcom Corporation |
894aa69a | 4 | * Copyright (c) 2016-2018 Broadcom Limited |
c0c050c5 MC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef BNXT_H | |
12 | #define BNXT_H | |
13 | ||
14 | #define DRV_MODULE_NAME "bnxt_en" | |
c0c050c5 | 15 | |
e3c0a635 LR |
16 | /* DO NOT CHANGE DRV_VER_* defines |
17 | * FIXME: Delete them | |
18 | */ | |
c193554e | 19 | #define DRV_VER_MAJ 1 |
31d357c0 | 20 | #define DRV_VER_MIN 10 |
31f67c2e | 21 | #define DRV_VER_UPD 2 |
c0c050c5 | 22 | |
cc69837f | 23 | #include <linux/ethtool.h> |
282ccf6e | 24 | #include <linux/interrupt.h> |
2ae7408f | 25 | #include <linux/rhashtable.h> |
d629522e | 26 | #include <linux/crash_dump.h> |
d80d88b0 | 27 | #include <linux/auxiliary_bus.h> |
4ab0c6a8 | 28 | #include <net/devlink.h> |
ee5c7fb3 | 29 | #include <net/dst_metadata.h> |
96a8604f | 30 | #include <net/xdp.h> |
4f75da36 | 31 | #include <linux/dim.h> |
c6132f6f | 32 | #include <linux/io-64-nonatomic-lo-hi.h> |
e07ab202 VV |
33 | #ifdef CONFIG_TEE_BNXT_FW |
34 | #include <linux/firmware/broadcom/tee_bnxt_fw.h> | |
35 | #endif | |
282ccf6e | 36 | |
627c89d0 SB |
37 | extern struct list_head bnxt_block_cb_list; |
38 | ||
322b87ca AG |
39 | struct page_pool; |
40 | ||
c0c050c5 MC |
41 | struct tx_bd { |
42 | __le32 tx_bd_len_flags_type; | |
43 | #define TX_BD_TYPE (0x3f << 0) | |
44 | #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) | |
45 | #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) | |
46 | #define TX_BD_FLAGS_PACKET_END (1 << 6) | |
47 | #define TX_BD_FLAGS_NO_CMPL (1 << 7) | |
48 | #define TX_BD_FLAGS_BD_CNT (0x1f << 8) | |
49 | #define TX_BD_FLAGS_BD_CNT_SHIFT 8 | |
50 | #define TX_BD_FLAGS_LHINT (3 << 13) | |
51 | #define TX_BD_FLAGS_LHINT_SHIFT 13 | |
52 | #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) | |
53 | #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) | |
54 | #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) | |
55 | #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) | |
56 | #define TX_BD_FLAGS_COAL_NOW (1 << 15) | |
57 | #define TX_BD_LEN (0xffff << 16) | |
58 | #define TX_BD_LEN_SHIFT 16 | |
59 | ||
60 | u32 tx_bd_opaque; | |
61 | __le64 tx_bd_haddr; | |
62 | } __packed; | |
63 | ||
64 | struct tx_bd_ext { | |
65 | __le32 tx_bd_hsize_lflags; | |
66 | #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) | |
67 | #define TX_BD_FLAGS_IP_CKSUM (1 << 1) | |
68 | #define TX_BD_FLAGS_NO_CRC (1 << 2) | |
69 | #define TX_BD_FLAGS_STAMP (1 << 3) | |
70 | #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) | |
71 | #define TX_BD_FLAGS_LSO (1 << 5) | |
72 | #define TX_BD_FLAGS_IPID_FMT (1 << 6) | |
73 | #define TX_BD_FLAGS_T_IPID (1 << 7) | |
74 | #define TX_BD_HSIZE (0xff << 16) | |
75 | #define TX_BD_HSIZE_SHIFT 16 | |
76 | ||
77 | __le32 tx_bd_mss; | |
78 | __le32 tx_bd_cfa_action; | |
79 | #define TX_BD_CFA_ACTION (0xffff << 16) | |
80 | #define TX_BD_CFA_ACTION_SHIFT 16 | |
81 | ||
82 | __le32 tx_bd_cfa_meta; | |
83 | #define TX_BD_CFA_META_MASK 0xfffffff | |
84 | #define TX_BD_CFA_META_VID_MASK 0xfff | |
85 | #define TX_BD_CFA_META_PRI_MASK (0xf << 12) | |
86 | #define TX_BD_CFA_META_PRI_SHIFT 12 | |
87 | #define TX_BD_CFA_META_TPID_MASK (3 << 16) | |
88 | #define TX_BD_CFA_META_TPID_SHIFT 16 | |
89 | #define TX_BD_CFA_META_KEY (0xf << 28) | |
90 | #define TX_BD_CFA_META_KEY_SHIFT 28 | |
91 | #define TX_BD_CFA_META_KEY_VLAN (1 << 28) | |
92 | }; | |
93 | ||
83bb623c PC |
94 | #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP)) |
95 | ||
c0c050c5 MC |
96 | struct rx_bd { |
97 | __le32 rx_bd_len_flags_type; | |
98 | #define RX_BD_TYPE (0x3f << 0) | |
99 | #define RX_BD_TYPE_RX_PACKET_BD 0x4 | |
100 | #define RX_BD_TYPE_RX_BUFFER_BD 0x5 | |
101 | #define RX_BD_TYPE_RX_AGG_BD 0x6 | |
102 | #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) | |
103 | #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) | |
104 | #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) | |
105 | #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) | |
106 | #define RX_BD_FLAGS_SOP (1 << 6) | |
107 | #define RX_BD_FLAGS_EOP (1 << 7) | |
108 | #define RX_BD_FLAGS_BUFFERS (3 << 8) | |
109 | #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) | |
110 | #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) | |
111 | #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) | |
112 | #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) | |
113 | #define RX_BD_LEN (0xffff << 16) | |
114 | #define RX_BD_LEN_SHIFT 16 | |
115 | ||
116 | u32 rx_bd_opaque; | |
117 | __le64 rx_bd_haddr; | |
118 | }; | |
119 | ||
120 | struct tx_cmp { | |
121 | __le32 tx_cmp_flags_type; | |
122 | #define CMP_TYPE (0x3f << 0) | |
123 | #define CMP_TYPE_TX_L2_CMP 0 | |
124 | #define CMP_TYPE_RX_L2_CMP 17 | |
125 | #define CMP_TYPE_RX_AGG_CMP 18 | |
126 | #define CMP_TYPE_RX_L2_TPA_START_CMP 19 | |
127 | #define CMP_TYPE_RX_L2_TPA_END_CMP 21 | |
218a8a71 | 128 | #define CMP_TYPE_RX_TPA_AGG_CMP 22 |
c0c050c5 MC |
129 | #define CMP_TYPE_STATUS_CMP 32 |
130 | #define CMP_TYPE_REMOTE_DRIVER_REQ 34 | |
131 | #define CMP_TYPE_REMOTE_DRIVER_RESP 36 | |
132 | #define CMP_TYPE_ERROR_STATUS 48 | |
441cabbb MC |
133 | #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL |
134 | #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL | |
135 | #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL | |
136 | #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL | |
137 | #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL | |
c0c050c5 MC |
138 | |
139 | #define TX_CMP_FLAGS_ERROR (1 << 6) | |
140 | #define TX_CMP_FLAGS_PUSH (1 << 7) | |
141 | ||
142 | u32 tx_cmp_opaque; | |
143 | __le32 tx_cmp_errors_v; | |
144 | #define TX_CMP_V (1 << 0) | |
145 | #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) | |
146 | #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 | |
147 | #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 | |
148 | #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 | |
149 | #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 | |
150 | #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) | |
151 | #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) | |
152 | #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) | |
153 | #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) | |
154 | ||
155 | __le32 tx_cmp_unsed_3; | |
156 | }; | |
157 | ||
158 | struct rx_cmp { | |
159 | __le32 rx_cmp_len_flags_type; | |
160 | #define RX_CMP_CMP_TYPE (0x3f << 0) | |
161 | #define RX_CMP_FLAGS_ERROR (1 << 6) | |
162 | #define RX_CMP_FLAGS_PLACEMENT (7 << 7) | |
163 | #define RX_CMP_FLAGS_RSS_VALID (1 << 10) | |
c13e268c | 164 | #define RX_CMP_FLAGS_PKT_METADATA_PRESENT (1 << 11) |
c0c050c5 | 165 | #define RX_CMP_FLAGS_ITYPES_SHIFT 12 |
7f5515d1 | 166 | #define RX_CMP_FLAGS_ITYPES_MASK 0xf000 |
c0c050c5 MC |
167 | #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) |
168 | #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) | |
169 | #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) | |
170 | #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) | |
171 | #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) | |
172 | #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) | |
173 | #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) | |
174 | #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) | |
175 | #define RX_CMP_LEN (0xffff << 16) | |
176 | #define RX_CMP_LEN_SHIFT 16 | |
177 | ||
178 | u32 rx_cmp_opaque; | |
179 | __le32 rx_cmp_misc_v1; | |
180 | #define RX_CMP_V1 (1 << 0) | |
181 | #define RX_CMP_AGG_BUFS (0x1f << 1) | |
182 | #define RX_CMP_AGG_BUFS_SHIFT 1 | |
183 | #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) | |
184 | #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 | |
185 | #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) | |
186 | #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 | |
187 | ||
188 | __le32 rx_cmp_rss_hash; | |
189 | }; | |
190 | ||
c13e268c MC |
191 | #define BNXT_PTP_RX_TS_VALID(flags) \ |
192 | (((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS) | |
193 | ||
194 | #define BNXT_ALL_RX_TS_VALID(flags) \ | |
195 | !((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT) | |
196 | ||
c0c050c5 MC |
197 | #define RX_CMP_HASH_VALID(rxcmp) \ |
198 | ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) | |
199 | ||
614388ce MC |
200 | #define RSS_PROFILE_ID_MASK 0x1f |
201 | ||
c0c050c5 | 202 | #define RX_CMP_HASH_TYPE(rxcmp) \ |
614388ce MC |
203 | (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ |
204 | RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) | |
c0c050c5 MC |
205 | |
206 | struct rx_cmp_ext { | |
207 | __le32 rx_cmp_flags2; | |
208 | #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 | |
209 | #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) | |
210 | #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) | |
211 | #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) | |
212 | #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) | |
213 | __le32 rx_cmp_meta_data; | |
ed7bc602 | 214 | #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff |
c0c050c5 MC |
215 | #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff |
216 | #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 | |
217 | #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 | |
218 | __le32 rx_cmp_cfa_code_errors_v2; | |
219 | #define RX_CMP_V (1 << 0) | |
220 | #define RX_CMPL_ERRORS_MASK (0x7fff << 1) | |
221 | #define RX_CMPL_ERRORS_SFT 1 | |
222 | #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) | |
223 | #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) | |
224 | #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) | |
225 | #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) | |
226 | #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) | |
227 | #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) | |
228 | #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) | |
229 | #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) | |
230 | #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) | |
231 | #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) | |
232 | #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) | |
233 | #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) | |
234 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) | |
235 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) | |
236 | #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) | |
237 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) | |
238 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) | |
239 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) | |
240 | #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) | |
241 | #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) | |
242 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) | |
243 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) | |
244 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) | |
245 | #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) | |
246 | #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) | |
247 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) | |
248 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) | |
249 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) | |
250 | ||
251 | #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) | |
252 | #define RX_CMPL_CFA_CODE_SFT 16 | |
253 | ||
7f5515d1 | 254 | __le32 rx_cmp_timestamp; |
c0c050c5 MC |
255 | }; |
256 | ||
257 | #define RX_CMP_L2_ERRORS \ | |
258 | cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) | |
259 | ||
260 | #define RX_CMP_L4_CS_BITS \ | |
261 | (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) | |
262 | ||
263 | #define RX_CMP_L4_CS_ERR_BITS \ | |
264 | (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) | |
265 | ||
266 | #define RX_CMP_L4_CS_OK(rxcmp1) \ | |
267 | (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ | |
268 | !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) | |
269 | ||
270 | #define RX_CMP_ENCAP(rxcmp1) \ | |
271 | ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ | |
272 | RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) | |
273 | ||
ee5c7fb3 SP |
274 | #define RX_CMP_CFA_CODE(rxcmpl1) \ |
275 | ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \ | |
276 | RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT) | |
277 | ||
c0c050c5 MC |
278 | struct rx_agg_cmp { |
279 | __le32 rx_agg_cmp_len_flags_type; | |
280 | #define RX_AGG_CMP_TYPE (0x3f << 0) | |
281 | #define RX_AGG_CMP_LEN (0xffff << 16) | |
282 | #define RX_AGG_CMP_LEN_SHIFT 16 | |
283 | u32 rx_agg_cmp_opaque; | |
284 | __le32 rx_agg_cmp_v; | |
285 | #define RX_AGG_CMP_V (1 << 0) | |
218a8a71 MC |
286 | #define RX_AGG_CMP_AGG_ID (0xffff << 16) |
287 | #define RX_AGG_CMP_AGG_ID_SHIFT 16 | |
c0c050c5 MC |
288 | __le32 rx_agg_cmp_unused; |
289 | }; | |
290 | ||
218a8a71 MC |
291 | #define TPA_AGG_AGG_ID(rx_agg) \ |
292 | ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \ | |
293 | RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT) | |
294 | ||
c0c050c5 MC |
295 | struct rx_tpa_start_cmp { |
296 | __le32 rx_tpa_start_cmp_len_flags_type; | |
297 | #define RX_TPA_START_CMP_TYPE (0x3f << 0) | |
298 | #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) | |
299 | #define RX_TPA_START_CMP_FLAGS_SHIFT 6 | |
218a8a71 | 300 | #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6) |
c0c050c5 MC |
301 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) |
302 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 | |
303 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) | |
304 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) | |
305 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) | |
306 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) | |
307 | #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) | |
218a8a71 | 308 | #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11) |
c0c050c5 MC |
309 | #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) |
310 | #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 | |
311 | #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) | |
312 | #define RX_TPA_START_CMP_LEN (0xffff << 16) | |
313 | #define RX_TPA_START_CMP_LEN_SHIFT 16 | |
314 | ||
315 | u32 rx_tpa_start_cmp_opaque; | |
316 | __le32 rx_tpa_start_cmp_misc_v1; | |
317 | #define RX_TPA_START_CMP_V1 (0x1 << 0) | |
318 | #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) | |
319 | #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 | |
320 | #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) | |
321 | #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 | |
218a8a71 MC |
322 | #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16) |
323 | #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16 | |
c0c050c5 MC |
324 | |
325 | __le32 rx_tpa_start_cmp_rss_hash; | |
326 | }; | |
327 | ||
328 | #define TPA_START_HASH_VALID(rx_tpa_start) \ | |
329 | ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ | |
330 | cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) | |
331 | ||
332 | #define TPA_START_HASH_TYPE(rx_tpa_start) \ | |
614388ce MC |
333 | (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ |
334 | RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ | |
335 | RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) | |
c0c050c5 MC |
336 | |
337 | #define TPA_START_AGG_ID(rx_tpa_start) \ | |
338 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ | |
339 | RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) | |
340 | ||
218a8a71 MC |
341 | #define TPA_START_AGG_ID_P5(rx_tpa_start) \ |
342 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ | |
343 | RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5) | |
344 | ||
345 | #define TPA_START_ERROR(rx_tpa_start) \ | |
346 | ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ | |
347 | cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR)) | |
348 | ||
c0c050c5 MC |
349 | struct rx_tpa_start_cmp_ext { |
350 | __le32 rx_tpa_start_cmp_flags2; | |
351 | #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) | |
352 | #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) | |
353 | #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) | |
354 | #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) | |
94758f8d | 355 | #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) |
218a8a71 MC |
356 | #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9) |
357 | #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10) | |
358 | #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10 | |
359 | #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16) | |
360 | #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16 | |
c0c050c5 MC |
361 | |
362 | __le32 rx_tpa_start_cmp_metadata; | |
363 | __le32 rx_tpa_start_cmp_cfa_code_v2; | |
364 | #define RX_TPA_START_CMP_V2 (0x1 << 0) | |
218a8a71 MC |
365 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) |
366 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1 | |
367 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) | |
368 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) | |
369 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1) | |
c0c050c5 MC |
370 | #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) |
371 | #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 | |
94758f8d | 372 | __le32 rx_tpa_start_cmp_hdr_info; |
c0c050c5 MC |
373 | }; |
374 | ||
ee5c7fb3 SP |
375 | #define TPA_START_CFA_CODE(rx_tpa_start) \ |
376 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ | |
377 | RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT) | |
378 | ||
50f011b6 MC |
379 | #define TPA_START_IS_IPV6(rx_tpa_start) \ |
380 | (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \ | |
381 | cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE))) | |
382 | ||
218a8a71 MC |
383 | #define TPA_START_ERROR_CODE(rx_tpa_start) \ |
384 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ | |
385 | RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \ | |
386 | RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT) | |
387 | ||
c0c050c5 MC |
388 | struct rx_tpa_end_cmp { |
389 | __le32 rx_tpa_end_cmp_len_flags_type; | |
390 | #define RX_TPA_END_CMP_TYPE (0x3f << 0) | |
391 | #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) | |
392 | #define RX_TPA_END_CMP_FLAGS_SHIFT 6 | |
393 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) | |
394 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 | |
395 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) | |
396 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) | |
397 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) | |
398 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) | |
399 | #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) | |
400 | #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) | |
401 | #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 | |
402 | #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) | |
403 | #define RX_TPA_END_CMP_LEN (0xffff << 16) | |
404 | #define RX_TPA_END_CMP_LEN_SHIFT 16 | |
405 | ||
406 | u32 rx_tpa_end_cmp_opaque; | |
407 | __le32 rx_tpa_end_cmp_misc_v1; | |
408 | #define RX_TPA_END_CMP_V1 (0x1 << 0) | |
409 | #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) | |
410 | #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 | |
411 | #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) | |
412 | #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 | |
413 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) | |
414 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 | |
415 | #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) | |
416 | #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 | |
218a8a71 MC |
417 | #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16) |
418 | #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16 | |
c0c050c5 MC |
419 | |
420 | __le32 rx_tpa_end_cmp_tsdelta; | |
421 | #define RX_TPA_END_GRO_TS (0x1 << 31) | |
422 | }; | |
423 | ||
424 | #define TPA_END_AGG_ID(rx_tpa_end) \ | |
425 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
426 | RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) | |
427 | ||
218a8a71 MC |
428 | #define TPA_END_AGG_ID_P5(rx_tpa_end) \ |
429 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
430 | RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5) | |
431 | ||
432 | #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \ | |
433 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
434 | RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT) | |
435 | ||
436 | #define TPA_END_AGG_BUFS(rx_tpa_end) \ | |
437 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
438 | RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT) | |
439 | ||
c0c050c5 MC |
440 | #define TPA_END_TPA_SEGS(rx_tpa_end) \ |
441 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
442 | RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) | |
443 | ||
444 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ | |
445 | cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ | |
446 | RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) | |
447 | ||
448 | #define TPA_END_GRO(rx_tpa_end) \ | |
449 | ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ | |
450 | RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) | |
451 | ||
452 | #define TPA_END_GRO_TS(rx_tpa_end) \ | |
a58a3e68 MC |
453 | (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ |
454 | cpu_to_le32(RX_TPA_END_GRO_TS))) | |
c0c050c5 MC |
455 | |
456 | struct rx_tpa_end_cmp_ext { | |
457 | __le32 rx_tpa_end_cmp_dup_acks; | |
458 | #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) | |
218a8a71 MC |
459 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16) |
460 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16 | |
461 | #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24) | |
462 | #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24 | |
c0c050c5 MC |
463 | |
464 | __le32 rx_tpa_end_cmp_seg_len; | |
465 | #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) | |
466 | ||
467 | __le32 rx_tpa_end_cmp_errors_v2; | |
468 | #define RX_TPA_END_CMP_V2 (0x1 << 0) | |
69c149e2 | 469 | #define RX_TPA_END_CMP_ERRORS (0x3 << 1) |
218a8a71 | 470 | #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1) |
c0c050c5 | 471 | #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 |
218a8a71 MC |
472 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) |
473 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) | |
474 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) | |
475 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1) | |
476 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1) | |
c0c050c5 MC |
477 | |
478 | u32 rx_tpa_end_cmp_start_opaque; | |
479 | }; | |
480 | ||
69c149e2 MC |
481 | #define TPA_END_ERRORS(rx_tpa_end_ext) \ |
482 | ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \ | |
483 | cpu_to_le32(RX_TPA_END_CMP_ERRORS)) | |
484 | ||
218a8a71 MC |
485 | #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \ |
486 | ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \ | |
487 | RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \ | |
488 | RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5) | |
489 | ||
490 | #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \ | |
491 | ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \ | |
492 | RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5) | |
493 | ||
acfb50e4 VV |
494 | #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \ |
495 | (((data1) & \ | |
496 | ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ | |
497 | ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL) | |
498 | ||
8f6c5e4d EP |
499 | #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \ |
500 | (((data1) & \ | |
501 | ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ | |
502 | ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION) | |
503 | ||
aadb0b1a EP |
504 | #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \ |
505 | ((data2) & \ | |
506 | ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK) | |
507 | ||
7e914027 MC |
508 | #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \ |
509 | !!((data1) & \ | |
510 | ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC) | |
511 | ||
512 | #define EVENT_DATA1_RECOVERY_ENABLED(data1) \ | |
513 | !!((data1) & \ | |
514 | ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED) | |
515 | ||
abf90ac2 PC |
516 | #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ |
517 | (((data1) & \ | |
518 | ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\ | |
519 | ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) | |
520 | ||
521 | #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \ | |
522 | (((data2) & \ | |
523 | ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\ | |
524 | ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT) | |
525 | ||
e38287b7 MC |
526 | struct nqe_cn { |
527 | __le16 type; | |
528 | #define NQ_CN_TYPE_MASK 0x3fUL | |
529 | #define NQ_CN_TYPE_SFT 0 | |
530 | #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL | |
531 | #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION | |
532 | __le16 reserved16; | |
533 | __le32 cq_handle_low; | |
534 | __le32 v; | |
535 | #define NQ_CN_V 0x1UL | |
536 | __le32 cq_handle_high; | |
537 | }; | |
538 | ||
c0c050c5 MC |
539 | #define DB_IDX_MASK 0xffffff |
540 | #define DB_IDX_VALID (0x1 << 26) | |
541 | #define DB_IRQ_DIS (0x1 << 27) | |
542 | #define DB_KEY_TX (0x0 << 28) | |
543 | #define DB_KEY_RX (0x1 << 28) | |
544 | #define DB_KEY_CP (0x2 << 28) | |
545 | #define DB_KEY_ST (0x3 << 28) | |
546 | #define DB_KEY_TX_PUSH (0x4 << 28) | |
547 | #define DB_LONG_TX_PUSH (0x2 << 24) | |
548 | ||
e4060d30 MC |
549 | #define BNXT_MIN_ROCE_CP_RINGS 2 |
550 | #define BNXT_MIN_ROCE_STAT_CTXS 1 | |
551 | ||
e38287b7 MC |
552 | /* 64-bit doorbell */ |
553 | #define DBR_INDEX_MASK 0x0000000000ffffffULL | |
554 | #define DBR_XID_MASK 0x000fffff00000000ULL | |
555 | #define DBR_XID_SFT 32 | |
556 | #define DBR_PATH_L2 (0x1ULL << 56) | |
557 | #define DBR_TYPE_SQ (0x0ULL << 60) | |
558 | #define DBR_TYPE_RQ (0x1ULL << 60) | |
559 | #define DBR_TYPE_SRQ (0x2ULL << 60) | |
560 | #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) | |
561 | #define DBR_TYPE_CQ (0x4ULL << 60) | |
562 | #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) | |
563 | #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) | |
564 | #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) | |
565 | #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) | |
566 | #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) | |
567 | #define DBR_TYPE_NQ (0xaULL << 60) | |
568 | #define DBR_TYPE_NQ_ARM (0xbULL << 60) | |
569 | #define DBR_TYPE_NULL (0xfULL << 60) | |
570 | ||
ebdf73dc MC |
571 | #define DB_PF_OFFSET_P5 0x10000 |
572 | #define DB_VF_OFFSET_P5 0x4000 | |
573 | ||
c0c050c5 MC |
574 | #define INVALID_HW_RING_ID ((u16)-1) |
575 | ||
c0c050c5 MC |
576 | /* The hardware supports certain page sizes. Use the supported page sizes |
577 | * to allocate the rings. | |
578 | */ | |
579 | #if (PAGE_SHIFT < 12) | |
580 | #define BNXT_PAGE_SHIFT 12 | |
581 | #elif (PAGE_SHIFT <= 13) | |
582 | #define BNXT_PAGE_SHIFT PAGE_SHIFT | |
583 | #elif (PAGE_SHIFT < 16) | |
584 | #define BNXT_PAGE_SHIFT 13 | |
585 | #else | |
586 | #define BNXT_PAGE_SHIFT 16 | |
587 | #endif | |
588 | ||
589 | #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) | |
590 | ||
2839f28b MC |
591 | /* The RXBD length is 16-bit so we can only support page sizes < 64K */ |
592 | #if (PAGE_SHIFT > 15) | |
593 | #define BNXT_RX_PAGE_SHIFT 15 | |
594 | #else | |
595 | #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT | |
596 | #endif | |
597 | ||
598 | #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) | |
599 | ||
c61fb99c | 600 | #define BNXT_MAX_MTU 9500 |
1abeacc1 MC |
601 | |
602 | /* First RX buffer page in XDP multi-buf mode | |
603 | * | |
604 | * +-------------------------------------------------------------------------+ | |
605 | * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info| | |
606 | * | (bp->rx_dma_offset) | | | | |
607 | * +-------------------------------------------------------------------------+ | |
608 | */ | |
609 | #define BNXT_MAX_PAGE_MODE_MTU_SBUF \ | |
c6d30e83 | 610 | ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \ |
b231c3f3 AG |
611 | XDP_PACKET_HEADROOM) |
612 | #define BNXT_MAX_PAGE_MODE_MTU \ | |
1abeacc1 MC |
613 | (BNXT_MAX_PAGE_MODE_MTU_SBUF - \ |
614 | SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info))) | |
c61fb99c | 615 | |
4ffcd582 | 616 | #define BNXT_MIN_PKT_SIZE 52 |
c0c050c5 | 617 | |
51dd55b5 MC |
618 | #define BNXT_DEFAULT_RX_RING_SIZE 511 |
619 | #define BNXT_DEFAULT_TX_RING_SIZE 511 | |
c0c050c5 MC |
620 | |
621 | #define MAX_TPA 64 | |
79632e9b | 622 | #define MAX_TPA_P5 256 |
ec4d8e7c | 623 | #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1) |
79632e9b | 624 | #define MAX_TPA_SEGS_P5 0x3f |
c0c050c5 | 625 | |
d0a42d6f | 626 | #if (BNXT_PAGE_SHIFT == 16) |
c1129b51 MC |
627 | #define MAX_RX_PAGES_AGG_ENA 1 |
628 | #define MAX_RX_PAGES 4 | |
d0a42d6f MC |
629 | #define MAX_RX_AGG_PAGES 4 |
630 | #define MAX_TX_PAGES 1 | |
c1129b51 | 631 | #define MAX_CP_PAGES 16 |
d0a42d6f | 632 | #else |
c1129b51 MC |
633 | #define MAX_RX_PAGES_AGG_ENA 8 |
634 | #define MAX_RX_PAGES 32 | |
c0c050c5 MC |
635 | #define MAX_RX_AGG_PAGES 32 |
636 | #define MAX_TX_PAGES 8 | |
c1129b51 | 637 | #define MAX_CP_PAGES 128 |
d0a42d6f | 638 | #endif |
c0c050c5 MC |
639 | |
640 | #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) | |
641 | #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) | |
642 | #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) | |
643 | ||
644 | #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) | |
645 | #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) | |
646 | ||
647 | #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) | |
648 | ||
649 | #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) | |
650 | #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) | |
651 | ||
652 | #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) | |
653 | ||
654 | #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) | |
c1129b51 | 655 | #define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1) |
c0c050c5 MC |
656 | #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) |
657 | #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) | |
658 | ||
5bed8b07 MC |
659 | /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra |
660 | * BD because the first TX BD is always a long BD. | |
661 | */ | |
662 | #define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2) | |
663 | ||
c0c050c5 MC |
664 | #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) |
665 | #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) | |
666 | ||
667 | #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
668 | #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) | |
669 | ||
670 | #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
671 | #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) | |
672 | ||
673 | #define TX_CMP_VALID(txcmp, raw_cons) \ | |
674 | (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ | |
675 | !((raw_cons) & bp->cp_bit)) | |
676 | ||
677 | #define RX_CMP_VALID(rxcmp1, raw_cons) \ | |
678 | (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ | |
679 | !((raw_cons) & bp->cp_bit)) | |
680 | ||
681 | #define RX_AGG_CMP_VALID(agg, raw_cons) \ | |
682 | (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ | |
683 | !((raw_cons) & bp->cp_bit)) | |
684 | ||
0fcec985 MC |
685 | #define NQ_CMP_VALID(nqcmp, raw_cons) \ |
686 | (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit)) | |
687 | ||
c0c050c5 MC |
688 | #define TX_CMP_TYPE(txcmp) \ |
689 | (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) | |
690 | ||
691 | #define RX_CMP_TYPE(rxcmp) \ | |
692 | (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) | |
693 | ||
694 | #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) | |
695 | ||
696 | #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) | |
697 | ||
698 | #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) | |
699 | ||
700 | #define ADV_RAW_CMP(idx, n) ((idx) + (n)) | |
701 | #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) | |
702 | #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) | |
703 | #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) | |
704 | ||
ff4fe81d | 705 | #define DFLT_HWRM_CMD_TIMEOUT 500 |
760b6d33 | 706 | |
f18c2b77 AG |
707 | #define BNXT_RX_EVENT 1 |
708 | #define BNXT_AGG_EVENT 2 | |
709 | #define BNXT_TX_EVENT 4 | |
710 | #define BNXT_REDIRECT_EVENT 8 | |
4e5dbbda | 711 | |
c0c050c5 | 712 | struct bnxt_sw_tx_bd { |
f18c2b77 AG |
713 | union { |
714 | struct sk_buff *skb; | |
715 | struct xdp_frame *xdpf; | |
716 | }; | |
c0c050c5 | 717 | DEFINE_DMA_UNMAP_ADDR(mapping); |
f18c2b77 | 718 | DEFINE_DMA_UNMAP_LEN(len); |
a7559bc8 | 719 | struct page *page; |
c0c050c5 MC |
720 | u8 is_gso; |
721 | u8 is_push; | |
c1ba92a8 | 722 | u8 action; |
a7559bc8 AG |
723 | unsigned short nr_frags; |
724 | u16 rx_prod; | |
c0c050c5 MC |
725 | }; |
726 | ||
727 | struct bnxt_sw_rx_bd { | |
6bb19474 MC |
728 | void *data; |
729 | u8 *data_ptr; | |
11cd119d | 730 | dma_addr_t mapping; |
c0c050c5 MC |
731 | }; |
732 | ||
733 | struct bnxt_sw_rx_agg_bd { | |
734 | struct page *page; | |
89d0a06c | 735 | unsigned int offset; |
c0c050c5 MC |
736 | dma_addr_t mapping; |
737 | }; | |
738 | ||
e9696ff3 MC |
739 | struct bnxt_mem_init { |
740 | u8 init_val; | |
741 | u16 offset; | |
742 | #define BNXT_MEM_INVALID_OFFSET 0xffff | |
743 | u16 size; | |
744 | }; | |
745 | ||
6fe19886 | 746 | struct bnxt_ring_mem_info { |
c0c050c5 MC |
747 | int nr_pages; |
748 | int page_size; | |
4f49b2b8 | 749 | u16 flags; |
66cca20a MC |
750 | #define BNXT_RMEM_VALID_PTE_FLAG 1 |
751 | #define BNXT_RMEM_RING_PTE_FLAG 2 | |
4f49b2b8 MC |
752 | #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 |
753 | ||
754 | u16 depth; | |
e9696ff3 | 755 | struct bnxt_mem_init *mem_init; |
66cca20a | 756 | |
c0c050c5 MC |
757 | void **pg_arr; |
758 | dma_addr_t *dma_arr; | |
759 | ||
760 | __le64 *pg_tbl; | |
761 | dma_addr_t pg_tbl_map; | |
762 | ||
763 | int vmem_size; | |
764 | void **vmem; | |
6fe19886 MC |
765 | }; |
766 | ||
767 | struct bnxt_ring_struct { | |
768 | struct bnxt_ring_mem_info ring_mem; | |
c0c050c5 MC |
769 | |
770 | u16 fw_ring_id; /* Ring id filled by Chimp FW */ | |
9899bb59 MC |
771 | union { |
772 | u16 grp_idx; | |
773 | u16 map_idx; /* Used by cmpl rings */ | |
774 | }; | |
23aefdd7 | 775 | u32 handle; |
c0c050c5 MC |
776 | u8 queue_id; |
777 | }; | |
778 | ||
779 | struct tx_push_bd { | |
780 | __le32 doorbell; | |
4419dbe6 MC |
781 | __le32 tx_bd_len_flags_type; |
782 | u32 tx_bd_opaque; | |
c0c050c5 MC |
783 | struct tx_bd_ext txbd2; |
784 | }; | |
785 | ||
4419dbe6 MC |
786 | struct tx_push_buffer { |
787 | struct tx_push_bd push_bd; | |
788 | u32 data[25]; | |
789 | }; | |
790 | ||
697197e5 MC |
791 | struct bnxt_db_info { |
792 | void __iomem *doorbell; | |
793 | union { | |
794 | u64 db_key64; | |
795 | u32 db_key32; | |
796 | }; | |
797 | }; | |
798 | ||
c0c050c5 | 799 | struct bnxt_tx_ring_info { |
b6ab4b01 | 800 | struct bnxt_napi *bnapi; |
c0c050c5 MC |
801 | u16 tx_prod; |
802 | u16 tx_cons; | |
a960dec9 | 803 | u16 txq_index; |
e8d8c5d8 | 804 | u8 kick_pending; |
697197e5 | 805 | struct bnxt_db_info tx_db; |
c0c050c5 MC |
806 | |
807 | struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; | |
808 | struct bnxt_sw_tx_bd *tx_buf_ring; | |
809 | ||
810 | dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; | |
811 | ||
4419dbe6 | 812 | struct tx_push_buffer *tx_push; |
c0c050c5 | 813 | dma_addr_t tx_push_mapping; |
4419dbe6 | 814 | __le64 data_mapping; |
c0c050c5 MC |
815 | |
816 | #define BNXT_DEV_STATE_CLOSING 0x1 | |
817 | u32 dev_state; | |
818 | ||
819 | struct bnxt_ring_struct tx_ring_struct; | |
4f81def2 PC |
820 | /* Synchronize simultaneous xdp_xmit on same ring */ |
821 | spinlock_t xdp_tx_lock; | |
c0c050c5 MC |
822 | }; |
823 | ||
74706afa MC |
824 | #define BNXT_LEGACY_COAL_CMPL_PARAMS \ |
825 | (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \ | |
826 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \ | |
827 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \ | |
828 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \ | |
829 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \ | |
830 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \ | |
831 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \ | |
832 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \ | |
833 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT) | |
834 | ||
835 | #define BNXT_COAL_CMPL_ENABLES \ | |
836 | (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \ | |
837 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \ | |
838 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \ | |
839 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT) | |
840 | ||
841 | #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \ | |
842 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN | |
843 | ||
844 | #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \ | |
845 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT | |
846 | ||
847 | struct bnxt_coal_cap { | |
848 | u32 cmpl_params; | |
849 | u32 nq_params; | |
850 | u16 num_cmpl_dma_aggr_max; | |
851 | u16 num_cmpl_dma_aggr_during_int_max; | |
852 | u16 cmpl_aggr_dma_tmr_max; | |
853 | u16 cmpl_aggr_dma_tmr_during_int_max; | |
854 | u16 int_lat_tmr_min_max; | |
855 | u16 int_lat_tmr_max_max; | |
856 | u16 num_cmpl_aggr_int_max; | |
857 | u16 timer_units; | |
858 | }; | |
859 | ||
6a8788f2 AG |
860 | struct bnxt_coal { |
861 | u16 coal_ticks; | |
862 | u16 coal_ticks_irq; | |
863 | u16 coal_bufs; | |
864 | u16 coal_bufs_irq; | |
865 | /* RING_IDLE enabled when coal ticks < idle_thresh */ | |
866 | u16 idle_thresh; | |
867 | u8 bufs_per_record; | |
868 | u8 budget; | |
df78ea22 | 869 | u16 flags; |
6a8788f2 AG |
870 | }; |
871 | ||
c0c050c5 | 872 | struct bnxt_tpa_info { |
6bb19474 MC |
873 | void *data; |
874 | u8 *data_ptr; | |
c0c050c5 MC |
875 | dma_addr_t mapping; |
876 | u16 len; | |
877 | unsigned short gso_type; | |
878 | u32 flags2; | |
879 | u32 metadata; | |
880 | enum pkt_hash_types hash_type; | |
881 | u32 rss_hash; | |
94758f8d MC |
882 | u32 hdr_info; |
883 | ||
884 | #define BNXT_TPA_L4_SIZE(hdr_info) \ | |
885 | (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) | |
886 | ||
887 | #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ | |
888 | (((hdr_info) >> 18) & 0x1ff) | |
889 | ||
890 | #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ | |
891 | (((hdr_info) >> 9) & 0x1ff) | |
892 | ||
893 | #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ | |
894 | ((hdr_info) & 0x1ff) | |
4ab0c6a8 SP |
895 | |
896 | u16 cfa_code; /* cfa_code in TPA start compl */ | |
79632e9b MC |
897 | u8 agg_count; |
898 | struct rx_agg_cmp *agg_arr; | |
c0c050c5 MC |
899 | }; |
900 | ||
ec4d8e7c MC |
901 | #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG) |
902 | ||
903 | struct bnxt_tpa_idx_map { | |
904 | u16 agg_id_tbl[1024]; | |
905 | unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE]; | |
906 | }; | |
907 | ||
c0c050c5 | 908 | struct bnxt_rx_ring_info { |
b6ab4b01 | 909 | struct bnxt_napi *bnapi; |
c0c050c5 MC |
910 | u16 rx_prod; |
911 | u16 rx_agg_prod; | |
912 | u16 rx_sw_agg_prod; | |
376a5b86 | 913 | u16 rx_next_cons; |
697197e5 MC |
914 | struct bnxt_db_info rx_db; |
915 | struct bnxt_db_info rx_agg_db; | |
c0c050c5 | 916 | |
c6d30e83 MC |
917 | struct bpf_prog *xdp_prog; |
918 | ||
c0c050c5 MC |
919 | struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; |
920 | struct bnxt_sw_rx_bd *rx_buf_ring; | |
921 | ||
922 | struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; | |
923 | struct bnxt_sw_rx_agg_bd *rx_agg_ring; | |
924 | ||
925 | unsigned long *rx_agg_bmap; | |
926 | u16 rx_agg_bmap_size; | |
927 | ||
928 | dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; | |
929 | dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; | |
930 | ||
931 | struct bnxt_tpa_info *rx_tpa; | |
ec4d8e7c | 932 | struct bnxt_tpa_idx_map *rx_tpa_idx_map; |
c0c050c5 MC |
933 | |
934 | struct bnxt_ring_struct rx_ring_struct; | |
935 | struct bnxt_ring_struct rx_agg_ring_struct; | |
96a8604f | 936 | struct xdp_rxq_info xdp_rxq; |
322b87ca | 937 | struct page_pool *page_pool; |
c0c050c5 MC |
938 | }; |
939 | ||
9d8b5f05 MC |
940 | struct bnxt_rx_sw_stats { |
941 | u64 rx_l4_csum_errors; | |
8a27d4b9 | 942 | u64 rx_resets; |
9d8b5f05 | 943 | u64 rx_buf_errors; |
907fd4a2 | 944 | u64 rx_oom_discards; |
40bedf7c | 945 | u64 rx_netpoll_discards; |
9d8b5f05 MC |
946 | }; |
947 | ||
8becd196 MC |
948 | struct bnxt_tx_sw_stats { |
949 | u64 tx_resets; | |
950 | }; | |
951 | ||
9d8b5f05 MC |
952 | struct bnxt_cmn_sw_stats { |
953 | u64 missed_irqs; | |
954 | }; | |
955 | ||
956 | struct bnxt_sw_stats { | |
957 | struct bnxt_rx_sw_stats rx; | |
8becd196 | 958 | struct bnxt_tx_sw_stats tx; |
9d8b5f05 MC |
959 | struct bnxt_cmn_sw_stats cmn; |
960 | }; | |
961 | ||
4c70dbe3 MC |
962 | struct bnxt_total_ring_err_stats { |
963 | u64 rx_total_l4_csum_errors; | |
964 | u64 rx_total_resets; | |
965 | u64 rx_total_buf_errors; | |
966 | u64 rx_total_oom_discards; | |
967 | u64 rx_total_netpoll_discards; | |
968 | u64 rx_total_ring_discards; | |
8becd196 | 969 | u64 tx_total_resets; |
4c70dbe3 MC |
970 | u64 tx_total_ring_discards; |
971 | u64 total_missed_irqs; | |
972 | }; | |
973 | ||
177a6cde | 974 | struct bnxt_stats_mem { |
a37120b2 MC |
975 | u64 *sw_stats; |
976 | u64 *hw_masks; | |
177a6cde MC |
977 | void *hw_stats; |
978 | dma_addr_t hw_stats_map; | |
979 | int len; | |
980 | }; | |
981 | ||
c0c050c5 | 982 | struct bnxt_cp_ring_info { |
50e3ab78 | 983 | struct bnxt_napi *bnapi; |
c0c050c5 | 984 | u32 cp_raw_cons; |
697197e5 | 985 | struct bnxt_db_info cp_db; |
c0c050c5 | 986 | |
3675b92f | 987 | u8 had_work_done:1; |
0fcec985 | 988 | u8 has_more_work:1; |
3675b92f | 989 | |
ffd77621 MC |
990 | u32 last_cp_raw_cons; |
991 | ||
6a8788f2 AG |
992 | struct bnxt_coal rx_ring_coal; |
993 | u64 rx_packets; | |
994 | u64 rx_bytes; | |
995 | u64 event_ctr; | |
996 | ||
8960b389 | 997 | struct dim dim; |
6a8788f2 | 998 | |
e38287b7 | 999 | union { |
03c74487 MC |
1000 | struct tx_cmp **cp_desc_ring; |
1001 | struct nqe_cn **nq_desc_ring; | |
e38287b7 | 1002 | }; |
c0c050c5 | 1003 | |
03c74487 | 1004 | dma_addr_t *cp_desc_mapping; |
c0c050c5 | 1005 | |
177a6cde | 1006 | struct bnxt_stats_mem stats; |
c0c050c5 | 1007 | u32 hw_stats_ctx_id; |
9d8b5f05 MC |
1008 | |
1009 | struct bnxt_sw_stats sw_stats; | |
c0c050c5 MC |
1010 | |
1011 | struct bnxt_ring_struct cp_ring_struct; | |
e38287b7 MC |
1012 | |
1013 | struct bnxt_cp_ring_info *cp_ring_arr[2]; | |
50e3ab78 MC |
1014 | #define BNXT_RX_HDL 0 |
1015 | #define BNXT_TX_HDL 1 | |
c0c050c5 MC |
1016 | }; |
1017 | ||
1018 | struct bnxt_napi { | |
1019 | struct napi_struct napi; | |
1020 | struct bnxt *bp; | |
1021 | ||
1022 | int index; | |
1023 | struct bnxt_cp_ring_info cp_ring; | |
b6ab4b01 MC |
1024 | struct bnxt_rx_ring_info *rx_ring; |
1025 | struct bnxt_tx_ring_info *tx_ring; | |
c0c050c5 | 1026 | |
fa3e93e8 | 1027 | void (*tx_int)(struct bnxt *, struct bnxt_napi *, |
37b61cda | 1028 | int budget); |
3675b92f MC |
1029 | int tx_pkts; |
1030 | u8 events; | |
2b56b3d9 | 1031 | u8 tx_fault:1; |
3675b92f | 1032 | |
fa3e93e8 MC |
1033 | u32 flags; |
1034 | #define BNXT_NAPI_FLAG_XDP 0x1 | |
1035 | ||
fa7e2812 | 1036 | bool in_reset; |
c0c050c5 MC |
1037 | }; |
1038 | ||
c0c050c5 MC |
1039 | struct bnxt_irq { |
1040 | irq_handler_t handler; | |
1041 | unsigned int vector; | |
56f0fd80 VV |
1042 | u8 requested:1; |
1043 | u8 have_cpumask:1; | |
c0c050c5 | 1044 | char name[IFNAMSIZ + 2]; |
56f0fd80 | 1045 | cpumask_var_t cpu_mask; |
c0c050c5 MC |
1046 | }; |
1047 | ||
1048 | #define HWRM_RING_ALLOC_TX 0x1 | |
1049 | #define HWRM_RING_ALLOC_RX 0x2 | |
1050 | #define HWRM_RING_ALLOC_AGG 0x4 | |
1051 | #define HWRM_RING_ALLOC_CMPL 0x8 | |
697197e5 | 1052 | #define HWRM_RING_ALLOC_NQ 0x10 |
c0c050c5 MC |
1053 | |
1054 | #define INVALID_STATS_CTX_ID -1 | |
1055 | ||
c0c050c5 MC |
1056 | struct bnxt_ring_grp_info { |
1057 | u16 fw_stats_ctx; | |
1058 | u16 fw_grp_id; | |
1059 | u16 rx_fw_ring_id; | |
1060 | u16 agg_fw_ring_id; | |
1061 | u16 cp_fw_ring_id; | |
1062 | }; | |
1063 | ||
1064 | struct bnxt_vnic_info { | |
1065 | u16 fw_vnic_id; /* returned by Chimp during alloc */ | |
44c6f72a | 1066 | #define BNXT_MAX_CTX_PER_VNIC 8 |
94ce9caa | 1067 | u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; |
c0c050c5 MC |
1068 | u16 fw_l2_ctx_id; |
1069 | #define BNXT_MAX_UC_ADDRS 4 | |
1070 | __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; | |
1071 | /* index 0 always dev_addr */ | |
1072 | u16 uc_filter_count; | |
1073 | u8 *uc_list; | |
1074 | ||
1075 | u16 *fw_grp_ids; | |
c0c050c5 MC |
1076 | dma_addr_t rss_table_dma_addr; |
1077 | __le16 *rss_table; | |
1078 | dma_addr_t rss_hash_key_dma_addr; | |
1079 | u64 *rss_hash_key; | |
34370d24 MC |
1080 | int rss_table_size; |
1081 | #define BNXT_RSS_TABLE_ENTRIES_P5 64 | |
1082 | #define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4) | |
1083 | #define BNXT_RSS_TABLE_MAX_TBL_P5 8 | |
1084 | #define BNXT_MAX_RSS_TABLE_SIZE_P5 \ | |
1085 | (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5) | |
1667cbf6 MC |
1086 | #define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \ |
1087 | (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5) | |
34370d24 | 1088 | |
c0c050c5 MC |
1089 | u32 rx_mask; |
1090 | ||
1091 | u8 *mc_list; | |
1092 | int mc_list_size; | |
1093 | int mc_list_count; | |
1094 | dma_addr_t mc_list_mapping; | |
1095 | #define BNXT_MAX_MC_ADDRS 16 | |
1096 | ||
1097 | u32 flags; | |
1098 | #define BNXT_VNIC_RSS_FLAG 1 | |
1099 | #define BNXT_VNIC_RFS_FLAG 2 | |
1100 | #define BNXT_VNIC_MCAST_FLAG 4 | |
1101 | #define BNXT_VNIC_UCAST_FLAG 8 | |
ae10ae74 | 1102 | #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10 |
c0c050c5 MC |
1103 | }; |
1104 | ||
6a4f2947 MC |
1105 | struct bnxt_hw_resc { |
1106 | u16 min_rsscos_ctxs; | |
c0c050c5 | 1107 | u16 max_rsscos_ctxs; |
6a4f2947 | 1108 | u16 min_cp_rings; |
c0c050c5 | 1109 | u16 max_cp_rings; |
6a4f2947 MC |
1110 | u16 resv_cp_rings; |
1111 | u16 min_tx_rings; | |
c0c050c5 | 1112 | u16 max_tx_rings; |
6a4f2947 | 1113 | u16 resv_tx_rings; |
db4723b3 | 1114 | u16 max_tx_sch_inputs; |
6a4f2947 | 1115 | u16 min_rx_rings; |
c0c050c5 | 1116 | u16 max_rx_rings; |
6a4f2947 MC |
1117 | u16 resv_rx_rings; |
1118 | u16 min_hw_ring_grps; | |
b72d4a68 | 1119 | u16 max_hw_ring_grps; |
6a4f2947 MC |
1120 | u16 resv_hw_ring_grps; |
1121 | u16 min_l2_ctxs; | |
c0c050c5 | 1122 | u16 max_l2_ctxs; |
6a4f2947 | 1123 | u16 min_vnics; |
c0c050c5 | 1124 | u16 max_vnics; |
6a4f2947 MC |
1125 | u16 resv_vnics; |
1126 | u16 min_stat_ctxs; | |
c0c050c5 | 1127 | u16 max_stat_ctxs; |
780baad4 | 1128 | u16 resv_stat_ctxs; |
f7588cd8 | 1129 | u16 max_nqs; |
6a4f2947 | 1130 | u16 max_irqs; |
75720e63 | 1131 | u16 resv_irqs; |
6a4f2947 MC |
1132 | }; |
1133 | ||
1134 | #if defined(CONFIG_BNXT_SRIOV) | |
1135 | struct bnxt_vf_info { | |
1136 | u16 fw_fid; | |
91cdda40 VV |
1137 | u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */ |
1138 | u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only | |
1139 | * stored by PF. | |
1140 | */ | |
c0c050c5 | 1141 | u16 vlan; |
2a516444 | 1142 | u16 func_qcfg_flags; |
c0c050c5 | 1143 | u32 flags; |
c2715368 | 1144 | #define BNXT_VF_QOS 0x1 |
c0c050c5 MC |
1145 | #define BNXT_VF_SPOOFCHK 0x2 |
1146 | #define BNXT_VF_LINK_FORCED 0x4 | |
1147 | #define BNXT_VF_LINK_UP 0x8 | |
746df139 | 1148 | #define BNXT_VF_TRUST 0x10 |
c0c050c5 MC |
1149 | u32 min_tx_rate; |
1150 | u32 max_tx_rate; | |
1151 | void *hwrm_cmd_req_addr; | |
1152 | dma_addr_t hwrm_cmd_req_dma_addr; | |
1153 | }; | |
379a80a1 | 1154 | #endif |
c0c050c5 MC |
1155 | |
1156 | struct bnxt_pf_info { | |
1157 | #define BNXT_FIRST_PF_FID 1 | |
1158 | #define BNXT_FIRST_VF_FID 128 | |
a58a3e68 MC |
1159 | u16 fw_fid; |
1160 | u16 port_id; | |
c0c050c5 | 1161 | u8 mac_addr[ETH_ALEN]; |
c0c050c5 MC |
1162 | u32 first_vf_id; |
1163 | u16 active_vfs; | |
230d1f0d | 1164 | u16 registered_vfs; |
c0c050c5 MC |
1165 | u16 max_vfs; |
1166 | u32 max_encap_records; | |
1167 | u32 max_decap_records; | |
1168 | u32 max_tx_em_flows; | |
1169 | u32 max_tx_wm_flows; | |
1170 | u32 max_rx_em_flows; | |
1171 | u32 max_rx_wm_flows; | |
1172 | unsigned long *vf_event_bmap; | |
1173 | u16 hwrm_cmd_req_pages; | |
4673d664 MC |
1174 | u8 vf_resv_strategy; |
1175 | #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0 | |
1176 | #define BNXT_VF_RESV_STRATEGY_MINIMAL 1 | |
bf82736d | 1177 | #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2 |
c0c050c5 MC |
1178 | void *hwrm_cmd_req_addr[4]; |
1179 | dma_addr_t hwrm_cmd_req_dma_addr[4]; | |
1180 | struct bnxt_vf_info *vf; | |
1181 | }; | |
c0c050c5 MC |
1182 | |
1183 | struct bnxt_ntuple_filter { | |
1184 | struct hlist_node hash; | |
a54c4d74 | 1185 | u8 dst_mac_addr[ETH_ALEN]; |
c0c050c5 MC |
1186 | u8 src_mac_addr[ETH_ALEN]; |
1187 | struct flow_keys fkeys; | |
1188 | __le64 filter_id; | |
1189 | u16 sw_id; | |
a54c4d74 | 1190 | u8 l2_fltr_idx; |
c0c050c5 MC |
1191 | u16 rxq; |
1192 | u32 flow_id; | |
1193 | unsigned long state; | |
1194 | #define BNXT_FLTR_VALID 0 | |
1195 | #define BNXT_FLTR_UPDATE 1 | |
1196 | }; | |
1197 | ||
c0c050c5 | 1198 | struct bnxt_link_info { |
03efbec0 | 1199 | u8 phy_type; |
c0c050c5 MC |
1200 | u8 media_type; |
1201 | u8 transceiver; | |
1202 | u8 phy_addr; | |
1203 | u8 phy_link_status; | |
1204 | #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK | |
1205 | #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL | |
1206 | #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK | |
1207 | u8 wire_speed; | |
3128e811 MC |
1208 | u8 phy_state; |
1209 | #define BNXT_PHY_STATE_ENABLED 0 | |
1210 | #define BNXT_PHY_STATE_DISABLED 1 | |
1211 | ||
0f5a4841 EP |
1212 | u8 link_state; |
1213 | #define BNXT_LINK_STATE_UNKNOWN 0 | |
1214 | #define BNXT_LINK_STATE_DOWN 1 | |
1215 | #define BNXT_LINK_STATE_UP 2 | |
1216 | #define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP) | |
c0c050c5 | 1217 | u8 duplex; |
acb20054 MC |
1218 | #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF |
1219 | #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL | |
c0c050c5 MC |
1220 | u8 pause; |
1221 | #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX | |
1222 | #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX | |
1223 | #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ | |
1224 | PORT_PHY_QCFG_RESP_PAUSE_TX) | |
3277360e | 1225 | u8 lp_pause; |
c0c050c5 MC |
1226 | u8 auto_pause_setting; |
1227 | u8 force_pause_setting; | |
1228 | u8 duplex_setting; | |
1229 | u8 auto_mode; | |
1230 | #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ | |
1231 | (mode) <= BNXT_LINK_AUTO_MSK) | |
1232 | #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE | |
1233 | #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS | |
1234 | #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED | |
1235 | #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW | |
11f15ed3 | 1236 | #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK |
c0c050c5 MC |
1237 | #define PHY_VER_LEN 3 |
1238 | u8 phy_ver[PHY_VER_LEN]; | |
1239 | u16 link_speed; | |
1240 | #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB | |
1241 | #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB | |
1242 | #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB | |
1243 | #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB | |
1244 | #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB | |
1245 | #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB | |
1246 | #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB | |
1247 | #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB | |
1248 | #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB | |
38a21b34 | 1249 | #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB |
581bce7b | 1250 | #define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB |
c0c050c5 | 1251 | u16 support_speeds; |
d058426e | 1252 | u16 support_pam4_speeds; |
68515a18 | 1253 | u16 auto_link_speeds; /* fw adv setting */ |
c0c050c5 MC |
1254 | #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB |
1255 | #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB | |
1256 | #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB | |
1257 | #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB | |
1258 | #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB | |
1259 | #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB | |
1260 | #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB | |
1261 | #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB | |
1262 | #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB | |
38a21b34 | 1263 | #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB |
d058426e EP |
1264 | u16 auto_pam4_link_speeds; |
1265 | #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G | |
1266 | #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G | |
1267 | #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G | |
93ed8117 | 1268 | u16 support_auto_speeds; |
d058426e | 1269 | u16 support_pam4_auto_speeds; |
3277360e | 1270 | u16 lp_auto_link_speeds; |
d058426e | 1271 | u16 lp_auto_pam4_link_speeds; |
c0c050c5 | 1272 | u16 force_link_speed; |
d058426e | 1273 | u16 force_pam4_link_speed; |
c0c050c5 | 1274 | u32 preemphasis; |
42ee18fe | 1275 | u8 module_status; |
8b277589 | 1276 | u8 active_fec_sig_mode; |
e70c752f | 1277 | u16 fec_cfg; |
8b277589 MC |
1278 | #define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED |
1279 | #define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED | |
e70c752f | 1280 | #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED |
8b277589 MC |
1281 | #define BNXT_FEC_ENC_BASE_R_CAP \ |
1282 | PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED | |
e70c752f | 1283 | #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED |
8b277589 MC |
1284 | #define BNXT_FEC_ENC_RS_CAP \ |
1285 | PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED | |
1286 | #define BNXT_FEC_ENC_LLRS_CAP \ | |
1287 | (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \ | |
1288 | PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED) | |
1289 | #define BNXT_FEC_ENC_RS \ | |
1290 | (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \ | |
1291 | PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \ | |
1292 | PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED) | |
1293 | #define BNXT_FEC_ENC_LLRS \ | |
1294 | (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \ | |
1295 | PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED) | |
c0c050c5 MC |
1296 | |
1297 | /* copy of requested setting from ethtool cmd */ | |
1298 | u8 autoneg; | |
1299 | #define BNXT_AUTONEG_SPEED 1 | |
1300 | #define BNXT_AUTONEG_FLOW_CTRL 2 | |
d058426e EP |
1301 | u8 req_signal_mode; |
1302 | #define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ | |
1303 | #define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 | |
ecdad2a6 | 1304 | #define BNXT_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1) |
c0c050c5 MC |
1305 | u8 req_duplex; |
1306 | u8 req_flow_ctrl; | |
1307 | u16 req_link_speed; | |
68515a18 | 1308 | u16 advertising; /* user adv setting */ |
d058426e | 1309 | u16 advertising_pam4; |
c0c050c5 | 1310 | bool force_link_chng; |
4bb13abf | 1311 | |
a1ef4a79 MC |
1312 | bool phy_retry; |
1313 | unsigned long phy_retry_expires; | |
1314 | ||
c0c050c5 MC |
1315 | /* a copy of phy_qcfg output used to report link |
1316 | * info to VF | |
1317 | */ | |
1318 | struct hwrm_port_phy_qcfg_output phy_qcfg_resp; | |
1319 | }; | |
1320 | ||
ccd6a9dc MC |
1321 | #define BNXT_FEC_RS544_ON \ |
1322 | (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \ | |
1323 | PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE) | |
1324 | ||
1325 | #define BNXT_FEC_RS544_OFF \ | |
1326 | (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \ | |
1327 | PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE) | |
1328 | ||
1329 | #define BNXT_FEC_RS272_ON \ | |
1330 | (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \ | |
1331 | PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE) | |
1332 | ||
1333 | #define BNXT_FEC_RS272_OFF \ | |
1334 | (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \ | |
1335 | PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE) | |
1336 | ||
1337 | #define BNXT_PAM4_SUPPORTED(link_info) \ | |
1338 | ((link_info)->support_pam4_speeds) | |
1339 | ||
1340 | #define BNXT_FEC_RS_ON(link_info) \ | |
1341 | (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \ | |
1342 | PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \ | |
1343 | (BNXT_PAM4_SUPPORTED(link_info) ? \ | |
1344 | (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0)) | |
1345 | ||
1346 | #define BNXT_FEC_LLRS_ON \ | |
1347 | (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \ | |
1348 | PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \ | |
1349 | BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF) | |
1350 | ||
1351 | #define BNXT_FEC_RS_OFF(link_info) \ | |
1352 | (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \ | |
1353 | (BNXT_PAM4_SUPPORTED(link_info) ? \ | |
1354 | (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0)) | |
1355 | ||
1356 | #define BNXT_FEC_BASE_R_ON(link_info) \ | |
1357 | (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \ | |
1358 | BNXT_FEC_RS_OFF(link_info)) | |
1359 | ||
1360 | #define BNXT_FEC_ALL_OFF(link_info) \ | |
1361 | (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \ | |
1362 | BNXT_FEC_RS_OFF(link_info)) | |
1363 | ||
c0c050c5 MC |
1364 | #define BNXT_MAX_QUEUE 8 |
1365 | ||
1366 | struct bnxt_queue_info { | |
1367 | u8 queue_id; | |
1368 | u8 queue_profile; | |
1369 | }; | |
1370 | ||
5ad2cbee MC |
1371 | #define BNXT_MAX_LED 4 |
1372 | ||
1373 | struct bnxt_led_info { | |
1374 | u8 led_id; | |
1375 | u8 led_type; | |
1376 | u8 led_group_id; | |
1377 | u8 unused; | |
1378 | __le16 led_state_caps; | |
1379 | #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ | |
1380 | cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED)) | |
1381 | ||
1382 | __le16 led_color_caps; | |
1383 | }; | |
1384 | ||
eb513658 MC |
1385 | #define BNXT_MAX_TEST 8 |
1386 | ||
1387 | struct bnxt_test_info { | |
1388 | u8 offline_mask; | |
1389 | u16 timeout; | |
1390 | char string[BNXT_MAX_TEST][ETH_GSTRING_LEN]; | |
1391 | }; | |
1392 | ||
b5d600b0 VV |
1393 | #define CHIMP_REG_VIEW_ADDR \ |
1394 | ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000) | |
1395 | ||
2e9ee398 VD |
1396 | #define BNXT_GRCPF_REG_CHIMP_COMM 0x0 |
1397 | #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 | |
1398 | #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 | |
1399 | #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 | |
1400 | #define BNXT_CAG_REG_BASE 0x300000 | |
11809490 | 1401 | |
d1cbd165 MC |
1402 | #define BNXT_GRC_REG_STATUS_P5 0x520 |
1403 | ||
760b6d33 VD |
1404 | #define BNXT_GRCPF_REG_KONG_COMM 0xA00 |
1405 | #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00 | |
1406 | ||
d1cbd165 MC |
1407 | #define BNXT_GRC_REG_CHIP_NUM 0x48 |
1408 | #define BNXT_GRC_REG_BASE 0x260000 | |
1409 | ||
ae5c42f0 MC |
1410 | #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c |
1411 | #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810 | |
1412 | ||
9ffbd677 MC |
1413 | #define BNXT_GRC_BASE_MASK 0xfffff000 |
1414 | #define BNXT_GRC_OFFSET_MASK 0x00000ffc | |
1415 | ||
5a84acbe SP |
1416 | struct bnxt_tc_flow_stats { |
1417 | u64 packets; | |
1418 | u64 bytes; | |
1419 | }; | |
1420 | ||
627c89d0 SB |
1421 | #ifdef CONFIG_BNXT_FLOWER_OFFLOAD |
1422 | struct bnxt_flower_indr_block_cb_priv { | |
1423 | struct net_device *tunnel_netdev; | |
1424 | struct bnxt *bp; | |
1425 | struct list_head list; | |
1426 | }; | |
1427 | #endif | |
1428 | ||
2ae7408f SP |
1429 | struct bnxt_tc_info { |
1430 | bool enabled; | |
1431 | ||
1432 | /* hash table to store TC offloaded flows */ | |
1433 | struct rhashtable flow_table; | |
1434 | struct rhashtable_params flow_ht_params; | |
1435 | ||
1436 | /* hash table to store L2 keys of TC flows */ | |
1437 | struct rhashtable l2_table; | |
1438 | struct rhashtable_params l2_ht_params; | |
8c95f773 SP |
1439 | /* hash table to store L2 keys for TC tunnel decap */ |
1440 | struct rhashtable decap_l2_table; | |
1441 | struct rhashtable_params decap_l2_ht_params; | |
1442 | /* hash table to store tunnel decap entries */ | |
1443 | struct rhashtable decap_table; | |
1444 | struct rhashtable_params decap_ht_params; | |
1445 | /* hash table to store tunnel encap entries */ | |
1446 | struct rhashtable encap_table; | |
1447 | struct rhashtable_params encap_ht_params; | |
2ae7408f SP |
1448 | |
1449 | /* lock to atomically add/del an l2 node when a flow is | |
1450 | * added or deleted. | |
1451 | */ | |
1452 | struct mutex lock; | |
1453 | ||
5a84acbe SP |
1454 | /* Fields used for batching stats query */ |
1455 | struct rhashtable_iter iter; | |
1456 | #define BNXT_FLOW_STATS_BATCH_MAX 10 | |
1457 | struct bnxt_tc_stats_batch { | |
1458 | void *flow_node; | |
1459 | struct bnxt_tc_flow_stats hw_stats; | |
1460 | } stats_batch[BNXT_FLOW_STATS_BATCH_MAX]; | |
1461 | ||
2ae7408f SP |
1462 | /* Stat counter mask (width) */ |
1463 | u64 bytes_mask; | |
1464 | u64 packets_mask; | |
1465 | }; | |
1466 | ||
4ab0c6a8 SP |
1467 | struct bnxt_vf_rep_stats { |
1468 | u64 packets; | |
1469 | u64 bytes; | |
1470 | u64 dropped; | |
1471 | }; | |
1472 | ||
1473 | struct bnxt_vf_rep { | |
1474 | struct bnxt *bp; | |
1475 | struct net_device *dev; | |
ee5c7fb3 | 1476 | struct metadata_dst *dst; |
4ab0c6a8 SP |
1477 | u16 vf_idx; |
1478 | u16 tx_cfa_action; | |
1479 | u16 rx_cfa_code; | |
1480 | ||
1481 | struct bnxt_vf_rep_stats rx_stats; | |
1482 | struct bnxt_vf_rep_stats tx_stats; | |
1483 | }; | |
1484 | ||
66cca20a MC |
1485 | #define PTU_PTE_VALID 0x1UL |
1486 | #define PTU_PTE_LAST 0x2UL | |
1487 | #define PTU_PTE_NEXT_TO_LAST 0x4UL | |
1488 | ||
98f04cf0 | 1489 | #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) |
08fe9d18 | 1490 | #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) |
98f04cf0 MC |
1491 | |
1492 | struct bnxt_ctx_pg_info { | |
1493 | u32 entries; | |
08fe9d18 | 1494 | u32 nr_pages; |
98f04cf0 MC |
1495 | void *ctx_pg_arr[MAX_CTX_PAGES]; |
1496 | dma_addr_t ctx_dma_arr[MAX_CTX_PAGES]; | |
1497 | struct bnxt_ring_mem_info ring_mem; | |
08fe9d18 | 1498 | struct bnxt_ctx_pg_info **ctx_pg_tbl; |
98f04cf0 MC |
1499 | }; |
1500 | ||
a029a2fe MC |
1501 | #define BNXT_MAX_TQM_SP_RINGS 1 |
1502 | #define BNXT_MAX_TQM_FP_RINGS 8 | |
1503 | #define BNXT_MAX_TQM_RINGS \ | |
1504 | (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) | |
1505 | ||
16db6323 MC |
1506 | #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 |
1507 | ||
702279d2 MC |
1508 | #define BNXT_SET_CTX_PAGE_ATTR(attr) \ |
1509 | do { \ | |
1510 | if (BNXT_PAGE_SIZE == 0x2000) \ | |
1511 | attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \ | |
1512 | else if (BNXT_PAGE_SIZE == 0x10000) \ | |
1513 | attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \ | |
1514 | else \ | |
1515 | attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \ | |
1516 | } while (0) | |
1517 | ||
98f04cf0 MC |
1518 | struct bnxt_ctx_mem_info { |
1519 | u32 qp_max_entries; | |
1520 | u16 qp_min_qp1_entries; | |
1521 | u16 qp_max_l2_entries; | |
1522 | u16 qp_entry_size; | |
1523 | u16 srq_max_l2_entries; | |
1524 | u32 srq_max_entries; | |
1525 | u16 srq_entry_size; | |
1526 | u16 cq_max_l2_entries; | |
1527 | u32 cq_max_entries; | |
1528 | u16 cq_entry_size; | |
1529 | u16 vnic_max_vnic_entries; | |
1530 | u16 vnic_max_ring_table_entries; | |
1531 | u16 vnic_entry_size; | |
1532 | u32 stat_max_entries; | |
1533 | u16 stat_entry_size; | |
1534 | u16 tqm_entry_size; | |
1535 | u32 tqm_min_entries_per_ring; | |
1536 | u32 tqm_max_entries_per_ring; | |
1537 | u32 mrav_max_entries; | |
1538 | u16 mrav_entry_size; | |
1539 | u16 tim_entry_size; | |
1540 | u32 tim_max_entries; | |
53579e37 | 1541 | u16 mrav_num_entries_units; |
98f04cf0 | 1542 | u8 tqm_entries_multiple; |
ac3158cb | 1543 | u8 tqm_fp_rings_count; |
98f04cf0 MC |
1544 | |
1545 | u32 flags; | |
1546 | #define BNXT_CTX_FLAG_INITED 0x01 | |
1547 | ||
1548 | struct bnxt_ctx_pg_info qp_mem; | |
1549 | struct bnxt_ctx_pg_info srq_mem; | |
1550 | struct bnxt_ctx_pg_info cq_mem; | |
1551 | struct bnxt_ctx_pg_info vnic_mem; | |
1552 | struct bnxt_ctx_pg_info stat_mem; | |
cf6daed0 MC |
1553 | struct bnxt_ctx_pg_info mrav_mem; |
1554 | struct bnxt_ctx_pg_info tim_mem; | |
a029a2fe | 1555 | struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS]; |
e9696ff3 MC |
1556 | |
1557 | #define BNXT_CTX_MEM_INIT_QP 0 | |
1558 | #define BNXT_CTX_MEM_INIT_SRQ 1 | |
1559 | #define BNXT_CTX_MEM_INIT_CQ 2 | |
1560 | #define BNXT_CTX_MEM_INIT_VNIC 3 | |
1561 | #define BNXT_CTX_MEM_INIT_STAT 4 | |
1562 | #define BNXT_CTX_MEM_INIT_MRAV 5 | |
1563 | #define BNXT_CTX_MEM_INIT_MAX 6 | |
1564 | struct bnxt_mem_init mem_init[BNXT_CTX_MEM_INIT_MAX]; | |
98f04cf0 MC |
1565 | }; |
1566 | ||
8cc95ceb EP |
1567 | enum bnxt_health_severity { |
1568 | SEVERITY_NORMAL = 0, | |
1569 | SEVERITY_WARNING, | |
1570 | SEVERITY_RECOVERABLE, | |
1571 | SEVERITY_FATAL, | |
1572 | }; | |
1573 | ||
1574 | enum bnxt_health_remedy { | |
1575 | REMEDY_DEVLINK_RECOVER, | |
1576 | REMEDY_POWER_CYCLE_DEVICE, | |
1577 | REMEDY_POWER_CYCLE_HOST, | |
1578 | REMEDY_FW_UPDATE, | |
1579 | REMEDY_HW_REPLACE, | |
1580 | }; | |
1581 | ||
07f83d72 MC |
1582 | struct bnxt_fw_health { |
1583 | u32 flags; | |
1584 | u32 polling_dsecs; | |
1585 | u32 master_func_wait_dsecs; | |
1586 | u32 normal_func_wait_dsecs; | |
1587 | u32 post_reset_wait_dsecs; | |
1588 | u32 post_reset_max_wait_dsecs; | |
1589 | u32 regs[4]; | |
1590 | u32 mapped_regs[4]; | |
1591 | #define BNXT_FW_HEALTH_REG 0 | |
1592 | #define BNXT_FW_HEARTBEAT_REG 1 | |
1593 | #define BNXT_FW_RESET_CNT_REG 2 | |
1594 | #define BNXT_FW_RESET_INPROG_REG 3 | |
1595 | u32 fw_reset_inprog_reg_mask; | |
1596 | u32 last_fw_heartbeat; | |
1597 | u32 last_fw_reset_cnt; | |
1598 | u8 enabled:1; | |
1596847d | 1599 | u8 primary:1; |
ba02629f | 1600 | u8 status_reliable:1; |
8cc95ceb | 1601 | u8 resets_reliable:1; |
07f83d72 MC |
1602 | u8 tmr_multiplier; |
1603 | u8 tmr_counter; | |
1604 | u8 fw_reset_seq_cnt; | |
1605 | u32 fw_reset_seq_regs[16]; | |
1606 | u32 fw_reset_seq_vals[16]; | |
1607 | u32 fw_reset_seq_delay_msec[16]; | |
df97b34d MC |
1608 | u32 echo_req_data1; |
1609 | u32 echo_req_data2; | |
6763c779 | 1610 | struct devlink_health_reporter *fw_reporter; |
8cc95ceb EP |
1611 | /* Protects severity and remedy */ |
1612 | struct mutex lock; | |
1613 | enum bnxt_health_severity severity; | |
1614 | enum bnxt_health_remedy remedy; | |
1615 | u32 arrests; | |
1616 | u32 discoveries; | |
1617 | u32 survivals; | |
1618 | u32 fatalities; | |
1619 | u32 diagnoses; | |
657a33c8 VV |
1620 | }; |
1621 | ||
07f83d72 MC |
1622 | #define BNXT_FW_HEALTH_REG_TYPE_MASK 3 |
1623 | #define BNXT_FW_HEALTH_REG_TYPE_CFG 0 | |
1624 | #define BNXT_FW_HEALTH_REG_TYPE_GRC 1 | |
1625 | #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2 | |
1626 | #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3 | |
1627 | ||
1628 | #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK) | |
1629 | #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK) | |
9ffbd677 MC |
1630 | |
1631 | #define BNXT_FW_HEALTH_WIN_BASE 0x3000 | |
1632 | #define BNXT_FW_HEALTH_WIN_MAP_OFF 8 | |
07f83d72 | 1633 | |
ba02629f EP |
1634 | #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \ |
1635 | ((reg) & BNXT_GRC_OFFSET_MASK)) | |
1636 | ||
fe1b8535 | 1637 | #define BNXT_FW_STATUS_HEALTH_MSK 0xffff |
6763c779 | 1638 | #define BNXT_FW_STATUS_HEALTHY 0x8000 |
4037eb71 | 1639 | #define BNXT_FW_STATUS_SHUTDOWN 0x100000 |
861aae78 | 1640 | #define BNXT_FW_STATUS_RECOVERING 0x400000 |
fe1b8535 MC |
1641 | |
1642 | #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\ | |
1643 | BNXT_FW_STATUS_HEALTHY) | |
1644 | ||
1645 | #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \ | |
1646 | BNXT_FW_STATUS_HEALTHY) | |
1647 | ||
1648 | #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \ | |
1649 | BNXT_FW_STATUS_HEALTHY) | |
d1cbd165 | 1650 | |
861aae78 MC |
1651 | #define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \ |
1652 | ((sts) & BNXT_FW_STATUS_RECOVERING)) | |
1653 | ||
d1cbd165 | 1654 | #define BNXT_FW_RETRY 5 |
5d06eb5c | 1655 | #define BNXT_FW_IF_RETRY 10 |
0cf736a1 | 1656 | #define BNXT_FW_SLOT_RESET_RETRY 4 |
6763c779 | 1657 | |
d80d88b0 AK |
1658 | struct bnxt_aux_priv { |
1659 | struct auxiliary_device aux_dev; | |
1660 | struct bnxt_en_dev *edev; | |
1661 | int id; | |
1662 | }; | |
1663 | ||
c7dd4a5b EP |
1664 | enum board_idx { |
1665 | BCM57301, | |
1666 | BCM57302, | |
1667 | BCM57304, | |
1668 | BCM57417_NPAR, | |
1669 | BCM58700, | |
1670 | BCM57311, | |
1671 | BCM57312, | |
1672 | BCM57402, | |
1673 | BCM57404, | |
1674 | BCM57406, | |
1675 | BCM57402_NPAR, | |
1676 | BCM57407, | |
1677 | BCM57412, | |
1678 | BCM57414, | |
1679 | BCM57416, | |
1680 | BCM57417, | |
1681 | BCM57412_NPAR, | |
1682 | BCM57314, | |
1683 | BCM57417_SFP, | |
1684 | BCM57416_SFP, | |
1685 | BCM57404_NPAR, | |
1686 | BCM57406_NPAR, | |
1687 | BCM57407_SFP, | |
1688 | BCM57407_NPAR, | |
1689 | BCM57414_NPAR, | |
1690 | BCM57416_NPAR, | |
1691 | BCM57452, | |
1692 | BCM57454, | |
1693 | BCM5745x_NPAR, | |
1694 | BCM57508, | |
1695 | BCM57504, | |
1696 | BCM57502, | |
1697 | BCM57508_NPAR, | |
1698 | BCM57504_NPAR, | |
1699 | BCM57502_NPAR, | |
1700 | BCM58802, | |
1701 | BCM58804, | |
1702 | BCM58808, | |
1703 | NETXTREME_E_VF, | |
1704 | NETXTREME_C_VF, | |
1705 | NETXTREME_S_VF, | |
1706 | NETXTREME_C_VF_HV, | |
1707 | NETXTREME_E_VF_HV, | |
1708 | NETXTREME_E_P5_VF, | |
1709 | NETXTREME_E_P5_VF_HV, | |
1710 | }; | |
1711 | ||
c0c050c5 MC |
1712 | struct bnxt { |
1713 | void __iomem *bar0; | |
1714 | void __iomem *bar1; | |
1715 | void __iomem *bar2; | |
1716 | ||
1717 | u32 reg_base; | |
659c805c MC |
1718 | u16 chip_num; |
1719 | #define CHIP_NUM_57301 0x16c8 | |
1720 | #define CHIP_NUM_57302 0x16c9 | |
1721 | #define CHIP_NUM_57304 0x16ca | |
3e8060fa | 1722 | #define CHIP_NUM_58700 0x16cd |
659c805c MC |
1723 | #define CHIP_NUM_57402 0x16d0 |
1724 | #define CHIP_NUM_57404 0x16d1 | |
1725 | #define CHIP_NUM_57406 0x16d2 | |
3284f9e1 | 1726 | #define CHIP_NUM_57407 0x16d5 |
659c805c MC |
1727 | |
1728 | #define CHIP_NUM_57311 0x16ce | |
1729 | #define CHIP_NUM_57312 0x16cf | |
1730 | #define CHIP_NUM_57314 0x16df | |
3284f9e1 | 1731 | #define CHIP_NUM_57317 0x16e0 |
659c805c MC |
1732 | #define CHIP_NUM_57412 0x16d6 |
1733 | #define CHIP_NUM_57414 0x16d7 | |
1734 | #define CHIP_NUM_57416 0x16d8 | |
1735 | #define CHIP_NUM_57417 0x16d9 | |
3284f9e1 MC |
1736 | #define CHIP_NUM_57412L 0x16da |
1737 | #define CHIP_NUM_57414L 0x16db | |
1738 | ||
1739 | #define CHIP_NUM_5745X 0xd730 | |
fb4cd81e MC |
1740 | #define CHIP_NUM_57452 0xc452 |
1741 | #define CHIP_NUM_57454 0xc454 | |
659c805c | 1742 | |
1dc88b97 MC |
1743 | #define CHIP_NUM_57508 0x1750 |
1744 | #define CHIP_NUM_57504 0x1751 | |
1745 | #define CHIP_NUM_57502 0x1752 | |
e38287b7 | 1746 | |
4a58139b | 1747 | #define CHIP_NUM_58802 0xd802 |
8ed693b7 | 1748 | #define CHIP_NUM_58804 0xd804 |
4a58139b RJ |
1749 | #define CHIP_NUM_58808 0xd808 |
1750 | ||
5313845f MC |
1751 | u8 chip_rev; |
1752 | ||
9d6b648c MC |
1753 | #define CHIP_NUM_58818 0xd818 |
1754 | ||
659c805c MC |
1755 | #define BNXT_CHIP_NUM_5730X(chip_num) \ |
1756 | ((chip_num) >= CHIP_NUM_57301 && \ | |
1757 | (chip_num) <= CHIP_NUM_57304) | |
1758 | ||
1759 | #define BNXT_CHIP_NUM_5740X(chip_num) \ | |
3284f9e1 MC |
1760 | (((chip_num) >= CHIP_NUM_57402 && \ |
1761 | (chip_num) <= CHIP_NUM_57406) || \ | |
1762 | (chip_num) == CHIP_NUM_57407) | |
659c805c MC |
1763 | |
1764 | #define BNXT_CHIP_NUM_5731X(chip_num) \ | |
1765 | ((chip_num) == CHIP_NUM_57311 || \ | |
1766 | (chip_num) == CHIP_NUM_57312 || \ | |
3284f9e1 MC |
1767 | (chip_num) == CHIP_NUM_57314 || \ |
1768 | (chip_num) == CHIP_NUM_57317) | |
659c805c MC |
1769 | |
1770 | #define BNXT_CHIP_NUM_5741X(chip_num) \ | |
1771 | ((chip_num) >= CHIP_NUM_57412 && \ | |
3284f9e1 MC |
1772 | (chip_num) <= CHIP_NUM_57414L) |
1773 | ||
1774 | #define BNXT_CHIP_NUM_58700(chip_num) \ | |
1775 | ((chip_num) == CHIP_NUM_58700) | |
1776 | ||
1777 | #define BNXT_CHIP_NUM_5745X(chip_num) \ | |
fb4cd81e MC |
1778 | ((chip_num) == CHIP_NUM_5745X || \ |
1779 | (chip_num) == CHIP_NUM_57452 || \ | |
1780 | (chip_num) == CHIP_NUM_57454) | |
1781 | ||
659c805c MC |
1782 | |
1783 | #define BNXT_CHIP_NUM_57X0X(chip_num) \ | |
1784 | (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) | |
1785 | ||
1786 | #define BNXT_CHIP_NUM_57X1X(chip_num) \ | |
1787 | (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) | |
c0c050c5 | 1788 | |
4a58139b RJ |
1789 | #define BNXT_CHIP_NUM_588XX(chip_num) \ |
1790 | ((chip_num) == CHIP_NUM_58802 || \ | |
8ed693b7 | 1791 | (chip_num) == CHIP_NUM_58804 || \ |
4a58139b RJ |
1792 | (chip_num) == CHIP_NUM_58808) |
1793 | ||
a0d0fd70 VV |
1794 | #define BNXT_VPD_FLD_LEN 32 |
1795 | char board_partno[BNXT_VPD_FLD_LEN]; | |
1796 | char board_serialno[BNXT_VPD_FLD_LEN]; | |
1797 | ||
c0c050c5 MC |
1798 | struct net_device *dev; |
1799 | struct pci_dev *pdev; | |
1800 | ||
1801 | atomic_t intr_sem; | |
1802 | ||
1803 | u32 flags; | |
e38287b7 | 1804 | #define BNXT_FLAG_CHIP_P5 0x1 |
c0c050c5 MC |
1805 | #define BNXT_FLAG_VF 0x2 |
1806 | #define BNXT_FLAG_LRO 0x4 | |
d1611c3a | 1807 | #ifdef CONFIG_INET |
c0c050c5 | 1808 | #define BNXT_FLAG_GRO 0x8 |
d1611c3a MC |
1809 | #else |
1810 | /* Cannot support hardware GRO if CONFIG_INET is not set */ | |
1811 | #define BNXT_FLAG_GRO 0x0 | |
1812 | #endif | |
c0c050c5 MC |
1813 | #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) |
1814 | #define BNXT_FLAG_JUMBO 0x10 | |
1815 | #define BNXT_FLAG_STRIP_VLAN 0x20 | |
1816 | #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ | |
1817 | BNXT_FLAG_LRO) | |
1818 | #define BNXT_FLAG_USING_MSIX 0x40 | |
1819 | #define BNXT_FLAG_MSIX_CAP 0x80 | |
1820 | #define BNXT_FLAG_RFS 0x100 | |
6e6c5a57 | 1821 | #define BNXT_FLAG_SHARED_RINGS 0x200 |
3bdf56c4 | 1822 | #define BNXT_FLAG_PORT_STATS 0x400 |
87da7f79 | 1823 | #define BNXT_FLAG_UDP_RSS_CAP 0x800 |
8fdefd63 | 1824 | #define BNXT_FLAG_NEW_RSS_CAP 0x2000 |
c1ef146a | 1825 | #define BNXT_FLAG_WOL_CAP 0x4000 |
e4060d30 MC |
1826 | #define BNXT_FLAG_ROCEV1_CAP 0x8000 |
1827 | #define BNXT_FLAG_ROCEV2_CAP 0x10000 | |
1828 | #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \ | |
1829 | BNXT_FLAG_ROCEV2_CAP) | |
bdbd1eb5 | 1830 | #define BNXT_FLAG_NO_AGG_RINGS 0x20000 |
c61fb99c | 1831 | #define BNXT_FLAG_RX_PAGE_MODE 0x40000 |
9d6b648c | 1832 | #define BNXT_FLAG_CHIP_SR2 0x80000 |
9e54e322 | 1833 | #define BNXT_FLAG_MULTI_HOST 0x100000 |
d061b241 | 1834 | #define BNXT_FLAG_DSN_VALID 0x200000 |
434c975a | 1835 | #define BNXT_FLAG_DOUBLE_DB 0x400000 |
3e8060fa | 1836 | #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 |
6a8788f2 | 1837 | #define BNXT_FLAG_DIM 0x2000000 |
abe93ad2 | 1838 | #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000 |
00db3cba | 1839 | #define BNXT_FLAG_PORT_STATS_EXT 0x10000000 |
6e6c5a57 | 1840 | |
c0c050c5 MC |
1841 | #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ |
1842 | BNXT_FLAG_RFS | \ | |
1843 | BNXT_FLAG_STRIP_VLAN) | |
1844 | ||
1845 | #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) | |
1846 | #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) | |
567b2abe | 1847 | #define BNXT_NPAR(bp) ((bp)->port_partition_type) |
9e54e322 DK |
1848 | #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) |
1849 | #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) | |
b0d28207 MC |
1850 | #define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \ |
1851 | ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG)) | |
3128e811 | 1852 | #define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \ |
b0d28207 | 1853 | BNXT_SH_PORT_CFG_OK(bp)) && \ |
3128e811 | 1854 | (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED) |
3e8060fa | 1855 | #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) |
c61fb99c | 1856 | #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE) |
e38287b7 | 1857 | #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \ |
7c380918 MC |
1858 | (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \ |
1859 | (bp)->max_tpa_v2) && !is_kdump_kernel()) | |
32861236 | 1860 | #define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO) |
c0c050c5 | 1861 | |
9d6b648c MC |
1862 | #define BNXT_CHIP_SR2(bp) \ |
1863 | ((bp)->chip_num == CHIP_NUM_58818) | |
1864 | ||
1865 | #define BNXT_CHIP_P5_THOR(bp) \ | |
1dc88b97 MC |
1866 | ((bp)->chip_num == CHIP_NUM_57508 || \ |
1867 | (bp)->chip_num == CHIP_NUM_57504 || \ | |
1868 | (bp)->chip_num == CHIP_NUM_57502) | |
e38287b7 | 1869 | |
9d6b648c MC |
1870 | /* Chip class phase 5 */ |
1871 | #define BNXT_CHIP_P5(bp) \ | |
1872 | (BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp)) | |
1873 | ||
e38287b7 MC |
1874 | /* Chip class phase 4.x */ |
1875 | #define BNXT_CHIP_P4(bp) \ | |
3284f9e1 MC |
1876 | (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \ |
1877 | BNXT_CHIP_NUM_5745X((bp)->chip_num) || \ | |
4a58139b | 1878 | BNXT_CHIP_NUM_588XX((bp)->chip_num) || \ |
3284f9e1 MC |
1879 | (BNXT_CHIP_NUM_58700((bp)->chip_num) && \ |
1880 | !BNXT_CHIP_TYPE_NITRO_A0(bp))) | |
1881 | ||
e38287b7 MC |
1882 | #define BNXT_CHIP_P4_PLUS(bp) \ |
1883 | (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp)) | |
1884 | ||
d80d88b0 | 1885 | struct bnxt_aux_priv *aux_priv; |
a588e458 | 1886 | struct bnxt_en_dev *edev; |
a588e458 | 1887 | |
c0c050c5 MC |
1888 | struct bnxt_napi **bnapi; |
1889 | ||
b6ab4b01 MC |
1890 | struct bnxt_rx_ring_info *rx_ring; |
1891 | struct bnxt_tx_ring_info *tx_ring; | |
a960dec9 | 1892 | u16 *tx_ring_map; |
b6ab4b01 | 1893 | |
309369c9 MC |
1894 | struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, |
1895 | struct sk_buff *); | |
1896 | ||
6bb19474 MC |
1897 | struct sk_buff * (*rx_skb_func)(struct bnxt *, |
1898 | struct bnxt_rx_ring_info *, | |
1899 | u16, void *, u8 *, dma_addr_t, | |
1900 | unsigned int); | |
1901 | ||
79632e9b MC |
1902 | u16 max_tpa_v2; |
1903 | u16 max_tpa; | |
c0c050c5 MC |
1904 | u32 rx_buf_size; |
1905 | u32 rx_buf_use_size; /* useable size */ | |
b3dba77c MC |
1906 | u16 rx_offset; |
1907 | u16 rx_dma_offset; | |
745fc05c | 1908 | enum dma_data_direction rx_dir; |
c0c050c5 MC |
1909 | u32 rx_ring_size; |
1910 | u32 rx_agg_ring_size; | |
1911 | u32 rx_copy_thresh; | |
1912 | u32 rx_ring_mask; | |
1913 | u32 rx_agg_ring_mask; | |
1914 | int rx_nr_pages; | |
1915 | int rx_agg_nr_pages; | |
1916 | int rx_nr_rings; | |
1917 | int rsscos_nr_ctxs; | |
1918 | ||
1919 | u32 tx_ring_size; | |
1920 | u32 tx_ring_mask; | |
1921 | int tx_nr_pages; | |
1922 | int tx_nr_rings; | |
1923 | int tx_nr_rings_per_tc; | |
5f449249 | 1924 | int tx_nr_rings_xdp; |
c0c050c5 MC |
1925 | |
1926 | int tx_wake_thresh; | |
1927 | int tx_push_thresh; | |
1928 | int tx_push_size; | |
1929 | ||
1930 | u32 cp_ring_size; | |
1931 | u32 cp_ring_mask; | |
1932 | u32 cp_bit; | |
1933 | int cp_nr_pages; | |
1934 | int cp_nr_rings; | |
1935 | ||
b81a90d3 | 1936 | /* grp_info indexed by completion ring index */ |
c0c050c5 MC |
1937 | struct bnxt_ring_grp_info *grp_info; |
1938 | struct bnxt_vnic_info *vnic_info; | |
1939 | int nr_vnics; | |
1667cbf6 MC |
1940 | u16 *rss_indir_tbl; |
1941 | u16 rss_indir_tbl_entries; | |
87da7f79 | 1942 | u32 rss_hash_cfg; |
98a4322b | 1943 | u32 rss_hash_delta; |
c0c050c5 | 1944 | |
7eb9bb3a | 1945 | u16 max_mtu; |
c0c050c5 | 1946 | u8 max_tc; |
87c374de | 1947 | u8 max_lltc; /* lossless TCs */ |
c0c050c5 | 1948 | struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; |
2e8ef77e | 1949 | u8 tc_to_qidx[BNXT_MAX_QUEUE]; |
98f04cf0 MC |
1950 | u8 q_ids[BNXT_MAX_QUEUE]; |
1951 | u8 max_q; | |
c0c050c5 MC |
1952 | |
1953 | unsigned int current_interval; | |
3bdf56c4 | 1954 | #define BNXT_TIMER_INTERVAL HZ |
c0c050c5 MC |
1955 | |
1956 | struct timer_list timer; | |
1957 | ||
caefe526 MC |
1958 | unsigned long state; |
1959 | #define BNXT_STATE_OPEN 0 | |
4cebdcec | 1960 | #define BNXT_STATE_IN_SP_TASK 1 |
f9b76ebd | 1961 | #define BNXT_STATE_READ_STATS 2 |
ec5d31e3 | 1962 | #define BNXT_STATE_FW_RESET_DET 3 |
3bc7d4a3 | 1963 | #define BNXT_STATE_IN_FW_RESET 4 |
ec5d31e3 | 1964 | #define BNXT_STATE_ABORT_ERR 5 |
b4fff207 | 1965 | #define BNXT_STATE_FW_FATAL_COND 6 |
bdb38602 | 1966 | #define BNXT_STATE_DRV_REGISTERED 7 |
f75d9a0a | 1967 | #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8 |
e340a5c4 | 1968 | #define BNXT_STATE_NAPI_DISABLED 9 |
662c9b22 | 1969 | #define BNXT_STATE_L2_FILTER_RETRY 10 |
8f6c5e4d | 1970 | #define BNXT_STATE_FW_ACTIVATE 11 |
aadb0b1a EP |
1971 | #define BNXT_STATE_RECOVER 12 |
1972 | #define BNXT_STATE_FW_NON_FATAL_COND 13 | |
8f6c5e4d | 1973 | #define BNXT_STATE_FW_ACTIVATE_RESET 14 |
cfcab3b3 | 1974 | #define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */ |
c0c050c5 | 1975 | |
b340dc68 VV |
1976 | #define BNXT_NO_FW_ACCESS(bp) \ |
1977 | (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \ | |
1978 | pci_channel_offline((bp)->pdev)) | |
1979 | ||
c0c050c5 | 1980 | struct bnxt_irq *irq_tbl; |
7809592d | 1981 | int total_irqs; |
c0c050c5 MC |
1982 | u8 mac_addr[ETH_ALEN]; |
1983 | ||
7df4ae9f MC |
1984 | #ifdef CONFIG_BNXT_DCB |
1985 | struct ieee_pfc *ieee_pfc; | |
1986 | struct ieee_ets *ieee_ets; | |
1987 | u8 dcbx_cap; | |
1988 | u8 default_pri; | |
afdc8a84 | 1989 | u8 max_dscp_value; |
7df4ae9f MC |
1990 | #endif /* CONFIG_BNXT_DCB */ |
1991 | ||
c0c050c5 MC |
1992 | u32 msg_enable; |
1993 | ||
a3a4e300 PC |
1994 | u64 fw_cap; |
1995 | #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0) | |
1996 | #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1) | |
1997 | #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2) | |
1998 | #define BNXT_FW_CAP_NEW_RM BIT_ULL(3) | |
1999 | #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4) | |
2000 | #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7) | |
2001 | #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10) | |
2002 | #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11) | |
2003 | #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13) | |
2004 | #define BNXT_FW_CAP_PKG_VER BIT_ULL(14) | |
2005 | #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15) | |
2006 | #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16) | |
2007 | #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17) | |
2008 | #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18) | |
2009 | #define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(19) | |
2010 | #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20) | |
2011 | #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21) | |
2012 | #define BNXT_FW_CAP_PTP_RTC BIT_ULL(22) | |
2013 | #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23) | |
2014 | #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24) | |
2015 | #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25) | |
2016 | #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26) | |
2017 | #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27) | |
2018 | #define BNXT_FW_CAP_PTP_PPS BIT_ULL(28) | |
2019 | #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29) | |
2020 | #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30) | |
2021 | #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31) | |
edc52873 | 2022 | #define BNXT_FW_CAP_PTP BIT_ULL(32) |
cd13244f | 2023 | #define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED BIT_ULL(33) |
e76d44fe | 2024 | #define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34) |
cbdbf0aa | 2025 | #define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35) |
80194db9 VV |
2026 | |
2027 | u32 fw_dbg_cap; | |
97381a18 MC |
2028 | |
2029 | #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM) | |
131db499 VF |
2030 | #define BNXT_PTP_USE_RTC(bp) (!BNXT_MH(bp) && \ |
2031 | ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC)) | |
11f15ed3 | 2032 | u32 hwrm_spec_code; |
c0c050c5 | 2033 | u16 hwrm_cmd_seq; |
760b6d33 | 2034 | u16 hwrm_cmd_kong_seq; |
f9ff5782 | 2035 | struct dma_pool *hwrm_dma_pool; |
68f684e2 | 2036 | struct hlist_head hwrm_pending_list; |
3bdf56c4 | 2037 | |
b8875ca3 | 2038 | struct rtnl_link_stats64 net_stats_prev; |
177a6cde MC |
2039 | struct bnxt_stats_mem port_stats; |
2040 | struct bnxt_stats_mem rx_port_stats_ext; | |
2041 | struct bnxt_stats_mem tx_port_stats_ext; | |
36e53349 MC |
2042 | u16 fw_rx_stats_ext_size; |
2043 | u16 fw_tx_stats_ext_size; | |
4e748506 | 2044 | u16 hw_ring_stats_size; |
a24ec322 | 2045 | u8 pri2cos_idx[8]; |
e37fed79 | 2046 | u8 pri2cos_valid; |
3bdf56c4 | 2047 | |
4c70dbe3 MC |
2048 | struct bnxt_total_ring_err_stats ring_err_stats_prev; |
2049 | ||
e6ef2699 | 2050 | u16 hwrm_max_req_len; |
1dfddc41 | 2051 | u16 hwrm_max_ext_req_len; |
bce9a0b7 EP |
2052 | unsigned int hwrm_cmd_timeout; |
2053 | unsigned int hwrm_cmd_max_timeout; | |
c0c050c5 MC |
2054 | struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ |
2055 | struct hwrm_ver_get_output ver_resp; | |
2056 | #define FW_VER_STR_LEN 32 | |
2057 | #define BC_HWRM_STR_LEN 21 | |
2058 | #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) | |
2059 | char fw_ver_str[FW_VER_STR_LEN]; | |
b7a444f0 | 2060 | char hwrm_ver_supp[FW_VER_STR_LEN]; |
4933f675 | 2061 | char nvm_cfg_ver[FW_VER_STR_LEN]; |
d0ad2ea2 MC |
2062 | u64 fw_ver_code; |
2063 | #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \ | |
2064 | ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv)) | |
fed7edd1 | 2065 | #define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48) |
cbdbf0aa | 2066 | #define BNXT_FW_BLD(bp) (((bp)->fw_ver_code >> 16) & 0xffff) |
d0ad2ea2 | 2067 | |
442a35a5 JK |
2068 | u16 vxlan_fw_dst_port_id; |
2069 | u16 nge_fw_dst_port_id; | |
1698d600 MC |
2070 | __be16 vxlan_port; |
2071 | __be16 nge_port; | |
567b2abe | 2072 | u8 port_partition_type; |
d5430d31 | 2073 | u8 port_count; |
32e8239c | 2074 | u16 br_mode; |
dfc9c94a | 2075 | |
74706afa | 2076 | struct bnxt_coal_cap coal_cap; |
18775aa8 MC |
2077 | struct bnxt_coal rx_coal; |
2078 | struct bnxt_coal tx_coal; | |
c0c050c5 | 2079 | |
51f30785 MC |
2080 | u32 stats_coal_ticks; |
2081 | #define BNXT_DEF_STATS_COAL_TICKS 1000000 | |
2082 | #define BNXT_MIN_STATS_COAL_TICKS 250000 | |
2083 | #define BNXT_MAX_STATS_COAL_TICKS 1000000 | |
2084 | ||
c0c050c5 MC |
2085 | struct work_struct sp_task; |
2086 | unsigned long sp_event; | |
2087 | #define BNXT_RX_MASK_SP_EVENT 0 | |
2088 | #define BNXT_RX_NTP_FLTR_SP_EVENT 1 | |
2089 | #define BNXT_LINK_CHNG_SP_EVENT 2 | |
c5d7774d | 2090 | #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 |
c5d7774d JH |
2091 | #define BNXT_RESET_TASK_SP_EVENT 6 |
2092 | #define BNXT_RST_RING_SP_EVENT 7 | |
19241368 | 2093 | #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 |
3bdf56c4 | 2094 | #define BNXT_PERIODIC_STATS_SP_EVENT 9 |
4bb13abf | 2095 | #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 |
fc0f1929 | 2096 | #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 |
286ef9d6 | 2097 | #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 |
5a84acbe | 2098 | #define BNXT_FLOW_STATS_SP_EVENT 15 |
a1ef4a79 | 2099 | #define BNXT_UPDATE_PHY_SP_EVENT 16 |
ffd77621 | 2100 | #define BNXT_RING_COAL_NOW_SP_EVENT 17 |
2151fe08 | 2101 | #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18 |
acfb50e4 | 2102 | #define BNXT_FW_EXCEPTION_SP_EVENT 19 |
b1613e78 | 2103 | #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21 |
55862094 | 2104 | #define BNXT_THERMAL_THRESHOLD_SP_EVENT 22 |
df97b34d | 2105 | #define BNXT_FW_ECHO_REQUEST_SP_EVENT 23 |
2151fe08 | 2106 | |
230d1f0d MC |
2107 | struct delayed_work fw_reset_task; |
2108 | int fw_reset_state; | |
2109 | #define BNXT_FW_RESET_STATE_POLL_VF 1 | |
2110 | #define BNXT_FW_RESET_STATE_RESET_FW 2 | |
2111 | #define BNXT_FW_RESET_STATE_ENABLE_DEV 3 | |
2112 | #define BNXT_FW_RESET_STATE_POLL_FW 4 | |
2113 | #define BNXT_FW_RESET_STATE_OPENING 5 | |
4037eb71 | 2114 | #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6 |
230d1f0d | 2115 | |
2151fe08 MC |
2116 | u16 fw_reset_min_dsecs; |
2117 | #define BNXT_DFLT_FW_RST_MIN_DSECS 20 | |
2118 | u16 fw_reset_max_dsecs; | |
2119 | #define BNXT_DFLT_FW_RST_MAX_DSECS 60 | |
2120 | unsigned long fw_reset_timestamp; | |
c0c050c5 | 2121 | |
07f83d72 MC |
2122 | struct bnxt_fw_health *fw_health; |
2123 | ||
6a4f2947 | 2124 | struct bnxt_hw_resc hw_resc; |
379a80a1 | 2125 | struct bnxt_pf_info pf; |
98f04cf0 | 2126 | struct bnxt_ctx_mem_info *ctx; |
c0c050c5 MC |
2127 | #ifdef CONFIG_BNXT_SRIOV |
2128 | int nr_vfs; | |
c0c050c5 MC |
2129 | struct bnxt_vf_info vf; |
2130 | wait_queue_head_t sriov_cfg_wait; | |
2131 | bool sriov_cfg; | |
2132 | #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) | |
2133 | #endif | |
2134 | ||
c6132f6f | 2135 | #if BITS_PER_LONG == 32 |
697197e5 MC |
2136 | /* ensure atomic 64-bit doorbell writes on 32-bit systems. */ |
2137 | spinlock_t db_lock; | |
2138 | #endif | |
8ae24738 | 2139 | int db_size; |
697197e5 | 2140 | |
c0c050c5 MC |
2141 | #define BNXT_NTP_FLTR_MAX_FLTR 4096 |
2142 | #define BNXT_NTP_FLTR_HASH_SIZE 512 | |
2143 | #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) | |
2144 | struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; | |
2145 | spinlock_t ntp_fltr_lock; /* for hash table add, del */ | |
2146 | ||
2147 | unsigned long *ntp_fltr_bmap; | |
2148 | int ntp_fltr_count; | |
2149 | ||
e2dc9b6e MC |
2150 | /* To protect link related settings during link changes and |
2151 | * ethtool settings changes. | |
2152 | */ | |
2153 | struct mutex link_lock; | |
c0c050c5 | 2154 | struct bnxt_link_info link_info; |
170ce013 MC |
2155 | struct ethtool_eee eee; |
2156 | u32 lpi_tmr_lo; | |
2157 | u32 lpi_tmr_hi; | |
5ad2cbee | 2158 | |
9a3bc77e MC |
2159 | /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */ |
2160 | u32 phy_flags; | |
b0d28207 MC |
2161 | #define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED |
2162 | #define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED | |
2163 | #define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED | |
2164 | #define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED | |
2165 | #define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET | |
2166 | #define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED | |
d5ca9905 | 2167 | #define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN |
dade5e15 | 2168 | #define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS |
9a3bc77e MC |
2169 | #define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8) |
2170 | #define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8) | |
7ef3d390 | 2171 | #define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8) |
b0d28207 | 2172 | |
eb513658 MC |
2173 | u8 num_tests; |
2174 | struct bnxt_test_info *test_info; | |
2175 | ||
c1ef146a MC |
2176 | u8 wol_filter_id; |
2177 | u8 wol; | |
2178 | ||
5ad2cbee MC |
2179 | u8 num_leds; |
2180 | struct bnxt_led_info leds[BNXT_MAX_LED]; | |
0b0eacf3 VV |
2181 | u16 dump_flag; |
2182 | #define BNXT_DUMP_LIVE 0 | |
2183 | #define BNXT_DUMP_CRASH 1 | |
c6d30e83 MC |
2184 | |
2185 | struct bpf_prog *xdp_prog; | |
4ab0c6a8 | 2186 | |
ae5c42f0 | 2187 | struct bnxt_ptp_cfg *ptp_cfg; |
66ed81dc | 2188 | u8 ptp_all_rx_tstamp; |
ae5c42f0 | 2189 | |
4ab0c6a8 SP |
2190 | /* devlink interface and vf-rep structs */ |
2191 | struct devlink *dl; | |
782a624d | 2192 | struct devlink_port dl_port; |
4ab0c6a8 SP |
2193 | enum devlink_eswitch_mode eswitch_mode; |
2194 | struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */ | |
2195 | u16 *cfa_code_map; /* cfa_code -> vf_idx map */ | |
b014232f | 2196 | u8 dsn[8]; |
cd66358e | 2197 | struct bnxt_tc_info *tc_info; |
627c89d0 | 2198 | struct list_head tc_indr_block_list; |
cabfb09d | 2199 | struct dentry *debugfs_pdev; |
cd13244f | 2200 | #ifdef CONFIG_BNXT_HWMON |
cde49a42 | 2201 | struct device *hwmon_dev; |
cd13244f KA |
2202 | u8 warn_thresh_temp; |
2203 | u8 crit_thresh_temp; | |
2204 | u8 fatal_thresh_temp; | |
2205 | u8 shutdown_thresh_temp; | |
2206 | #endif | |
55862094 | 2207 | u32 thermal_threshold_type; |
c7dd4a5b | 2208 | enum board_idx board_idx; |
c0c050c5 MC |
2209 | }; |
2210 | ||
9d6b648c MC |
2211 | #define BNXT_NUM_RX_RING_STATS 8 |
2212 | #define BNXT_NUM_TX_RING_STATS 8 | |
2213 | #define BNXT_NUM_TPA_RING_STATS 4 | |
2214 | #define BNXT_NUM_TPA_RING_STATS_P5 5 | |
2215 | #define BNXT_NUM_TPA_RING_STATS_P5_SR2 6 | |
2216 | ||
2217 | #define BNXT_RING_STATS_SIZE_P5 \ | |
2218 | ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \ | |
2219 | BNXT_NUM_TPA_RING_STATS_P5) * 8) | |
2220 | ||
2221 | #define BNXT_RING_STATS_SIZE_P5_SR2 \ | |
2222 | ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \ | |
2223 | BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8) | |
2224 | ||
a0c30621 MC |
2225 | #define BNXT_GET_RING_STATS64(sw, counter) \ |
2226 | (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8)) | |
2227 | ||
2228 | #define BNXT_GET_RX_PORT_STATS64(sw, counter) \ | |
2229 | (*((sw) + offsetof(struct rx_port_stats, counter) / 8)) | |
2230 | ||
2231 | #define BNXT_GET_TX_PORT_STATS64(sw, counter) \ | |
2232 | (*((sw) + offsetof(struct tx_port_stats, counter) / 8)) | |
2233 | ||
24c93443 MC |
2234 | #define BNXT_PORT_STATS_SIZE \ |
2235 | (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024) | |
2236 | ||
2237 | #define BNXT_TX_PORT_STATS_BYTE_OFFSET \ | |
2238 | (sizeof(struct rx_port_stats) + 512) | |
2239 | ||
c77192f2 MC |
2240 | #define BNXT_RX_STATS_OFFSET(counter) \ |
2241 | (offsetof(struct rx_port_stats, counter) / 8) | |
2242 | ||
2243 | #define BNXT_TX_STATS_OFFSET(counter) \ | |
2244 | ((offsetof(struct tx_port_stats, counter) + \ | |
24c93443 | 2245 | BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8) |
c77192f2 | 2246 | |
00db3cba VV |
2247 | #define BNXT_RX_STATS_EXT_OFFSET(counter) \ |
2248 | (offsetof(struct rx_port_stats_ext, counter) / 8) | |
2249 | ||
21e70778 MC |
2250 | #define BNXT_RX_STATS_EXT_NUM_LEGACY \ |
2251 | BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks) | |
2252 | ||
36e53349 MC |
2253 | #define BNXT_TX_STATS_EXT_OFFSET(counter) \ |
2254 | (offsetof(struct tx_port_stats_ext, counter) / 8) | |
2255 | ||
a196e96b EP |
2256 | #define BNXT_HW_FEATURE_VLAN_ALL_RX \ |
2257 | (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX) | |
2258 | #define BNXT_HW_FEATURE_VLAN_ALL_TX \ | |
2259 | (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX) | |
2260 | ||
42ee18fe AK |
2261 | #define I2C_DEV_ADDR_A0 0xa0 |
2262 | #define I2C_DEV_ADDR_A2 0xa2 | |
7328a23c | 2263 | #define SFF_DIAG_SUPPORT_OFFSET 0x5c |
42ee18fe AK |
2264 | #define SFF_MODULE_ID_SFP 0x3 |
2265 | #define SFF_MODULE_ID_QSFP 0xc | |
2266 | #define SFF_MODULE_ID_QSFP_PLUS 0xd | |
2267 | #define SFF_MODULE_ID_QSFP28 0x11 | |
2268 | #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 | |
2269 | ||
36647b20 JK |
2270 | static inline u32 bnxt_tx_avail(struct bnxt *bp, |
2271 | const struct bnxt_tx_ring_info *txr) | |
38413406 | 2272 | { |
36647b20 | 2273 | u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons); |
38413406 | 2274 | |
36647b20 | 2275 | return bp->tx_ring_size - (used & bp->tx_ring_mask); |
38413406 MC |
2276 | } |
2277 | ||
c6132f6f MC |
2278 | static inline void bnxt_writeq(struct bnxt *bp, u64 val, |
2279 | volatile void __iomem *addr) | |
2280 | { | |
2281 | #if BITS_PER_LONG == 32 | |
2282 | spin_lock(&bp->db_lock); | |
2283 | lo_hi_writeq(val, addr); | |
2284 | spin_unlock(&bp->db_lock); | |
2285 | #else | |
2286 | writeq(val, addr); | |
2287 | #endif | |
2288 | } | |
697197e5 | 2289 | |
c6132f6f MC |
2290 | static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val, |
2291 | volatile void __iomem *addr) | |
2292 | { | |
2293 | #if BITS_PER_LONG == 32 | |
2294 | spin_lock(&bp->db_lock); | |
2295 | lo_hi_writeq_relaxed(val, addr); | |
2296 | spin_unlock(&bp->db_lock); | |
2297 | #else | |
2298 | writeq_relaxed(val, addr); | |
697197e5 | 2299 | #endif |
c6132f6f | 2300 | } |
697197e5 | 2301 | |
fd141fa4 | 2302 | /* For TX and RX ring doorbells with no ordering guarantee*/ |
697197e5 MC |
2303 | static inline void bnxt_db_write_relaxed(struct bnxt *bp, |
2304 | struct bnxt_db_info *db, u32 idx) | |
fd141fa4 | 2305 | { |
697197e5 | 2306 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
c6132f6f | 2307 | bnxt_writeq_relaxed(bp, db->db_key64 | idx, db->doorbell); |
697197e5 MC |
2308 | } else { |
2309 | u32 db_val = db->db_key32 | idx; | |
2310 | ||
2311 | writel_relaxed(db_val, db->doorbell); | |
2312 | if (bp->flags & BNXT_FLAG_DOUBLE_DB) | |
2313 | writel_relaxed(db_val, db->doorbell); | |
2314 | } | |
fd141fa4 SK |
2315 | } |
2316 | ||
434c975a | 2317 | /* For TX and RX ring doorbells */ |
697197e5 MC |
2318 | static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db, |
2319 | u32 idx) | |
434c975a | 2320 | { |
697197e5 | 2321 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
c6132f6f | 2322 | bnxt_writeq(bp, db->db_key64 | idx, db->doorbell); |
697197e5 MC |
2323 | } else { |
2324 | u32 db_val = db->db_key32 | idx; | |
2325 | ||
2326 | writel(db_val, db->doorbell); | |
2327 | if (bp->flags & BNXT_FLAG_DOUBLE_DB) | |
2328 | writel(db_val, db->doorbell); | |
2329 | } | |
434c975a MC |
2330 | } |
2331 | ||
9f536391 MC |
2332 | /* Must hold rtnl_lock */ |
2333 | static inline bool bnxt_sriov_cfg(struct bnxt *bp) | |
2334 | { | |
2335 | #if defined(CONFIG_BNXT_SRIOV) | |
2336 | return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg); | |
2337 | #else | |
2338 | return false; | |
2339 | #endif | |
2340 | } | |
2341 | ||
38413406 MC |
2342 | extern const u16 bnxt_lhint_arr[]; |
2343 | ||
2344 | int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, | |
2345 | u16 prod, gfp_t gfp); | |
c6d30e83 | 2346 | void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); |
7e914027 | 2347 | u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx); |
c6d30e83 | 2348 | void bnxt_set_tpa_flags(struct bnxt *bp); |
c0c050c5 | 2349 | void bnxt_set_ring_params(struct bnxt *); |
c61fb99c | 2350 | int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); |
2e882468 VV |
2351 | int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, |
2352 | int bmap_size, bool async_only); | |
228ea8c1 | 2353 | int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp); |
f9f6a3fb | 2354 | int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings); |
a588e458 | 2355 | int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id); |
391be5c2 | 2356 | int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings); |
b16b6891 | 2357 | int bnxt_nq_rings_in_use(struct bnxt *bp); |
c0c050c5 | 2358 | int bnxt_hwrm_set_coal(struct bnxt *); |
228ea8c1 | 2359 | void bnxt_free_ctx_mem(struct bnxt *bp); |
e4060d30 | 2360 | unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); |
c027c6b4 | 2361 | unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp); |
e4060d30 | 2362 | unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); |
e916b081 | 2363 | unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp); |
fbcfc8e4 | 2364 | int bnxt_get_avail_msix(struct bnxt *bp, int num); |
1b3f0b75 | 2365 | int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init); |
7df4ae9f MC |
2366 | void bnxt_tx_disable(struct bnxt *bp); |
2367 | void bnxt_tx_enable(struct bnxt *bp); | |
2b56b3d9 JK |
2368 | void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr, |
2369 | int idx); | |
228ea8c1 | 2370 | void bnxt_report_link(struct bnxt *bp); |
ccd6a9dc | 2371 | int bnxt_update_link(struct bnxt *bp, bool chng_link_state); |
c0c050c5 | 2372 | int bnxt_hwrm_set_pause(struct bnxt *); |
939f7f0c | 2373 | int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); |
d900aadd | 2374 | int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset); |
5282db6c MC |
2375 | int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp); |
2376 | int bnxt_hwrm_free_wol_fltr(struct bnxt *bp); | |
db4723b3 | 2377 | int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all); |
c5b744d3 | 2378 | int bnxt_hwrm_func_qcaps(struct bnxt *bp); |
5ac67d8b | 2379 | int bnxt_hwrm_fw_set_time(struct bnxt *); |
c0c050c5 | 2380 | int bnxt_open_nic(struct bnxt *, bool, bool); |
f7dc1ea6 MC |
2381 | int bnxt_half_open_nic(struct bnxt *bp); |
2382 | void bnxt_half_close_nic(struct bnxt *bp); | |
228ea8c1 | 2383 | void bnxt_reenable_sriov(struct bnxt *bp); |
bd6781c1 | 2384 | void bnxt_close_nic(struct bnxt *, bool, bool); |
4c70dbe3 MC |
2385 | void bnxt_get_ring_err_stats(struct bnxt *bp, |
2386 | struct bnxt_total_ring_err_stats *stats); | |
b5d600b0 VV |
2387 | int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words, |
2388 | u32 *reg_buf); | |
d1db9e16 | 2389 | void bnxt_fw_exception(struct bnxt *bp); |
230d1f0d | 2390 | void bnxt_fw_reset(struct bnxt *bp); |
98fdbe73 MC |
2391 | int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, |
2392 | int tx_xdp); | |
228ea8c1 | 2393 | int bnxt_fw_init_one(struct bnxt *bp); |
892a662f | 2394 | bool bnxt_hwrm_reset_permitted(struct bnxt *bp); |
c5e3deb8 | 2395 | int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); |
6e6c5a57 | 2396 | int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); |
80fcaf46 | 2397 | int bnxt_restore_pf_fw_resources(struct bnxt *bp); |
52d5254a FF |
2398 | int bnxt_get_port_parent_id(struct net_device *dev, |
2399 | struct netdev_phys_item_id *ppid); | |
6a8788f2 AG |
2400 | void bnxt_dim_work(struct work_struct *work); |
2401 | int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi); | |
c7dd4a5b | 2402 | void bnxt_print_device_info(struct bnxt *bp); |
c0c050c5 | 2403 | #endif |