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c0c050c5 MC |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
11f15ed3 | 3 | * Copyright (c) 2014-2016 Broadcom Corporation |
894aa69a | 4 | * Copyright (c) 2016-2018 Broadcom Limited |
c0c050c5 MC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef BNXT_H | |
12 | #define BNXT_H | |
13 | ||
14 | #define DRV_MODULE_NAME "bnxt_en" | |
c0c050c5 | 15 | |
e3c0a635 LR |
16 | /* DO NOT CHANGE DRV_VER_* defines |
17 | * FIXME: Delete them | |
18 | */ | |
c193554e | 19 | #define DRV_VER_MAJ 1 |
31d357c0 | 20 | #define DRV_VER_MIN 10 |
41136ab3 | 21 | #define DRV_VER_UPD 1 |
c0c050c5 | 22 | |
282ccf6e | 23 | #include <linux/interrupt.h> |
2ae7408f | 24 | #include <linux/rhashtable.h> |
d629522e | 25 | #include <linux/crash_dump.h> |
4ab0c6a8 | 26 | #include <net/devlink.h> |
ee5c7fb3 | 27 | #include <net/dst_metadata.h> |
96a8604f | 28 | #include <net/xdp.h> |
4f75da36 | 29 | #include <linux/dim.h> |
e07ab202 VV |
30 | #ifdef CONFIG_TEE_BNXT_FW |
31 | #include <linux/firmware/broadcom/tee_bnxt_fw.h> | |
32 | #endif | |
282ccf6e | 33 | |
627c89d0 SB |
34 | extern struct list_head bnxt_block_cb_list; |
35 | ||
322b87ca AG |
36 | struct page_pool; |
37 | ||
c0c050c5 MC |
38 | struct tx_bd { |
39 | __le32 tx_bd_len_flags_type; | |
40 | #define TX_BD_TYPE (0x3f << 0) | |
41 | #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) | |
42 | #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) | |
43 | #define TX_BD_FLAGS_PACKET_END (1 << 6) | |
44 | #define TX_BD_FLAGS_NO_CMPL (1 << 7) | |
45 | #define TX_BD_FLAGS_BD_CNT (0x1f << 8) | |
46 | #define TX_BD_FLAGS_BD_CNT_SHIFT 8 | |
47 | #define TX_BD_FLAGS_LHINT (3 << 13) | |
48 | #define TX_BD_FLAGS_LHINT_SHIFT 13 | |
49 | #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) | |
50 | #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) | |
51 | #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) | |
52 | #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) | |
53 | #define TX_BD_FLAGS_COAL_NOW (1 << 15) | |
54 | #define TX_BD_LEN (0xffff << 16) | |
55 | #define TX_BD_LEN_SHIFT 16 | |
56 | ||
57 | u32 tx_bd_opaque; | |
58 | __le64 tx_bd_haddr; | |
59 | } __packed; | |
60 | ||
61 | struct tx_bd_ext { | |
62 | __le32 tx_bd_hsize_lflags; | |
63 | #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) | |
64 | #define TX_BD_FLAGS_IP_CKSUM (1 << 1) | |
65 | #define TX_BD_FLAGS_NO_CRC (1 << 2) | |
66 | #define TX_BD_FLAGS_STAMP (1 << 3) | |
67 | #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) | |
68 | #define TX_BD_FLAGS_LSO (1 << 5) | |
69 | #define TX_BD_FLAGS_IPID_FMT (1 << 6) | |
70 | #define TX_BD_FLAGS_T_IPID (1 << 7) | |
71 | #define TX_BD_HSIZE (0xff << 16) | |
72 | #define TX_BD_HSIZE_SHIFT 16 | |
73 | ||
74 | __le32 tx_bd_mss; | |
75 | __le32 tx_bd_cfa_action; | |
76 | #define TX_BD_CFA_ACTION (0xffff << 16) | |
77 | #define TX_BD_CFA_ACTION_SHIFT 16 | |
78 | ||
79 | __le32 tx_bd_cfa_meta; | |
80 | #define TX_BD_CFA_META_MASK 0xfffffff | |
81 | #define TX_BD_CFA_META_VID_MASK 0xfff | |
82 | #define TX_BD_CFA_META_PRI_MASK (0xf << 12) | |
83 | #define TX_BD_CFA_META_PRI_SHIFT 12 | |
84 | #define TX_BD_CFA_META_TPID_MASK (3 << 16) | |
85 | #define TX_BD_CFA_META_TPID_SHIFT 16 | |
86 | #define TX_BD_CFA_META_KEY (0xf << 28) | |
87 | #define TX_BD_CFA_META_KEY_SHIFT 28 | |
88 | #define TX_BD_CFA_META_KEY_VLAN (1 << 28) | |
89 | }; | |
90 | ||
91 | struct rx_bd { | |
92 | __le32 rx_bd_len_flags_type; | |
93 | #define RX_BD_TYPE (0x3f << 0) | |
94 | #define RX_BD_TYPE_RX_PACKET_BD 0x4 | |
95 | #define RX_BD_TYPE_RX_BUFFER_BD 0x5 | |
96 | #define RX_BD_TYPE_RX_AGG_BD 0x6 | |
97 | #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) | |
98 | #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) | |
99 | #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) | |
100 | #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) | |
101 | #define RX_BD_FLAGS_SOP (1 << 6) | |
102 | #define RX_BD_FLAGS_EOP (1 << 7) | |
103 | #define RX_BD_FLAGS_BUFFERS (3 << 8) | |
104 | #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) | |
105 | #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) | |
106 | #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) | |
107 | #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) | |
108 | #define RX_BD_LEN (0xffff << 16) | |
109 | #define RX_BD_LEN_SHIFT 16 | |
110 | ||
111 | u32 rx_bd_opaque; | |
112 | __le64 rx_bd_haddr; | |
113 | }; | |
114 | ||
115 | struct tx_cmp { | |
116 | __le32 tx_cmp_flags_type; | |
117 | #define CMP_TYPE (0x3f << 0) | |
118 | #define CMP_TYPE_TX_L2_CMP 0 | |
119 | #define CMP_TYPE_RX_L2_CMP 17 | |
120 | #define CMP_TYPE_RX_AGG_CMP 18 | |
121 | #define CMP_TYPE_RX_L2_TPA_START_CMP 19 | |
122 | #define CMP_TYPE_RX_L2_TPA_END_CMP 21 | |
218a8a71 | 123 | #define CMP_TYPE_RX_TPA_AGG_CMP 22 |
c0c050c5 MC |
124 | #define CMP_TYPE_STATUS_CMP 32 |
125 | #define CMP_TYPE_REMOTE_DRIVER_REQ 34 | |
126 | #define CMP_TYPE_REMOTE_DRIVER_RESP 36 | |
127 | #define CMP_TYPE_ERROR_STATUS 48 | |
441cabbb MC |
128 | #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL |
129 | #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL | |
130 | #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL | |
131 | #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL | |
132 | #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL | |
c0c050c5 MC |
133 | |
134 | #define TX_CMP_FLAGS_ERROR (1 << 6) | |
135 | #define TX_CMP_FLAGS_PUSH (1 << 7) | |
136 | ||
137 | u32 tx_cmp_opaque; | |
138 | __le32 tx_cmp_errors_v; | |
139 | #define TX_CMP_V (1 << 0) | |
140 | #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) | |
141 | #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 | |
142 | #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 | |
143 | #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 | |
144 | #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 | |
145 | #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) | |
146 | #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) | |
147 | #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) | |
148 | #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) | |
149 | ||
150 | __le32 tx_cmp_unsed_3; | |
151 | }; | |
152 | ||
153 | struct rx_cmp { | |
154 | __le32 rx_cmp_len_flags_type; | |
155 | #define RX_CMP_CMP_TYPE (0x3f << 0) | |
156 | #define RX_CMP_FLAGS_ERROR (1 << 6) | |
157 | #define RX_CMP_FLAGS_PLACEMENT (7 << 7) | |
158 | #define RX_CMP_FLAGS_RSS_VALID (1 << 10) | |
159 | #define RX_CMP_FLAGS_UNUSED (1 << 11) | |
160 | #define RX_CMP_FLAGS_ITYPES_SHIFT 12 | |
161 | #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) | |
162 | #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) | |
163 | #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) | |
164 | #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) | |
165 | #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) | |
166 | #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) | |
167 | #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) | |
168 | #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) | |
169 | #define RX_CMP_LEN (0xffff << 16) | |
170 | #define RX_CMP_LEN_SHIFT 16 | |
171 | ||
172 | u32 rx_cmp_opaque; | |
173 | __le32 rx_cmp_misc_v1; | |
174 | #define RX_CMP_V1 (1 << 0) | |
175 | #define RX_CMP_AGG_BUFS (0x1f << 1) | |
176 | #define RX_CMP_AGG_BUFS_SHIFT 1 | |
177 | #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) | |
178 | #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 | |
179 | #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) | |
180 | #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 | |
181 | ||
182 | __le32 rx_cmp_rss_hash; | |
183 | }; | |
184 | ||
185 | #define RX_CMP_HASH_VALID(rxcmp) \ | |
186 | ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) | |
187 | ||
614388ce MC |
188 | #define RSS_PROFILE_ID_MASK 0x1f |
189 | ||
c0c050c5 | 190 | #define RX_CMP_HASH_TYPE(rxcmp) \ |
614388ce MC |
191 | (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ |
192 | RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) | |
c0c050c5 MC |
193 | |
194 | struct rx_cmp_ext { | |
195 | __le32 rx_cmp_flags2; | |
196 | #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 | |
197 | #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) | |
198 | #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) | |
199 | #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) | |
200 | #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) | |
201 | __le32 rx_cmp_meta_data; | |
ed7bc602 | 202 | #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff |
c0c050c5 MC |
203 | #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff |
204 | #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 | |
205 | #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 | |
206 | __le32 rx_cmp_cfa_code_errors_v2; | |
207 | #define RX_CMP_V (1 << 0) | |
208 | #define RX_CMPL_ERRORS_MASK (0x7fff << 1) | |
209 | #define RX_CMPL_ERRORS_SFT 1 | |
210 | #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) | |
211 | #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) | |
212 | #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) | |
213 | #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) | |
214 | #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) | |
215 | #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) | |
216 | #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) | |
217 | #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) | |
218 | #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) | |
219 | #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) | |
220 | #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) | |
221 | #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) | |
222 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) | |
223 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) | |
224 | #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) | |
225 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) | |
226 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) | |
227 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) | |
228 | #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) | |
229 | #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) | |
230 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) | |
231 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) | |
232 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) | |
233 | #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) | |
234 | #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) | |
235 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) | |
236 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) | |
237 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) | |
238 | ||
239 | #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) | |
240 | #define RX_CMPL_CFA_CODE_SFT 16 | |
241 | ||
242 | __le32 rx_cmp_unused3; | |
243 | }; | |
244 | ||
245 | #define RX_CMP_L2_ERRORS \ | |
246 | cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) | |
247 | ||
248 | #define RX_CMP_L4_CS_BITS \ | |
249 | (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) | |
250 | ||
251 | #define RX_CMP_L4_CS_ERR_BITS \ | |
252 | (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) | |
253 | ||
254 | #define RX_CMP_L4_CS_OK(rxcmp1) \ | |
255 | (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ | |
256 | !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) | |
257 | ||
258 | #define RX_CMP_ENCAP(rxcmp1) \ | |
259 | ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ | |
260 | RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) | |
261 | ||
ee5c7fb3 SP |
262 | #define RX_CMP_CFA_CODE(rxcmpl1) \ |
263 | ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \ | |
264 | RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT) | |
265 | ||
c0c050c5 MC |
266 | struct rx_agg_cmp { |
267 | __le32 rx_agg_cmp_len_flags_type; | |
268 | #define RX_AGG_CMP_TYPE (0x3f << 0) | |
269 | #define RX_AGG_CMP_LEN (0xffff << 16) | |
270 | #define RX_AGG_CMP_LEN_SHIFT 16 | |
271 | u32 rx_agg_cmp_opaque; | |
272 | __le32 rx_agg_cmp_v; | |
273 | #define RX_AGG_CMP_V (1 << 0) | |
218a8a71 MC |
274 | #define RX_AGG_CMP_AGG_ID (0xffff << 16) |
275 | #define RX_AGG_CMP_AGG_ID_SHIFT 16 | |
c0c050c5 MC |
276 | __le32 rx_agg_cmp_unused; |
277 | }; | |
278 | ||
218a8a71 MC |
279 | #define TPA_AGG_AGG_ID(rx_agg) \ |
280 | ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \ | |
281 | RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT) | |
282 | ||
c0c050c5 MC |
283 | struct rx_tpa_start_cmp { |
284 | __le32 rx_tpa_start_cmp_len_flags_type; | |
285 | #define RX_TPA_START_CMP_TYPE (0x3f << 0) | |
286 | #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) | |
287 | #define RX_TPA_START_CMP_FLAGS_SHIFT 6 | |
218a8a71 | 288 | #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6) |
c0c050c5 MC |
289 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) |
290 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 | |
291 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) | |
292 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) | |
293 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) | |
294 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) | |
295 | #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) | |
218a8a71 | 296 | #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11) |
c0c050c5 MC |
297 | #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) |
298 | #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 | |
299 | #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) | |
300 | #define RX_TPA_START_CMP_LEN (0xffff << 16) | |
301 | #define RX_TPA_START_CMP_LEN_SHIFT 16 | |
302 | ||
303 | u32 rx_tpa_start_cmp_opaque; | |
304 | __le32 rx_tpa_start_cmp_misc_v1; | |
305 | #define RX_TPA_START_CMP_V1 (0x1 << 0) | |
306 | #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) | |
307 | #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 | |
308 | #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) | |
309 | #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 | |
218a8a71 MC |
310 | #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16) |
311 | #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16 | |
c0c050c5 MC |
312 | |
313 | __le32 rx_tpa_start_cmp_rss_hash; | |
314 | }; | |
315 | ||
316 | #define TPA_START_HASH_VALID(rx_tpa_start) \ | |
317 | ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ | |
318 | cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) | |
319 | ||
320 | #define TPA_START_HASH_TYPE(rx_tpa_start) \ | |
614388ce MC |
321 | (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ |
322 | RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ | |
323 | RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) | |
c0c050c5 MC |
324 | |
325 | #define TPA_START_AGG_ID(rx_tpa_start) \ | |
326 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ | |
327 | RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) | |
328 | ||
218a8a71 MC |
329 | #define TPA_START_AGG_ID_P5(rx_tpa_start) \ |
330 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ | |
331 | RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5) | |
332 | ||
333 | #define TPA_START_ERROR(rx_tpa_start) \ | |
334 | ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ | |
335 | cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR)) | |
336 | ||
c0c050c5 MC |
337 | struct rx_tpa_start_cmp_ext { |
338 | __le32 rx_tpa_start_cmp_flags2; | |
339 | #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) | |
340 | #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) | |
341 | #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) | |
342 | #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) | |
94758f8d | 343 | #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) |
218a8a71 MC |
344 | #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9) |
345 | #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10) | |
346 | #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10 | |
347 | #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16) | |
348 | #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16 | |
c0c050c5 MC |
349 | |
350 | __le32 rx_tpa_start_cmp_metadata; | |
351 | __le32 rx_tpa_start_cmp_cfa_code_v2; | |
352 | #define RX_TPA_START_CMP_V2 (0x1 << 0) | |
218a8a71 MC |
353 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) |
354 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1 | |
355 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) | |
356 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) | |
357 | #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1) | |
c0c050c5 MC |
358 | #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) |
359 | #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 | |
94758f8d | 360 | __le32 rx_tpa_start_cmp_hdr_info; |
c0c050c5 MC |
361 | }; |
362 | ||
ee5c7fb3 SP |
363 | #define TPA_START_CFA_CODE(rx_tpa_start) \ |
364 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ | |
365 | RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT) | |
366 | ||
50f011b6 MC |
367 | #define TPA_START_IS_IPV6(rx_tpa_start) \ |
368 | (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \ | |
369 | cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE))) | |
370 | ||
218a8a71 MC |
371 | #define TPA_START_ERROR_CODE(rx_tpa_start) \ |
372 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ | |
373 | RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \ | |
374 | RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT) | |
375 | ||
c0c050c5 MC |
376 | struct rx_tpa_end_cmp { |
377 | __le32 rx_tpa_end_cmp_len_flags_type; | |
378 | #define RX_TPA_END_CMP_TYPE (0x3f << 0) | |
379 | #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) | |
380 | #define RX_TPA_END_CMP_FLAGS_SHIFT 6 | |
381 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) | |
382 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 | |
383 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) | |
384 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) | |
385 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) | |
386 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) | |
387 | #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) | |
388 | #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) | |
389 | #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 | |
390 | #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) | |
391 | #define RX_TPA_END_CMP_LEN (0xffff << 16) | |
392 | #define RX_TPA_END_CMP_LEN_SHIFT 16 | |
393 | ||
394 | u32 rx_tpa_end_cmp_opaque; | |
395 | __le32 rx_tpa_end_cmp_misc_v1; | |
396 | #define RX_TPA_END_CMP_V1 (0x1 << 0) | |
397 | #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) | |
398 | #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 | |
399 | #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) | |
400 | #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 | |
401 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) | |
402 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 | |
403 | #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) | |
404 | #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 | |
218a8a71 MC |
405 | #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16) |
406 | #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16 | |
c0c050c5 MC |
407 | |
408 | __le32 rx_tpa_end_cmp_tsdelta; | |
409 | #define RX_TPA_END_GRO_TS (0x1 << 31) | |
410 | }; | |
411 | ||
412 | #define TPA_END_AGG_ID(rx_tpa_end) \ | |
413 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
414 | RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) | |
415 | ||
218a8a71 MC |
416 | #define TPA_END_AGG_ID_P5(rx_tpa_end) \ |
417 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
418 | RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5) | |
419 | ||
420 | #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \ | |
421 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
422 | RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT) | |
423 | ||
424 | #define TPA_END_AGG_BUFS(rx_tpa_end) \ | |
425 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
426 | RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT) | |
427 | ||
c0c050c5 MC |
428 | #define TPA_END_TPA_SEGS(rx_tpa_end) \ |
429 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
430 | RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) | |
431 | ||
432 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ | |
433 | cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ | |
434 | RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) | |
435 | ||
436 | #define TPA_END_GRO(rx_tpa_end) \ | |
437 | ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ | |
438 | RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) | |
439 | ||
440 | #define TPA_END_GRO_TS(rx_tpa_end) \ | |
a58a3e68 MC |
441 | (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ |
442 | cpu_to_le32(RX_TPA_END_GRO_TS))) | |
c0c050c5 MC |
443 | |
444 | struct rx_tpa_end_cmp_ext { | |
445 | __le32 rx_tpa_end_cmp_dup_acks; | |
446 | #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) | |
218a8a71 MC |
447 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16) |
448 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16 | |
449 | #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24) | |
450 | #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24 | |
c0c050c5 MC |
451 | |
452 | __le32 rx_tpa_end_cmp_seg_len; | |
453 | #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) | |
454 | ||
455 | __le32 rx_tpa_end_cmp_errors_v2; | |
456 | #define RX_TPA_END_CMP_V2 (0x1 << 0) | |
69c149e2 | 457 | #define RX_TPA_END_CMP_ERRORS (0x3 << 1) |
218a8a71 | 458 | #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1) |
c0c050c5 | 459 | #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 |
218a8a71 MC |
460 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) |
461 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) | |
462 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) | |
463 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1) | |
464 | #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1) | |
c0c050c5 MC |
465 | |
466 | u32 rx_tpa_end_cmp_start_opaque; | |
467 | }; | |
468 | ||
69c149e2 MC |
469 | #define TPA_END_ERRORS(rx_tpa_end_ext) \ |
470 | ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \ | |
471 | cpu_to_le32(RX_TPA_END_CMP_ERRORS)) | |
472 | ||
218a8a71 MC |
473 | #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \ |
474 | ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \ | |
475 | RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \ | |
476 | RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5) | |
477 | ||
478 | #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \ | |
479 | ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \ | |
480 | RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5) | |
481 | ||
acfb50e4 VV |
482 | #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \ |
483 | (((data1) & \ | |
484 | ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ | |
485 | ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL) | |
486 | ||
7e914027 MC |
487 | #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \ |
488 | !!((data1) & \ | |
489 | ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC) | |
490 | ||
491 | #define EVENT_DATA1_RECOVERY_ENABLED(data1) \ | |
492 | !!((data1) & \ | |
493 | ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED) | |
494 | ||
e38287b7 MC |
495 | struct nqe_cn { |
496 | __le16 type; | |
497 | #define NQ_CN_TYPE_MASK 0x3fUL | |
498 | #define NQ_CN_TYPE_SFT 0 | |
499 | #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL | |
500 | #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION | |
501 | __le16 reserved16; | |
502 | __le32 cq_handle_low; | |
503 | __le32 v; | |
504 | #define NQ_CN_V 0x1UL | |
505 | __le32 cq_handle_high; | |
506 | }; | |
507 | ||
c0c050c5 MC |
508 | #define DB_IDX_MASK 0xffffff |
509 | #define DB_IDX_VALID (0x1 << 26) | |
510 | #define DB_IRQ_DIS (0x1 << 27) | |
511 | #define DB_KEY_TX (0x0 << 28) | |
512 | #define DB_KEY_RX (0x1 << 28) | |
513 | #define DB_KEY_CP (0x2 << 28) | |
514 | #define DB_KEY_ST (0x3 << 28) | |
515 | #define DB_KEY_TX_PUSH (0x4 << 28) | |
516 | #define DB_LONG_TX_PUSH (0x2 << 24) | |
517 | ||
e4060d30 MC |
518 | #define BNXT_MIN_ROCE_CP_RINGS 2 |
519 | #define BNXT_MIN_ROCE_STAT_CTXS 1 | |
520 | ||
e38287b7 MC |
521 | /* 64-bit doorbell */ |
522 | #define DBR_INDEX_MASK 0x0000000000ffffffULL | |
523 | #define DBR_XID_MASK 0x000fffff00000000ULL | |
524 | #define DBR_XID_SFT 32 | |
525 | #define DBR_PATH_L2 (0x1ULL << 56) | |
526 | #define DBR_TYPE_SQ (0x0ULL << 60) | |
527 | #define DBR_TYPE_RQ (0x1ULL << 60) | |
528 | #define DBR_TYPE_SRQ (0x2ULL << 60) | |
529 | #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) | |
530 | #define DBR_TYPE_CQ (0x4ULL << 60) | |
531 | #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) | |
532 | #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) | |
533 | #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) | |
534 | #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) | |
535 | #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) | |
536 | #define DBR_TYPE_NQ (0xaULL << 60) | |
537 | #define DBR_TYPE_NQ_ARM (0xbULL << 60) | |
538 | #define DBR_TYPE_NULL (0xfULL << 60) | |
539 | ||
c0c050c5 MC |
540 | #define INVALID_HW_RING_ID ((u16)-1) |
541 | ||
c0c050c5 MC |
542 | /* The hardware supports certain page sizes. Use the supported page sizes |
543 | * to allocate the rings. | |
544 | */ | |
545 | #if (PAGE_SHIFT < 12) | |
546 | #define BNXT_PAGE_SHIFT 12 | |
547 | #elif (PAGE_SHIFT <= 13) | |
548 | #define BNXT_PAGE_SHIFT PAGE_SHIFT | |
549 | #elif (PAGE_SHIFT < 16) | |
550 | #define BNXT_PAGE_SHIFT 13 | |
551 | #else | |
552 | #define BNXT_PAGE_SHIFT 16 | |
553 | #endif | |
554 | ||
555 | #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) | |
556 | ||
2839f28b MC |
557 | /* The RXBD length is 16-bit so we can only support page sizes < 64K */ |
558 | #if (PAGE_SHIFT > 15) | |
559 | #define BNXT_RX_PAGE_SHIFT 15 | |
560 | #else | |
561 | #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT | |
562 | #endif | |
563 | ||
564 | #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) | |
565 | ||
c61fb99c MC |
566 | #define BNXT_MAX_MTU 9500 |
567 | #define BNXT_MAX_PAGE_MODE_MTU \ | |
c6d30e83 MC |
568 | ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \ |
569 | XDP_PACKET_HEADROOM) | |
c61fb99c | 570 | |
4ffcd582 | 571 | #define BNXT_MIN_PKT_SIZE 52 |
c0c050c5 | 572 | |
51dd55b5 MC |
573 | #define BNXT_DEFAULT_RX_RING_SIZE 511 |
574 | #define BNXT_DEFAULT_TX_RING_SIZE 511 | |
c0c050c5 MC |
575 | |
576 | #define MAX_TPA 64 | |
79632e9b | 577 | #define MAX_TPA_P5 256 |
ec4d8e7c | 578 | #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1) |
79632e9b | 579 | #define MAX_TPA_SEGS_P5 0x3f |
c0c050c5 | 580 | |
d0a42d6f MC |
581 | #if (BNXT_PAGE_SHIFT == 16) |
582 | #define MAX_RX_PAGES 1 | |
583 | #define MAX_RX_AGG_PAGES 4 | |
584 | #define MAX_TX_PAGES 1 | |
585 | #define MAX_CP_PAGES 8 | |
586 | #else | |
c0c050c5 MC |
587 | #define MAX_RX_PAGES 8 |
588 | #define MAX_RX_AGG_PAGES 32 | |
589 | #define MAX_TX_PAGES 8 | |
590 | #define MAX_CP_PAGES 64 | |
d0a42d6f | 591 | #endif |
c0c050c5 MC |
592 | |
593 | #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) | |
594 | #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) | |
595 | #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) | |
596 | ||
597 | #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) | |
598 | #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) | |
599 | ||
600 | #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) | |
601 | ||
602 | #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) | |
603 | #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) | |
604 | ||
605 | #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) | |
606 | ||
607 | #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) | |
608 | #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) | |
609 | #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) | |
610 | ||
611 | #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
612 | #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) | |
613 | ||
614 | #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
615 | #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) | |
616 | ||
617 | #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
618 | #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) | |
619 | ||
620 | #define TX_CMP_VALID(txcmp, raw_cons) \ | |
621 | (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ | |
622 | !((raw_cons) & bp->cp_bit)) | |
623 | ||
624 | #define RX_CMP_VALID(rxcmp1, raw_cons) \ | |
625 | (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ | |
626 | !((raw_cons) & bp->cp_bit)) | |
627 | ||
628 | #define RX_AGG_CMP_VALID(agg, raw_cons) \ | |
629 | (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ | |
630 | !((raw_cons) & bp->cp_bit)) | |
631 | ||
0fcec985 MC |
632 | #define NQ_CMP_VALID(nqcmp, raw_cons) \ |
633 | (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit)) | |
634 | ||
c0c050c5 MC |
635 | #define TX_CMP_TYPE(txcmp) \ |
636 | (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) | |
637 | ||
638 | #define RX_CMP_TYPE(rxcmp) \ | |
639 | (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) | |
640 | ||
641 | #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) | |
642 | ||
643 | #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) | |
644 | ||
645 | #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) | |
646 | ||
647 | #define ADV_RAW_CMP(idx, n) ((idx) + (n)) | |
648 | #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) | |
649 | #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) | |
650 | #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) | |
651 | ||
e6ef2699 | 652 | #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) |
e605db80 | 653 | #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) |
ff4fe81d | 654 | #define DFLT_HWRM_CMD_TIMEOUT 500 |
230d1f0d | 655 | #define SHORT_HWRM_CMD_TIMEOUT 20 |
ff4fe81d | 656 | #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) |
c0c050c5 | 657 | #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) |
57a8730b | 658 | #define HWRM_COREDUMP_TIMEOUT ((HWRM_CMD_TIMEOUT) * 12) |
c0c050c5 | 659 | #define HWRM_RESP_ERR_CODE_MASK 0xffff |
a8643e16 | 660 | #define HWRM_RESP_LEN_OFFSET 4 |
c0c050c5 MC |
661 | #define HWRM_RESP_LEN_MASK 0xffff0000 |
662 | #define HWRM_RESP_LEN_SFT 16 | |
663 | #define HWRM_RESP_VALID_MASK 0xff000000 | |
664 | #define BNXT_HWRM_REQ_MAX_SIZE 128 | |
665 | #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \ | |
666 | BNXT_HWRM_REQ_MAX_SIZE) | |
9751e8e7 AG |
667 | #define HWRM_SHORT_MIN_TIMEOUT 3 |
668 | #define HWRM_SHORT_MAX_TIMEOUT 10 | |
669 | #define HWRM_SHORT_TIMEOUT_COUNTER 5 | |
670 | ||
671 | #define HWRM_MIN_TIMEOUT 25 | |
672 | #define HWRM_MAX_TIMEOUT 40 | |
c0c050c5 | 673 | |
cc559c1a MC |
674 | #define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \ |
675 | ((n) * HWRM_SHORT_MIN_TIMEOUT) : \ | |
676 | (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \ | |
677 | ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT)) | |
678 | ||
0000b81a | 679 | #define HWRM_VALID_BIT_DELAY_USEC 150 |
cc559c1a | 680 | |
760b6d33 VD |
681 | #define BNXT_HWRM_CHNL_CHIMP 0 |
682 | #define BNXT_HWRM_CHNL_KONG 1 | |
683 | ||
f18c2b77 AG |
684 | #define BNXT_RX_EVENT 1 |
685 | #define BNXT_AGG_EVENT 2 | |
686 | #define BNXT_TX_EVENT 4 | |
687 | #define BNXT_REDIRECT_EVENT 8 | |
4e5dbbda | 688 | |
c0c050c5 | 689 | struct bnxt_sw_tx_bd { |
f18c2b77 AG |
690 | union { |
691 | struct sk_buff *skb; | |
692 | struct xdp_frame *xdpf; | |
693 | }; | |
c0c050c5 | 694 | DEFINE_DMA_UNMAP_ADDR(mapping); |
f18c2b77 | 695 | DEFINE_DMA_UNMAP_LEN(len); |
c0c050c5 MC |
696 | u8 is_gso; |
697 | u8 is_push; | |
c1ba92a8 | 698 | u8 action; |
38413406 MC |
699 | union { |
700 | unsigned short nr_frags; | |
701 | u16 rx_prod; | |
702 | }; | |
c0c050c5 MC |
703 | }; |
704 | ||
705 | struct bnxt_sw_rx_bd { | |
6bb19474 MC |
706 | void *data; |
707 | u8 *data_ptr; | |
11cd119d | 708 | dma_addr_t mapping; |
c0c050c5 MC |
709 | }; |
710 | ||
711 | struct bnxt_sw_rx_agg_bd { | |
712 | struct page *page; | |
89d0a06c | 713 | unsigned int offset; |
c0c050c5 MC |
714 | dma_addr_t mapping; |
715 | }; | |
716 | ||
6fe19886 | 717 | struct bnxt_ring_mem_info { |
c0c050c5 MC |
718 | int nr_pages; |
719 | int page_size; | |
4f49b2b8 | 720 | u16 flags; |
66cca20a MC |
721 | #define BNXT_RMEM_VALID_PTE_FLAG 1 |
722 | #define BNXT_RMEM_RING_PTE_FLAG 2 | |
4f49b2b8 MC |
723 | #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 |
724 | ||
725 | u16 depth; | |
3be8136c | 726 | u8 init_val; |
66cca20a | 727 | |
c0c050c5 MC |
728 | void **pg_arr; |
729 | dma_addr_t *dma_arr; | |
730 | ||
731 | __le64 *pg_tbl; | |
732 | dma_addr_t pg_tbl_map; | |
733 | ||
734 | int vmem_size; | |
735 | void **vmem; | |
6fe19886 MC |
736 | }; |
737 | ||
738 | struct bnxt_ring_struct { | |
739 | struct bnxt_ring_mem_info ring_mem; | |
c0c050c5 MC |
740 | |
741 | u16 fw_ring_id; /* Ring id filled by Chimp FW */ | |
9899bb59 MC |
742 | union { |
743 | u16 grp_idx; | |
744 | u16 map_idx; /* Used by cmpl rings */ | |
745 | }; | |
23aefdd7 | 746 | u32 handle; |
c0c050c5 MC |
747 | u8 queue_id; |
748 | }; | |
749 | ||
750 | struct tx_push_bd { | |
751 | __le32 doorbell; | |
4419dbe6 MC |
752 | __le32 tx_bd_len_flags_type; |
753 | u32 tx_bd_opaque; | |
c0c050c5 MC |
754 | struct tx_bd_ext txbd2; |
755 | }; | |
756 | ||
4419dbe6 MC |
757 | struct tx_push_buffer { |
758 | struct tx_push_bd push_bd; | |
759 | u32 data[25]; | |
760 | }; | |
761 | ||
697197e5 MC |
762 | struct bnxt_db_info { |
763 | void __iomem *doorbell; | |
764 | union { | |
765 | u64 db_key64; | |
766 | u32 db_key32; | |
767 | }; | |
768 | }; | |
769 | ||
c0c050c5 | 770 | struct bnxt_tx_ring_info { |
b6ab4b01 | 771 | struct bnxt_napi *bnapi; |
c0c050c5 MC |
772 | u16 tx_prod; |
773 | u16 tx_cons; | |
a960dec9 | 774 | u16 txq_index; |
697197e5 | 775 | struct bnxt_db_info tx_db; |
c0c050c5 MC |
776 | |
777 | struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; | |
778 | struct bnxt_sw_tx_bd *tx_buf_ring; | |
779 | ||
780 | dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; | |
781 | ||
4419dbe6 | 782 | struct tx_push_buffer *tx_push; |
c0c050c5 | 783 | dma_addr_t tx_push_mapping; |
4419dbe6 | 784 | __le64 data_mapping; |
c0c050c5 MC |
785 | |
786 | #define BNXT_DEV_STATE_CLOSING 0x1 | |
787 | u32 dev_state; | |
788 | ||
789 | struct bnxt_ring_struct tx_ring_struct; | |
790 | }; | |
791 | ||
74706afa MC |
792 | #define BNXT_LEGACY_COAL_CMPL_PARAMS \ |
793 | (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \ | |
794 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \ | |
795 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \ | |
796 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \ | |
797 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \ | |
798 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \ | |
799 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \ | |
800 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \ | |
801 | RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT) | |
802 | ||
803 | #define BNXT_COAL_CMPL_ENABLES \ | |
804 | (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \ | |
805 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \ | |
806 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \ | |
807 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT) | |
808 | ||
809 | #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \ | |
810 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN | |
811 | ||
812 | #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \ | |
813 | RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT | |
814 | ||
815 | struct bnxt_coal_cap { | |
816 | u32 cmpl_params; | |
817 | u32 nq_params; | |
818 | u16 num_cmpl_dma_aggr_max; | |
819 | u16 num_cmpl_dma_aggr_during_int_max; | |
820 | u16 cmpl_aggr_dma_tmr_max; | |
821 | u16 cmpl_aggr_dma_tmr_during_int_max; | |
822 | u16 int_lat_tmr_min_max; | |
823 | u16 int_lat_tmr_max_max; | |
824 | u16 num_cmpl_aggr_int_max; | |
825 | u16 timer_units; | |
826 | }; | |
827 | ||
6a8788f2 AG |
828 | struct bnxt_coal { |
829 | u16 coal_ticks; | |
830 | u16 coal_ticks_irq; | |
831 | u16 coal_bufs; | |
832 | u16 coal_bufs_irq; | |
833 | /* RING_IDLE enabled when coal ticks < idle_thresh */ | |
834 | u16 idle_thresh; | |
835 | u8 bufs_per_record; | |
836 | u8 budget; | |
837 | }; | |
838 | ||
c0c050c5 | 839 | struct bnxt_tpa_info { |
6bb19474 MC |
840 | void *data; |
841 | u8 *data_ptr; | |
c0c050c5 MC |
842 | dma_addr_t mapping; |
843 | u16 len; | |
844 | unsigned short gso_type; | |
845 | u32 flags2; | |
846 | u32 metadata; | |
847 | enum pkt_hash_types hash_type; | |
848 | u32 rss_hash; | |
94758f8d MC |
849 | u32 hdr_info; |
850 | ||
851 | #define BNXT_TPA_L4_SIZE(hdr_info) \ | |
852 | (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) | |
853 | ||
854 | #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ | |
855 | (((hdr_info) >> 18) & 0x1ff) | |
856 | ||
857 | #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ | |
858 | (((hdr_info) >> 9) & 0x1ff) | |
859 | ||
860 | #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ | |
861 | ((hdr_info) & 0x1ff) | |
4ab0c6a8 SP |
862 | |
863 | u16 cfa_code; /* cfa_code in TPA start compl */ | |
79632e9b MC |
864 | u8 agg_count; |
865 | struct rx_agg_cmp *agg_arr; | |
c0c050c5 MC |
866 | }; |
867 | ||
ec4d8e7c MC |
868 | #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG) |
869 | ||
870 | struct bnxt_tpa_idx_map { | |
871 | u16 agg_id_tbl[1024]; | |
872 | unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE]; | |
873 | }; | |
874 | ||
c0c050c5 | 875 | struct bnxt_rx_ring_info { |
b6ab4b01 | 876 | struct bnxt_napi *bnapi; |
c0c050c5 MC |
877 | u16 rx_prod; |
878 | u16 rx_agg_prod; | |
879 | u16 rx_sw_agg_prod; | |
376a5b86 | 880 | u16 rx_next_cons; |
697197e5 MC |
881 | struct bnxt_db_info rx_db; |
882 | struct bnxt_db_info rx_agg_db; | |
c0c050c5 | 883 | |
c6d30e83 MC |
884 | struct bpf_prog *xdp_prog; |
885 | ||
c0c050c5 MC |
886 | struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; |
887 | struct bnxt_sw_rx_bd *rx_buf_ring; | |
888 | ||
889 | struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; | |
890 | struct bnxt_sw_rx_agg_bd *rx_agg_ring; | |
891 | ||
892 | unsigned long *rx_agg_bmap; | |
893 | u16 rx_agg_bmap_size; | |
894 | ||
89d0a06c MC |
895 | struct page *rx_page; |
896 | unsigned int rx_page_offset; | |
897 | ||
c0c050c5 MC |
898 | dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; |
899 | dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; | |
900 | ||
901 | struct bnxt_tpa_info *rx_tpa; | |
ec4d8e7c | 902 | struct bnxt_tpa_idx_map *rx_tpa_idx_map; |
c0c050c5 MC |
903 | |
904 | struct bnxt_ring_struct rx_ring_struct; | |
905 | struct bnxt_ring_struct rx_agg_ring_struct; | |
96a8604f | 906 | struct xdp_rxq_info xdp_rxq; |
322b87ca | 907 | struct page_pool *page_pool; |
c0c050c5 MC |
908 | }; |
909 | ||
910 | struct bnxt_cp_ring_info { | |
50e3ab78 | 911 | struct bnxt_napi *bnapi; |
c0c050c5 | 912 | u32 cp_raw_cons; |
697197e5 | 913 | struct bnxt_db_info cp_db; |
c0c050c5 | 914 | |
3675b92f | 915 | u8 had_work_done:1; |
0fcec985 | 916 | u8 has_more_work:1; |
3675b92f | 917 | |
ffd77621 MC |
918 | u32 last_cp_raw_cons; |
919 | ||
6a8788f2 AG |
920 | struct bnxt_coal rx_ring_coal; |
921 | u64 rx_packets; | |
922 | u64 rx_bytes; | |
923 | u64 event_ctr; | |
924 | ||
8960b389 | 925 | struct dim dim; |
6a8788f2 | 926 | |
e38287b7 MC |
927 | union { |
928 | struct tx_cmp *cp_desc_ring[MAX_CP_PAGES]; | |
929 | struct nqe_cn *nq_desc_ring[MAX_CP_PAGES]; | |
930 | }; | |
c0c050c5 MC |
931 | |
932 | dma_addr_t cp_desc_mapping[MAX_CP_PAGES]; | |
933 | ||
934 | struct ctx_hw_stats *hw_stats; | |
935 | dma_addr_t hw_stats_map; | |
936 | u32 hw_stats_ctx_id; | |
937 | u64 rx_l4_csum_errors; | |
19b3751f | 938 | u64 rx_buf_errors; |
83eb5c5c | 939 | u64 missed_irqs; |
c0c050c5 MC |
940 | |
941 | struct bnxt_ring_struct cp_ring_struct; | |
e38287b7 MC |
942 | |
943 | struct bnxt_cp_ring_info *cp_ring_arr[2]; | |
50e3ab78 MC |
944 | #define BNXT_RX_HDL 0 |
945 | #define BNXT_TX_HDL 1 | |
c0c050c5 MC |
946 | }; |
947 | ||
948 | struct bnxt_napi { | |
949 | struct napi_struct napi; | |
950 | struct bnxt *bp; | |
951 | ||
952 | int index; | |
953 | struct bnxt_cp_ring_info cp_ring; | |
b6ab4b01 MC |
954 | struct bnxt_rx_ring_info *rx_ring; |
955 | struct bnxt_tx_ring_info *tx_ring; | |
c0c050c5 | 956 | |
fa3e93e8 MC |
957 | void (*tx_int)(struct bnxt *, struct bnxt_napi *, |
958 | int); | |
3675b92f MC |
959 | int tx_pkts; |
960 | u8 events; | |
961 | ||
fa3e93e8 MC |
962 | u32 flags; |
963 | #define BNXT_NAPI_FLAG_XDP 0x1 | |
964 | ||
fa7e2812 | 965 | bool in_reset; |
c0c050c5 MC |
966 | }; |
967 | ||
c0c050c5 MC |
968 | struct bnxt_irq { |
969 | irq_handler_t handler; | |
970 | unsigned int vector; | |
56f0fd80 VV |
971 | u8 requested:1; |
972 | u8 have_cpumask:1; | |
c0c050c5 | 973 | char name[IFNAMSIZ + 2]; |
56f0fd80 | 974 | cpumask_var_t cpu_mask; |
c0c050c5 MC |
975 | }; |
976 | ||
977 | #define HWRM_RING_ALLOC_TX 0x1 | |
978 | #define HWRM_RING_ALLOC_RX 0x2 | |
979 | #define HWRM_RING_ALLOC_AGG 0x4 | |
980 | #define HWRM_RING_ALLOC_CMPL 0x8 | |
697197e5 | 981 | #define HWRM_RING_ALLOC_NQ 0x10 |
c0c050c5 MC |
982 | |
983 | #define INVALID_STATS_CTX_ID -1 | |
984 | ||
c0c050c5 MC |
985 | struct bnxt_ring_grp_info { |
986 | u16 fw_stats_ctx; | |
987 | u16 fw_grp_id; | |
988 | u16 rx_fw_ring_id; | |
989 | u16 agg_fw_ring_id; | |
990 | u16 cp_fw_ring_id; | |
991 | }; | |
992 | ||
993 | struct bnxt_vnic_info { | |
994 | u16 fw_vnic_id; /* returned by Chimp during alloc */ | |
44c6f72a | 995 | #define BNXT_MAX_CTX_PER_VNIC 8 |
94ce9caa | 996 | u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; |
c0c050c5 MC |
997 | u16 fw_l2_ctx_id; |
998 | #define BNXT_MAX_UC_ADDRS 4 | |
999 | __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; | |
1000 | /* index 0 always dev_addr */ | |
1001 | u16 uc_filter_count; | |
1002 | u8 *uc_list; | |
1003 | ||
1004 | u16 *fw_grp_ids; | |
c0c050c5 MC |
1005 | dma_addr_t rss_table_dma_addr; |
1006 | __le16 *rss_table; | |
1007 | dma_addr_t rss_hash_key_dma_addr; | |
1008 | u64 *rss_hash_key; | |
1009 | u32 rx_mask; | |
1010 | ||
1011 | u8 *mc_list; | |
1012 | int mc_list_size; | |
1013 | int mc_list_count; | |
1014 | dma_addr_t mc_list_mapping; | |
1015 | #define BNXT_MAX_MC_ADDRS 16 | |
1016 | ||
1017 | u32 flags; | |
1018 | #define BNXT_VNIC_RSS_FLAG 1 | |
1019 | #define BNXT_VNIC_RFS_FLAG 2 | |
1020 | #define BNXT_VNIC_MCAST_FLAG 4 | |
1021 | #define BNXT_VNIC_UCAST_FLAG 8 | |
ae10ae74 | 1022 | #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10 |
c0c050c5 MC |
1023 | }; |
1024 | ||
6a4f2947 MC |
1025 | struct bnxt_hw_resc { |
1026 | u16 min_rsscos_ctxs; | |
c0c050c5 | 1027 | u16 max_rsscos_ctxs; |
6a4f2947 | 1028 | u16 min_cp_rings; |
c0c050c5 | 1029 | u16 max_cp_rings; |
6a4f2947 MC |
1030 | u16 resv_cp_rings; |
1031 | u16 min_tx_rings; | |
c0c050c5 | 1032 | u16 max_tx_rings; |
6a4f2947 | 1033 | u16 resv_tx_rings; |
db4723b3 | 1034 | u16 max_tx_sch_inputs; |
6a4f2947 | 1035 | u16 min_rx_rings; |
c0c050c5 | 1036 | u16 max_rx_rings; |
6a4f2947 MC |
1037 | u16 resv_rx_rings; |
1038 | u16 min_hw_ring_grps; | |
b72d4a68 | 1039 | u16 max_hw_ring_grps; |
6a4f2947 MC |
1040 | u16 resv_hw_ring_grps; |
1041 | u16 min_l2_ctxs; | |
c0c050c5 | 1042 | u16 max_l2_ctxs; |
6a4f2947 | 1043 | u16 min_vnics; |
c0c050c5 | 1044 | u16 max_vnics; |
6a4f2947 MC |
1045 | u16 resv_vnics; |
1046 | u16 min_stat_ctxs; | |
c0c050c5 | 1047 | u16 max_stat_ctxs; |
780baad4 | 1048 | u16 resv_stat_ctxs; |
f7588cd8 | 1049 | u16 max_nqs; |
6a4f2947 | 1050 | u16 max_irqs; |
75720e63 | 1051 | u16 resv_irqs; |
6a4f2947 MC |
1052 | }; |
1053 | ||
1054 | #if defined(CONFIG_BNXT_SRIOV) | |
1055 | struct bnxt_vf_info { | |
1056 | u16 fw_fid; | |
91cdda40 VV |
1057 | u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */ |
1058 | u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only | |
1059 | * stored by PF. | |
1060 | */ | |
c0c050c5 | 1061 | u16 vlan; |
2a516444 | 1062 | u16 func_qcfg_flags; |
c0c050c5 MC |
1063 | u32 flags; |
1064 | #define BNXT_VF_QOS 0x1 | |
1065 | #define BNXT_VF_SPOOFCHK 0x2 | |
1066 | #define BNXT_VF_LINK_FORCED 0x4 | |
1067 | #define BNXT_VF_LINK_UP 0x8 | |
746df139 | 1068 | #define BNXT_VF_TRUST 0x10 |
c0c050c5 MC |
1069 | u32 min_tx_rate; |
1070 | u32 max_tx_rate; | |
1071 | void *hwrm_cmd_req_addr; | |
1072 | dma_addr_t hwrm_cmd_req_dma_addr; | |
1073 | }; | |
379a80a1 | 1074 | #endif |
c0c050c5 MC |
1075 | |
1076 | struct bnxt_pf_info { | |
1077 | #define BNXT_FIRST_PF_FID 1 | |
1078 | #define BNXT_FIRST_VF_FID 128 | |
a58a3e68 MC |
1079 | u16 fw_fid; |
1080 | u16 port_id; | |
c0c050c5 | 1081 | u8 mac_addr[ETH_ALEN]; |
c0c050c5 MC |
1082 | u32 first_vf_id; |
1083 | u16 active_vfs; | |
230d1f0d | 1084 | u16 registered_vfs; |
c0c050c5 MC |
1085 | u16 max_vfs; |
1086 | u32 max_encap_records; | |
1087 | u32 max_decap_records; | |
1088 | u32 max_tx_em_flows; | |
1089 | u32 max_tx_wm_flows; | |
1090 | u32 max_rx_em_flows; | |
1091 | u32 max_rx_wm_flows; | |
1092 | unsigned long *vf_event_bmap; | |
1093 | u16 hwrm_cmd_req_pages; | |
4673d664 MC |
1094 | u8 vf_resv_strategy; |
1095 | #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0 | |
1096 | #define BNXT_VF_RESV_STRATEGY_MINIMAL 1 | |
bf82736d | 1097 | #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2 |
c0c050c5 MC |
1098 | void *hwrm_cmd_req_addr[4]; |
1099 | dma_addr_t hwrm_cmd_req_dma_addr[4]; | |
1100 | struct bnxt_vf_info *vf; | |
1101 | }; | |
c0c050c5 MC |
1102 | |
1103 | struct bnxt_ntuple_filter { | |
1104 | struct hlist_node hash; | |
a54c4d74 | 1105 | u8 dst_mac_addr[ETH_ALEN]; |
c0c050c5 MC |
1106 | u8 src_mac_addr[ETH_ALEN]; |
1107 | struct flow_keys fkeys; | |
1108 | __le64 filter_id; | |
1109 | u16 sw_id; | |
a54c4d74 | 1110 | u8 l2_fltr_idx; |
c0c050c5 MC |
1111 | u16 rxq; |
1112 | u32 flow_id; | |
1113 | unsigned long state; | |
1114 | #define BNXT_FLTR_VALID 0 | |
1115 | #define BNXT_FLTR_UPDATE 1 | |
1116 | }; | |
1117 | ||
c0c050c5 | 1118 | struct bnxt_link_info { |
03efbec0 | 1119 | u8 phy_type; |
c0c050c5 MC |
1120 | u8 media_type; |
1121 | u8 transceiver; | |
1122 | u8 phy_addr; | |
1123 | u8 phy_link_status; | |
1124 | #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK | |
1125 | #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL | |
1126 | #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK | |
1127 | u8 wire_speed; | |
1128 | u8 loop_back; | |
1129 | u8 link_up; | |
1130 | u8 duplex; | |
acb20054 MC |
1131 | #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF |
1132 | #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL | |
c0c050c5 MC |
1133 | u8 pause; |
1134 | #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX | |
1135 | #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX | |
1136 | #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ | |
1137 | PORT_PHY_QCFG_RESP_PAUSE_TX) | |
3277360e | 1138 | u8 lp_pause; |
c0c050c5 MC |
1139 | u8 auto_pause_setting; |
1140 | u8 force_pause_setting; | |
1141 | u8 duplex_setting; | |
1142 | u8 auto_mode; | |
1143 | #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ | |
1144 | (mode) <= BNXT_LINK_AUTO_MSK) | |
1145 | #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE | |
1146 | #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS | |
1147 | #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED | |
1148 | #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW | |
11f15ed3 | 1149 | #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK |
c0c050c5 MC |
1150 | #define PHY_VER_LEN 3 |
1151 | u8 phy_ver[PHY_VER_LEN]; | |
1152 | u16 link_speed; | |
1153 | #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB | |
1154 | #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB | |
1155 | #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB | |
1156 | #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB | |
1157 | #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB | |
1158 | #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB | |
1159 | #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB | |
1160 | #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB | |
1161 | #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB | |
38a21b34 | 1162 | #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB |
c0c050c5 | 1163 | u16 support_speeds; |
68515a18 | 1164 | u16 auto_link_speeds; /* fw adv setting */ |
c0c050c5 MC |
1165 | #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB |
1166 | #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB | |
1167 | #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB | |
1168 | #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB | |
1169 | #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB | |
1170 | #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB | |
1171 | #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB | |
1172 | #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB | |
1173 | #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB | |
38a21b34 | 1174 | #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB |
93ed8117 | 1175 | u16 support_auto_speeds; |
3277360e | 1176 | u16 lp_auto_link_speeds; |
c0c050c5 MC |
1177 | u16 force_link_speed; |
1178 | u32 preemphasis; | |
42ee18fe | 1179 | u8 module_status; |
e70c752f MC |
1180 | u16 fec_cfg; |
1181 | #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED | |
1182 | #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED | |
1183 | #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | |
c0c050c5 MC |
1184 | |
1185 | /* copy of requested setting from ethtool cmd */ | |
1186 | u8 autoneg; | |
1187 | #define BNXT_AUTONEG_SPEED 1 | |
1188 | #define BNXT_AUTONEG_FLOW_CTRL 2 | |
1189 | u8 req_duplex; | |
1190 | u8 req_flow_ctrl; | |
1191 | u16 req_link_speed; | |
68515a18 | 1192 | u16 advertising; /* user adv setting */ |
c0c050c5 | 1193 | bool force_link_chng; |
4bb13abf | 1194 | |
a1ef4a79 MC |
1195 | bool phy_retry; |
1196 | unsigned long phy_retry_expires; | |
1197 | ||
c0c050c5 MC |
1198 | /* a copy of phy_qcfg output used to report link |
1199 | * info to VF | |
1200 | */ | |
1201 | struct hwrm_port_phy_qcfg_output phy_qcfg_resp; | |
1202 | }; | |
1203 | ||
1204 | #define BNXT_MAX_QUEUE 8 | |
1205 | ||
1206 | struct bnxt_queue_info { | |
1207 | u8 queue_id; | |
1208 | u8 queue_profile; | |
1209 | }; | |
1210 | ||
5ad2cbee MC |
1211 | #define BNXT_MAX_LED 4 |
1212 | ||
1213 | struct bnxt_led_info { | |
1214 | u8 led_id; | |
1215 | u8 led_type; | |
1216 | u8 led_group_id; | |
1217 | u8 unused; | |
1218 | __le16 led_state_caps; | |
1219 | #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ | |
1220 | cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED)) | |
1221 | ||
1222 | __le16 led_color_caps; | |
1223 | }; | |
1224 | ||
eb513658 MC |
1225 | #define BNXT_MAX_TEST 8 |
1226 | ||
1227 | struct bnxt_test_info { | |
1228 | u8 offline_mask; | |
55fd0cf3 | 1229 | u8 flags; |
8a60efd1 MC |
1230 | #define BNXT_TEST_FL_EXT_LPBK 0x1 |
1231 | #define BNXT_TEST_FL_AN_PHY_LPBK 0x2 | |
eb513658 MC |
1232 | u16 timeout; |
1233 | char string[BNXT_MAX_TEST][ETH_GSTRING_LEN]; | |
1234 | }; | |
1235 | ||
2e9ee398 VD |
1236 | #define BNXT_GRCPF_REG_CHIMP_COMM 0x0 |
1237 | #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 | |
1238 | #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 | |
1239 | #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 | |
1240 | #define BNXT_CAG_REG_BASE 0x300000 | |
11809490 | 1241 | |
760b6d33 VD |
1242 | #define BNXT_GRCPF_REG_KONG_COMM 0xA00 |
1243 | #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00 | |
1244 | ||
9ffbd677 MC |
1245 | #define BNXT_GRC_BASE_MASK 0xfffff000 |
1246 | #define BNXT_GRC_OFFSET_MASK 0x00000ffc | |
1247 | ||
5a84acbe SP |
1248 | struct bnxt_tc_flow_stats { |
1249 | u64 packets; | |
1250 | u64 bytes; | |
1251 | }; | |
1252 | ||
627c89d0 SB |
1253 | #ifdef CONFIG_BNXT_FLOWER_OFFLOAD |
1254 | struct bnxt_flower_indr_block_cb_priv { | |
1255 | struct net_device *tunnel_netdev; | |
1256 | struct bnxt *bp; | |
1257 | struct list_head list; | |
1258 | }; | |
1259 | #endif | |
1260 | ||
2ae7408f SP |
1261 | struct bnxt_tc_info { |
1262 | bool enabled; | |
1263 | ||
1264 | /* hash table to store TC offloaded flows */ | |
1265 | struct rhashtable flow_table; | |
1266 | struct rhashtable_params flow_ht_params; | |
1267 | ||
1268 | /* hash table to store L2 keys of TC flows */ | |
1269 | struct rhashtable l2_table; | |
1270 | struct rhashtable_params l2_ht_params; | |
8c95f773 SP |
1271 | /* hash table to store L2 keys for TC tunnel decap */ |
1272 | struct rhashtable decap_l2_table; | |
1273 | struct rhashtable_params decap_l2_ht_params; | |
1274 | /* hash table to store tunnel decap entries */ | |
1275 | struct rhashtable decap_table; | |
1276 | struct rhashtable_params decap_ht_params; | |
1277 | /* hash table to store tunnel encap entries */ | |
1278 | struct rhashtable encap_table; | |
1279 | struct rhashtable_params encap_ht_params; | |
2ae7408f SP |
1280 | |
1281 | /* lock to atomically add/del an l2 node when a flow is | |
1282 | * added or deleted. | |
1283 | */ | |
1284 | struct mutex lock; | |
1285 | ||
5a84acbe SP |
1286 | /* Fields used for batching stats query */ |
1287 | struct rhashtable_iter iter; | |
1288 | #define BNXT_FLOW_STATS_BATCH_MAX 10 | |
1289 | struct bnxt_tc_stats_batch { | |
1290 | void *flow_node; | |
1291 | struct bnxt_tc_flow_stats hw_stats; | |
1292 | } stats_batch[BNXT_FLOW_STATS_BATCH_MAX]; | |
1293 | ||
2ae7408f SP |
1294 | /* Stat counter mask (width) */ |
1295 | u64 bytes_mask; | |
1296 | u64 packets_mask; | |
1297 | }; | |
1298 | ||
4ab0c6a8 SP |
1299 | struct bnxt_vf_rep_stats { |
1300 | u64 packets; | |
1301 | u64 bytes; | |
1302 | u64 dropped; | |
1303 | }; | |
1304 | ||
1305 | struct bnxt_vf_rep { | |
1306 | struct bnxt *bp; | |
1307 | struct net_device *dev; | |
ee5c7fb3 | 1308 | struct metadata_dst *dst; |
4ab0c6a8 SP |
1309 | u16 vf_idx; |
1310 | u16 tx_cfa_action; | |
1311 | u16 rx_cfa_code; | |
1312 | ||
1313 | struct bnxt_vf_rep_stats rx_stats; | |
1314 | struct bnxt_vf_rep_stats tx_stats; | |
1315 | }; | |
1316 | ||
66cca20a MC |
1317 | #define PTU_PTE_VALID 0x1UL |
1318 | #define PTU_PTE_LAST 0x2UL | |
1319 | #define PTU_PTE_NEXT_TO_LAST 0x4UL | |
1320 | ||
98f04cf0 | 1321 | #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) |
08fe9d18 | 1322 | #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) |
98f04cf0 MC |
1323 | |
1324 | struct bnxt_ctx_pg_info { | |
1325 | u32 entries; | |
08fe9d18 | 1326 | u32 nr_pages; |
98f04cf0 MC |
1327 | void *ctx_pg_arr[MAX_CTX_PAGES]; |
1328 | dma_addr_t ctx_dma_arr[MAX_CTX_PAGES]; | |
1329 | struct bnxt_ring_mem_info ring_mem; | |
08fe9d18 | 1330 | struct bnxt_ctx_pg_info **ctx_pg_tbl; |
98f04cf0 MC |
1331 | }; |
1332 | ||
1333 | struct bnxt_ctx_mem_info { | |
1334 | u32 qp_max_entries; | |
1335 | u16 qp_min_qp1_entries; | |
1336 | u16 qp_max_l2_entries; | |
1337 | u16 qp_entry_size; | |
1338 | u16 srq_max_l2_entries; | |
1339 | u32 srq_max_entries; | |
1340 | u16 srq_entry_size; | |
1341 | u16 cq_max_l2_entries; | |
1342 | u32 cq_max_entries; | |
1343 | u16 cq_entry_size; | |
1344 | u16 vnic_max_vnic_entries; | |
1345 | u16 vnic_max_ring_table_entries; | |
1346 | u16 vnic_entry_size; | |
1347 | u32 stat_max_entries; | |
1348 | u16 stat_entry_size; | |
1349 | u16 tqm_entry_size; | |
1350 | u32 tqm_min_entries_per_ring; | |
1351 | u32 tqm_max_entries_per_ring; | |
1352 | u32 mrav_max_entries; | |
1353 | u16 mrav_entry_size; | |
1354 | u16 tim_entry_size; | |
1355 | u32 tim_max_entries; | |
53579e37 | 1356 | u16 mrav_num_entries_units; |
98f04cf0 | 1357 | u8 tqm_entries_multiple; |
3be8136c | 1358 | u8 ctx_kind_initializer; |
98f04cf0 MC |
1359 | |
1360 | u32 flags; | |
1361 | #define BNXT_CTX_FLAG_INITED 0x01 | |
1362 | ||
1363 | struct bnxt_ctx_pg_info qp_mem; | |
1364 | struct bnxt_ctx_pg_info srq_mem; | |
1365 | struct bnxt_ctx_pg_info cq_mem; | |
1366 | struct bnxt_ctx_pg_info vnic_mem; | |
1367 | struct bnxt_ctx_pg_info stat_mem; | |
cf6daed0 MC |
1368 | struct bnxt_ctx_pg_info mrav_mem; |
1369 | struct bnxt_ctx_pg_info tim_mem; | |
98f04cf0 MC |
1370 | struct bnxt_ctx_pg_info *tqm_mem[9]; |
1371 | }; | |
1372 | ||
07f83d72 MC |
1373 | struct bnxt_fw_health { |
1374 | u32 flags; | |
1375 | u32 polling_dsecs; | |
1376 | u32 master_func_wait_dsecs; | |
1377 | u32 normal_func_wait_dsecs; | |
1378 | u32 post_reset_wait_dsecs; | |
1379 | u32 post_reset_max_wait_dsecs; | |
1380 | u32 regs[4]; | |
1381 | u32 mapped_regs[4]; | |
1382 | #define BNXT_FW_HEALTH_REG 0 | |
1383 | #define BNXT_FW_HEARTBEAT_REG 1 | |
1384 | #define BNXT_FW_RESET_CNT_REG 2 | |
1385 | #define BNXT_FW_RESET_INPROG_REG 3 | |
1386 | u32 fw_reset_inprog_reg_mask; | |
1387 | u32 last_fw_heartbeat; | |
1388 | u32 last_fw_reset_cnt; | |
1389 | u8 enabled:1; | |
1390 | u8 master:1; | |
e4e38237 | 1391 | u8 fatal:1; |
07f83d72 MC |
1392 | u8 tmr_multiplier; |
1393 | u8 tmr_counter; | |
1394 | u8 fw_reset_seq_cnt; | |
1395 | u32 fw_reset_seq_regs[16]; | |
1396 | u32 fw_reset_seq_vals[16]; | |
1397 | u32 fw_reset_seq_delay_msec[16]; | |
6763c779 | 1398 | struct devlink_health_reporter *fw_reporter; |
657a33c8 | 1399 | struct devlink_health_reporter *fw_reset_reporter; |
acfb50e4 | 1400 | struct devlink_health_reporter *fw_fatal_reporter; |
657a33c8 VV |
1401 | }; |
1402 | ||
1403 | struct bnxt_fw_reporter_ctx { | |
1404 | unsigned long sp_event; | |
07f83d72 MC |
1405 | }; |
1406 | ||
1407 | #define BNXT_FW_HEALTH_REG_TYPE_MASK 3 | |
1408 | #define BNXT_FW_HEALTH_REG_TYPE_CFG 0 | |
1409 | #define BNXT_FW_HEALTH_REG_TYPE_GRC 1 | |
1410 | #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2 | |
1411 | #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3 | |
1412 | ||
1413 | #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK) | |
1414 | #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK) | |
9ffbd677 MC |
1415 | |
1416 | #define BNXT_FW_HEALTH_WIN_BASE 0x3000 | |
1417 | #define BNXT_FW_HEALTH_WIN_MAP_OFF 8 | |
07f83d72 | 1418 | |
6763c779 | 1419 | #define BNXT_FW_STATUS_HEALTHY 0x8000 |
4037eb71 | 1420 | #define BNXT_FW_STATUS_SHUTDOWN 0x100000 |
6763c779 | 1421 | |
c0c050c5 MC |
1422 | struct bnxt { |
1423 | void __iomem *bar0; | |
1424 | void __iomem *bar1; | |
1425 | void __iomem *bar2; | |
1426 | ||
1427 | u32 reg_base; | |
659c805c MC |
1428 | u16 chip_num; |
1429 | #define CHIP_NUM_57301 0x16c8 | |
1430 | #define CHIP_NUM_57302 0x16c9 | |
1431 | #define CHIP_NUM_57304 0x16ca | |
3e8060fa | 1432 | #define CHIP_NUM_58700 0x16cd |
659c805c MC |
1433 | #define CHIP_NUM_57402 0x16d0 |
1434 | #define CHIP_NUM_57404 0x16d1 | |
1435 | #define CHIP_NUM_57406 0x16d2 | |
3284f9e1 | 1436 | #define CHIP_NUM_57407 0x16d5 |
659c805c MC |
1437 | |
1438 | #define CHIP_NUM_57311 0x16ce | |
1439 | #define CHIP_NUM_57312 0x16cf | |
1440 | #define CHIP_NUM_57314 0x16df | |
3284f9e1 | 1441 | #define CHIP_NUM_57317 0x16e0 |
659c805c MC |
1442 | #define CHIP_NUM_57412 0x16d6 |
1443 | #define CHIP_NUM_57414 0x16d7 | |
1444 | #define CHIP_NUM_57416 0x16d8 | |
1445 | #define CHIP_NUM_57417 0x16d9 | |
3284f9e1 MC |
1446 | #define CHIP_NUM_57412L 0x16da |
1447 | #define CHIP_NUM_57414L 0x16db | |
1448 | ||
1449 | #define CHIP_NUM_5745X 0xd730 | |
fb4cd81e MC |
1450 | #define CHIP_NUM_57452 0xc452 |
1451 | #define CHIP_NUM_57454 0xc454 | |
659c805c | 1452 | |
1dc88b97 MC |
1453 | #define CHIP_NUM_57508 0x1750 |
1454 | #define CHIP_NUM_57504 0x1751 | |
1455 | #define CHIP_NUM_57502 0x1752 | |
e38287b7 | 1456 | |
4a58139b | 1457 | #define CHIP_NUM_58802 0xd802 |
8ed693b7 | 1458 | #define CHIP_NUM_58804 0xd804 |
4a58139b RJ |
1459 | #define CHIP_NUM_58808 0xd808 |
1460 | ||
5313845f MC |
1461 | u8 chip_rev; |
1462 | ||
659c805c MC |
1463 | #define BNXT_CHIP_NUM_5730X(chip_num) \ |
1464 | ((chip_num) >= CHIP_NUM_57301 && \ | |
1465 | (chip_num) <= CHIP_NUM_57304) | |
1466 | ||
1467 | #define BNXT_CHIP_NUM_5740X(chip_num) \ | |
3284f9e1 MC |
1468 | (((chip_num) >= CHIP_NUM_57402 && \ |
1469 | (chip_num) <= CHIP_NUM_57406) || \ | |
1470 | (chip_num) == CHIP_NUM_57407) | |
659c805c MC |
1471 | |
1472 | #define BNXT_CHIP_NUM_5731X(chip_num) \ | |
1473 | ((chip_num) == CHIP_NUM_57311 || \ | |
1474 | (chip_num) == CHIP_NUM_57312 || \ | |
3284f9e1 MC |
1475 | (chip_num) == CHIP_NUM_57314 || \ |
1476 | (chip_num) == CHIP_NUM_57317) | |
659c805c MC |
1477 | |
1478 | #define BNXT_CHIP_NUM_5741X(chip_num) \ | |
1479 | ((chip_num) >= CHIP_NUM_57412 && \ | |
3284f9e1 MC |
1480 | (chip_num) <= CHIP_NUM_57414L) |
1481 | ||
1482 | #define BNXT_CHIP_NUM_58700(chip_num) \ | |
1483 | ((chip_num) == CHIP_NUM_58700) | |
1484 | ||
1485 | #define BNXT_CHIP_NUM_5745X(chip_num) \ | |
fb4cd81e MC |
1486 | ((chip_num) == CHIP_NUM_5745X || \ |
1487 | (chip_num) == CHIP_NUM_57452 || \ | |
1488 | (chip_num) == CHIP_NUM_57454) | |
1489 | ||
659c805c MC |
1490 | |
1491 | #define BNXT_CHIP_NUM_57X0X(chip_num) \ | |
1492 | (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) | |
1493 | ||
1494 | #define BNXT_CHIP_NUM_57X1X(chip_num) \ | |
1495 | (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) | |
c0c050c5 | 1496 | |
4a58139b RJ |
1497 | #define BNXT_CHIP_NUM_588XX(chip_num) \ |
1498 | ((chip_num) == CHIP_NUM_58802 || \ | |
8ed693b7 | 1499 | (chip_num) == CHIP_NUM_58804 || \ |
4a58139b RJ |
1500 | (chip_num) == CHIP_NUM_58808) |
1501 | ||
a0d0fd70 VV |
1502 | #define BNXT_VPD_FLD_LEN 32 |
1503 | char board_partno[BNXT_VPD_FLD_LEN]; | |
1504 | char board_serialno[BNXT_VPD_FLD_LEN]; | |
1505 | ||
c0c050c5 MC |
1506 | struct net_device *dev; |
1507 | struct pci_dev *pdev; | |
1508 | ||
1509 | atomic_t intr_sem; | |
1510 | ||
1511 | u32 flags; | |
e38287b7 | 1512 | #define BNXT_FLAG_CHIP_P5 0x1 |
c0c050c5 MC |
1513 | #define BNXT_FLAG_VF 0x2 |
1514 | #define BNXT_FLAG_LRO 0x4 | |
d1611c3a | 1515 | #ifdef CONFIG_INET |
c0c050c5 | 1516 | #define BNXT_FLAG_GRO 0x8 |
d1611c3a MC |
1517 | #else |
1518 | /* Cannot support hardware GRO if CONFIG_INET is not set */ | |
1519 | #define BNXT_FLAG_GRO 0x0 | |
1520 | #endif | |
c0c050c5 MC |
1521 | #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) |
1522 | #define BNXT_FLAG_JUMBO 0x10 | |
1523 | #define BNXT_FLAG_STRIP_VLAN 0x20 | |
1524 | #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ | |
1525 | BNXT_FLAG_LRO) | |
1526 | #define BNXT_FLAG_USING_MSIX 0x40 | |
1527 | #define BNXT_FLAG_MSIX_CAP 0x80 | |
1528 | #define BNXT_FLAG_RFS 0x100 | |
6e6c5a57 | 1529 | #define BNXT_FLAG_SHARED_RINGS 0x200 |
3bdf56c4 | 1530 | #define BNXT_FLAG_PORT_STATS 0x400 |
87da7f79 | 1531 | #define BNXT_FLAG_UDP_RSS_CAP 0x800 |
170ce013 | 1532 | #define BNXT_FLAG_EEE_CAP 0x1000 |
8fdefd63 | 1533 | #define BNXT_FLAG_NEW_RSS_CAP 0x2000 |
c1ef146a | 1534 | #define BNXT_FLAG_WOL_CAP 0x4000 |
e4060d30 MC |
1535 | #define BNXT_FLAG_ROCEV1_CAP 0x8000 |
1536 | #define BNXT_FLAG_ROCEV2_CAP 0x10000 | |
1537 | #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \ | |
1538 | BNXT_FLAG_ROCEV2_CAP) | |
bdbd1eb5 | 1539 | #define BNXT_FLAG_NO_AGG_RINGS 0x20000 |
c61fb99c | 1540 | #define BNXT_FLAG_RX_PAGE_MODE 0x40000 |
9e54e322 | 1541 | #define BNXT_FLAG_MULTI_HOST 0x100000 |
d061b241 | 1542 | #define BNXT_FLAG_DSN_VALID 0x200000 |
434c975a | 1543 | #define BNXT_FLAG_DOUBLE_DB 0x400000 |
3e8060fa | 1544 | #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 |
6a8788f2 | 1545 | #define BNXT_FLAG_DIM 0x2000000 |
abe93ad2 | 1546 | #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000 |
00db3cba | 1547 | #define BNXT_FLAG_PORT_STATS_EXT 0x10000000 |
55e4398d | 1548 | #define BNXT_FLAG_PCIE_STATS 0x40000000 |
6e6c5a57 | 1549 | |
c0c050c5 MC |
1550 | #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ |
1551 | BNXT_FLAG_RFS | \ | |
1552 | BNXT_FLAG_STRIP_VLAN) | |
1553 | ||
1554 | #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) | |
1555 | #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) | |
567b2abe | 1556 | #define BNXT_NPAR(bp) ((bp)->port_partition_type) |
9e54e322 DK |
1557 | #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) |
1558 | #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) | |
c7e457f4 MC |
1559 | #define BNXT_PHY_CFG_ABLE(bp) (BNXT_SINGLE_PF(bp) || \ |
1560 | ((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG)) | |
3e8060fa | 1561 | #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) |
c61fb99c | 1562 | #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE) |
e38287b7 | 1563 | #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \ |
7c380918 MC |
1564 | (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \ |
1565 | (bp)->max_tpa_v2) && !is_kdump_kernel()) | |
c0c050c5 | 1566 | |
e38287b7 MC |
1567 | /* Chip class phase 5 */ |
1568 | #define BNXT_CHIP_P5(bp) \ | |
1dc88b97 MC |
1569 | ((bp)->chip_num == CHIP_NUM_57508 || \ |
1570 | (bp)->chip_num == CHIP_NUM_57504 || \ | |
1571 | (bp)->chip_num == CHIP_NUM_57502) | |
e38287b7 MC |
1572 | |
1573 | /* Chip class phase 4.x */ | |
1574 | #define BNXT_CHIP_P4(bp) \ | |
3284f9e1 MC |
1575 | (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \ |
1576 | BNXT_CHIP_NUM_5745X((bp)->chip_num) || \ | |
4a58139b | 1577 | BNXT_CHIP_NUM_588XX((bp)->chip_num) || \ |
3284f9e1 MC |
1578 | (BNXT_CHIP_NUM_58700((bp)->chip_num) && \ |
1579 | !BNXT_CHIP_TYPE_NITRO_A0(bp))) | |
1580 | ||
e38287b7 MC |
1581 | #define BNXT_CHIP_P4_PLUS(bp) \ |
1582 | (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp)) | |
1583 | ||
a588e458 MC |
1584 | struct bnxt_en_dev *edev; |
1585 | struct bnxt_en_dev * (*ulp_probe)(struct net_device *); | |
1586 | ||
c0c050c5 MC |
1587 | struct bnxt_napi **bnapi; |
1588 | ||
b6ab4b01 MC |
1589 | struct bnxt_rx_ring_info *rx_ring; |
1590 | struct bnxt_tx_ring_info *tx_ring; | |
a960dec9 | 1591 | u16 *tx_ring_map; |
b6ab4b01 | 1592 | |
309369c9 MC |
1593 | struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, |
1594 | struct sk_buff *); | |
1595 | ||
6bb19474 MC |
1596 | struct sk_buff * (*rx_skb_func)(struct bnxt *, |
1597 | struct bnxt_rx_ring_info *, | |
1598 | u16, void *, u8 *, dma_addr_t, | |
1599 | unsigned int); | |
1600 | ||
79632e9b MC |
1601 | u16 max_tpa_v2; |
1602 | u16 max_tpa; | |
c0c050c5 MC |
1603 | u32 rx_buf_size; |
1604 | u32 rx_buf_use_size; /* useable size */ | |
b3dba77c MC |
1605 | u16 rx_offset; |
1606 | u16 rx_dma_offset; | |
745fc05c | 1607 | enum dma_data_direction rx_dir; |
c0c050c5 MC |
1608 | u32 rx_ring_size; |
1609 | u32 rx_agg_ring_size; | |
1610 | u32 rx_copy_thresh; | |
1611 | u32 rx_ring_mask; | |
1612 | u32 rx_agg_ring_mask; | |
1613 | int rx_nr_pages; | |
1614 | int rx_agg_nr_pages; | |
1615 | int rx_nr_rings; | |
1616 | int rsscos_nr_ctxs; | |
1617 | ||
1618 | u32 tx_ring_size; | |
1619 | u32 tx_ring_mask; | |
1620 | int tx_nr_pages; | |
1621 | int tx_nr_rings; | |
1622 | int tx_nr_rings_per_tc; | |
5f449249 | 1623 | int tx_nr_rings_xdp; |
c0c050c5 MC |
1624 | |
1625 | int tx_wake_thresh; | |
1626 | int tx_push_thresh; | |
1627 | int tx_push_size; | |
1628 | ||
1629 | u32 cp_ring_size; | |
1630 | u32 cp_ring_mask; | |
1631 | u32 cp_bit; | |
1632 | int cp_nr_pages; | |
1633 | int cp_nr_rings; | |
1634 | ||
b81a90d3 | 1635 | /* grp_info indexed by completion ring index */ |
c0c050c5 MC |
1636 | struct bnxt_ring_grp_info *grp_info; |
1637 | struct bnxt_vnic_info *vnic_info; | |
1638 | int nr_vnics; | |
87da7f79 | 1639 | u32 rss_hash_cfg; |
c0c050c5 | 1640 | |
7eb9bb3a | 1641 | u16 max_mtu; |
c0c050c5 | 1642 | u8 max_tc; |
87c374de | 1643 | u8 max_lltc; /* lossless TCs */ |
c0c050c5 | 1644 | struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; |
2e8ef77e | 1645 | u8 tc_to_qidx[BNXT_MAX_QUEUE]; |
98f04cf0 MC |
1646 | u8 q_ids[BNXT_MAX_QUEUE]; |
1647 | u8 max_q; | |
c0c050c5 MC |
1648 | |
1649 | unsigned int current_interval; | |
3bdf56c4 | 1650 | #define BNXT_TIMER_INTERVAL HZ |
c0c050c5 MC |
1651 | |
1652 | struct timer_list timer; | |
1653 | ||
caefe526 MC |
1654 | unsigned long state; |
1655 | #define BNXT_STATE_OPEN 0 | |
4cebdcec | 1656 | #define BNXT_STATE_IN_SP_TASK 1 |
f9b76ebd | 1657 | #define BNXT_STATE_READ_STATS 2 |
ec5d31e3 | 1658 | #define BNXT_STATE_FW_RESET_DET 3 |
3bc7d4a3 | 1659 | #define BNXT_STATE_IN_FW_RESET 4 |
ec5d31e3 | 1660 | #define BNXT_STATE_ABORT_ERR 5 |
b4fff207 | 1661 | #define BNXT_STATE_FW_FATAL_COND 6 |
bdb38602 | 1662 | #define BNXT_STATE_DRV_REGISTERED 7 |
c0c050c5 MC |
1663 | |
1664 | struct bnxt_irq *irq_tbl; | |
7809592d | 1665 | int total_irqs; |
c0c050c5 MC |
1666 | u8 mac_addr[ETH_ALEN]; |
1667 | ||
7df4ae9f MC |
1668 | #ifdef CONFIG_BNXT_DCB |
1669 | struct ieee_pfc *ieee_pfc; | |
1670 | struct ieee_ets *ieee_ets; | |
1671 | u8 dcbx_cap; | |
1672 | u8 default_pri; | |
afdc8a84 | 1673 | u8 max_dscp_value; |
7df4ae9f MC |
1674 | #endif /* CONFIG_BNXT_DCB */ |
1675 | ||
c0c050c5 MC |
1676 | u32 msg_enable; |
1677 | ||
97381a18 | 1678 | u32 fw_cap; |
760b6d33 VD |
1679 | #define BNXT_FW_CAP_SHORT_CMD 0x00000001 |
1680 | #define BNXT_FW_CAP_LLDP_AGENT 0x00000002 | |
1681 | #define BNXT_FW_CAP_DCBX_AGENT 0x00000004 | |
1682 | #define BNXT_FW_CAP_NEW_RM 0x00000008 | |
1683 | #define BNXT_FW_CAP_IF_CHANGE 0x00000010 | |
1684 | #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080 | |
abd43a13 | 1685 | #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400 |
2a516444 | 1686 | #define BNXT_FW_CAP_TRUSTED_VF 0x00000800 |
07f83d72 | 1687 | #define BNXT_FW_CAP_ERROR_RECOVERY 0x00002000 |
691aa620 | 1688 | #define BNXT_FW_CAP_PKG_VER 0x00004000 |
e969ae5b | 1689 | #define BNXT_FW_CAP_CFA_ADV_FLOW 0x00008000 |
41136ab3 | 1690 | #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 0x00010000 |
55e4398d | 1691 | #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000 |
6154532f | 1692 | #define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000 |
4037eb71 | 1693 | #define BNXT_FW_CAP_ERR_RECOVER_RELOAD 0x00100000 |
0a3f4e4f | 1694 | #define BNXT_FW_CAP_HOT_RESET 0x00200000 |
c7e457f4 | 1695 | #define BNXT_FW_CAP_SHARED_PORT_CFG 0x00400000 |
97381a18 MC |
1696 | |
1697 | #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM) | |
11f15ed3 | 1698 | u32 hwrm_spec_code; |
c0c050c5 | 1699 | u16 hwrm_cmd_seq; |
760b6d33 | 1700 | u16 hwrm_cmd_kong_seq; |
fc718bb2 | 1701 | u16 hwrm_intr_seq_id; |
e605db80 DK |
1702 | void *hwrm_short_cmd_req_addr; |
1703 | dma_addr_t hwrm_short_cmd_req_dma_addr; | |
c0c050c5 MC |
1704 | void *hwrm_cmd_resp_addr; |
1705 | dma_addr_t hwrm_cmd_resp_dma_addr; | |
760b6d33 VD |
1706 | void *hwrm_cmd_kong_resp_addr; |
1707 | dma_addr_t hwrm_cmd_kong_resp_dma_addr; | |
3bdf56c4 | 1708 | |
b8875ca3 | 1709 | struct rtnl_link_stats64 net_stats_prev; |
3bdf56c4 MC |
1710 | struct rx_port_stats *hw_rx_port_stats; |
1711 | struct tx_port_stats *hw_tx_port_stats; | |
00db3cba | 1712 | struct rx_port_stats_ext *hw_rx_port_stats_ext; |
35b842f2 | 1713 | struct tx_port_stats_ext *hw_tx_port_stats_ext; |
55e4398d | 1714 | struct pcie_ctx_hw_stats *hw_pcie_stats; |
3bdf56c4 MC |
1715 | dma_addr_t hw_rx_port_stats_map; |
1716 | dma_addr_t hw_tx_port_stats_map; | |
00db3cba | 1717 | dma_addr_t hw_rx_port_stats_ext_map; |
36e53349 | 1718 | dma_addr_t hw_tx_port_stats_ext_map; |
55e4398d | 1719 | dma_addr_t hw_pcie_stats_map; |
3bdf56c4 | 1720 | int hw_port_stats_size; |
36e53349 MC |
1721 | u16 fw_rx_stats_ext_size; |
1722 | u16 fw_tx_stats_ext_size; | |
4e748506 | 1723 | u16 hw_ring_stats_size; |
a24ec322 | 1724 | u8 pri2cos_idx[8]; |
e37fed79 | 1725 | u8 pri2cos_valid; |
3bdf56c4 | 1726 | |
e6ef2699 | 1727 | u16 hwrm_max_req_len; |
1dfddc41 | 1728 | u16 hwrm_max_ext_req_len; |
ff4fe81d | 1729 | int hwrm_cmd_timeout; |
c0c050c5 MC |
1730 | struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ |
1731 | struct hwrm_ver_get_output ver_resp; | |
1732 | #define FW_VER_STR_LEN 32 | |
1733 | #define BC_HWRM_STR_LEN 21 | |
1734 | #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) | |
1735 | char fw_ver_str[FW_VER_STR_LEN]; | |
b7a444f0 | 1736 | char hwrm_ver_supp[FW_VER_STR_LEN]; |
c0c050c5 MC |
1737 | __be16 vxlan_port; |
1738 | u8 vxlan_port_cnt; | |
1739 | __le16 vxlan_fw_dst_port_id; | |
7cdd5fc3 | 1740 | __be16 nge_port; |
c0c050c5 MC |
1741 | u8 nge_port_cnt; |
1742 | __le16 nge_fw_dst_port_id; | |
567b2abe | 1743 | u8 port_partition_type; |
d5430d31 | 1744 | u8 port_count; |
32e8239c | 1745 | u16 br_mode; |
dfc9c94a | 1746 | |
74706afa | 1747 | struct bnxt_coal_cap coal_cap; |
18775aa8 MC |
1748 | struct bnxt_coal rx_coal; |
1749 | struct bnxt_coal tx_coal; | |
c0c050c5 | 1750 | |
51f30785 MC |
1751 | u32 stats_coal_ticks; |
1752 | #define BNXT_DEF_STATS_COAL_TICKS 1000000 | |
1753 | #define BNXT_MIN_STATS_COAL_TICKS 250000 | |
1754 | #define BNXT_MAX_STATS_COAL_TICKS 1000000 | |
1755 | ||
c0c050c5 MC |
1756 | struct work_struct sp_task; |
1757 | unsigned long sp_event; | |
1758 | #define BNXT_RX_MASK_SP_EVENT 0 | |
1759 | #define BNXT_RX_NTP_FLTR_SP_EVENT 1 | |
1760 | #define BNXT_LINK_CHNG_SP_EVENT 2 | |
c5d7774d JH |
1761 | #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 |
1762 | #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 | |
1763 | #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 | |
1764 | #define BNXT_RESET_TASK_SP_EVENT 6 | |
1765 | #define BNXT_RST_RING_SP_EVENT 7 | |
19241368 | 1766 | #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 |
3bdf56c4 | 1767 | #define BNXT_PERIODIC_STATS_SP_EVENT 9 |
4bb13abf | 1768 | #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 |
fc0f1929 | 1769 | #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 |
7cdd5fc3 AD |
1770 | #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 |
1771 | #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 | |
286ef9d6 | 1772 | #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 |
5a84acbe | 1773 | #define BNXT_FLOW_STATS_SP_EVENT 15 |
a1ef4a79 | 1774 | #define BNXT_UPDATE_PHY_SP_EVENT 16 |
ffd77621 | 1775 | #define BNXT_RING_COAL_NOW_SP_EVENT 17 |
2151fe08 | 1776 | #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18 |
acfb50e4 | 1777 | #define BNXT_FW_EXCEPTION_SP_EVENT 19 |
b1613e78 | 1778 | #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21 |
2151fe08 | 1779 | |
230d1f0d MC |
1780 | struct delayed_work fw_reset_task; |
1781 | int fw_reset_state; | |
1782 | #define BNXT_FW_RESET_STATE_POLL_VF 1 | |
1783 | #define BNXT_FW_RESET_STATE_RESET_FW 2 | |
1784 | #define BNXT_FW_RESET_STATE_ENABLE_DEV 3 | |
1785 | #define BNXT_FW_RESET_STATE_POLL_FW 4 | |
1786 | #define BNXT_FW_RESET_STATE_OPENING 5 | |
4037eb71 | 1787 | #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6 |
230d1f0d | 1788 | |
2151fe08 MC |
1789 | u16 fw_reset_min_dsecs; |
1790 | #define BNXT_DFLT_FW_RST_MIN_DSECS 20 | |
1791 | u16 fw_reset_max_dsecs; | |
1792 | #define BNXT_DFLT_FW_RST_MAX_DSECS 60 | |
1793 | unsigned long fw_reset_timestamp; | |
c0c050c5 | 1794 | |
07f83d72 MC |
1795 | struct bnxt_fw_health *fw_health; |
1796 | ||
6a4f2947 | 1797 | struct bnxt_hw_resc hw_resc; |
379a80a1 | 1798 | struct bnxt_pf_info pf; |
98f04cf0 | 1799 | struct bnxt_ctx_mem_info *ctx; |
c0c050c5 MC |
1800 | #ifdef CONFIG_BNXT_SRIOV |
1801 | int nr_vfs; | |
c0c050c5 MC |
1802 | struct bnxt_vf_info vf; |
1803 | wait_queue_head_t sriov_cfg_wait; | |
1804 | bool sriov_cfg; | |
1805 | #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) | |
4ab0c6a8 SP |
1806 | |
1807 | /* lock to protect VF-rep creation/cleanup via | |
1808 | * multiple paths such as ->sriov_configure() and | |
1809 | * devlink ->eswitch_mode_set() | |
1810 | */ | |
1811 | struct mutex sriov_lock; | |
c0c050c5 MC |
1812 | #endif |
1813 | ||
697197e5 MC |
1814 | #if BITS_PER_LONG == 32 |
1815 | /* ensure atomic 64-bit doorbell writes on 32-bit systems. */ | |
1816 | spinlock_t db_lock; | |
1817 | #endif | |
1818 | ||
c0c050c5 MC |
1819 | #define BNXT_NTP_FLTR_MAX_FLTR 4096 |
1820 | #define BNXT_NTP_FLTR_HASH_SIZE 512 | |
1821 | #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) | |
1822 | struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; | |
1823 | spinlock_t ntp_fltr_lock; /* for hash table add, del */ | |
1824 | ||
1825 | unsigned long *ntp_fltr_bmap; | |
1826 | int ntp_fltr_count; | |
1827 | ||
e2dc9b6e MC |
1828 | /* To protect link related settings during link changes and |
1829 | * ethtool settings changes. | |
1830 | */ | |
1831 | struct mutex link_lock; | |
c0c050c5 | 1832 | struct bnxt_link_info link_info; |
170ce013 MC |
1833 | struct ethtool_eee eee; |
1834 | u32 lpi_tmr_lo; | |
1835 | u32 lpi_tmr_hi; | |
5ad2cbee | 1836 | |
eb513658 MC |
1837 | u8 num_tests; |
1838 | struct bnxt_test_info *test_info; | |
1839 | ||
c1ef146a MC |
1840 | u8 wol_filter_id; |
1841 | u8 wol; | |
1842 | ||
5ad2cbee MC |
1843 | u8 num_leds; |
1844 | struct bnxt_led_info leds[BNXT_MAX_LED]; | |
0b0eacf3 VV |
1845 | u16 dump_flag; |
1846 | #define BNXT_DUMP_LIVE 0 | |
1847 | #define BNXT_DUMP_CRASH 1 | |
c6d30e83 MC |
1848 | |
1849 | struct bpf_prog *xdp_prog; | |
4ab0c6a8 SP |
1850 | |
1851 | /* devlink interface and vf-rep structs */ | |
1852 | struct devlink *dl; | |
782a624d | 1853 | struct devlink_port dl_port; |
4ab0c6a8 SP |
1854 | enum devlink_eswitch_mode eswitch_mode; |
1855 | struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */ | |
1856 | u16 *cfa_code_map; /* cfa_code -> vf_idx map */ | |
b014232f | 1857 | u8 dsn[8]; |
cd66358e | 1858 | struct bnxt_tc_info *tc_info; |
627c89d0 SB |
1859 | struct list_head tc_indr_block_list; |
1860 | struct notifier_block tc_netdev_nb; | |
cabfb09d | 1861 | struct dentry *debugfs_pdev; |
cde49a42 | 1862 | struct device *hwmon_dev; |
c0c050c5 MC |
1863 | }; |
1864 | ||
c77192f2 MC |
1865 | #define BNXT_RX_STATS_OFFSET(counter) \ |
1866 | (offsetof(struct rx_port_stats, counter) / 8) | |
1867 | ||
1868 | #define BNXT_TX_STATS_OFFSET(counter) \ | |
1869 | ((offsetof(struct tx_port_stats, counter) + \ | |
1870 | sizeof(struct rx_port_stats) + 512) / 8) | |
1871 | ||
00db3cba VV |
1872 | #define BNXT_RX_STATS_EXT_OFFSET(counter) \ |
1873 | (offsetof(struct rx_port_stats_ext, counter) / 8) | |
1874 | ||
36e53349 MC |
1875 | #define BNXT_TX_STATS_EXT_OFFSET(counter) \ |
1876 | (offsetof(struct tx_port_stats_ext, counter) / 8) | |
1877 | ||
55e4398d VV |
1878 | #define BNXT_PCIE_STATS_OFFSET(counter) \ |
1879 | (offsetof(struct pcie_ctx_hw_stats, counter) / 8) | |
1880 | ||
42ee18fe AK |
1881 | #define I2C_DEV_ADDR_A0 0xa0 |
1882 | #define I2C_DEV_ADDR_A2 0xa2 | |
7328a23c | 1883 | #define SFF_DIAG_SUPPORT_OFFSET 0x5c |
42ee18fe AK |
1884 | #define SFF_MODULE_ID_SFP 0x3 |
1885 | #define SFF_MODULE_ID_QSFP 0xc | |
1886 | #define SFF_MODULE_ID_QSFP_PLUS 0xd | |
1887 | #define SFF_MODULE_ID_QSFP28 0x11 | |
1888 | #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 | |
1889 | ||
38413406 MC |
1890 | static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) |
1891 | { | |
1892 | /* Tell compiler to fetch tx indices from memory. */ | |
1893 | barrier(); | |
1894 | ||
1895 | return bp->tx_ring_size - | |
1896 | ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); | |
1897 | } | |
1898 | ||
697197e5 MC |
1899 | #if BITS_PER_LONG == 32 |
1900 | #define writeq(val64, db) \ | |
1901 | do { \ | |
1902 | spin_lock(&bp->db_lock); \ | |
1903 | writel((val64) & 0xffffffff, db); \ | |
1904 | writel((val64) >> 32, (db) + 4); \ | |
1905 | spin_unlock(&bp->db_lock); \ | |
1906 | } while (0) | |
1907 | ||
1908 | #define writeq_relaxed writeq | |
1909 | #endif | |
1910 | ||
fd141fa4 | 1911 | /* For TX and RX ring doorbells with no ordering guarantee*/ |
697197e5 MC |
1912 | static inline void bnxt_db_write_relaxed(struct bnxt *bp, |
1913 | struct bnxt_db_info *db, u32 idx) | |
fd141fa4 | 1914 | { |
697197e5 MC |
1915 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
1916 | writeq_relaxed(db->db_key64 | idx, db->doorbell); | |
1917 | } else { | |
1918 | u32 db_val = db->db_key32 | idx; | |
1919 | ||
1920 | writel_relaxed(db_val, db->doorbell); | |
1921 | if (bp->flags & BNXT_FLAG_DOUBLE_DB) | |
1922 | writel_relaxed(db_val, db->doorbell); | |
1923 | } | |
fd141fa4 SK |
1924 | } |
1925 | ||
434c975a | 1926 | /* For TX and RX ring doorbells */ |
697197e5 MC |
1927 | static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db, |
1928 | u32 idx) | |
434c975a | 1929 | { |
697197e5 MC |
1930 | if (bp->flags & BNXT_FLAG_CHIP_P5) { |
1931 | writeq(db->db_key64 | idx, db->doorbell); | |
1932 | } else { | |
1933 | u32 db_val = db->db_key32 | idx; | |
1934 | ||
1935 | writel(db_val, db->doorbell); | |
1936 | if (bp->flags & BNXT_FLAG_DOUBLE_DB) | |
1937 | writel(db_val, db->doorbell); | |
1938 | } | |
434c975a MC |
1939 | } |
1940 | ||
760b6d33 VD |
1941 | static inline bool bnxt_cfa_hwrm_message(u16 req_type) |
1942 | { | |
1943 | switch (req_type) { | |
1944 | case HWRM_CFA_ENCAP_RECORD_ALLOC: | |
1945 | case HWRM_CFA_ENCAP_RECORD_FREE: | |
1946 | case HWRM_CFA_DECAP_FILTER_ALLOC: | |
1947 | case HWRM_CFA_DECAP_FILTER_FREE: | |
760b6d33 VD |
1948 | case HWRM_CFA_EM_FLOW_ALLOC: |
1949 | case HWRM_CFA_EM_FLOW_FREE: | |
1950 | case HWRM_CFA_EM_FLOW_CFG: | |
1951 | case HWRM_CFA_FLOW_ALLOC: | |
1952 | case HWRM_CFA_FLOW_FREE: | |
1953 | case HWRM_CFA_FLOW_INFO: | |
1954 | case HWRM_CFA_FLOW_FLUSH: | |
1955 | case HWRM_CFA_FLOW_STATS: | |
1956 | case HWRM_CFA_METER_PROFILE_ALLOC: | |
1957 | case HWRM_CFA_METER_PROFILE_FREE: | |
1958 | case HWRM_CFA_METER_PROFILE_CFG: | |
1959 | case HWRM_CFA_METER_INSTANCE_ALLOC: | |
1960 | case HWRM_CFA_METER_INSTANCE_FREE: | |
1961 | return true; | |
1962 | default: | |
1963 | return false; | |
1964 | } | |
1965 | } | |
1966 | ||
1967 | static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req) | |
1968 | { | |
1969 | return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL && | |
1970 | bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type))); | |
1971 | } | |
1972 | ||
1973 | static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req) | |
1974 | { | |
1975 | return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL && | |
1976 | req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr)); | |
1977 | } | |
1978 | ||
5c209fc8 VD |
1979 | static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req) |
1980 | { | |
760b6d33 VD |
1981 | if (bnxt_hwrm_kong_chnl(bp, (struct input *)req)) |
1982 | return bp->hwrm_cmd_kong_resp_addr; | |
1983 | else | |
1984 | return bp->hwrm_cmd_resp_addr; | |
5c209fc8 VD |
1985 | } |
1986 | ||
760b6d33 | 1987 | static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst) |
5c209fc8 VD |
1988 | { |
1989 | u16 seq_id; | |
1990 | ||
760b6d33 VD |
1991 | if (dst == BNXT_HWRM_CHNL_CHIMP) |
1992 | seq_id = bp->hwrm_cmd_seq++; | |
1993 | else | |
1994 | seq_id = bp->hwrm_cmd_kong_seq++; | |
5c209fc8 VD |
1995 | return seq_id; |
1996 | } | |
1997 | ||
38413406 MC |
1998 | extern const u16 bnxt_lhint_arr[]; |
1999 | ||
2000 | int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, | |
2001 | u16 prod, gfp_t gfp); | |
c6d30e83 | 2002 | void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); |
7e914027 | 2003 | u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx); |
c6d30e83 | 2004 | void bnxt_set_tpa_flags(struct bnxt *bp); |
c0c050c5 | 2005 | void bnxt_set_ring_params(struct bnxt *); |
c61fb99c | 2006 | int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); |
c0c050c5 MC |
2007 | void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16); |
2008 | int _hwrm_send_message(struct bnxt *, void *, u32, int); | |
cc72f3b1 | 2009 | int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout); |
c0c050c5 | 2010 | int hwrm_send_message(struct bnxt *, void *, u32, int); |
90e20921 | 2011 | int hwrm_send_message_silent(struct bnxt *, void *, u32, int); |
2e882468 VV |
2012 | int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, |
2013 | int bmap_size, bool async_only); | |
a588e458 | 2014 | int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id); |
391be5c2 | 2015 | int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings); |
b16b6891 | 2016 | int bnxt_nq_rings_in_use(struct bnxt *bp); |
c0c050c5 | 2017 | int bnxt_hwrm_set_coal(struct bnxt *); |
e4060d30 | 2018 | unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); |
c027c6b4 | 2019 | unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp); |
e4060d30 | 2020 | unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); |
e916b081 | 2021 | unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp); |
fbcfc8e4 | 2022 | int bnxt_get_avail_msix(struct bnxt *bp, int num); |
1b3f0b75 | 2023 | int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init); |
7df4ae9f MC |
2024 | void bnxt_tx_disable(struct bnxt *bp); |
2025 | void bnxt_tx_enable(struct bnxt *bp); | |
c0c050c5 | 2026 | int bnxt_hwrm_set_pause(struct bnxt *); |
939f7f0c | 2027 | int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); |
5282db6c MC |
2028 | int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp); |
2029 | int bnxt_hwrm_free_wol_fltr(struct bnxt *bp); | |
db4723b3 | 2030 | int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all); |
5ac67d8b | 2031 | int bnxt_hwrm_fw_set_time(struct bnxt *); |
c0c050c5 | 2032 | int bnxt_open_nic(struct bnxt *, bool, bool); |
f7dc1ea6 MC |
2033 | int bnxt_half_open_nic(struct bnxt *bp); |
2034 | void bnxt_half_close_nic(struct bnxt *bp); | |
c0c050c5 | 2035 | int bnxt_close_nic(struct bnxt *, bool, bool); |
d1db9e16 | 2036 | void bnxt_fw_exception(struct bnxt *bp); |
230d1f0d | 2037 | void bnxt_fw_reset(struct bnxt *bp); |
98fdbe73 MC |
2038 | int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, |
2039 | int tx_xdp); | |
c5e3deb8 | 2040 | int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); |
6e6c5a57 | 2041 | int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); |
80fcaf46 | 2042 | int bnxt_restore_pf_fw_resources(struct bnxt *bp); |
52d5254a FF |
2043 | int bnxt_get_port_parent_id(struct net_device *dev, |
2044 | struct netdev_phys_item_id *ppid); | |
6a8788f2 AG |
2045 | void bnxt_dim_work(struct work_struct *work); |
2046 | int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi); | |
2047 | ||
c0c050c5 | 2048 | #endif |