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c0c050c5 MC |
1 | /* Broadcom NetXtreme-C/E network driver. |
2 | * | |
11f15ed3 | 3 | * Copyright (c) 2014-2016 Broadcom Corporation |
c0c050c5 MC |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifndef BNXT_H | |
11 | #define BNXT_H | |
12 | ||
13 | #define DRV_MODULE_NAME "bnxt_en" | |
87c374de | 14 | #define DRV_MODULE_VERSION "1.6.0" |
c0c050c5 | 15 | |
c193554e | 16 | #define DRV_VER_MAJ 1 |
87c374de | 17 | #define DRV_VER_MIN 6 |
c193554e | 18 | #define DRV_VER_UPD 0 |
c0c050c5 MC |
19 | |
20 | struct tx_bd { | |
21 | __le32 tx_bd_len_flags_type; | |
22 | #define TX_BD_TYPE (0x3f << 0) | |
23 | #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) | |
24 | #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) | |
25 | #define TX_BD_FLAGS_PACKET_END (1 << 6) | |
26 | #define TX_BD_FLAGS_NO_CMPL (1 << 7) | |
27 | #define TX_BD_FLAGS_BD_CNT (0x1f << 8) | |
28 | #define TX_BD_FLAGS_BD_CNT_SHIFT 8 | |
29 | #define TX_BD_FLAGS_LHINT (3 << 13) | |
30 | #define TX_BD_FLAGS_LHINT_SHIFT 13 | |
31 | #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) | |
32 | #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) | |
33 | #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) | |
34 | #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) | |
35 | #define TX_BD_FLAGS_COAL_NOW (1 << 15) | |
36 | #define TX_BD_LEN (0xffff << 16) | |
37 | #define TX_BD_LEN_SHIFT 16 | |
38 | ||
39 | u32 tx_bd_opaque; | |
40 | __le64 tx_bd_haddr; | |
41 | } __packed; | |
42 | ||
43 | struct tx_bd_ext { | |
44 | __le32 tx_bd_hsize_lflags; | |
45 | #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) | |
46 | #define TX_BD_FLAGS_IP_CKSUM (1 << 1) | |
47 | #define TX_BD_FLAGS_NO_CRC (1 << 2) | |
48 | #define TX_BD_FLAGS_STAMP (1 << 3) | |
49 | #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) | |
50 | #define TX_BD_FLAGS_LSO (1 << 5) | |
51 | #define TX_BD_FLAGS_IPID_FMT (1 << 6) | |
52 | #define TX_BD_FLAGS_T_IPID (1 << 7) | |
53 | #define TX_BD_HSIZE (0xff << 16) | |
54 | #define TX_BD_HSIZE_SHIFT 16 | |
55 | ||
56 | __le32 tx_bd_mss; | |
57 | __le32 tx_bd_cfa_action; | |
58 | #define TX_BD_CFA_ACTION (0xffff << 16) | |
59 | #define TX_BD_CFA_ACTION_SHIFT 16 | |
60 | ||
61 | __le32 tx_bd_cfa_meta; | |
62 | #define TX_BD_CFA_META_MASK 0xfffffff | |
63 | #define TX_BD_CFA_META_VID_MASK 0xfff | |
64 | #define TX_BD_CFA_META_PRI_MASK (0xf << 12) | |
65 | #define TX_BD_CFA_META_PRI_SHIFT 12 | |
66 | #define TX_BD_CFA_META_TPID_MASK (3 << 16) | |
67 | #define TX_BD_CFA_META_TPID_SHIFT 16 | |
68 | #define TX_BD_CFA_META_KEY (0xf << 28) | |
69 | #define TX_BD_CFA_META_KEY_SHIFT 28 | |
70 | #define TX_BD_CFA_META_KEY_VLAN (1 << 28) | |
71 | }; | |
72 | ||
73 | struct rx_bd { | |
74 | __le32 rx_bd_len_flags_type; | |
75 | #define RX_BD_TYPE (0x3f << 0) | |
76 | #define RX_BD_TYPE_RX_PACKET_BD 0x4 | |
77 | #define RX_BD_TYPE_RX_BUFFER_BD 0x5 | |
78 | #define RX_BD_TYPE_RX_AGG_BD 0x6 | |
79 | #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) | |
80 | #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) | |
81 | #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) | |
82 | #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) | |
83 | #define RX_BD_FLAGS_SOP (1 << 6) | |
84 | #define RX_BD_FLAGS_EOP (1 << 7) | |
85 | #define RX_BD_FLAGS_BUFFERS (3 << 8) | |
86 | #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) | |
87 | #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) | |
88 | #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) | |
89 | #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) | |
90 | #define RX_BD_LEN (0xffff << 16) | |
91 | #define RX_BD_LEN_SHIFT 16 | |
92 | ||
93 | u32 rx_bd_opaque; | |
94 | __le64 rx_bd_haddr; | |
95 | }; | |
96 | ||
97 | struct tx_cmp { | |
98 | __le32 tx_cmp_flags_type; | |
99 | #define CMP_TYPE (0x3f << 0) | |
100 | #define CMP_TYPE_TX_L2_CMP 0 | |
101 | #define CMP_TYPE_RX_L2_CMP 17 | |
102 | #define CMP_TYPE_RX_AGG_CMP 18 | |
103 | #define CMP_TYPE_RX_L2_TPA_START_CMP 19 | |
104 | #define CMP_TYPE_RX_L2_TPA_END_CMP 21 | |
105 | #define CMP_TYPE_STATUS_CMP 32 | |
106 | #define CMP_TYPE_REMOTE_DRIVER_REQ 34 | |
107 | #define CMP_TYPE_REMOTE_DRIVER_RESP 36 | |
108 | #define CMP_TYPE_ERROR_STATUS 48 | |
441cabbb MC |
109 | #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL |
110 | #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL | |
111 | #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL | |
112 | #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL | |
113 | #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL | |
c0c050c5 MC |
114 | |
115 | #define TX_CMP_FLAGS_ERROR (1 << 6) | |
116 | #define TX_CMP_FLAGS_PUSH (1 << 7) | |
117 | ||
118 | u32 tx_cmp_opaque; | |
119 | __le32 tx_cmp_errors_v; | |
120 | #define TX_CMP_V (1 << 0) | |
121 | #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) | |
122 | #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 | |
123 | #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 | |
124 | #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 | |
125 | #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 | |
126 | #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) | |
127 | #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) | |
128 | #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) | |
129 | #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) | |
130 | ||
131 | __le32 tx_cmp_unsed_3; | |
132 | }; | |
133 | ||
134 | struct rx_cmp { | |
135 | __le32 rx_cmp_len_flags_type; | |
136 | #define RX_CMP_CMP_TYPE (0x3f << 0) | |
137 | #define RX_CMP_FLAGS_ERROR (1 << 6) | |
138 | #define RX_CMP_FLAGS_PLACEMENT (7 << 7) | |
139 | #define RX_CMP_FLAGS_RSS_VALID (1 << 10) | |
140 | #define RX_CMP_FLAGS_UNUSED (1 << 11) | |
141 | #define RX_CMP_FLAGS_ITYPES_SHIFT 12 | |
142 | #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) | |
143 | #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) | |
144 | #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) | |
145 | #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) | |
146 | #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) | |
147 | #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) | |
148 | #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) | |
149 | #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) | |
150 | #define RX_CMP_LEN (0xffff << 16) | |
151 | #define RX_CMP_LEN_SHIFT 16 | |
152 | ||
153 | u32 rx_cmp_opaque; | |
154 | __le32 rx_cmp_misc_v1; | |
155 | #define RX_CMP_V1 (1 << 0) | |
156 | #define RX_CMP_AGG_BUFS (0x1f << 1) | |
157 | #define RX_CMP_AGG_BUFS_SHIFT 1 | |
158 | #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) | |
159 | #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 | |
160 | #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) | |
161 | #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 | |
162 | ||
163 | __le32 rx_cmp_rss_hash; | |
164 | }; | |
165 | ||
166 | #define RX_CMP_HASH_VALID(rxcmp) \ | |
167 | ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) | |
168 | ||
614388ce MC |
169 | #define RSS_PROFILE_ID_MASK 0x1f |
170 | ||
c0c050c5 | 171 | #define RX_CMP_HASH_TYPE(rxcmp) \ |
614388ce MC |
172 | (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ |
173 | RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) | |
c0c050c5 MC |
174 | |
175 | struct rx_cmp_ext { | |
176 | __le32 rx_cmp_flags2; | |
177 | #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 | |
178 | #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) | |
179 | #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) | |
180 | #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) | |
181 | #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) | |
182 | __le32 rx_cmp_meta_data; | |
183 | #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff | |
184 | #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 | |
185 | #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 | |
186 | __le32 rx_cmp_cfa_code_errors_v2; | |
187 | #define RX_CMP_V (1 << 0) | |
188 | #define RX_CMPL_ERRORS_MASK (0x7fff << 1) | |
189 | #define RX_CMPL_ERRORS_SFT 1 | |
190 | #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) | |
191 | #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) | |
192 | #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) | |
193 | #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) | |
194 | #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) | |
195 | #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) | |
196 | #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) | |
197 | #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) | |
198 | #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) | |
199 | #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) | |
200 | #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) | |
201 | #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) | |
202 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) | |
203 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) | |
204 | #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) | |
205 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) | |
206 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) | |
207 | #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) | |
208 | #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) | |
209 | #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) | |
210 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) | |
211 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) | |
212 | #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) | |
213 | #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) | |
214 | #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) | |
215 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) | |
216 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) | |
217 | #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) | |
218 | ||
219 | #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) | |
220 | #define RX_CMPL_CFA_CODE_SFT 16 | |
221 | ||
222 | __le32 rx_cmp_unused3; | |
223 | }; | |
224 | ||
225 | #define RX_CMP_L2_ERRORS \ | |
226 | cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) | |
227 | ||
228 | #define RX_CMP_L4_CS_BITS \ | |
229 | (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) | |
230 | ||
231 | #define RX_CMP_L4_CS_ERR_BITS \ | |
232 | (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) | |
233 | ||
234 | #define RX_CMP_L4_CS_OK(rxcmp1) \ | |
235 | (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ | |
236 | !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) | |
237 | ||
238 | #define RX_CMP_ENCAP(rxcmp1) \ | |
239 | ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ | |
240 | RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) | |
241 | ||
242 | struct rx_agg_cmp { | |
243 | __le32 rx_agg_cmp_len_flags_type; | |
244 | #define RX_AGG_CMP_TYPE (0x3f << 0) | |
245 | #define RX_AGG_CMP_LEN (0xffff << 16) | |
246 | #define RX_AGG_CMP_LEN_SHIFT 16 | |
247 | u32 rx_agg_cmp_opaque; | |
248 | __le32 rx_agg_cmp_v; | |
249 | #define RX_AGG_CMP_V (1 << 0) | |
250 | __le32 rx_agg_cmp_unused; | |
251 | }; | |
252 | ||
253 | struct rx_tpa_start_cmp { | |
254 | __le32 rx_tpa_start_cmp_len_flags_type; | |
255 | #define RX_TPA_START_CMP_TYPE (0x3f << 0) | |
256 | #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) | |
257 | #define RX_TPA_START_CMP_FLAGS_SHIFT 6 | |
258 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) | |
259 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 | |
260 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) | |
261 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) | |
262 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) | |
263 | #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) | |
264 | #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) | |
265 | #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) | |
266 | #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 | |
267 | #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) | |
268 | #define RX_TPA_START_CMP_LEN (0xffff << 16) | |
269 | #define RX_TPA_START_CMP_LEN_SHIFT 16 | |
270 | ||
271 | u32 rx_tpa_start_cmp_opaque; | |
272 | __le32 rx_tpa_start_cmp_misc_v1; | |
273 | #define RX_TPA_START_CMP_V1 (0x1 << 0) | |
274 | #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) | |
275 | #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 | |
276 | #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) | |
277 | #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 | |
278 | ||
279 | __le32 rx_tpa_start_cmp_rss_hash; | |
280 | }; | |
281 | ||
282 | #define TPA_START_HASH_VALID(rx_tpa_start) \ | |
283 | ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ | |
284 | cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) | |
285 | ||
286 | #define TPA_START_HASH_TYPE(rx_tpa_start) \ | |
614388ce MC |
287 | (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ |
288 | RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ | |
289 | RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) | |
c0c050c5 MC |
290 | |
291 | #define TPA_START_AGG_ID(rx_tpa_start) \ | |
292 | ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ | |
293 | RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) | |
294 | ||
295 | struct rx_tpa_start_cmp_ext { | |
296 | __le32 rx_tpa_start_cmp_flags2; | |
297 | #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) | |
298 | #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) | |
299 | #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) | |
300 | #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) | |
94758f8d | 301 | #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) |
c0c050c5 MC |
302 | |
303 | __le32 rx_tpa_start_cmp_metadata; | |
304 | __le32 rx_tpa_start_cmp_cfa_code_v2; | |
305 | #define RX_TPA_START_CMP_V2 (0x1 << 0) | |
306 | #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) | |
307 | #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 | |
94758f8d | 308 | __le32 rx_tpa_start_cmp_hdr_info; |
c0c050c5 MC |
309 | }; |
310 | ||
311 | struct rx_tpa_end_cmp { | |
312 | __le32 rx_tpa_end_cmp_len_flags_type; | |
313 | #define RX_TPA_END_CMP_TYPE (0x3f << 0) | |
314 | #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) | |
315 | #define RX_TPA_END_CMP_FLAGS_SHIFT 6 | |
316 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) | |
317 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 | |
318 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) | |
319 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) | |
320 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) | |
321 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) | |
322 | #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) | |
323 | #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) | |
324 | #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 | |
325 | #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) | |
326 | #define RX_TPA_END_CMP_LEN (0xffff << 16) | |
327 | #define RX_TPA_END_CMP_LEN_SHIFT 16 | |
328 | ||
329 | u32 rx_tpa_end_cmp_opaque; | |
330 | __le32 rx_tpa_end_cmp_misc_v1; | |
331 | #define RX_TPA_END_CMP_V1 (0x1 << 0) | |
332 | #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) | |
333 | #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 | |
334 | #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) | |
335 | #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 | |
336 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) | |
337 | #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 | |
338 | #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) | |
339 | #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 | |
340 | ||
341 | __le32 rx_tpa_end_cmp_tsdelta; | |
342 | #define RX_TPA_END_GRO_TS (0x1 << 31) | |
343 | }; | |
344 | ||
345 | #define TPA_END_AGG_ID(rx_tpa_end) \ | |
346 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
347 | RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) | |
348 | ||
349 | #define TPA_END_TPA_SEGS(rx_tpa_end) \ | |
350 | ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ | |
351 | RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) | |
352 | ||
353 | #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ | |
354 | cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ | |
355 | RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) | |
356 | ||
357 | #define TPA_END_GRO(rx_tpa_end) \ | |
358 | ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ | |
359 | RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) | |
360 | ||
361 | #define TPA_END_GRO_TS(rx_tpa_end) \ | |
a58a3e68 MC |
362 | (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ |
363 | cpu_to_le32(RX_TPA_END_GRO_TS))) | |
c0c050c5 MC |
364 | |
365 | struct rx_tpa_end_cmp_ext { | |
366 | __le32 rx_tpa_end_cmp_dup_acks; | |
367 | #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) | |
368 | ||
369 | __le32 rx_tpa_end_cmp_seg_len; | |
370 | #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) | |
371 | ||
372 | __le32 rx_tpa_end_cmp_errors_v2; | |
373 | #define RX_TPA_END_CMP_V2 (0x1 << 0) | |
374 | #define RX_TPA_END_CMP_ERRORS (0x7fff << 1) | |
375 | #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 | |
376 | ||
377 | u32 rx_tpa_end_cmp_start_opaque; | |
378 | }; | |
379 | ||
380 | #define DB_IDX_MASK 0xffffff | |
381 | #define DB_IDX_VALID (0x1 << 26) | |
382 | #define DB_IRQ_DIS (0x1 << 27) | |
383 | #define DB_KEY_TX (0x0 << 28) | |
384 | #define DB_KEY_RX (0x1 << 28) | |
385 | #define DB_KEY_CP (0x2 << 28) | |
386 | #define DB_KEY_ST (0x3 << 28) | |
387 | #define DB_KEY_TX_PUSH (0x4 << 28) | |
388 | #define DB_LONG_TX_PUSH (0x2 << 24) | |
389 | ||
e4060d30 MC |
390 | #define BNXT_MIN_ROCE_CP_RINGS 2 |
391 | #define BNXT_MIN_ROCE_STAT_CTXS 1 | |
392 | ||
c0c050c5 MC |
393 | #define INVALID_HW_RING_ID ((u16)-1) |
394 | ||
c0c050c5 MC |
395 | /* The hardware supports certain page sizes. Use the supported page sizes |
396 | * to allocate the rings. | |
397 | */ | |
398 | #if (PAGE_SHIFT < 12) | |
399 | #define BNXT_PAGE_SHIFT 12 | |
400 | #elif (PAGE_SHIFT <= 13) | |
401 | #define BNXT_PAGE_SHIFT PAGE_SHIFT | |
402 | #elif (PAGE_SHIFT < 16) | |
403 | #define BNXT_PAGE_SHIFT 13 | |
404 | #else | |
405 | #define BNXT_PAGE_SHIFT 16 | |
406 | #endif | |
407 | ||
408 | #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) | |
409 | ||
2839f28b MC |
410 | /* The RXBD length is 16-bit so we can only support page sizes < 64K */ |
411 | #if (PAGE_SHIFT > 15) | |
412 | #define BNXT_RX_PAGE_SHIFT 15 | |
413 | #else | |
414 | #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT | |
415 | #endif | |
416 | ||
417 | #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) | |
418 | ||
4ffcd582 | 419 | #define BNXT_MIN_PKT_SIZE 52 |
c0c050c5 MC |
420 | |
421 | #define BNXT_NUM_TESTS(bp) 0 | |
422 | ||
51dd55b5 MC |
423 | #define BNXT_DEFAULT_RX_RING_SIZE 511 |
424 | #define BNXT_DEFAULT_TX_RING_SIZE 511 | |
c0c050c5 MC |
425 | |
426 | #define MAX_TPA 64 | |
427 | ||
d0a42d6f MC |
428 | #if (BNXT_PAGE_SHIFT == 16) |
429 | #define MAX_RX_PAGES 1 | |
430 | #define MAX_RX_AGG_PAGES 4 | |
431 | #define MAX_TX_PAGES 1 | |
432 | #define MAX_CP_PAGES 8 | |
433 | #else | |
c0c050c5 MC |
434 | #define MAX_RX_PAGES 8 |
435 | #define MAX_RX_AGG_PAGES 32 | |
436 | #define MAX_TX_PAGES 8 | |
437 | #define MAX_CP_PAGES 64 | |
d0a42d6f | 438 | #endif |
c0c050c5 MC |
439 | |
440 | #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) | |
441 | #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) | |
442 | #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) | |
443 | ||
444 | #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) | |
445 | #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) | |
446 | ||
447 | #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) | |
448 | ||
449 | #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) | |
450 | #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) | |
451 | ||
452 | #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) | |
453 | ||
454 | #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) | |
455 | #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) | |
456 | #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) | |
457 | ||
458 | #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
459 | #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) | |
460 | ||
461 | #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
462 | #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) | |
463 | ||
464 | #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) | |
465 | #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) | |
466 | ||
467 | #define TX_CMP_VALID(txcmp, raw_cons) \ | |
468 | (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ | |
469 | !((raw_cons) & bp->cp_bit)) | |
470 | ||
471 | #define RX_CMP_VALID(rxcmp1, raw_cons) \ | |
472 | (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ | |
473 | !((raw_cons) & bp->cp_bit)) | |
474 | ||
475 | #define RX_AGG_CMP_VALID(agg, raw_cons) \ | |
476 | (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ | |
477 | !((raw_cons) & bp->cp_bit)) | |
478 | ||
479 | #define TX_CMP_TYPE(txcmp) \ | |
480 | (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) | |
481 | ||
482 | #define RX_CMP_TYPE(rxcmp) \ | |
483 | (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) | |
484 | ||
485 | #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) | |
486 | ||
487 | #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) | |
488 | ||
489 | #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) | |
490 | ||
491 | #define ADV_RAW_CMP(idx, n) ((idx) + (n)) | |
492 | #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) | |
493 | #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) | |
494 | #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) | |
495 | ||
e6ef2699 | 496 | #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) |
ff4fe81d MC |
497 | #define DFLT_HWRM_CMD_TIMEOUT 500 |
498 | #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) | |
c0c050c5 MC |
499 | #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) |
500 | #define HWRM_RESP_ERR_CODE_MASK 0xffff | |
a8643e16 | 501 | #define HWRM_RESP_LEN_OFFSET 4 |
c0c050c5 MC |
502 | #define HWRM_RESP_LEN_MASK 0xffff0000 |
503 | #define HWRM_RESP_LEN_SFT 16 | |
504 | #define HWRM_RESP_VALID_MASK 0xff000000 | |
a8643e16 | 505 | #define HWRM_SEQ_ID_INVALID -1 |
c0c050c5 MC |
506 | #define BNXT_HWRM_REQ_MAX_SIZE 128 |
507 | #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \ | |
508 | BNXT_HWRM_REQ_MAX_SIZE) | |
509 | ||
510 | struct bnxt_sw_tx_bd { | |
511 | struct sk_buff *skb; | |
512 | DEFINE_DMA_UNMAP_ADDR(mapping); | |
513 | u8 is_gso; | |
514 | u8 is_push; | |
515 | unsigned short nr_frags; | |
516 | }; | |
517 | ||
518 | struct bnxt_sw_rx_bd { | |
519 | u8 *data; | |
520 | DEFINE_DMA_UNMAP_ADDR(mapping); | |
521 | }; | |
522 | ||
523 | struct bnxt_sw_rx_agg_bd { | |
524 | struct page *page; | |
89d0a06c | 525 | unsigned int offset; |
c0c050c5 MC |
526 | dma_addr_t mapping; |
527 | }; | |
528 | ||
529 | struct bnxt_ring_struct { | |
530 | int nr_pages; | |
531 | int page_size; | |
532 | void **pg_arr; | |
533 | dma_addr_t *dma_arr; | |
534 | ||
535 | __le64 *pg_tbl; | |
536 | dma_addr_t pg_tbl_map; | |
537 | ||
538 | int vmem_size; | |
539 | void **vmem; | |
540 | ||
541 | u16 fw_ring_id; /* Ring id filled by Chimp FW */ | |
542 | u8 queue_id; | |
543 | }; | |
544 | ||
545 | struct tx_push_bd { | |
546 | __le32 doorbell; | |
4419dbe6 MC |
547 | __le32 tx_bd_len_flags_type; |
548 | u32 tx_bd_opaque; | |
c0c050c5 MC |
549 | struct tx_bd_ext txbd2; |
550 | }; | |
551 | ||
4419dbe6 MC |
552 | struct tx_push_buffer { |
553 | struct tx_push_bd push_bd; | |
554 | u32 data[25]; | |
555 | }; | |
556 | ||
c0c050c5 | 557 | struct bnxt_tx_ring_info { |
b6ab4b01 | 558 | struct bnxt_napi *bnapi; |
c0c050c5 MC |
559 | u16 tx_prod; |
560 | u16 tx_cons; | |
561 | void __iomem *tx_doorbell; | |
562 | ||
563 | struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; | |
564 | struct bnxt_sw_tx_bd *tx_buf_ring; | |
565 | ||
566 | dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; | |
567 | ||
4419dbe6 | 568 | struct tx_push_buffer *tx_push; |
c0c050c5 | 569 | dma_addr_t tx_push_mapping; |
4419dbe6 | 570 | __le64 data_mapping; |
c0c050c5 MC |
571 | |
572 | #define BNXT_DEV_STATE_CLOSING 0x1 | |
573 | u32 dev_state; | |
574 | ||
575 | struct bnxt_ring_struct tx_ring_struct; | |
576 | }; | |
577 | ||
578 | struct bnxt_tpa_info { | |
579 | u8 *data; | |
580 | dma_addr_t mapping; | |
581 | u16 len; | |
582 | unsigned short gso_type; | |
583 | u32 flags2; | |
584 | u32 metadata; | |
585 | enum pkt_hash_types hash_type; | |
586 | u32 rss_hash; | |
94758f8d MC |
587 | u32 hdr_info; |
588 | ||
589 | #define BNXT_TPA_L4_SIZE(hdr_info) \ | |
590 | (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) | |
591 | ||
592 | #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ | |
593 | (((hdr_info) >> 18) & 0x1ff) | |
594 | ||
595 | #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ | |
596 | (((hdr_info) >> 9) & 0x1ff) | |
597 | ||
598 | #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ | |
599 | ((hdr_info) & 0x1ff) | |
c0c050c5 MC |
600 | }; |
601 | ||
602 | struct bnxt_rx_ring_info { | |
b6ab4b01 | 603 | struct bnxt_napi *bnapi; |
c0c050c5 MC |
604 | u16 rx_prod; |
605 | u16 rx_agg_prod; | |
606 | u16 rx_sw_agg_prod; | |
376a5b86 | 607 | u16 rx_next_cons; |
c0c050c5 MC |
608 | void __iomem *rx_doorbell; |
609 | void __iomem *rx_agg_doorbell; | |
610 | ||
611 | struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; | |
612 | struct bnxt_sw_rx_bd *rx_buf_ring; | |
613 | ||
614 | struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; | |
615 | struct bnxt_sw_rx_agg_bd *rx_agg_ring; | |
616 | ||
617 | unsigned long *rx_agg_bmap; | |
618 | u16 rx_agg_bmap_size; | |
619 | ||
89d0a06c MC |
620 | struct page *rx_page; |
621 | unsigned int rx_page_offset; | |
622 | ||
c0c050c5 MC |
623 | dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; |
624 | dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; | |
625 | ||
626 | struct bnxt_tpa_info *rx_tpa; | |
627 | ||
628 | struct bnxt_ring_struct rx_ring_struct; | |
629 | struct bnxt_ring_struct rx_agg_ring_struct; | |
630 | }; | |
631 | ||
632 | struct bnxt_cp_ring_info { | |
633 | u32 cp_raw_cons; | |
634 | void __iomem *cp_doorbell; | |
635 | ||
636 | struct tx_cmp *cp_desc_ring[MAX_CP_PAGES]; | |
637 | ||
638 | dma_addr_t cp_desc_mapping[MAX_CP_PAGES]; | |
639 | ||
640 | struct ctx_hw_stats *hw_stats; | |
641 | dma_addr_t hw_stats_map; | |
642 | u32 hw_stats_ctx_id; | |
643 | u64 rx_l4_csum_errors; | |
644 | ||
645 | struct bnxt_ring_struct cp_ring_struct; | |
646 | }; | |
647 | ||
648 | struct bnxt_napi { | |
649 | struct napi_struct napi; | |
650 | struct bnxt *bp; | |
651 | ||
652 | int index; | |
653 | struct bnxt_cp_ring_info cp_ring; | |
b6ab4b01 MC |
654 | struct bnxt_rx_ring_info *rx_ring; |
655 | struct bnxt_tx_ring_info *tx_ring; | |
c0c050c5 | 656 | |
fa7e2812 | 657 | bool in_reset; |
c0c050c5 MC |
658 | }; |
659 | ||
c0c050c5 MC |
660 | struct bnxt_irq { |
661 | irq_handler_t handler; | |
662 | unsigned int vector; | |
663 | u8 requested; | |
664 | char name[IFNAMSIZ + 2]; | |
665 | }; | |
666 | ||
667 | #define HWRM_RING_ALLOC_TX 0x1 | |
668 | #define HWRM_RING_ALLOC_RX 0x2 | |
669 | #define HWRM_RING_ALLOC_AGG 0x4 | |
670 | #define HWRM_RING_ALLOC_CMPL 0x8 | |
671 | ||
672 | #define INVALID_STATS_CTX_ID -1 | |
673 | ||
c0c050c5 MC |
674 | struct bnxt_ring_grp_info { |
675 | u16 fw_stats_ctx; | |
676 | u16 fw_grp_id; | |
677 | u16 rx_fw_ring_id; | |
678 | u16 agg_fw_ring_id; | |
679 | u16 cp_fw_ring_id; | |
680 | }; | |
681 | ||
682 | struct bnxt_vnic_info { | |
683 | u16 fw_vnic_id; /* returned by Chimp during alloc */ | |
94ce9caa PS |
684 | #define BNXT_MAX_CTX_PER_VNIC 2 |
685 | u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; | |
c0c050c5 MC |
686 | u16 fw_l2_ctx_id; |
687 | #define BNXT_MAX_UC_ADDRS 4 | |
688 | __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; | |
689 | /* index 0 always dev_addr */ | |
690 | u16 uc_filter_count; | |
691 | u8 *uc_list; | |
692 | ||
693 | u16 *fw_grp_ids; | |
c0c050c5 MC |
694 | dma_addr_t rss_table_dma_addr; |
695 | __le16 *rss_table; | |
696 | dma_addr_t rss_hash_key_dma_addr; | |
697 | u64 *rss_hash_key; | |
698 | u32 rx_mask; | |
699 | ||
700 | u8 *mc_list; | |
701 | int mc_list_size; | |
702 | int mc_list_count; | |
703 | dma_addr_t mc_list_mapping; | |
704 | #define BNXT_MAX_MC_ADDRS 16 | |
705 | ||
706 | u32 flags; | |
707 | #define BNXT_VNIC_RSS_FLAG 1 | |
708 | #define BNXT_VNIC_RFS_FLAG 2 | |
709 | #define BNXT_VNIC_MCAST_FLAG 4 | |
710 | #define BNXT_VNIC_UCAST_FLAG 8 | |
711 | }; | |
712 | ||
713 | #if defined(CONFIG_BNXT_SRIOV) | |
714 | struct bnxt_vf_info { | |
715 | u16 fw_fid; | |
716 | u8 mac_addr[ETH_ALEN]; | |
717 | u16 max_rsscos_ctxs; | |
718 | u16 max_cp_rings; | |
719 | u16 max_tx_rings; | |
720 | u16 max_rx_rings; | |
b72d4a68 | 721 | u16 max_hw_ring_grps; |
c0c050c5 MC |
722 | u16 max_l2_ctxs; |
723 | u16 max_irqs; | |
724 | u16 max_vnics; | |
725 | u16 max_stat_ctxs; | |
726 | u16 vlan; | |
727 | u32 flags; | |
728 | #define BNXT_VF_QOS 0x1 | |
729 | #define BNXT_VF_SPOOFCHK 0x2 | |
730 | #define BNXT_VF_LINK_FORCED 0x4 | |
731 | #define BNXT_VF_LINK_UP 0x8 | |
732 | u32 func_flags; /* func cfg flags */ | |
733 | u32 min_tx_rate; | |
734 | u32 max_tx_rate; | |
735 | void *hwrm_cmd_req_addr; | |
736 | dma_addr_t hwrm_cmd_req_dma_addr; | |
737 | }; | |
379a80a1 | 738 | #endif |
c0c050c5 MC |
739 | |
740 | struct bnxt_pf_info { | |
741 | #define BNXT_FIRST_PF_FID 1 | |
742 | #define BNXT_FIRST_VF_FID 128 | |
a58a3e68 MC |
743 | u16 fw_fid; |
744 | u16 port_id; | |
c0c050c5 MC |
745 | u8 mac_addr[ETH_ALEN]; |
746 | u16 max_rsscos_ctxs; | |
747 | u16 max_cp_rings; | |
748 | u16 max_tx_rings; /* HW assigned max tx rings for this PF */ | |
c0c050c5 | 749 | u16 max_rx_rings; /* HW assigned max rx rings for this PF */ |
b72d4a68 | 750 | u16 max_hw_ring_grps; |
c0c050c5 MC |
751 | u16 max_irqs; |
752 | u16 max_l2_ctxs; | |
753 | u16 max_vnics; | |
754 | u16 max_stat_ctxs; | |
755 | u32 first_vf_id; | |
756 | u16 active_vfs; | |
757 | u16 max_vfs; | |
758 | u32 max_encap_records; | |
759 | u32 max_decap_records; | |
760 | u32 max_tx_em_flows; | |
761 | u32 max_tx_wm_flows; | |
762 | u32 max_rx_em_flows; | |
763 | u32 max_rx_wm_flows; | |
764 | unsigned long *vf_event_bmap; | |
765 | u16 hwrm_cmd_req_pages; | |
766 | void *hwrm_cmd_req_addr[4]; | |
767 | dma_addr_t hwrm_cmd_req_dma_addr[4]; | |
768 | struct bnxt_vf_info *vf; | |
769 | }; | |
c0c050c5 MC |
770 | |
771 | struct bnxt_ntuple_filter { | |
772 | struct hlist_node hash; | |
a54c4d74 | 773 | u8 dst_mac_addr[ETH_ALEN]; |
c0c050c5 MC |
774 | u8 src_mac_addr[ETH_ALEN]; |
775 | struct flow_keys fkeys; | |
776 | __le64 filter_id; | |
777 | u16 sw_id; | |
a54c4d74 | 778 | u8 l2_fltr_idx; |
c0c050c5 MC |
779 | u16 rxq; |
780 | u32 flow_id; | |
781 | unsigned long state; | |
782 | #define BNXT_FLTR_VALID 0 | |
783 | #define BNXT_FLTR_UPDATE 1 | |
784 | }; | |
785 | ||
c0c050c5 | 786 | struct bnxt_link_info { |
03efbec0 | 787 | u8 phy_type; |
c0c050c5 MC |
788 | u8 media_type; |
789 | u8 transceiver; | |
790 | u8 phy_addr; | |
791 | u8 phy_link_status; | |
792 | #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK | |
793 | #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL | |
794 | #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK | |
795 | u8 wire_speed; | |
796 | u8 loop_back; | |
797 | u8 link_up; | |
798 | u8 duplex; | |
799 | #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_HALF | |
800 | #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_FULL | |
801 | u8 pause; | |
802 | #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX | |
803 | #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX | |
804 | #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ | |
805 | PORT_PHY_QCFG_RESP_PAUSE_TX) | |
3277360e | 806 | u8 lp_pause; |
c0c050c5 MC |
807 | u8 auto_pause_setting; |
808 | u8 force_pause_setting; | |
809 | u8 duplex_setting; | |
810 | u8 auto_mode; | |
811 | #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ | |
812 | (mode) <= BNXT_LINK_AUTO_MSK) | |
813 | #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE | |
814 | #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS | |
815 | #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED | |
816 | #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW | |
11f15ed3 | 817 | #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK |
c0c050c5 MC |
818 | #define PHY_VER_LEN 3 |
819 | u8 phy_ver[PHY_VER_LEN]; | |
820 | u16 link_speed; | |
821 | #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB | |
822 | #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB | |
823 | #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB | |
824 | #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB | |
825 | #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB | |
826 | #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB | |
827 | #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB | |
828 | #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB | |
829 | #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB | |
830 | u16 support_speeds; | |
68515a18 | 831 | u16 auto_link_speeds; /* fw adv setting */ |
c0c050c5 MC |
832 | #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB |
833 | #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB | |
834 | #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB | |
835 | #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB | |
836 | #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB | |
837 | #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB | |
838 | #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB | |
839 | #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB | |
840 | #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB | |
93ed8117 | 841 | u16 support_auto_speeds; |
3277360e | 842 | u16 lp_auto_link_speeds; |
c0c050c5 MC |
843 | u16 force_link_speed; |
844 | u32 preemphasis; | |
42ee18fe | 845 | u8 module_status; |
c0c050c5 MC |
846 | |
847 | /* copy of requested setting from ethtool cmd */ | |
848 | u8 autoneg; | |
849 | #define BNXT_AUTONEG_SPEED 1 | |
850 | #define BNXT_AUTONEG_FLOW_CTRL 2 | |
851 | u8 req_duplex; | |
852 | u8 req_flow_ctrl; | |
853 | u16 req_link_speed; | |
68515a18 | 854 | u16 advertising; /* user adv setting */ |
c0c050c5 | 855 | bool force_link_chng; |
4bb13abf | 856 | |
c0c050c5 MC |
857 | /* a copy of phy_qcfg output used to report link |
858 | * info to VF | |
859 | */ | |
860 | struct hwrm_port_phy_qcfg_output phy_qcfg_resp; | |
861 | }; | |
862 | ||
863 | #define BNXT_MAX_QUEUE 8 | |
864 | ||
865 | struct bnxt_queue_info { | |
866 | u8 queue_id; | |
867 | u8 queue_profile; | |
868 | }; | |
869 | ||
11809490 JH |
870 | #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 |
871 | #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 | |
872 | #define BNXT_CAG_REG_BASE 0x300000 | |
873 | ||
c0c050c5 MC |
874 | struct bnxt { |
875 | void __iomem *bar0; | |
876 | void __iomem *bar1; | |
877 | void __iomem *bar2; | |
878 | ||
879 | u32 reg_base; | |
659c805c MC |
880 | u16 chip_num; |
881 | #define CHIP_NUM_57301 0x16c8 | |
882 | #define CHIP_NUM_57302 0x16c9 | |
883 | #define CHIP_NUM_57304 0x16ca | |
3e8060fa | 884 | #define CHIP_NUM_58700 0x16cd |
659c805c MC |
885 | #define CHIP_NUM_57402 0x16d0 |
886 | #define CHIP_NUM_57404 0x16d1 | |
887 | #define CHIP_NUM_57406 0x16d2 | |
888 | ||
889 | #define CHIP_NUM_57311 0x16ce | |
890 | #define CHIP_NUM_57312 0x16cf | |
891 | #define CHIP_NUM_57314 0x16df | |
892 | #define CHIP_NUM_57412 0x16d6 | |
893 | #define CHIP_NUM_57414 0x16d7 | |
894 | #define CHIP_NUM_57416 0x16d8 | |
895 | #define CHIP_NUM_57417 0x16d9 | |
896 | ||
897 | #define BNXT_CHIP_NUM_5730X(chip_num) \ | |
898 | ((chip_num) >= CHIP_NUM_57301 && \ | |
899 | (chip_num) <= CHIP_NUM_57304) | |
900 | ||
901 | #define BNXT_CHIP_NUM_5740X(chip_num) \ | |
902 | ((chip_num) >= CHIP_NUM_57402 && \ | |
903 | (chip_num) <= CHIP_NUM_57406) | |
904 | ||
905 | #define BNXT_CHIP_NUM_5731X(chip_num) \ | |
906 | ((chip_num) == CHIP_NUM_57311 || \ | |
907 | (chip_num) == CHIP_NUM_57312 || \ | |
908 | (chip_num) == CHIP_NUM_57314) | |
909 | ||
910 | #define BNXT_CHIP_NUM_5741X(chip_num) \ | |
911 | ((chip_num) >= CHIP_NUM_57412 && \ | |
912 | (chip_num) <= CHIP_NUM_57417) | |
913 | ||
914 | #define BNXT_CHIP_NUM_57X0X(chip_num) \ | |
915 | (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) | |
916 | ||
917 | #define BNXT_CHIP_NUM_57X1X(chip_num) \ | |
918 | (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) | |
c0c050c5 MC |
919 | |
920 | struct net_device *dev; | |
921 | struct pci_dev *pdev; | |
922 | ||
923 | atomic_t intr_sem; | |
924 | ||
925 | u32 flags; | |
926 | #define BNXT_FLAG_DCB_ENABLED 0x1 | |
927 | #define BNXT_FLAG_VF 0x2 | |
928 | #define BNXT_FLAG_LRO 0x4 | |
d1611c3a | 929 | #ifdef CONFIG_INET |
c0c050c5 | 930 | #define BNXT_FLAG_GRO 0x8 |
d1611c3a MC |
931 | #else |
932 | /* Cannot support hardware GRO if CONFIG_INET is not set */ | |
933 | #define BNXT_FLAG_GRO 0x0 | |
934 | #endif | |
c0c050c5 MC |
935 | #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) |
936 | #define BNXT_FLAG_JUMBO 0x10 | |
937 | #define BNXT_FLAG_STRIP_VLAN 0x20 | |
938 | #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ | |
939 | BNXT_FLAG_LRO) | |
940 | #define BNXT_FLAG_USING_MSIX 0x40 | |
941 | #define BNXT_FLAG_MSIX_CAP 0x80 | |
942 | #define BNXT_FLAG_RFS 0x100 | |
6e6c5a57 | 943 | #define BNXT_FLAG_SHARED_RINGS 0x200 |
3bdf56c4 | 944 | #define BNXT_FLAG_PORT_STATS 0x400 |
87da7f79 | 945 | #define BNXT_FLAG_UDP_RSS_CAP 0x800 |
170ce013 | 946 | #define BNXT_FLAG_EEE_CAP 0x1000 |
8fdefd63 | 947 | #define BNXT_FLAG_NEW_RSS_CAP 0x2000 |
e4060d30 MC |
948 | #define BNXT_FLAG_ROCEV1_CAP 0x8000 |
949 | #define BNXT_FLAG_ROCEV2_CAP 0x10000 | |
950 | #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \ | |
951 | BNXT_FLAG_ROCEV2_CAP) | |
3e8060fa | 952 | #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 |
6e6c5a57 | 953 | |
c0c050c5 MC |
954 | #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ |
955 | BNXT_FLAG_RFS | \ | |
956 | BNXT_FLAG_STRIP_VLAN) | |
957 | ||
958 | #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) | |
959 | #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) | |
567b2abe SB |
960 | #define BNXT_NPAR(bp) ((bp)->port_partition_type) |
961 | #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp)) | |
3e8060fa | 962 | #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) |
c0c050c5 | 963 | |
a588e458 MC |
964 | struct bnxt_en_dev *edev; |
965 | struct bnxt_en_dev * (*ulp_probe)(struct net_device *); | |
966 | ||
c0c050c5 MC |
967 | struct bnxt_napi **bnapi; |
968 | ||
b6ab4b01 MC |
969 | struct bnxt_rx_ring_info *rx_ring; |
970 | struct bnxt_tx_ring_info *tx_ring; | |
971 | ||
309369c9 MC |
972 | struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, |
973 | struct sk_buff *); | |
974 | ||
c0c050c5 MC |
975 | u32 rx_buf_size; |
976 | u32 rx_buf_use_size; /* useable size */ | |
977 | u32 rx_ring_size; | |
978 | u32 rx_agg_ring_size; | |
979 | u32 rx_copy_thresh; | |
980 | u32 rx_ring_mask; | |
981 | u32 rx_agg_ring_mask; | |
982 | int rx_nr_pages; | |
983 | int rx_agg_nr_pages; | |
984 | int rx_nr_rings; | |
985 | int rsscos_nr_ctxs; | |
986 | ||
987 | u32 tx_ring_size; | |
988 | u32 tx_ring_mask; | |
989 | int tx_nr_pages; | |
990 | int tx_nr_rings; | |
991 | int tx_nr_rings_per_tc; | |
992 | ||
993 | int tx_wake_thresh; | |
994 | int tx_push_thresh; | |
995 | int tx_push_size; | |
996 | ||
997 | u32 cp_ring_size; | |
998 | u32 cp_ring_mask; | |
999 | u32 cp_bit; | |
1000 | int cp_nr_pages; | |
1001 | int cp_nr_rings; | |
1002 | ||
1003 | int num_stat_ctxs; | |
b81a90d3 MC |
1004 | |
1005 | /* grp_info indexed by completion ring index */ | |
c0c050c5 MC |
1006 | struct bnxt_ring_grp_info *grp_info; |
1007 | struct bnxt_vnic_info *vnic_info; | |
1008 | int nr_vnics; | |
87da7f79 | 1009 | u32 rss_hash_cfg; |
c0c050c5 MC |
1010 | |
1011 | u8 max_tc; | |
87c374de | 1012 | u8 max_lltc; /* lossless TCs */ |
c0c050c5 MC |
1013 | struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; |
1014 | ||
1015 | unsigned int current_interval; | |
3bdf56c4 | 1016 | #define BNXT_TIMER_INTERVAL HZ |
c0c050c5 MC |
1017 | |
1018 | struct timer_list timer; | |
1019 | ||
caefe526 MC |
1020 | unsigned long state; |
1021 | #define BNXT_STATE_OPEN 0 | |
4cebdcec | 1022 | #define BNXT_STATE_IN_SP_TASK 1 |
c0c050c5 MC |
1023 | |
1024 | struct bnxt_irq *irq_tbl; | |
7809592d | 1025 | int total_irqs; |
c0c050c5 MC |
1026 | u8 mac_addr[ETH_ALEN]; |
1027 | ||
7df4ae9f MC |
1028 | #ifdef CONFIG_BNXT_DCB |
1029 | struct ieee_pfc *ieee_pfc; | |
1030 | struct ieee_ets *ieee_ets; | |
1031 | u8 dcbx_cap; | |
1032 | u8 default_pri; | |
1033 | #endif /* CONFIG_BNXT_DCB */ | |
1034 | ||
c0c050c5 MC |
1035 | u32 msg_enable; |
1036 | ||
11f15ed3 | 1037 | u32 hwrm_spec_code; |
c0c050c5 MC |
1038 | u16 hwrm_cmd_seq; |
1039 | u32 hwrm_intr_seq_id; | |
1040 | void *hwrm_cmd_resp_addr; | |
1041 | dma_addr_t hwrm_cmd_resp_dma_addr; | |
1042 | void *hwrm_dbg_resp_addr; | |
1043 | dma_addr_t hwrm_dbg_resp_dma_addr; | |
1044 | #define HWRM_DBG_REG_BUF_SIZE 128 | |
3bdf56c4 MC |
1045 | |
1046 | struct rx_port_stats *hw_rx_port_stats; | |
1047 | struct tx_port_stats *hw_tx_port_stats; | |
1048 | dma_addr_t hw_rx_port_stats_map; | |
1049 | dma_addr_t hw_tx_port_stats_map; | |
1050 | int hw_port_stats_size; | |
1051 | ||
e6ef2699 | 1052 | u16 hwrm_max_req_len; |
ff4fe81d | 1053 | int hwrm_cmd_timeout; |
c0c050c5 MC |
1054 | struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ |
1055 | struct hwrm_ver_get_output ver_resp; | |
1056 | #define FW_VER_STR_LEN 32 | |
1057 | #define BC_HWRM_STR_LEN 21 | |
1058 | #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) | |
1059 | char fw_ver_str[FW_VER_STR_LEN]; | |
1060 | __be16 vxlan_port; | |
1061 | u8 vxlan_port_cnt; | |
1062 | __le16 vxlan_fw_dst_port_id; | |
7cdd5fc3 | 1063 | __be16 nge_port; |
c0c050c5 MC |
1064 | u8 nge_port_cnt; |
1065 | __le16 nge_fw_dst_port_id; | |
567b2abe | 1066 | u8 port_partition_type; |
dfc9c94a | 1067 | |
dfb5b894 MC |
1068 | u16 rx_coal_ticks; |
1069 | u16 rx_coal_ticks_irq; | |
1070 | u16 rx_coal_bufs; | |
1071 | u16 rx_coal_bufs_irq; | |
dfc9c94a MC |
1072 | u16 tx_coal_ticks; |
1073 | u16 tx_coal_ticks_irq; | |
1074 | u16 tx_coal_bufs; | |
1075 | u16 tx_coal_bufs_irq; | |
c0c050c5 MC |
1076 | |
1077 | #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) | |
c0c050c5 | 1078 | |
51f30785 MC |
1079 | u32 stats_coal_ticks; |
1080 | #define BNXT_DEF_STATS_COAL_TICKS 1000000 | |
1081 | #define BNXT_MIN_STATS_COAL_TICKS 250000 | |
1082 | #define BNXT_MAX_STATS_COAL_TICKS 1000000 | |
1083 | ||
c0c050c5 MC |
1084 | struct work_struct sp_task; |
1085 | unsigned long sp_event; | |
1086 | #define BNXT_RX_MASK_SP_EVENT 0 | |
1087 | #define BNXT_RX_NTP_FLTR_SP_EVENT 1 | |
1088 | #define BNXT_LINK_CHNG_SP_EVENT 2 | |
c5d7774d JH |
1089 | #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 |
1090 | #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 | |
1091 | #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 | |
1092 | #define BNXT_RESET_TASK_SP_EVENT 6 | |
1093 | #define BNXT_RST_RING_SP_EVENT 7 | |
19241368 | 1094 | #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 |
3bdf56c4 | 1095 | #define BNXT_PERIODIC_STATS_SP_EVENT 9 |
4bb13abf | 1096 | #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 |
fc0f1929 | 1097 | #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 |
7cdd5fc3 AD |
1098 | #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 |
1099 | #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 | |
286ef9d6 | 1100 | #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 |
c0c050c5 | 1101 | |
379a80a1 | 1102 | struct bnxt_pf_info pf; |
c0c050c5 MC |
1103 | #ifdef CONFIG_BNXT_SRIOV |
1104 | int nr_vfs; | |
c0c050c5 MC |
1105 | struct bnxt_vf_info vf; |
1106 | wait_queue_head_t sriov_cfg_wait; | |
1107 | bool sriov_cfg; | |
1108 | #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) | |
1109 | #endif | |
1110 | ||
1111 | #define BNXT_NTP_FLTR_MAX_FLTR 4096 | |
1112 | #define BNXT_NTP_FLTR_HASH_SIZE 512 | |
1113 | #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) | |
1114 | struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; | |
1115 | spinlock_t ntp_fltr_lock; /* for hash table add, del */ | |
1116 | ||
1117 | unsigned long *ntp_fltr_bmap; | |
1118 | int ntp_fltr_count; | |
1119 | ||
1120 | struct bnxt_link_info link_info; | |
170ce013 MC |
1121 | struct ethtool_eee eee; |
1122 | u32 lpi_tmr_lo; | |
1123 | u32 lpi_tmr_hi; | |
c0c050c5 MC |
1124 | }; |
1125 | ||
c77192f2 MC |
1126 | #define BNXT_RX_STATS_OFFSET(counter) \ |
1127 | (offsetof(struct rx_port_stats, counter) / 8) | |
1128 | ||
1129 | #define BNXT_TX_STATS_OFFSET(counter) \ | |
1130 | ((offsetof(struct tx_port_stats, counter) + \ | |
1131 | sizeof(struct rx_port_stats) + 512) / 8) | |
1132 | ||
42ee18fe AK |
1133 | #define I2C_DEV_ADDR_A0 0xa0 |
1134 | #define I2C_DEV_ADDR_A2 0xa2 | |
1135 | #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e | |
1136 | #define SFP_EEPROM_SFF_8472_COMP_SIZE 1 | |
1137 | #define SFF_MODULE_ID_SFP 0x3 | |
1138 | #define SFF_MODULE_ID_QSFP 0xc | |
1139 | #define SFF_MODULE_ID_QSFP_PLUS 0xd | |
1140 | #define SFF_MODULE_ID_QSFP28 0x11 | |
1141 | #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 | |
1142 | ||
c0c050c5 MC |
1143 | void bnxt_set_ring_params(struct bnxt *); |
1144 | void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16); | |
1145 | int _hwrm_send_message(struct bnxt *, void *, u32, int); | |
1146 | int hwrm_send_message(struct bnxt *, void *, u32, int); | |
90e20921 | 1147 | int hwrm_send_message_silent(struct bnxt *, void *, u32, int); |
a1653b13 MC |
1148 | int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, |
1149 | int bmap_size); | |
a588e458 | 1150 | int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id); |
c0c050c5 | 1151 | int bnxt_hwrm_set_coal(struct bnxt *); |
e4060d30 | 1152 | unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); |
a588e458 | 1153 | void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max); |
e4060d30 | 1154 | unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); |
a588e458 | 1155 | void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max); |
33c2657e | 1156 | void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max); |
7df4ae9f MC |
1157 | void bnxt_tx_disable(struct bnxt *bp); |
1158 | void bnxt_tx_enable(struct bnxt *bp); | |
c0c050c5 | 1159 | int bnxt_hwrm_set_pause(struct bnxt *); |
939f7f0c | 1160 | int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); |
5ac67d8b | 1161 | int bnxt_hwrm_fw_set_time(struct bnxt *); |
c0c050c5 MC |
1162 | int bnxt_open_nic(struct bnxt *, bool, bool); |
1163 | int bnxt_close_nic(struct bnxt *, bool, bool); | |
c5e3deb8 | 1164 | int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); |
6e6c5a57 | 1165 | int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); |
7b08f661 | 1166 | void bnxt_restore_pf_fw_resources(struct bnxt *bp); |
c0c050c5 | 1167 | #endif |