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Merge tag 'x86-fpu-2020-06-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
[thirdparty/linux.git] / drivers / net / ethernet / broadcom / bnxt / bnxt_ethtool.c
CommitLineData
c0c050c5
MC		 1/* Broadcom NetXtreme-C/E network driver.
2 *
11f15ed3 3 * Copyright (c) 2014-2016 Broadcom Corporation
8e202366 4 * Copyright (c) 2016-2017 Broadcom Limited
c0c050c5
MC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
3ebf6f0a 11#include <linux/ctype.h>
8ddc9aaa 12#include <linux/stringify.h>
c0c050c5
MC		 13#include <linux/ethtool.h>
14#include <linux/interrupt.h>
15#include <linux/pci.h>
16#include <linux/etherdevice.h>
17#include <linux/crc32.h>
18#include <linux/firmware.h>
6c5657d0
VV		 19#include <linux/utsname.h>
20#include <linux/time.h>
c0c050c5
MC		 21#include "bnxt_hsi.h"
22#include "bnxt.h"
f7dc1ea6 23#include "bnxt_xdp.h"
c0c050c5
MC		 24#include "bnxt_ethtool.h"
25#include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
26#include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
6c5657d0 27#include "bnxt_coredump.h"
c0c050c5 28#define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100)
5ac67d8b
RS		 29#define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
30#define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
c0c050c5
MC		 31
32static u32 bnxt_get_msglevel(struct net_device *dev)
33{
34 struct bnxt *bp = netdev_priv(dev);
35
36 return bp->msg_enable;
37}
38
39static void bnxt_set_msglevel(struct net_device *dev, u32 value)
40{
41 struct bnxt *bp = netdev_priv(dev);
42
43 bp->msg_enable = value;
44}
45
46static int bnxt_get_coalesce(struct net_device *dev,
47 struct ethtool_coalesce *coal)
48{
49 struct bnxt *bp = netdev_priv(dev);
18775aa8
MC		 50 struct bnxt_coal *hw_coal;
51 u16 mult;
c0c050c5
MC		 52
53 memset(coal, 0, sizeof(*coal));
54
6a8788f2
AG		 55 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
56
18775aa8
MC		 57 hw_coal = &bp->rx_coal;
58 mult = hw_coal->bufs_per_record;
59 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
60 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
61 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
62 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
c0c050c5 63
18775aa8
MC		 64 hw_coal = &bp->tx_coal;
65 mult = hw_coal->bufs_per_record;
66 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
67 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
68 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
69 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
dfc9c94a 70
51f30785
MC		 71 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
72
c0c050c5
MC		 73 return 0;
74}
75
76static int bnxt_set_coalesce(struct net_device *dev,
77 struct ethtool_coalesce *coal)
78{
79 struct bnxt *bp = netdev_priv(dev);
51f30785 80 bool update_stats = false;
18775aa8 81 struct bnxt_coal *hw_coal;
c0c050c5 82 int rc = 0;
18775aa8
MC		 83 u16 mult;
84
6a8788f2
AG		 85 if (coal->use_adaptive_rx_coalesce) {
86 bp->flags |= BNXT_FLAG_DIM;
87 } else {
88 if (bp->flags & BNXT_FLAG_DIM) {
89 bp->flags &= ~(BNXT_FLAG_DIM);
90 goto reset_coalesce;
91 }
92 }
93
18775aa8
MC		 94 hw_coal = &bp->rx_coal;
95 mult = hw_coal->bufs_per_record;
96 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
97 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
98 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
99 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
100
de4a10ef 101 hw_coal = &bp->tx_coal;
18775aa8
MC		 102 mult = hw_coal->bufs_per_record;
103 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
104 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
105 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
106 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
dfc9c94a 107
51f30785
MC		 108 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
109 u32 stats_ticks = coal->stats_block_coalesce_usecs;
110
adcc331e
MC		 111 /* Allow 0, which means disable. */
112 if (stats_ticks)
113 stats_ticks = clamp_t(u32, stats_ticks,
114 BNXT_MIN_STATS_COAL_TICKS,
115 BNXT_MAX_STATS_COAL_TICKS);
51f30785
MC		 116 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
117 bp->stats_coal_ticks = stats_ticks;
e795892e
MC		 118 if (bp->stats_coal_ticks)
119 bp->current_interval =
120 bp->stats_coal_ticks * HZ / 1000000;
121 else
122 bp->current_interval = BNXT_TIMER_INTERVAL;
51f30785
MC		 123 update_stats = true;
124 }
125
6a8788f2 126reset_coalesce:
51f30785
MC		 127 if (netif_running(dev)) {
128 if (update_stats) {
129 rc = bnxt_close_nic(bp, true, false);
130 if (!rc)
131 rc = bnxt_open_nic(bp, true, false);
132 } else {
133 rc = bnxt_hwrm_set_coal(bp);
134 }
135 }
c0c050c5
MC		 136
137 return rc;
138}
139
ee79566e
MC		 140static const char * const bnxt_ring_stats_str[] = {
141 "rx_ucast_packets",
142 "rx_mcast_packets",
143 "rx_bcast_packets",
144 "rx_discards",
145 "rx_drops",
146 "rx_ucast_bytes",
147 "rx_mcast_bytes",
148 "rx_bcast_bytes",
149 "tx_ucast_packets",
150 "tx_mcast_packets",
151 "tx_bcast_packets",
152 "tx_discards",
153 "tx_drops",
154 "tx_ucast_bytes",
155 "tx_mcast_bytes",
156 "tx_bcast_bytes",
157};
158
159static const char * const bnxt_ring_tpa_stats_str[] = {
160 "tpa_packets",
161 "tpa_bytes",
162 "tpa_events",
163 "tpa_aborts",
164};
165
78e7b866
MC		 166static const char * const bnxt_ring_tpa2_stats_str[] = {
167 "rx_tpa_eligible_pkt",
168 "rx_tpa_eligible_bytes",
169 "rx_tpa_pkt",
170 "rx_tpa_bytes",
171 "rx_tpa_errors",
172};
173
ee79566e
MC		 174static const char * const bnxt_ring_sw_stats_str[] = {
175 "rx_l4_csum_errors",
19b3751f 176 "rx_buf_errors",
ee79566e
MC		 177 "missed_irqs",
178};
c0c050c5 179
8ddc9aaa
MC		 180#define BNXT_RX_STATS_ENTRY(counter) \
181 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
182
8ddc9aaa
MC		 183#define BNXT_TX_STATS_ENTRY(counter) \
184 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
185
00db3cba
VV		 186#define BNXT_RX_STATS_EXT_ENTRY(counter) \
187 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
188
36e53349
MC		 189#define BNXT_TX_STATS_EXT_ENTRY(counter) \
190 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
191
192#define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
193 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
194 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
195
196#define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
197 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
198 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
199
200#define BNXT_RX_STATS_EXT_PFC_ENTRIES \
201 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
202 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
203 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
204 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
205 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
206 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
207 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
208 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
209
210#define BNXT_TX_STATS_EXT_PFC_ENTRIES \
211 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
212 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
213 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
214 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
215 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
216 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
217 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
218 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
219
220#define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
221 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
222 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
223
224#define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
225 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
226 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
227
228#define BNXT_RX_STATS_EXT_COS_ENTRIES \
229 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
230 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
231 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
232 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
233 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
234 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
235 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
236 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
237
238#define BNXT_TX_STATS_EXT_COS_ENTRIES \
239 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
240 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
241 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
242 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
243 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
244 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
245 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
246 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
247
2792b5b9
MC		 248#define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
249 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
250 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
251
252#define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
253 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
254 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
255 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
256 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
257 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
258 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
259 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
260 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
261
e37fed79
MC		 262#define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
263 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
264 __stringify(counter##_pri##n) }
265
266#define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
267 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
268 __stringify(counter##_pri##n) }
269
270#define BNXT_RX_STATS_PRI_ENTRIES(counter) \
271 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
272 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
273 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
274 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
275 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
276 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
277 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
278 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
279
280#define BNXT_TX_STATS_PRI_ENTRIES(counter) \
281 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
282 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
283 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
284 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
285 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
286 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
287 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
288 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
289
55e4398d
VV		 290#define BNXT_PCIE_STATS_ENTRY(counter) \
291 { BNXT_PCIE_STATS_OFFSET(counter), __stringify(counter) }
292
20c1d28e
VV		 293enum {
294 RX_TOTAL_DISCARDS,
295 TX_TOTAL_DISCARDS,
296};
297
298static struct {
299 u64 counter;
300 char string[ETH_GSTRING_LEN];
301} bnxt_sw_func_stats[] = {
302 {0, "rx_total_discard_pkts"},
303 {0, "tx_total_discard_pkts"},
304};
305
8ddc9aaa
MC		 306static const struct {
307 long offset;
308 char string[ETH_GSTRING_LEN];
309} bnxt_port_stats_arr[] = {
310 BNXT_RX_STATS_ENTRY(rx_64b_frames),
311 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
312 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
313 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
314 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
6fc92c33 315 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
8ddc9aaa
MC		 316 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
317 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
318 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
319 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
320 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
321 BNXT_RX_STATS_ENTRY(rx_total_frames),
322 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
323 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
324 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
325 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
326 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
327 BNXT_RX_STATS_ENTRY(rx_pause_frames),
328 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
329 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
330 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
331 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
332 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
333 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
334 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
335 BNXT_RX_STATS_ENTRY(rx_good_frames),
c77192f2
MC		 336 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
337 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
338 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
339 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
340 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
341 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
342 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
343 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
8ddc9aaa
MC		 344 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
345 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
346 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
347 BNXT_RX_STATS_ENTRY(rx_bytes),
348 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
349 BNXT_RX_STATS_ENTRY(rx_runt_frames),
699efed0
VV		 350 BNXT_RX_STATS_ENTRY(rx_stat_discard),
351 BNXT_RX_STATS_ENTRY(rx_stat_err),
8ddc9aaa
MC		 352
353 BNXT_TX_STATS_ENTRY(tx_64b_frames),
354 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
355 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
356 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
357 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
6fc92c33 358 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
8ddc9aaa 359 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
6fc92c33 360 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
8ddc9aaa
MC		 361 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
362 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
363 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
364 BNXT_TX_STATS_ENTRY(tx_good_frames),
365 BNXT_TX_STATS_ENTRY(tx_total_frames),
366 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
367 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
368 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
369 BNXT_TX_STATS_ENTRY(tx_pause_frames),
370 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
371 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
372 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
373 BNXT_TX_STATS_ENTRY(tx_err),
374 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
c77192f2
MC		 375 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
376 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
377 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
378 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
379 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
380 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
381 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
382 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
8ddc9aaa
MC		 383 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
384 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
385 BNXT_TX_STATS_ENTRY(tx_total_collisions),
386 BNXT_TX_STATS_ENTRY(tx_bytes),
699efed0
VV		 387 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
388 BNXT_TX_STATS_ENTRY(tx_stat_discard),
389 BNXT_TX_STATS_ENTRY(tx_stat_error),
8ddc9aaa
MC		 390};
391
00db3cba
VV		 392static const struct {
393 long offset;
394 char string[ETH_GSTRING_LEN];
395} bnxt_port_stats_ext_arr[] = {
396 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
397 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
398 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
399 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
400 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
36e53349
MC		 401 BNXT_RX_STATS_EXT_COS_ENTRIES,
402 BNXT_RX_STATS_EXT_PFC_ENTRIES,
4a50ddc2
MC		 403 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
404 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
405 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
406 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
2792b5b9 407 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
36e53349
MC		 408};
409
410static const struct {
411 long offset;
412 char string[ETH_GSTRING_LEN];
413} bnxt_tx_port_stats_ext_arr[] = {
414 BNXT_TX_STATS_EXT_COS_ENTRIES,
415 BNXT_TX_STATS_EXT_PFC_ENTRIES,
00db3cba
VV		 416};
417
e37fed79
MC		 418static const struct {
419 long base_off;
420 char string[ETH_GSTRING_LEN];
421} bnxt_rx_bytes_pri_arr[] = {
422 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
423};
424
425static const struct {
426 long base_off;
427 char string[ETH_GSTRING_LEN];
428} bnxt_rx_pkts_pri_arr[] = {
429 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
430};
431
432static const struct {
433 long base_off;
434 char string[ETH_GSTRING_LEN];
435} bnxt_tx_bytes_pri_arr[] = {
436 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
437};
438
439static const struct {
440 long base_off;
441 char string[ETH_GSTRING_LEN];
442} bnxt_tx_pkts_pri_arr[] = {
443 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
444};
445
55e4398d
VV		 446static const struct {
447 long offset;
448 char string[ETH_GSTRING_LEN];
449} bnxt_pcie_stats_arr[] = {
450 BNXT_PCIE_STATS_ENTRY(pcie_pl_signal_integrity),
451 BNXT_PCIE_STATS_ENTRY(pcie_dl_signal_integrity),
452 BNXT_PCIE_STATS_ENTRY(pcie_tl_signal_integrity),
453 BNXT_PCIE_STATS_ENTRY(pcie_link_integrity),
454 BNXT_PCIE_STATS_ENTRY(pcie_tx_traffic_rate),
455 BNXT_PCIE_STATS_ENTRY(pcie_rx_traffic_rate),
456 BNXT_PCIE_STATS_ENTRY(pcie_tx_dllp_statistics),
457 BNXT_PCIE_STATS_ENTRY(pcie_rx_dllp_statistics),
458 BNXT_PCIE_STATS_ENTRY(pcie_equalization_time),
459 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[0]),
460 BNXT_PCIE_STATS_ENTRY(pcie_ltssm_histogram[2]),
461 BNXT_PCIE_STATS_ENTRY(pcie_recovery_histogram),
462};
463
20c1d28e 464#define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats)
8ddc9aaa 465#define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
e37fed79
MC		 466#define BNXT_NUM_STATS_PRI \
467 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
468 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
469 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
470 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
55e4398d 471#define BNXT_NUM_PCIE_STATS ARRAY_SIZE(bnxt_pcie_stats_arr)
8ddc9aaa 472
78e7b866
MC		 473static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
474{
475 if (BNXT_SUPPORTS_TPA(bp)) {
476 if (bp->max_tpa_v2)
477 return ARRAY_SIZE(bnxt_ring_tpa2_stats_str);
478 return ARRAY_SIZE(bnxt_ring_tpa_stats_str);
479 }
480 return 0;
481}
482
ee79566e
MC		 483static int bnxt_get_num_ring_stats(struct bnxt *bp)
484{
485 int num_stats;
486
487 num_stats = ARRAY_SIZE(bnxt_ring_stats_str) +
78e7b866
MC		 488 ARRAY_SIZE(bnxt_ring_sw_stats_str) +
489 bnxt_get_num_tpa_ring_stats(bp);
ee79566e
MC		 490 return num_stats * bp->cp_nr_rings;
491}
492
5c8227d0
MC		 493static int bnxt_get_num_stats(struct bnxt *bp)
494{
ee79566e 495 int num_stats = bnxt_get_num_ring_stats(bp);
5c8227d0 496
20c1d28e
VV		 497 num_stats += BNXT_NUM_SW_FUNC_STATS;
498
5c8227d0
MC		 499 if (bp->flags & BNXT_FLAG_PORT_STATS)
500 num_stats += BNXT_NUM_PORT_STATS;
501
e37fed79 502 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
36e53349
MC		 503 num_stats += bp->fw_rx_stats_ext_size +
504 bp->fw_tx_stats_ext_size;
e37fed79
MC		 505 if (bp->pri2cos_valid)
506 num_stats += BNXT_NUM_STATS_PRI;
507 }
00db3cba 508
55e4398d
VV		 509 if (bp->flags & BNXT_FLAG_PCIE_STATS)
510 num_stats += BNXT_NUM_PCIE_STATS;
511
5c8227d0
MC		 512 return num_stats;
513}
514
c0c050c5
MC		 515static int bnxt_get_sset_count(struct net_device *dev, int sset)
516{
517 struct bnxt *bp = netdev_priv(dev);
518
519 switch (sset) {
5c8227d0
MC		 520 case ETH_SS_STATS:
521 return bnxt_get_num_stats(bp);
eb513658
MC		 522 case ETH_SS_TEST:
523 if (!bp->num_tests)
524 return -EOPNOTSUPP;
525 return bp->num_tests;
c0c050c5
MC		 526 default:
527 return -EOPNOTSUPP;
528 }
529}
530
531static void bnxt_get_ethtool_stats(struct net_device *dev,
532 struct ethtool_stats *stats, u64 *buf)
533{
534 u32 i, j = 0;
535 struct bnxt *bp = netdev_priv(dev);
78e7b866
MC		 536 u32 stat_fields = ARRAY_SIZE(bnxt_ring_stats_str) +
537 bnxt_get_num_tpa_ring_stats(bp);
c0c050c5 538
fd3ab1c7 539 if (!bp->bnapi) {
ee79566e 540 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS;
fd3ab1c7
MC		 541 goto skip_ring_stats;
542 }
c0c050c5 543
20c1d28e
VV		 544 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++)
545 bnxt_sw_func_stats[i].counter = 0;
546
c0c050c5
MC		 547 for (i = 0; i < bp->cp_nr_rings; i++) {
548 struct bnxt_napi *bnapi = bp->bnapi[i];
549 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
550 __le64 *hw_stats = (__le64 *)cpr->hw_stats;
551 int k;
552
553 for (k = 0; k < stat_fields; j++, k++)
554 buf[j] = le64_to_cpu(hw_stats[k]);
555 buf[j++] = cpr->rx_l4_csum_errors;
19b3751f 556 buf[j++] = cpr->rx_buf_errors;
83eb5c5c 557 buf[j++] = cpr->missed_irqs;
20c1d28e
VV		 558
559 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter +=
560 le64_to_cpu(cpr->hw_stats->rx_discard_pkts);
561 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter +=
562 le64_to_cpu(cpr->hw_stats->tx_discard_pkts);
c0c050c5 563 }
20c1d28e
VV		 564
565 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++)
566 buf[j] = bnxt_sw_func_stats[i].counter;
567
fd3ab1c7 568skip_ring_stats:
8ddc9aaa
MC		 569 if (bp->flags & BNXT_FLAG_PORT_STATS) {
570 __le64 *port_stats = (__le64 *)bp->hw_rx_port_stats;
571
572 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++) {
573 buf[j] = le64_to_cpu(*(port_stats +
574 bnxt_port_stats_arr[i].offset));
575 }
576 }
00db3cba 577 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
36e53349
MC		 578 __le64 *rx_port_stats_ext = (__le64 *)bp->hw_rx_port_stats_ext;
579 __le64 *tx_port_stats_ext = (__le64 *)bp->hw_tx_port_stats_ext;
00db3cba 580
36e53349
MC		 581 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) {
582 buf[j] = le64_to_cpu(*(rx_port_stats_ext +
00db3cba
VV		 583 bnxt_port_stats_ext_arr[i].offset));
584 }
36e53349
MC		 585 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) {
586 buf[j] = le64_to_cpu(*(tx_port_stats_ext +
587 bnxt_tx_port_stats_ext_arr[i].offset));
588 }
e37fed79
MC		 589 if (bp->pri2cos_valid) {
590 for (i = 0; i < 8; i++, j++) {
591 long n = bnxt_rx_bytes_pri_arr[i].base_off +
a24ec322 592 bp->pri2cos_idx[i];
e37fed79
MC		 593
594 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n));
595 }
596 for (i = 0; i < 8; i++, j++) {
597 long n = bnxt_rx_pkts_pri_arr[i].base_off +
a24ec322 598 bp->pri2cos_idx[i];
e37fed79
MC		 599
600 buf[j] = le64_to_cpu(*(rx_port_stats_ext + n));
601 }
602 for (i = 0; i < 8; i++, j++) {
603 long n = bnxt_tx_bytes_pri_arr[i].base_off +
a24ec322 604 bp->pri2cos_idx[i];
e37fed79
MC		 605
606 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n));
607 }
608 for (i = 0; i < 8; i++, j++) {
609 long n = bnxt_tx_pkts_pri_arr[i].base_off +
a24ec322 610 bp->pri2cos_idx[i];
e37fed79
MC		 611
612 buf[j] = le64_to_cpu(*(tx_port_stats_ext + n));
613 }
614 }
00db3cba 615 }
55e4398d
VV		 616 if (bp->flags & BNXT_FLAG_PCIE_STATS) {
617 __le64 *pcie_stats = (__le64 *)bp->hw_pcie_stats;
618
619 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++, j++) {
620 buf[j] = le64_to_cpu(*(pcie_stats +
621 bnxt_pcie_stats_arr[i].offset));
622 }
623 }
c0c050c5
MC		 624}
625
626static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
627{
628 struct bnxt *bp = netdev_priv(dev);
78e7b866 629 static const char * const *str;
ee79566e 630 u32 i, j, num_str;
c0c050c5
MC		 631
632 switch (stringset) {
c0c050c5
MC		 633 case ETH_SS_STATS:
634 for (i = 0; i < bp->cp_nr_rings; i++) {
ee79566e
MC		 635 num_str = ARRAY_SIZE(bnxt_ring_stats_str);
636 for (j = 0; j < num_str; j++) {
637 sprintf(buf, "[%d]: %s", i,
638 bnxt_ring_stats_str[j]);
639 buf += ETH_GSTRING_LEN;
640 }
641 if (!BNXT_SUPPORTS_TPA(bp))
642 goto skip_tpa_stats;
643
78e7b866
MC		 644 if (bp->max_tpa_v2) {
645 num_str = ARRAY_SIZE(bnxt_ring_tpa2_stats_str);
646 str = bnxt_ring_tpa2_stats_str;
647 } else {
648 num_str = ARRAY_SIZE(bnxt_ring_tpa_stats_str);
649 str = bnxt_ring_tpa_stats_str;
650 }
ee79566e 651 for (j = 0; j < num_str; j++) {
78e7b866 652 sprintf(buf, "[%d]: %s", i, str[j]);
ee79566e
MC		 653 buf += ETH_GSTRING_LEN;
654 }
655skip_tpa_stats:
656 num_str = ARRAY_SIZE(bnxt_ring_sw_stats_str);
657 for (j = 0; j < num_str; j++) {
658 sprintf(buf, "[%d]: %s", i,
659 bnxt_ring_sw_stats_str[j]);
660 buf += ETH_GSTRING_LEN;
661 }
c0c050c5 662 }
20c1d28e
VV		 663 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) {
664 strcpy(buf, bnxt_sw_func_stats[i].string);
665 buf += ETH_GSTRING_LEN;
666 }
667
8ddc9aaa
MC		 668 if (bp->flags & BNXT_FLAG_PORT_STATS) {
669 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
670 strcpy(buf, bnxt_port_stats_arr[i].string);
671 buf += ETH_GSTRING_LEN;
672 }
673 }
00db3cba 674 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
36e53349 675 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) {
00db3cba
VV		 676 strcpy(buf, bnxt_port_stats_ext_arr[i].string);
677 buf += ETH_GSTRING_LEN;
678 }
36e53349
MC		 679 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) {
680 strcpy(buf,
681 bnxt_tx_port_stats_ext_arr[i].string);
682 buf += ETH_GSTRING_LEN;
683 }
e37fed79
MC		 684 if (bp->pri2cos_valid) {
685 for (i = 0; i < 8; i++) {
686 strcpy(buf,
687 bnxt_rx_bytes_pri_arr[i].string);
688 buf += ETH_GSTRING_LEN;
689 }
690 for (i = 0; i < 8; i++) {
691 strcpy(buf,
692 bnxt_rx_pkts_pri_arr[i].string);
693 buf += ETH_GSTRING_LEN;
694 }
695 for (i = 0; i < 8; i++) {
696 strcpy(buf,
697 bnxt_tx_bytes_pri_arr[i].string);
698 buf += ETH_GSTRING_LEN;
699 }
700 for (i = 0; i < 8; i++) {
701 strcpy(buf,
702 bnxt_tx_pkts_pri_arr[i].string);
703 buf += ETH_GSTRING_LEN;
704 }
705 }
00db3cba 706 }
55e4398d
VV		 707 if (bp->flags & BNXT_FLAG_PCIE_STATS) {
708 for (i = 0; i < BNXT_NUM_PCIE_STATS; i++) {
709 strcpy(buf, bnxt_pcie_stats_arr[i].string);
710 buf += ETH_GSTRING_LEN;
711 }
712 }
c0c050c5 713 break;
eb513658
MC		 714 case ETH_SS_TEST:
715 if (bp->num_tests)
716 memcpy(buf, bp->test_info->string,
717 bp->num_tests * ETH_GSTRING_LEN);
718 break;
c0c050c5
MC		 719 default:
720 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
721 stringset);
722 break;
723 }
724}
725
726static void bnxt_get_ringparam(struct net_device *dev,
727 struct ethtool_ringparam *ering)
728{
729 struct bnxt *bp = netdev_priv(dev);
730
731 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
732 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
733 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
734
735 ering->rx_pending = bp->rx_ring_size;
736 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
737 ering->tx_pending = bp->tx_ring_size;
738}
739
740static int bnxt_set_ringparam(struct net_device *dev,
741 struct ethtool_ringparam *ering)
742{
743 struct bnxt *bp = netdev_priv(dev);
744
745 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
746 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
747 (ering->tx_pending <= MAX_SKB_FRAGS))
748 return -EINVAL;
749
750 if (netif_running(dev))
751 bnxt_close_nic(bp, false, false);
752
753 bp->rx_ring_size = ering->rx_pending;
754 bp->tx_ring_size = ering->tx_pending;
755 bnxt_set_ring_params(bp);
756
757 if (netif_running(dev))
758 return bnxt_open_nic(bp, false, false);
759
760 return 0;
761}
762
763static void bnxt_get_channels(struct net_device *dev,
764 struct ethtool_channels *channel)
765{
766 struct bnxt *bp = netdev_priv(dev);
db4723b3 767 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
c0c050c5 768 int max_rx_rings, max_tx_rings, tcs;
db4723b3
MC		 769 int max_tx_sch_inputs;
770
771 /* Get the most up-to-date max_tx_sch_inputs. */
f1ca94de 772 if (BNXT_NEW_RM(bp))
db4723b3
MC		 773 bnxt_hwrm_func_resc_qcaps(bp, false);
774 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
c0c050c5 775
6e6c5a57 776 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
db4723b3
MC		 777 if (max_tx_sch_inputs)
778 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
a79a5276 779 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
068c9ec6 780
18d6e4e2
SB		 781 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
782 max_rx_rings = 0;
783 max_tx_rings = 0;
784 }
db4723b3
MC		 785 if (max_tx_sch_inputs)
786 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
18d6e4e2 787
c0c050c5
MC		 788 tcs = netdev_get_num_tc(dev);
789 if (tcs > 1)
790 max_tx_rings /= tcs;
791
792 channel->max_rx = max_rx_rings;
793 channel->max_tx = max_tx_rings;
794 channel->max_other = 0;
068c9ec6
MC		 795 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
796 channel->combined_count = bp->rx_nr_rings;
76595193
PS		 797 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
798 channel->combined_count--;
068c9ec6 799 } else {
76595193
PS		 800 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
801 channel->rx_count = bp->rx_nr_rings;
802 channel->tx_count = bp->tx_nr_rings_per_tc;
803 }
068c9ec6 804 }
c0c050c5
MC		 805}
806
807static int bnxt_set_channels(struct net_device *dev,
808 struct ethtool_channels *channel)
809{
810 struct bnxt *bp = netdev_priv(dev);
d1e7925e 811 int req_tx_rings, req_rx_rings, tcs;
068c9ec6 812 bool sh = false;
5f449249 813 int tx_xdp = 0;
d1e7925e 814 int rc = 0;
c0c050c5 815
068c9ec6 816 if (channel->other_count)
c0c050c5
MC		 817 return -EINVAL;
818
068c9ec6
MC		 819 if (!channel->combined_count &&
820 (!channel->rx_count || !channel->tx_count))
821 return -EINVAL;
822
823 if (channel->combined_count &&
824 (channel->rx_count || channel->tx_count))
825 return -EINVAL;
826
76595193
PS		 827 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
828 channel->tx_count))
829 return -EINVAL;
830
068c9ec6
MC		 831 if (channel->combined_count)
832 sh = true;
833
c0c050c5 834 tcs = netdev_get_num_tc(dev);
c0c050c5 835
391be5c2 836 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
d1e7925e 837 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
5f449249
MC		 838 if (bp->tx_nr_rings_xdp) {
839 if (!sh) {
840 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
841 return -EINVAL;
842 }
843 tx_xdp = req_rx_rings;
844 }
98fdbe73 845 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
d1e7925e
MC		 846 if (rc) {
847 netdev_warn(dev, "Unable to allocate the requested rings\n");
848 return rc;
391be5c2
MC		 849 }
850
c0c050c5
MC		 851 if (netif_running(dev)) {
852 if (BNXT_PF(bp)) {
853 /* TODO CHIMP_FW: Send message to all VF's
854 * before PF unload
855 */
856 }
857 rc = bnxt_close_nic(bp, true, false);
858 if (rc) {
859 netdev_err(bp->dev, "Set channel failure rc :%x\n",
860 rc);
861 return rc;
862 }
863 }
864
068c9ec6
MC		 865 if (sh) {
866 bp->flags |= BNXT_FLAG_SHARED_RINGS;
d1e7925e
MC		 867 bp->rx_nr_rings = channel->combined_count;
868 bp->tx_nr_rings_per_tc = channel->combined_count;
068c9ec6
MC		 869 } else {
870 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
871 bp->rx_nr_rings = channel->rx_count;
872 bp->tx_nr_rings_per_tc = channel->tx_count;
873 }
5f449249
MC		 874 bp->tx_nr_rings_xdp = tx_xdp;
875 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
c0c050c5 876 if (tcs > 1)
5f449249 877 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
068c9ec6
MC		 878
879 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
880 bp->tx_nr_rings + bp->rx_nr_rings;
881
2bcfa6f6
MC		 882 /* After changing number of rx channels, update NTUPLE feature. */
883 netdev_update_features(dev);
c0c050c5
MC		 884 if (netif_running(dev)) {
885 rc = bnxt_open_nic(bp, true, false);
886 if ((!rc) && BNXT_PF(bp)) {
887 /* TODO CHIMP_FW: Send message to all VF's
888 * to renable
889 */
890 }
d8c09f19 891 } else {
1b3f0b75 892 rc = bnxt_reserve_rings(bp, true);
c0c050c5
MC		 893 }
894
895 return rc;
896}
897
898#ifdef CONFIG_RFS_ACCEL
899static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
900 u32 *rule_locs)
901{
902 int i, j = 0;
903
904 cmd->data = bp->ntp_fltr_count;
905 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
906 struct hlist_head *head;
907 struct bnxt_ntuple_filter *fltr;
908
909 head = &bp->ntp_fltr_hash_tbl[i];
910 rcu_read_lock();
911 hlist_for_each_entry_rcu(fltr, head, hash) {
912 if (j == cmd->rule_cnt)
913 break;
914 rule_locs[j++] = fltr->sw_id;
915 }
916 rcu_read_unlock();
917 if (j == cmd->rule_cnt)
918 break;
919 }
920 cmd->rule_cnt = j;
921 return 0;
922}
923
924static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
925{
926 struct ethtool_rx_flow_spec *fs =
927 (struct ethtool_rx_flow_spec *)&cmd->fs;
928 struct bnxt_ntuple_filter *fltr;
929 struct flow_keys *fkeys;
930 int i, rc = -EINVAL;
931
b721cfaf 932 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
c0c050c5
MC		 933 return rc;
934
935 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
936 struct hlist_head *head;
937
938 head = &bp->ntp_fltr_hash_tbl[i];
939 rcu_read_lock();
940 hlist_for_each_entry_rcu(fltr, head, hash) {
941 if (fltr->sw_id == fs->location)
942 goto fltr_found;
943 }
944 rcu_read_unlock();
945 }
946 return rc;
947
948fltr_found:
949 fkeys = &fltr->fkeys;
dda0e746
MC		 950 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
951 if (fkeys->basic.ip_proto == IPPROTO_TCP)
952 fs->flow_type = TCP_V4_FLOW;
953 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
954 fs->flow_type = UDP_V4_FLOW;
955 else
956 goto fltr_err;
c0c050c5 957
dda0e746
MC		 958 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
959 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
c0c050c5 960
dda0e746
MC		 961 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
962 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
c0c050c5 963
dda0e746
MC		 964 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
965 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
c0c050c5 966
dda0e746
MC		 967 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
968 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
969 } else {
970 int i;
971
972 if (fkeys->basic.ip_proto == IPPROTO_TCP)
973 fs->flow_type = TCP_V6_FLOW;
974 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
975 fs->flow_type = UDP_V6_FLOW;
976 else
977 goto fltr_err;
978
979 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
980 fkeys->addrs.v6addrs.src;
981 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
982 fkeys->addrs.v6addrs.dst;
983 for (i = 0; i < 4; i++) {
984 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0);
985 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0);
986 }
987 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
988 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);
989
990 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
991 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);
992 }
c0c050c5
MC		 993
994 fs->ring_cookie = fltr->rxq;
995 rc = 0;
996
997fltr_err:
998 rcu_read_unlock();
999
1000 return rc;
1001}
a011952a
MC		 1002#endif
1003
1004static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1005{
1006 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1007 return RXH_IP_SRC | RXH_IP_DST;
1008 return 0;
1009}
1010
1011static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1012{
1013 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1014 return RXH_IP_SRC | RXH_IP_DST;
1015 return 0;
1016}
1017
1018static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1019{
1020 cmd->data = 0;
1021 switch (cmd->flow_type) {
1022 case TCP_V4_FLOW:
1023 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1024 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1025 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1026 cmd->data |= get_ethtool_ipv4_rss(bp);
1027 break;
1028 case UDP_V4_FLOW:
1029 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1030 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1031 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1032 /* fall through */
1033 case SCTP_V4_FLOW:
1034 case AH_ESP_V4_FLOW:
1035 case AH_V4_FLOW:
1036 case ESP_V4_FLOW:
1037 case IPV4_FLOW:
1038 cmd->data |= get_ethtool_ipv4_rss(bp);
1039 break;
1040
1041 case TCP_V6_FLOW:
1042 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1043 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1044 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1045 cmd->data |= get_ethtool_ipv6_rss(bp);
1046 break;
1047 case UDP_V6_FLOW:
1048 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1049 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1050 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1051 /* fall through */
1052 case SCTP_V6_FLOW:
1053 case AH_ESP_V6_FLOW:
1054 case AH_V6_FLOW:
1055 case ESP_V6_FLOW:
1056 case IPV6_FLOW:
1057 cmd->data |= get_ethtool_ipv6_rss(bp);
1058 break;
1059 }
1060 return 0;
1061}
1062
1063#define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1064#define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1065
1066static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1067{
1068 u32 rss_hash_cfg = bp->rss_hash_cfg;
1069 int tuple, rc = 0;
1070
1071 if (cmd->data == RXH_4TUPLE)
1072 tuple = 4;
1073 else if (cmd->data == RXH_2TUPLE)
1074 tuple = 2;
1075 else if (!cmd->data)
1076 tuple = 0;
1077 else
1078 return -EINVAL;
1079
1080 if (cmd->flow_type == TCP_V4_FLOW) {
1081 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1082 if (tuple == 4)
1083 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1084 } else if (cmd->flow_type == UDP_V4_FLOW) {
1085 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1086 return -EINVAL;
1087 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1088 if (tuple == 4)
1089 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1090 } else if (cmd->flow_type == TCP_V6_FLOW) {
1091 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1092 if (tuple == 4)
1093 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1094 } else if (cmd->flow_type == UDP_V6_FLOW) {
1095 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1096 return -EINVAL;
1097 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1098 if (tuple == 4)
1099 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1100 } else if (tuple == 4) {
1101 return -EINVAL;
1102 }
1103
1104 switch (cmd->flow_type) {
1105 case TCP_V4_FLOW:
1106 case UDP_V4_FLOW:
1107 case SCTP_V4_FLOW:
1108 case AH_ESP_V4_FLOW:
1109 case AH_V4_FLOW:
1110 case ESP_V4_FLOW:
1111 case IPV4_FLOW:
1112 if (tuple == 2)
1113 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1114 else if (!tuple)
1115 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1116 break;
1117
1118 case TCP_V6_FLOW:
1119 case UDP_V6_FLOW:
1120 case SCTP_V6_FLOW:
1121 case AH_ESP_V6_FLOW:
1122 case AH_V6_FLOW:
1123 case ESP_V6_FLOW:
1124 case IPV6_FLOW:
1125 if (tuple == 2)
1126 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1127 else if (!tuple)
1128 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1129 break;
1130 }
1131
1132 if (bp->rss_hash_cfg == rss_hash_cfg)
1133 return 0;
1134
1135 bp->rss_hash_cfg = rss_hash_cfg;
1136 if (netif_running(bp->dev)) {
1137 bnxt_close_nic(bp, false, false);
1138 rc = bnxt_open_nic(bp, false, false);
1139 }
1140 return rc;
1141}
c0c050c5
MC		 1142
1143static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1144 u32 *rule_locs)
1145{
1146 struct bnxt *bp = netdev_priv(dev);
1147 int rc = 0;
1148
1149 switch (cmd->cmd) {
a011952a 1150#ifdef CONFIG_RFS_ACCEL
c0c050c5
MC		 1151 case ETHTOOL_GRXRINGS:
1152 cmd->data = bp->rx_nr_rings;
1153 break;
1154
1155 case ETHTOOL_GRXCLSRLCNT:
1156 cmd->rule_cnt = bp->ntp_fltr_count;
1157 cmd->data = BNXT_NTP_FLTR_MAX_FLTR;
1158 break;
1159
1160 case ETHTOOL_GRXCLSRLALL:
1161 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1162 break;
1163
1164 case ETHTOOL_GRXCLSRULE:
1165 rc = bnxt_grxclsrule(bp, cmd);
1166 break;
a011952a
MC		 1167#endif
1168
1169 case ETHTOOL_GRXFH:
1170 rc = bnxt_grxfh(bp, cmd);
1171 break;
c0c050c5
MC		 1172
1173 default:
1174 rc = -EOPNOTSUPP;
1175 break;
1176 }
1177
1178 return rc;
1179}
a011952a
MC		 1180
1181static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1182{
1183 struct bnxt *bp = netdev_priv(dev);
1184 int rc;
1185
1186 switch (cmd->cmd) {
1187 case ETHTOOL_SRXFH:
1188 rc = bnxt_srxfh(bp, cmd);
1189 break;
1190
1191 default:
1192 rc = -EOPNOTSUPP;
1193 break;
1194 }
1195 return rc;
1196}
c0c050c5
MC		 1197
1198static u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1199{
1200 return HW_HASH_INDEX_SIZE;
1201}
1202
1203static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1204{
1205 return HW_HASH_KEY_SIZE;
1206}
1207
1208static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1209 u8 *hfunc)
1210{
1211 struct bnxt *bp = netdev_priv(dev);
7991cb9c 1212 struct bnxt_vnic_info *vnic;
c0c050c5
MC		 1213 int i = 0;
1214
1215 if (hfunc)
1216 *hfunc = ETH_RSS_HASH_TOP;
1217
7991cb9c
MC		 1218 if (!bp->vnic_info)
1219 return 0;
1220
1221 vnic = &bp->vnic_info[0];
1222 if (indir && vnic->rss_table) {
c0c050c5
MC		 1223 for (i = 0; i < HW_HASH_INDEX_SIZE; i++)
1224 indir[i] = le16_to_cpu(vnic->rss_table[i]);
7991cb9c 1225 }
c0c050c5 1226
7991cb9c 1227 if (key && vnic->rss_hash_key)
c0c050c5
MC		 1228 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1229
1230 return 0;
1231}
1232
1233static void bnxt_get_drvinfo(struct net_device *dev,
1234 struct ethtool_drvinfo *info)
1235{
1236 struct bnxt *bp = netdev_priv(dev);
1237
1238 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
431aa1eb 1239 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
c0c050c5 1240 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
5c8227d0 1241 info->n_stats = bnxt_get_num_stats(bp);
eb513658 1242 info->testinfo_len = bp->num_tests;
c0c050c5
MC		 1243 /* TODO CHIMP_FW: eeprom dump details */
1244 info->eedump_len = 0;
1245 /* TODO CHIMP FW: reg dump details */
1246 info->regdump_len = 0;
1247}
1248
8e202366
MC		 1249static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1250{
1251 struct bnxt *bp = netdev_priv(dev);
1252
1253 wol->supported = 0;
1254 wol->wolopts = 0;
1255 memset(&wol->sopass, 0, sizeof(wol->sopass));
1256 if (bp->flags & BNXT_FLAG_WOL_CAP) {
1257 wol->supported = WAKE_MAGIC;
1258 if (bp->wol)
1259 wol->wolopts = WAKE_MAGIC;
1260 }
1261}
1262
5282db6c
MC		 1263static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1264{
1265 struct bnxt *bp = netdev_priv(dev);
1266
1267 if (wol->wolopts & ~WAKE_MAGIC)
1268 return -EINVAL;
1269
1270 if (wol->wolopts & WAKE_MAGIC) {
1271 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
1272 return -EINVAL;
1273 if (!bp->wol) {
1274 if (bnxt_hwrm_alloc_wol_fltr(bp))
1275 return -EBUSY;
1276 bp->wol = 1;
1277 }
1278 } else {
1279 if (bp->wol) {
1280 if (bnxt_hwrm_free_wol_fltr(bp))
1281 return -EBUSY;
1282 bp->wol = 0;
1283 }
1284 }
1285 return 0;
1286}
1287
170ce013 1288u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
c0c050c5 1289{
c0c050c5
MC		 1290 u32 speed_mask = 0;
1291
1292 /* TODO: support 25GB, 40GB, 50GB with different cable type */
1293 /* set the advertised speeds */
1294 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
1295 speed_mask |= ADVERTISED_100baseT_Full;
1296 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
1297 speed_mask |= ADVERTISED_1000baseT_Full;
1298 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
1299 speed_mask |= ADVERTISED_2500baseX_Full;
1300 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
1301 speed_mask |= ADVERTISED_10000baseT_Full;
c0c050c5 1302 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
1c49c421 1303 speed_mask |= ADVERTISED_40000baseCR4_Full;
27c4d578
MC		 1304
1305 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
1306 speed_mask |= ADVERTISED_Pause;
1307 else if (fw_pause & BNXT_LINK_PAUSE_TX)
1308 speed_mask |= ADVERTISED_Asym_Pause;
1309 else if (fw_pause & BNXT_LINK_PAUSE_RX)
1310 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1311
c0c050c5
MC		 1312 return speed_mask;
1313}
1314
00c04a92
MC		 1315#define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\
1316{ \
1317 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \
1318 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1319 100baseT_Full); \
1320 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \
1321 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1322 1000baseT_Full); \
1323 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \
1324 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1325 10000baseT_Full); \
1326 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \
1327 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1328 25000baseCR_Full); \
1329 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \
1330 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1331 40000baseCR4_Full);\
1332 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \
1333 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1334 50000baseCR2_Full);\
38a21b34
DK		 1335 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \
1336 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1337 100000baseCR4_Full);\
00c04a92
MC		 1338 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \
1339 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1340 Pause); \
1341 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \
1342 ethtool_link_ksettings_add_link_mode( \
1343 lk_ksettings, name, Asym_Pause);\
1344 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \
1345 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1346 Asym_Pause); \
1347 } \
1348}
1349
1350#define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \
1351{ \
1352 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1353 100baseT_Full) || \
1354 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1355 100baseT_Half)) \
1356 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \
1357 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1358 1000baseT_Full) || \
1359 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1360 1000baseT_Half)) \
1361 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \
1362 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1363 10000baseT_Full)) \
1364 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \
1365 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1366 25000baseCR_Full)) \
1367 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \
1368 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1369 40000baseCR4_Full)) \
1370 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \
1371 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1372 50000baseCR2_Full)) \
1373 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \
38a21b34
DK		 1374 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1375 100000baseCR4_Full)) \
1376 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \
00c04a92
MC		 1377}
1378
1379static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info,
1380 struct ethtool_link_ksettings *lk_ksettings)
27c4d578 1381{
68515a18 1382 u16 fw_speeds = link_info->advertising;
27c4d578
MC		 1383 u8 fw_pause = 0;
1384
1385 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1386 fw_pause = link_info->auto_pause_setting;
1387
00c04a92 1388 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising);
27c4d578
MC		 1389}
1390
00c04a92
MC		 1391static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info,
1392 struct ethtool_link_ksettings *lk_ksettings)
3277360e
MC		 1393{
1394 u16 fw_speeds = link_info->lp_auto_link_speeds;
1395 u8 fw_pause = 0;
1396
1397 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1398 fw_pause = link_info->lp_pause;
1399
00c04a92
MC		 1400 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings,
1401 lp_advertising);
3277360e
MC		 1402}
1403
00c04a92
MC		 1404static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info,
1405 struct ethtool_link_ksettings *lk_ksettings)
4b32cacc
MC		 1406{
1407 u16 fw_speeds = link_info->support_speeds;
4b32cacc 1408
00c04a92 1409 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported);
4b32cacc 1410
00c04a92
MC		 1411 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause);
1412 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1413 Asym_Pause);
93ed8117 1414
00c04a92
MC		 1415 if (link_info->support_auto_speeds)
1416 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1417 Autoneg);
93ed8117
MC		 1418}
1419
c0c050c5
MC		 1420u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
1421{
1422 switch (fw_link_speed) {
1423 case BNXT_LINK_SPEED_100MB:
1424 return SPEED_100;
1425 case BNXT_LINK_SPEED_1GB:
1426 return SPEED_1000;
1427 case BNXT_LINK_SPEED_2_5GB:
1428 return SPEED_2500;
1429 case BNXT_LINK_SPEED_10GB:
1430 return SPEED_10000;
1431 case BNXT_LINK_SPEED_20GB:
1432 return SPEED_20000;
1433 case BNXT_LINK_SPEED_25GB:
1434 return SPEED_25000;
1435 case BNXT_LINK_SPEED_40GB:
1436 return SPEED_40000;
1437 case BNXT_LINK_SPEED_50GB:
1438 return SPEED_50000;
38a21b34
DK		 1439 case BNXT_LINK_SPEED_100GB:
1440 return SPEED_100000;
c0c050c5
MC		 1441 default:
1442 return SPEED_UNKNOWN;
1443 }
1444}
1445
00c04a92
MC		 1446static int bnxt_get_link_ksettings(struct net_device *dev,
1447 struct ethtool_link_ksettings *lk_ksettings)
c0c050c5
MC		 1448{
1449 struct bnxt *bp = netdev_priv(dev);
1450 struct bnxt_link_info *link_info = &bp->link_info;
00c04a92
MC		 1451 struct ethtool_link_settings *base = &lk_ksettings->base;
1452 u32 ethtool_speed;
c0c050c5 1453
00c04a92 1454 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
e2dc9b6e 1455 mutex_lock(&bp->link_lock);
00c04a92 1456 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings);
c0c050c5 1457
00c04a92 1458 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
b763499e 1459 if (link_info->autoneg) {
00c04a92
MC		 1460 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings);
1461 ethtool_link_ksettings_add_link_mode(lk_ksettings,
1462 advertising, Autoneg);
1463 base->autoneg = AUTONEG_ENABLE;
83d8f5e9
MC		 1464 base->duplex = DUPLEX_UNKNOWN;
1465 if (link_info->phy_link_status == BNXT_LINK_LINK) {
00c04a92 1466 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings);
83d8f5e9
MC		 1467 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
1468 base->duplex = DUPLEX_FULL;
1469 else
1470 base->duplex = DUPLEX_HALF;
1471 }
29c262fe 1472 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
c0c050c5 1473 } else {
00c04a92 1474 base->autoneg = AUTONEG_DISABLE;
29c262fe
MC		 1475 ethtool_speed =
1476 bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
00c04a92 1477 base->duplex = DUPLEX_HALF;
29c262fe 1478 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
00c04a92 1479 base->duplex = DUPLEX_FULL;
c0c050c5 1480 }
00c04a92 1481 base->speed = ethtool_speed;
c0c050c5 1482
00c04a92 1483 base->port = PORT_NONE;
c0c050c5 1484 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
00c04a92
MC		 1485 base->port = PORT_TP;
1486 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1487 TP);
1488 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1489 TP);
c0c050c5 1490 } else {
00c04a92
MC		 1491 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1492 FIBRE);
1493 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1494 FIBRE);
c0c050c5
MC		 1495
1496 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
00c04a92 1497 base->port = PORT_DA;
c0c050c5
MC		 1498 else if (link_info->media_type ==
1499 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE)
00c04a92 1500 base->port = PORT_FIBRE;
c0c050c5 1501 }
00c04a92 1502 base->phy_address = link_info->phy_addr;
e2dc9b6e 1503 mutex_unlock(&bp->link_lock);
c0c050c5
MC		 1504
1505 return 0;
1506}
1507
38a21b34 1508static u32 bnxt_get_fw_speed(struct net_device *dev, u32 ethtool_speed)
c0c050c5 1509{
9d9cee08
MC		 1510 struct bnxt *bp = netdev_priv(dev);
1511 struct bnxt_link_info *link_info = &bp->link_info;
1512 u16 support_spds = link_info->support_speeds;
1513 u32 fw_speed = 0;
1514
c0c050c5
MC		 1515 switch (ethtool_speed) {
1516 case SPEED_100:
9d9cee08
MC		 1517 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
1518 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB;
1519 break;
c0c050c5 1520 case SPEED_1000:
9d9cee08
MC		 1521 if (support_spds & BNXT_LINK_SPEED_MSK_1GB)
1522 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB;
1523 break;
c0c050c5 1524 case SPEED_2500:
9d9cee08
MC		 1525 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
1526 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB;
1527 break;
c0c050c5 1528 case SPEED_10000:
9d9cee08
MC		 1529 if (support_spds & BNXT_LINK_SPEED_MSK_10GB)
1530 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB;
1531 break;
c0c050c5 1532 case SPEED_20000:
9d9cee08
MC		 1533 if (support_spds & BNXT_LINK_SPEED_MSK_20GB)
1534 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB;
1535 break;
c0c050c5 1536 case SPEED_25000:
9d9cee08
MC		 1537 if (support_spds & BNXT_LINK_SPEED_MSK_25GB)
1538 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB;
1539 break;
c0c050c5 1540 case SPEED_40000:
9d9cee08
MC		 1541 if (support_spds & BNXT_LINK_SPEED_MSK_40GB)
1542 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB;
1543 break;
c0c050c5 1544 case SPEED_50000:
9d9cee08
MC		 1545 if (support_spds & BNXT_LINK_SPEED_MSK_50GB)
1546 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB;
1547 break;
38a21b34
DK		 1548 case SPEED_100000:
1549 if (support_spds & BNXT_LINK_SPEED_MSK_100GB)
1550 fw_speed = PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB;
1551 break;
c0c050c5
MC		 1552 default:
1553 netdev_err(dev, "unsupported speed!\n");
1554 break;
1555 }
9d9cee08 1556 return fw_speed;
c0c050c5
MC		 1557}
1558
939f7f0c 1559u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
c0c050c5
MC		 1560{
1561 u16 fw_speed_mask = 0;
1562
1563 /* only support autoneg at speed 100, 1000, and 10000 */
1564 if (advertising & (ADVERTISED_100baseT_Full |
1565 ADVERTISED_100baseT_Half)) {
1566 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
1567 }
1568 if (advertising & (ADVERTISED_1000baseT_Full |
1569 ADVERTISED_1000baseT_Half)) {
1570 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
1571 }
1572 if (advertising & ADVERTISED_10000baseT_Full)
1573 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
1574
1c49c421
MC		 1575 if (advertising & ADVERTISED_40000baseCR4_Full)
1576 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
1577
c0c050c5
MC		 1578 return fw_speed_mask;
1579}
1580
00c04a92
MC		 1581static int bnxt_set_link_ksettings(struct net_device *dev,
1582 const struct ethtool_link_ksettings *lk_ksettings)
c0c050c5 1583{
c0c050c5
MC		 1584 struct bnxt *bp = netdev_priv(dev);
1585 struct bnxt_link_info *link_info = &bp->link_info;
00c04a92 1586 const struct ethtool_link_settings *base = &lk_ksettings->base;
c0c050c5 1587 bool set_pause = false;
68515a18
MC		 1588 u16 fw_advertising = 0;
1589 u32 speed;
00c04a92 1590 int rc = 0;
c0c050c5 1591
c7e457f4 1592 if (!BNXT_PHY_CFG_ABLE(bp))
00c04a92 1593 return -EOPNOTSUPP;
f1a082a6 1594
e2dc9b6e 1595 mutex_lock(&bp->link_lock);
00c04a92
MC		 1596 if (base->autoneg == AUTONEG_ENABLE) {
1597 BNXT_ETHTOOL_TO_FW_SPDS(fw_advertising, lk_ksettings,
1598 advertising);
c0c050c5
MC		 1599 link_info->autoneg |= BNXT_AUTONEG_SPEED;
1600 if (!fw_advertising)
93ed8117 1601 link_info->advertising = link_info->support_auto_speeds;
c0c050c5
MC		 1602 else
1603 link_info->advertising = fw_advertising;
1604 /* any change to autoneg will cause link change, therefore the
1605 * driver should put back the original pause setting in autoneg
1606 */
1607 set_pause = true;
1608 } else {
9d9cee08 1609 u16 fw_speed;
03efbec0 1610 u8 phy_type = link_info->phy_type;
9d9cee08 1611
03efbec0
MC		 1612 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
1613 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
1614 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1615 netdev_err(dev, "10GBase-T devices must autoneg\n");
1616 rc = -EINVAL;
1617 goto set_setting_exit;
1618 }
00c04a92 1619 if (base->duplex == DUPLEX_HALF) {
c0c050c5
MC		 1620 netdev_err(dev, "HALF DUPLEX is not supported!\n");
1621 rc = -EINVAL;
1622 goto set_setting_exit;
1623 }
00c04a92 1624 speed = base->speed;
9d9cee08
MC		 1625 fw_speed = bnxt_get_fw_speed(dev, speed);
1626 if (!fw_speed) {
1627 rc = -EINVAL;
1628 goto set_setting_exit;
1629 }
1630 link_info->req_link_speed = fw_speed;
c0c050c5 1631 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
b763499e 1632 link_info->autoneg = 0;
c0c050c5
MC		 1633 link_info->advertising = 0;
1634 }
1635
1636 if (netif_running(dev))
939f7f0c 1637 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
c0c050c5
MC		 1638
1639set_setting_exit:
e2dc9b6e 1640 mutex_unlock(&bp->link_lock);
c0c050c5
MC		 1641 return rc;
1642}
1643
1644static void bnxt_get_pauseparam(struct net_device *dev,
1645 struct ethtool_pauseparam *epause)
1646{
1647 struct bnxt *bp = netdev_priv(dev);
1648 struct bnxt_link_info *link_info = &bp->link_info;
1649
1650 if (BNXT_VF(bp))
1651 return;
b763499e 1652 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
3c02d1bb
MC		 1653 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
1654 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
c0c050c5
MC		 1655}
1656
1657static int bnxt_set_pauseparam(struct net_device *dev,
1658 struct ethtool_pauseparam *epause)
1659{
1660 int rc = 0;
1661 struct bnxt *bp = netdev_priv(dev);
1662 struct bnxt_link_info *link_info = &bp->link_info;
1663
c7e457f4 1664 if (!BNXT_PHY_CFG_ABLE(bp))
75362a3f 1665 return -EOPNOTSUPP;
c0c050c5
MC		 1666
1667 if (epause->autoneg) {
b763499e
MC		 1668 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
1669 return -EINVAL;
1670
c0c050c5 1671 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
c9ee9516
MC		 1672 if (bp->hwrm_spec_code >= 0x10201)
1673 link_info->req_flow_ctrl =
1674 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
c0c050c5
MC		 1675 } else {
1676 /* when transition from auto pause to force pause,
1677 * force a link change
1678 */
1679 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1680 link_info->force_link_chng = true;
1681 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
c9ee9516 1682 link_info->req_flow_ctrl = 0;
c0c050c5
MC		 1683 }
1684 if (epause->rx_pause)
1685 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
c0c050c5
MC		 1686
1687 if (epause->tx_pause)
1688 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
c0c050c5
MC		 1689
1690 if (netif_running(dev))
1691 rc = bnxt_hwrm_set_pause(bp);
1692 return rc;
1693}
1694
1695static u32 bnxt_get_link(struct net_device *dev)
1696{
1697 struct bnxt *bp = netdev_priv(dev);
1698
1699 /* TODO: handle MF, VF, driver close case */
1700 return bp->link_info.link_up;
1701}
1702
b3b0ddd0
MC		 1703static void bnxt_print_admin_err(struct bnxt *bp)
1704{
1705 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
1706}
1707
5ac67d8b
RS		 1708static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
1709 u16 ext, u16 *index, u32 *item_length,
1710 u32 *data_length);
1711
c0c050c5
MC		 1712static int bnxt_flash_nvram(struct net_device *dev,
1713 u16 dir_type,
1714 u16 dir_ordinal,
1715 u16 dir_ext,
1716 u16 dir_attr,
1717 const u8 *data,
1718 size_t data_len)
1719{
1720 struct bnxt *bp = netdev_priv(dev);
1721 int rc;
1722 struct hwrm_nvm_write_input req = {0};
1723 dma_addr_t dma_handle;
1724 u8 *kmem;
1725
1726 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1);
1727
1728 req.dir_type = cpu_to_le16(dir_type);
1729 req.dir_ordinal = cpu_to_le16(dir_ordinal);
1730 req.dir_ext = cpu_to_le16(dir_ext);
1731 req.dir_attr = cpu_to_le16(dir_attr);
1732 req.dir_data_length = cpu_to_le32(data_len);
1733
1734 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle,
1735 GFP_KERNEL);
1736 if (!kmem) {
1737 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
1738 (unsigned)data_len);
1739 return -ENOMEM;
1740 }
1741 memcpy(kmem, data, data_len);
1742 req.host_src_addr = cpu_to_le64(dma_handle);
1743
1744 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT);
1745 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle);
1746
d4f1420d 1747 if (rc == -EACCES)
b3b0ddd0 1748 bnxt_print_admin_err(bp);
c0c050c5
MC		 1749 return rc;
1750}
1751
d2d6318c
RS		 1752static int bnxt_firmware_reset(struct net_device *dev,
1753 u16 dir_type)
1754{
d2d6318c 1755 struct hwrm_fw_reset_input req = {0};
7c675421
VV		 1756 struct bnxt *bp = netdev_priv(dev);
1757 int rc;
d2d6318c
RS		 1758
1759 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
1760
d2d6318c
RS		 1761 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
1762 /* (e.g. when firmware isn't already running) */
1763 switch (dir_type) {
1764 case BNX_DIR_TYPE_CHIMP_PATCH:
1765 case BNX_DIR_TYPE_BOOTCODE:
1766 case BNX_DIR_TYPE_BOOTCODE_2:
1767 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
1768 /* Self-reset ChiMP upon next PCIe reset: */
1769 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
1770 break;
1771 case BNX_DIR_TYPE_APE_FW:
1772 case BNX_DIR_TYPE_APE_PATCH:
1773 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
08141e0b
RS		 1774 /* Self-reset APE upon next PCIe reset: */
1775 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
d2d6318c
RS		 1776 break;
1777 case BNX_DIR_TYPE_KONG_FW:
1778 case BNX_DIR_TYPE_KONG_PATCH:
1779 req.embedded_proc_type =
1780 FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
1781 break;
1782 case BNX_DIR_TYPE_BONO_FW:
1783 case BNX_DIR_TYPE_BONO_PATCH:
1784 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
1785 break;
49f7972f
VV		 1786 case BNXT_FW_RESET_CHIP:
1787 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
1788 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
0a3f4e4f
VV		 1789 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1790 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
49f7972f 1791 break;
6502ad59
SB		 1792 case BNXT_FW_RESET_AP:
1793 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP;
1794 break;
d2d6318c
RS		 1795 default:
1796 return -EINVAL;
1797 }
1798
7c675421 1799 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
d4f1420d 1800 if (rc == -EACCES)
b3b0ddd0 1801 bnxt_print_admin_err(bp);
7c675421 1802 return rc;
d2d6318c
RS		 1803}
1804
c0c050c5
MC		 1805static int bnxt_flash_firmware(struct net_device *dev,
1806 u16 dir_type,
1807 const u8 *fw_data,
1808 size_t fw_size)
1809{
1810 int rc = 0;
1811 u16 code_type;
1812 u32 stored_crc;
1813 u32 calculated_crc;
1814 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
1815
1816 switch (dir_type) {
1817 case BNX_DIR_TYPE_BOOTCODE:
1818 case BNX_DIR_TYPE_BOOTCODE_2:
1819 code_type = CODE_BOOT;
1820 break;
93e0b4fe
RS		 1821 case BNX_DIR_TYPE_CHIMP_PATCH:
1822 code_type = CODE_CHIMP_PATCH;
1823 break;
2731d70f
RS		 1824 case BNX_DIR_TYPE_APE_FW:
1825 code_type = CODE_MCTP_PASSTHRU;
1826 break;
93e0b4fe
RS		 1827 case BNX_DIR_TYPE_APE_PATCH:
1828 code_type = CODE_APE_PATCH;
1829 break;
1830 case BNX_DIR_TYPE_KONG_FW:
1831 code_type = CODE_KONG_FW;
1832 break;
1833 case BNX_DIR_TYPE_KONG_PATCH:
1834 code_type = CODE_KONG_PATCH;
1835 break;
1836 case BNX_DIR_TYPE_BONO_FW:
1837 code_type = CODE_BONO_FW;
1838 break;
1839 case BNX_DIR_TYPE_BONO_PATCH:
1840 code_type = CODE_BONO_PATCH;
1841 break;
c0c050c5
MC		 1842 default:
1843 netdev_err(dev, "Unsupported directory entry type: %u\n",
1844 dir_type);
1845 return -EINVAL;
1846 }
1847 if (fw_size < sizeof(struct bnxt_fw_header)) {
1848 netdev_err(dev, "Invalid firmware file size: %u\n",
1849 (unsigned int)fw_size);
1850 return -EINVAL;
1851 }
1852 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
1853 netdev_err(dev, "Invalid firmware signature: %08X\n",
1854 le32_to_cpu(header->signature));
1855 return -EINVAL;
1856 }
1857 if (header->code_type != code_type) {
1858 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
1859 code_type, header->code_type);
1860 return -EINVAL;
1861 }
1862 if (header->device != DEVICE_CUMULUS_FAMILY) {
1863 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
1864 DEVICE_CUMULUS_FAMILY, header->device);
1865 return -EINVAL;
1866 }
1867 /* Confirm the CRC32 checksum of the file: */
1868 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
1869 sizeof(stored_crc)));
1870 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
1871 if (calculated_crc != stored_crc) {
1872 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
1873 (unsigned long)stored_crc,
1874 (unsigned long)calculated_crc);
1875 return -EINVAL;
1876 }
c0c050c5
MC		 1877 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
1878 0, 0, fw_data, fw_size);
d2d6318c
RS		 1879 if (rc == 0) /* Firmware update successful */
1880 rc = bnxt_firmware_reset(dev, dir_type);
1881
c0c050c5
MC		 1882 return rc;
1883}
1884
5ac67d8b
RS		 1885static int bnxt_flash_microcode(struct net_device *dev,
1886 u16 dir_type,
1887 const u8 *fw_data,
1888 size_t fw_size)
1889{
1890 struct bnxt_ucode_trailer *trailer;
1891 u32 calculated_crc;
1892 u32 stored_crc;
1893 int rc = 0;
1894
1895 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
1896 netdev_err(dev, "Invalid microcode file size: %u\n",
1897 (unsigned int)fw_size);
1898 return -EINVAL;
1899 }
1900 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
1901 sizeof(*trailer)));
1902 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
1903 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
1904 le32_to_cpu(trailer->sig));
1905 return -EINVAL;
1906 }
1907 if (le16_to_cpu(trailer->dir_type) != dir_type) {
1908 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
1909 dir_type, le16_to_cpu(trailer->dir_type));
1910 return -EINVAL;
1911 }
1912 if (le16_to_cpu(trailer->trailer_length) <
1913 sizeof(struct bnxt_ucode_trailer)) {
1914 netdev_err(dev, "Invalid microcode trailer length: %d\n",
1915 le16_to_cpu(trailer->trailer_length));
1916 return -EINVAL;
1917 }
1918
1919 /* Confirm the CRC32 checksum of the file: */
1920 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
1921 sizeof(stored_crc)));
1922 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
1923 if (calculated_crc != stored_crc) {
1924 netdev_err(dev,
1925 "CRC32 (%08lX) does not match calculated: %08lX\n",
1926 (unsigned long)stored_crc,
1927 (unsigned long)calculated_crc);
1928 return -EINVAL;
1929 }
1930 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
1931 0, 0, fw_data, fw_size);
1932
1933 return rc;
1934}
1935
c0c050c5
MC		 1936static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
1937{
1938 switch (dir_type) {
1939 case BNX_DIR_TYPE_CHIMP_PATCH:
1940 case BNX_DIR_TYPE_BOOTCODE:
1941 case BNX_DIR_TYPE_BOOTCODE_2:
1942 case BNX_DIR_TYPE_APE_FW:
1943 case BNX_DIR_TYPE_APE_PATCH:
1944 case BNX_DIR_TYPE_KONG_FW:
1945 case BNX_DIR_TYPE_KONG_PATCH:
93e0b4fe
RS		 1946 case BNX_DIR_TYPE_BONO_FW:
1947 case BNX_DIR_TYPE_BONO_PATCH:
c0c050c5
MC		 1948 return true;
1949 }
1950
1951 return false;
1952}
1953
5ac67d8b 1954static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
c0c050c5
MC		 1955{
1956 switch (dir_type) {
1957 case BNX_DIR_TYPE_AVS:
1958 case BNX_DIR_TYPE_EXP_ROM_MBA:
1959 case BNX_DIR_TYPE_PCIE:
1960 case BNX_DIR_TYPE_TSCF_UCODE:
1961 case BNX_DIR_TYPE_EXT_PHY:
1962 case BNX_DIR_TYPE_CCM:
1963 case BNX_DIR_TYPE_ISCSI_BOOT:
1964 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
1965 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
1966 return true;
1967 }
1968
1969 return false;
1970}
1971
1972static bool bnxt_dir_type_is_executable(u16 dir_type)
1973{
1974 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
5ac67d8b 1975 bnxt_dir_type_is_other_exec_format(dir_type);
c0c050c5
MC		 1976}
1977
1978static int bnxt_flash_firmware_from_file(struct net_device *dev,
1979 u16 dir_type,
1980 const char *filename)
1981{
1982 const struct firmware *fw;
1983 int rc;
1984
c0c050c5
MC		 1985 rc = request_firmware(&fw, filename, &dev->dev);
1986 if (rc != 0) {
1987 netdev_err(dev, "Error %d requesting firmware file: %s\n",
1988 rc, filename);
1989 return rc;
1990 }
1991 if (bnxt_dir_type_is_ape_bin_format(dir_type) == true)
1992 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
5ac67d8b
RS		 1993 else if (bnxt_dir_type_is_other_exec_format(dir_type) == true)
1994 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
c0c050c5
MC		 1995 else
1996 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
1997 0, 0, fw->data, fw->size);
1998 release_firmware(fw);
1999 return rc;
2000}
2001
d168f328
VV		 2002int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
2003 u32 install_type)
c0c050c5 2004{
5ac67d8b
RS		 2005 struct bnxt *bp = netdev_priv(dev);
2006 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr;
2007 struct hwrm_nvm_install_update_input install = {0};
2008 const struct firmware *fw;
2009 u32 item_len;
22630e28 2010 int rc = 0;
5ac67d8b 2011 u16 index;
5ac67d8b
RS		 2012
2013 bnxt_hwrm_fw_set_time(bp);
2014
95ec1f47
VV		 2015 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
2016 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
2017 &index, &item_len, NULL);
2018 if (rc) {
5ac67d8b 2019 netdev_err(dev, "PKG update area not created in nvram\n");
95ec1f47 2020 return rc;
5ac67d8b
RS		 2021 }
2022
2023 rc = request_firmware(&fw, filename, &dev->dev);
2024 if (rc != 0) {
2025 netdev_err(dev, "PKG error %d requesting file: %s\n",
2026 rc, filename);
2027 return rc;
2028 }
2029
2030 if (fw->size > item_len) {
9a005c38 2031 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n",
5ac67d8b
RS		 2032 (unsigned long)fw->size);
2033 rc = -EFBIG;
2034 } else {
2035 dma_addr_t dma_handle;
2036 u8 *kmem;
2037 struct hwrm_nvm_modify_input modify = {0};
2038
2039 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1);
2040
2041 modify.dir_idx = cpu_to_le16(index);
2042 modify.len = cpu_to_le32(fw->size);
2043
2044 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size,
2045 &dma_handle, GFP_KERNEL);
2046 if (!kmem) {
2047 netdev_err(dev,
2048 "dma_alloc_coherent failure, length = %u\n",
2049 (unsigned int)fw->size);
2050 rc = -ENOMEM;
2051 } else {
2052 memcpy(kmem, fw->data, fw->size);
2053 modify.host_src_addr = cpu_to_le64(dma_handle);
2054
22630e28
EP		 2055 rc = hwrm_send_message(bp, &modify, sizeof(modify),
2056 FLASH_PACKAGE_TIMEOUT);
5ac67d8b
RS		 2057 dma_free_coherent(&bp->pdev->dev, fw->size, kmem,
2058 dma_handle);
2059 }
2060 }
2061 release_firmware(fw);
22630e28 2062 if (rc)
7c675421 2063 goto err_exit;
5ac67d8b
RS		 2064
2065 if ((install_type & 0xffff) == 0)
2066 install_type >>= 16;
2067 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1);
2068 install.install_type = cpu_to_le32(install_type);
2069
cb4d1d62 2070 mutex_lock(&bp->hwrm_cmd_lock);
22630e28
EP		 2071 rc = _hwrm_send_message(bp, &install, sizeof(install),
2072 INSTALL_PACKAGE_TIMEOUT);
2073 if (rc) {
cb4d1d62
KS		 2074 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err;
2075
dd2ebf34
VV		 2076 if (resp->error_code && error_code ==
2077 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) {
cb4d1d62
KS		 2078 install.flags |= cpu_to_le16(
2079 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
22630e28
EP		 2080 rc = _hwrm_send_message(bp, &install, sizeof(install),
2081 INSTALL_PACKAGE_TIMEOUT);
cb4d1d62 2082 }
22630e28 2083 if (rc)
dd2ebf34 2084 goto flash_pkg_exit;
cb4d1d62 2085 }
5ac67d8b
RS		 2086
2087 if (resp->result) {
2088 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
2089 (s8)resp->result, (int)resp->problem_item);
cb4d1d62 2090 rc = -ENOPKG;
5ac67d8b 2091 }
cb4d1d62
KS		 2092flash_pkg_exit:
2093 mutex_unlock(&bp->hwrm_cmd_lock);
7c675421 2094err_exit:
22630e28 2095 if (rc == -EACCES)
b3b0ddd0 2096 bnxt_print_admin_err(bp);
cb4d1d62 2097 return rc;
c0c050c5
MC		 2098}
2099
2100static int bnxt_flash_device(struct net_device *dev,
2101 struct ethtool_flash *flash)
2102{
2103 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
2104 netdev_err(dev, "flashdev not supported from a virtual function\n");
2105 return -EINVAL;
2106 }
2107
5ac67d8b
RS		 2108 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
2109 flash->region > 0xffff)
2110 return bnxt_flash_package_from_file(dev, flash->data,
2111 flash->region);
c0c050c5
MC		 2112
2113 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
2114}
2115
2116static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
2117{
2118 struct bnxt *bp = netdev_priv(dev);
2119 int rc;
2120 struct hwrm_nvm_get_dir_info_input req = {0};
2121 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr;
2122
2123 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1);
2124
2125 mutex_lock(&bp->hwrm_cmd_lock);
2126 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2127 if (!rc) {
2128 *entries = le32_to_cpu(output->entries);
2129 *length = le32_to_cpu(output->entry_length);
2130 }
2131 mutex_unlock(&bp->hwrm_cmd_lock);
2132 return rc;
2133}
2134
2135static int bnxt_get_eeprom_len(struct net_device *dev)
2136{
4cebbaca
MC		 2137 struct bnxt *bp = netdev_priv(dev);
2138
2139 if (BNXT_VF(bp))
2140 return 0;
2141
c0c050c5
MC		 2142 /* The -1 return value allows the entire 32-bit range of offsets to be
2143 * passed via the ethtool command-line utility.
2144 */
2145 return -1;
2146}
2147
2148static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
2149{
2150 struct bnxt *bp = netdev_priv(dev);
2151 int rc;
2152 u32 dir_entries;
2153 u32 entry_length;
2154 u8 *buf;
2155 size_t buflen;
2156 dma_addr_t dma_handle;
2157 struct hwrm_nvm_get_dir_entries_input req = {0};
2158
2159 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
2160 if (rc != 0)
2161 return rc;
2162
2163 /* Insert 2 bytes of directory info (count and size of entries) */
2164 if (len < 2)
2165 return -EINVAL;
2166
2167 *data++ = dir_entries;
2168 *data++ = entry_length;
2169 len -= 2;
2170 memset(data, 0xff, len);
2171
2172 buflen = dir_entries * entry_length;
2173 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle,
2174 GFP_KERNEL);
2175 if (!buf) {
2176 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2177 (unsigned)buflen);
2178 return -ENOMEM;
2179 }
2180 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1);
2181 req.host_dest_addr = cpu_to_le64(dma_handle);
2182 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2183 if (rc == 0)
2184 memcpy(data, buf, len > buflen ? buflen : len);
2185 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle);
2186 return rc;
2187}
2188
2189static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
2190 u32 length, u8 *data)
2191{
2192 struct bnxt *bp = netdev_priv(dev);
2193 int rc;
2194 u8 *buf;
2195 dma_addr_t dma_handle;
2196 struct hwrm_nvm_read_input req = {0};
2197
e0ad8fc5
MC		 2198 if (!length)
2199 return -EINVAL;
2200
c0c050c5
MC		 2201 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle,
2202 GFP_KERNEL);
2203 if (!buf) {
2204 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2205 (unsigned)length);
2206 return -ENOMEM;
2207 }
2208 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1);
2209 req.host_dest_addr = cpu_to_le64(dma_handle);
2210 req.dir_idx = cpu_to_le16(index);
2211 req.offset = cpu_to_le32(offset);
2212 req.len = cpu_to_le32(length);
2213
2214 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2215 if (rc == 0)
2216 memcpy(data, buf, length);
2217 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle);
2218 return rc;
2219}
2220
3ebf6f0a
RS		 2221static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2222 u16 ext, u16 *index, u32 *item_length,
2223 u32 *data_length)
2224{
2225 struct bnxt *bp = netdev_priv(dev);
2226 int rc;
2227 struct hwrm_nvm_find_dir_entry_input req = {0};
2228 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr;
2229
2230 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1);
2231 req.enables = 0;
2232 req.dir_idx = 0;
2233 req.dir_type = cpu_to_le16(type);
2234 req.dir_ordinal = cpu_to_le16(ordinal);
2235 req.dir_ext = cpu_to_le16(ext);
2236 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
cc72f3b1
MC		 2237 mutex_lock(&bp->hwrm_cmd_lock);
2238 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3ebf6f0a
RS		 2239 if (rc == 0) {
2240 if (index)
2241 *index = le16_to_cpu(output->dir_idx);
2242 if (item_length)
2243 *item_length = le32_to_cpu(output->dir_item_length);
2244 if (data_length)
2245 *data_length = le32_to_cpu(output->dir_data_length);
2246 }
cc72f3b1 2247 mutex_unlock(&bp->hwrm_cmd_lock);
3ebf6f0a
RS		 2248 return rc;
2249}
2250
2251static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
2252{
2253 char *retval = NULL;
2254 char *p;
2255 char *value;
2256 int field = 0;
2257
2258 if (datalen < 1)
2259 return NULL;
2260 /* null-terminate the log data (removing last '\n'): */
2261 data[datalen - 1] = 0;
2262 for (p = data; *p != 0; p++) {
2263 field = 0;
2264 retval = NULL;
2265 while (*p != 0 && *p != '\n') {
2266 value = p;
2267 while (*p != 0 && *p != '\t' && *p != '\n')
2268 p++;
2269 if (field == desired_field)
2270 retval = value;
2271 if (*p != '\t')
2272 break;
2273 *p = 0;
2274 field++;
2275 p++;
2276 }
2277 if (*p == 0)
2278 break;
2279 *p = 0;
2280 }
2281 return retval;
2282}
2283
a60faa60 2284static void bnxt_get_pkgver(struct net_device *dev)
3ebf6f0a 2285{
a60faa60 2286 struct bnxt *bp = netdev_priv(dev);
3ebf6f0a 2287 u16 index = 0;
a60faa60
VV		 2288 char *pkgver;
2289 u32 pkglen;
2290 u8 *pkgbuf;
2291 int len;
3ebf6f0a
RS		 2292
2293 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
2294 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
a60faa60
VV		 2295 &index, NULL, &pkglen) != 0)
2296 return;
3ebf6f0a 2297
a60faa60
VV		 2298 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
2299 if (!pkgbuf) {
2300 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
2301 pkglen);
2302 return;
2303 }
2304
2305 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf))
2306 goto err;
3ebf6f0a 2307
a60faa60
VV		 2308 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
2309 pkglen);
2310 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) {
2311 len = strlen(bp->fw_ver_str);
2312 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1,
2313 "/pkg %s", pkgver);
2314 }
2315err:
2316 kfree(pkgbuf);
3ebf6f0a
RS		 2317}
2318
c0c050c5
MC		 2319static int bnxt_get_eeprom(struct net_device *dev,
2320 struct ethtool_eeprom *eeprom,
2321 u8 *data)
2322{
2323 u32 index;
2324 u32 offset;
2325
2326 if (eeprom->offset == 0) /* special offset value to get directory */
2327 return bnxt_get_nvram_directory(dev, eeprom->len, data);
2328
2329 index = eeprom->offset >> 24;
2330 offset = eeprom->offset & 0xffffff;
2331
2332 if (index == 0) {
2333 netdev_err(dev, "unsupported index value: %d\n", index);
2334 return -EINVAL;
2335 }
2336
2337 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
2338}
2339
2340static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
2341{
2342 struct bnxt *bp = netdev_priv(dev);
2343 struct hwrm_nvm_erase_dir_entry_input req = {0};
2344
2345 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1);
2346 req.dir_idx = cpu_to_le16(index);
2347 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2348}
2349
2350static int bnxt_set_eeprom(struct net_device *dev,
2351 struct ethtool_eeprom *eeprom,
2352 u8 *data)
2353{
2354 struct bnxt *bp = netdev_priv(dev);
2355 u8 index, dir_op;
2356 u16 type, ext, ordinal, attr;
2357
2358 if (!BNXT_PF(bp)) {
2359 netdev_err(dev, "NVM write not supported from a virtual function\n");
2360 return -EINVAL;
2361 }
2362
2363 type = eeprom->magic >> 16;
2364
2365 if (type == 0xffff) { /* special value for directory operations */
2366 index = eeprom->magic & 0xff;
2367 dir_op = eeprom->magic >> 8;
2368 if (index == 0)
2369 return -EINVAL;
2370 switch (dir_op) {
2371 case 0x0e: /* erase */
2372 if (eeprom->offset != ~eeprom->magic)
2373 return -EINVAL;
2374 return bnxt_erase_nvram_directory(dev, index - 1);
2375 default:
2376 return -EINVAL;
2377 }
2378 }
2379
2380 /* Create or re-write an NVM item: */
2381 if (bnxt_dir_type_is_executable(type) == true)
5ac67d8b 2382 return -EOPNOTSUPP;
c0c050c5
MC		 2383 ext = eeprom->magic & 0xffff;
2384 ordinal = eeprom->offset >> 16;
2385 attr = eeprom->offset & 0xffff;
2386
2387 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data,
2388 eeprom->len);
2389}
2390
72b34f04
MC		 2391static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2392{
2393 struct bnxt *bp = netdev_priv(dev);
2394 struct ethtool_eee *eee = &bp->eee;
2395 struct bnxt_link_info *link_info = &bp->link_info;
2396 u32 advertising =
2397 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
2398 int rc = 0;
2399
c7e457f4 2400 if (!BNXT_PHY_CFG_ABLE(bp))
75362a3f 2401 return -EOPNOTSUPP;
72b34f04
MC		 2402
2403 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
2404 return -EOPNOTSUPP;
2405
2406 if (!edata->eee_enabled)
2407 goto eee_ok;
2408
2409 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2410 netdev_warn(dev, "EEE requires autoneg\n");
2411 return -EINVAL;
2412 }
2413 if (edata->tx_lpi_enabled) {
2414 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
2415 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
2416 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
2417 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
2418 return -EINVAL;
2419 } else if (!bp->lpi_tmr_hi) {
2420 edata->tx_lpi_timer = eee->tx_lpi_timer;
2421 }
2422 }
2423 if (!edata->advertised) {
2424 edata->advertised = advertising & eee->supported;
2425 } else if (edata->advertised & ~advertising) {
2426 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
2427 edata->advertised, advertising);
2428 return -EINVAL;
2429 }
2430
2431 eee->advertised = edata->advertised;
2432 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
2433 eee->tx_lpi_timer = edata->tx_lpi_timer;
2434eee_ok:
2435 eee->eee_enabled = edata->eee_enabled;
2436
2437 if (netif_running(dev))
2438 rc = bnxt_hwrm_set_link_setting(bp, false, true);
2439
2440 return rc;
2441}
2442
2443static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2444{
2445 struct bnxt *bp = netdev_priv(dev);
2446
2447 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
2448 return -EOPNOTSUPP;
2449
2450 *edata = bp->eee;
2451 if (!bp->eee.eee_enabled) {
2452 /* Preserve tx_lpi_timer so that the last value will be used
2453 * by default when it is re-enabled.
2454 */
2455 edata->advertised = 0;
2456 edata->tx_lpi_enabled = 0;
2457 }
2458
2459 if (!bp->eee.eee_active)
2460 edata->lp_advertised = 0;
2461
2462 return 0;
2463}
2464
42ee18fe
AK		 2465static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
2466 u16 page_number, u16 start_addr,
2467 u16 data_length, u8 *buf)
2468{
2469 struct hwrm_port_phy_i2c_read_input req = {0};
2470 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr;
2471 int rc, byte_offset = 0;
2472
2473 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1);
2474 req.i2c_slave_addr = i2c_addr;
2475 req.page_number = cpu_to_le16(page_number);
2476 req.port_id = cpu_to_le16(bp->pf.port_id);
2477 do {
2478 u16 xfer_size;
2479
2480 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
2481 data_length -= xfer_size;
2482 req.page_offset = cpu_to_le16(start_addr + byte_offset);
2483 req.data_length = xfer_size;
2484 req.enables = cpu_to_le32(start_addr + byte_offset ?
2485 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0);
2486 mutex_lock(&bp->hwrm_cmd_lock);
2487 rc = _hwrm_send_message(bp, &req, sizeof(req),
2488 HWRM_CMD_TIMEOUT);
2489 if (!rc)
2490 memcpy(buf + byte_offset, output->data, xfer_size);
2491 mutex_unlock(&bp->hwrm_cmd_lock);
2492 byte_offset += xfer_size;
2493 } while (!rc && data_length > 0);
2494
2495 return rc;
2496}
2497
2498static int bnxt_get_module_info(struct net_device *dev,
2499 struct ethtool_modinfo *modinfo)
2500{
7328a23c 2501 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
42ee18fe 2502 struct bnxt *bp = netdev_priv(dev);
42ee18fe
AK		 2503 int rc;
2504
2505 /* No point in going further if phy status indicates
2506 * module is not inserted or if it is powered down or
2507 * if it is of type 10GBase-T
2508 */
2509 if (bp->link_info.module_status >
2510 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
2511 return -EOPNOTSUPP;
2512
2513 /* This feature is not supported in older firmware versions */
2514 if (bp->hwrm_spec_code < 0x10202)
2515 return -EOPNOTSUPP;
2516
7328a23c
VV		 2517 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
2518 SFF_DIAG_SUPPORT_OFFSET + 1,
2519 data);
42ee18fe 2520 if (!rc) {
7328a23c
VV		 2521 u8 module_id = data[0];
2522 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
42ee18fe
AK		 2523
2524 switch (module_id) {
2525 case SFF_MODULE_ID_SFP:
2526 modinfo->type = ETH_MODULE_SFF_8472;
2527 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
7328a23c
VV		 2528 if (!diag_supported)
2529 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
42ee18fe
AK		 2530 break;
2531 case SFF_MODULE_ID_QSFP:
2532 case SFF_MODULE_ID_QSFP_PLUS:
2533 modinfo->type = ETH_MODULE_SFF_8436;
2534 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2535 break;
2536 case SFF_MODULE_ID_QSFP28:
2537 modinfo->type = ETH_MODULE_SFF_8636;
2538 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2539 break;
2540 default:
2541 rc = -EOPNOTSUPP;
2542 break;
2543 }
2544 }
42ee18fe
AK		 2545 return rc;
2546}
2547
2548static int bnxt_get_module_eeprom(struct net_device *dev,
2549 struct ethtool_eeprom *eeprom,
2550 u8 *data)
2551{
2552 struct bnxt *bp = netdev_priv(dev);
2553 u16 start = eeprom->offset, length = eeprom->len;
f3ea3119 2554 int rc = 0;
42ee18fe
AK		 2555
2556 memset(data, 0, eeprom->len);
2557
2558 /* Read A0 portion of the EEPROM */
2559 if (start < ETH_MODULE_SFF_8436_LEN) {
2560 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
2561 length = ETH_MODULE_SFF_8436_LEN - start;
2562 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
2563 start, length, data);
2564 if (rc)
2565 return rc;
2566 start += length;
2567 data += length;
2568 length = eeprom->len - length;
2569 }
2570
2571 /* Read A2 portion of the EEPROM */
2572 if (length) {
2573 start -= ETH_MODULE_SFF_8436_LEN;
dea521a2
CJ		 2574 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1,
2575 start, length, data);
42ee18fe
AK		 2576 }
2577 return rc;
2578}
2579
ae8e98a6
DK		 2580static int bnxt_nway_reset(struct net_device *dev)
2581{
2582 int rc = 0;
2583
2584 struct bnxt *bp = netdev_priv(dev);
2585 struct bnxt_link_info *link_info = &bp->link_info;
2586
c7e457f4 2587 if (!BNXT_PHY_CFG_ABLE(bp))
ae8e98a6
DK		 2588 return -EOPNOTSUPP;
2589
2590 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
2591 return -EINVAL;
2592
2593 if (netif_running(dev))
2594 rc = bnxt_hwrm_set_link_setting(bp, true, false);
2595
2596 return rc;
2597}
2598
5ad2cbee
MC		 2599static int bnxt_set_phys_id(struct net_device *dev,
2600 enum ethtool_phys_id_state state)
2601{
2602 struct hwrm_port_led_cfg_input req = {0};
2603 struct bnxt *bp = netdev_priv(dev);
2604 struct bnxt_pf_info *pf = &bp->pf;
2605 struct bnxt_led_cfg *led_cfg;
2606 u8 led_state;
2607 __le16 duration;
9f90445c 2608 int i;
5ad2cbee
MC		 2609
2610 if (!bp->num_leds || BNXT_VF(bp))
2611 return -EOPNOTSUPP;
2612
2613 if (state == ETHTOOL_ID_ACTIVE) {
2614 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
2615 duration = cpu_to_le16(500);
2616 } else if (state == ETHTOOL_ID_INACTIVE) {
2617 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
2618 duration = cpu_to_le16(0);
2619 } else {
2620 return -EINVAL;
2621 }
2622 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1);
2623 req.port_id = cpu_to_le16(pf->port_id);
2624 req.num_leds = bp->num_leds;
2625 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2626 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2627 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2628 led_cfg->led_id = bp->leds[i].led_id;
2629 led_cfg->led_state = led_state;
2630 led_cfg->led_blink_on = duration;
2631 led_cfg->led_blink_off = duration;
2632 led_cfg->led_group_id = bp->leds[i].led_group_id;
2633 }
9f90445c 2634 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5ad2cbee
MC		 2635}
2636
67fea463
MC		 2637static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
2638{
2639 struct hwrm_selftest_irq_input req = {0};
2640
2641 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1);
2642 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2643}
2644
2645static int bnxt_test_irq(struct bnxt *bp)
2646{
2647 int i;
2648
2649 for (i = 0; i < bp->cp_nr_rings; i++) {
2650 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
2651 int rc;
2652
2653 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
2654 if (rc)
2655 return rc;
2656 }
2657 return 0;
2658}
2659
f7dc1ea6
MC		 2660static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
2661{
2662 struct hwrm_port_mac_cfg_input req = {0};
2663
2664 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1);
2665
2666 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
2667 if (enable)
2668 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
2669 else
2670 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
2671 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2672}
2673
56d37462
VV		 2674static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
2675{
2676 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2677 struct hwrm_port_phy_qcaps_input req = {0};
2678 int rc;
2679
2680 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
2681 mutex_lock(&bp->hwrm_cmd_lock);
2682 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2683 if (!rc)
2684 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
2685
2686 mutex_unlock(&bp->hwrm_cmd_lock);
2687 return rc;
2688}
2689
91725d89
MC		 2690static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
2691 struct hwrm_port_phy_cfg_input *req)
2692{
2693 struct bnxt_link_info *link_info = &bp->link_info;
56d37462 2694 u16 fw_advertising;
91725d89
MC		 2695 u16 fw_speed;
2696 int rc;
2697
8a60efd1
MC		 2698 if (!link_info->autoneg ||
2699 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK))
91725d89
MC		 2700 return 0;
2701
56d37462
VV		 2702 rc = bnxt_query_force_speeds(bp, &fw_advertising);
2703 if (rc)
2704 return rc;
2705
91725d89 2706 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
83d8f5e9 2707 if (bp->link_info.link_up)
91725d89
MC		 2708 fw_speed = bp->link_info.link_speed;
2709 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
2710 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
2711 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
2712 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
2713 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
2714 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
2715 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
2716 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
2717
2718 req->force_link_speed = cpu_to_le16(fw_speed);
2719 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
2720 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
2721 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT);
2722 req->flags = 0;
2723 req->force_link_speed = cpu_to_le16(0);
2724 return rc;
2725}
2726
55fd0cf3 2727static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
91725d89
MC		 2728{
2729 struct hwrm_port_phy_cfg_input req = {0};
2730
2731 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
2732
2733 if (enable) {
2734 bnxt_disable_an_for_lpbk(bp, &req);
55fd0cf3
MC		 2735 if (ext)
2736 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
2737 else
2738 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
91725d89
MC		 2739 } else {
2740 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
2741 }
2742 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
2743 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2744}
2745
e44758b7 2746static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
f7dc1ea6
MC		 2747 u32 raw_cons, int pkt_size)
2748{
e44758b7
MC		 2749 struct bnxt_napi *bnapi = cpr->bnapi;
2750 struct bnxt_rx_ring_info *rxr;
f7dc1ea6
MC		 2751 struct bnxt_sw_rx_bd *rx_buf;
2752 struct rx_cmp *rxcmp;
2753 u16 cp_cons, cons;
2754 u8 *data;
2755 u32 len;
2756 int i;
2757
e44758b7 2758 rxr = bnapi->rx_ring;
f7dc1ea6
MC		 2759 cp_cons = RING_CMP(raw_cons);
2760 rxcmp = (struct rx_cmp *)
2761 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2762 cons = rxcmp->rx_cmp_opaque;
2763 rx_buf = &rxr->rx_buf_ring[cons];
2764 data = rx_buf->data_ptr;
2765 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
2766 if (len != pkt_size)
2767 return -EIO;
2768 i = ETH_ALEN;
2769 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
2770 return -EIO;
2771 i += ETH_ALEN;
2772 for ( ; i < pkt_size; i++) {
2773 if (data[i] != (u8)(i & 0xff))
2774 return -EIO;
2775 }
2776 return 0;
2777}
2778
e44758b7
MC		 2779static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2780 int pkt_size)
f7dc1ea6 2781{
f7dc1ea6
MC		 2782 struct tx_cmp *txcmp;
2783 int rc = -EIO;
2784 u32 raw_cons;
2785 u32 cons;
2786 int i;
2787
f7dc1ea6
MC		 2788 raw_cons = cpr->cp_raw_cons;
2789 for (i = 0; i < 200; i++) {
2790 cons = RING_CMP(raw_cons);
2791 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2792
2793 if (!TX_CMP_VALID(txcmp, raw_cons)) {
2794 udelay(5);
2795 continue;
2796 }
2797
2798 /* The valid test of the entry must be done first before
2799 * reading any further.
2800 */
2801 dma_rmb();
2802 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {
e44758b7 2803 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
f7dc1ea6
MC		 2804 raw_cons = NEXT_RAW_CMP(raw_cons);
2805 raw_cons = NEXT_RAW_CMP(raw_cons);
2806 break;
2807 }
2808 raw_cons = NEXT_RAW_CMP(raw_cons);
2809 }
2810 cpr->cp_raw_cons = raw_cons;
2811 return rc;
2812}
2813
2814static int bnxt_run_loopback(struct bnxt *bp)
2815{
2816 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
84404d5f 2817 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
e44758b7 2818 struct bnxt_cp_ring_info *cpr;
f7dc1ea6
MC		 2819 int pkt_size, i = 0;
2820 struct sk_buff *skb;
2821 dma_addr_t map;
2822 u8 *data;
2823 int rc;
2824
84404d5f
MC		 2825 cpr = &rxr->bnapi->cp_ring;
2826 if (bp->flags & BNXT_FLAG_CHIP_P5)
2827 cpr = cpr->cp_ring_arr[BNXT_RX_HDL];
f7dc1ea6
MC		 2828 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
2829 skb = netdev_alloc_skb(bp->dev, pkt_size);
2830 if (!skb)
2831 return -ENOMEM;
2832 data = skb_put(skb, pkt_size);
2833 eth_broadcast_addr(data);
2834 i += ETH_ALEN;
2835 ether_addr_copy(&data[i], bp->dev->dev_addr);
2836 i += ETH_ALEN;
2837 for ( ; i < pkt_size; i++)
2838 data[i] = (u8)(i & 0xff);
2839
2840 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
2841 PCI_DMA_TODEVICE);
2842 if (dma_mapping_error(&bp->pdev->dev, map)) {
2843 dev_kfree_skb(skb);
2844 return -EIO;
2845 }
c1ba92a8 2846 bnxt_xmit_bd(bp, txr, map, pkt_size);
f7dc1ea6
MC		 2847
2848 /* Sync BD data before updating doorbell */
2849 wmb();
2850
697197e5 2851 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
e44758b7 2852 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
f7dc1ea6
MC		 2853
2854 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
2855 dev_kfree_skb(skb);
2856 return rc;
2857}
2858
eb513658
MC		 2859static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
2860{
2861 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr;
2862 struct hwrm_selftest_exec_input req = {0};
2863 int rc;
2864
2865 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1);
2866 mutex_lock(&bp->hwrm_cmd_lock);
2867 resp->test_success = 0;
2868 req.flags = test_mask;
2869 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout);
2870 *test_results = resp->test_success;
2871 mutex_unlock(&bp->hwrm_cmd_lock);
2872 return rc;
2873}
2874
55fd0cf3 2875#define BNXT_DRV_TESTS 4
f7dc1ea6 2876#define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
91725d89 2877#define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
55fd0cf3
MC		 2878#define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
2879#define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
eb513658
MC		 2880
2881static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
2882 u64 *buf)
2883{
2884 struct bnxt *bp = netdev_priv(dev);
55fd0cf3 2885 bool do_ext_lpbk = false;
eb513658
MC		 2886 bool offline = false;
2887 u8 test_results = 0;
2888 u8 test_mask = 0;
d27e2ca1 2889 int rc = 0, i;
eb513658
MC		 2890
2891 if (!bp->num_tests || !BNXT_SINGLE_PF(bp))
2892 return;
2893 memset(buf, 0, sizeof(u64) * bp->num_tests);
2894 if (!netif_running(dev)) {
2895 etest->flags |= ETH_TEST_FL_FAILED;
2896 return;
2897 }
2898
55fd0cf3
MC		 2899 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
2900 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK))
2901 do_ext_lpbk = true;
2902
eb513658
MC		 2903 if (etest->flags & ETH_TEST_FL_OFFLINE) {
2904 if (bp->pf.active_vfs) {
2905 etest->flags |= ETH_TEST_FL_FAILED;
2906 netdev_warn(dev, "Offline tests cannot be run with active VFs\n");
2907 return;
2908 }
2909 offline = true;
2910 }
2911
2912 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
2913 u8 bit_val = 1 << i;
2914
2915 if (!(bp->test_info->offline_mask & bit_val))
2916 test_mask |= bit_val;
2917 else if (offline)
2918 test_mask |= bit_val;
2919 }
2920 if (!offline) {
2921 bnxt_run_fw_tests(bp, test_mask, &test_results);
2922 } else {
2923 rc = bnxt_close_nic(bp, false, false);
2924 if (rc)
2925 return;
2926 bnxt_run_fw_tests(bp, test_mask, &test_results);
f7dc1ea6
MC		 2927
2928 buf[BNXT_MACLPBK_TEST_IDX] = 1;
2929 bnxt_hwrm_mac_loopback(bp, true);
2930 msleep(250);
2931 rc = bnxt_half_open_nic(bp);
2932 if (rc) {
2933 bnxt_hwrm_mac_loopback(bp, false);
2934 etest->flags |= ETH_TEST_FL_FAILED;
2935 return;
2936 }
2937 if (bnxt_run_loopback(bp))
2938 etest->flags |= ETH_TEST_FL_FAILED;
2939 else
2940 buf[BNXT_MACLPBK_TEST_IDX] = 0;
2941
f7dc1ea6 2942 bnxt_hwrm_mac_loopback(bp, false);
55fd0cf3 2943 bnxt_hwrm_phy_loopback(bp, true, false);
91725d89
MC		 2944 msleep(1000);
2945 if (bnxt_run_loopback(bp)) {
2946 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
2947 etest->flags |= ETH_TEST_FL_FAILED;
2948 }
55fd0cf3
MC		 2949 if (do_ext_lpbk) {
2950 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2951 bnxt_hwrm_phy_loopback(bp, true, true);
2952 msleep(1000);
2953 if (bnxt_run_loopback(bp)) {
2954 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
2955 etest->flags |= ETH_TEST_FL_FAILED;
2956 }
2957 }
2958 bnxt_hwrm_phy_loopback(bp, false, false);
91725d89 2959 bnxt_half_close_nic(bp);
d27e2ca1 2960 rc = bnxt_open_nic(bp, false, true);
eb513658 2961 }
d27e2ca1 2962 if (rc || bnxt_test_irq(bp)) {
67fea463
MC		 2963 buf[BNXT_IRQ_TEST_IDX] = 1;
2964 etest->flags |= ETH_TEST_FL_FAILED;
2965 }
eb513658
MC		 2966 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
2967 u8 bit_val = 1 << i;
2968
2969 if ((test_mask & bit_val) && !(test_results & bit_val)) {
2970 buf[i] = 1;
2971 etest->flags |= ETH_TEST_FL_FAILED;
2972 }
2973 }
2974}
2975
49f7972f
VV		 2976static int bnxt_reset(struct net_device *dev, u32 *flags)
2977{
2978 struct bnxt *bp = netdev_priv(dev);
2979 int rc = 0;
2980
2981 if (!BNXT_PF(bp)) {
2982 netdev_err(dev, "Reset is not supported from a VF\n");
2983 return -EOPNOTSUPP;
2984 }
2985
0a3f4e4f
VV		 2986 if (pci_vfs_assigned(bp->pdev) &&
2987 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
49f7972f
VV		 2988 netdev_err(dev,
2989 "Reset not allowed when VFs are assigned to VMs\n");
2990 return -EBUSY;
2991 }
2992
2993 if (*flags == ETH_RESET_ALL) {
2994 /* This feature is not supported in older firmware versions */
2995 if (bp->hwrm_spec_code < 0x10803)
2996 return -EOPNOTSUPP;
2997
2998 rc = bnxt_firmware_reset(dev, BNXT_FW_RESET_CHIP);
2373d8d6 2999 if (!rc) {
0a3f4e4f
VV		 3000 netdev_info(dev, "Reset request successful.\n");
3001 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
3002 netdev_info(dev, "Reload driver to complete reset\n");
2373d8d6
SB		 3003 *flags = 0;
3004 }
6502ad59
SB		 3005 } else if (*flags == ETH_RESET_AP) {
3006 /* This feature is not supported in older firmware versions */
3007 if (bp->hwrm_spec_code < 0x10803)
3008 return -EOPNOTSUPP;
3009
3010 rc = bnxt_firmware_reset(dev, BNXT_FW_RESET_AP);
2373d8d6 3011 if (!rc) {
6502ad59 3012 netdev_info(dev, "Reset Application Processor request successful.\n");
2373d8d6
SB		 3013 *flags = 0;
3014 }
49f7972f
VV		 3015 } else {
3016 rc = -EINVAL;
3017 }
3018
3019 return rc;
3020}
3021
6c5657d0
VV		 3022static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len,
3023 struct bnxt_hwrm_dbg_dma_info *info)
3024{
3025 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr;
3026 struct hwrm_dbg_cmn_input *cmn_req = msg;
3027 __le16 *seq_ptr = msg + info->seq_off;
3028 u16 seq = 0, len, segs_off;
3029 void *resp = cmn_resp;
3030 dma_addr_t dma_handle;
3031 int rc, off = 0;
3032 void *dma_buf;
3033
3034 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle,
3035 GFP_KERNEL);
3036 if (!dma_buf)
3037 return -ENOMEM;
3038
3039 segs_off = offsetof(struct hwrm_dbg_coredump_list_output,
3040 total_segments);
3041 cmn_req->host_dest_addr = cpu_to_le64(dma_handle);
3042 cmn_req->host_buf_len = cpu_to_le32(info->dma_len);
3043 mutex_lock(&bp->hwrm_cmd_lock);
3044 while (1) {
3045 *seq_ptr = cpu_to_le16(seq);
5b306bde
VV		 3046 rc = _hwrm_send_message(bp, msg, msg_len,
3047 HWRM_COREDUMP_TIMEOUT);
6c5657d0
VV		 3048 if (rc)
3049 break;
3050
3051 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off)));
3052 if (!seq &&
3053 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) {
3054 info->segs = le16_to_cpu(*((__le16 *)(resp +
3055 segs_off)));
3056 if (!info->segs) {
3057 rc = -EIO;
3058 break;
3059 }
3060
3061 info->dest_buf_size = info->segs *
3062 sizeof(struct coredump_segment_record);
3063 info->dest_buf = kmalloc(info->dest_buf_size,
3064 GFP_KERNEL);
3065 if (!info->dest_buf) {
3066 rc = -ENOMEM;
3067 break;
3068 }
3069 }
3070
c74751f4
VV		 3071 if (info->dest_buf) {
3072 if ((info->seg_start + off + len) <=
3073 BNXT_COREDUMP_BUF_LEN(info->buf_len)) {
3074 memcpy(info->dest_buf + off, dma_buf, len);
3075 } else {
3076 rc = -ENOBUFS;
3077 break;
3078 }
3079 }
6c5657d0
VV		 3080
3081 if (cmn_req->req_type ==
3082 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE))
3083 info->dest_buf_size += len;
3084
3085 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE))
3086 break;
3087
3088 seq++;
3089 off += len;
3090 }
3091 mutex_unlock(&bp->hwrm_cmd_lock);
3092 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle);
3093 return rc;
3094}
3095
3096static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp,
3097 struct bnxt_coredump *coredump)
3098{
3099 struct hwrm_dbg_coredump_list_input req = {0};
3100 struct bnxt_hwrm_dbg_dma_info info = {NULL};
3101 int rc;
3102
3103 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1);
3104
3105 info.dma_len = COREDUMP_LIST_BUF_LEN;
3106 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no);
3107 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output,
3108 data_len);
3109
3110 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
3111 if (!rc) {
3112 coredump->data = info.dest_buf;
3113 coredump->data_size = info.dest_buf_size;
3114 coredump->total_segs = info.segs;
3115 }
3116 return rc;
3117}
3118
3119static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id,
3120 u16 segment_id)
3121{
3122 struct hwrm_dbg_coredump_initiate_input req = {0};
3123
3124 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1);
3125 req.component_id = cpu_to_le16(component_id);
3126 req.segment_id = cpu_to_le16(segment_id);
3127
57a8730b 3128 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT);
6c5657d0
VV		 3129}
3130
3131static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id,
3132 u16 segment_id, u32 *seg_len,
c74751f4 3133 void *buf, u32 buf_len, u32 offset)
6c5657d0
VV		 3134{
3135 struct hwrm_dbg_coredump_retrieve_input req = {0};
3136 struct bnxt_hwrm_dbg_dma_info info = {NULL};
3137 int rc;
3138
3139 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1);
3140 req.component_id = cpu_to_le16(component_id);
3141 req.segment_id = cpu_to_le16(segment_id);
3142
3143 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN;
3144 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input,
3145 seq_no);
3146 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output,
3147 data_len);
c74751f4 3148 if (buf) {
6c5657d0 3149 info.dest_buf = buf + offset;
c74751f4
VV		 3150 info.buf_len = buf_len;
3151 info.seg_start = offset;
3152 }
6c5657d0
VV		 3153
3154 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
3155 if (!rc)
3156 *seg_len = info.dest_buf_size;
3157
3158 return rc;
3159}
3160
3161static void
3162bnxt_fill_coredump_seg_hdr(struct bnxt *bp,
3163 struct bnxt_coredump_segment_hdr *seg_hdr,
3164 struct coredump_segment_record *seg_rec, u32 seg_len,
3165 int status, u32 duration, u32 instance)
3166{
3167 memset(seg_hdr, 0, sizeof(*seg_hdr));
8605212a 3168 memcpy(seg_hdr->signature, "sEgM", 4);
6c5657d0
VV		 3169 if (seg_rec) {
3170 seg_hdr->component_id = (__force __le32)seg_rec->component_id;
3171 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id;
3172 seg_hdr->low_version = seg_rec->version_low;
3173 seg_hdr->high_version = seg_rec->version_hi;
3174 } else {
3175 /* For hwrm_ver_get response Component id = 2
3176 * and Segment id = 0
3177 */
3178 seg_hdr->component_id = cpu_to_le32(2);
3179 seg_hdr->segment_id = 0;
3180 }
3181 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn);
3182 seg_hdr->length = cpu_to_le32(seg_len);
3183 seg_hdr->status = cpu_to_le32(status);
3184 seg_hdr->duration = cpu_to_le32(duration);
3185 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr));
3186 seg_hdr->instance = cpu_to_le32(instance);
3187}
3188
3189static void
3190bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record,
3191 time64_t start, s16 start_utc, u16 total_segs,
3192 int status)
3193{
3194 time64_t end = ktime_get_real_seconds();
3195 u32 os_ver_major = 0, os_ver_minor = 0;
3196 struct tm tm;
3197
3198 time64_to_tm(start, 0, &tm);
3199 memset(record, 0, sizeof(*record));
8605212a 3200 memcpy(record->signature, "cOrE", 4);
6c5657d0
VV		 3201 record->flags = 0;
3202 record->low_version = 0;
3203 record->high_version = 1;
3204 record->asic_state = 0;
3d46eee5
AB		 3205 strlcpy(record->system_name, utsname()->nodename,
3206 sizeof(record->system_name));
8dc5ae2d
VV		 3207 record->year = cpu_to_le16(tm.tm_year + 1900);
3208 record->month = cpu_to_le16(tm.tm_mon + 1);
6c5657d0
VV		 3209 record->day = cpu_to_le16(tm.tm_mday);
3210 record->hour = cpu_to_le16(tm.tm_hour);
3211 record->minute = cpu_to_le16(tm.tm_min);
3212 record->second = cpu_to_le16(tm.tm_sec);
3213 record->utc_bias = cpu_to_le16(start_utc);
3214 strcpy(record->commandline, "ethtool -w");
3215 record->total_segments = cpu_to_le32(total_segs);
3216
3217 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor);
3218 record->os_ver_major = cpu_to_le32(os_ver_major);
3219 record->os_ver_minor = cpu_to_le32(os_ver_minor);
3220
8605212a 3221 strlcpy(record->os_name, utsname()->sysname, 32);
6c5657d0
VV		 3222 time64_to_tm(end, 0, &tm);
3223 record->end_year = cpu_to_le16(tm.tm_year + 1900);
3224 record->end_month = cpu_to_le16(tm.tm_mon + 1);
3225 record->end_day = cpu_to_le16(tm.tm_mday);
3226 record->end_hour = cpu_to_le16(tm.tm_hour);
3227 record->end_minute = cpu_to_le16(tm.tm_min);
3228 record->end_second = cpu_to_le16(tm.tm_sec);
3229 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60);
3230 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 |
3231 bp->ver_resp.chip_rev << 8 |
3232 bp->ver_resp.chip_metal);
3233 record->asic_id2 = 0;
3234 record->coredump_status = cpu_to_le32(status);
3235 record->ioctl_low_version = 0;
3236 record->ioctl_high_version = 0;
3237}
3238
3239static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len)
3240{
3241 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output);
c74751f4 3242 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0;
6c5657d0 3243 struct coredump_segment_record *seg_record = NULL;
6c5657d0 3244 struct bnxt_coredump_segment_hdr seg_hdr;
6c5657d0
VV		 3245 struct bnxt_coredump coredump = {NULL};
3246 time64_t start_time;
3247 u16 start_utc;
3248 int rc = 0, i;
3249
c74751f4
VV		 3250 if (buf)
3251 buf_len = *dump_len;
3252
6c5657d0
VV		 3253 start_time = ktime_get_real_seconds();
3254 start_utc = sys_tz.tz_minuteswest * 60;
3255 seg_hdr_len = sizeof(seg_hdr);
3256
3257 /* First segment should be hwrm_ver_get response */
3258 *dump_len = seg_hdr_len + ver_get_resp_len;
3259 if (buf) {
3260 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len,
3261 0, 0, 0);
3262 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
3263 offset += seg_hdr_len;
3264 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len);
3265 offset += ver_get_resp_len;
3266 }
3267
3268 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump);
3269 if (rc) {
3270 netdev_err(bp->dev, "Failed to get coredump segment list\n");
3271 goto err;
3272 }
3273
3274 *dump_len += seg_hdr_len * coredump.total_segs;
3275
3276 seg_record = (struct coredump_segment_record *)coredump.data;
3277 seg_record_len = sizeof(*seg_record);
3278
3279 for (i = 0; i < coredump.total_segs; i++) {
3280 u16 comp_id = le16_to_cpu(seg_record->component_id);
3281 u16 seg_id = le16_to_cpu(seg_record->segment_id);
3282 u32 duration = 0, seg_len = 0;
3283 unsigned long start, end;
3284
c74751f4
VV		 3285 if (buf && ((offset + seg_hdr_len) >
3286 BNXT_COREDUMP_BUF_LEN(buf_len))) {
3287 rc = -ENOBUFS;
3288 goto err;
3289 }
3290
6c5657d0
VV		 3291 start = jiffies;
3292
3293 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id);
3294 if (rc) {
3295 netdev_err(bp->dev,
3296 "Failed to initiate coredump for seg = %d\n",
3297 seg_record->segment_id);
3298 goto next_seg;
3299 }
3300
3301 /* Write segment data into the buffer */
3302 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id,
c74751f4 3303 &seg_len, buf, buf_len,
6c5657d0 3304 offset + seg_hdr_len);
c74751f4
VV		 3305 if (rc && rc == -ENOBUFS)
3306 goto err;
3307 else if (rc)
6c5657d0
VV		 3308 netdev_err(bp->dev,
3309 "Failed to retrieve coredump for seg = %d\n",
3310 seg_record->segment_id);
3311
3312next_seg:
3313 end = jiffies;
3314 duration = jiffies_to_msecs(end - start);
3315 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len,
3316 rc, duration, 0);
3317
3318 if (buf) {
3319 /* Write segment header into the buffer */
3320 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
3321 offset += seg_hdr_len + seg_len;
3322 }
3323
3324 *dump_len += seg_len;
3325 seg_record =
3326 (struct coredump_segment_record *)((u8 *)seg_record +
3327 seg_record_len);
3328 }
3329
3330err:
1bbf3aed
AB		 3331 if (buf)
3332 bnxt_fill_coredump_record(bp, buf + offset, start_time,
6c5657d0
VV		 3333 start_utc, coredump.total_segs + 1,
3334 rc);
6c5657d0 3335 kfree(coredump.data);
1bbf3aed 3336 *dump_len += sizeof(struct bnxt_coredump_record);
c74751f4 3337 if (rc == -ENOBUFS)
9a005c38 3338 netdev_err(bp->dev, "Firmware returned large coredump buffer\n");
6c5657d0
VV		 3339 return rc;
3340}
3341
0b0eacf3
VV		 3342static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
3343{
3344 struct bnxt *bp = netdev_priv(dev);
3345
3346 if (dump->flag > BNXT_DUMP_CRASH) {
3347 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n");
3348 return -EINVAL;
3349 }
3350
3351 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) {
3352 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
3353 return -EOPNOTSUPP;
3354 }
3355
3356 bp->dump_flag = dump->flag;
3357 return 0;
3358}
3359
6c5657d0
VV		 3360static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
3361{
3362 struct bnxt *bp = netdev_priv(dev);
3363
3364 if (bp->hwrm_spec_code < 0x10801)
3365 return -EOPNOTSUPP;
3366
3367 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
3368 bp->ver_resp.hwrm_fw_min_8b << 16 |
3369 bp->ver_resp.hwrm_fw_bld_8b << 8 |
3370 bp->ver_resp.hwrm_fw_rsvd_8b;
3371
0b0eacf3
VV		 3372 dump->flag = bp->dump_flag;
3373 if (bp->dump_flag == BNXT_DUMP_CRASH)
3374 dump->len = BNXT_CRASH_DUMP_LEN;
3375 else
3376 bnxt_get_coredump(bp, NULL, &dump->len);
3377 return 0;
6c5657d0
VV		 3378}
3379
3380static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
3381 void *buf)
3382{
3383 struct bnxt *bp = netdev_priv(dev);
3384
3385 if (bp->hwrm_spec_code < 0x10801)
3386 return -EOPNOTSUPP;
3387
3388 memset(buf, 0, dump->len);
3389
0b0eacf3
VV		 3390 dump->flag = bp->dump_flag;
3391 if (dump->flag == BNXT_DUMP_CRASH) {
3392#ifdef CONFIG_TEE_BNXT_FW
3393 return tee_bnxt_copy_coredump(buf, 0, dump->len);
3394#endif
3395 } else {
3396 return bnxt_get_coredump(bp, buf, &dump->len);
3397 }
3398
3399 return 0;
6c5657d0
VV		 3400}
3401
eb513658
MC		 3402void bnxt_ethtool_init(struct bnxt *bp)
3403{
3404 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr;
3405 struct hwrm_selftest_qlist_input req = {0};
3406 struct bnxt_test_info *test_info;
431aa1eb 3407 struct net_device *dev = bp->dev;
eb513658
MC		 3408 int i, rc;
3409
691aa620
VV		 3410 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
3411 bnxt_get_pkgver(dev);
431aa1eb 3412
ba642ab7 3413 bp->num_tests = 0;
eb513658
MC		 3414 if (bp->hwrm_spec_code < 0x10704 || !BNXT_SINGLE_PF(bp))
3415 return;
3416
3417 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1);
3418 mutex_lock(&bp->hwrm_cmd_lock);
3419 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3420 if (rc)
3421 goto ethtool_init_exit;
3422
ba642ab7
MC		 3423 test_info = bp->test_info;
3424 if (!test_info)
3425 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
eb513658
MC		 3426 if (!test_info)
3427 goto ethtool_init_exit;
3428
3429 bp->test_info = test_info;
3430 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
3431 if (bp->num_tests > BNXT_MAX_TEST)
3432 bp->num_tests = BNXT_MAX_TEST;
3433
3434 test_info->offline_mask = resp->offline_tests;
3435 test_info->timeout = le16_to_cpu(resp->test_timeout);
3436 if (!test_info->timeout)
3437 test_info->timeout = HWRM_CMD_TIMEOUT;
3438 for (i = 0; i < bp->num_tests; i++) {
3439 char *str = test_info->string[i];
3440 char *fw_str = resp->test0_name + i * 32;
3441
f7dc1ea6
MC		 3442 if (i == BNXT_MACLPBK_TEST_IDX) {
3443 strcpy(str, "Mac loopback test (offline)");
91725d89
MC		 3444 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
3445 strcpy(str, "Phy loopback test (offline)");
55fd0cf3
MC		 3446 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
3447 strcpy(str, "Ext loopback test (offline)");
67fea463
MC		 3448 } else if (i == BNXT_IRQ_TEST_IDX) {
3449 strcpy(str, "Interrupt_test (offline)");
f7dc1ea6
MC		 3450 } else {
3451 strlcpy(str, fw_str, ETH_GSTRING_LEN);
3452 strncat(str, " test", ETH_GSTRING_LEN - strlen(str));
3453 if (test_info->offline_mask & (1 << i))
3454 strncat(str, " (offline)",
3455 ETH_GSTRING_LEN - strlen(str));
3456 else
3457 strncat(str, " (online)",
3458 ETH_GSTRING_LEN - strlen(str));
3459 }
eb513658
MC		 3460 }
3461
3462ethtool_init_exit:
3463 mutex_unlock(&bp->hwrm_cmd_lock);
3464}
3465
3466void bnxt_ethtool_free(struct bnxt *bp)
3467{
3468 kfree(bp->test_info);
3469 bp->test_info = NULL;
3470}
3471
c0c050c5 3472const struct ethtool_ops bnxt_ethtool_ops = {
f704d243
JK		 3473 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3474 ETHTOOL_COALESCE_MAX_FRAMES |
3475 ETHTOOL_COALESCE_USECS_IRQ |
3476 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
3477 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
3478 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
00c04a92
MC		 3479 .get_link_ksettings = bnxt_get_link_ksettings,
3480 .set_link_ksettings = bnxt_set_link_ksettings,
c0c050c5
MC		 3481 .get_pauseparam = bnxt_get_pauseparam,
3482 .set_pauseparam = bnxt_set_pauseparam,
3483 .get_drvinfo = bnxt_get_drvinfo,
8e202366 3484 .get_wol = bnxt_get_wol,
5282db6c 3485 .set_wol = bnxt_set_wol,
c0c050c5
MC		 3486 .get_coalesce = bnxt_get_coalesce,
3487 .set_coalesce = bnxt_set_coalesce,
3488 .get_msglevel = bnxt_get_msglevel,
3489 .set_msglevel = bnxt_set_msglevel,
3490 .get_sset_count = bnxt_get_sset_count,
3491 .get_strings = bnxt_get_strings,
3492 .get_ethtool_stats = bnxt_get_ethtool_stats,
3493 .set_ringparam = bnxt_set_ringparam,
3494 .get_ringparam = bnxt_get_ringparam,
3495 .get_channels = bnxt_get_channels,
3496 .set_channels = bnxt_set_channels,
c0c050c5 3497 .get_rxnfc = bnxt_get_rxnfc,
a011952a 3498 .set_rxnfc = bnxt_set_rxnfc,
c0c050c5
MC		 3499 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
3500 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
3501 .get_rxfh = bnxt_get_rxfh,
3502 .flash_device = bnxt_flash_device,
3503 .get_eeprom_len = bnxt_get_eeprom_len,
3504 .get_eeprom = bnxt_get_eeprom,
3505 .set_eeprom = bnxt_set_eeprom,
3506 .get_link = bnxt_get_link,
72b34f04
MC		 3507 .get_eee = bnxt_get_eee,
3508 .set_eee = bnxt_set_eee,
42ee18fe
AK		 3509 .get_module_info = bnxt_get_module_info,
3510 .get_module_eeprom = bnxt_get_module_eeprom,
5ad2cbee
MC		 3511 .nway_reset = bnxt_nway_reset,
3512 .set_phys_id = bnxt_set_phys_id,
eb513658 3513 .self_test = bnxt_self_test,
49f7972f 3514 .reset = bnxt_reset,
0b0eacf3 3515 .set_dump = bnxt_set_dump,
6c5657d0
VV		 3516 .get_dump_flag = bnxt_get_dump_flag,
3517 .get_dump_data = bnxt_get_dump_data,
c0c050c5 3518};
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