[thirdparty/kernel/linux.git] / drivers / net / ethernet / chelsio / cxgb / my3126.c

// SPDX-License-Identifier: GPL-2.0
/* $Date: 2005/11/12 02:13:49 $ $RCSfile: my3126.c,v $ $Revision: 1.15 $ */
#include "cphy.h"
#include "elmer0.h"
#include "suni1x10gexp_regs.h"

/* Port Reset */
static int my3126_reset(struct cphy *cphy, int wait)
{
	/*
	 * This can be done through registers.  It is not required since
	 * a full chip reset is used.
	 */
	return 0;
}

static int my3126_interrupt_enable(struct cphy *cphy)
{
	schedule_delayed_work(&cphy->phy_update, HZ/30);
	t1_tpi_read(cphy->adapter, A_ELMER0_GPO, &cphy->elmer_gpo);
	return 0;
}

static int my3126_interrupt_disable(struct cphy *cphy)
{
	cancel_delayed_work_sync(&cphy->phy_update);
	return 0;
}

static int my3126_interrupt_clear(struct cphy *cphy)
{
	return 0;
}

#define OFFSET(REG_ADDR)    (REG_ADDR << 2)

static int my3126_interrupt_handler(struct cphy *cphy)
{
	u32 val;
	u16 val16;
	u16 status;
	u32 act_count;
	adapter_t *adapter;
	adapter = cphy->adapter;

	if (cphy->count == 50) {
		cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
		val16 = (u16) val;
		status = cphy->bmsr ^ val16;

		if (status & MDIO_STAT1_LSTATUS)
			t1_link_changed(adapter, 0);
		cphy->bmsr = val16;

		/* We have only enabled link change interrupts so it
		   must be that
		 */
		cphy->count = 0;
	}

	t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL),
		SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
	t1_tpi_read(adapter,
		OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW), &act_count);
	t1_tpi_read(adapter,
		OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val);
	act_count += val;

	/* Populate elmer_gpo with the register value */
	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	cphy->elmer_gpo = val;

	if ( (val & (1 << 8)) || (val & (1 << 19)) ||
	     (cphy->act_count == act_count) || cphy->act_on ) {
		if (is_T2(adapter))
			val |= (1 << 9);
		else if (t1_is_T1B(adapter))
			val |= (1 << 20);
		cphy->act_on = 0;
	} else {
		if (is_T2(adapter))
			val &= ~(1 << 9);
		else if (t1_is_T1B(adapter))
			val &= ~(1 << 20);
		cphy->act_on = 1;
	}

	t1_tpi_write(adapter, A_ELMER0_GPO, val);

	cphy->elmer_gpo = val;
	cphy->act_count = act_count;
	cphy->count++;

	return cphy_cause_link_change;
}

static void my3216_poll(struct work_struct *work)
{
	struct cphy *cphy = container_of(work, struct cphy, phy_update.work);

	my3126_interrupt_handler(cphy);
}

static int my3126_set_loopback(struct cphy *cphy, int on)
{
	return 0;
}

/* To check the activity LED */
static int my3126_get_link_status(struct cphy *cphy,
			int *link_ok, int *speed, int *duplex, int *fc)
{
	u32 val;
	u16 val16;
	adapter_t *adapter;

	adapter = cphy->adapter;
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
	val16 = (u16) val;

	/* Populate elmer_gpo with the register value */
	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	cphy->elmer_gpo = val;

	*link_ok = (val16 & MDIO_STAT1_LSTATUS);

	if (*link_ok) {
		/* Turn on the LED. */
		if (is_T2(adapter))
			 val &= ~(1 << 8);
		else if (t1_is_T1B(adapter))
			 val &= ~(1 << 19);
	} else {
		/* Turn off the LED. */
		if (is_T2(adapter))
			 val |= (1 << 8);
		else if (t1_is_T1B(adapter))
			 val |= (1 << 19);
	}

	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	cphy->elmer_gpo = val;
	*speed = SPEED_10000;
	*duplex = DUPLEX_FULL;

	/* need to add flow control */
	if (fc)
		*fc = PAUSE_RX | PAUSE_TX;

	return 0;
}

static void my3126_destroy(struct cphy *cphy)
{
	kfree(cphy);
}

static const struct cphy_ops my3126_ops = {
	.destroy		= my3126_destroy,
	.reset			= my3126_reset,
	.interrupt_enable	= my3126_interrupt_enable,
	.interrupt_disable	= my3126_interrupt_disable,
	.interrupt_clear	= my3126_interrupt_clear,
	.interrupt_handler	= my3126_interrupt_handler,
	.get_link_status	= my3126_get_link_status,
	.set_loopback		= my3126_set_loopback,
	.mmds			= (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
				   MDIO_DEVS_PHYXS),
};

static struct cphy *my3126_phy_create(struct net_device *dev,
			int phy_addr, const struct mdio_ops *mdio_ops)
{
	struct cphy *cphy = kzalloc(sizeof (*cphy), GFP_KERNEL);

	if (!cphy)
		return NULL;

	cphy_init(cphy, dev, phy_addr, &my3126_ops, mdio_ops);
	INIT_DELAYED_WORK(&cphy->phy_update, my3216_poll);
	cphy->bmsr = 0;

	return cphy;
}

/* Chip Reset */
static int my3126_phy_reset(adapter_t * adapter)
{
	u32 val;

	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	val &= ~4;
	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	msleep(100);

	t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
	msleep(1000);

	/* Now lets enable the Laser. Delay 100us */
	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	val |= 0x8000;
	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	udelay(100);
	return 0;
}

const struct gphy t1_my3126_ops = {
	.create = my3126_phy_create,
	.reset = my3126_phy_reset
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
f1d3d38a SH	2	/* $Date: 2005/11/12 02:13:49 $ $RCSfile: my3126.c,v $ $Revision: 1.15 $ */
	3	#include "cphy.h"
	4	#include "elmer0.h"
	5	#include "suni1x10gexp_regs.h"
	6
	7	/* Port Reset */
	8	static int my3126_reset(struct cphy *cphy, int wait)
	9	{
	10	/*
	11	* This can be done through registers. It is not required since
	12	* a full chip reset is used.
	13	*/
b7d58394	14	return 0;
f1d3d38a SH	15	}
	16
	17	static int my3126_interrupt_enable(struct cphy *cphy)
	18	{
	19	schedule_delayed_work(&cphy->phy_update, HZ/30);
	20	t1_tpi_read(cphy->adapter, A_ELMER0_GPO, &cphy->elmer_gpo);
b7d58394	21	return 0;
f1d3d38a SH	22	}
	23
	24	static int my3126_interrupt_disable(struct cphy *cphy)
	25	{
afe2c511	26	cancel_delayed_work_sync(&cphy->phy_update);
b7d58394	27	return 0;
f1d3d38a SH	28	}
	29
	30	static int my3126_interrupt_clear(struct cphy *cphy)
	31	{
b7d58394	32	return 0;
f1d3d38a SH	33	}
	34
	35	#define OFFSET(REG_ADDR) (REG_ADDR << 2)
	36
	37	static int my3126_interrupt_handler(struct cphy *cphy)
	38	{
	39	u32 val;
	40	u16 val16;
	41	u16 status;
	42	u32 act_count;
	43	adapter_t *adapter;
	44	adapter = cphy->adapter;
	45
	46	if (cphy->count == 50) {
23c3320c	47	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
f1d3d38a SH	48	val16 = (u16) val;
	49	status = cphy->bmsr ^ val16;
	50
23c3320c	51	if (status & MDIO_STAT1_LSTATUS)
f1d3d38a SH	52	t1_link_changed(adapter, 0);
	53	cphy->bmsr = val16;
	54
	55	/* We have only enabled link change interrupts so it
	56	must be that
	57	*/
	58	cphy->count = 0;
	59	}
	60
	61	t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL),
	62	SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
	63	t1_tpi_read(adapter,
	64	OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW), &act_count);
	65	t1_tpi_read(adapter,
	66	OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val);
	67	act_count += val;
	68
	69	/* Populate elmer_gpo with the register value */
	70	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	71	cphy->elmer_gpo = val;
	72
	73	if ( (val & (1 << 8)) \|\| (val & (1 << 19)) \|\|
	74	(cphy->act_count == act_count) \|\| cphy->act_on ) {
	75	if (is_T2(adapter))
	76	val \|= (1 << 9);
	77	else if (t1_is_T1B(adapter))
	78	val \|= (1 << 20);
	79	cphy->act_on = 0;
	80	} else {
	81	if (is_T2(adapter))
	82	val &= ~(1 << 9);
	83	else if (t1_is_T1B(adapter))
	84	val &= ~(1 << 20);
	85	cphy->act_on = 1;
	86	}
	87
	88	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	89
	90	cphy->elmer_gpo = val;
	91	cphy->act_count = act_count;
	92	cphy->count++;
	93
	94	return cphy_cause_link_change;
	95	}
	96
6d5aefb8	97	static void my3216_poll(struct work_struct *work)
f1d3d38a	98	{
6d5aefb8 DH	99	struct cphy *cphy = container_of(work, struct cphy, phy_update.work);
	100
	101	my3126_interrupt_handler(cphy);
f1d3d38a SH	102	}
	103
	104	static int my3126_set_loopback(struct cphy *cphy, int on)
	105	{
b7d58394	106	return 0;
f1d3d38a SH	107	}
	108
	109	/* To check the activity LED */
	110	static int my3126_get_link_status(struct cphy *cphy,
	111	int link_ok, int speed, int duplex, int fc)
	112	{
	113	u32 val;
	114	u16 val16;
	115	adapter_t *adapter;
	116
	117	adapter = cphy->adapter;
23c3320c	118	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
f1d3d38a SH	119	val16 = (u16) val;
	120
	121	/* Populate elmer_gpo with the register value */
	122	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	123	cphy->elmer_gpo = val;
	124
23c3320c	125	*link_ok = (val16 & MDIO_STAT1_LSTATUS);
f1d3d38a SH	126
	127	if (*link_ok) {
	128	/* Turn on the LED. */
	129	if (is_T2(adapter))
	130	val &= ~(1 << 8);
	131	else if (t1_is_T1B(adapter))
	132	val &= ~(1 << 19);
	133	} else {
	134	/* Turn off the LED. */
	135	if (is_T2(adapter))
	136	val \|= (1 << 8);
	137	else if (t1_is_T1B(adapter))
	138	val \|= (1 << 19);
	139	}
	140
	141	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	142	cphy->elmer_gpo = val;
	143	*speed = SPEED_10000;
	144	*duplex = DUPLEX_FULL;
	145
	146	/* need to add flow control */
	147	if (fc)
	148	*fc = PAUSE_RX \| PAUSE_TX;
	149
b7d58394	150	return 0;
f1d3d38a SH	151	}
	152
	153	static void my3126_destroy(struct cphy *cphy)
	154	{
	155	kfree(cphy);
	156	}
	157
46f85a92	158	static const struct cphy_ops my3126_ops = {
f1d3d38a SH	159	.destroy = my3126_destroy,
	160	.reset = my3126_reset,
	161	.interrupt_enable = my3126_interrupt_enable,
	162	.interrupt_disable = my3126_interrupt_disable,
	163	.interrupt_clear = my3126_interrupt_clear,
	164	.interrupt_handler = my3126_interrupt_handler,
	165	.get_link_status = my3126_get_link_status,
	166	.set_loopback = my3126_set_loopback,
23c3320c BH	167	.mmds = (MDIO_DEVS_PMAPMD \| MDIO_DEVS_PCS \|
23c3320c BH	168	MDIO_DEVS_PHYXS),
f1d3d38a SH	169	};
f1d3d38a SH	170
703cebab	171	static struct cphy my3126_phy_create(struct net_device dev,
459e536b	172	int phy_addr, const struct mdio_ops *mdio_ops)
f1d3d38a SH	173	{
	174	struct cphy cphy = kzalloc(sizeof (cphy), GFP_KERNEL);
	175
ab3b1c7e SH	176	if (!cphy)
ab3b1c7e SH	177	return NULL;
f1d3d38a	178
703cebab	179	cphy_init(cphy, dev, phy_addr, &my3126_ops, mdio_ops);
6d5aefb8	180	INIT_DELAYED_WORK(&cphy->phy_update, my3216_poll);
f1d3d38a SH	181	cphy->bmsr = 0;
f1d3d38a SH	182
b7d58394	183	return cphy;
f1d3d38a SH	184	}
	185
	186	/* Chip Reset */
	187	static int my3126_phy_reset(adapter_t * adapter)
	188	{
	189	u32 val;
	190
	191	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	192	val &= ~4;
	193	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	194	msleep(100);
	195
	196	t1_tpi_write(adapter, A_ELMER0_GPO, val \| 4);
	197	msleep(1000);
	198
	199	/* Now lets enable the Laser. Delay 100us */
	200	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	201	val \|= 0x8000;
	202	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	203	udelay(100);
b7d58394	204	return 0;
f1d3d38a SH	205	}
f1d3d38a SH	206
459e536b SH	207	const struct gphy t1_my3126_ops = {
	208	.create = my3126_phy_create,
	209	.reset = my3126_phy_reset
f1d3d38a	210	};