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cxgb4: memory corruption in debugfs
[thirdparty/kernel/stable.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_debugfs.c
CommitLineData
fd88b31a
HS		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/seq_file.h>
36#include <linux/debugfs.h>
37#include <linux/string_helpers.h>
38#include <linux/sort.h>
688ea5fe 39#include <linux/ctype.h>
fd88b31a
HS		 40
41#include "cxgb4.h"
42#include "t4_regs.h"
bf7c781d 43#include "t4_values.h"
fd88b31a
HS		 44#include "t4fw_api.h"
45#include "cxgb4_debugfs.h"
b5a02f50 46#include "clip_tbl.h"
fd88b31a
HS		 47#include "l2t.h"
48
f1ff24aa
HS		 49/* generic seq_file support for showing a table of size rows x width. */
50static void *seq_tab_get_idx(struct seq_tab *tb, loff_t pos)
51{
52 pos -= tb->skip_first;
53 return pos >= tb->rows ? NULL : &tb->data[pos * tb->width];
54}
55
56static void *seq_tab_start(struct seq_file *seq, loff_t *pos)
57{
58 struct seq_tab *tb = seq->private;
59
60 if (tb->skip_first && *pos == 0)
61 return SEQ_START_TOKEN;
62
63 return seq_tab_get_idx(tb, *pos);
64}
65
66static void *seq_tab_next(struct seq_file *seq, void *v, loff_t *pos)
67{
68 v = seq_tab_get_idx(seq->private, *pos + 1);
69 if (v)
70 ++*pos;
71 return v;
72}
73
74static void seq_tab_stop(struct seq_file *seq, void *v)
75{
76}
77
78static int seq_tab_show(struct seq_file *seq, void *v)
79{
80 const struct seq_tab *tb = seq->private;
81
82 return tb->show(seq, v, ((char *)v - tb->data) / tb->width);
83}
84
85static const struct seq_operations seq_tab_ops = {
86 .start = seq_tab_start,
87 .next = seq_tab_next,
88 .stop = seq_tab_stop,
89 .show = seq_tab_show
90};
91
92struct seq_tab *seq_open_tab(struct file *f, unsigned int rows,
93 unsigned int width, unsigned int have_header,
94 int (*show)(struct seq_file *seq, void *v, int i))
95{
96 struct seq_tab *p;
97
98 p = __seq_open_private(f, &seq_tab_ops, sizeof(*p) + rows * width);
99 if (p) {
100 p->show = show;
101 p->rows = rows;
102 p->width = width;
103 p->skip_first = have_header != 0;
104 }
105 return p;
106}
107
c778af7d
HS		 108/* Trim the size of a seq_tab to the supplied number of rows. The operation is
109 * irreversible.
110 */
111static int seq_tab_trim(struct seq_tab *p, unsigned int new_rows)
112{
113 if (new_rows > p->rows)
114 return -EINVAL;
115 p->rows = new_rows;
116 return 0;
117}
118
f1ff24aa
HS		 119static int cim_la_show(struct seq_file *seq, void *v, int idx)
120{
121 if (v == SEQ_START_TOKEN)
122 seq_puts(seq, "Status Data PC LS0Stat LS0Addr "
123 " LS0Data\n");
124 else {
125 const u32 *p = v;
126
127 seq_printf(seq,
128 " %02x %x%07x %x%07x %08x %08x %08x%08x%08x%08x\n",
129 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
130 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
131 p[6], p[7]);
132 }
133 return 0;
134}
135
136static int cim_la_show_3in1(struct seq_file *seq, void *v, int idx)
137{
138 if (v == SEQ_START_TOKEN) {
139 seq_puts(seq, "Status Data PC\n");
140 } else {
141 const u32 *p = v;
142
143 seq_printf(seq, " %02x %08x %08x\n", p[5] & 0xff, p[6],
144 p[7]);
145 seq_printf(seq, " %02x %02x%06x %02x%06x\n",
146 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
147 p[4] & 0xff, p[5] >> 8);
148 seq_printf(seq, " %02x %x%07x %x%07x\n", (p[0] >> 4) & 0xff,
149 p[0] & 0xf, p[1] >> 4, p[1] & 0xf, p[2] >> 4);
150 }
151 return 0;
152}
153
b7660642
HS		 154static int cim_la_show_t6(struct seq_file *seq, void *v, int idx)
155{
156 if (v == SEQ_START_TOKEN) {
157 seq_puts(seq, "Status Inst Data PC LS0Stat "
158 "LS0Addr LS0Data LS1Stat LS1Addr LS1Data\n");
159 } else {
160 const u32 *p = v;
161
162 seq_printf(seq, " %02x %04x%04x %04x%04x %04x%04x %08x %08x %08x %08x %08x %08x\n",
163 (p[9] >> 16) & 0xff, /* Status */
164 p[9] & 0xffff, p[8] >> 16, /* Inst */
165 p[8] & 0xffff, p[7] >> 16, /* Data */
166 p[7] & 0xffff, p[6] >> 16, /* PC */
167 p[2], p[1], p[0], /* LS0 Stat, Addr and Data */
168 p[5], p[4], p[3]); /* LS1 Stat, Addr and Data */
169 }
170 return 0;
171}
172
173static int cim_la_show_pc_t6(struct seq_file *seq, void *v, int idx)
174{
175 if (v == SEQ_START_TOKEN) {
176 seq_puts(seq, "Status Inst Data PC\n");
177 } else {
178 const u32 *p = v;
179
180 seq_printf(seq, " %02x %08x %08x %08x\n",
181 p[3] & 0xff, p[2], p[1], p[0]);
182 seq_printf(seq, " %02x %02x%06x %02x%06x %02x%06x\n",
183 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
184 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
185 seq_printf(seq, " %02x %04x%04x %04x%04x %04x%04x\n",
186 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
187 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
188 p[6] >> 16);
189 }
190 return 0;
191}
192
f1ff24aa
HS		 193static int cim_la_open(struct inode *inode, struct file *file)
194{
195 int ret;
196 unsigned int cfg;
197 struct seq_tab *p;
198 struct adapter *adap = inode->i_private;
199
200 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
201 if (ret)
202 return ret;
203
b7660642
HS		 204 if (is_t6(adap->params.chip)) {
205 /* +1 to account for integer division of CIMLA_SIZE/10 */
206 p = seq_open_tab(file, (adap->params.cim_la_size / 10) + 1,
207 10 * sizeof(u32), 1,
208 cfg & UPDBGLACAPTPCONLY_F ?
209 cim_la_show_pc_t6 : cim_la_show_t6);
210 } else {
211 p = seq_open_tab(file, adap->params.cim_la_size / 8,
212 8 * sizeof(u32), 1,
213 cfg & UPDBGLACAPTPCONLY_F ? cim_la_show_3in1 :
214 cim_la_show);
215 }
f1ff24aa
HS		 216 if (!p)
217 return -ENOMEM;
218
219 ret = t4_cim_read_la(adap, (u32 *)p->data, NULL);
220 if (ret)
221 seq_release_private(inode, file);
222 return ret;
223}
224
225static const struct file_operations cim_la_fops = {
226 .owner = THIS_MODULE,
227 .open = cim_la_open,
228 .read = seq_read,
229 .llseek = seq_lseek,
230 .release = seq_release_private
231};
232
19689609
HS		 233static int cim_pif_la_show(struct seq_file *seq, void *v, int idx)
234{
235 const u32 *p = v;
236
237 if (v == SEQ_START_TOKEN) {
238 seq_puts(seq, "Cntl ID DataBE Addr Data\n");
239 } else if (idx < CIM_PIFLA_SIZE) {
240 seq_printf(seq, " %02x %02x %04x %08x %08x%08x%08x%08x\n",
241 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f,
242 p[5] & 0xffff, p[4], p[3], p[2], p[1], p[0]);
243 } else {
244 if (idx == CIM_PIFLA_SIZE)
245 seq_puts(seq, "\nCntl ID Data\n");
246 seq_printf(seq, " %02x %02x %08x%08x%08x%08x\n",
247 (p[4] >> 6) & 0xff, p[4] & 0x3f,
248 p[3], p[2], p[1], p[0]);
249 }
250 return 0;
251}
252
253static int cim_pif_la_open(struct inode *inode, struct file *file)
254{
255 struct seq_tab *p;
256 struct adapter *adap = inode->i_private;
257
258 p = seq_open_tab(file, 2 * CIM_PIFLA_SIZE, 6 * sizeof(u32), 1,
259 cim_pif_la_show);
260 if (!p)
261 return -ENOMEM;
262
263 t4_cim_read_pif_la(adap, (u32 *)p->data,
264 (u32 *)p->data + 6 * CIM_PIFLA_SIZE, NULL, NULL);
265 return 0;
266}
267
268static const struct file_operations cim_pif_la_fops = {
269 .owner = THIS_MODULE,
270 .open = cim_pif_la_open,
271 .read = seq_read,
272 .llseek = seq_lseek,
273 .release = seq_release_private
274};
275
26fae93f
HS		 276static int cim_ma_la_show(struct seq_file *seq, void *v, int idx)
277{
278 const u32 *p = v;
279
280 if (v == SEQ_START_TOKEN) {
281 seq_puts(seq, "\n");
282 } else if (idx < CIM_MALA_SIZE) {
283 seq_printf(seq, "%02x%08x%08x%08x%08x\n",
284 p[4], p[3], p[2], p[1], p[0]);
285 } else {
286 if (idx == CIM_MALA_SIZE)
287 seq_puts(seq,
288 "\nCnt ID Tag UE Data RDY VLD\n");
289 seq_printf(seq, "%3u %2u %x %u %08x%08x %u %u\n",
290 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
291 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
292 (p[1] >> 2) | ((p[2] & 3) << 30),
293 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
294 p[0] & 1);
295 }
296 return 0;
297}
298
299static int cim_ma_la_open(struct inode *inode, struct file *file)
300{
301 struct seq_tab *p;
302 struct adapter *adap = inode->i_private;
303
304 p = seq_open_tab(file, 2 * CIM_MALA_SIZE, 5 * sizeof(u32), 1,
305 cim_ma_la_show);
306 if (!p)
307 return -ENOMEM;
308
309 t4_cim_read_ma_la(adap, (u32 *)p->data,
310 (u32 *)p->data + 5 * CIM_MALA_SIZE);
311 return 0;
312}
313
314static const struct file_operations cim_ma_la_fops = {
315 .owner = THIS_MODULE,
316 .open = cim_ma_la_open,
317 .read = seq_read,
318 .llseek = seq_lseek,
319 .release = seq_release_private
320};
321
74b3092c
HS		 322static int cim_qcfg_show(struct seq_file *seq, void *v)
323{
324 static const char * const qname[] = {
325 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",
326 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",
327 "SGE0-RX", "SGE1-RX"
328 };
329
330 int i;
331 struct adapter *adap = seq->private;
332 u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
333 u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
334 u32 stat[(4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5))];
335 u16 thres[CIM_NUM_IBQ];
336 u32 obq_wr_t4[2 * CIM_NUM_OBQ], *wr;
337 u32 obq_wr_t5[2 * CIM_NUM_OBQ_T5];
338 u32 *p = stat;
339 int cim_num_obq = is_t4(adap->params.chip) ?
340 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
341
342 i = t4_cim_read(adap, is_t4(adap->params.chip) ? UP_IBQ_0_RDADDR_A :
343 UP_IBQ_0_SHADOW_RDADDR_A,
344 ARRAY_SIZE(stat), stat);
345 if (!i) {
346 if (is_t4(adap->params.chip)) {
347 i = t4_cim_read(adap, UP_OBQ_0_REALADDR_A,
348 ARRAY_SIZE(obq_wr_t4), obq_wr_t4);
2f3a8732 349 wr = obq_wr_t4;
74b3092c
HS		 350 } else {
351 i = t4_cim_read(adap, UP_OBQ_0_SHADOW_REALADDR_A,
352 ARRAY_SIZE(obq_wr_t5), obq_wr_t5);
2f3a8732 353 wr = obq_wr_t5;
74b3092c
HS		 354 }
355 }
356 if (i)
357 return i;
358
359 t4_read_cimq_cfg(adap, base, size, thres);
360
361 seq_printf(seq,
362 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail\n");
363 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
364 seq_printf(seq, "%7s %5x %5u %5u %6x %4x %4u %4u %5u\n",
365 qname[i], base[i], size[i], thres[i],
366 IBQRDADDR_G(p[0]), IBQWRADDR_G(p[1]),
367 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
368 QUEREMFLITS_G(p[2]) * 16);
369 for ( ; i < CIM_NUM_IBQ + cim_num_obq; i++, p += 4, wr += 2)
370 seq_printf(seq, "%7s %5x %5u %12x %4x %4u %4u %5u\n",
371 qname[i], base[i], size[i],
372 QUERDADDR_G(p[0]) & 0x3fff, wr[0] - base[i],
373 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
374 QUEREMFLITS_G(p[2]) * 16);
375 return 0;
376}
377
378static int cim_qcfg_open(struct inode *inode, struct file *file)
379{
380 return single_open(file, cim_qcfg_show, inode->i_private);
381}
382
383static const struct file_operations cim_qcfg_fops = {
384 .owner = THIS_MODULE,
385 .open = cim_qcfg_open,
386 .read = seq_read,
387 .llseek = seq_lseek,
388 .release = single_release,
389};
390
e5f0e43b
HS		 391static int cimq_show(struct seq_file *seq, void *v, int idx)
392{
393 const u32 *p = v;
394
395 seq_printf(seq, "%#06x: %08x %08x %08x %08x\n", idx * 16, p[0], p[1],
396 p[2], p[3]);
397 return 0;
398}
399
400static int cim_ibq_open(struct inode *inode, struct file *file)
401{
402 int ret;
403 struct seq_tab *p;
404 unsigned int qid = (uintptr_t)inode->i_private & 7;
405 struct adapter *adap = inode->i_private - qid;
406
407 p = seq_open_tab(file, CIM_IBQ_SIZE, 4 * sizeof(u32), 0, cimq_show);
408 if (!p)
409 return -ENOMEM;
410
411 ret = t4_read_cim_ibq(adap, qid, (u32 *)p->data, CIM_IBQ_SIZE * 4);
412 if (ret < 0)
413 seq_release_private(inode, file);
414 else
415 ret = 0;
416 return ret;
417}
418
419static const struct file_operations cim_ibq_fops = {
420 .owner = THIS_MODULE,
421 .open = cim_ibq_open,
422 .read = seq_read,
423 .llseek = seq_lseek,
424 .release = seq_release_private
425};
426
c778af7d
HS		 427static int cim_obq_open(struct inode *inode, struct file *file)
428{
429 int ret;
430 struct seq_tab *p;
431 unsigned int qid = (uintptr_t)inode->i_private & 7;
432 struct adapter *adap = inode->i_private - qid;
433
434 p = seq_open_tab(file, 6 * CIM_OBQ_SIZE, 4 * sizeof(u32), 0, cimq_show);
435 if (!p)
436 return -ENOMEM;
437
438 ret = t4_read_cim_obq(adap, qid, (u32 *)p->data, 6 * CIM_OBQ_SIZE * 4);
439 if (ret < 0) {
440 seq_release_private(inode, file);
441 } else {
442 seq_tab_trim(p, ret / 4);
443 ret = 0;
444 }
445 return ret;
446}
447
448static const struct file_operations cim_obq_fops = {
449 .owner = THIS_MODULE,
450 .open = cim_obq_open,
451 .read = seq_read,
452 .llseek = seq_lseek,
453 .release = seq_release_private
454};
455
2d277b3b
HS		 456struct field_desc {
457 const char *name;
458 unsigned int start;
459 unsigned int width;
460};
461
462static void field_desc_show(struct seq_file *seq, u64 v,
463 const struct field_desc *p)
464{
465 char buf[32];
466 int line_size = 0;
467
468 while (p->name) {
469 u64 mask = (1ULL << p->width) - 1;
470 int len = scnprintf(buf, sizeof(buf), "%s: %llu", p->name,
471 ((unsigned long long)v >> p->start) & mask);
472
473 if (line_size + len >= 79) {
474 line_size = 8;
475 seq_puts(seq, "\n ");
476 }
477 seq_printf(seq, "%s ", buf);
478 line_size += len + 1;
479 p++;
480 }
481 seq_putc(seq, '\n');
482}
483
484static struct field_desc tp_la0[] = {
485 { "RcfOpCodeOut", 60, 4 },
486 { "State", 56, 4 },
487 { "WcfState", 52, 4 },
488 { "RcfOpcSrcOut", 50, 2 },
489 { "CRxError", 49, 1 },
490 { "ERxError", 48, 1 },
491 { "SanityFailed", 47, 1 },
492 { "SpuriousMsg", 46, 1 },
493 { "FlushInputMsg", 45, 1 },
494 { "FlushInputCpl", 44, 1 },
495 { "RssUpBit", 43, 1 },
496 { "RssFilterHit", 42, 1 },
497 { "Tid", 32, 10 },
498 { "InitTcb", 31, 1 },
499 { "LineNumber", 24, 7 },
500 { "Emsg", 23, 1 },
501 { "EdataOut", 22, 1 },
502 { "Cmsg", 21, 1 },
503 { "CdataOut", 20, 1 },
504 { "EreadPdu", 19, 1 },
505 { "CreadPdu", 18, 1 },
506 { "TunnelPkt", 17, 1 },
507 { "RcfPeerFin", 16, 1 },
508 { "RcfReasonOut", 12, 4 },
509 { "TxCchannel", 10, 2 },
510 { "RcfTxChannel", 8, 2 },
511 { "RxEchannel", 6, 2 },
512 { "RcfRxChannel", 5, 1 },
513 { "RcfDataOutSrdy", 4, 1 },
514 { "RxDvld", 3, 1 },
515 { "RxOoDvld", 2, 1 },
516 { "RxCongestion", 1, 1 },
517 { "TxCongestion", 0, 1 },
518 { NULL }
519};
520
521static int tp_la_show(struct seq_file *seq, void *v, int idx)
522{
523 const u64 *p = v;
524
525 field_desc_show(seq, *p, tp_la0);
526 return 0;
527}
528
529static int tp_la_show2(struct seq_file *seq, void *v, int idx)
530{
531 const u64 *p = v;
532
533 if (idx)
534 seq_putc(seq, '\n');
535 field_desc_show(seq, p[0], tp_la0);
536 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
537 field_desc_show(seq, p[1], tp_la0);
538 return 0;
539}
540
541static int tp_la_show3(struct seq_file *seq, void *v, int idx)
542{
543 static struct field_desc tp_la1[] = {
544 { "CplCmdIn", 56, 8 },
545 { "CplCmdOut", 48, 8 },
546 { "ESynOut", 47, 1 },
547 { "EAckOut", 46, 1 },
548 { "EFinOut", 45, 1 },
549 { "ERstOut", 44, 1 },
550 { "SynIn", 43, 1 },
551 { "AckIn", 42, 1 },
552 { "FinIn", 41, 1 },
553 { "RstIn", 40, 1 },
554 { "DataIn", 39, 1 },
555 { "DataInVld", 38, 1 },
556 { "PadIn", 37, 1 },
557 { "RxBufEmpty", 36, 1 },
558 { "RxDdp", 35, 1 },
559 { "RxFbCongestion", 34, 1 },
560 { "TxFbCongestion", 33, 1 },
561 { "TxPktSumSrdy", 32, 1 },
562 { "RcfUlpType", 28, 4 },
563 { "Eread", 27, 1 },
564 { "Ebypass", 26, 1 },
565 { "Esave", 25, 1 },
566 { "Static0", 24, 1 },
567 { "Cread", 23, 1 },
568 { "Cbypass", 22, 1 },
569 { "Csave", 21, 1 },
570 { "CPktOut", 20, 1 },
571 { "RxPagePoolFull", 18, 2 },
572 { "RxLpbkPkt", 17, 1 },
573 { "TxLpbkPkt", 16, 1 },
574 { "RxVfValid", 15, 1 },
575 { "SynLearned", 14, 1 },
576 { "SetDelEntry", 13, 1 },
577 { "SetInvEntry", 12, 1 },
578 { "CpcmdDvld", 11, 1 },
579 { "CpcmdSave", 10, 1 },
580 { "RxPstructsFull", 8, 2 },
581 { "EpcmdDvld", 7, 1 },
582 { "EpcmdFlush", 6, 1 },
583 { "EpcmdTrimPrefix", 5, 1 },
584 { "EpcmdTrimPostfix", 4, 1 },
585 { "ERssIp4Pkt", 3, 1 },
586 { "ERssIp6Pkt", 2, 1 },
587 { "ERssTcpUdpPkt", 1, 1 },
588 { "ERssFceFipPkt", 0, 1 },
589 { NULL }
590 };
591 static struct field_desc tp_la2[] = {
592 { "CplCmdIn", 56, 8 },
593 { "MpsVfVld", 55, 1 },
594 { "MpsPf", 52, 3 },
595 { "MpsVf", 44, 8 },
596 { "SynIn", 43, 1 },
597 { "AckIn", 42, 1 },
598 { "FinIn", 41, 1 },
599 { "RstIn", 40, 1 },
600 { "DataIn", 39, 1 },
601 { "DataInVld", 38, 1 },
602 { "PadIn", 37, 1 },
603 { "RxBufEmpty", 36, 1 },
604 { "RxDdp", 35, 1 },
605 { "RxFbCongestion", 34, 1 },
606 { "TxFbCongestion", 33, 1 },
607 { "TxPktSumSrdy", 32, 1 },
608 { "RcfUlpType", 28, 4 },
609 { "Eread", 27, 1 },
610 { "Ebypass", 26, 1 },
611 { "Esave", 25, 1 },
612 { "Static0", 24, 1 },
613 { "Cread", 23, 1 },
614 { "Cbypass", 22, 1 },
615 { "Csave", 21, 1 },
616 { "CPktOut", 20, 1 },
617 { "RxPagePoolFull", 18, 2 },
618 { "RxLpbkPkt", 17, 1 },
619 { "TxLpbkPkt", 16, 1 },
620 { "RxVfValid", 15, 1 },
621 { "SynLearned", 14, 1 },
622 { "SetDelEntry", 13, 1 },
623 { "SetInvEntry", 12, 1 },
624 { "CpcmdDvld", 11, 1 },
625 { "CpcmdSave", 10, 1 },
626 { "RxPstructsFull", 8, 2 },
627 { "EpcmdDvld", 7, 1 },
628 { "EpcmdFlush", 6, 1 },
629 { "EpcmdTrimPrefix", 5, 1 },
630 { "EpcmdTrimPostfix", 4, 1 },
631 { "ERssIp4Pkt", 3, 1 },
632 { "ERssIp6Pkt", 2, 1 },
633 { "ERssTcpUdpPkt", 1, 1 },
634 { "ERssFceFipPkt", 0, 1 },
635 { NULL }
636 };
637 const u64 *p = v;
638
639 if (idx)
640 seq_putc(seq, '\n');
641 field_desc_show(seq, p[0], tp_la0);
642 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
643 field_desc_show(seq, p[1], (p[0] & BIT(17)) ? tp_la2 : tp_la1);
644 return 0;
645}
646
647static int tp_la_open(struct inode *inode, struct file *file)
648{
649 struct seq_tab *p;
650 struct adapter *adap = inode->i_private;
651
652 switch (DBGLAMODE_G(t4_read_reg(adap, TP_DBG_LA_CONFIG_A))) {
653 case 2:
654 p = seq_open_tab(file, TPLA_SIZE / 2, 2 * sizeof(u64), 0,
655 tp_la_show2);
656 break;
657 case 3:
658 p = seq_open_tab(file, TPLA_SIZE / 2, 2 * sizeof(u64), 0,
659 tp_la_show3);
660 break;
661 default:
662 p = seq_open_tab(file, TPLA_SIZE, sizeof(u64), 0, tp_la_show);
663 }
664 if (!p)
665 return -ENOMEM;
666
667 t4_tp_read_la(adap, (u64 *)p->data, NULL);
668 return 0;
669}
670
671static ssize_t tp_la_write(struct file *file, const char __user *buf,
672 size_t count, loff_t *pos)
673{
674 int err;
675 char s[32];
676 unsigned long val;
677 size_t size = min(sizeof(s) - 1, count);
c1d81b1c 678 struct adapter *adap = file_inode(file)->i_private;
2d277b3b
HS		 679
680 if (copy_from_user(s, buf, size))
681 return -EFAULT;
682 s[size] = '\0';
683 err = kstrtoul(s, 0, &val);
684 if (err)
685 return err;
686 if (val > 0xffff)
687 return -EINVAL;
688 adap->params.tp.la_mask = val << 16;
689 t4_set_reg_field(adap, TP_DBG_LA_CONFIG_A, 0xffff0000U,
690 adap->params.tp.la_mask);
691 return count;
692}
693
694static const struct file_operations tp_la_fops = {
695 .owner = THIS_MODULE,
696 .open = tp_la_open,
697 .read = seq_read,
698 .llseek = seq_lseek,
699 .release = seq_release_private,
700 .write = tp_la_write
701};
702
797ff0f5
HS		 703static int ulprx_la_show(struct seq_file *seq, void *v, int idx)
704{
705 const u32 *p = v;
706
707 if (v == SEQ_START_TOKEN)
708 seq_puts(seq, " Pcmd Type Message"
709 " Data\n");
710 else
711 seq_printf(seq, "%08x%08x %4x %08x %08x%08x%08x%08x\n",
712 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
713 return 0;
714}
715
716static int ulprx_la_open(struct inode *inode, struct file *file)
717{
718 struct seq_tab *p;
719 struct adapter *adap = inode->i_private;
720
721 p = seq_open_tab(file, ULPRX_LA_SIZE, 8 * sizeof(u32), 1,
722 ulprx_la_show);
723 if (!p)
724 return -ENOMEM;
725
726 t4_ulprx_read_la(adap, (u32 *)p->data);
727 return 0;
728}
729
730static const struct file_operations ulprx_la_fops = {
731 .owner = THIS_MODULE,
732 .open = ulprx_la_open,
733 .read = seq_read,
734 .llseek = seq_lseek,
735 .release = seq_release_private
736};
737
b3bbe36a
HS		 738/* Show the PM memory stats. These stats include:
739 *
740 * TX:
741 * Read: memory read operation
742 * Write Bypass: cut-through
743 * Bypass + mem: cut-through and save copy
744 *
745 * RX:
746 * Read: memory read
747 * Write Bypass: cut-through
748 * Flush: payload trim or drop
749 */
750static int pm_stats_show(struct seq_file *seq, void *v)
751{
752 static const char * const tx_pm_stats[] = {
753 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:"
754 };
755 static const char * const rx_pm_stats[] = {
756 "Read:", "Write bypass:", "Write mem:", "Flush:"
757 };
758
759 int i;
760 u32 tx_cnt[PM_NSTATS], rx_cnt[PM_NSTATS];
761 u64 tx_cyc[PM_NSTATS], rx_cyc[PM_NSTATS];
762 struct adapter *adap = seq->private;
763
764 t4_pmtx_get_stats(adap, tx_cnt, tx_cyc);
765 t4_pmrx_get_stats(adap, rx_cnt, rx_cyc);
766
767 seq_printf(seq, "%13s %10s %20s\n", " ", "Tx pcmds", "Tx bytes");
768 for (i = 0; i < PM_NSTATS - 1; i++)
769 seq_printf(seq, "%-13s %10u %20llu\n",
770 tx_pm_stats[i], tx_cnt[i], tx_cyc[i]);
771
772 seq_printf(seq, "%13s %10s %20s\n", " ", "Rx pcmds", "Rx bytes");
773 for (i = 0; i < PM_NSTATS - 1; i++)
774 seq_printf(seq, "%-13s %10u %20llu\n",
775 rx_pm_stats[i], rx_cnt[i], rx_cyc[i]);
776 return 0;
777}
778
779static int pm_stats_open(struct inode *inode, struct file *file)
780{
781 return single_open(file, pm_stats_show, inode->i_private);
782}
783
784static ssize_t pm_stats_clear(struct file *file, const char __user *buf,
785 size_t count, loff_t *pos)
786{
c1d81b1c 787 struct adapter *adap = file_inode(file)->i_private;
b3bbe36a
HS		 788
789 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, 0);
790 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, 0);
791 return count;
792}
793
794static const struct file_operations pm_stats_debugfs_fops = {
795 .owner = THIS_MODULE,
796 .open = pm_stats_open,
797 .read = seq_read,
798 .llseek = seq_lseek,
799 .release = single_release,
800 .write = pm_stats_clear
801};
802
7864026b
HS		 803static int tx_rate_show(struct seq_file *seq, void *v)
804{
805 u64 nrate[NCHAN], orate[NCHAN];
806 struct adapter *adap = seq->private;
807
808 t4_get_chan_txrate(adap, nrate, orate);
809 if (adap->params.arch.nchan == NCHAN) {
810 seq_puts(seq, " channel 0 channel 1 "
811 "channel 2 channel 3\n");
812 seq_printf(seq, "NIC B/s: %10llu %10llu %10llu %10llu\n",
813 (unsigned long long)nrate[0],
814 (unsigned long long)nrate[1],
815 (unsigned long long)nrate[2],
816 (unsigned long long)nrate[3]);
817 seq_printf(seq, "Offload B/s: %10llu %10llu %10llu %10llu\n",
818 (unsigned long long)orate[0],
819 (unsigned long long)orate[1],
820 (unsigned long long)orate[2],
821 (unsigned long long)orate[3]);
822 } else {
823 seq_puts(seq, " channel 0 channel 1\n");
824 seq_printf(seq, "NIC B/s: %10llu %10llu\n",
825 (unsigned long long)nrate[0],
826 (unsigned long long)nrate[1]);
827 seq_printf(seq, "Offload B/s: %10llu %10llu\n",
828 (unsigned long long)orate[0],
829 (unsigned long long)orate[1]);
830 }
831 return 0;
832}
833
834DEFINE_SIMPLE_DEBUGFS_FILE(tx_rate);
835
bad43792
HS		 836static int cctrl_tbl_show(struct seq_file *seq, void *v)
837{
838 static const char * const dec_fac[] = {
839 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
840 "0.9375" };
841
842 int i;
dde93dfe 843 u16 (*incr)[NCCTRL_WIN];
bad43792
HS		 844 struct adapter *adap = seq->private;
845
dde93dfe
HS		 846 incr = kmalloc(sizeof(*incr) * NMTUS, GFP_KERNEL);
847 if (!incr)
848 return -ENOMEM;
849
bad43792
HS		 850 t4_read_cong_tbl(adap, incr);
851
852 for (i = 0; i < NCCTRL_WIN; ++i) {
853 seq_printf(seq, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
854 incr[0][i], incr[1][i], incr[2][i], incr[3][i],
855 incr[4][i], incr[5][i], incr[6][i], incr[7][i]);
856 seq_printf(seq, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
857 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
858 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
859 adap->params.a_wnd[i],
860 dec_fac[adap->params.b_wnd[i]]);
861 }
dde93dfe
HS		 862
863 kfree(incr);
bad43792
HS		 864 return 0;
865}
866
867DEFINE_SIMPLE_DEBUGFS_FILE(cctrl_tbl);
868
b58b6676
HS		 869/* Format a value in a unit that differs from the value's native unit by the
870 * given factor.
871 */
872static char *unit_conv(char *buf, size_t len, unsigned int val,
873 unsigned int factor)
874{
875 unsigned int rem = val % factor;
876
877 if (rem == 0) {
878 snprintf(buf, len, "%u", val / factor);
879 } else {
880 while (rem % 10 == 0)
881 rem /= 10;
882 snprintf(buf, len, "%u.%u", val / factor, rem);
883 }
884 return buf;
885}
886
887static int clk_show(struct seq_file *seq, void *v)
888{
889 char buf[32];
890 struct adapter *adap = seq->private;
891 unsigned int cclk_ps = 1000000000 / adap->params.vpd.cclk; /* in ps */
892 u32 res = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
893 unsigned int tre = TIMERRESOLUTION_G(res);
894 unsigned int dack_re = DELAYEDACKRESOLUTION_G(res);
895 unsigned long long tp_tick_us = (cclk_ps << tre) / 1000000; /* in us */
896
897 seq_printf(seq, "Core clock period: %s ns\n",
898 unit_conv(buf, sizeof(buf), cclk_ps, 1000));
899 seq_printf(seq, "TP timer tick: %s us\n",
900 unit_conv(buf, sizeof(buf), (cclk_ps << tre), 1000000));
901 seq_printf(seq, "TCP timestamp tick: %s us\n",
902 unit_conv(buf, sizeof(buf),
903 (cclk_ps << TIMESTAMPRESOLUTION_G(res)), 1000000));
904 seq_printf(seq, "DACK tick: %s us\n",
905 unit_conv(buf, sizeof(buf), (cclk_ps << dack_re), 1000000));
906 seq_printf(seq, "DACK timer: %u us\n",
907 ((cclk_ps << dack_re) / 1000000) *
908 t4_read_reg(adap, TP_DACK_TIMER_A));
909 seq_printf(seq, "Retransmit min: %llu us\n",
910 tp_tick_us * t4_read_reg(adap, TP_RXT_MIN_A));
911 seq_printf(seq, "Retransmit max: %llu us\n",
912 tp_tick_us * t4_read_reg(adap, TP_RXT_MAX_A));
913 seq_printf(seq, "Persist timer min: %llu us\n",
914 tp_tick_us * t4_read_reg(adap, TP_PERS_MIN_A));
915 seq_printf(seq, "Persist timer max: %llu us\n",
916 tp_tick_us * t4_read_reg(adap, TP_PERS_MAX_A));
917 seq_printf(seq, "Keepalive idle timer: %llu us\n",
918 tp_tick_us * t4_read_reg(adap, TP_KEEP_IDLE_A));
919 seq_printf(seq, "Keepalive interval: %llu us\n",
920 tp_tick_us * t4_read_reg(adap, TP_KEEP_INTVL_A));
921 seq_printf(seq, "Initial SRTT: %llu us\n",
922 tp_tick_us * INITSRTT_G(t4_read_reg(adap, TP_INIT_SRTT_A)));
923 seq_printf(seq, "FINWAIT2 timer: %llu us\n",
924 tp_tick_us * t4_read_reg(adap, TP_FINWAIT2_TIMER_A));
925
926 return 0;
927}
928
929DEFINE_SIMPLE_DEBUGFS_FILE(clk);
930
f1ff24aa 931/* Firmware Device Log dump. */
49aa284f
HS		 932static const char * const devlog_level_strings[] = {
933 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
934 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
935 [FW_DEVLOG_LEVEL_ERR] = "ERR",
936 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
937 [FW_DEVLOG_LEVEL_INFO] = "INFO",
938 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
939};
940
941static const char * const devlog_facility_strings[] = {
942 [FW_DEVLOG_FACILITY_CORE] = "CORE",
943 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
944 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
945 [FW_DEVLOG_FACILITY_RES] = "RES",
946 [FW_DEVLOG_FACILITY_HW] = "HW",
947 [FW_DEVLOG_FACILITY_FLR] = "FLR",
948 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
949 [FW_DEVLOG_FACILITY_PHY] = "PHY",
950 [FW_DEVLOG_FACILITY_MAC] = "MAC",
951 [FW_DEVLOG_FACILITY_PORT] = "PORT",
952 [FW_DEVLOG_FACILITY_VI] = "VI",
953 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
954 [FW_DEVLOG_FACILITY_ACL] = "ACL",
955 [FW_DEVLOG_FACILITY_TM] = "TM",
956 [FW_DEVLOG_FACILITY_QFC] = "QFC",
957 [FW_DEVLOG_FACILITY_DCB] = "DCB",
958 [FW_DEVLOG_FACILITY_ETH] = "ETH",
959 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
960 [FW_DEVLOG_FACILITY_RI] = "RI",
961 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
962 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
963 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
964 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE"
965};
966
967/* Information gathered by Device Log Open routine for the display routine.
968 */
969struct devlog_info {
970 unsigned int nentries; /* number of entries in log[] */
971 unsigned int first; /* first [temporal] entry in log[] */
972 struct fw_devlog_e log[0]; /* Firmware Device Log */
973};
974
975/* Dump a Firmaware Device Log entry.
976 */
977static int devlog_show(struct seq_file *seq, void *v)
978{
979 if (v == SEQ_START_TOKEN)
980 seq_printf(seq, "%10s %15s %8s %8s %s\n",
981 "Seq#", "Tstamp", "Level", "Facility", "Message");
982 else {
983 struct devlog_info *dinfo = seq->private;
984 int fidx = (uintptr_t)v - 2;
985 unsigned long index;
986 struct fw_devlog_e *e;
987
988 /* Get a pointer to the log entry to display. Skip unused log
989 * entries.
990 */
991 index = dinfo->first + fidx;
992 if (index >= dinfo->nentries)
993 index -= dinfo->nentries;
994 e = &dinfo->log[index];
995 if (e->timestamp == 0)
996 return 0;
997
998 /* Print the message. This depends on the firmware using
999 * exactly the same formating strings as the kernel so we may
1000 * eventually have to put a format interpreter in here ...
1001 */
1002 seq_printf(seq, "%10d %15llu %8s %8s ",
fda8b18c
HS		 1003 be32_to_cpu(e->seqno),
1004 be64_to_cpu(e->timestamp),
49aa284f
HS		 1005 (e->level < ARRAY_SIZE(devlog_level_strings)
1006 ? devlog_level_strings[e->level]
1007 : "UNKNOWN"),
1008 (e->facility < ARRAY_SIZE(devlog_facility_strings)
1009 ? devlog_facility_strings[e->facility]
1010 : "UNKNOWN"));
fda8b18c
HS		 1011 seq_printf(seq, e->fmt,
1012 be32_to_cpu(e->params[0]),
1013 be32_to_cpu(e->params[1]),
1014 be32_to_cpu(e->params[2]),
1015 be32_to_cpu(e->params[3]),
1016 be32_to_cpu(e->params[4]),
1017 be32_to_cpu(e->params[5]),
1018 be32_to_cpu(e->params[6]),
1019 be32_to_cpu(e->params[7]));
49aa284f
HS		 1020 }
1021 return 0;
1022}
1023
1024/* Sequential File Operations for Device Log.
1025 */
1026static inline void *devlog_get_idx(struct devlog_info *dinfo, loff_t pos)
1027{
1028 if (pos > dinfo->nentries)
1029 return NULL;
1030
1031 return (void *)(uintptr_t)(pos + 1);
1032}
1033
1034static void *devlog_start(struct seq_file *seq, loff_t *pos)
1035{
1036 struct devlog_info *dinfo = seq->private;
1037
1038 return (*pos
1039 ? devlog_get_idx(dinfo, *pos)
1040 : SEQ_START_TOKEN);
1041}
1042
1043static void *devlog_next(struct seq_file *seq, void *v, loff_t *pos)
1044{
1045 struct devlog_info *dinfo = seq->private;
1046
1047 (*pos)++;
1048 return devlog_get_idx(dinfo, *pos);
1049}
1050
1051static void devlog_stop(struct seq_file *seq, void *v)
1052{
1053}
1054
1055static const struct seq_operations devlog_seq_ops = {
1056 .start = devlog_start,
1057 .next = devlog_next,
1058 .stop = devlog_stop,
1059 .show = devlog_show
1060};
1061
1062/* Set up for reading the firmware's device log. We read the entire log here
1063 * and then display it incrementally in devlog_show().
1064 */
1065static int devlog_open(struct inode *inode, struct file *file)
1066{
1067 struct adapter *adap = inode->i_private;
1068 struct devlog_params *dparams = &adap->params.devlog;
1069 struct devlog_info *dinfo;
1070 unsigned int index;
1071 u32 fseqno;
1072 int ret;
1073
1074 /* If we don't know where the log is we can't do anything.
1075 */
1076 if (dparams->start == 0)
1077 return -ENXIO;
1078
1079 /* Allocate the space to read in the firmware's device log and set up
1080 * for the iterated call to our display function.
1081 */
1082 dinfo = __seq_open_private(file, &devlog_seq_ops,
1083 sizeof(*dinfo) + dparams->size);
1084 if (!dinfo)
1085 return -ENOMEM;
1086
1087 /* Record the basic log buffer information and read in the raw log.
1088 */
1089 dinfo->nentries = (dparams->size / sizeof(struct fw_devlog_e));
1090 dinfo->first = 0;
1091 spin_lock(&adap->win0_lock);
1092 ret = t4_memory_rw(adap, adap->params.drv_memwin, dparams->memtype,
1093 dparams->start, dparams->size, (__be32 *)dinfo->log,
1094 T4_MEMORY_READ);
1095 spin_unlock(&adap->win0_lock);
1096 if (ret) {
1097 seq_release_private(inode, file);
1098 return ret;
1099 }
1100
fda8b18c
HS		 1101 /* Find the earliest (lowest Sequence Number) log entry in the
1102 * circular Device Log.
49aa284f
HS		 1103 */
1104 for (fseqno = ~((u32)0), index = 0; index < dinfo->nentries; index++) {
1105 struct fw_devlog_e *e = &dinfo->log[index];
49aa284f
HS		 1106 __u32 seqno;
1107
1108 if (e->timestamp == 0)
1109 continue;
1110
49aa284f 1111 seqno = be32_to_cpu(e->seqno);
49aa284f
HS		 1112 if (seqno < fseqno) {
1113 fseqno = seqno;
1114 dinfo->first = index;
1115 }
1116 }
1117 return 0;
1118}
1119
1120static const struct file_operations devlog_fops = {
1121 .owner = THIS_MODULE,
1122 .open = devlog_open,
1123 .read = seq_read,
1124 .llseek = seq_lseek,
1125 .release = seq_release_private
1126};
1127
bf7c781d
HS		 1128static int mbox_show(struct seq_file *seq, void *v)
1129{
1130 static const char * const owner[] = { "none", "FW", "driver",
1131 "unknown" };
1132
1133 int i;
1134 unsigned int mbox = (uintptr_t)seq->private & 7;
1135 struct adapter *adap = seq->private - mbox;
1136 void __iomem *addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
1137 unsigned int ctrl_reg = (is_t4(adap->params.chip)
1138 ? CIM_PF_MAILBOX_CTRL_A
1139 : CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A);
1140 void __iomem *ctrl = adap->regs + PF_REG(mbox, ctrl_reg);
1141
1142 i = MBOWNER_G(readl(ctrl));
1143 seq_printf(seq, "mailbox owned by %s\n\n", owner[i]);
1144
1145 for (i = 0; i < MBOX_LEN; i += 8)
1146 seq_printf(seq, "%016llx\n",
1147 (unsigned long long)readq(addr + i));
1148 return 0;
1149}
1150
1151static int mbox_open(struct inode *inode, struct file *file)
1152{
1153 return single_open(file, mbox_show, inode->i_private);
1154}
1155
1156static ssize_t mbox_write(struct file *file, const char __user *buf,
1157 size_t count, loff_t *pos)
1158{
1159 int i;
1160 char c = '\n', s[256];
1161 unsigned long long data[8];
1162 const struct inode *ino;
1163 unsigned int mbox;
1164 struct adapter *adap;
1165 void __iomem *addr;
1166 void __iomem *ctrl;
1167
1168 if (count > sizeof(s) - 1 || !count)
1169 return -EINVAL;
1170 if (copy_from_user(s, buf, count))
1171 return -EFAULT;
1172 s[count] = '\0';
1173
1174 if (sscanf(s, "%llx %llx %llx %llx %llx %llx %llx %llx%c", &data[0],
1175 &data[1], &data[2], &data[3], &data[4], &data[5], &data[6],
1176 &data[7], &c) < 8 || c != '\n')
1177 return -EINVAL;
1178
c1d81b1c 1179 ino = file_inode(file);
bf7c781d
HS		 1180 mbox = (uintptr_t)ino->i_private & 7;
1181 adap = ino->i_private - mbox;
1182 addr = adap->regs + PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
1183 ctrl = addr + MBOX_LEN;
1184
1185 if (MBOWNER_G(readl(ctrl)) != X_MBOWNER_PL)
1186 return -EBUSY;
1187
1188 for (i = 0; i < 8; i++)
1189 writeq(data[i], addr + 8 * i);
1190
1191 writel(MBMSGVALID_F | MBOWNER_V(X_MBOWNER_FW), ctrl);
1192 return count;
1193}
1194
1195static const struct file_operations mbox_debugfs_fops = {
1196 .owner = THIS_MODULE,
1197 .open = mbox_open,
1198 .read = seq_read,
1199 .llseek = seq_lseek,
1200 .release = single_release,
1201 .write = mbox_write
1202};
1203
8e3d04fd
HS		 1204static int mps_trc_show(struct seq_file *seq, void *v)
1205{
1206 int enabled, i;
1207 struct trace_params tp;
1208 unsigned int trcidx = (uintptr_t)seq->private & 3;
1209 struct adapter *adap = seq->private - trcidx;
1210
1211 t4_get_trace_filter(adap, &tp, trcidx, &enabled);
1212 if (!enabled) {
1213 seq_puts(seq, "tracer is disabled\n");
1214 return 0;
1215 }
1216
1217 if (tp.skip_ofst * 8 >= TRACE_LEN) {
1218 dev_err(adap->pdev_dev, "illegal trace pattern skip offset\n");
1219 return -EINVAL;
1220 }
1221 if (tp.port < 8) {
1222 i = adap->chan_map[tp.port & 3];
1223 if (i >= MAX_NPORTS) {
1224 dev_err(adap->pdev_dev, "tracer %u is assigned "
1225 "to non-existing port\n", trcidx);
1226 return -EINVAL;
1227 }
1228 seq_printf(seq, "tracer is capturing %s %s, ",
1229 adap->port[i]->name, tp.port < 4 ? "Rx" : "Tx");
1230 } else
1231 seq_printf(seq, "tracer is capturing loopback %d, ",
1232 tp.port - 8);
1233 seq_printf(seq, "snap length: %u, min length: %u\n", tp.snap_len,
1234 tp.min_len);
1235 seq_printf(seq, "packets captured %smatch filter\n",
1236 tp.invert ? "do not " : "");
1237
1238 if (tp.skip_ofst) {
1239 seq_puts(seq, "filter pattern: ");
1240 for (i = 0; i < tp.skip_ofst * 2; i += 2)
1241 seq_printf(seq, "%08x%08x", tp.data[i], tp.data[i + 1]);
1242 seq_putc(seq, '/');
1243 for (i = 0; i < tp.skip_ofst * 2; i += 2)
1244 seq_printf(seq, "%08x%08x", tp.mask[i], tp.mask[i + 1]);
1245 seq_puts(seq, "@0\n");
1246 }
1247
1248 seq_puts(seq, "filter pattern: ");
1249 for (i = tp.skip_ofst * 2; i < TRACE_LEN / 4; i += 2)
1250 seq_printf(seq, "%08x%08x", tp.data[i], tp.data[i + 1]);
1251 seq_putc(seq, '/');
1252 for (i = tp.skip_ofst * 2; i < TRACE_LEN / 4; i += 2)
1253 seq_printf(seq, "%08x%08x", tp.mask[i], tp.mask[i + 1]);
1254 seq_printf(seq, "@%u\n", (tp.skip_ofst + tp.skip_len) * 8);
1255 return 0;
1256}
1257
1258static int mps_trc_open(struct inode *inode, struct file *file)
1259{
1260 return single_open(file, mps_trc_show, inode->i_private);
1261}
1262
1263static unsigned int xdigit2int(unsigned char c)
1264{
1265 return isdigit(c) ? c - '0' : tolower(c) - 'a' + 10;
1266}
1267
1268#define TRC_PORT_NONE 0xff
1269#define TRC_RSS_ENABLE 0x33
1270#define TRC_RSS_DISABLE 0x13
1271
1272/* Set an MPS trace filter. Syntax is:
1273 *
1274 * disable
1275 *
1276 * to disable tracing, or
1277 *
1278 * interface qid=<qid no> [snaplen=<val>] [minlen=<val>] [not] [<pattern>]...
1279 *
1280 * where interface is one of rxN, txN, or loopbackN, N = 0..3, qid can be one
1281 * of the NIC's response qid obtained from sge_qinfo and pattern has the form
1282 *
1283 * <pattern data>[/<pattern mask>][@<anchor>]
1284 *
1285 * Up to 2 filter patterns can be specified. If 2 are supplied the first one
1286 * must be anchored at 0. An omited mask is taken as a mask of 1s, an omitted
1287 * anchor is taken as 0.
1288 */
1289static ssize_t mps_trc_write(struct file *file, const char __user *buf,
1290 size_t count, loff_t *pos)
1291{
c938a003 1292 int i, enable, ret;
8e3d04fd
HS		 1293 u32 *data, *mask;
1294 struct trace_params tp;
1295 const struct inode *ino;
1296 unsigned int trcidx;
1297 char *s, *p, *word, *end;
1298 struct adapter *adap;
c938a003 1299 u32 j;
8e3d04fd
HS		 1300
1301 ino = file_inode(file);
1302 trcidx = (uintptr_t)ino->i_private & 3;
1303 adap = ino->i_private - trcidx;
1304
1305 /* Don't accept input more than 1K, can't be anything valid except lots
1306 * of whitespace. Well, use less.
1307 */
1308 if (count > 1024)
1309 return -EFBIG;
1310 p = s = kzalloc(count + 1, GFP_USER);
1311 if (!s)
1312 return -ENOMEM;
1313 if (copy_from_user(s, buf, count)) {
1314 count = -EFAULT;
1315 goto out;
1316 }
1317
1318 if (s[count - 1] == '\n')
1319 s[count - 1] = '\0';
1320
1321 enable = strcmp("disable", s) != 0;
1322 if (!enable)
1323 goto apply;
1324
1325 /* enable or disable trace multi rss filter */
1326 if (adap->trace_rss)
1327 t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_ENABLE);
1328 else
1329 t4_write_reg(adap, MPS_TRC_CFG_A, TRC_RSS_DISABLE);
1330
1331 memset(&tp, 0, sizeof(tp));
1332 tp.port = TRC_PORT_NONE;
1333 i = 0; /* counts pattern nibbles */
1334
1335 while (p) {
1336 while (isspace(*p))
1337 p++;
1338 word = strsep(&p, " ");
1339 if (!*word)
1340 break;
1341
1342 if (!strncmp(word, "qid=", 4)) {
1343 end = (char *)word + 4;
c938a003 1344 ret = kstrtouint(end, 10, &j);
8e3d04fd
HS		 1345 if (ret)
1346 goto out;
1347 if (!adap->trace_rss) {
1348 t4_write_reg(adap, MPS_T5_TRC_RSS_CONTROL_A, j);
1349 continue;
1350 }
1351
1352 switch (trcidx) {
1353 case 0:
1354 t4_write_reg(adap, MPS_TRC_RSS_CONTROL_A, j);
1355 break;
1356 case 1:
1357 t4_write_reg(adap,
1358 MPS_TRC_FILTER1_RSS_CONTROL_A, j);
1359 break;
1360 case 2:
1361 t4_write_reg(adap,
1362 MPS_TRC_FILTER2_RSS_CONTROL_A, j);
1363 break;
1364 case 3:
1365 t4_write_reg(adap,
1366 MPS_TRC_FILTER3_RSS_CONTROL_A, j);
1367 break;
1368 }
1369 continue;
1370 }
1371 if (!strncmp(word, "snaplen=", 8)) {
1372 end = (char *)word + 8;
c938a003 1373 ret = kstrtouint(end, 10, &j);
8e3d04fd
HS		 1374 if (ret || j > 9600) {
1375inval: count = -EINVAL;
1376 goto out;
1377 }
1378 tp.snap_len = j;
1379 continue;
1380 }
1381 if (!strncmp(word, "minlen=", 7)) {
1382 end = (char *)word + 7;
c938a003 1383 ret = kstrtouint(end, 10, &j);
8e3d04fd
HS		 1384 if (ret || j > TFMINPKTSIZE_M)
1385 goto inval;
1386 tp.min_len = j;
1387 continue;
1388 }
1389 if (!strcmp(word, "not")) {
1390 tp.invert = !tp.invert;
1391 continue;
1392 }
1393 if (!strncmp(word, "loopback", 8) && tp.port == TRC_PORT_NONE) {
1394 if (word[8] < '0' || word[8] > '3' || word[9])
1395 goto inval;
1396 tp.port = word[8] - '0' + 8;
1397 continue;
1398 }
1399 if (!strncmp(word, "tx", 2) && tp.port == TRC_PORT_NONE) {
1400 if (word[2] < '0' || word[2] > '3' || word[3])
1401 goto inval;
1402 tp.port = word[2] - '0' + 4;
1403 if (adap->chan_map[tp.port & 3] >= MAX_NPORTS)
1404 goto inval;
1405 continue;
1406 }
1407 if (!strncmp(word, "rx", 2) && tp.port == TRC_PORT_NONE) {
1408 if (word[2] < '0' || word[2] > '3' || word[3])
1409 goto inval;
1410 tp.port = word[2] - '0';
1411 if (adap->chan_map[tp.port] >= MAX_NPORTS)
1412 goto inval;
1413 continue;
1414 }
1415 if (!isxdigit(*word))
1416 goto inval;
1417
1418 /* we have found a trace pattern */
1419 if (i) { /* split pattern */
1420 if (tp.skip_len) /* too many splits */
1421 goto inval;
1422 tp.skip_ofst = i / 16;
1423 }
1424
1425 data = &tp.data[i / 8];
1426 mask = &tp.mask[i / 8];
1427 j = i;
1428
1429 while (isxdigit(*word)) {
1430 if (i >= TRACE_LEN * 2) {
1431 count = -EFBIG;
1432 goto out;
1433 }
1434 *data = (*data << 4) + xdigit2int(*word++);
1435 if (++i % 8 == 0)
1436 data++;
1437 }
1438 if (*word == '/') {
1439 word++;
1440 while (isxdigit(*word)) {
1441 if (j >= i) /* mask longer than data */
1442 goto inval;
1443 *mask = (*mask << 4) + xdigit2int(*word++);
1444 if (++j % 8 == 0)
1445 mask++;
1446 }
1447 if (i != j) /* mask shorter than data */
1448 goto inval;
1449 } else { /* no mask, use all 1s */
1450 for ( ; i - j >= 8; j += 8)
1451 *mask++ = 0xffffffff;
1452 if (i % 8)
1453 *mask = (1 << (i % 8) * 4) - 1;
1454 }
1455 if (*word == '@') {
1456 end = (char *)word + 1;
c938a003 1457 ret = kstrtouint(end, 10, &j);
8e3d04fd
HS		 1458 if (*end && *end != '\n')
1459 goto inval;
1460 if (j & 7) /* doesn't start at multiple of 8 */
1461 goto inval;
1462 j /= 8;
1463 if (j < tp.skip_ofst) /* overlaps earlier pattern */
1464 goto inval;
1465 if (j - tp.skip_ofst > 31) /* skip too big */
1466 goto inval;
1467 tp.skip_len = j - tp.skip_ofst;
1468 }
1469 if (i % 8) {
1470 *data <<= (8 - i % 8) * 4;
1471 *mask <<= (8 - i % 8) * 4;
1472 i = (i + 15) & ~15; /* 8-byte align */
1473 }
1474 }
1475
1476 if (tp.port == TRC_PORT_NONE)
1477 goto inval;
1478
1479apply:
1480 i = t4_set_trace_filter(adap, &tp, trcidx, enable);
1481 if (i)
1482 count = i;
1483out:
1484 kfree(s);
1485 return count;
1486}
1487
1488static const struct file_operations mps_trc_debugfs_fops = {
1489 .owner = THIS_MODULE,
1490 .open = mps_trc_open,
1491 .read = seq_read,
1492 .llseek = seq_lseek,
1493 .release = single_release,
1494 .write = mps_trc_write
1495};
1496
49216c1c
HS		 1497static ssize_t flash_read(struct file *file, char __user *buf, size_t count,
1498 loff_t *ppos)
1499{
1500 loff_t pos = *ppos;
c1d81b1c 1501 loff_t avail = file_inode(file)->i_size;
49216c1c
HS		 1502 struct adapter *adap = file->private_data;
1503
1504 if (pos < 0)
1505 return -EINVAL;
1506 if (pos >= avail)
1507 return 0;
1508 if (count > avail - pos)
1509 count = avail - pos;
1510
1511 while (count) {
1512 size_t len;
1513 int ret, ofst;
1514 u8 data[256];
1515
1516 ofst = pos & 3;
1517 len = min(count + ofst, sizeof(data));
1518 ret = t4_read_flash(adap, pos - ofst, (len + 3) / 4,
1519 (u32 *)data, 1);
1520 if (ret)
1521 return ret;
1522
1523 len -= ofst;
1524 if (copy_to_user(buf, data + ofst, len))
1525 return -EFAULT;
1526
1527 buf += len;
1528 pos += len;
1529 count -= len;
1530 }
1531 count = pos - *ppos;
1532 *ppos = pos;
1533 return count;
1534}
1535
1536static const struct file_operations flash_debugfs_fops = {
1537 .owner = THIS_MODULE,
1538 .open = mem_open,
1539 .read = flash_read,
1540};
1541
ef82f662
HS		 1542static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
1543{
1544 *mask = x | y;
1545 y = (__force u64)cpu_to_be64(y);
1546 memcpy(addr, (char *)&y + 2, ETH_ALEN);
1547}
1548
1549static int mps_tcam_show(struct seq_file *seq, void *v)
1550{
3ccc6cf7
HS		 1551 struct adapter *adap = seq->private;
1552 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
1553
1554 if (v == SEQ_START_TOKEN) {
1555 if (adap->params.arch.mps_rplc_size > 128)
1556 seq_puts(seq, "Idx Ethernet address Mask "
1557 "Vld Ports PF VF "
1558 "Replication "
1559 " P0 P1 P2 P3 ML\n");
1560 else
1561 seq_puts(seq, "Idx Ethernet address Mask "
1562 "Vld Ports PF VF Replication"
1563 " P0 P1 P2 P3 ML\n");
1564 } else {
ef82f662
HS		 1565 u64 mask;
1566 u8 addr[ETH_ALEN];
3ccc6cf7 1567 bool replicate;
ef82f662 1568 unsigned int idx = (uintptr_t)v - 2;
3ccc6cf7
HS		 1569 u64 tcamy, tcamx, val;
1570 u32 cls_lo, cls_hi, ctl;
1571 u32 rplc[8] = {0};
1572
1573 if (chip_ver > CHELSIO_T5) {
1574 /* CtlCmdType - 0: Read, 1: Write
1575 * CtlTcamSel - 0: TCAM0, 1: TCAM1
1576 * CtlXYBitSel- 0: Y bit, 1: X bit
1577 */
1578
1579 /* Read tcamy */
1580 ctl = CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
1581 if (idx < 256)
1582 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0);
1583 else
1584 ctl |= CTLTCAMINDEX_V(idx - 256) |
1585 CTLTCAMSEL_V(1);
1586 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
1587 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);
1588 tcamy = DMACH_G(val) << 32;
1589 tcamy |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);
1590
1591 /* Read tcamx. Change the control param */
1592 ctl |= CTLXYBITSEL_V(1);
1593 t4_write_reg(adap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
1594 val = t4_read_reg(adap, MPS_CLS_TCAM_DATA1_A);
1595 tcamx = DMACH_G(val) << 32;
1596 tcamx |= t4_read_reg(adap, MPS_CLS_TCAM_DATA0_A);
1597 } else {
1598 tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx));
1599 tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));
1600 }
1601
1602 cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
1603 cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));
ef82f662
HS		 1604
1605 if (tcamx & tcamy) {
1606 seq_printf(seq, "%3u -\n", idx);
1607 goto out;
1608 }
1609
3ccc6cf7
HS		 1610 rplc[0] = rplc[1] = rplc[2] = rplc[3] = 0;
1611 if (chip_ver > CHELSIO_T5)
1612 replicate = (cls_lo & T6_REPLICATE_F);
1613 else
1614 replicate = (cls_lo & REPLICATE_F);
1615
1616 if (replicate) {
ef82f662
HS		 1617 struct fw_ldst_cmd ldst_cmd;
1618 int ret;
3ccc6cf7
HS		 1619 struct fw_ldst_mps_rplc mps_rplc;
1620 u32 ldst_addrspc;
ef82f662
HS		 1621
1622 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
3ccc6cf7
HS		 1623 ldst_addrspc =
1624 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS);
ef82f662
HS		 1625 ldst_cmd.op_to_addrspace =
1626 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
1627 FW_CMD_REQUEST_F |
1628 FW_CMD_READ_F |
3ccc6cf7 1629 ldst_addrspc);
ef82f662 1630 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
3ccc6cf7 1631 ldst_cmd.u.mps.rplc.fid_idx =
ef82f662 1632 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
3ccc6cf7 1633 FW_LDST_CMD_IDX_V(idx));
ef82f662
HS		 1634 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd,
1635 sizeof(ldst_cmd), &ldst_cmd);
1636 if (ret)
1637 dev_warn(adap->pdev_dev, "Can't read MPS "
1638 "replication map for idx %d: %d\n",
1639 idx, -ret);
1640 else {
3ccc6cf7
HS		 1641 mps_rplc = ldst_cmd.u.mps.rplc;
1642 rplc[0] = ntohl(mps_rplc.rplc31_0);
1643 rplc[1] = ntohl(mps_rplc.rplc63_32);
1644 rplc[2] = ntohl(mps_rplc.rplc95_64);
1645 rplc[3] = ntohl(mps_rplc.rplc127_96);
1646 if (adap->params.arch.mps_rplc_size > 128) {
1647 rplc[4] = ntohl(mps_rplc.rplc159_128);
1648 rplc[5] = ntohl(mps_rplc.rplc191_160);
1649 rplc[6] = ntohl(mps_rplc.rplc223_192);
1650 rplc[7] = ntohl(mps_rplc.rplc255_224);
1651 }
ef82f662
HS		 1652 }
1653 }
1654
1655 tcamxy2valmask(tcamx, tcamy, addr, &mask);
3ccc6cf7
HS		 1656 if (chip_ver > CHELSIO_T5)
1657 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x "
1658 "%012llx%3c %#x%4u%4d",
1659 idx, addr[0], addr[1], addr[2], addr[3],
1660 addr[4], addr[5], (unsigned long long)mask,
1661 (cls_lo & T6_SRAM_VLD_F) ? 'Y' : 'N',
1662 PORTMAP_G(cls_hi),
1663 T6_PF_G(cls_lo),
1664 (cls_lo & T6_VF_VALID_F) ?
1665 T6_VF_G(cls_lo) : -1);
ef82f662 1666 else
3ccc6cf7
HS		 1667 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x "
1668 "%012llx%3c %#x%4u%4d",
1669 idx, addr[0], addr[1], addr[2], addr[3],
1670 addr[4], addr[5], (unsigned long long)mask,
1671 (cls_lo & SRAM_VLD_F) ? 'Y' : 'N',
1672 PORTMAP_G(cls_hi),
1673 PF_G(cls_lo),
1674 (cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1);
1675
1676 if (replicate) {
1677 if (adap->params.arch.mps_rplc_size > 128)
1678 seq_printf(seq, " %08x %08x %08x %08x "
1679 "%08x %08x %08x %08x",
1680 rplc[7], rplc[6], rplc[5], rplc[4],
1681 rplc[3], rplc[2], rplc[1], rplc[0]);
1682 else
1683 seq_printf(seq, " %08x %08x %08x %08x",
1684 rplc[3], rplc[2], rplc[1], rplc[0]);
1685 } else {
1686 if (adap->params.arch.mps_rplc_size > 128)
1687 seq_printf(seq, "%72c", ' ');
1688 else
1689 seq_printf(seq, "%36c", ' ');
1690 }
1691
1692 if (chip_ver > CHELSIO_T5)
1693 seq_printf(seq, "%4u%3u%3u%3u %#x\n",
1694 T6_SRAM_PRIO0_G(cls_lo),
1695 T6_SRAM_PRIO1_G(cls_lo),
1696 T6_SRAM_PRIO2_G(cls_lo),
1697 T6_SRAM_PRIO3_G(cls_lo),
1698 (cls_lo >> T6_MULTILISTEN0_S) & 0xf);
1699 else
1700 seq_printf(seq, "%4u%3u%3u%3u %#x\n",
1701 SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo),
1702 SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo),
1703 (cls_lo >> MULTILISTEN0_S) & 0xf);
ef82f662
HS		 1704 }
1705out: return 0;
1706}
1707
1708static inline void *mps_tcam_get_idx(struct seq_file *seq, loff_t pos)
1709{
1710 struct adapter *adap = seq->private;
1711 int max_mac_addr = is_t4(adap->params.chip) ?
1712 NUM_MPS_CLS_SRAM_L_INSTANCES :
1713 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
1714 return ((pos <= max_mac_addr) ? (void *)(uintptr_t)(pos + 1) : NULL);
1715}
1716
1717static void *mps_tcam_start(struct seq_file *seq, loff_t *pos)
1718{
1719 return *pos ? mps_tcam_get_idx(seq, *pos) : SEQ_START_TOKEN;
1720}
1721
1722static void *mps_tcam_next(struct seq_file *seq, void *v, loff_t *pos)
1723{
1724 ++*pos;
1725 return mps_tcam_get_idx(seq, *pos);
1726}
1727
1728static void mps_tcam_stop(struct seq_file *seq, void *v)
1729{
1730}
1731
1732static const struct seq_operations mps_tcam_seq_ops = {
1733 .start = mps_tcam_start,
1734 .next = mps_tcam_next,
1735 .stop = mps_tcam_stop,
1736 .show = mps_tcam_show
1737};
1738
1739static int mps_tcam_open(struct inode *inode, struct file *file)
1740{
1741 int res = seq_open(file, &mps_tcam_seq_ops);
1742
1743 if (!res) {
1744 struct seq_file *seq = file->private_data;
1745
1746 seq->private = inode->i_private;
1747 }
1748 return res;
1749}
1750
1751static const struct file_operations mps_tcam_debugfs_fops = {
1752 .owner = THIS_MODULE,
1753 .open = mps_tcam_open,
1754 .read = seq_read,
1755 .llseek = seq_lseek,
1756 .release = seq_release,
1757};
1758
70a5f3bb
HS		 1759/* Display various sensor information.
1760 */
1761static int sensors_show(struct seq_file *seq, void *v)
1762{
1763 struct adapter *adap = seq->private;
1764 u32 param[7], val[7];
1765 int ret;
1766
1767 /* Note that if the sensors haven't been initialized and turned on
1768 * we'll get values of 0, so treat those as "<unknown>" ...
1769 */
1770 param[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
1771 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG) |
1772 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_TMP));
1773 param[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
1774 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DIAG) |
1775 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_DIAG_VDD));
b2612722 1776 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
70a5f3bb
HS		 1777 param, val);
1778
1779 if (ret < 0 || val[0] == 0)
1780 seq_puts(seq, "Temperature: <unknown>\n");
1781 else
1782 seq_printf(seq, "Temperature: %dC\n", val[0]);
1783
1784 if (ret < 0 || val[1] == 0)
1785 seq_puts(seq, "Core VDD: <unknown>\n");
1786 else
1787 seq_printf(seq, "Core VDD: %dmV\n", val[1]);
1788
1789 return 0;
1790}
1791
1792DEFINE_SIMPLE_DEBUGFS_FILE(sensors);
1793
b5a02f50
AB		 1794#if IS_ENABLED(CONFIG_IPV6)
1795static int clip_tbl_open(struct inode *inode, struct file *file)
1796{
acde2c2d 1797 return single_open(file, clip_tbl_show, inode->i_private);
b5a02f50
AB		 1798}
1799
1800static const struct file_operations clip_tbl_debugfs_fops = {
1801 .owner = THIS_MODULE,
1802 .open = clip_tbl_open,
1803 .read = seq_read,
1804 .llseek = seq_lseek,
1805 .release = single_release
1806};
1807#endif
1808
688ea5fe
HS		 1809/*RSS Table.
1810 */
1811
1812static int rss_show(struct seq_file *seq, void *v, int idx)
1813{
1814 u16 *entry = v;
1815
1816 seq_printf(seq, "%4d: %4u %4u %4u %4u %4u %4u %4u %4u\n",
1817 idx * 8, entry[0], entry[1], entry[2], entry[3], entry[4],
1818 entry[5], entry[6], entry[7]);
1819 return 0;
1820}
1821
1822static int rss_open(struct inode *inode, struct file *file)
1823{
1824 int ret;
1825 struct seq_tab *p;
1826 struct adapter *adap = inode->i_private;
1827
1828 p = seq_open_tab(file, RSS_NENTRIES / 8, 8 * sizeof(u16), 0, rss_show);
1829 if (!p)
1830 return -ENOMEM;
1831
1832 ret = t4_read_rss(adap, (u16 *)p->data);
1833 if (ret)
1834 seq_release_private(inode, file);
1835
1836 return ret;
1837}
1838
1839static const struct file_operations rss_debugfs_fops = {
1840 .owner = THIS_MODULE,
1841 .open = rss_open,
1842 .read = seq_read,
1843 .llseek = seq_lseek,
1844 .release = seq_release_private
1845};
1846
1847/* RSS Configuration.
1848 */
1849
1850/* Small utility function to return the strings "yes" or "no" if the supplied
1851 * argument is non-zero.
1852 */
1853static const char *yesno(int x)
1854{
1855 static const char *yes = "yes";
1856 static const char *no = "no";
1857
1858 return x ? yes : no;
1859}
1860
1861static int rss_config_show(struct seq_file *seq, void *v)
1862{
1863 struct adapter *adapter = seq->private;
1864 static const char * const keymode[] = {
1865 "global",
1866 "global and per-VF scramble",
1867 "per-PF and per-VF scramble",
1868 "per-VF and per-VF scramble",
1869 };
1870 u32 rssconf;
1871
1872 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_A);
1873 seq_printf(seq, "TP_RSS_CONFIG: %#x\n", rssconf);
1874 seq_printf(seq, " Tnl4TupEnIpv6: %3s\n", yesno(rssconf &
1875 TNL4TUPENIPV6_F));
1876 seq_printf(seq, " Tnl2TupEnIpv6: %3s\n", yesno(rssconf &
1877 TNL2TUPENIPV6_F));
1878 seq_printf(seq, " Tnl4TupEnIpv4: %3s\n", yesno(rssconf &
1879 TNL4TUPENIPV4_F));
1880 seq_printf(seq, " Tnl2TupEnIpv4: %3s\n", yesno(rssconf &
1881 TNL2TUPENIPV4_F));
1882 seq_printf(seq, " TnlTcpSel: %3s\n", yesno(rssconf & TNLTCPSEL_F));
1883 seq_printf(seq, " TnlIp6Sel: %3s\n", yesno(rssconf & TNLIP6SEL_F));
1884 seq_printf(seq, " TnlVrtSel: %3s\n", yesno(rssconf & TNLVRTSEL_F));
1885 seq_printf(seq, " TnlMapEn: %3s\n", yesno(rssconf & TNLMAPEN_F));
1886 seq_printf(seq, " OfdHashSave: %3s\n", yesno(rssconf &
1887 OFDHASHSAVE_F));
1888 seq_printf(seq, " OfdVrtSel: %3s\n", yesno(rssconf & OFDVRTSEL_F));
1889 seq_printf(seq, " OfdMapEn: %3s\n", yesno(rssconf & OFDMAPEN_F));
1890 seq_printf(seq, " OfdLkpEn: %3s\n", yesno(rssconf & OFDLKPEN_F));
1891 seq_printf(seq, " Syn4TupEnIpv6: %3s\n", yesno(rssconf &
1892 SYN4TUPENIPV6_F));
1893 seq_printf(seq, " Syn2TupEnIpv6: %3s\n", yesno(rssconf &
1894 SYN2TUPENIPV6_F));
1895 seq_printf(seq, " Syn4TupEnIpv4: %3s\n", yesno(rssconf &
1896 SYN4TUPENIPV4_F));
1897 seq_printf(seq, " Syn2TupEnIpv4: %3s\n", yesno(rssconf &
1898 SYN2TUPENIPV4_F));
1899 seq_printf(seq, " Syn4TupEnIpv6: %3s\n", yesno(rssconf &
1900 SYN4TUPENIPV6_F));
1901 seq_printf(seq, " SynIp6Sel: %3s\n", yesno(rssconf & SYNIP6SEL_F));
1902 seq_printf(seq, " SynVrt6Sel: %3s\n", yesno(rssconf & SYNVRTSEL_F));
1903 seq_printf(seq, " SynMapEn: %3s\n", yesno(rssconf & SYNMAPEN_F));
1904 seq_printf(seq, " SynLkpEn: %3s\n", yesno(rssconf & SYNLKPEN_F));
1905 seq_printf(seq, " ChnEn: %3s\n", yesno(rssconf &
1906 CHANNELENABLE_F));
1907 seq_printf(seq, " PrtEn: %3s\n", yesno(rssconf &
1908 PORTENABLE_F));
1909 seq_printf(seq, " TnlAllLkp: %3s\n", yesno(rssconf &
1910 TNLALLLOOKUP_F));
1911 seq_printf(seq, " VrtEn: %3s\n", yesno(rssconf &
1912 VIRTENABLE_F));
1913 seq_printf(seq, " CngEn: %3s\n", yesno(rssconf &
1914 CONGESTIONENABLE_F));
1915 seq_printf(seq, " HashToeplitz: %3s\n", yesno(rssconf &
1916 HASHTOEPLITZ_F));
1917 seq_printf(seq, " Udp4En: %3s\n", yesno(rssconf & UDPENABLE_F));
1918 seq_printf(seq, " Disable: %3s\n", yesno(rssconf & DISABLE_F));
1919
1920 seq_puts(seq, "\n");
1921
1922 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_TNL_A);
1923 seq_printf(seq, "TP_RSS_CONFIG_TNL: %#x\n", rssconf);
1924 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf));
1925 seq_printf(seq, " MaskFilter: %3d\n", MASKFILTER_G(rssconf));
1926 if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) {
1927 seq_printf(seq, " HashAll: %3s\n",
1928 yesno(rssconf & HASHALL_F));
1929 seq_printf(seq, " HashEth: %3s\n",
1930 yesno(rssconf & HASHETH_F));
1931 }
1932 seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F));
1933
1934 seq_puts(seq, "\n");
1935
1936 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_OFD_A);
1937 seq_printf(seq, "TP_RSS_CONFIG_OFD: %#x\n", rssconf);
1938 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf));
1939 seq_printf(seq, " RRCplMapEn: %3s\n", yesno(rssconf &
1940 RRCPLMAPEN_F));
1941 seq_printf(seq, " RRCplQueWidth: %3d\n", RRCPLQUEWIDTH_G(rssconf));
1942
1943 seq_puts(seq, "\n");
1944
1945 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_SYN_A);
1946 seq_printf(seq, "TP_RSS_CONFIG_SYN: %#x\n", rssconf);
1947 seq_printf(seq, " MaskSize: %3d\n", MASKSIZE_G(rssconf));
1948 seq_printf(seq, " UseWireCh: %3s\n", yesno(rssconf & USEWIRECH_F));
1949
1950 seq_puts(seq, "\n");
1951
1952 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
1953 seq_printf(seq, "TP_RSS_CONFIG_VRT: %#x\n", rssconf);
1954 if (CHELSIO_CHIP_VERSION(adapter->params.chip) > CHELSIO_T5) {
1955 seq_printf(seq, " KeyWrAddrX: %3d\n",
1956 KEYWRADDRX_G(rssconf));
1957 seq_printf(seq, " KeyExtend: %3s\n",
1958 yesno(rssconf & KEYEXTEND_F));
1959 }
1960 seq_printf(seq, " VfRdRg: %3s\n", yesno(rssconf & VFRDRG_F));
1961 seq_printf(seq, " VfRdEn: %3s\n", yesno(rssconf & VFRDEN_F));
1962 seq_printf(seq, " VfPerrEn: %3s\n", yesno(rssconf & VFPERREN_F));
1963 seq_printf(seq, " KeyPerrEn: %3s\n", yesno(rssconf & KEYPERREN_F));
1964 seq_printf(seq, " DisVfVlan: %3s\n", yesno(rssconf &
1965 DISABLEVLAN_F));
1966 seq_printf(seq, " EnUpSwt: %3s\n", yesno(rssconf & ENABLEUP0_F));
1967 seq_printf(seq, " HashDelay: %3d\n", HASHDELAY_G(rssconf));
1968 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
1969 seq_printf(seq, " VfWrAddr: %3d\n", VFWRADDR_G(rssconf));
3ccc6cf7
HS		 1970 else
1971 seq_printf(seq, " VfWrAddr: %3d\n",
1972 T6_VFWRADDR_G(rssconf));
688ea5fe
HS		 1973 seq_printf(seq, " KeyMode: %s\n", keymode[KEYMODE_G(rssconf)]);
1974 seq_printf(seq, " VfWrEn: %3s\n", yesno(rssconf & VFWREN_F));
1975 seq_printf(seq, " KeyWrEn: %3s\n", yesno(rssconf & KEYWREN_F));
1976 seq_printf(seq, " KeyWrAddr: %3d\n", KEYWRADDR_G(rssconf));
1977
1978 seq_puts(seq, "\n");
1979
1980 rssconf = t4_read_reg(adapter, TP_RSS_CONFIG_CNG_A);
1981 seq_printf(seq, "TP_RSS_CONFIG_CNG: %#x\n", rssconf);
1982 seq_printf(seq, " ChnCount3: %3s\n", yesno(rssconf & CHNCOUNT3_F));
1983 seq_printf(seq, " ChnCount2: %3s\n", yesno(rssconf & CHNCOUNT2_F));
1984 seq_printf(seq, " ChnCount1: %3s\n", yesno(rssconf & CHNCOUNT1_F));
1985 seq_printf(seq, " ChnCount0: %3s\n", yesno(rssconf & CHNCOUNT0_F));
1986 seq_printf(seq, " ChnUndFlow3: %3s\n", yesno(rssconf &
1987 CHNUNDFLOW3_F));
1988 seq_printf(seq, " ChnUndFlow2: %3s\n", yesno(rssconf &
1989 CHNUNDFLOW2_F));
1990 seq_printf(seq, " ChnUndFlow1: %3s\n", yesno(rssconf &
1991 CHNUNDFLOW1_F));
1992 seq_printf(seq, " ChnUndFlow0: %3s\n", yesno(rssconf &
1993 CHNUNDFLOW0_F));
1994 seq_printf(seq, " RstChn3: %3s\n", yesno(rssconf & RSTCHN3_F));
1995 seq_printf(seq, " RstChn2: %3s\n", yesno(rssconf & RSTCHN2_F));
1996 seq_printf(seq, " RstChn1: %3s\n", yesno(rssconf & RSTCHN1_F));
1997 seq_printf(seq, " RstChn0: %3s\n", yesno(rssconf & RSTCHN0_F));
1998 seq_printf(seq, " UpdVld: %3s\n", yesno(rssconf & UPDVLD_F));
1999 seq_printf(seq, " Xoff: %3s\n", yesno(rssconf & XOFF_F));
2000 seq_printf(seq, " UpdChn3: %3s\n", yesno(rssconf & UPDCHN3_F));
2001 seq_printf(seq, " UpdChn2: %3s\n", yesno(rssconf & UPDCHN2_F));
2002 seq_printf(seq, " UpdChn1: %3s\n", yesno(rssconf & UPDCHN1_F));
2003 seq_printf(seq, " UpdChn0: %3s\n", yesno(rssconf & UPDCHN0_F));
2004 seq_printf(seq, " Queue: %3d\n", QUEUE_G(rssconf));
2005
2006 return 0;
2007}
2008
2009DEFINE_SIMPLE_DEBUGFS_FILE(rss_config);
2010
2011/* RSS Secret Key.
2012 */
2013
2014static int rss_key_show(struct seq_file *seq, void *v)
2015{
2016 u32 key[10];
2017
2018 t4_read_rss_key(seq->private, key);
2019 seq_printf(seq, "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n",
2020 key[9], key[8], key[7], key[6], key[5], key[4], key[3],
2021 key[2], key[1], key[0]);
2022 return 0;
2023}
2024
2025static int rss_key_open(struct inode *inode, struct file *file)
2026{
2027 return single_open(file, rss_key_show, inode->i_private);
2028}
2029
2030static ssize_t rss_key_write(struct file *file, const char __user *buf,
2031 size_t count, loff_t *pos)
2032{
2033 int i, j;
2034 u32 key[10];
2035 char s[100], *p;
c1d81b1c 2036 struct adapter *adap = file_inode(file)->i_private;
688ea5fe
HS		 2037
2038 if (count > sizeof(s) - 1)
2039 return -EINVAL;
2040 if (copy_from_user(s, buf, count))
2041 return -EFAULT;
2042 for (i = count; i > 0 && isspace(s[i - 1]); i--)
2043 ;
2044 s[i] = '\0';
2045
2046 for (p = s, i = 9; i >= 0; i--) {
2047 key[i] = 0;
2048 for (j = 0; j < 8; j++, p++) {
2049 if (!isxdigit(*p))
2050 return -EINVAL;
2051 key[i] = (key[i] << 4) | hex2val(*p);
2052 }
2053 }
2054
2055 t4_write_rss_key(adap, key, -1);
2056 return count;
2057}
2058
2059static const struct file_operations rss_key_debugfs_fops = {
2060 .owner = THIS_MODULE,
2061 .open = rss_key_open,
2062 .read = seq_read,
2063 .llseek = seq_lseek,
2064 .release = single_release,
2065 .write = rss_key_write
2066};
2067
2068/* PF RSS Configuration.
2069 */
2070
2071struct rss_pf_conf {
2072 u32 rss_pf_map;
2073 u32 rss_pf_mask;
2074 u32 rss_pf_config;
2075};
2076
2077static int rss_pf_config_show(struct seq_file *seq, void *v, int idx)
2078{
2079 struct rss_pf_conf *pfconf;
2080
2081 if (v == SEQ_START_TOKEN) {
2082 /* use the 0th entry to dump the PF Map Index Size */
2083 pfconf = seq->private + offsetof(struct seq_tab, data);
2084 seq_printf(seq, "PF Map Index Size = %d\n\n",
2085 LKPIDXSIZE_G(pfconf->rss_pf_map));
2086
2087 seq_puts(seq, " RSS PF VF Hash Tuple Enable Default\n");
2088 seq_puts(seq, " Enable IPF Mask Mask IPv6 IPv4 UDP Queue\n");
2089 seq_puts(seq, " PF Map Chn Prt Map Size Size Four Two Four Two Four Ch1 Ch0\n");
2090 } else {
2091 #define G_PFnLKPIDX(map, n) \
2092 (((map) >> PF1LKPIDX_S*(n)) & PF0LKPIDX_M)
2093 #define G_PFnMSKSIZE(mask, n) \
2094 (((mask) >> PF1MSKSIZE_S*(n)) & PF1MSKSIZE_M)
2095
2096 pfconf = v;
2097 seq_printf(seq, "%3d %3s %3s %3s %3d %3d %3d %3s %3s %3s %3s %3s %3d %3d\n",
2098 idx,
2099 yesno(pfconf->rss_pf_config & MAPENABLE_F),
2100 yesno(pfconf->rss_pf_config & CHNENABLE_F),
2101 yesno(pfconf->rss_pf_config & PRTENABLE_F),
2102 G_PFnLKPIDX(pfconf->rss_pf_map, idx),
2103 G_PFnMSKSIZE(pfconf->rss_pf_mask, idx),
2104 IVFWIDTH_G(pfconf->rss_pf_config),
2105 yesno(pfconf->rss_pf_config & IP6FOURTUPEN_F),
2106 yesno(pfconf->rss_pf_config & IP6TWOTUPEN_F),
2107 yesno(pfconf->rss_pf_config & IP4FOURTUPEN_F),
2108 yesno(pfconf->rss_pf_config & IP4TWOTUPEN_F),
2109 yesno(pfconf->rss_pf_config & UDPFOURTUPEN_F),
2110 CH1DEFAULTQUEUE_G(pfconf->rss_pf_config),
2111 CH0DEFAULTQUEUE_G(pfconf->rss_pf_config));
2112
2113 #undef G_PFnLKPIDX
2114 #undef G_PFnMSKSIZE
2115 }
2116 return 0;
2117}
2118
2119static int rss_pf_config_open(struct inode *inode, struct file *file)
2120{
2121 struct adapter *adapter = inode->i_private;
2122 struct seq_tab *p;
2123 u32 rss_pf_map, rss_pf_mask;
2124 struct rss_pf_conf *pfconf;
2125 int pf;
2126
2127 p = seq_open_tab(file, 8, sizeof(*pfconf), 1, rss_pf_config_show);
2128 if (!p)
2129 return -ENOMEM;
2130
2131 pfconf = (struct rss_pf_conf *)p->data;
2132 rss_pf_map = t4_read_rss_pf_map(adapter);
2133 rss_pf_mask = t4_read_rss_pf_mask(adapter);
2134 for (pf = 0; pf < 8; pf++) {
2135 pfconf[pf].rss_pf_map = rss_pf_map;
2136 pfconf[pf].rss_pf_mask = rss_pf_mask;
2137 t4_read_rss_pf_config(adapter, pf, &pfconf[pf].rss_pf_config);
2138 }
2139 return 0;
2140}
2141
2142static const struct file_operations rss_pf_config_debugfs_fops = {
2143 .owner = THIS_MODULE,
2144 .open = rss_pf_config_open,
2145 .read = seq_read,
2146 .llseek = seq_lseek,
2147 .release = seq_release_private
2148};
2149
2150/* VF RSS Configuration.
2151 */
2152
2153struct rss_vf_conf {
2154 u32 rss_vf_vfl;
2155 u32 rss_vf_vfh;
2156};
2157
2158static int rss_vf_config_show(struct seq_file *seq, void *v, int idx)
2159{
2160 if (v == SEQ_START_TOKEN) {
2161 seq_puts(seq, " RSS Hash Tuple Enable\n");
2162 seq_puts(seq, " Enable IVF Dis Enb IPv6 IPv4 UDP Def Secret Key\n");
2163 seq_puts(seq, " VF Chn Prt Map VLAN uP Four Two Four Two Four Que Idx Hash\n");
2164 } else {
2165 struct rss_vf_conf *vfconf = v;
2166
2167 seq_printf(seq, "%3d %3s %3s %3d %3s %3s %3s %3s %3s %3s %3s %4d %3d %#10x\n",
2168 idx,
2169 yesno(vfconf->rss_vf_vfh & VFCHNEN_F),
2170 yesno(vfconf->rss_vf_vfh & VFPRTEN_F),
2171 VFLKPIDX_G(vfconf->rss_vf_vfh),
2172 yesno(vfconf->rss_vf_vfh & VFVLNEX_F),
2173 yesno(vfconf->rss_vf_vfh & VFUPEN_F),
2174 yesno(vfconf->rss_vf_vfh & VFIP4FOURTUPEN_F),
2175 yesno(vfconf->rss_vf_vfh & VFIP6TWOTUPEN_F),
2176 yesno(vfconf->rss_vf_vfh & VFIP4FOURTUPEN_F),
2177 yesno(vfconf->rss_vf_vfh & VFIP4TWOTUPEN_F),
2178 yesno(vfconf->rss_vf_vfh & ENABLEUDPHASH_F),
2179 DEFAULTQUEUE_G(vfconf->rss_vf_vfh),
2180 KEYINDEX_G(vfconf->rss_vf_vfh),
2181 vfconf->rss_vf_vfl);
2182 }
2183 return 0;
2184}
2185
2186static int rss_vf_config_open(struct inode *inode, struct file *file)
2187{
2188 struct adapter *adapter = inode->i_private;
2189 struct seq_tab *p;
2190 struct rss_vf_conf *vfconf;
3ccc6cf7 2191 int vf, vfcount = adapter->params.arch.vfcount;
688ea5fe 2192
3ccc6cf7 2193 p = seq_open_tab(file, vfcount, sizeof(*vfconf), 1, rss_vf_config_show);
688ea5fe
HS		 2194 if (!p)
2195 return -ENOMEM;
2196
2197 vfconf = (struct rss_vf_conf *)p->data;
3ccc6cf7 2198 for (vf = 0; vf < vfcount; vf++) {
688ea5fe
HS		 2199 t4_read_rss_vf_config(adapter, vf, &vfconf[vf].rss_vf_vfl,
2200 &vfconf[vf].rss_vf_vfh);
2201 }
2202 return 0;
2203}
2204
2205static const struct file_operations rss_vf_config_debugfs_fops = {
2206 .owner = THIS_MODULE,
2207 .open = rss_vf_config_open,
2208 .read = seq_read,
2209 .llseek = seq_lseek,
2210 .release = seq_release_private
2211};
2212
3051fa61
HS		 2213/**
2214 * ethqset2pinfo - return port_info of an Ethernet Queue Set
2215 * @adap: the adapter
2216 * @qset: Ethernet Queue Set
2217 */
2218static inline struct port_info *ethqset2pinfo(struct adapter *adap, int qset)
2219{
2220 int pidx;
2221
2222 for_each_port(adap, pidx) {
2223 struct port_info *pi = adap2pinfo(adap, pidx);
2224
2225 if (qset >= pi->first_qset &&
2226 qset < pi->first_qset + pi->nqsets)
2227 return pi;
2228 }
2229
2230 /* should never happen! */
2231 BUG_ON(1);
2232 return NULL;
2233}
2234
dc9daab2
HS		 2235static int sge_qinfo_show(struct seq_file *seq, void *v)
2236{
2237 struct adapter *adap = seq->private;
2238 int eth_entries = DIV_ROUND_UP(adap->sge.ethqsets, 4);
e106a4d9 2239 int iscsi_entries = DIV_ROUND_UP(adap->sge.ofldqsets, 4);
dc9daab2
HS		 2240 int rdma_entries = DIV_ROUND_UP(adap->sge.rdmaqs, 4);
2241 int ciq_entries = DIV_ROUND_UP(adap->sge.rdmaciqs, 4);
2242 int ctrl_entries = DIV_ROUND_UP(MAX_CTRL_QUEUES, 4);
2243 int i, r = (uintptr_t)v - 1;
e106a4d9
HS		 2244 int iscsi_idx = r - eth_entries;
2245 int rdma_idx = iscsi_idx - iscsi_entries;
dc9daab2
HS		 2246 int ciq_idx = rdma_idx - rdma_entries;
2247 int ctrl_idx = ciq_idx - ciq_entries;
2248 int fq_idx = ctrl_idx - ctrl_entries;
2249
2250 if (r)
2251 seq_putc(seq, '\n');
2252
2253#define S3(fmt_spec, s, v) \
2254do { \
2255 seq_printf(seq, "%-12s", s); \
2256 for (i = 0; i < n; ++i) \
2257 seq_printf(seq, " %16" fmt_spec, v); \
2258 seq_putc(seq, '\n'); \
2259} while (0)
2260#define S(s, v) S3("s", s, v)
e106a4d9 2261#define T3(fmt_spec, s, v) S3(fmt_spec, s, tx[i].v)
dc9daab2 2262#define T(s, v) S3("u", s, tx[i].v)
e106a4d9
HS		 2263#define TL(s, v) T3("lu", s, v)
2264#define R3(fmt_spec, s, v) S3(fmt_spec, s, rx[i].v)
dc9daab2 2265#define R(s, v) S3("u", s, rx[i].v)
e106a4d9 2266#define RL(s, v) R3("lu", s, v)
dc9daab2
HS		 2267
2268 if (r < eth_entries) {
2269 int base_qset = r * 4;
2270 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[base_qset];
2271 const struct sge_eth_txq *tx = &adap->sge.ethtxq[base_qset];
2272 int n = min(4, adap->sge.ethqsets - 4 * r);
2273
2274 S("QType:", "Ethernet");
2275 S("Interface:",
2276 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A");
2277 T("TxQ ID:", q.cntxt_id);
2278 T("TxQ size:", q.size);
2279 T("TxQ inuse:", q.in_use);
2280 T("TxQ CIDX:", q.cidx);
2281 T("TxQ PIDX:", q.pidx);
3051fa61 2282#ifdef CONFIG_CHELSIO_T4_DCB
dc9daab2
HS		 2283 T("DCB Prio:", dcb_prio);
2284 S3("u", "DCB PGID:",
2285 (ethqset2pinfo(adap, base_qset + i)->dcb.pgid >>
2286 4*(7-tx[i].dcb_prio)) & 0xf);
2287 S3("u", "DCB PFC:",
2288 (ethqset2pinfo(adap, base_qset + i)->dcb.pfcen >>
2289 1*(7-tx[i].dcb_prio)) & 0x1);
2290#endif
2291 R("RspQ ID:", rspq.abs_id);
2292 R("RspQ size:", rspq.size);
2293 R("RspQE size:", rspq.iqe_len);
2294 R("RspQ CIDX:", rspq.cidx);
2295 R("RspQ Gen:", rspq.gen);
2296 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
2297 S3("u", "Intr pktcnt:",
2298 adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);
2299 R("FL ID:", fl.cntxt_id);
2300 R("FL size:", fl.size - 8);
2301 R("FL pend:", fl.pend_cred);
2302 R("FL avail:", fl.avail);
2303 R("FL PIDX:", fl.pidx);
2304 R("FL CIDX:", fl.cidx);
e106a4d9
HS		 2305 RL("RxPackets:", stats.pkts);
2306 RL("RxCSO:", stats.rx_cso);
2307 RL("VLANxtract:", stats.vlan_ex);
2308 RL("LROmerged:", stats.lro_merged);
2309 RL("LROpackets:", stats.lro_pkts);
2310 RL("RxDrops:", stats.rx_drops);
2311 TL("TSO:", tso);
2312 TL("TxCSO:", tx_cso);
2313 TL("VLANins:", vlan_ins);
2314 TL("TxQFull:", q.stops);
2315 TL("TxQRestarts:", q.restarts);
2316 TL("TxMapErr:", mapping_err);
2317 RL("FLAllocErr:", fl.alloc_failed);
2318 RL("FLLrgAlcErr:", fl.large_alloc_failed);
2319 RL("FLStarving:", fl.starving);
2320
2321 } else if (iscsi_idx < iscsi_entries) {
2322 const struct sge_ofld_rxq *rx =
2323 &adap->sge.ofldrxq[iscsi_idx * 4];
2324 const struct sge_ofld_txq *tx =
2325 &adap->sge.ofldtxq[iscsi_idx * 4];
2326 int n = min(4, adap->sge.ofldqsets - 4 * iscsi_idx);
dc9daab2 2327
e106a4d9 2328 S("QType:", "iSCSI");
dc9daab2
HS		 2329 T("TxQ ID:", q.cntxt_id);
2330 T("TxQ size:", q.size);
2331 T("TxQ inuse:", q.in_use);
2332 T("TxQ CIDX:", q.cidx);
2333 T("TxQ PIDX:", q.pidx);
2334 R("RspQ ID:", rspq.abs_id);
2335 R("RspQ size:", rspq.size);
2336 R("RspQE size:", rspq.iqe_len);
2337 R("RspQ CIDX:", rspq.cidx);
2338 R("RspQ Gen:", rspq.gen);
2339 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
2340 S3("u", "Intr pktcnt:",
2341 adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);
2342 R("FL ID:", fl.cntxt_id);
2343 R("FL size:", fl.size - 8);
2344 R("FL pend:", fl.pend_cred);
2345 R("FL avail:", fl.avail);
2346 R("FL PIDX:", fl.pidx);
2347 R("FL CIDX:", fl.cidx);
e106a4d9
HS		 2348 RL("RxPackets:", stats.pkts);
2349 RL("RxImmPkts:", stats.imm);
2350 RL("RxNoMem:", stats.nomem);
2351 RL("FLAllocErr:", fl.alloc_failed);
2352 RL("FLLrgAlcErr:", fl.large_alloc_failed);
2353 RL("FLStarving:", fl.starving);
2354
dc9daab2
HS		 2355 } else if (rdma_idx < rdma_entries) {
2356 const struct sge_ofld_rxq *rx =
2357 &adap->sge.rdmarxq[rdma_idx * 4];
2358 int n = min(4, adap->sge.rdmaqs - 4 * rdma_idx);
2359
2360 S("QType:", "RDMA-CPL");
f36e58e5
HS		 2361 S("Interface:",
2362 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A");
dc9daab2
HS		 2363 R("RspQ ID:", rspq.abs_id);
2364 R("RspQ size:", rspq.size);
2365 R("RspQE size:", rspq.iqe_len);
2366 R("RspQ CIDX:", rspq.cidx);
2367 R("RspQ Gen:", rspq.gen);
2368 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
2369 S3("u", "Intr pktcnt:",
2370 adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);
2371 R("FL ID:", fl.cntxt_id);
2372 R("FL size:", fl.size - 8);
2373 R("FL pend:", fl.pend_cred);
2374 R("FL avail:", fl.avail);
2375 R("FL PIDX:", fl.pidx);
2376 R("FL CIDX:", fl.cidx);
e106a4d9
HS		 2377 RL("RxPackets:", stats.pkts);
2378 RL("RxImmPkts:", stats.imm);
2379 RL("RxNoMem:", stats.nomem);
2380 RL("FLAllocErr:", fl.alloc_failed);
2381 RL("FLLrgAlcErr:", fl.large_alloc_failed);
2382 RL("FLStarving:", fl.starving);
2383
dc9daab2
HS		 2384 } else if (ciq_idx < ciq_entries) {
2385 const struct sge_ofld_rxq *rx = &adap->sge.rdmaciq[ciq_idx * 4];
2386 int n = min(4, adap->sge.rdmaciqs - 4 * ciq_idx);
2387
2388 S("QType:", "RDMA-CIQ");
f36e58e5
HS		 2389 S("Interface:",
2390 rx[i].rspq.netdev ? rx[i].rspq.netdev->name : "N/A");
dc9daab2
HS		 2391 R("RspQ ID:", rspq.abs_id);
2392 R("RspQ size:", rspq.size);
2393 R("RspQE size:", rspq.iqe_len);
2394 R("RspQ CIDX:", rspq.cidx);
2395 R("RspQ Gen:", rspq.gen);
2396 S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
2397 S3("u", "Intr pktcnt:",
2398 adap->sge.counter_val[rx[i].rspq.pktcnt_idx]);
e106a4d9
HS		 2399 RL("RxAN:", stats.an);
2400 RL("RxNoMem:", stats.nomem);
2401
dc9daab2
HS		 2402 } else if (ctrl_idx < ctrl_entries) {
2403 const struct sge_ctrl_txq *tx = &adap->sge.ctrlq[ctrl_idx * 4];
2404 int n = min(4, adap->params.nports - 4 * ctrl_idx);
2405
2406 S("QType:", "Control");
2407 T("TxQ ID:", q.cntxt_id);
2408 T("TxQ size:", q.size);
2409 T("TxQ inuse:", q.in_use);
2410 T("TxQ CIDX:", q.cidx);
2411 T("TxQ PIDX:", q.pidx);
e106a4d9
HS		 2412 TL("TxQFull:", q.stops);
2413 TL("TxQRestarts:", q.restarts);
dc9daab2
HS		 2414 } else if (fq_idx == 0) {
2415 const struct sge_rspq *evtq = &adap->sge.fw_evtq;
2416
2417 seq_printf(seq, "%-12s %16s\n", "QType:", "FW event queue");
2418 seq_printf(seq, "%-12s %16u\n", "RspQ ID:", evtq->abs_id);
2419 seq_printf(seq, "%-12s %16u\n", "RspQ size:", evtq->size);
2420 seq_printf(seq, "%-12s %16u\n", "RspQE size:", evtq->iqe_len);
2421 seq_printf(seq, "%-12s %16u\n", "RspQ CIDX:", evtq->cidx);
2422 seq_printf(seq, "%-12s %16u\n", "RspQ Gen:", evtq->gen);
2423 seq_printf(seq, "%-12s %16u\n", "Intr delay:",
2424 qtimer_val(adap, evtq));
2425 seq_printf(seq, "%-12s %16u\n", "Intr pktcnt:",
2426 adap->sge.counter_val[evtq->pktcnt_idx]);
2427 }
2428#undef R
e106a4d9 2429#undef RL
dc9daab2 2430#undef T
e106a4d9 2431#undef TL
dc9daab2 2432#undef S
e106a4d9
HS		 2433#undef R3
2434#undef T3
dc9daab2 2435#undef S3
2f3a8732 2436 return 0;
dc9daab2
HS		 2437}
2438
2439static int sge_queue_entries(const struct adapter *adap)
2440{
2441 return DIV_ROUND_UP(adap->sge.ethqsets, 4) +
2442 DIV_ROUND_UP(adap->sge.ofldqsets, 4) +
2443 DIV_ROUND_UP(adap->sge.rdmaqs, 4) +
2444 DIV_ROUND_UP(adap->sge.rdmaciqs, 4) +
2445 DIV_ROUND_UP(MAX_CTRL_QUEUES, 4) + 1;
2446}
2447
2448static void *sge_queue_start(struct seq_file *seq, loff_t *pos)
2449{
2450 int entries = sge_queue_entries(seq->private);
2451
2452 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
2453}
2454
2455static void sge_queue_stop(struct seq_file *seq, void *v)
2456{
2457}
2458
2459static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos)
2460{
2461 int entries = sge_queue_entries(seq->private);
2462
2463 ++*pos;
2464 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
2465}
2466
2467static const struct seq_operations sge_qinfo_seq_ops = {
2468 .start = sge_queue_start,
2469 .next = sge_queue_next,
2470 .stop = sge_queue_stop,
2471 .show = sge_qinfo_show
2472};
2473
2474static int sge_qinfo_open(struct inode *inode, struct file *file)
2475{
2476 int res = seq_open(file, &sge_qinfo_seq_ops);
2477
2478 if (!res) {
2479 struct seq_file *seq = file->private_data;
2480
2481 seq->private = inode->i_private;
2482 }
2483 return res;
2484}
2485
2486static const struct file_operations sge_qinfo_debugfs_fops = {
2487 .owner = THIS_MODULE,
2488 .open = sge_qinfo_open,
2489 .read = seq_read,
2490 .llseek = seq_lseek,
2491 .release = seq_release,
2492};
2493
49216c1c
HS		 2494int mem_open(struct inode *inode, struct file *file)
2495{
2496 unsigned int mem;
2497 struct adapter *adap;
2498
2499 file->private_data = inode->i_private;
2500
2501 mem = (uintptr_t)file->private_data & 0x3;
2502 adap = file->private_data - mem;
2503
2504 (void)t4_fwcache(adap, FW_PARAM_DEV_FWCACHE_FLUSH);
2505
2506 return 0;
2507}
2508
fd88b31a
HS		 2509static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
2510 loff_t *ppos)
2511{
2512 loff_t pos = *ppos;
2513 loff_t avail = file_inode(file)->i_size;
2514 unsigned int mem = (uintptr_t)file->private_data & 3;
2515 struct adapter *adap = file->private_data - mem;
2516 __be32 *data;
2517 int ret;
2518
2519 if (pos < 0)
2520 return -EINVAL;
2521 if (pos >= avail)
2522 return 0;
2523 if (count > avail - pos)
2524 count = avail - pos;
2525
2526 data = t4_alloc_mem(count);
2527 if (!data)
2528 return -ENOMEM;
2529
2530 spin_lock(&adap->win0_lock);
2531 ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ);
2532 spin_unlock(&adap->win0_lock);
2533 if (ret) {
2534 t4_free_mem(data);
2535 return ret;
2536 }
2537 ret = copy_to_user(buf, data, count);
2538
2539 t4_free_mem(data);
2540 if (ret)
2541 return -EFAULT;
2542
2543 *ppos = pos + count;
2544 return count;
2545}
fd88b31a
HS		 2546static const struct file_operations mem_debugfs_fops = {
2547 .owner = THIS_MODULE,
2548 .open = simple_open,
2549 .read = mem_read,
2550 .llseek = default_llseek,
2551};
2552
a4011fd4
HS		 2553static int tid_info_show(struct seq_file *seq, void *v)
2554{
2555 struct adapter *adap = seq->private;
2556 const struct tid_info *t = &adap->tids;
2557 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
2558
2559 if (t4_read_reg(adap, LE_DB_CONFIG_A) & HASHEN_F) {
2560 unsigned int sb;
2561
2562 if (chip <= CHELSIO_T5)
2563 sb = t4_read_reg(adap, LE_DB_SERVER_INDEX_A) / 4;
2564 else
2565 sb = t4_read_reg(adap, LE_DB_SRVR_START_INDEX_A);
2566
2567 if (sb) {
2568 seq_printf(seq, "TID range: 0..%u/%u..%u", sb - 1,
2569 adap->tids.hash_base,
2570 t->ntids - 1);
2571 seq_printf(seq, ", in use: %u/%u\n",
2572 atomic_read(&t->tids_in_use),
2573 atomic_read(&t->hash_tids_in_use));
2574 } else if (adap->flags & FW_OFLD_CONN) {
2575 seq_printf(seq, "TID range: %u..%u/%u..%u",
2576 t->aftid_base,
2577 t->aftid_end,
2578 adap->tids.hash_base,
2579 t->ntids - 1);
2580 seq_printf(seq, ", in use: %u/%u\n",
2581 atomic_read(&t->tids_in_use),
2582 atomic_read(&t->hash_tids_in_use));
2583 } else {
2584 seq_printf(seq, "TID range: %u..%u",
2585 adap->tids.hash_base,
2586 t->ntids - 1);
2587 seq_printf(seq, ", in use: %u\n",
2588 atomic_read(&t->hash_tids_in_use));
2589 }
2590 } else if (t->ntids) {
2591 seq_printf(seq, "TID range: 0..%u", t->ntids - 1);
2592 seq_printf(seq, ", in use: %u\n",
2593 atomic_read(&t->tids_in_use));
2594 }
2595
2596 if (t->nstids)
2597 seq_printf(seq, "STID range: %u..%u, in use: %u\n",
2598 (!t->stid_base &&
2599 (chip <= CHELSIO_T5)) ?
2600 t->stid_base + 1 : t->stid_base,
2601 t->stid_base + t->nstids - 1, t->stids_in_use);
2602 if (t->natids)
2603 seq_printf(seq, "ATID range: 0..%u, in use: %u\n",
2604 t->natids - 1, t->atids_in_use);
2605 seq_printf(seq, "FTID range: %u..%u\n", t->ftid_base,
2606 t->ftid_base + t->nftids - 1);
2607 if (t->nsftids)
2608 seq_printf(seq, "SFTID range: %u..%u in use: %u\n",
2609 t->sftid_base, t->sftid_base + t->nsftids - 2,
2610 t->sftids_in_use);
2611 if (t->ntids)
2612 seq_printf(seq, "HW TID usage: %u IP users, %u IPv6 users\n",
2613 t4_read_reg(adap, LE_DB_ACT_CNT_IPV4_A),
2614 t4_read_reg(adap, LE_DB_ACT_CNT_IPV6_A));
2615 return 0;
2616}
2617
2618DEFINE_SIMPLE_DEBUGFS_FILE(tid_info);
2619
fd88b31a
HS		 2620static void add_debugfs_mem(struct adapter *adap, const char *name,
2621 unsigned int idx, unsigned int size_mb)
2622{
e59b4e91
DH		 2623 debugfs_create_file_size(name, S_IRUSR, adap->debugfs_root,
2624 (void *)adap + idx, &mem_debugfs_fops,
2625 size_mb << 20);
fd88b31a
HS		 2626}
2627
5b377d11
HS		 2628static int blocked_fl_open(struct inode *inode, struct file *file)
2629{
2630 file->private_data = inode->i_private;
2631 return 0;
2632}
2633
2634static ssize_t blocked_fl_read(struct file *filp, char __user *ubuf,
2635 size_t count, loff_t *ppos)
2636{
2637 int len;
2638 const struct adapter *adap = filp->private_data;
2639 char *buf;
2640 ssize_t size = (adap->sge.egr_sz + 3) / 4 +
2641 adap->sge.egr_sz / 32 + 2; /* includes ,/\n/\0 */
2642
2643 buf = kzalloc(size, GFP_KERNEL);
2644 if (!buf)
2645 return -ENOMEM;
2646
2647 len = snprintf(buf, size - 1, "%*pb\n",
2648 adap->sge.egr_sz, adap->sge.blocked_fl);
2649 len += sprintf(buf + len, "\n");
2650 size = simple_read_from_buffer(ubuf, count, ppos, buf, len);
2651 t4_free_mem(buf);
2652 return size;
2653}
2654
2655static ssize_t blocked_fl_write(struct file *filp, const char __user *ubuf,
2656 size_t count, loff_t *ppos)
2657{
2658 int err;
2659 unsigned long *t;
2660 struct adapter *adap = filp->private_data;
2661
2662 t = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), sizeof(long), GFP_KERNEL);
2663 if (!t)
2664 return -ENOMEM;
2665
2666 err = bitmap_parse_user(ubuf, count, t, adap->sge.egr_sz);
2667 if (err)
2668 return err;
2669
2670 bitmap_copy(adap->sge.blocked_fl, t, adap->sge.egr_sz);
2671 t4_free_mem(t);
2672 return count;
2673}
2674
2675static const struct file_operations blocked_fl_fops = {
2676 .owner = THIS_MODULE,
2677 .open = blocked_fl_open,
2678 .read = blocked_fl_read,
2679 .write = blocked_fl_write,
2680 .llseek = generic_file_llseek,
2681};
2682
5888111c
HS		 2683struct mem_desc {
2684 unsigned int base;
2685 unsigned int limit;
2686 unsigned int idx;
2687};
2688
2689static int mem_desc_cmp(const void *a, const void *b)
2690{
2691 return ((const struct mem_desc *)a)->base -
2692 ((const struct mem_desc *)b)->base;
2693}
2694
2695static void mem_region_show(struct seq_file *seq, const char *name,
2696 unsigned int from, unsigned int to)
2697{
2698 char buf[40];
2699
2700 string_get_size((u64)to - from + 1, 1, STRING_UNITS_2, buf,
2701 sizeof(buf));
2702 seq_printf(seq, "%-15s %#x-%#x [%s]\n", name, from, to, buf);
2703}
2704
2705static int meminfo_show(struct seq_file *seq, void *v)
2706{
2707 static const char * const memory[] = { "EDC0:", "EDC1:", "MC:",
2708 "MC0:", "MC1:"};
2709 static const char * const region[] = {
2710 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
2711 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
2712 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
2713 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
2714 "RQUDP region:", "PBL region:", "TXPBL region:",
2715 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
2716 "On-chip queues:"
2717 };
2718
2719 int i, n;
2720 u32 lo, hi, used, alloc;
2721 struct mem_desc avail[4];
2722 struct mem_desc mem[ARRAY_SIZE(region) + 3]; /* up to 3 holes */
2723 struct mem_desc *md = mem;
2724 struct adapter *adap = seq->private;
2725
2726 for (i = 0; i < ARRAY_SIZE(mem); i++) {
2727 mem[i].limit = 0;
2728 mem[i].idx = i;
2729 }
2730
2731 /* Find and sort the populated memory ranges */
2732 i = 0;
2733 lo = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
2734 if (lo & EDRAM0_ENABLE_F) {
2735 hi = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2736 avail[i].base = EDRAM0_BASE_G(hi) << 20;
2737 avail[i].limit = avail[i].base + (EDRAM0_SIZE_G(hi) << 20);
2738 avail[i].idx = 0;
2739 i++;
2740 }
2741 if (lo & EDRAM1_ENABLE_F) {
2742 hi = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2743 avail[i].base = EDRAM1_BASE_G(hi) << 20;
2744 avail[i].limit = avail[i].base + (EDRAM1_SIZE_G(hi) << 20);
2745 avail[i].idx = 1;
2746 i++;
2747 }
2748
2749 if (is_t5(adap->params.chip)) {
2750 if (lo & EXT_MEM0_ENABLE_F) {
2751 hi = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2752 avail[i].base = EXT_MEM0_BASE_G(hi) << 20;
2753 avail[i].limit =
2754 avail[i].base + (EXT_MEM0_SIZE_G(hi) << 20);
2755 avail[i].idx = 3;
2756 i++;
2757 }
2758 if (lo & EXT_MEM1_ENABLE_F) {
2759 hi = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2760 avail[i].base = EXT_MEM1_BASE_G(hi) << 20;
2761 avail[i].limit =
2762 avail[i].base + (EXT_MEM1_SIZE_G(hi) << 20);
2763 avail[i].idx = 4;
2764 i++;
2765 }
2766 } else {
2767 if (lo & EXT_MEM_ENABLE_F) {
2768 hi = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
2769 avail[i].base = EXT_MEM_BASE_G(hi) << 20;
2770 avail[i].limit =
2771 avail[i].base + (EXT_MEM_SIZE_G(hi) << 20);
2772 avail[i].idx = 2;
2773 i++;
2774 }
2775 }
2776 if (!i) /* no memory available */
2777 return 0;
2778 sort(avail, i, sizeof(struct mem_desc), mem_desc_cmp, NULL);
2779
2780 (md++)->base = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A);
2781 (md++)->base = t4_read_reg(adap, SGE_IMSG_CTXT_BADDR_A);
2782 (md++)->base = t4_read_reg(adap, SGE_FLM_CACHE_BADDR_A);
2783 (md++)->base = t4_read_reg(adap, TP_CMM_TCB_BASE_A);
2784 (md++)->base = t4_read_reg(adap, TP_CMM_MM_BASE_A);
2785 (md++)->base = t4_read_reg(adap, TP_CMM_TIMER_BASE_A);
2786 (md++)->base = t4_read_reg(adap, TP_CMM_MM_RX_FLST_BASE_A);
2787 (md++)->base = t4_read_reg(adap, TP_CMM_MM_TX_FLST_BASE_A);
2788 (md++)->base = t4_read_reg(adap, TP_CMM_MM_PS_FLST_BASE_A);
2789
2790 /* the next few have explicit upper bounds */
2791 md->base = t4_read_reg(adap, TP_PMM_TX_BASE_A);
2792 md->limit = md->base - 1 +
2793 t4_read_reg(adap, TP_PMM_TX_PAGE_SIZE_A) *
2794 PMTXMAXPAGE_G(t4_read_reg(adap, TP_PMM_TX_MAX_PAGE_A));
2795 md++;
2796
2797 md->base = t4_read_reg(adap, TP_PMM_RX_BASE_A);
2798 md->limit = md->base - 1 +
2799 t4_read_reg(adap, TP_PMM_RX_PAGE_SIZE_A) *
2800 PMRXMAXPAGE_G(t4_read_reg(adap, TP_PMM_RX_MAX_PAGE_A));
2801 md++;
2802
2803 if (t4_read_reg(adap, LE_DB_CONFIG_A) & HASHEN_F) {
2804 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) {
2805 hi = t4_read_reg(adap, LE_DB_TID_HASHBASE_A) / 4;
2806 md->base = t4_read_reg(adap, LE_DB_HASH_TID_BASE_A);
2807 } else {
2808 hi = t4_read_reg(adap, LE_DB_HASH_TID_BASE_A);
2809 md->base = t4_read_reg(adap,
2810 LE_DB_HASH_TBL_BASE_ADDR_A);
2811 }
2812 md->limit = 0;
2813 } else {
2814 md->base = 0;
2815 md->idx = ARRAY_SIZE(region); /* hide it */
2816 }
2817 md++;
2818
2819#define ulp_region(reg) do { \
2820 md->base = t4_read_reg(adap, ULP_ ## reg ## _LLIMIT_A);\
2821 (md++)->limit = t4_read_reg(adap, ULP_ ## reg ## _ULIMIT_A); \
2822} while (0)
2823
2824 ulp_region(RX_ISCSI);
2825 ulp_region(RX_TDDP);
2826 ulp_region(TX_TPT);
2827 ulp_region(RX_STAG);
2828 ulp_region(RX_RQ);
2829 ulp_region(RX_RQUDP);
2830 ulp_region(RX_PBL);
2831 ulp_region(TX_PBL);
2832#undef ulp_region
2833 md->base = 0;
2834 md->idx = ARRAY_SIZE(region);
2835 if (!is_t4(adap->params.chip)) {
2836 u32 size = 0;
2837 u32 sge_ctrl = t4_read_reg(adap, SGE_CONTROL2_A);
2838 u32 fifo_size = t4_read_reg(adap, SGE_DBVFIFO_SIZE_A);
2839
2840 if (is_t5(adap->params.chip)) {
2841 if (sge_ctrl & VFIFO_ENABLE_F)
2842 size = DBVFIFO_SIZE_G(fifo_size);
2843 } else {
2844 size = T6_DBVFIFO_SIZE_G(fifo_size);
2845 }
2846
2847 if (size) {
2848 md->base = BASEADDR_G(t4_read_reg(adap,
2849 SGE_DBVFIFO_BADDR_A));
2850 md->limit = md->base + (size << 2) - 1;
2851 }
2852 }
2853
2854 md++;
2855
2856 md->base = t4_read_reg(adap, ULP_RX_CTX_BASE_A);
2857 md->limit = 0;
2858 md++;
2859 md->base = t4_read_reg(adap, ULP_TX_ERR_TABLE_BASE_A);
2860 md->limit = 0;
2861 md++;
2862
2863 md->base = adap->vres.ocq.start;
2864 if (adap->vres.ocq.size)
2865 md->limit = md->base + adap->vres.ocq.size - 1;
2866 else
2867 md->idx = ARRAY_SIZE(region); /* hide it */
2868 md++;
2869
2870 /* add any address-space holes, there can be up to 3 */
2871 for (n = 0; n < i - 1; n++)
2872 if (avail[n].limit < avail[n + 1].base)
2873 (md++)->base = avail[n].limit;
2874 if (avail[n].limit)
2875 (md++)->base = avail[n].limit;
2876
2877 n = md - mem;
2878 sort(mem, n, sizeof(struct mem_desc), mem_desc_cmp, NULL);
2879
2880 for (lo = 0; lo < i; lo++)
2881 mem_region_show(seq, memory[avail[lo].idx], avail[lo].base,
2882 avail[lo].limit - 1);
2883
2884 seq_putc(seq, '\n');
2885 for (i = 0; i < n; i++) {
2886 if (mem[i].idx >= ARRAY_SIZE(region))
2887 continue; /* skip holes */
2888 if (!mem[i].limit)
2889 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
2890 mem_region_show(seq, region[mem[i].idx], mem[i].base,
2891 mem[i].limit);
2892 }
2893
2894 seq_putc(seq, '\n');
2895 lo = t4_read_reg(adap, CIM_SDRAM_BASE_ADDR_A);
2896 hi = t4_read_reg(adap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1;
2897 mem_region_show(seq, "uP RAM:", lo, hi);
2898
2899 lo = t4_read_reg(adap, CIM_EXTMEM2_BASE_ADDR_A);
2900 hi = t4_read_reg(adap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1;
2901 mem_region_show(seq, "uP Extmem2:", lo, hi);
2902
2903 lo = t4_read_reg(adap, TP_PMM_RX_MAX_PAGE_A);
2904 seq_printf(seq, "\n%u Rx pages of size %uKiB for %u channels\n",
2905 PMRXMAXPAGE_G(lo),
2906 t4_read_reg(adap, TP_PMM_RX_PAGE_SIZE_A) >> 10,
2907 (lo & PMRXNUMCHN_F) ? 2 : 1);
2908
2909 lo = t4_read_reg(adap, TP_PMM_TX_MAX_PAGE_A);
2910 hi = t4_read_reg(adap, TP_PMM_TX_PAGE_SIZE_A);
2911 seq_printf(seq, "%u Tx pages of size %u%ciB for %u channels\n",
2912 PMTXMAXPAGE_G(lo),
2913 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
2914 hi >= (1 << 20) ? 'M' : 'K', 1 << PMTXNUMCHN_G(lo));
2915 seq_printf(seq, "%u p-structs\n\n",
2916 t4_read_reg(adap, TP_CMM_MM_MAX_PSTRUCT_A));
2917
2918 for (i = 0; i < 4; i++) {
2919 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5)
2920 lo = t4_read_reg(adap, MPS_RX_MAC_BG_PG_CNT0_A + i * 4);
2921 else
2922 lo = t4_read_reg(adap, MPS_RX_PG_RSV0_A + i * 4);
2923 if (is_t5(adap->params.chip)) {
2924 used = T5_USED_G(lo);
2925 alloc = T5_ALLOC_G(lo);
2926 } else {
2927 used = USED_G(lo);
2928 alloc = ALLOC_G(lo);
2929 }
2930 /* For T6 these are MAC buffer groups */
2931 seq_printf(seq, "Port %d using %u pages out of %u allocated\n",
2932 i, used, alloc);
2933 }
2934 for (i = 0; i < adap->params.arch.nchan; i++) {
2935 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5)
2936 lo = t4_read_reg(adap,
2937 MPS_RX_LPBK_BG_PG_CNT0_A + i * 4);
2938 else
2939 lo = t4_read_reg(adap, MPS_RX_PG_RSV4_A + i * 4);
2940 if (is_t5(adap->params.chip)) {
2941 used = T5_USED_G(lo);
2942 alloc = T5_ALLOC_G(lo);
2943 } else {
2944 used = USED_G(lo);
2945 alloc = ALLOC_G(lo);
2946 }
2947 /* For T6 these are MAC buffer groups */
2948 seq_printf(seq,
2949 "Loopback %d using %u pages out of %u allocated\n",
2950 i, used, alloc);
2951 }
2952 return 0;
2953}
2954
2955static int meminfo_open(struct inode *inode, struct file *file)
2956{
2957 return single_open(file, meminfo_show, inode->i_private);
2958}
2959
2960static const struct file_operations meminfo_fops = {
2961 .owner = THIS_MODULE,
2962 .open = meminfo_open,
2963 .read = seq_read,
2964 .llseek = seq_lseek,
2965 .release = single_release,
2966};
fd88b31a
HS		 2967/* Add an array of Debug FS files.
2968 */
2969void add_debugfs_files(struct adapter *adap,
2970 struct t4_debugfs_entry *files,
2971 unsigned int nfiles)
2972{
2973 int i;
2974
2975 /* debugfs support is best effort */
2976 for (i = 0; i < nfiles; i++)
2977 debugfs_create_file(files[i].name, files[i].mode,
2978 adap->debugfs_root,
2979 (void *)adap + files[i].data,
2980 files[i].ops);
2981}
2982
2983int t4_setup_debugfs(struct adapter *adap)
2984{
2985 int i;
3ccc6cf7 2986 u32 size = 0;
49216c1c 2987 struct dentry *de;
fd88b31a
HS		 2988
2989 static struct t4_debugfs_entry t4_debugfs_files[] = {
f1ff24aa 2990 { "cim_la", &cim_la_fops, S_IRUSR, 0 },
19689609 2991 { "cim_pif_la", &cim_pif_la_fops, S_IRUSR, 0 },
26fae93f 2992 { "cim_ma_la", &cim_ma_la_fops, S_IRUSR, 0 },
74b3092c 2993 { "cim_qcfg", &cim_qcfg_fops, S_IRUSR, 0 },
b58b6676 2994 { "clk", &clk_debugfs_fops, S_IRUSR, 0 },
49aa284f 2995 { "devlog", &devlog_fops, S_IRUSR, 0 },
bf7c781d
HS		 2996 { "mbox0", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 0 },
2997 { "mbox1", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 1 },
2998 { "mbox2", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 2 },
2999 { "mbox3", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 3 },
3000 { "mbox4", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 4 },
3001 { "mbox5", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 5 },
3002 { "mbox6", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 6 },
3003 { "mbox7", &mbox_debugfs_fops, S_IRUSR | S_IWUSR, 7 },
8e3d04fd
HS		 3004 { "trace0", &mps_trc_debugfs_fops, S_IRUSR | S_IWUSR, 0 },
3005 { "trace1", &mps_trc_debugfs_fops, S_IRUSR | S_IWUSR, 1 },
3006 { "trace2", &mps_trc_debugfs_fops, S_IRUSR | S_IWUSR, 2 },
3007 { "trace3", &mps_trc_debugfs_fops, S_IRUSR | S_IWUSR, 3 },
fd88b31a 3008 { "l2t", &t4_l2t_fops, S_IRUSR, 0},
ef82f662 3009 { "mps_tcam", &mps_tcam_debugfs_fops, S_IRUSR, 0 },
688ea5fe
HS		 3010 { "rss", &rss_debugfs_fops, S_IRUSR, 0 },
3011 { "rss_config", &rss_config_debugfs_fops, S_IRUSR, 0 },
3012 { "rss_key", &rss_key_debugfs_fops, S_IRUSR, 0 },
3013 { "rss_pf_config", &rss_pf_config_debugfs_fops, S_IRUSR, 0 },
3014 { "rss_vf_config", &rss_vf_config_debugfs_fops, S_IRUSR, 0 },
dc9daab2 3015 { "sge_qinfo", &sge_qinfo_debugfs_fops, S_IRUSR, 0 },
e5f0e43b
HS		 3016 { "ibq_tp0", &cim_ibq_fops, S_IRUSR, 0 },
3017 { "ibq_tp1", &cim_ibq_fops, S_IRUSR, 1 },
3018 { "ibq_ulp", &cim_ibq_fops, S_IRUSR, 2 },
3019 { "ibq_sge0", &cim_ibq_fops, S_IRUSR, 3 },
3020 { "ibq_sge1", &cim_ibq_fops, S_IRUSR, 4 },
3021 { "ibq_ncsi", &cim_ibq_fops, S_IRUSR, 5 },
c778af7d
HS		 3022 { "obq_ulp0", &cim_obq_fops, S_IRUSR, 0 },
3023 { "obq_ulp1", &cim_obq_fops, S_IRUSR, 1 },
3024 { "obq_ulp2", &cim_obq_fops, S_IRUSR, 2 },
3025 { "obq_ulp3", &cim_obq_fops, S_IRUSR, 3 },
3026 { "obq_sge", &cim_obq_fops, S_IRUSR, 4 },
3027 { "obq_ncsi", &cim_obq_fops, S_IRUSR, 5 },
2d277b3b 3028 { "tp_la", &tp_la_fops, S_IRUSR, 0 },
797ff0f5 3029 { "ulprx_la", &ulprx_la_fops, S_IRUSR, 0 },
70a5f3bb 3030 { "sensors", &sensors_debugfs_fops, S_IRUSR, 0 },
b3bbe36a 3031 { "pm_stats", &pm_stats_debugfs_fops, S_IRUSR, 0 },
7864026b 3032 { "tx_rate", &tx_rate_debugfs_fops, S_IRUSR, 0 },
bad43792 3033 { "cctrl", &cctrl_tbl_debugfs_fops, S_IRUSR, 0 },
b5a02f50
AB		 3034#if IS_ENABLED(CONFIG_IPV6)
3035 { "clip_tbl", &clip_tbl_debugfs_fops, S_IRUSR, 0 },
3036#endif
a4011fd4 3037 { "tids", &tid_info_debugfs_fops, S_IRUSR, 0},
5b377d11 3038 { "blocked_fl", &blocked_fl_fops, S_IRUSR | S_IWUSR, 0 },
5888111c 3039 { "meminfo", &meminfo_fops, S_IRUSR, 0 },
fd88b31a
HS		 3040 };
3041
c778af7d
HS		 3042 /* Debug FS nodes common to all T5 and later adapters.
3043 */
3044 static struct t4_debugfs_entry t5_debugfs_files[] = {
3045 { "obq_sge_rx_q0", &cim_obq_fops, S_IRUSR, 6 },
3046 { "obq_sge_rx_q1", &cim_obq_fops, S_IRUSR, 7 },
3047 };
3048
fd88b31a
HS		 3049 add_debugfs_files(adap,
3050 t4_debugfs_files,
3051 ARRAY_SIZE(t4_debugfs_files));
c778af7d
HS		 3052 if (!is_t4(adap->params.chip))
3053 add_debugfs_files(adap,
3054 t5_debugfs_files,
3055 ARRAY_SIZE(t5_debugfs_files));
fd88b31a 3056
6559a7e8
HS		 3057 i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
3058 if (i & EDRAM0_ENABLE_F) {
3059 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
3060 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM0_SIZE_G(size));
fd88b31a 3061 }
6559a7e8
HS		 3062 if (i & EDRAM1_ENABLE_F) {
3063 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
3064 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size));
fd88b31a 3065 }
3ccc6cf7 3066 if (is_t5(adap->params.chip)) {
6559a7e8
HS		 3067 if (i & EXT_MEM0_ENABLE_F) {
3068 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
fd88b31a 3069 add_debugfs_mem(adap, "mc0", MEM_MC0,
6559a7e8 3070 EXT_MEM0_SIZE_G(size));
fd88b31a 3071 }
6559a7e8
HS		 3072 if (i & EXT_MEM1_ENABLE_F) {
3073 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
fd88b31a 3074 add_debugfs_mem(adap, "mc1", MEM_MC1,
6559a7e8 3075 EXT_MEM1_SIZE_G(size));
fd88b31a 3076 }
3ccc6cf7 3077 } else {
21a44763 3078 if (i & EXT_MEM_ENABLE_F) {
3ccc6cf7
HS		 3079 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
3080 add_debugfs_mem(adap, "mc", MEM_MC,
3081 EXT_MEM_SIZE_G(size));
21a44763 3082 }
fd88b31a 3083 }
49216c1c 3084
c1d81b1c
DH		 3085 de = debugfs_create_file_size("flash", S_IRUSR, adap->debugfs_root, adap,
3086 &flash_debugfs_fops, adap->params.sf_size);
0b2c2a93
HS		 3087 debugfs_create_bool("use_backdoor", S_IWUSR | S_IRUSR,
3088 adap->debugfs_root, &adap->use_bd);
8e3d04fd
HS		 3089 debugfs_create_bool("trace_rss", S_IWUSR | S_IRUSR,
3090 adap->debugfs_root, &adap->trace_rss);
49216c1c 3091
fd88b31a
HS		 3092 return 0;
3093}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git