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[thirdparty/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
b72a32da 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
1ef8019b 64#include <net/bonding.h>
7c0f6ba6 65#include <linux/uaccess.h>
c5a8c0f3 66#include <linux/crash_dump.h>
846eac3f 67#include <net/udp_tunnel.h>
b8ff05a9
DM		 68
69#include "cxgb4.h"
d57fd6ca 70#include "cxgb4_filter.h"
b8ff05a9 71#include "t4_regs.h"
f612b815 72#include "t4_values.h"
b8ff05a9
DM		 73#include "t4_msg.h"
74#include "t4fw_api.h"
cd6c2f12 75#include "t4fw_version.h"
688848b1 76#include "cxgb4_dcb.h"
c68644ef 77#include "srq.h"
fd88b31a 78#include "cxgb4_debugfs.h"
b5a02f50 79#include "clip_tbl.h"
b8ff05a9 80#include "l2t.h"
3bdb376e 81#include "smt.h"
b72a32da 82#include "sched.h"
d8931847 83#include "cxgb4_tc_u32.h"
6a345b3d 84#include "cxgb4_tc_flower.h"
a4569504 85#include "cxgb4_ptp.h"
ad75b7d3 86#include "cxgb4_cudbg.h"
b8ff05a9 87
812034f1
HS		 88char cxgb4_driver_name[] = KBUILD_MODNAME;
89
01bcca68
VP		 90#ifdef DRV_VERSION
91#undef DRV_VERSION
92#endif
3a7f8554 93#define DRV_VERSION "2.0.0-ko"
812034f1 94const char cxgb4_driver_version[] = DRV_VERSION;
52a5f846 95#define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
b8ff05a9 96
b8ff05a9
DM		 97#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
98 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
99 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
100
3fedeab1
HS		 101/* Macros needed to support the PCI Device ID Table ...
102 */
103#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
768ffc66 104 static const struct pci_device_id cxgb4_pci_tbl[] = {
baf50868
GG		 105#define CXGB4_UNIFIED_PF 0x4
106
107#define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
b8ff05a9 108
3fedeab1
HS		 109/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
110 * called for both.
111 */
112#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
113
114#define CH_PCI_ID_TABLE_ENTRY(devid) \
baf50868 115 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
3fedeab1
HS		 116
117#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
118 { 0, } \
119 }
120
121#include "t4_pci_id_tbl.h"
b8ff05a9 122
16e47624 123#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 124#define FW5_FNAME "cxgb4/t5fw.bin"
3ccc6cf7 125#define FW6_FNAME "cxgb4/t6fw.bin"
16e47624 126#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 127#define FW5_CFNAME "cxgb4/t5-config.txt"
3ccc6cf7 128#define FW6_CFNAME "cxgb4/t6-config.txt"
01b69614
HS		 129#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
130#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
131#define PHY_AQ1202_DEVICEID 0x4409
132#define PHY_BCM84834_DEVICEID 0x4486
b8ff05a9
DM		 133
134MODULE_DESCRIPTION(DRV_DESC);
135MODULE_AUTHOR("Chelsio Communications");
136MODULE_LICENSE("Dual BSD/GPL");
137MODULE_VERSION(DRV_VERSION);
138MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 139MODULE_FIRMWARE(FW4_FNAME);
0a57a536 140MODULE_FIRMWARE(FW5_FNAME);
52a5f846 141MODULE_FIRMWARE(FW6_FNAME);
b8ff05a9 142
b8ff05a9
DM		 143/*
144 * The driver uses the best interrupt scheme available on a platform in the
145 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
146 * of these schemes the driver may consider as follows:
147 *
148 * msi = 2: choose from among all three options
149 * msi = 1: only consider MSI and INTx interrupts
150 * msi = 0: force INTx interrupts
151 */
152static int msi = 2;
153
154module_param(msi, int, 0644);
155MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
156
636f9d37
VP		 157/*
158 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
159 * offset by 2 bytes in order to have the IP headers line up on 4-byte
160 * boundaries. This is a requirement for many architectures which will throw
161 * a machine check fault if an attempt is made to access one of the 4-byte IP
162 * header fields on a non-4-byte boundary. And it's a major performance issue
163 * even on some architectures which allow it like some implementations of the
164 * x86 ISA. However, some architectures don't mind this and for some very
165 * edge-case performance sensitive applications (like forwarding large volumes
166 * of small packets), setting this DMA offset to 0 will decrease the number of
167 * PCI-E Bus transfers enough to measurably affect performance.
168 */
169static int rx_dma_offset = 2;
170
688848b1
AB		 171/* TX Queue select used to determine what algorithm to use for selecting TX
172 * queue. Select between the kernel provided function (select_queue=0) or user
173 * cxgb_select_queue function (select_queue=1)
174 *
175 * Default: select_queue=0
176 */
177static int select_queue;
178module_param(select_queue, int, 0644);
179MODULE_PARM_DESC(select_queue,
180 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
181
b8ff05a9
DM		 182static struct dentry *cxgb4_debugfs_root;
183
94cdb8bb
HS		 184LIST_HEAD(adapter_list);
185DEFINE_MUTEX(uld_mutex);
b8ff05a9
DM		 186
187static void link_report(struct net_device *dev)
188{
189 if (!netif_carrier_ok(dev))
190 netdev_info(dev, "link down\n");
191 else {
192 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
193
85412255 194 const char *s;
b8ff05a9
DM		 195 const struct port_info *p = netdev_priv(dev);
196
197 switch (p->link_cfg.speed) {
5e78f7fd
GG		 198 case 100:
199 s = "100Mbps";
b8ff05a9 200 break;
e8b39015 201 case 1000:
5e78f7fd 202 s = "1Gbps";
b8ff05a9 203 break;
5e78f7fd
GG		 204 case 10000:
205 s = "10Gbps";
206 break;
207 case 25000:
208 s = "25Gbps";
b8ff05a9 209 break;
e8b39015 210 case 40000:
72aca4bf
KS		 211 s = "40Gbps";
212 break;
7cbe543c
GG		 213 case 50000:
214 s = "50Gbps";
215 break;
5e78f7fd
GG		 216 case 100000:
217 s = "100Gbps";
218 break;
85412255
HS		 219 default:
220 pr_info("%s: unsupported speed: %d\n",
221 dev->name, p->link_cfg.speed);
222 return;
b8ff05a9
DM		 223 }
224
225 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
226 fc[p->link_cfg.fc]);
227 }
228}
229
688848b1
AB		 230#ifdef CONFIG_CHELSIO_T4_DCB
231/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
232static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
233{
234 struct port_info *pi = netdev_priv(dev);
235 struct adapter *adap = pi->adapter;
236 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
237 int i;
238
239 /* We use a simple mapping of Port TX Queue Index to DCB
240 * Priority when we're enabling DCB.
241 */
242 for (i = 0; i < pi->nqsets; i++, txq++) {
243 u32 name, value;
244 int err;
245
5167865a
HS		 246 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
247 FW_PARAMS_PARAM_X_V(
248 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
249 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
688848b1
AB		 250 value = enable ? i : 0xffffffff;
251
252 /* Since we can be called while atomic (from "interrupt
253 * level") we need to issue the Set Parameters Commannd
254 * without sleeping (timeout < 0).
255 */
b2612722 256 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
01b69614
HS		 257 &name, &value,
258 -FW_CMD_MAX_TIMEOUT);
688848b1
AB		 259
260 if (err)
261 dev_err(adap->pdev_dev,
262 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
263 enable ? "set" : "unset", pi->port_id, i, -err);
10b00466 264 else
5ce36338 265 txq->dcb_prio = enable ? value : 0;
688848b1
AB		 266 }
267}
688848b1 268
ebddd97a 269int cxgb4_dcb_enabled(const struct net_device *dev)
218d48e7 270{
218d48e7
HS		 271 struct port_info *pi = netdev_priv(dev);
272
273 if (!pi->dcb.enabled)
274 return 0;
275
276 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
277 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
218d48e7 278}
7c70c4f8 279#endif /* CONFIG_CHELSIO_T4_DCB */
218d48e7 280
b8ff05a9
DM		 281void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
282{
283 struct net_device *dev = adapter->port[port_id];
284
285 /* Skip changes from disabled ports. */
286 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
287 if (link_stat)
288 netif_carrier_on(dev);
688848b1
AB		 289 else {
290#ifdef CONFIG_CHELSIO_T4_DCB
218d48e7 291 if (cxgb4_dcb_enabled(dev)) {
ba581f77 292 cxgb4_dcb_reset(dev);
218d48e7
HS		 293 dcb_tx_queue_prio_enable(dev, false);
294 }
688848b1 295#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 296 netif_carrier_off(dev);
688848b1 297 }
b8ff05a9
DM		 298
299 link_report(dev);
300 }
301}
302
8156b0ba 303void t4_os_portmod_changed(struct adapter *adap, int port_id)
b8ff05a9
DM		 304{
305 static const char *mod_str[] = {
a0881cab 306 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 307 };
308
8156b0ba
GG		 309 struct net_device *dev = adap->port[port_id];
310 struct port_info *pi = netdev_priv(dev);
b8ff05a9
DM		 311
312 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
313 netdev_info(dev, "port module unplugged\n");
a0881cab 314 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9 315 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
be81a2de
HS		 316 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
317 netdev_info(dev, "%s: unsupported port module inserted\n",
318 dev->name);
319 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
320 netdev_info(dev, "%s: unknown port module inserted\n",
321 dev->name);
322 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
323 netdev_info(dev, "%s: transceiver module error\n", dev->name);
324 else
325 netdev_info(dev, "%s: unknown module type %d inserted\n",
326 dev->name, pi->mod_type);
8156b0ba
GG		 327
328 /* If the interface is running, then we'll need any "sticky" Link
329 * Parameters redone with a new Transceiver Module.
330 */
331 pi->link_cfg.redo_l1cfg = netif_running(dev);
b8ff05a9
DM		 332}
333
fc08a01a
HS		 334int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
335module_param(dbfifo_int_thresh, int, 0644);
336MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
337
b8ff05a9 338/*
fc08a01a 339 * usecs to sleep while draining the dbfifo
b8ff05a9 340 */
fc08a01a
HS		 341static int dbfifo_drain_delay = 1000;
342module_param(dbfifo_drain_delay, int, 0644);
343MODULE_PARM_DESC(dbfifo_drain_delay,
344 "usecs to sleep while draining the dbfifo");
345
346static inline int cxgb4_set_addr_hash(struct port_info *pi)
b8ff05a9 347{
fc08a01a
HS		 348 struct adapter *adap = pi->adapter;
349 u64 vec = 0;
350 bool ucast = false;
351 struct hash_mac_addr *entry;
352
353 /* Calculate the hash vector for the updated list and program it */
354 list_for_each_entry(entry, &adap->mac_hlist, list) {
355 ucast |= is_unicast_ether_addr(entry->addr);
356 vec |= (1ULL << hash_mac_addr(entry->addr));
357 }
358 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
359 vec, false);
360}
361
362static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
363{
364 struct port_info *pi = netdev_priv(netdev);
365 struct adapter *adap = pi->adapter;
366 int ret;
b8ff05a9
DM		 367 u64 mhash = 0;
368 u64 uhash = 0;
fc08a01a
HS		 369 bool free = false;
370 bool ucast = is_unicast_ether_addr(mac_addr);
371 const u8 *maclist[1] = {mac_addr};
372 struct hash_mac_addr *new_entry;
373
374 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
375 NULL, ucast ? &uhash : &mhash, false);
376 if (ret < 0)
377 goto out;
378 /* if hash != 0, then add the addr to hash addr list
379 * so on the end we will calculate the hash for the
380 * list and program it
381 */
382 if (uhash || mhash) {
383 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
384 if (!new_entry)
385 return -ENOMEM;
386 ether_addr_copy(new_entry->addr, mac_addr);
387 list_add_tail(&new_entry->list, &adap->mac_hlist);
388 ret = cxgb4_set_addr_hash(pi);
b8ff05a9 389 }
fc08a01a
HS		 390out:
391 return ret < 0 ? ret : 0;
392}
b8ff05a9 393
fc08a01a
HS		 394static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
395{
396 struct port_info *pi = netdev_priv(netdev);
397 struct adapter *adap = pi->adapter;
398 int ret;
399 const u8 *maclist[1] = {mac_addr};
400 struct hash_mac_addr *entry, *tmp;
b8ff05a9 401
fc08a01a
HS		 402 /* If the MAC address to be removed is in the hash addr
403 * list, delete it from the list and update hash vector
404 */
405 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
406 if (ether_addr_equal(entry->addr, mac_addr)) {
407 list_del(&entry->list);
408 kfree(entry);
409 return cxgb4_set_addr_hash(pi);
b8ff05a9
DM		 410 }
411 }
412
fc08a01a
HS		 413 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
414 return ret < 0 ? -EINVAL : 0;
b8ff05a9
DM		 415}
416
417/*
418 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
419 * If @mtu is -1 it is left unchanged.
420 */
421static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
422{
b8ff05a9 423 struct port_info *pi = netdev_priv(dev);
fc08a01a 424 struct adapter *adapter = pi->adapter;
b8ff05a9 425
d01f7abc
HS		 426 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
427 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
fc08a01a
HS		 428
429 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
430 (dev->flags & IFF_PROMISC) ? 1 : 0,
431 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
432 sleep_ok);
b8ff05a9
DM		 433}
434
435/**
436 * link_start - enable a port
437 * @dev: the port to enable
438 *
439 * Performs the MAC and PHY actions needed to enable a port.
440 */
441static int link_start(struct net_device *dev)
442{
443 int ret;
444 struct port_info *pi = netdev_priv(dev);
b2612722 445 unsigned int mb = pi->adapter->pf;
b8ff05a9
DM		 446
447 /*
448 * We do not set address filters and promiscuity here, the stack does
449 * that step explicitly.
450 */
060e0c75 451 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 452 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 453 if (ret == 0) {
060e0c75 454 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 455 pi->xact_addr_filt, dev->dev_addr, true,
02d805dc 456 &pi->smt_idx);
b8ff05a9
DM		 457 if (ret >= 0) {
458 pi->xact_addr_filt = ret;
459 ret = 0;
460 }
461 }
462 if (ret == 0)
4036da90 463 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
060e0c75 464 &pi->link_cfg);
30f00847
AB		 465 if (ret == 0) {
466 local_bh_disable();
e2f4f4e9 467 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
688848b1 468 true, CXGB4_DCB_ENABLED);
30f00847
AB		 469 local_bh_enable();
470 }
688848b1 471
b8ff05a9
DM		 472 return ret;
473}
474
688848b1
AB		 475#ifdef CONFIG_CHELSIO_T4_DCB
476/* Handle a Data Center Bridging update message from the firmware. */
477static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
478{
2b5fb1f2 479 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
134491fd 480 struct net_device *dev = adap->port[adap->chan_map[port]];
688848b1
AB		 481 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
482 int new_dcb_enabled;
483
484 cxgb4_dcb_handle_fw_update(adap, pcmd);
485 new_dcb_enabled = cxgb4_dcb_enabled(dev);
486
487 /* If the DCB has become enabled or disabled on the port then we're
488 * going to need to set up/tear down DCB Priority parameters for the
489 * TX Queues associated with the port.
490 */
491 if (new_dcb_enabled != old_dcb_enabled)
492 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
493}
494#endif /* CONFIG_CHELSIO_T4_DCB */
495
f2b7e78d 496/* Response queue handler for the FW event queue.
b8ff05a9
DM		 497 */
498static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
499 const struct pkt_gl *gl)
500{
501 u8 opcode = ((const struct rss_header *)rsp)->opcode;
502
503 rsp++; /* skip RSS header */
b407a4a9
VP		 504
505 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
506 */
507 if (unlikely(opcode == CPL_FW4_MSG &&
508 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
509 rsp++;
510 opcode = ((const struct rss_header *)rsp)->opcode;
511 rsp++;
512 if (opcode != CPL_SGE_EGR_UPDATE) {
513 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
514 , opcode);
515 goto out;
516 }
517 }
518
b8ff05a9
DM		 519 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
520 const struct cpl_sge_egr_update *p = (void *)rsp;
bdc590b9 521 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
e46dab4d 522 struct sge_txq *txq;
b8ff05a9 523
e46dab4d 524 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 525 txq->restarts++;
ab677ff4 526 if (txq->q_type == CXGB4_TXQ_ETH) {
b8ff05a9
DM		 527 struct sge_eth_txq *eq;
528
529 eq = container_of(txq, struct sge_eth_txq, q);
530 netif_tx_wake_queue(eq->txq);
531 } else {
ab677ff4 532 struct sge_uld_txq *oq;
b8ff05a9 533
ab677ff4 534 oq = container_of(txq, struct sge_uld_txq, q);
b8ff05a9
DM		 535 tasklet_schedule(&oq->qresume_tsk);
536 }
537 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
538 const struct cpl_fw6_msg *p = (void *)rsp;
539
688848b1
AB		 540#ifdef CONFIG_CHELSIO_T4_DCB
541 const struct fw_port_cmd *pcmd = (const void *)p->data;
e2ac9628 542 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
688848b1 543 unsigned int action =
2b5fb1f2 544 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
688848b1
AB		 545
546 if (cmd == FW_PORT_CMD &&
c3168cab
GG		 547 (action == FW_PORT_ACTION_GET_PORT_INFO ||
548 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
2b5fb1f2 549 int port = FW_PORT_CMD_PORTID_G(
688848b1 550 be32_to_cpu(pcmd->op_to_portid));
c3168cab
GG		 551 struct net_device *dev;
552 int dcbxdis, state_input;
553
554 dev = q->adap->port[q->adap->chan_map[port]];
555 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
90d4c5bb
GG		 556 ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
557 : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
558 & FW_PORT_CMD_DCBXDIS32_F));
c3168cab
GG		 559 state_input = (dcbxdis
560 ? CXGB4_DCB_INPUT_FW_DISABLED
561 : CXGB4_DCB_INPUT_FW_ENABLED);
688848b1
AB		 562
563 cxgb4_dcb_state_fsm(dev, state_input);
564 }
565
566 if (cmd == FW_PORT_CMD &&
567 action == FW_PORT_ACTION_L2_DCB_CFG)
568 dcb_rpl(q->adap, pcmd);
569 else
570#endif
571 if (p->type == 0)
572 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 573 } else if (opcode == CPL_L2T_WRITE_RPL) {
574 const struct cpl_l2t_write_rpl *p = (void *)rsp;
575
576 do_l2t_write_rpl(q->adap, p);
3bdb376e
KS		 577 } else if (opcode == CPL_SMT_WRITE_RPL) {
578 const struct cpl_smt_write_rpl *p = (void *)rsp;
579
580 do_smt_write_rpl(q->adap, p);
f2b7e78d
VP		 581 } else if (opcode == CPL_SET_TCB_RPL) {
582 const struct cpl_set_tcb_rpl *p = (void *)rsp;
583
584 filter_rpl(q->adap, p);
12b276fb
KS		 585 } else if (opcode == CPL_ACT_OPEN_RPL) {
586 const struct cpl_act_open_rpl *p = (void *)rsp;
587
588 hash_filter_rpl(q->adap, p);
3b0b3bee
KS		 589 } else if (opcode == CPL_ABORT_RPL_RSS) {
590 const struct cpl_abort_rpl_rss *p = (void *)rsp;
591
592 hash_del_filter_rpl(q->adap, p);
c68644ef
RR		 593 } else if (opcode == CPL_SRQ_TABLE_RPL) {
594 const struct cpl_srq_table_rpl *p = (void *)rsp;
595
596 do_srq_table_rpl(q->adap, p);
b8ff05a9
DM		 597 } else
598 dev_err(q->adap->pdev_dev,
599 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 600out:
b8ff05a9
DM		 601 return 0;
602}
603
b8ff05a9
DM		 604static void disable_msi(struct adapter *adapter)
605{
606 if (adapter->flags & USING_MSIX) {
607 pci_disable_msix(adapter->pdev);
608 adapter->flags &= ~USING_MSIX;
609 } else if (adapter->flags & USING_MSI) {
610 pci_disable_msi(adapter->pdev);
611 adapter->flags &= ~USING_MSI;
612 }
613}
614
615/*
616 * Interrupt handler for non-data events used with MSI-X.
617 */
618static irqreturn_t t4_nondata_intr(int irq, void *cookie)
619{
620 struct adapter *adap = cookie;
0d804338 621 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
b8ff05a9 622
0d804338 623 if (v & PFSW_F) {
b8ff05a9 624 adap->swintr = 1;
0d804338 625 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
b8ff05a9 626 }
c3c7b121
HS		 627 if (adap->flags & MASTER_PF)
628 t4_slow_intr_handler(adap);
b8ff05a9
DM		 629 return IRQ_HANDLED;
630}
631
632/*
633 * Name the MSI-X interrupts.
634 */
635static void name_msix_vecs(struct adapter *adap)
636{
ba27816c 637 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 638
639 /* non-data interrupts */
b1a3c2b6 640 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 641
642 /* FW events */
b1a3c2b6
DM		 643 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
644 adap->port[0]->name);
b8ff05a9
DM		 645
646 /* Ethernet queues */
647 for_each_port(adap, j) {
648 struct net_device *d = adap->port[j];
649 const struct port_info *pi = netdev_priv(d);
650
ba27816c 651 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 652 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
653 d->name, i);
b8ff05a9 654 }
b8ff05a9
DM		 655}
656
657static int request_msix_queue_irqs(struct adapter *adap)
658{
659 struct sge *s = &adap->sge;
0fbc81b3 660 int err, ethqidx;
cf38be6d 661 int msi_index = 2;
b8ff05a9
DM		 662
663 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
664 adap->msix_info[1].desc, &s->fw_evtq);
665 if (err)
666 return err;
667
668 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP		 669 err = request_irq(adap->msix_info[msi_index].vec,
670 t4_sge_intr_msix, 0,
671 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 672 &s->ethrxq[ethqidx].rspq);
673 if (err)
674 goto unwind;
404d9e3f 675 msi_index++;
b8ff05a9 676 }
b8ff05a9
DM		 677 return 0;
678
679unwind:
b8ff05a9 680 while (--ethqidx >= 0)
404d9e3f
VP		 681 free_irq(adap->msix_info[--msi_index].vec,
682 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM		 683 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
684 return err;
685}
686
687static void free_msix_queue_irqs(struct adapter *adap)
688{
404d9e3f 689 int i, msi_index = 2;
b8ff05a9
DM		 690 struct sge *s = &adap->sge;
691
692 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
693 for_each_ethrxq(s, i)
404d9e3f 694 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
b8ff05a9
DM		 695}
696
671b0060 697/**
812034f1 698 * cxgb4_write_rss - write the RSS table for a given port
671b0060
DM		 699 * @pi: the port
700 * @queues: array of queue indices for RSS
701 *
702 * Sets up the portion of the HW RSS table for the port's VI to distribute
703 * packets to the Rx queues in @queues.
c035e183 704 * Should never be called before setting up sge eth rx queues
671b0060 705 */
812034f1 706int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
671b0060
DM		 707{
708 u16 *rss;
709 int i, err;
c035e183
HS		 710 struct adapter *adapter = pi->adapter;
711 const struct sge_eth_rxq *rxq;
671b0060 712
c035e183 713 rxq = &adapter->sge.ethrxq[pi->first_qset];
6da2ec56 714 rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
671b0060
DM		 715 if (!rss)
716 return -ENOMEM;
717
718 /* map the queue indices to queue ids */
719 for (i = 0; i < pi->rss_size; i++, queues++)
c035e183 720 rss[i] = rxq[*queues].rspq.abs_id;
671b0060 721
b2612722 722 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
060e0c75 723 pi->rss_size, rss, pi->rss_size);
c035e183
HS		 724 /* If Tunnel All Lookup isn't specified in the global RSS
725 * Configuration, then we need to specify a default Ingress
726 * Queue for any ingress packets which aren't hashed. We'll
727 * use our first ingress queue ...
728 */
729 if (!err)
730 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
731 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
732 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
733 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
734 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
735 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
736 rss[0]);
671b0060
DM		 737 kfree(rss);
738 return err;
739}
740
b8ff05a9
DM		 741/**
742 * setup_rss - configure RSS
743 * @adap: the adapter
744 *
671b0060 745 * Sets up RSS for each port.
b8ff05a9
DM		 746 */
747static int setup_rss(struct adapter *adap)
748{
c035e183 749 int i, j, err;
b8ff05a9
DM		 750
751 for_each_port(adap, i) {
752 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 753
c035e183
HS		 754 /* Fill default values with equal distribution */
755 for (j = 0; j < pi->rss_size; j++)
756 pi->rss[j] = j % pi->nqsets;
757
812034f1 758 err = cxgb4_write_rss(pi, pi->rss);
b8ff05a9
DM		 759 if (err)
760 return err;
761 }
762 return 0;
763}
764
e46dab4d
DM		 765/*
766 * Return the channel of the ingress queue with the given qid.
767 */
768static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
769{
770 qid -= p->ingr_start;
771 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
772}
773
b8ff05a9
DM		 774/*
775 * Wait until all NAPI handlers are descheduled.
776 */
777static void quiesce_rx(struct adapter *adap)
778{
779 int i;
780
4b8e27a8 781 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 782 struct sge_rspq *q = adap->sge.ingr_map[i];
783
5226b791 784 if (q && q->handler)
b8ff05a9
DM		 785 napi_disable(&q->napi);
786 }
787}
788
b37987e8
HS		 789/* Disable interrupt and napi handler */
790static void disable_interrupts(struct adapter *adap)
791{
792 if (adap->flags & FULL_INIT_DONE) {
793 t4_intr_disable(adap);
794 if (adap->flags & USING_MSIX) {
795 free_msix_queue_irqs(adap);
796 free_irq(adap->msix_info[0].vec, adap);
797 } else {
798 free_irq(adap->pdev->irq, adap);
799 }
800 quiesce_rx(adap);
801 }
802}
803
b8ff05a9
DM		 804/*
805 * Enable NAPI scheduling and interrupt generation for all Rx queues.
806 */
807static void enable_rx(struct adapter *adap)
808{
809 int i;
810
4b8e27a8 811 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 812 struct sge_rspq *q = adap->sge.ingr_map[i];
813
814 if (!q)
815 continue;
5226b791 816 if (q->handler)
b8ff05a9 817 napi_enable(&q->napi);
5226b791 818
b8ff05a9 819 /* 0-increment GTS to start the timer and enable interrupts */
f612b815
HS		 820 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
821 SEINTARM_V(q->intr_params) |
822 INGRESSQID_V(q->cntxt_id));
b8ff05a9
DM		 823 }
824}
825
1c6a5b0e 826
0fbc81b3 827static int setup_fw_sge_queues(struct adapter *adap)
b8ff05a9 828{
b8ff05a9 829 struct sge *s = &adap->sge;
0fbc81b3 830 int err = 0;
b8ff05a9 831
4b8e27a8
HS		 832 bitmap_zero(s->starving_fl, s->egr_sz);
833 bitmap_zero(s->txq_maperr, s->egr_sz);
b8ff05a9
DM		 834
835 if (adap->flags & USING_MSIX)
94cdb8bb 836 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */
b8ff05a9
DM		 837 else {
838 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
2337ba42 839 NULL, NULL, NULL, -1);
b8ff05a9
DM		 840 if (err)
841 return err;
94cdb8bb 842 adap->msi_idx = -((int)s->intrq.abs_id + 1);
b8ff05a9
DM		 843 }
844
845 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
94cdb8bb 846 adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
0fbc81b3
HS		 847 return err;
848}
849
850/**
851 * setup_sge_queues - configure SGE Tx/Rx/response queues
852 * @adap: the adapter
853 *
854 * Determines how many sets of SGE queues to use and initializes them.
855 * We support multiple queue sets per port if we have MSI-X, otherwise
856 * just one queue set per port.
857 */
858static int setup_sge_queues(struct adapter *adap)
859{
860 int err, i, j;
861 struct sge *s = &adap->sge;
d427caee 862 struct sge_uld_rxq_info *rxq_info = NULL;
0fbc81b3 863 unsigned int cmplqid = 0;
b8ff05a9 864
d427caee
GG		 865 if (is_uld(adap))
866 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
867
b8ff05a9
DM		 868 for_each_port(adap, i) {
869 struct net_device *dev = adap->port[i];
870 struct port_info *pi = netdev_priv(dev);
871 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
872 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
873
874 for (j = 0; j < pi->nqsets; j++, q++) {
94cdb8bb
HS		 875 if (adap->msi_idx > 0)
876 adap->msi_idx++;
b8ff05a9 877 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
94cdb8bb 878 adap->msi_idx, &q->fl,
145ef8a5 879 t4_ethrx_handler,
2337ba42 880 NULL,
193c4c28
AV		 881 t4_get_tp_ch_map(adap,
882 pi->tx_chan));
b8ff05a9
DM		 883 if (err)
884 goto freeout;
885 q->rspq.idx = j;
886 memset(&q->stats, 0, sizeof(q->stats));
887 }
888 for (j = 0; j < pi->nqsets; j++, t++) {
889 err = t4_sge_alloc_eth_txq(adap, t, dev,
890 netdev_get_tx_queue(dev, j),
891 s->fw_evtq.cntxt_id);
892 if (err)
893 goto freeout;
894 }
895 }
896
b8ff05a9 897 for_each_port(adap, i) {
0fbc81b3 898 /* Note that cmplqid below is 0 if we don't
b8ff05a9
DM		 899 * have RDMA queues, and that's the right value.
900 */
0fbc81b3
HS		 901 if (rxq_info)
902 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
903
b8ff05a9 904 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
0fbc81b3 905 s->fw_evtq.cntxt_id, cmplqid);
b8ff05a9
DM		 906 if (err)
907 goto freeout;
908 }
909
a4569504
AG		 910 if (!is_t4(adap->params.chip)) {
911 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
912 netdev_get_tx_queue(adap->port[0], 0)
913 , s->fw_evtq.cntxt_id);
914 if (err)
915 goto freeout;
916 }
917
9bb59b96 918 t4_write_reg(adap, is_t4(adap->params.chip) ?
837e4a42
HS		 919 MPS_TRC_RSS_CONTROL_A :
920 MPS_T5_TRC_RSS_CONTROL_A,
921 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
922 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
b8ff05a9 923 return 0;
0fbc81b3 924freeout:
0eaec62a 925 dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
0fbc81b3
HS		 926 t4_free_sge_resources(adap);
927 return err;
b8ff05a9
DM		 928}
929
688848b1 930static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
4f49dec9
AD		 931 struct net_device *sb_dev,
932 select_queue_fallback_t fallback)
688848b1
AB		 933{
934 int txq;
935
936#ifdef CONFIG_CHELSIO_T4_DCB
937 /* If a Data Center Bridging has been successfully negotiated on this
938 * link then we'll use the skb's priority to map it to a TX Queue.
939 * The skb's priority is determined via the VLAN Tag Priority Code
940 * Point field.
941 */
85eacf3f 942 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
688848b1
AB		 943 u16 vlan_tci;
944 int err;
945
946 err = vlan_get_tag(skb, &vlan_tci);
947 if (unlikely(err)) {
948 if (net_ratelimit())
949 netdev_warn(dev,
950 "TX Packet without VLAN Tag on DCB Link\n");
951 txq = 0;
952 } else {
953 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
84a200b3
VP		 954#ifdef CONFIG_CHELSIO_T4_FCOE
955 if (skb->protocol == htons(ETH_P_FCOE))
956 txq = skb->priority & 0x7;
957#endif /* CONFIG_CHELSIO_T4_FCOE */
688848b1
AB		 958 }
959 return txq;
960 }
961#endif /* CONFIG_CHELSIO_T4_DCB */
962
963 if (select_queue) {
964 txq = (skb_rx_queue_recorded(skb)
965 ? skb_get_rx_queue(skb)
966 : smp_processor_id());
967
968 while (unlikely(txq >= dev->real_num_tx_queues))
969 txq -= dev->real_num_tx_queues;
970
971 return txq;
972 }
973
8ec56fc3 974 return fallback(dev, skb, NULL) % dev->real_num_tx_queues;
688848b1
AB		 975}
976
b8ff05a9
DM		 977static int closest_timer(const struct sge *s, int time)
978{
979 int i, delta, match = 0, min_delta = INT_MAX;
980
981 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
982 delta = time - s->timer_val[i];
983 if (delta < 0)
984 delta = -delta;
985 if (delta < min_delta) {
986 min_delta = delta;
987 match = i;
988 }
989 }
990 return match;
991}
992
993static int closest_thres(const struct sge *s, int thres)
994{
995 int i, delta, match = 0, min_delta = INT_MAX;
996
997 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
998 delta = thres - s->counter_val[i];
999 if (delta < 0)
1000 delta = -delta;
1001 if (delta < min_delta) {
1002 min_delta = delta;
1003 match = i;
1004 }
1005 }
1006 return match;
1007}
1008
b8ff05a9 1009/**
812034f1 1010 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 1011 * @q: the Rx queue
1012 * @us: the hold-off time in us, or 0 to disable timer
1013 * @cnt: the hold-off packet count, or 0 to disable counter
1014 *
1015 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1016 * one of the two needs to be enabled for the queue to generate interrupts.
1017 */
812034f1
HS		 1018int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1019 unsigned int us, unsigned int cnt)
b8ff05a9 1020{
c887ad0e
HS		 1021 struct adapter *adap = q->adap;
1022
b8ff05a9
DM		 1023 if ((us | cnt) == 0)
1024 cnt = 1;
1025
1026 if (cnt) {
1027 int err;
1028 u32 v, new_idx;
1029
1030 new_idx = closest_thres(&adap->sge, cnt);
1031 if (q->desc && q->pktcnt_idx != new_idx) {
1032 /* the queue has already been created, update it */
5167865a
HS		 1033 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1034 FW_PARAMS_PARAM_X_V(
1035 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1036 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
b2612722
HS		 1037 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1038 &v, &new_idx);
b8ff05a9
DM		 1039 if (err)
1040 return err;
1041 }
1042 q->pktcnt_idx = new_idx;
1043 }
1044
1045 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1ecc7b7a 1046 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
b8ff05a9
DM		 1047 return 0;
1048}
1049
c8f44aff 1050static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 1051{
2ed28baa 1052 const struct port_info *pi = netdev_priv(dev);
c8f44aff 1053 netdev_features_t changed = dev->features ^ features;
19ecae2c 1054 int err;
19ecae2c 1055
f646968f 1056 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 1057 return 0;
19ecae2c 1058
b2612722 1059 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
2ed28baa 1060 -1, -1, -1,
f646968f 1061 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 1062 if (unlikely(err))
f646968f 1063 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 1064 return err;
87b6cf51
DM		 1065}
1066
91744948 1067static int setup_debugfs(struct adapter *adap)
b8ff05a9 1068{
b8ff05a9
DM		 1069 if (IS_ERR_OR_NULL(adap->debugfs_root))
1070 return -1;
1071
fd88b31a
HS		 1072#ifdef CONFIG_DEBUG_FS
1073 t4_setup_debugfs(adap);
1074#endif
b8ff05a9
DM		 1075 return 0;
1076}
1077
1078/*
1079 * upper-layer driver support
1080 */
1081
1082/*
1083 * Allocate an active-open TID and set it to the supplied value.
1084 */
1085int cxgb4_alloc_atid(struct tid_info *t, void *data)
1086{
1087 int atid = -1;
1088
1089 spin_lock_bh(&t->atid_lock);
1090 if (t->afree) {
1091 union aopen_entry *p = t->afree;
1092
f2b7e78d 1093 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 1094 t->afree = p->next;
1095 p->data = data;
1096 t->atids_in_use++;
1097 }
1098 spin_unlock_bh(&t->atid_lock);
1099 return atid;
1100}
1101EXPORT_SYMBOL(cxgb4_alloc_atid);
1102
1103/*
1104 * Release an active-open TID.
1105 */
1106void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1107{
f2b7e78d 1108 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 1109
1110 spin_lock_bh(&t->atid_lock);
1111 p->next = t->afree;
1112 t->afree = p;
1113 t->atids_in_use--;
1114 spin_unlock_bh(&t->atid_lock);
1115}
1116EXPORT_SYMBOL(cxgb4_free_atid);
1117
1118/*
1119 * Allocate a server TID and set it to the supplied value.
1120 */
1121int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1122{
1123 int stid;
1124
1125 spin_lock_bh(&t->stid_lock);
1126 if (family == PF_INET) {
1127 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1128 if (stid < t->nstids)
1129 __set_bit(stid, t->stid_bmap);
1130 else
1131 stid = -1;
1132 } else {
a99c683e 1133 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
b8ff05a9
DM		 1134 if (stid < 0)
1135 stid = -1;
1136 }
1137 if (stid >= 0) {
1138 t->stid_tab[stid].data = data;
1139 stid += t->stid_base;
15f63b74
KS		 1140 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1141 * This is equivalent to 4 TIDs. With CLIP enabled it
1142 * needs 2 TIDs.
1143 */
1dec4cec 1144 if (family == PF_INET6) {
a99c683e 1145 t->stids_in_use += 2;
1dec4cec
GG		 1146 t->v6_stids_in_use += 2;
1147 } else {
1148 t->stids_in_use++;
1149 }
b8ff05a9
DM		 1150 }
1151 spin_unlock_bh(&t->stid_lock);
1152 return stid;
1153}
1154EXPORT_SYMBOL(cxgb4_alloc_stid);
1155
dca4faeb
VP		 1156/* Allocate a server filter TID and set it to the supplied value.
1157 */
1158int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1159{
1160 int stid;
1161
1162 spin_lock_bh(&t->stid_lock);
1163 if (family == PF_INET) {
1164 stid = find_next_zero_bit(t->stid_bmap,
1165 t->nstids + t->nsftids, t->nstids);
1166 if (stid < (t->nstids + t->nsftids))
1167 __set_bit(stid, t->stid_bmap);
1168 else
1169 stid = -1;
1170 } else {
1171 stid = -1;
1172 }
1173 if (stid >= 0) {
1174 t->stid_tab[stid].data = data;
470c60c4
KS		 1175 stid -= t->nstids;
1176 stid += t->sftid_base;
2248b293 1177 t->sftids_in_use++;
dca4faeb
VP		 1178 }
1179 spin_unlock_bh(&t->stid_lock);
1180 return stid;
1181}
1182EXPORT_SYMBOL(cxgb4_alloc_sftid);
1183
1184/* Release a server TID.
b8ff05a9
DM		 1185 */
1186void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1187{
470c60c4
KS		 1188 /* Is it a server filter TID? */
1189 if (t->nsftids && (stid >= t->sftid_base)) {
1190 stid -= t->sftid_base;
1191 stid += t->nstids;
1192 } else {
1193 stid -= t->stid_base;
1194 }
1195
b8ff05a9
DM		 1196 spin_lock_bh(&t->stid_lock);
1197 if (family == PF_INET)
1198 __clear_bit(stid, t->stid_bmap);
1199 else
a99c683e 1200 bitmap_release_region(t->stid_bmap, stid, 1);
b8ff05a9 1201 t->stid_tab[stid].data = NULL;
2248b293 1202 if (stid < t->nstids) {
1dec4cec 1203 if (family == PF_INET6) {
a99c683e 1204 t->stids_in_use -= 2;
1dec4cec
GG		 1205 t->v6_stids_in_use -= 2;
1206 } else {
1207 t->stids_in_use--;
1208 }
2248b293
HS		 1209 } else {
1210 t->sftids_in_use--;
1211 }
1dec4cec 1212
b8ff05a9
DM		 1213 spin_unlock_bh(&t->stid_lock);
1214}
1215EXPORT_SYMBOL(cxgb4_free_stid);
1216
1217/*
1218 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1219 */
1220static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1221 unsigned int tid)
1222{
1223 struct cpl_tid_release *req;
1224
1225 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
4df864c1 1226 req = __skb_put(skb, sizeof(*req));
b8ff05a9
DM		 1227 INIT_TP_WR(req, tid);
1228 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1229}
1230
1231/*
1232 * Queue a TID release request and if necessary schedule a work queue to
1233 * process it.
1234 */
31b9c19b 1235static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1236 unsigned int tid)
b8ff05a9
DM		 1237{
1238 void **p = &t->tid_tab[tid];
1239 struct adapter *adap = container_of(t, struct adapter, tids);
1240
1241 spin_lock_bh(&adap->tid_release_lock);
1242 *p = adap->tid_release_head;
1243 /* Low 2 bits encode the Tx channel number */
1244 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1245 if (!adap->tid_release_task_busy) {
1246 adap->tid_release_task_busy = true;
29aaee65 1247 queue_work(adap->workq, &adap->tid_release_task);
b8ff05a9
DM		 1248 }
1249 spin_unlock_bh(&adap->tid_release_lock);
1250}
b8ff05a9
DM		 1251
1252/*
1253 * Process the list of pending TID release requests.
1254 */
1255static void process_tid_release_list(struct work_struct *work)
1256{
1257 struct sk_buff *skb;
1258 struct adapter *adap;
1259
1260 adap = container_of(work, struct adapter, tid_release_task);
1261
1262 spin_lock_bh(&adap->tid_release_lock);
1263 while (adap->tid_release_head) {
1264 void **p = adap->tid_release_head;
1265 unsigned int chan = (uintptr_t)p & 3;
1266 p = (void *)p - chan;
1267
1268 adap->tid_release_head = *p;
1269 *p = NULL;
1270 spin_unlock_bh(&adap->tid_release_lock);
1271
1272 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1273 GFP_KERNEL)))
1274 schedule_timeout_uninterruptible(1);
1275
1276 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1277 t4_ofld_send(adap, skb);
1278 spin_lock_bh(&adap->tid_release_lock);
1279 }
1280 adap->tid_release_task_busy = false;
1281 spin_unlock_bh(&adap->tid_release_lock);
1282}
1283
1284/*
1285 * Release a TID and inform HW. If we are unable to allocate the release
1286 * message we defer to a work queue.
1287 */
1dec4cec
GG		 1288void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1289 unsigned short family)
b8ff05a9 1290{
b8ff05a9
DM		 1291 struct sk_buff *skb;
1292 struct adapter *adap = container_of(t, struct adapter, tids);
1293
9a1bb9f6
HS		 1294 WARN_ON(tid >= t->ntids);
1295
1296 if (t->tid_tab[tid]) {
1297 t->tid_tab[tid] = NULL;
1dec4cec
GG		 1298 atomic_dec(&t->conns_in_use);
1299 if (t->hash_base && (tid >= t->hash_base)) {
1300 if (family == AF_INET6)
1301 atomic_sub(2, &t->hash_tids_in_use);
1302 else
1303 atomic_dec(&t->hash_tids_in_use);
1304 } else {
1305 if (family == AF_INET6)
1306 atomic_sub(2, &t->tids_in_use);
1307 else
1308 atomic_dec(&t->tids_in_use);
1309 }
9a1bb9f6
HS		 1310 }
1311
b8ff05a9
DM		 1312 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1313 if (likely(skb)) {
b8ff05a9
DM		 1314 mk_tid_release(skb, chan, tid);
1315 t4_ofld_send(adap, skb);
1316 } else
1317 cxgb4_queue_tid_release(t, chan, tid);
b8ff05a9
DM		 1318}
1319EXPORT_SYMBOL(cxgb4_remove_tid);
1320
1321/*
1322 * Allocate and initialize the TID tables. Returns 0 on success.
1323 */
1324static int tid_init(struct tid_info *t)
1325{
b6f8eaec 1326 struct adapter *adap = container_of(t, struct adapter, tids);
578b46b9
RL		 1327 unsigned int max_ftids = t->nftids + t->nsftids;
1328 unsigned int natids = t->natids;
1329 unsigned int stid_bmap_size;
1330 unsigned int ftid_bmap_size;
1331 size_t size;
b8ff05a9 1332
dca4faeb 1333 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
578b46b9 1334 ftid_bmap_size = BITS_TO_LONGS(t->nftids);
f2b7e78d
VP		 1335 size = t->ntids * sizeof(*t->tid_tab) +
1336 natids * sizeof(*t->atid_tab) +
b8ff05a9 1337 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 1338 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 1339 stid_bmap_size * sizeof(long) +
578b46b9
RL		 1340 max_ftids * sizeof(*t->ftid_tab) +
1341 ftid_bmap_size * sizeof(long);
f2b7e78d 1342
752ade68 1343 t->tid_tab = kvzalloc(size, GFP_KERNEL);
b8ff05a9
DM		 1344 if (!t->tid_tab)
1345 return -ENOMEM;
1346
1347 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1348 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 1349 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 1350 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
578b46b9 1351 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
b8ff05a9
DM		 1352 spin_lock_init(&t->stid_lock);
1353 spin_lock_init(&t->atid_lock);
578b46b9 1354 spin_lock_init(&t->ftid_lock);
b8ff05a9
DM		 1355
1356 t->stids_in_use = 0;
1dec4cec 1357 t->v6_stids_in_use = 0;
2248b293 1358 t->sftids_in_use = 0;
b8ff05a9
DM		 1359 t->afree = NULL;
1360 t->atids_in_use = 0;
1361 atomic_set(&t->tids_in_use, 0);
1dec4cec 1362 atomic_set(&t->conns_in_use, 0);
9a1bb9f6 1363 atomic_set(&t->hash_tids_in_use, 0);
b8ff05a9
DM		 1364
1365 /* Setup the free list for atid_tab and clear the stid bitmap. */
1366 if (natids) {
1367 while (--natids)
1368 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1369 t->afree = t->atid_tab;
1370 }
b6f8eaec 1371
578b46b9
RL		 1372 if (is_offload(adap)) {
1373 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1374 /* Reserve stid 0 for T4/T5 adapters */
1375 if (!t->stid_base &&
1376 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1377 __set_bit(0, t->stid_bmap);
1378 }
1379
1380 bitmap_zero(t->ftid_bmap, t->nftids);
b8ff05a9
DM		 1381 return 0;
1382}
1383
1384/**
1385 * cxgb4_create_server - create an IP server
1386 * @dev: the device
1387 * @stid: the server TID
1388 * @sip: local IP address to bind server to
1389 * @sport: the server's TCP port
1390 * @queue: queue to direct messages from this server to
1391 *
1392 * Create an IP server for the given port and address.
1393 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1394 */
1395int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 1396 __be32 sip, __be16 sport, __be16 vlan,
1397 unsigned int queue)
b8ff05a9
DM		 1398{
1399 unsigned int chan;
1400 struct sk_buff *skb;
1401 struct adapter *adap;
1402 struct cpl_pass_open_req *req;
80f40c1f 1403 int ret;
b8ff05a9
DM		 1404
1405 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1406 if (!skb)
1407 return -ENOMEM;
1408
1409 adap = netdev2adap(dev);
4df864c1 1410 req = __skb_put(skb, sizeof(*req));
b8ff05a9
DM		 1411 INIT_TP_WR(req, 0);
1412 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1413 req->local_port = sport;
1414 req->peer_port = htons(0);
1415 req->local_ip = sip;
1416 req->peer_ip = htonl(0);
e46dab4d 1417 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1418 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1419 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1420 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1421 ret = t4_mgmt_tx(adap, skb);
1422 return net_xmit_eval(ret);
b8ff05a9
DM		 1423}
1424EXPORT_SYMBOL(cxgb4_create_server);
1425
80f40c1f
VP		 1426/* cxgb4_create_server6 - create an IPv6 server
1427 * @dev: the device
1428 * @stid: the server TID
1429 * @sip: local IPv6 address to bind server to
1430 * @sport: the server's TCP port
1431 * @queue: queue to direct messages from this server to
1432 *
1433 * Create an IPv6 server for the given port and address.
1434 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1435 */
1436int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1437 const struct in6_addr *sip, __be16 sport,
1438 unsigned int queue)
1439{
1440 unsigned int chan;
1441 struct sk_buff *skb;
1442 struct adapter *adap;
1443 struct cpl_pass_open_req6 *req;
1444 int ret;
1445
1446 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1447 if (!skb)
1448 return -ENOMEM;
1449
1450 adap = netdev2adap(dev);
4df864c1 1451 req = __skb_put(skb, sizeof(*req));
80f40c1f
VP		 1452 INIT_TP_WR(req, 0);
1453 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1454 req->local_port = sport;
1455 req->peer_port = htons(0);
1456 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1457 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1458 req->peer_ip_hi = cpu_to_be64(0);
1459 req->peer_ip_lo = cpu_to_be64(0);
1460 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1461 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1462 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1463 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1464 ret = t4_mgmt_tx(adap, skb);
1465 return net_xmit_eval(ret);
1466}
1467EXPORT_SYMBOL(cxgb4_create_server6);
1468
1469int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1470 unsigned int queue, bool ipv6)
1471{
1472 struct sk_buff *skb;
1473 struct adapter *adap;
1474 struct cpl_close_listsvr_req *req;
1475 int ret;
1476
1477 adap = netdev2adap(dev);
1478
1479 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1480 if (!skb)
1481 return -ENOMEM;
1482
4df864c1 1483 req = __skb_put(skb, sizeof(*req));
80f40c1f
VP		 1484 INIT_TP_WR(req, 0);
1485 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
bdc590b9
HS		 1486 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1487 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
80f40c1f
VP		 1488 ret = t4_mgmt_tx(adap, skb);
1489 return net_xmit_eval(ret);
1490}
1491EXPORT_SYMBOL(cxgb4_remove_server);
1492
b8ff05a9
DM		 1493/**
1494 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1495 * @mtus: the HW MTU table
1496 * @mtu: the target MTU
1497 * @idx: index of selected entry in the MTU table
1498 *
1499 * Returns the index and the value in the HW MTU table that is closest to
1500 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1501 * table, in which case that smallest available value is selected.
1502 */
1503unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1504 unsigned int *idx)
1505{
1506 unsigned int i = 0;
1507
1508 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1509 ++i;
1510 if (idx)
1511 *idx = i;
1512 return mtus[i];
1513}
1514EXPORT_SYMBOL(cxgb4_best_mtu);
1515
92e7ae71
HS		 1516/**
1517 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1518 * @mtus: the HW MTU table
1519 * @header_size: Header Size
1520 * @data_size_max: maximum Data Segment Size
1521 * @data_size_align: desired Data Segment Size Alignment (2^N)
1522 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1523 *
1524 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1525 * MTU Table based solely on a Maximum MTU parameter, we break that
1526 * parameter up into a Header Size and Maximum Data Segment Size, and
1527 * provide a desired Data Segment Size Alignment. If we find an MTU in
1528 * the Hardware MTU Table which will result in a Data Segment Size with
1529 * the requested alignment _and_ that MTU isn't "too far" from the
1530 * closest MTU, then we'll return that rather than the closest MTU.
1531 */
1532unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1533 unsigned short header_size,
1534 unsigned short data_size_max,
1535 unsigned short data_size_align,
1536 unsigned int *mtu_idxp)
1537{
1538 unsigned short max_mtu = header_size + data_size_max;
1539 unsigned short data_size_align_mask = data_size_align - 1;
1540 int mtu_idx, aligned_mtu_idx;
1541
1542 /* Scan the MTU Table till we find an MTU which is larger than our
1543 * Maximum MTU or we reach the end of the table. Along the way,
1544 * record the last MTU found, if any, which will result in a Data
1545 * Segment Length matching the requested alignment.
1546 */
1547 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1548 unsigned short data_size = mtus[mtu_idx] - header_size;
1549
1550 /* If this MTU minus the Header Size would result in a
1551 * Data Segment Size of the desired alignment, remember it.
1552 */
1553 if ((data_size & data_size_align_mask) == 0)
1554 aligned_mtu_idx = mtu_idx;
1555
1556 /* If we're not at the end of the Hardware MTU Table and the
1557 * next element is larger than our Maximum MTU, drop out of
1558 * the loop.
1559 */
1560 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1561 break;
1562 }
1563
1564 /* If we fell out of the loop because we ran to the end of the table,
1565 * then we just have to use the last [largest] entry.
1566 */
1567 if (mtu_idx == NMTUS)
1568 mtu_idx--;
1569
1570 /* If we found an MTU which resulted in the requested Data Segment
1571 * Length alignment and that's "not far" from the largest MTU which is
1572 * less than or equal to the maximum MTU, then use that.
1573 */
1574 if (aligned_mtu_idx >= 0 &&
1575 mtu_idx - aligned_mtu_idx <= 1)
1576 mtu_idx = aligned_mtu_idx;
1577
1578 /* If the caller has passed in an MTU Index pointer, pass the
1579 * MTU Index back. Return the MTU value.
1580 */
1581 if (mtu_idxp)
1582 *mtu_idxp = mtu_idx;
1583 return mtus[mtu_idx];
1584}
1585EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1586
b8ff05a9
DM		 1587/**
1588 * cxgb4_port_chan - get the HW channel of a port
1589 * @dev: the net device for the port
1590 *
1591 * Return the HW Tx channel of the given port.
1592 */
1593unsigned int cxgb4_port_chan(const struct net_device *dev)
1594{
1595 return netdev2pinfo(dev)->tx_chan;
1596}
1597EXPORT_SYMBOL(cxgb4_port_chan);
1598
881806bc
VP		 1599unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1600{
1601 struct adapter *adap = netdev2adap(dev);
2cc301d2 1602 u32 v1, v2, lp_count, hp_count;
881806bc 1603
f061de42
HS		 1604 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1605 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1606 if (is_t4(adap->params.chip)) {
f061de42
HS		 1607 lp_count = LP_COUNT_G(v1);
1608 hp_count = HP_COUNT_G(v1);
2cc301d2 1609 } else {
f061de42
HS		 1610 lp_count = LP_COUNT_T5_G(v1);
1611 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1612 }
1613 return lpfifo ? lp_count : hp_count;
881806bc
VP		 1614}
1615EXPORT_SYMBOL(cxgb4_dbfifo_count);
1616
b8ff05a9
DM		 1617/**
1618 * cxgb4_port_viid - get the VI id of a port
1619 * @dev: the net device for the port
1620 *
1621 * Return the VI id of the given port.
1622 */
1623unsigned int cxgb4_port_viid(const struct net_device *dev)
1624{
1625 return netdev2pinfo(dev)->viid;
1626}
1627EXPORT_SYMBOL(cxgb4_port_viid);
1628
1629/**
1630 * cxgb4_port_idx - get the index of a port
1631 * @dev: the net device for the port
1632 *
1633 * Return the index of the given port.
1634 */
1635unsigned int cxgb4_port_idx(const struct net_device *dev)
1636{
1637 return netdev2pinfo(dev)->port_id;
1638}
1639EXPORT_SYMBOL(cxgb4_port_idx);
1640
b8ff05a9
DM		 1641void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1642 struct tp_tcp_stats *v6)
1643{
1644 struct adapter *adap = pci_get_drvdata(pdev);
1645
1646 spin_lock(&adap->stats_lock);
5ccf9d04 1647 t4_tp_get_tcp_stats(adap, v4, v6, false);
b8ff05a9
DM		 1648 spin_unlock(&adap->stats_lock);
1649}
1650EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1651
1652void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1653 const unsigned int *pgsz_order)
1654{
1655 struct adapter *adap = netdev2adap(dev);
1656
0d804338
HS		 1657 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1658 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1659 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1660 HPZ3_V(pgsz_order[3]));
b8ff05a9
DM		 1661}
1662EXPORT_SYMBOL(cxgb4_iscsi_init);
1663
3069ee9b
VP		 1664int cxgb4_flush_eq_cache(struct net_device *dev)
1665{
1666 struct adapter *adap = netdev2adap(dev);
3069ee9b 1667
736c3b94 1668 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
3069ee9b
VP		 1669}
1670EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1671
1672static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1673{
f061de42 1674 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
3069ee9b
VP		 1675 __be64 indices;
1676 int ret;
1677
fc5ab020
HS		 1678 spin_lock(&adap->win0_lock);
1679 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1680 sizeof(indices), (__be32 *)&indices,
1681 T4_MEMORY_READ);
1682 spin_unlock(&adap->win0_lock);
3069ee9b 1683 if (!ret) {
404d9e3f
VP		 1684 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1685 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 1686 }
1687 return ret;
1688}
1689
1690int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1691 u16 size)
1692{
1693 struct adapter *adap = netdev2adap(dev);
1694 u16 hw_pidx, hw_cidx;
1695 int ret;
1696
1697 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1698 if (ret)
1699 goto out;
1700
1701 if (pidx != hw_pidx) {
1702 u16 delta;
f612b815 1703 u32 val;
3069ee9b
VP		 1704
1705 if (pidx >= hw_pidx)
1706 delta = pidx - hw_pidx;
1707 else
1708 delta = size - hw_pidx + pidx;
f612b815
HS		 1709
1710 if (is_t4(adap->params.chip))
1711 val = PIDX_V(delta);
1712 else
1713 val = PIDX_T5_V(delta);
3069ee9b 1714 wmb();
f612b815
HS		 1715 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1716 QID_V(qid) | val);
3069ee9b
VP		 1717 }
1718out:
1719 return ret;
1720}
1721EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1722
031cf476
HS		 1723int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1724{
6559a7e8 1725 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
031cf476 1726 u32 edc0_end, edc1_end, mc0_end, mc1_end;
8b4e6b3c
AV		 1727 u32 offset, memtype, memaddr;
1728 struct adapter *adap;
1729 u32 hma_size = 0;
031cf476
HS		 1730 int ret;
1731
1732 adap = netdev2adap(dev);
1733
1734 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1735
1736 /* Figure out where the offset lands in the Memory Type/Address scheme.
1737 * This code assumes that the memory is laid out starting at offset 0
1738 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1739 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
1740 * MC0, and some have both MC0 and MC1.
1741 */
6559a7e8
HS		 1742 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1743 edc0_size = EDRAM0_SIZE_G(size) << 20;
1744 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1745 edc1_size = EDRAM1_SIZE_G(size) << 20;
1746 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1747 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
031cf476 1748
8b4e6b3c
AV		 1749 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1750 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1751 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1752 }
031cf476
HS		 1753 edc0_end = edc0_size;
1754 edc1_end = edc0_end + edc1_size;
1755 mc0_end = edc1_end + mc0_size;
1756
1757 if (offset < edc0_end) {
1758 memtype = MEM_EDC0;
1759 memaddr = offset;
1760 } else if (offset < edc1_end) {
1761 memtype = MEM_EDC1;
1762 memaddr = offset - edc0_end;
1763 } else {
8b4e6b3c
AV		 1764 if (hma_size && (offset < (edc1_end + hma_size))) {
1765 memtype = MEM_HMA;
1766 memaddr = offset - edc1_end;
1767 } else if (offset < mc0_end) {
031cf476
HS		 1768 memtype = MEM_MC0;
1769 memaddr = offset - edc1_end;
3ccc6cf7 1770 } else if (is_t5(adap->params.chip)) {
6559a7e8
HS		 1771 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1772 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
031cf476
HS		 1773 mc1_end = mc0_end + mc1_size;
1774 if (offset < mc1_end) {
1775 memtype = MEM_MC1;
1776 memaddr = offset - mc0_end;
1777 } else {
1778 /* offset beyond the end of any memory */
1779 goto err;
1780 }
3ccc6cf7
HS		 1781 } else {
1782 /* T4/T6 only has a single memory channel */
1783 goto err;
031cf476
HS		 1784 }
1785 }
1786
1787 spin_lock(&adap->win0_lock);
1788 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1789 spin_unlock(&adap->win0_lock);
1790 return ret;
1791
1792err:
1793 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1794 stag, offset);
1795 return -EINVAL;
1796}
1797EXPORT_SYMBOL(cxgb4_read_tpte);
1798
7730b4c7
HS		 1799u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1800{
1801 u32 hi, lo;
1802 struct adapter *adap;
1803
1804 adap = netdev2adap(dev);
f612b815
HS		 1805 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1806 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
7730b4c7
HS		 1807
1808 return ((u64)hi << 32) | (u64)lo;
1809}
1810EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1811
df64e4d3
HS		 1812int cxgb4_bar2_sge_qregs(struct net_device *dev,
1813 unsigned int qid,
1814 enum cxgb4_bar2_qtype qtype,
66cf188e 1815 int user,
df64e4d3
HS		 1816 u64 *pbar2_qoffset,
1817 unsigned int *pbar2_qid)
1818{
b2612722 1819 return t4_bar2_sge_qregs(netdev2adap(dev),
df64e4d3
HS		 1820 qid,
1821 (qtype == CXGB4_BAR2_QTYPE_EGRESS
1822 ? T4_BAR2_QTYPE_EGRESS
1823 : T4_BAR2_QTYPE_INGRESS),
66cf188e 1824 user,
df64e4d3
HS		 1825 pbar2_qoffset,
1826 pbar2_qid);
1827}
1828EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1829
b8ff05a9
DM		 1830static struct pci_driver cxgb4_driver;
1831
1832static void check_neigh_update(struct neighbour *neigh)
1833{
1834 const struct device *parent;
1835 const struct net_device *netdev = neigh->dev;
1836
d0d7b10b 1837 if (is_vlan_dev(netdev))
b8ff05a9
DM		 1838 netdev = vlan_dev_real_dev(netdev);
1839 parent = netdev->dev.parent;
1840 if (parent && parent->driver == &cxgb4_driver.driver)
1841 t4_l2t_update(dev_get_drvdata(parent), neigh);
1842}
1843
1844static int netevent_cb(struct notifier_block *nb, unsigned long event,
1845 void *data)
1846{
1847 switch (event) {
1848 case NETEVENT_NEIGH_UPDATE:
1849 check_neigh_update(data);
1850 break;
b8ff05a9
DM		 1851 case NETEVENT_REDIRECT:
1852 default:
1853 break;
1854 }
1855 return 0;
1856}
1857
1858static bool netevent_registered;
1859static struct notifier_block cxgb4_netevent_nb = {
1860 .notifier_call = netevent_cb
1861};
1862
3069ee9b
VP		 1863static void drain_db_fifo(struct adapter *adap, int usecs)
1864{
2cc301d2 1865 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 1866
1867 do {
f061de42
HS		 1868 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1869 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1870 if (is_t4(adap->params.chip)) {
f061de42
HS		 1871 lp_count = LP_COUNT_G(v1);
1872 hp_count = HP_COUNT_G(v1);
2cc301d2 1873 } else {
f061de42
HS		 1874 lp_count = LP_COUNT_T5_G(v1);
1875 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1876 }
1877
1878 if (lp_count == 0 && hp_count == 0)
1879 break;
3069ee9b
VP		 1880 set_current_state(TASK_UNINTERRUPTIBLE);
1881 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 1882 } while (1);
1883}
1884
1885static void disable_txq_db(struct sge_txq *q)
1886{
05eb2389
SW		 1887 unsigned long flags;
1888
1889 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 1890 q->db_disabled = 1;
05eb2389 1891 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 1892}
1893
05eb2389 1894static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 1895{
1896 spin_lock_irq(&q->db_lock);
05eb2389
SW		 1897 if (q->db_pidx_inc) {
1898 /* Make sure that all writes to the TX descriptors
1899 * are committed before we tell HW about them.
1900 */
1901 wmb();
f612b815
HS		 1902 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1903 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
05eb2389
SW		 1904 q->db_pidx_inc = 0;
1905 }
3069ee9b
VP		 1906 q->db_disabled = 0;
1907 spin_unlock_irq(&q->db_lock);
1908}
1909
1910static void disable_dbs(struct adapter *adap)
1911{
1912 int i;
1913
1914 for_each_ethrxq(&adap->sge, i)
1915 disable_txq_db(&adap->sge.ethtxq[i].q);
ab677ff4
HS		 1916 if (is_offload(adap)) {
1917 struct sge_uld_txq_info *txq_info =
1918 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1919
1920 if (txq_info) {
1921 for_each_ofldtxq(&adap->sge, i) {
1922 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1923
1924 disable_txq_db(&txq->q);
1925 }
1926 }
1927 }
3069ee9b
VP		 1928 for_each_port(adap, i)
1929 disable_txq_db(&adap->sge.ctrlq[i].q);
1930}
1931
1932static void enable_dbs(struct adapter *adap)
1933{
1934 int i;
1935
1936 for_each_ethrxq(&adap->sge, i)
05eb2389 1937 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
ab677ff4
HS		 1938 if (is_offload(adap)) {
1939 struct sge_uld_txq_info *txq_info =
1940 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1941
1942 if (txq_info) {
1943 for_each_ofldtxq(&adap->sge, i) {
1944 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1945
1946 enable_txq_db(adap, &txq->q);
1947 }
1948 }
1949 }
3069ee9b 1950 for_each_port(adap, i)
05eb2389
SW		 1951 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
1952}
1953
1954static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
1955{
0fbc81b3
HS		 1956 enum cxgb4_uld type = CXGB4_ULD_RDMA;
1957
1958 if (adap->uld && adap->uld[type].handle)
1959 adap->uld[type].control(adap->uld[type].handle, cmd);
05eb2389
SW		 1960}
1961
1962static void process_db_full(struct work_struct *work)
1963{
1964 struct adapter *adap;
1965
1966 adap = container_of(work, struct adapter, db_full_task);
1967
1968 drain_db_fifo(adap, dbfifo_drain_delay);
1969 enable_dbs(adap);
1970 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7
HS		 1971 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1972 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1973 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
1974 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
1975 else
1976 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1977 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
3069ee9b
VP		 1978}
1979
1980static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
1981{
1982 u16 hw_pidx, hw_cidx;
1983 int ret;
1984
05eb2389 1985 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 1986 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
1987 if (ret)
1988 goto out;
1989 if (q->db_pidx != hw_pidx) {
1990 u16 delta;
f612b815 1991 u32 val;
3069ee9b
VP		 1992
1993 if (q->db_pidx >= hw_pidx)
1994 delta = q->db_pidx - hw_pidx;
1995 else
1996 delta = q->size - hw_pidx + q->db_pidx;
f612b815
HS		 1997
1998 if (is_t4(adap->params.chip))
1999 val = PIDX_V(delta);
2000 else
2001 val = PIDX_T5_V(delta);
3069ee9b 2002 wmb();
f612b815
HS		 2003 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2004 QID_V(q->cntxt_id) | val);
3069ee9b
VP		 2005 }
2006out:
2007 q->db_disabled = 0;
05eb2389
SW		 2008 q->db_pidx_inc = 0;
2009 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 2010 if (ret)
2011 CH_WARN(adap, "DB drop recovery failed.\n");
2012}
0fbc81b3 2013
3069ee9b
VP		 2014static void recover_all_queues(struct adapter *adap)
2015{
2016 int i;
2017
2018 for_each_ethrxq(&adap->sge, i)
2019 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
ab677ff4
HS		 2020 if (is_offload(adap)) {
2021 struct sge_uld_txq_info *txq_info =
2022 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2023 if (txq_info) {
2024 for_each_ofldtxq(&adap->sge, i) {
2025 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2026
2027 sync_txq_pidx(adap, &txq->q);
2028 }
2029 }
2030 }
3069ee9b
VP		 2031 for_each_port(adap, i)
2032 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2033}
2034
881806bc
VP		 2035static void process_db_drop(struct work_struct *work)
2036{
2037 struct adapter *adap;
881806bc 2038
3069ee9b 2039 adap = container_of(work, struct adapter, db_drop_task);
881806bc 2040
d14807dd 2041 if (is_t4(adap->params.chip)) {
05eb2389 2042 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2043 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 2044 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2045 recover_all_queues(adap);
05eb2389 2046 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2047 enable_dbs(adap);
05eb2389 2048 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7 2049 } else if (is_t5(adap->params.chip)) {
2cc301d2
SR		 2050 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2051 u16 qid = (dropped_db >> 15) & 0x1ffff;
2052 u16 pidx_inc = dropped_db & 0x1fff;
df64e4d3
HS		 2053 u64 bar2_qoffset;
2054 unsigned int bar2_qid;
2055 int ret;
2cc301d2 2056
b2612722 2057 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
e0456717 2058 0, &bar2_qoffset, &bar2_qid);
df64e4d3
HS		 2059 if (ret)
2060 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2061 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2062 else
f612b815 2063 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
df64e4d3 2064 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2cc301d2
SR		 2065
2066 /* Re-enable BAR2 WC */
2067 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2068 }
2069
3ccc6cf7
HS		 2070 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2071 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
881806bc
VP		 2072}
2073
2074void t4_db_full(struct adapter *adap)
2075{
d14807dd 2076 if (is_t4(adap->params.chip)) {
05eb2389
SW		 2077 disable_dbs(adap);
2078 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
f612b815
HS		 2079 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2080 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
29aaee65 2081 queue_work(adap->workq, &adap->db_full_task);
2cc301d2 2082 }
881806bc
VP		 2083}
2084
2085void t4_db_dropped(struct adapter *adap)
2086{
05eb2389
SW		 2087 if (is_t4(adap->params.chip)) {
2088 disable_dbs(adap);
2089 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2090 }
29aaee65 2091 queue_work(adap->workq, &adap->db_drop_task);
881806bc
VP		 2092}
2093
0fbc81b3
HS		 2094void t4_register_netevent_notifier(void)
2095{
b8ff05a9
DM		 2096 if (!netevent_registered) {
2097 register_netevent_notifier(&cxgb4_netevent_nb);
2098 netevent_registered = true;
2099 }
b8ff05a9
DM		 2100}
2101
2102static void detach_ulds(struct adapter *adap)
2103{
2104 unsigned int i;
2105
2106 mutex_lock(&uld_mutex);
2107 list_del(&adap->list_node);
6a146f3a 2108
b8ff05a9 2109 for (i = 0; i < CXGB4_ULD_MAX; i++)
6a146f3a 2110 if (adap->uld && adap->uld[i].handle)
94cdb8bb
HS		 2111 adap->uld[i].state_change(adap->uld[i].handle,
2112 CXGB4_STATE_DETACH);
6a146f3a 2113
b8ff05a9
DM		 2114 if (netevent_registered && list_empty(&adapter_list)) {
2115 unregister_netevent_notifier(&cxgb4_netevent_nb);
2116 netevent_registered = false;
2117 }
2118 mutex_unlock(&uld_mutex);
2119}
2120
2121static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2122{
2123 unsigned int i;
2124
2125 mutex_lock(&uld_mutex);
2126 for (i = 0; i < CXGB4_ULD_MAX; i++)
94cdb8bb
HS		 2127 if (adap->uld && adap->uld[i].handle)
2128 adap->uld[i].state_change(adap->uld[i].handle,
2129 new_state);
b8ff05a9
DM		 2130 mutex_unlock(&uld_mutex);
2131}
2132
1bb60376 2133#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 2134static int cxgb4_inet6addr_handler(struct notifier_block *this,
2135 unsigned long event, void *data)
01bcca68 2136{
b5a02f50
AB		 2137 struct inet6_ifaddr *ifa = data;
2138 struct net_device *event_dev = ifa->idev->dev;
2139 const struct device *parent = NULL;
2140#if IS_ENABLED(CONFIG_BONDING)
01bcca68 2141 struct adapter *adap;
b5a02f50 2142#endif
d0d7b10b 2143 if (is_vlan_dev(event_dev))
b5a02f50
AB		 2144 event_dev = vlan_dev_real_dev(event_dev);
2145#if IS_ENABLED(CONFIG_BONDING)
2146 if (event_dev->flags & IFF_MASTER) {
2147 list_for_each_entry(adap, &adapter_list, list_node) {
2148 switch (event) {
2149 case NETDEV_UP:
2150 cxgb4_clip_get(adap->port[0],
2151 (const u32 *)ifa, 1);
2152 break;
2153 case NETDEV_DOWN:
2154 cxgb4_clip_release(adap->port[0],
2155 (const u32 *)ifa, 1);
2156 break;
2157 default:
2158 break;
2159 }
2160 }
2161 return NOTIFY_OK;
2162 }
2163#endif
01bcca68 2164
b5a02f50
AB		 2165 if (event_dev)
2166 parent = event_dev->dev.parent;
01bcca68 2167
b5a02f50 2168 if (parent && parent->driver == &cxgb4_driver.driver) {
01bcca68
VP		 2169 switch (event) {
2170 case NETDEV_UP:
b5a02f50 2171 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2172 break;
2173 case NETDEV_DOWN:
b5a02f50 2174 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2175 break;
2176 default:
2177 break;
2178 }
2179 }
b5a02f50 2180 return NOTIFY_OK;
01bcca68
VP		 2181}
2182
b5a02f50 2183static bool inet6addr_registered;
01bcca68
VP		 2184static struct notifier_block cxgb4_inet6addr_notifier = {
2185 .notifier_call = cxgb4_inet6addr_handler
2186};
2187
01bcca68
VP		 2188static void update_clip(const struct adapter *adap)
2189{
2190 int i;
2191 struct net_device *dev;
2192 int ret;
2193
2194 rcu_read_lock();
2195
2196 for (i = 0; i < MAX_NPORTS; i++) {
2197 dev = adap->port[i];
2198 ret = 0;
2199
2200 if (dev)
b5a02f50 2201 ret = cxgb4_update_root_dev_clip(dev);
01bcca68
VP		 2202
2203 if (ret < 0)
2204 break;
2205 }
2206 rcu_read_unlock();
2207}
1bb60376 2208#endif /* IS_ENABLED(CONFIG_IPV6) */
01bcca68 2209
b8ff05a9
DM		 2210/**
2211 * cxgb_up - enable the adapter
2212 * @adap: adapter being enabled
2213 *
2214 * Called when the first port is enabled, this function performs the
2215 * actions necessary to make an adapter operational, such as completing
2216 * the initialization of HW modules, and enabling interrupts.
2217 *
2218 * Must be called with the rtnl lock held.
2219 */
2220static int cxgb_up(struct adapter *adap)
2221{
aaefae9b 2222 int err;
b8ff05a9 2223
91060381 2224 mutex_lock(&uld_mutex);
aaefae9b
DM		 2225 err = setup_sge_queues(adap);
2226 if (err)
91060381 2227 goto rel_lock;
aaefae9b
DM		 2228 err = setup_rss(adap);
2229 if (err)
2230 goto freeq;
b8ff05a9
DM		 2231
2232 if (adap->flags & USING_MSIX) {
aaefae9b 2233 name_msix_vecs(adap);
b8ff05a9
DM		 2234 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2235 adap->msix_info[0].desc, adap);
2236 if (err)
2237 goto irq_err;
b8ff05a9
DM		 2238 err = request_msix_queue_irqs(adap);
2239 if (err) {
2240 free_irq(adap->msix_info[0].vec, adap);
2241 goto irq_err;
2242 }
2243 } else {
2244 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2245 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 2246 adap->port[0]->name, adap);
b8ff05a9
DM		 2247 if (err)
2248 goto irq_err;
2249 }
e7519f99 2250
b8ff05a9
DM		 2251 enable_rx(adap);
2252 t4_sge_start(adap);
2253 t4_intr_enable(adap);
aaefae9b 2254 adap->flags |= FULL_INIT_DONE;
e7519f99
GG		 2255 mutex_unlock(&uld_mutex);
2256
b8ff05a9 2257 notify_ulds(adap, CXGB4_STATE_UP);
1bb60376 2258#if IS_ENABLED(CONFIG_IPV6)
01bcca68 2259 update_clip(adap);
1bb60376 2260#endif
b8ff05a9 2261 return err;
91060381 2262
b8ff05a9
DM		 2263 irq_err:
2264 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 2265 freeq:
2266 t4_free_sge_resources(adap);
91060381
RR		 2267 rel_lock:
2268 mutex_unlock(&uld_mutex);
2269 return err;
b8ff05a9
DM		 2270}
2271
2272static void cxgb_down(struct adapter *adapter)
2273{
b8ff05a9 2274 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 2275 cancel_work_sync(&adapter->db_full_task);
2276 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 2277 adapter->tid_release_task_busy = false;
204dc3c0 2278 adapter->tid_release_head = NULL;
b8ff05a9 2279
aaefae9b
DM		 2280 t4_sge_stop(adapter);
2281 t4_free_sge_resources(adapter);
2a8d84bf 2282
aaefae9b 2283 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM		 2284}
2285
2286/*
2287 * net_device operations
2288 */
2289static int cxgb_open(struct net_device *dev)
2290{
2291 int err;
2292 struct port_info *pi = netdev_priv(dev);
2293 struct adapter *adapter = pi->adapter;
2294
6a3c869a
DM		 2295 netif_carrier_off(dev);
2296
aaefae9b
DM		 2297 if (!(adapter->flags & FULL_INIT_DONE)) {
2298 err = cxgb_up(adapter);
2299 if (err < 0)
2300 return err;
2301 }
b8ff05a9 2302
2061ec3f
GG		 2303 /* It's possible that the basic port information could have
2304 * changed since we first read it.
2305 */
2306 err = t4_update_port_info(pi);
2307 if (err < 0)
2308 return err;
2309
f68707b8
DM		 2310 err = link_start(dev);
2311 if (!err)
2312 netif_tx_start_all_queues(dev);
2313 return err;
b8ff05a9
DM		 2314}
2315
2316static int cxgb_close(struct net_device *dev)
2317{
b8ff05a9
DM		 2318 struct port_info *pi = netdev_priv(dev);
2319 struct adapter *adapter = pi->adapter;
ba581f77 2320 int ret;
b8ff05a9
DM		 2321
2322 netif_tx_stop_all_queues(dev);
2323 netif_carrier_off(dev);
e2f4f4e9
AV		 2324 ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2325 false, false, false);
ba581f77
GG		 2326#ifdef CONFIG_CHELSIO_T4_DCB
2327 cxgb4_dcb_reset(dev);
2328 dcb_tx_queue_prio_enable(dev, false);
2329#endif
2330 return ret;
b8ff05a9
DM		 2331}
2332
dca4faeb 2333int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 2334 __be32 sip, __be16 sport, __be16 vlan,
2335 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 2336{
2337 int ret;
2338 struct filter_entry *f;
2339 struct adapter *adap;
2340 int i;
2341 u8 *val;
2342
2343 adap = netdev2adap(dev);
2344
1cab775c 2345 /* Adjust stid to correct filter index */
470c60c4 2346 stid -= adap->tids.sftid_base;
1cab775c
VP		 2347 stid += adap->tids.nftids;
2348
dca4faeb
VP		 2349 /* Check to make sure the filter requested is writable ...
2350 */
2351 f = &adap->tids.ftid_tab[stid];
2352 ret = writable_filter(f);
2353 if (ret)
2354 return ret;
2355
2356 /* Clear out any old resources being used by the filter before
2357 * we start constructing the new filter.
2358 */
2359 if (f->valid)
2360 clear_filter(adap, f);
2361
2362 /* Clear out filter specifications */
2363 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2364 f->fs.val.lport = cpu_to_be16(sport);
2365 f->fs.mask.lport = ~0;
2366 val = (u8 *)&sip;
793dad94 2367 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 2368 for (i = 0; i < 4; i++) {
2369 f->fs.val.lip[i] = val[i];
2370 f->fs.mask.lip[i] = ~0;
2371 }
0d804338 2372 if (adap->params.tp.vlan_pri_map & PORT_F) {
793dad94
VP		 2373 f->fs.val.iport = port;
2374 f->fs.mask.iport = mask;
2375 }
2376 }
dca4faeb 2377
0d804338 2378 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
7c89e555
KS		 2379 f->fs.val.proto = IPPROTO_TCP;
2380 f->fs.mask.proto = ~0;
2381 }
2382
dca4faeb
VP		 2383 f->fs.dirsteer = 1;
2384 f->fs.iq = queue;
2385 /* Mark filter as locked */
2386 f->locked = 1;
2387 f->fs.rpttid = 1;
2388
6b254afd
GG		 2389 /* Save the actual tid. We need this to get the corresponding
2390 * filter entry structure in filter_rpl.
2391 */
2392 f->tid = stid + adap->tids.ftid_base;
dca4faeb
VP		 2393 ret = set_filter_wr(adap, stid);
2394 if (ret) {
2395 clear_filter(adap, f);
2396 return ret;
2397 }
2398
2399 return 0;
2400}
2401EXPORT_SYMBOL(cxgb4_create_server_filter);
2402
2403int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2404 unsigned int queue, bool ipv6)
2405{
dca4faeb
VP		 2406 struct filter_entry *f;
2407 struct adapter *adap;
2408
2409 adap = netdev2adap(dev);
1cab775c
VP		 2410
2411 /* Adjust stid to correct filter index */
470c60c4 2412 stid -= adap->tids.sftid_base;
1cab775c
VP		 2413 stid += adap->tids.nftids;
2414
dca4faeb
VP		 2415 f = &adap->tids.ftid_tab[stid];
2416 /* Unlock the filter */
2417 f->locked = 0;
2418
8c14846d 2419 return delete_filter(adap, stid);
dca4faeb
VP		 2420}
2421EXPORT_SYMBOL(cxgb4_remove_server_filter);
2422
bc1f4470 2423static void cxgb_get_stats(struct net_device *dev,
2424 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 2425{
2426 struct port_stats stats;
2427 struct port_info *p = netdev_priv(dev);
2428 struct adapter *adapter = p->adapter;
b8ff05a9 2429
9fe6cb58
GS		 2430 /* Block retrieving statistics during EEH error
2431 * recovery. Otherwise, the recovery might fail
2432 * and the PCI device will be removed permanently
2433 */
b8ff05a9 2434 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 2435 if (!netif_device_present(dev)) {
2436 spin_unlock(&adapter->stats_lock);
bc1f4470 2437 return;
9fe6cb58 2438 }
a4cfd929
HS		 2439 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2440 &p->stats_base);
b8ff05a9
DM		 2441 spin_unlock(&adapter->stats_lock);
2442
2443 ns->tx_bytes = stats.tx_octets;
2444 ns->tx_packets = stats.tx_frames;
2445 ns->rx_bytes = stats.rx_octets;
2446 ns->rx_packets = stats.rx_frames;
2447 ns->multicast = stats.rx_mcast_frames;
2448
2449 /* detailed rx_errors */
2450 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2451 stats.rx_runt;
2452 ns->rx_over_errors = 0;
2453 ns->rx_crc_errors = stats.rx_fcs_err;
2454 ns->rx_frame_errors = stats.rx_symbol_err;
b93f79be 2455 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 +
b8ff05a9
DM		 2456 stats.rx_ovflow2 + stats.rx_ovflow3 +
2457 stats.rx_trunc0 + stats.rx_trunc1 +
2458 stats.rx_trunc2 + stats.rx_trunc3;
2459 ns->rx_missed_errors = 0;
2460
2461 /* detailed tx_errors */
2462 ns->tx_aborted_errors = 0;
2463 ns->tx_carrier_errors = 0;
2464 ns->tx_fifo_errors = 0;
2465 ns->tx_heartbeat_errors = 0;
2466 ns->tx_window_errors = 0;
2467
2468 ns->tx_errors = stats.tx_error_frames;
2469 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2470 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
b8ff05a9
DM		 2471}
2472
2473static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2474{
060e0c75 2475 unsigned int mbox;
b8ff05a9
DM		 2476 int ret = 0, prtad, devad;
2477 struct port_info *pi = netdev_priv(dev);
a4569504 2478 struct adapter *adapter = pi->adapter;
b8ff05a9
DM		 2479 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2480
2481 switch (cmd) {
2482 case SIOCGMIIPHY:
2483 if (pi->mdio_addr < 0)
2484 return -EOPNOTSUPP;
2485 data->phy_id = pi->mdio_addr;
2486 break;
2487 case SIOCGMIIREG:
2488 case SIOCSMIIREG:
2489 if (mdio_phy_id_is_c45(data->phy_id)) {
2490 prtad = mdio_phy_id_prtad(data->phy_id);
2491 devad = mdio_phy_id_devad(data->phy_id);
2492 } else if (data->phy_id < 32) {
2493 prtad = data->phy_id;
2494 devad = 0;
2495 data->reg_num &= 0x1f;
2496 } else
2497 return -EINVAL;
2498
b2612722 2499 mbox = pi->adapter->pf;
b8ff05a9 2500 if (cmd == SIOCGMIIREG)
060e0c75 2501 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2502 data->reg_num, &data->val_out);
2503 else
060e0c75 2504 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2505 data->reg_num, data->val_in);
2506 break;
5e2a5ebc
HS		 2507 case SIOCGHWTSTAMP:
2508 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2509 sizeof(pi->tstamp_config)) ?
2510 -EFAULT : 0;
2511 case SIOCSHWTSTAMP:
2512 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2513 sizeof(pi->tstamp_config)))
2514 return -EFAULT;
2515
a4569504
AG		 2516 if (!is_t4(adapter->params.chip)) {
2517 switch (pi->tstamp_config.tx_type) {
2518 case HWTSTAMP_TX_OFF:
2519 case HWTSTAMP_TX_ON:
2520 break;
2521 default:
2522 return -ERANGE;
2523 }
2524
2525 switch (pi->tstamp_config.rx_filter) {
2526 case HWTSTAMP_FILTER_NONE:
2527 pi->rxtstamp = false;
2528 break;
2529 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2530 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2531 cxgb4_ptprx_timestamping(pi, pi->port_id,
2532 PTP_TS_L4);
2533 break;
2534 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2535 cxgb4_ptprx_timestamping(pi, pi->port_id,
2536 PTP_TS_L2_L4);
2537 break;
2538 case HWTSTAMP_FILTER_ALL:
2539 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2540 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2541 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2542 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2543 pi->rxtstamp = true;
2544 break;
2545 default:
2546 pi->tstamp_config.rx_filter =
2547 HWTSTAMP_FILTER_NONE;
2548 return -ERANGE;
2549 }
2550
2551 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2552 (pi->tstamp_config.rx_filter ==
2553 HWTSTAMP_FILTER_NONE)) {
2554 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2555 pi->ptp_enable = false;
2556 }
2557
2558 if (pi->tstamp_config.rx_filter !=
2559 HWTSTAMP_FILTER_NONE) {
2560 if (cxgb4_ptp_redirect_rx_packet(adapter,
2561 pi) >= 0)
2562 pi->ptp_enable = true;
2563 }
2564 } else {
2565 /* For T4 Adapters */
2566 switch (pi->tstamp_config.rx_filter) {
2567 case HWTSTAMP_FILTER_NONE:
5e2a5ebc
HS		 2568 pi->rxtstamp = false;
2569 break;
a4569504 2570 case HWTSTAMP_FILTER_ALL:
5e2a5ebc
HS		 2571 pi->rxtstamp = true;
2572 break;
a4569504
AG		 2573 default:
2574 pi->tstamp_config.rx_filter =
2575 HWTSTAMP_FILTER_NONE;
5e2a5ebc 2576 return -ERANGE;
a4569504 2577 }
5e2a5ebc 2578 }
5e2a5ebc
HS		 2579 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2580 sizeof(pi->tstamp_config)) ?
2581 -EFAULT : 0;
b8ff05a9
DM		 2582 default:
2583 return -EOPNOTSUPP;
2584 }
2585 return ret;
2586}
2587
2588static void cxgb_set_rxmode(struct net_device *dev)
2589{
2590 /* unfortunately we can't return errors to the stack */
2591 set_rxmode(dev, -1, false);
2592}
2593
2594static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2595{
2596 int ret;
2597 struct port_info *pi = netdev_priv(dev);
2598
b2612722 2599 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
060e0c75 2600 -1, -1, -1, true);
b8ff05a9
DM		 2601 if (!ret)
2602 dev->mtu = new_mtu;
2603 return ret;
2604}
2605
858aa65c 2606#ifdef CONFIG_PCI_IOV
baf50868 2607static int cxgb4_mgmt_open(struct net_device *dev)
e7b48a32
HS		 2608{
2609 /* Turn carrier off since we don't have to transmit anything on this
2610 * interface.
2611 */
2612 netif_carrier_off(dev);
2613 return 0;
2614}
2615
661dbeb9 2616/* Fill MAC address that will be assigned by the FW */
baf50868 2617static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
661dbeb9 2618{
661dbeb9 2619 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
baf50868
GG		 2620 unsigned int i, vf, nvfs;
2621 u16 a, b;
661dbeb9
HS		 2622 int err;
2623 u8 *na;
661dbeb9 2624
baf50868
GG		 2625 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2626 PCI_CAP_ID_VPD);
661dbeb9 2627 err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
baf50868
GG		 2628 if (err)
2629 return;
2630
2631 na = adap->params.vpd.na;
2632 for (i = 0; i < ETH_ALEN; i++)
2633 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2634 hex2val(na[2 * i + 1]));
2635
2636 a = (hw_addr[0] << 8) | hw_addr[1];
2637 b = (hw_addr[1] << 8) | hw_addr[2];
2638 a ^= b;
2639 a |= 0x0200; /* locally assigned Ethernet MAC address */
2640 a &= ~0x0100; /* not a multicast Ethernet MAC address */
2641 macaddr[0] = a >> 8;
2642 macaddr[1] = a & 0xff;
2643
2644 for (i = 2; i < 5; i++)
2645 macaddr[i] = hw_addr[i + 1];
2646
2647 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2648 vf < nvfs; vf++) {
1b974aa4 2649 macaddr[5] = adap->pf * nvfs + vf;
baf50868 2650 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
661dbeb9
HS		 2651 }
2652}
2653
baf50868 2654static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
858aa65c
HS		 2655{
2656 struct port_info *pi = netdev_priv(dev);
2657 struct adapter *adap = pi->adapter;
661dbeb9 2658 int ret;
858aa65c
HS		 2659
2660 /* verify MAC addr is valid */
2661 if (!is_valid_ether_addr(mac)) {
2662 dev_err(pi->adapter->pdev_dev,
2663 "Invalid Ethernet address %pM for VF %d\n",
2664 mac, vf);
2665 return -EINVAL;
2666 }
2667
2668 dev_info(pi->adapter->pdev_dev,
2669 "Setting MAC %pM on VF %d\n", mac, vf);
661dbeb9
HS		 2670 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2671 if (!ret)
2672 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2673 return ret;
2674}
2675
baf50868
GG		 2676static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2677 int vf, struct ifla_vf_info *ivi)
661dbeb9
HS		 2678{
2679 struct port_info *pi = netdev_priv(dev);
2680 struct adapter *adap = pi->adapter;
bd79acee 2681 struct vf_info *vfinfo;
661dbeb9
HS		 2682
2683 if (vf >= adap->num_vfs)
2684 return -EINVAL;
bd79acee
AV		 2685 vfinfo = &adap->vfinfo[vf];
2686
661dbeb9 2687 ivi->vf = vf;
bd79acee 2688 ivi->max_tx_rate = vfinfo->tx_rate;
8ea4fae9 2689 ivi->min_tx_rate = 0;
bd79acee
AV		 2690 ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2691 ivi->vlan = vfinfo->vlan;
661dbeb9 2692 return 0;
858aa65c 2693}
96fe11f2 2694
baf50868
GG		 2695static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2696 struct netdev_phys_item_id *ppid)
96fe11f2
GG		 2697{
2698 struct port_info *pi = netdev_priv(dev);
2699 unsigned int phy_port_id;
2700
2701 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2702 ppid->id_len = sizeof(phy_port_id);
2703 memcpy(ppid->id, &phy_port_id, ppid->id_len);
2704 return 0;
2705}
2706
baf50868
GG		 2707static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2708 int min_tx_rate, int max_tx_rate)
8ea4fae9
GG		 2709{
2710 struct port_info *pi = netdev_priv(dev);
2711 struct adapter *adap = pi->adapter;
c3168cab 2712 unsigned int link_ok, speed, mtu;
8ea4fae9
GG		 2713 u32 fw_pfvf, fw_class;
2714 int class_id = vf;
c3168cab 2715 int ret;
8ea4fae9
GG		 2716 u16 pktsize;
2717
2718 if (vf >= adap->num_vfs)
2719 return -EINVAL;
2720
2721 if (min_tx_rate) {
2722 dev_err(adap->pdev_dev,
2723 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2724 min_tx_rate, vf);
2725 return -EINVAL;
2726 }
c3168cab 2727
b5e281ab
GG		 2728 if (max_tx_rate == 0) {
2729 /* unbind VF to to any Traffic Class */
2730 fw_pfvf =
2731 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2732 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2733 fw_class = 0xffffffff;
2734 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2735 &fw_pfvf, &fw_class);
2736 if (ret) {
2737 dev_err(adap->pdev_dev,
2738 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2739 ret, adap->pf, vf);
2740 return -EINVAL;
2741 }
2742 dev_info(adap->pdev_dev,
2743 "PF %d VF %d is unbound from TX Rate Limiting\n",
2744 adap->pf, vf);
2745 adap->vfinfo[vf].tx_rate = 0;
2746 return 0;
2747 }
2748
c3168cab 2749 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
8ea4fae9
GG		 2750 if (ret != FW_SUCCESS) {
2751 dev_err(adap->pdev_dev,
c3168cab 2752 "Failed to get link information for VF %d\n", vf);
8ea4fae9
GG		 2753 return -EINVAL;
2754 }
c3168cab 2755
8ea4fae9
GG		 2756 if (!link_ok) {
2757 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2758 return -EINVAL;
2759 }
8ea4fae9
GG		 2760
2761 if (max_tx_rate > speed) {
2762 dev_err(adap->pdev_dev,
2763 "Max tx rate %d for VF %d can't be > link-speed %u",
2764 max_tx_rate, vf, speed);
2765 return -EINVAL;
2766 }
c3168cab
GG		 2767
2768 pktsize = mtu;
8ea4fae9
GG		 2769 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2770 pktsize = pktsize - sizeof(struct ethhdr) - 4;
2771 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2772 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2773 /* configure Traffic Class for rate-limiting */
2774 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2775 SCHED_CLASS_LEVEL_CL_RL,
2776 SCHED_CLASS_MODE_CLASS,
2777 SCHED_CLASS_RATEUNIT_BITS,
2778 SCHED_CLASS_RATEMODE_ABS,
c3168cab 2779 pi->tx_chan, class_id, 0,
8ea4fae9
GG		 2780 max_tx_rate * 1000, 0, pktsize);
2781 if (ret) {
2782 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2783 ret);
2784 return -EINVAL;
2785 }
2786 dev_info(adap->pdev_dev,
2787 "Class %d with MSS %u configured with rate %u\n",
2788 class_id, pktsize, max_tx_rate);
2789
2790 /* bind VF to configured Traffic Class */
2791 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2792 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2793 fw_class = class_id;
2794 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2795 &fw_class);
2796 if (ret) {
2797 dev_err(adap->pdev_dev,
b5e281ab
GG		 2798 "Err %d in binding PF %d VF %d to Traffic Class %d\n",
2799 ret, adap->pf, vf, class_id);
8ea4fae9
GG		 2800 return -EINVAL;
2801 }
2802 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2803 adap->pf, vf, class_id);
2804 adap->vfinfo[vf].tx_rate = max_tx_rate;
2805 return 0;
2806}
2807
9d5fd927
GG		 2808static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
2809 u16 vlan, u8 qos, __be16 vlan_proto)
2810{
2811 struct port_info *pi = netdev_priv(dev);
2812 struct adapter *adap = pi->adapter;
2813 int ret;
2814
2815 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
2816 return -EINVAL;
2817
2818 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
2819 return -EPROTONOSUPPORT;
2820
2821 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
2822 if (!ret) {
2823 adap->vfinfo[vf].vlan = vlan;
2824 return 0;
2825 }
2826
2827 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
2828 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
2829 return ret;
2830}
2831#endif /* CONFIG_PCI_IOV */
858aa65c 2832
b8ff05a9
DM		 2833static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2834{
2835 int ret;
2836 struct sockaddr *addr = p;
2837 struct port_info *pi = netdev_priv(dev);
2838
2839 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 2840 return -EADDRNOTAVAIL;
b8ff05a9 2841
b2612722 2842 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
02d805dc
SR		 2843 pi->xact_addr_filt, addr->sa_data, true,
2844 &pi->smt_idx);
b8ff05a9
DM		 2845 if (ret < 0)
2846 return ret;
2847
2848 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2849 pi->xact_addr_filt = ret;
2850 return 0;
2851}
2852
b8ff05a9
DM		 2853#ifdef CONFIG_NET_POLL_CONTROLLER
2854static void cxgb_netpoll(struct net_device *dev)
2855{
2856 struct port_info *pi = netdev_priv(dev);
2857 struct adapter *adap = pi->adapter;
2858
2859 if (adap->flags & USING_MSIX) {
2860 int i;
2861 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2862
2863 for (i = pi->nqsets; i; i--, rx++)
2864 t4_sge_intr_msix(0, &rx->rspq);
2865 } else
2866 t4_intr_handler(adap)(0, adap);
2867}
2868#endif
2869
10a2604e
RL		 2870static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2871{
2872 struct port_info *pi = netdev_priv(dev);
2873 struct adapter *adap = pi->adapter;
2874 struct sched_class *e;
2875 struct ch_sched_params p;
2876 struct ch_sched_queue qe;
2877 u32 req_rate;
2878 int err = 0;
2879
2880 if (!can_sched(dev))
2881 return -ENOTSUPP;
2882
2883 if (index < 0 || index > pi->nqsets - 1)
2884 return -EINVAL;
2885
2886 if (!(adap->flags & FULL_INIT_DONE)) {
2887 dev_err(adap->pdev_dev,
2888 "Failed to rate limit on queue %d. Link Down?\n",
2889 index);
2890 return -EINVAL;
2891 }
2892
2893 /* Convert from Mbps to Kbps */
b3c594ab 2894 req_rate = rate * 1000;
10a2604e 2895
d185efc1 2896 /* Max rate is 100 Gbps */
b3c594ab 2897 if (req_rate > SCHED_MAX_RATE_KBPS) {
10a2604e 2898 dev_err(adap->pdev_dev,
d185efc1 2899 "Invalid rate %u Mbps, Max rate is %u Mbps\n",
b3c594ab 2900 rate, SCHED_MAX_RATE_KBPS / 1000);
10a2604e
RL		 2901 return -ERANGE;
2902 }
2903
2904 /* First unbind the queue from any existing class */
2905 memset(&qe, 0, sizeof(qe));
2906 qe.queue = index;
2907 qe.class = SCHED_CLS_NONE;
2908
2909 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
2910 if (err) {
2911 dev_err(adap->pdev_dev,
2912 "Unbinding Queue %d on port %d fail. Err: %d\n",
2913 index, pi->port_id, err);
2914 return err;
2915 }
2916
2917 /* Queue already unbound */
2918 if (!req_rate)
2919 return 0;
2920
2921 /* Fetch any available unused or matching scheduling class */
2922 memset(&p, 0, sizeof(p));
2923 p.type = SCHED_CLASS_TYPE_PACKET;
2924 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL;
2925 p.u.params.mode = SCHED_CLASS_MODE_CLASS;
2926 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
2927 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
2928 p.u.params.channel = pi->tx_chan;
2929 p.u.params.class = SCHED_CLS_NONE;
2930 p.u.params.minrate = 0;
2931 p.u.params.maxrate = req_rate;
2932 p.u.params.weight = 0;
2933 p.u.params.pktsize = dev->mtu;
2934
2935 e = cxgb4_sched_class_alloc(dev, &p);
2936 if (!e)
2937 return -ENOMEM;
2938
2939 /* Bind the queue to a scheduling class */
2940 memset(&qe, 0, sizeof(qe));
2941 qe.queue = index;
2942 qe.class = e->idx;
2943
2944 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
2945 if (err)
2946 dev_err(adap->pdev_dev,
2947 "Queue rate limiting failed. Err: %d\n", err);
2948 return err;
2949}
2950
6a345b3d
KS		 2951static int cxgb_setup_tc_flower(struct net_device *dev,
2952 struct tc_cls_flower_offload *cls_flower)
2953{
6a345b3d
KS		 2954 switch (cls_flower->command) {
2955 case TC_CLSFLOWER_REPLACE:
2956 return cxgb4_tc_flower_replace(dev, cls_flower);
2957 case TC_CLSFLOWER_DESTROY:
2958 return cxgb4_tc_flower_destroy(dev, cls_flower);
2959 case TC_CLSFLOWER_STATS:
2960 return cxgb4_tc_flower_stats(dev, cls_flower);
2961 default:
2962 return -EOPNOTSUPP;
2963 }
2964}
2965
f7323043 2966static int cxgb_setup_tc_cls_u32(struct net_device *dev,
f7323043
JP		 2967 struct tc_cls_u32_offload *cls_u32)
2968{
f7323043
JP		 2969 switch (cls_u32->command) {
2970 case TC_CLSU32_NEW_KNODE:
2971 case TC_CLSU32_REPLACE_KNODE:
5fd9fc4e 2972 return cxgb4_config_knode(dev, cls_u32);
f7323043 2973 case TC_CLSU32_DELETE_KNODE:
5fd9fc4e 2974 return cxgb4_delete_knode(dev, cls_u32);
f7323043
JP		 2975 default:
2976 return -EOPNOTSUPP;
2977 }
2978}
2979
cd019e91
JP		 2980static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2981 void *cb_priv)
d8931847 2982{
cd019e91 2983 struct net_device *dev = cb_priv;
d8931847
RL		 2984 struct port_info *pi = netdev2pinfo(dev);
2985 struct adapter *adap = netdev2adap(dev);
2986
2987 if (!(adap->flags & FULL_INIT_DONE)) {
2988 dev_err(adap->pdev_dev,
2989 "Failed to setup tc on port %d. Link Down?\n",
2990 pi->port_id);
2991 return -EINVAL;
2992 }
2993
2a84bbaf 2994 if (!tc_cls_can_offload_and_chain0(dev, type_data))
44ae12a7
JP		 2995 return -EOPNOTSUPP;
2996
f7323043
JP		 2997 switch (type) {
2998 case TC_SETUP_CLSU32:
de4784ca 2999 return cxgb_setup_tc_cls_u32(dev, type_data);
6a345b3d
KS		 3000 case TC_SETUP_CLSFLOWER:
3001 return cxgb_setup_tc_flower(dev, type_data);
f7323043
JP		 3002 default:
3003 return -EOPNOTSUPP;
d8931847 3004 }
d8931847
RL		 3005}
3006
cd019e91
JP		 3007static int cxgb_setup_tc_block(struct net_device *dev,
3008 struct tc_block_offload *f)
3009{
3010 struct port_info *pi = netdev2pinfo(dev);
3011
3012 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3013 return -EOPNOTSUPP;
3014
3015 switch (f->command) {
3016 case TC_BLOCK_BIND:
3017 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb,
60513bd8 3018 pi, dev, f->extack);
cd019e91
JP		 3019 case TC_BLOCK_UNBIND:
3020 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi);
3021 return 0;
3022 default:
3023 return -EOPNOTSUPP;
3024 }
3025}
3026
3027static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3028 void *type_data)
3029{
3030 switch (type) {
cd019e91
JP		 3031 case TC_SETUP_BLOCK:
3032 return cxgb_setup_tc_block(dev, type_data);
3033 default:
3034 return -EOPNOTSUPP;
3035 }
3036}
3037
846eac3f
GG		 3038static void cxgb_del_udp_tunnel(struct net_device *netdev,
3039 struct udp_tunnel_info *ti)
3040{
3041 struct port_info *pi = netdev_priv(netdev);
3042 struct adapter *adapter = pi->adapter;
3043 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3044 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3045 int ret = 0, i;
3046
3047 if (chip_ver < CHELSIO_T6)
3048 return;
3049
3050 switch (ti->type) {
3051 case UDP_TUNNEL_TYPE_VXLAN:
3052 if (!adapter->vxlan_port_cnt ||
3053 adapter->vxlan_port != ti->port)
3054 return; /* Invalid VxLAN destination port */
3055
3056 adapter->vxlan_port_cnt--;
3057 if (adapter->vxlan_port_cnt)
3058 return;
3059
3060 adapter->vxlan_port = 0;
3061 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3062 break;
c746fc0e
GG		 3063 case UDP_TUNNEL_TYPE_GENEVE:
3064 if (!adapter->geneve_port_cnt ||
3065 adapter->geneve_port != ti->port)
3066 return; /* Invalid GENEVE destination port */
3067
3068 adapter->geneve_port_cnt--;
3069 if (adapter->geneve_port_cnt)
3070 return;
3071
3072 adapter->geneve_port = 0;
3073 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
942a656f 3074 break;
846eac3f
GG		 3075 default:
3076 return;
3077 }
3078
3079 /* Matchall mac entries can be deleted only after all tunnel ports
3080 * are brought down or removed.
3081 */
3082 if (!adapter->rawf_cnt)
3083 return;
3084 for_each_port(adapter, i) {
3085 pi = adap2pinfo(adapter, i);
3086 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3087 match_all_mac, match_all_mac,
3088 adapter->rawf_start +
3089 pi->port_id,
443e2dab 3090 1, pi->port_id, false);
846eac3f
GG		 3091 if (ret < 0) {
3092 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3093 i);
3094 return;
3095 }
3096 atomic_dec(&adapter->mps_encap[adapter->rawf_start +
3097 pi->port_id].refcnt);
3098 }
3099}
3100
3101static void cxgb_add_udp_tunnel(struct net_device *netdev,
3102 struct udp_tunnel_info *ti)
3103{
3104 struct port_info *pi = netdev_priv(netdev);
3105 struct adapter *adapter = pi->adapter;
3106 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3107 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3108 int i, ret;
3109
c746fc0e 3110 if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
846eac3f
GG		 3111 return;
3112
3113 switch (ti->type) {
3114 case UDP_TUNNEL_TYPE_VXLAN:
846eac3f
GG		 3115 /* Callback for adding vxlan port can be called with the same
3116 * port for both IPv4 and IPv6. We should not disable the
3117 * offloading when the same port for both protocols is added
3118 * and later one of them is removed.
3119 */
3120 if (adapter->vxlan_port_cnt &&
3121 adapter->vxlan_port == ti->port) {
3122 adapter->vxlan_port_cnt++;
3123 return;
3124 }
3125
3126 /* We will support only one VxLAN port */
3127 if (adapter->vxlan_port_cnt) {
3128 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3129 be16_to_cpu(adapter->vxlan_port),
3130 be16_to_cpu(ti->port));
3131 return;
3132 }
3133
3134 adapter->vxlan_port = ti->port;
3135 adapter->vxlan_port_cnt = 1;
3136
3137 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3138 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3139 break;
c746fc0e
GG		 3140 case UDP_TUNNEL_TYPE_GENEVE:
3141 if (adapter->geneve_port_cnt &&
3142 adapter->geneve_port == ti->port) {
3143 adapter->geneve_port_cnt++;
3144 return;
3145 }
3146
3147 /* We will support only one GENEVE port */
3148 if (adapter->geneve_port_cnt) {
3149 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3150 be16_to_cpu(adapter->geneve_port),
3151 be16_to_cpu(ti->port));
3152 return;
3153 }
3154
3155 adapter->geneve_port = ti->port;
3156 adapter->geneve_port_cnt = 1;
3157
3158 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3159 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
942a656f 3160 break;
846eac3f
GG		 3161 default:
3162 return;
3163 }
3164
3165 /* Create a 'match all' mac filter entry for inner mac,
3166 * if raw mac interface is supported. Once the linux kernel provides
3167 * driver entry points for adding/deleting the inner mac addresses,
3168 * we will remove this 'match all' entry and fallback to adding
3169 * exact match filters.
3170 */
c746fc0e
GG		 3171 for_each_port(adapter, i) {
3172 pi = adap2pinfo(adapter, i);
3173
3174 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3175 match_all_mac,
3176 match_all_mac,
3177 adapter->rawf_start +
3178 pi->port_id,
443e2dab 3179 1, pi->port_id, false);
c746fc0e
GG		 3180 if (ret < 0) {
3181 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3182 be16_to_cpu(ti->port));
3183 cxgb_del_udp_tunnel(netdev, ti);
3184 return;
846eac3f 3185 }
c746fc0e 3186 atomic_inc(&adapter->mps_encap[ret].refcnt);
846eac3f
GG		 3187 }
3188}
3189
4621ffd6
GG		 3190static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3191 struct net_device *dev,
3192 netdev_features_t features)
3193{
3194 struct port_info *pi = netdev_priv(dev);
3195 struct adapter *adapter = pi->adapter;
3196
3197 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3198 return features;
3199
3200 /* Check if hw supports offload for this packet */
3201 if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3202 return features;
3203
3204 /* Offload is not supported for this encapsulated packet */
3205 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3206}
3207
90592b9a
AV		 3208static netdev_features_t cxgb_fix_features(struct net_device *dev,
3209 netdev_features_t features)
3210{
3211 /* Disable GRO, if RX_CSUM is disabled */
3212 if (!(features & NETIF_F_RXCSUM))
3213 features &= ~NETIF_F_GRO;
3214
3215 return features;
3216}
3217
b8ff05a9
DM		 3218static const struct net_device_ops cxgb4_netdev_ops = {
3219 .ndo_open = cxgb_open,
3220 .ndo_stop = cxgb_close,
d5fbda61 3221 .ndo_start_xmit = t4_start_xmit,
688848b1 3222 .ndo_select_queue = cxgb_select_queue,
9be793bf 3223 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 3224 .ndo_set_rx_mode = cxgb_set_rxmode,
3225 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 3226 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 3227 .ndo_validate_addr = eth_validate_addr,
3228 .ndo_do_ioctl = cxgb_ioctl,
3229 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 3230#ifdef CONFIG_NET_POLL_CONTROLLER
3231 .ndo_poll_controller = cxgb_netpoll,
3232#endif
84a200b3
VP		 3233#ifdef CONFIG_CHELSIO_T4_FCOE
3234 .ndo_fcoe_enable = cxgb_fcoe_enable,
3235 .ndo_fcoe_disable = cxgb_fcoe_disable,
3236#endif /* CONFIG_CHELSIO_T4_FCOE */
10a2604e 3237 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate,
d8931847 3238 .ndo_setup_tc = cxgb_setup_tc,
846eac3f
GG		 3239 .ndo_udp_tunnel_add = cxgb_add_udp_tunnel,
3240 .ndo_udp_tunnel_del = cxgb_del_udp_tunnel,
4621ffd6 3241 .ndo_features_check = cxgb_features_check,
90592b9a 3242 .ndo_fix_features = cxgb_fix_features,
b8ff05a9
DM		 3243};
3244
858aa65c 3245#ifdef CONFIG_PCI_IOV
e7b48a32 3246static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
baf50868
GG		 3247 .ndo_open = cxgb4_mgmt_open,
3248 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac,
3249 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config,
3250 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate,
3251 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id,
9d5fd927 3252 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan,
7829451c 3253};
e7b48a32 3254#endif
7829451c 3255
baf50868
GG		 3256static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3257 struct ethtool_drvinfo *info)
7829451c
HS		 3258{
3259 struct adapter *adapter = netdev2adap(dev);
3260
3261 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3262 strlcpy(info->version, cxgb4_driver_version,
3263 sizeof(info->version));
3264 strlcpy(info->bus_info, pci_name(adapter->pdev),
3265 sizeof(info->bus_info));
3266}
3267
3268static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
baf50868 3269 .get_drvinfo = cxgb4_mgmt_get_drvinfo,
7829451c
HS		 3270};
3271
8b7372c1
GG		 3272static void notify_fatal_err(struct work_struct *work)
3273{
3274 struct adapter *adap;
3275
3276 adap = container_of(work, struct adapter, fatal_err_notify_task);
3277 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3278}
3279
b8ff05a9
DM		 3280void t4_fatal_err(struct adapter *adap)
3281{
3be0679b
HS		 3282 int port;
3283
025d0973
GP		 3284 if (pci_channel_offline(adap->pdev))
3285 return;
3286
3be0679b
HS		 3287 /* Disable the SGE since ULDs are going to free resources that
3288 * could be exposed to the adapter. RDMA MWs for example...
3289 */
3290 t4_shutdown_adapter(adap);
3291 for_each_port(adap, port) {
3292 struct net_device *dev = adap->port[port];
3293
3294 /* If we get here in very early initialization the network
3295 * devices may not have been set up yet.
3296 */
3297 if (!dev)
3298 continue;
3299
3300 netif_tx_stop_all_queues(dev);
3301 netif_carrier_off(dev);
3302 }
b8ff05a9 3303 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
8b7372c1 3304 queue_work(adap->workq, &adap->fatal_err_notify_task);
b8ff05a9
DM		 3305}
3306
3307static void setup_memwin(struct adapter *adap)
3308{
b562fc37 3309 u32 nic_win_base = t4_get_util_window(adap);
b8ff05a9 3310
b562fc37 3311 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
636f9d37
VP		 3312}
3313
3314static void setup_memwin_rdma(struct adapter *adap)
3315{
1ae970e0 3316 if (adap->vres.ocq.size) {
0abfd152
HS		 3317 u32 start;
3318 unsigned int sz_kb;
1ae970e0 3319
0abfd152
HS		 3320 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3321 start &= PCI_BASE_ADDRESS_MEM_MASK;
3322 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 3323 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3324 t4_write_reg(adap,
f061de42
HS		 3325 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3326 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
1ae970e0 3327 t4_write_reg(adap,
f061de42 3328 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
1ae970e0
DM		 3329 adap->vres.ocq.start);
3330 t4_read_reg(adap,
f061de42 3331 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
1ae970e0 3332 }
b8ff05a9
DM		 3333}
3334
8b4e6b3c
AV		 3335/* HMA Definitions */
3336
3337/* The maximum number of address that can be send in a single FW cmd */
3338#define HMA_MAX_ADDR_IN_CMD 5
3339
3340#define HMA_PAGE_SIZE PAGE_SIZE
3341
3342#define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */
3343
3344#define HMA_PAGE_ORDER \
3345 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \
3346 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3347
3348/* The minimum and maximum possible HMA sizes that can be specified in the FW
3349 * configuration(in units of MB).
3350 */
3351#define HMA_MIN_TOTAL_SIZE 1
3352#define HMA_MAX_TOTAL_SIZE \
3353 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \
3354 HMA_MAX_NO_FW_ADDRESS) >> 20)
3355
3356static void adap_free_hma_mem(struct adapter *adapter)
3357{
3358 struct scatterlist *iter;
3359 struct page *page;
3360 int i;
3361
3362 if (!adapter->hma.sgt)
3363 return;
3364
3365 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3366 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3367 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3368 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3369 }
3370
3371 for_each_sg(adapter->hma.sgt->sgl, iter,
3372 adapter->hma.sgt->orig_nents, i) {
3373 page = sg_page(iter);
3374 if (page)
3375 __free_pages(page, HMA_PAGE_ORDER);
3376 }
3377
3378 kfree(adapter->hma.phy_addr);
3379 sg_free_table(adapter->hma.sgt);
3380 kfree(adapter->hma.sgt);
3381 adapter->hma.sgt = NULL;
3382}
3383
3384static int adap_config_hma(struct adapter *adapter)
3385{
3386 struct scatterlist *sgl, *iter;
3387 struct sg_table *sgt;
3388 struct page *newpage;
3389 unsigned int i, j, k;
3390 u32 param, hma_size;
3391 unsigned int ncmds;
3392 size_t page_size;
3393 u32 page_order;
3394 int node, ret;
3395
3396 /* HMA is supported only for T6+ cards.
3397 * Avoid initializing HMA in kdump kernels.
3398 */
3399 if (is_kdump_kernel() ||
3400 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3401 return 0;
3402
3403 /* Get the HMA region size required by fw */
3404 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3405 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3406 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3407 1, &param, &hma_size);
3408 /* An error means card has its own memory or HMA is not supported by
3409 * the firmware. Return without any errors.
3410 */
3411 if (ret || !hma_size)
3412 return 0;
3413
3414 if (hma_size < HMA_MIN_TOTAL_SIZE ||
3415 hma_size > HMA_MAX_TOTAL_SIZE) {
3416 dev_err(adapter->pdev_dev,
3417 "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3418 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3419 return -EINVAL;
3420 }
3421
3422 page_size = HMA_PAGE_SIZE;
3423 page_order = HMA_PAGE_ORDER;
3424 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3425 if (unlikely(!adapter->hma.sgt)) {
3426 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3427 return -ENOMEM;
3428 }
3429 sgt = adapter->hma.sgt;
3430 /* FW returned value will be in MB's
3431 */
3432 sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3433 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3434 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3435 kfree(adapter->hma.sgt);
3436 adapter->hma.sgt = NULL;
3437 return -ENOMEM;
3438 }
3439
3440 sgl = adapter->hma.sgt->sgl;
3441 node = dev_to_node(adapter->pdev_dev);
3442 for_each_sg(sgl, iter, sgt->orig_nents, i) {
2b928749
GG		 3443 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
3444 __GFP_ZERO, page_order);
8b4e6b3c
AV		 3445 if (!newpage) {
3446 dev_err(adapter->pdev_dev,
3447 "Not enough memory for HMA page allocation\n");
3448 ret = -ENOMEM;
3449 goto free_hma;
3450 }
3451 sg_set_page(iter, newpage, page_size << page_order, 0);
3452 }
3453
3454 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3455 DMA_BIDIRECTIONAL);
3456 if (!sgt->nents) {
3457 dev_err(adapter->pdev_dev,
3458 "Not enough memory for HMA DMA mapping");
3459 ret = -ENOMEM;
3460 goto free_hma;
3461 }
3462 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3463
3464 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3465 GFP_KERNEL);
3466 if (unlikely(!adapter->hma.phy_addr))
3467 goto free_hma;
3468
3469 for_each_sg(sgl, iter, sgt->nents, i) {
3470 newpage = sg_page(iter);
3471 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3472 }
3473
3474 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3475 /* Pass on the addresses to firmware */
3476 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3477 struct fw_hma_cmd hma_cmd;
3478 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3479 u8 soc = 0, eoc = 0;
3480 u8 hma_mode = 1; /* Presently we support only Page table mode */
3481
3482 soc = (i == 0) ? 1 : 0;
3483 eoc = (i == ncmds - 1) ? 1 : 0;
3484
3485 /* For last cmd, set naddr corresponding to remaining
3486 * addresses
3487 */
3488 if (i == ncmds - 1) {
3489 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3490 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3491 }
3492 memset(&hma_cmd, 0, sizeof(hma_cmd));
3493 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3494 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3495 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3496
3497 hma_cmd.mode_to_pcie_params =
3498 htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3499 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3500
3501 /* HMA cmd size specified in MB's */
3502 hma_cmd.naddr_size =
3503 htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3504 FW_HMA_CMD_NADDR_V(naddr));
3505
3506 /* Total Page size specified in units of 4K */
3507 hma_cmd.addr_size_pkd =
3508 htonl(FW_HMA_CMD_ADDR_SIZE_V
3509 ((page_size << page_order) >> 12));
3510
3511 /* Fill the 5 addresses */
3512 for (j = 0; j < naddr; j++) {
3513 hma_cmd.phy_address[j] =
3514 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3515 }
3516 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3517 sizeof(hma_cmd), &hma_cmd);
3518 if (ret) {
3519 dev_err(adapter->pdev_dev,
3520 "HMA FW command failed with err %d\n", ret);
3521 goto free_hma;
3522 }
3523 }
3524
3525 if (!ret)
3526 dev_info(adapter->pdev_dev,
3527 "Reserved %uMB host memory for HMA\n", hma_size);
3528 return ret;
3529
3530free_hma:
3531 adap_free_hma_mem(adapter);
3532 return ret;
3533}
3534
02b5fb8e
DM		 3535static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3536{
3537 u32 v;
3538 int ret;
3539
0eaec62a
CL		 3540 /* Now that we've successfully configured and initialized the adapter
3541 * can ask the Firmware what resources it has provisioned for us.
3542 */
3543 ret = t4_get_pfres(adap);
3544 if (ret) {
3545 dev_err(adap->pdev_dev,
3546 "Unable to retrieve resource provisioning information\n");
3547 return ret;
3548 }
3549
02b5fb8e
DM		 3550 /* get device capabilities */
3551 memset(c, 0, sizeof(*c));
e2ac9628
HS		 3552 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3553 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3554 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
b2612722 3555 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
02b5fb8e
DM		 3556 if (ret < 0)
3557 return ret;
3558
e2ac9628
HS		 3559 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3560 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
b2612722 3561 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
02b5fb8e
DM		 3562 if (ret < 0)
3563 return ret;
3564
b2612722 3565 ret = t4_config_glbl_rss(adap, adap->pf,
02b5fb8e 3566 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
b2e1a3f0
HS		 3567 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3568 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
02b5fb8e
DM		 3569 if (ret < 0)
3570 return ret;
3571
b2612722 3572 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
4b8e27a8
HS		 3573 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3574 FW_CMD_CAP_PF);
02b5fb8e
DM		 3575 if (ret < 0)
3576 return ret;
3577
3578 t4_sge_init(adap);
3579
02b5fb8e 3580 /* tweak some settings */
837e4a42 3581 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
0d804338 3582 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
837e4a42
HS		 3583 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3584 v = t4_read_reg(adap, TP_PIO_DATA_A);
3585 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
060e0c75 3586
dca4faeb
VP		 3587 /* first 4 Tx modulation queues point to consecutive Tx channels */
3588 adap->params.tp.tx_modq_map = 0xE4;
0d804338
HS		 3589 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3590 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
dca4faeb
VP		 3591
3592 /* associate each Tx modulation queue with consecutive Tx channels */
3593 v = 0x84218421;
837e4a42 3594 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3595 &v, 1, TP_TX_SCHED_HDR_A);
837e4a42 3596 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3597 &v, 1, TP_TX_SCHED_FIFO_A);
837e4a42 3598 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3599 &v, 1, TP_TX_SCHED_PCMD_A);
dca4faeb
VP		 3600
3601#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3602 if (is_offload(adap)) {
0d804338
HS		 3603 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3604 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3605 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3606 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3607 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3608 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3609 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3610 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3611 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3612 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
dca4faeb
VP		 3613 }
3614
060e0c75 3615 /* get basic stuff going */
b2612722 3616 return t4_early_init(adap, adap->pf);
02b5fb8e
DM		 3617}
3618
b8ff05a9
DM		 3619/*
3620 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3621 */
3622#define MAX_ATIDS 8192U
3623
636f9d37
VP		 3624/*
3625 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3626 *
3627 * If the firmware we're dealing with has Configuration File support, then
3628 * we use that to perform all configuration
3629 */
3630
3631/*
3632 * Tweak configuration based on module parameters, etc. Most of these have
3633 * defaults assigned to them by Firmware Configuration Files (if we're using
3634 * them) but need to be explicitly set if we're using hard-coded
3635 * initialization. But even in the case of using Firmware Configuration
3636 * Files, we'd like to expose the ability to change these via module
3637 * parameters so these are essentially common tweaks/settings for
3638 * Configuration Files and hard-coded initialization ...
3639 */
3640static int adap_init0_tweaks(struct adapter *adapter)
3641{
3642 /*
3643 * Fix up various Host-Dependent Parameters like Page Size, Cache
3644 * Line Size, etc. The firmware default is for a 4KB Page Size and
3645 * 64B Cache Line Size ...
3646 */
3647 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3648
3649 /*
3650 * Process module parameters which affect early initialization.
3651 */
3652 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3653 dev_err(&adapter->pdev->dev,
3654 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3655 rx_dma_offset);
3656 rx_dma_offset = 2;
3657 }
f612b815
HS		 3658 t4_set_reg_field(adapter, SGE_CONTROL_A,
3659 PKTSHIFT_V(PKTSHIFT_M),
3660 PKTSHIFT_V(rx_dma_offset));
636f9d37
VP		 3661
3662 /*
3663 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3664 * adds the pseudo header itself.
3665 */
837e4a42
HS		 3666 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3667 CSUM_HAS_PSEUDO_HDR_F, 0);
636f9d37
VP		 3668
3669 return 0;
3670}
3671
01b69614
HS		 3672/* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3673 * unto themselves and they contain their own firmware to perform their
3674 * tasks ...
3675 */
3676static int phy_aq1202_version(const u8 *phy_fw_data,
3677 size_t phy_fw_size)
3678{
3679 int offset;
3680
3681 /* At offset 0x8 you're looking for the primary image's
3682 * starting offset which is 3 Bytes wide
3683 *
3684 * At offset 0xa of the primary image, you look for the offset
3685 * of the DRAM segment which is 3 Bytes wide.
3686 *
3687 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3688 * wide
3689 */
3690 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3691 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3692 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3693
3694 offset = le24(phy_fw_data + 0x8) << 12;
3695 offset = le24(phy_fw_data + offset + 0xa);
3696 return be16(phy_fw_data + offset + 0x27e);
3697
3698 #undef be16
3699 #undef le16
3700 #undef le24
3701}
3702
3703static struct info_10gbt_phy_fw {
3704 unsigned int phy_fw_id; /* PCI Device ID */
3705 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3706 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3707 int phy_flash; /* Has FLASH for PHY Firmware */
3708} phy_info_array[] = {
3709 {
3710 PHY_AQ1202_DEVICEID,
3711 PHY_AQ1202_FIRMWARE,
3712 phy_aq1202_version,
3713 1,
3714 },
3715 {
3716 PHY_BCM84834_DEVICEID,
3717 PHY_BCM84834_FIRMWARE,
3718 NULL,
3719 0,
3720 },
3721 { 0, NULL, NULL },
3722};
3723
3724static struct info_10gbt_phy_fw *find_phy_info(int devid)
3725{
3726 int i;
3727
3728 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3729 if (phy_info_array[i].phy_fw_id == devid)
3730 return &phy_info_array[i];
3731 }
3732 return NULL;
3733}
3734
3735/* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3736 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3737 * we return a negative error number. If we transfer new firmware we return 1
3738 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3739 */
3740static int adap_init0_phy(struct adapter *adap)
3741{
3742 const struct firmware *phyf;
3743 int ret;
3744 struct info_10gbt_phy_fw *phy_info;
3745
3746 /* Use the device ID to determine which PHY file to flash.
3747 */
3748 phy_info = find_phy_info(adap->pdev->device);
3749 if (!phy_info) {
3750 dev_warn(adap->pdev_dev,
3751 "No PHY Firmware file found for this PHY\n");
3752 return -EOPNOTSUPP;
3753 }
3754
3755 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3756 * use that. The adapter firmware provides us with a memory buffer
3757 * where we can load a PHY firmware file from the host if we want to
3758 * override the PHY firmware File in flash.
3759 */
3760 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3761 adap->pdev_dev);
3762 if (ret < 0) {
3763 /* For adapters without FLASH attached to PHY for their
3764 * firmware, it's obviously a fatal error if we can't get the
3765 * firmware to the adapter. For adapters with PHY firmware
3766 * FLASH storage, it's worth a warning if we can't find the
3767 * PHY Firmware but we'll neuter the error ...
3768 */
3769 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3770 "/lib/firmware/%s, error %d\n",
3771 phy_info->phy_fw_file, -ret);
3772 if (phy_info->phy_flash) {
3773 int cur_phy_fw_ver = 0;
3774
3775 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3776 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3777 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3778 ret = 0;
3779 }
3780
3781 return ret;
3782 }
3783
3784 /* Load PHY Firmware onto adapter.
3785 */
3786 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3787 phy_info->phy_fw_version,
3788 (u8 *)phyf->data, phyf->size);
3789 if (ret < 0)
3790 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3791 -ret);
3792 else if (ret > 0) {
3793 int new_phy_fw_ver = 0;
3794
3795 if (phy_info->phy_fw_version)
3796 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3797 phyf->size);
3798 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3799 "Firmware /lib/firmware/%s, version %#x\n",
3800 phy_info->phy_fw_file, new_phy_fw_ver);
3801 }
3802
3803 release_firmware(phyf);
3804
3805 return ret;
3806}
3807
636f9d37
VP		 3808/*
3809 * Attempt to initialize the adapter via a Firmware Configuration File.
3810 */
3811static int adap_init0_config(struct adapter *adapter, int reset)
3812{
3813 struct fw_caps_config_cmd caps_cmd;
3814 const struct firmware *cf;
3815 unsigned long mtype = 0, maddr = 0;
3816 u32 finiver, finicsum, cfcsum;
16e47624
HS		 3817 int ret;
3818 int config_issued = 0;
0a57a536 3819 char *fw_config_file, fw_config_file_path[256];
16e47624 3820 char *config_name = NULL;
636f9d37
VP		 3821
3822 /*
3823 * Reset device if necessary.
3824 */
3825 if (reset) {
3826 ret = t4_fw_reset(adapter, adapter->mbox,
0d804338 3827 PIORSTMODE_F | PIORST_F);
636f9d37
VP		 3828 if (ret < 0)
3829 goto bye;
3830 }
3831
01b69614
HS		 3832 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3833 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3834 * to be performed after any global adapter RESET above since some
3835 * PHYs only have local RAM copies of the PHY firmware.
3836 */
3837 if (is_10gbt_device(adapter->pdev->device)) {
3838 ret = adap_init0_phy(adapter);
3839 if (ret < 0)
3840 goto bye;
3841 }
636f9d37
VP		 3842 /*
3843 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3844 * then use that. Otherwise, use the configuration file stored
3845 * in the adapter flash ...
3846 */
d14807dd 3847 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 3848 case CHELSIO_T4:
16e47624 3849 fw_config_file = FW4_CFNAME;
0a57a536
SR		 3850 break;
3851 case CHELSIO_T5:
3852 fw_config_file = FW5_CFNAME;
3853 break;
3ccc6cf7
HS		 3854 case CHELSIO_T6:
3855 fw_config_file = FW6_CFNAME;
3856 break;
0a57a536
SR		 3857 default:
3858 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3859 adapter->pdev->device);
3860 ret = -EINVAL;
3861 goto bye;
3862 }
3863
3864 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 3865 if (ret < 0) {
16e47624 3866 config_name = "On FLASH";
636f9d37
VP		 3867 mtype = FW_MEMTYPE_CF_FLASH;
3868 maddr = t4_flash_cfg_addr(adapter);
3869 } else {
3870 u32 params[7], val[7];
3871
16e47624
HS		 3872 sprintf(fw_config_file_path,
3873 "/lib/firmware/%s", fw_config_file);
3874 config_name = fw_config_file_path;
3875
636f9d37
VP		 3876 if (cf->size >= FLASH_CFG_MAX_SIZE)
3877 ret = -ENOMEM;
3878 else {
5167865a
HS		 3879 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3880 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
636f9d37 3881 ret = t4_query_params(adapter, adapter->mbox,
b2612722 3882 adapter->pf, 0, 1, params, val);
636f9d37
VP		 3883 if (ret == 0) {
3884 /*
fc5ab020 3885 * For t4_memory_rw() below addresses and
636f9d37
VP		 3886 * sizes have to be in terms of multiples of 4
3887 * bytes. So, if the Configuration File isn't
3888 * a multiple of 4 bytes in length we'll have
3889 * to write that out separately since we can't
3890 * guarantee that the bytes following the
3891 * residual byte in the buffer returned by
3892 * request_firmware() are zeroed out ...
3893 */
3894 size_t resid = cf->size & 0x3;
3895 size_t size = cf->size & ~0x3;
3896 __be32 *data = (__be32 *)cf->data;
3897
5167865a
HS		 3898 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3899 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
636f9d37 3900
fc5ab020
HS		 3901 spin_lock(&adapter->win0_lock);
3902 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3903 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 3904 if (ret == 0 && resid != 0) {
3905 union {
3906 __be32 word;
3907 char buf[4];
3908 } last;
3909 int i;
3910
3911 last.word = data[size >> 2];
3912 for (i = resid; i < 4; i++)
3913 last.buf[i] = 0;
fc5ab020
HS		 3914 ret = t4_memory_rw(adapter, 0, mtype,
3915 maddr + size,
3916 4, &last.word,
3917 T4_MEMORY_WRITE);
636f9d37 3918 }
fc5ab020 3919 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 3920 }
3921 }
3922
3923 release_firmware(cf);
3924 if (ret)
3925 goto bye;
3926 }
3927
3928 /*
3929 * Issue a Capability Configuration command to the firmware to get it
3930 * to parse the Configuration File. We don't use t4_fw_config_file()
3931 * because we want the ability to modify various features after we've
3932 * processed the configuration file ...
3933 */
3934 memset(&caps_cmd, 0, sizeof(caps_cmd));
3935 caps_cmd.op_to_write =
e2ac9628
HS		 3936 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3937 FW_CMD_REQUEST_F |
3938 FW_CMD_READ_F);
ce91a923 3939 caps_cmd.cfvalid_to_len16 =
5167865a
HS		 3940 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3941 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3942 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
636f9d37
VP		 3943 FW_LEN16(caps_cmd));
3944 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3945 &caps_cmd);
16e47624
HS		 3946
3947 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3948 * Configuration File in FLASH), our last gasp effort is to use the
3949 * Firmware Configuration File which is embedded in the firmware. A
3950 * very few early versions of the firmware didn't have one embedded
3951 * but we can ignore those.
3952 */
3953 if (ret == -ENOENT) {
3954 memset(&caps_cmd, 0, sizeof(caps_cmd));
3955 caps_cmd.op_to_write =
e2ac9628
HS		 3956 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3957 FW_CMD_REQUEST_F |
3958 FW_CMD_READ_F);
16e47624
HS		 3959 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3960 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3961 sizeof(caps_cmd), &caps_cmd);
3962 config_name = "Firmware Default";
3963 }
3964
3965 config_issued = 1;
636f9d37
VP		 3966 if (ret < 0)
3967 goto bye;
3968
3969 finiver = ntohl(caps_cmd.finiver);
3970 finicsum = ntohl(caps_cmd.finicsum);
3971 cfcsum = ntohl(caps_cmd.cfcsum);
3972 if (finicsum != cfcsum)
3973 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3974 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3975 finicsum, cfcsum);
3976
636f9d37
VP		 3977 /*
3978 * And now tell the firmware to use the configuration we just loaded.
3979 */
3980 caps_cmd.op_to_write =
e2ac9628
HS		 3981 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3982 FW_CMD_REQUEST_F |
3983 FW_CMD_WRITE_F);
ce91a923 3984 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3985 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3986 NULL);
3987 if (ret < 0)
3988 goto bye;
3989
3990 /*
3991 * Tweak configuration based on system architecture, module
3992 * parameters, etc.
3993 */
3994 ret = adap_init0_tweaks(adapter);
3995 if (ret < 0)
3996 goto bye;
3997
8b4e6b3c
AV		 3998 /* We will proceed even if HMA init fails. */
3999 ret = adap_config_hma(adapter);
4000 if (ret)
4001 dev_err(adapter->pdev_dev,
4002 "HMA configuration failed with error %d\n", ret);
4003
636f9d37
VP		 4004 /*
4005 * And finally tell the firmware to initialize itself using the
4006 * parameters from the Configuration File.
4007 */
4008 ret = t4_fw_initialize(adapter, adapter->mbox);
4009 if (ret < 0)
4010 goto bye;
4011
06640310
HS		 4012 /* Emit Firmware Configuration File information and return
4013 * successfully.
636f9d37 4014 */
636f9d37 4015 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 4016 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
4017 config_name, finiver, cfcsum);
636f9d37
VP		 4018 return 0;
4019
4020 /*
4021 * Something bad happened. Return the error ... (If the "error"
4022 * is that there's no Configuration File on the adapter we don't
4023 * want to issue a warning since this is fairly common.)
4024 */
4025bye:
16e47624
HS		 4026 if (config_issued && ret != -ENOENT)
4027 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4028 config_name, -ret);
636f9d37
VP		 4029 return ret;
4030}
4031
16e47624
HS		 4032static struct fw_info fw_info_array[] = {
4033 {
4034 .chip = CHELSIO_T4,
4035 .fs_name = FW4_CFNAME,
4036 .fw_mod_name = FW4_FNAME,
4037 .fw_hdr = {
4038 .chip = FW_HDR_CHIP_T4,
4039 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4040 .intfver_nic = FW_INTFVER(T4, NIC),
4041 .intfver_vnic = FW_INTFVER(T4, VNIC),
4042 .intfver_ri = FW_INTFVER(T4, RI),
4043 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4044 .intfver_fcoe = FW_INTFVER(T4, FCOE),
4045 },
4046 }, {
4047 .chip = CHELSIO_T5,
4048 .fs_name = FW5_CFNAME,
4049 .fw_mod_name = FW5_FNAME,
4050 .fw_hdr = {
4051 .chip = FW_HDR_CHIP_T5,
4052 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4053 .intfver_nic = FW_INTFVER(T5, NIC),
4054 .intfver_vnic = FW_INTFVER(T5, VNIC),
4055 .intfver_ri = FW_INTFVER(T5, RI),
4056 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4057 .intfver_fcoe = FW_INTFVER(T5, FCOE),
4058 },
3ccc6cf7
HS		 4059 }, {
4060 .chip = CHELSIO_T6,
4061 .fs_name = FW6_CFNAME,
4062 .fw_mod_name = FW6_FNAME,
4063 .fw_hdr = {
4064 .chip = FW_HDR_CHIP_T6,
4065 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4066 .intfver_nic = FW_INTFVER(T6, NIC),
4067 .intfver_vnic = FW_INTFVER(T6, VNIC),
4068 .intfver_ofld = FW_INTFVER(T6, OFLD),
4069 .intfver_ri = FW_INTFVER(T6, RI),
4070 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4071 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4072 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4073 .intfver_fcoe = FW_INTFVER(T6, FCOE),
4074 },
16e47624 4075 }
3ccc6cf7 4076
16e47624
HS		 4077};
4078
4079static struct fw_info *find_fw_info(int chip)
4080{
4081 int i;
4082
4083 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4084 if (fw_info_array[i].chip == chip)
4085 return &fw_info_array[i];
4086 }
4087 return NULL;
4088}
4089
b8ff05a9
DM		 4090/*
4091 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4092 */
4093static int adap_init0(struct adapter *adap)
4094{
4095 int ret;
4096 u32 v, port_vec;
4097 enum dev_state state;
4098 u32 params[7], val[7];
9a4da2cd 4099 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 4100 int reset = 1;
b8ff05a9 4101
ae469b68
HS		 4102 /* Grab Firmware Device Log parameters as early as possible so we have
4103 * access to it for debugging, etc.
4104 */
4105 ret = t4_init_devlog_params(adap);
4106 if (ret < 0)
4107 return ret;
4108
666224d4 4109 /* Contact FW, advertising Master capability */
c5a8c0f3
HS		 4110 ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4111 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
b8ff05a9
DM		 4112 if (ret < 0) {
4113 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4114 ret);
4115 return ret;
4116 }
636f9d37
VP		 4117 if (ret == adap->mbox)
4118 adap->flags |= MASTER_PF;
b8ff05a9 4119
636f9d37
VP		 4120 /*
4121 * If we're the Master PF Driver and the device is uninitialized,
4122 * then let's consider upgrading the firmware ... (We always want
4123 * to check the firmware version number in order to A. get it for
4124 * later reporting and B. to warn if the currently loaded firmware
4125 * is excessively mismatched relative to the driver.)
4126 */
0de72738 4127
760446f9 4128 t4_get_version_info(adap);
a69265e9
HS		 4129 ret = t4_check_fw_version(adap);
4130 /* If firmware is too old (not supported by driver) force an update. */
21d11bd6 4131 if (ret)
a69265e9 4132 state = DEV_STATE_UNINIT;
636f9d37 4133 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 4134 struct fw_info *fw_info;
4135 struct fw_hdr *card_fw;
4136 const struct firmware *fw;
4137 const u8 *fw_data = NULL;
4138 unsigned int fw_size = 0;
4139
4140 /* This is the firmware whose headers the driver was compiled
4141 * against
4142 */
4143 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4144 if (fw_info == NULL) {
4145 dev_err(adap->pdev_dev,
4146 "unable to get firmware info for chip %d.\n",
4147 CHELSIO_CHIP_VERSION(adap->params.chip));
4148 return -EINVAL;
636f9d37 4149 }
16e47624
HS		 4150
4151 /* allocate memory to read the header of the firmware on the
4152 * card
4153 */
752ade68 4154 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
d624613e
Y		 4155 if (!card_fw) {
4156 ret = -ENOMEM;
4157 goto bye;
4158 }
16e47624
HS		 4159
4160 /* Get FW from from /lib/firmware/ */
4161 ret = request_firmware(&fw, fw_info->fw_mod_name,
4162 adap->pdev_dev);
4163 if (ret < 0) {
4164 dev_err(adap->pdev_dev,
4165 "unable to load firmware image %s, error %d\n",
4166 fw_info->fw_mod_name, ret);
4167 } else {
4168 fw_data = fw->data;
4169 fw_size = fw->size;
4170 }
4171
4172 /* upgrade FW logic */
4173 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4174 state, &reset);
4175
4176 /* Cleaning up */
0b5b6bee 4177 release_firmware(fw);
752ade68 4178 kvfree(card_fw);
16e47624 4179
636f9d37 4180 if (ret < 0)
16e47624 4181 goto bye;
636f9d37 4182 }
b8ff05a9 4183
06640310
HS		 4184 /* If the firmware is initialized already, emit a simply note to that
4185 * effect. Otherwise, it's time to try initializing the adapter.
636f9d37
VP		 4186 */
4187 if (state == DEV_STATE_INIT) {
8b4e6b3c
AV		 4188 ret = adap_config_hma(adap);
4189 if (ret)
4190 dev_err(adap->pdev_dev,
4191 "HMA configuration failed with error %d\n",
4192 ret);
636f9d37
VP		 4193 dev_info(adap->pdev_dev, "Coming up as %s: "\
4194 "Adapter already initialized\n",
4195 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
636f9d37
VP		 4196 } else {
4197 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4198 "Initializing adapter\n");
06640310
HS		 4199
4200 /* Find out whether we're dealing with a version of the
4201 * firmware which has configuration file support.
636f9d37 4202 */
06640310
HS		 4203 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4204 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
b2612722 4205 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
06640310 4206 params, val);
13ee15d3 4207
06640310
HS		 4208 /* If the firmware doesn't support Configuration Files,
4209 * return an error.
4210 */
4211 if (ret < 0) {
4212 dev_err(adap->pdev_dev, "firmware doesn't support "
4213 "Firmware Configuration Files\n");
4214 goto bye;
4215 }
4216
4217 /* The firmware provides us with a memory buffer where we can
4218 * load a Configuration File from the host if we want to
4219 * override the Configuration File in flash.
4220 */
4221 ret = adap_init0_config(adap, reset);
4222 if (ret == -ENOENT) {
4223 dev_err(adap->pdev_dev, "no Configuration File "
4224 "present on adapter.\n");
4225 goto bye;
636f9d37
VP		 4226 }
4227 if (ret < 0) {
06640310
HS		 4228 dev_err(adap->pdev_dev, "could not initialize "
4229 "adapter, error %d\n", -ret);
636f9d37
VP		 4230 goto bye;
4231 }
4232 }
4233
0eaec62a
CL		 4234 /* Now that we've successfully configured and initialized the adapter
4235 * (or found it already initialized), we can ask the Firmware what
4236 * resources it has provisioned for us.
4237 */
4238 ret = t4_get_pfres(adap);
4239 if (ret) {
4240 dev_err(adap->pdev_dev,
4241 "Unable to retrieve resource provisioning information\n");
4242 goto bye;
4243 }
4244
4245 /* Grab VPD parameters. This should be done after we establish a
4246 * connection to the firmware since some of the VPD parameters
4247 * (notably the Core Clock frequency) are retrieved via requests to
4248 * the firmware. On the other hand, we need these fairly early on
4249 * so we do this right after getting ahold of the firmware.
4250 *
4251 * We need to do this after initializing the adapter because someone
4252 * could have FLASHed a new VPD which won't be read by the firmware
4253 * until we do the RESET ...
4254 */
4255 ret = t4_get_vpd_params(adap, &adap->params.vpd);
4256 if (ret < 0)
4257 goto bye;
4258
4259 /* Find out what ports are available to us. Note that we need to do
4260 * this before calling adap_init0_no_config() since it needs nports
4261 * and portvec ...
4262 */
4263 v =
4264 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4265 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
4266 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
4267 if (ret < 0)
4268 goto bye;
4269
4270 adap->params.nports = hweight32(port_vec);
4271 adap->params.portvec = port_vec;
4272
06640310
HS		 4273 /* Give the SGE code a chance to pull in anything that it needs ...
4274 * Note that this must be called after we retrieve our VPD parameters
4275 * in order to know how to convert core ticks to seconds, etc.
636f9d37 4276 */
06640310
HS		 4277 ret = t4_sge_init(adap);
4278 if (ret < 0)
4279 goto bye;
636f9d37 4280
9a4da2cd
VP		 4281 if (is_bypass_device(adap->pdev->device))
4282 adap->params.bypass = 1;
4283
636f9d37
VP		 4284 /*
4285 * Grab some of our basic fundamental operating parameters.
4286 */
4287#define FW_PARAM_DEV(param) \
5167865a
HS		 4288 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
4289 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
636f9d37 4290
b8ff05a9 4291#define FW_PARAM_PFVF(param) \
5167865a
HS		 4292 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
4293 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
4294 FW_PARAMS_PARAM_Y_V(0) | \
4295 FW_PARAMS_PARAM_Z_V(0)
b8ff05a9 4296
636f9d37 4297 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 4298 params[1] = FW_PARAM_PFVF(L2T_START);
4299 params[2] = FW_PARAM_PFVF(L2T_END);
4300 params[3] = FW_PARAM_PFVF(FILTER_START);
4301 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 4302 params[5] = FW_PARAM_PFVF(IQFLINT_START);
b2612722 4303 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
b8ff05a9
DM		 4304 if (ret < 0)
4305 goto bye;
636f9d37
VP		 4306 adap->sge.egr_start = val[0];
4307 adap->l2t_start = val[1];
4308 adap->l2t_end = val[2];
b8ff05a9
DM		 4309 adap->tids.ftid_base = val[3];
4310 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 4311 adap->sge.ingr_start = val[5];
b8ff05a9 4312
0e249898
AV		 4313 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4314 /* Read the raw mps entries. In T6, the last 2 tcam entries
4315 * are reserved for raw mac addresses (rawf = 2, one per port).
4316 */
4317 params[0] = FW_PARAM_PFVF(RAWF_START);
4318 params[1] = FW_PARAM_PFVF(RAWF_END);
4319 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4320 params, val);
4321 if (ret == 0) {
4322 adap->rawf_start = val[0];
4323 adap->rawf_cnt = val[1] - val[0] + 1;
4324 }
4325 }
4326
4b8e27a8
HS		 4327 /* qids (ingress/egress) returned from firmware can be anywhere
4328 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4329 * Hence driver needs to allocate memory for this range to
4330 * store the queue info. Get the highest IQFLINT/EQ index returned
4331 * in FW_EQ_*_CMD.alloc command.
4332 */
4333 params[0] = FW_PARAM_PFVF(EQ_END);
4334 params[1] = FW_PARAM_PFVF(IQFLINT_END);
b2612722 4335 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4b8e27a8
HS		 4336 if (ret < 0)
4337 goto bye;
4338 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4339 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4340
4341 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4342 sizeof(*adap->sge.egr_map), GFP_KERNEL);
4343 if (!adap->sge.egr_map) {
4344 ret = -ENOMEM;
4345 goto bye;
4346 }
4347
4348 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4349 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4350 if (!adap->sge.ingr_map) {
4351 ret = -ENOMEM;
4352 goto bye;
4353 }
4354
4355 /* Allocate the memory for the vaious egress queue bitmaps
5b377d11 4356 * ie starving_fl, txq_maperr and blocked_fl.
4b8e27a8
HS		 4357 */
4358 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4359 sizeof(long), GFP_KERNEL);
4360 if (!adap->sge.starving_fl) {
4361 ret = -ENOMEM;
4362 goto bye;
4363 }
4364
4365 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4366 sizeof(long), GFP_KERNEL);
4367 if (!adap->sge.txq_maperr) {
4368 ret = -ENOMEM;
4369 goto bye;
4370 }
4371
5b377d11
HS		 4372#ifdef CONFIG_DEBUG_FS
4373 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4374 sizeof(long), GFP_KERNEL);
4375 if (!adap->sge.blocked_fl) {
4376 ret = -ENOMEM;
4377 goto bye;
4378 }
4379#endif
4380
b5a02f50
AB		 4381 params[0] = FW_PARAM_PFVF(CLIP_START);
4382 params[1] = FW_PARAM_PFVF(CLIP_END);
b2612722 4383 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
b5a02f50
AB		 4384 if (ret < 0)
4385 goto bye;
4386 adap->clipt_start = val[0];
4387 adap->clipt_end = val[1];
4388
b72a32da
RL		 4389 /* We don't yet have a PARAMs calls to retrieve the number of Traffic
4390 * Classes supported by the hardware/firmware so we hard code it here
4391 * for now.
4392 */
4393 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4394
636f9d37
VP		 4395 /* query params related to active filter region */
4396 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4397 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
b2612722 4398 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
636f9d37
VP		 4399 /* If Active filter size is set we enable establishing
4400 * offload connection through firmware work request
4401 */
4402 if ((val[0] != val[1]) && (ret >= 0)) {
4403 adap->flags |= FW_OFLD_CONN;
4404 adap->tids.aftid_base = val[0];
4405 adap->tids.aftid_end = val[1];
4406 }
4407
b407a4a9
VP		 4408 /* If we're running on newer firmware, let it know that we're
4409 * prepared to deal with encapsulated CPL messages. Older
4410 * firmware won't understand this and we'll just get
4411 * unencapsulated messages ...
4412 */
4413 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4414 val[0] = 1;
b2612722 4415 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
b407a4a9 4416
1ac0f095
KS		 4417 /*
4418 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4419 * capability. Earlier versions of the firmware didn't have the
4420 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4421 * permission to use ULPTX MEMWRITE DSGL.
4422 */
4423 if (is_t4(adap->params.chip)) {
4424 adap->params.ulptx_memwrite_dsgl = false;
4425 } else {
4426 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
b2612722 4427 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1ac0f095
KS		 4428 1, params, val);
4429 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4430 }
4431
086de575
SW		 4432 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4433 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4434 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4435 1, params, val);
4436 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4437
0ff90994
KS		 4438 /* See if FW supports FW_FILTER2 work request */
4439 if (is_t4(adap->params.chip)) {
4440 adap->params.filter2_wr_support = 0;
4441 } else {
4442 params[0] = FW_PARAM_DEV(FILTER2_WR);
4443 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4444 1, params, val);
4445 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4446 }
4447
02d805dc
SR		 4448 /* Check if FW supports returning vin and smt index.
4449 * If this is not supported, driver will interpret
4450 * these values from viid.
4451 */
4452 params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4453 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4454 1, params, val);
4455 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
4456
636f9d37
VP		 4457 /*
4458 * Get device capabilities so we can determine what resources we need
4459 * to manage.
4460 */
4461 memset(&caps_cmd, 0, sizeof(caps_cmd));
e2ac9628
HS		 4462 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4463 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 4464 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 4465 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4466 &caps_cmd);
4467 if (ret < 0)
4468 goto bye;
4469
5c31254e
KS		 4470 if (caps_cmd.ofldcaps ||
4471 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) {
b8ff05a9
DM		 4472 /* query offload-related parameters */
4473 params[0] = FW_PARAM_DEV(NTID);
4474 params[1] = FW_PARAM_PFVF(SERVER_START);
4475 params[2] = FW_PARAM_PFVF(SERVER_END);
4476 params[3] = FW_PARAM_PFVF(TDDP_START);
4477 params[4] = FW_PARAM_PFVF(TDDP_END);
4478 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
b2612722 4479 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 4480 params, val);
b8ff05a9
DM		 4481 if (ret < 0)
4482 goto bye;
4483 adap->tids.ntids = val[0];
4484 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4485 adap->tids.stid_base = val[1];
4486 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37 4487 /*
dbedd44e 4488 * Setup server filter region. Divide the available filter
636f9d37
VP		 4489 * region into two parts. Regular filters get 1/3rd and server
4490 * filters get 2/3rd part. This is only enabled if workarond
4491 * path is enabled.
4492 * 1. For regular filters.
4493 * 2. Server filter: This are special filters which are used
4494 * to redirect SYN packets to offload queue.
4495 */
4496 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
4497 adap->tids.sftid_base = adap->tids.ftid_base +
4498 DIV_ROUND_UP(adap->tids.nftids, 3);
4499 adap->tids.nsftids = adap->tids.nftids -
4500 DIV_ROUND_UP(adap->tids.nftids, 3);
4501 adap->tids.nftids = adap->tids.sftid_base -
4502 adap->tids.ftid_base;
4503 }
b8ff05a9
DM		 4504 adap->vres.ddp.start = val[3];
4505 adap->vres.ddp.size = val[4] - val[3] + 1;
4506 adap->params.ofldq_wr_cred = val[5];
636f9d37 4507
5c31254e 4508 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
004c3cf1
WY		 4509 ret = init_hash_filter(adap);
4510 if (ret < 0)
5c31254e
KS		 4511 goto bye;
4512 } else {
4513 adap->params.offload = 1;
4514 adap->num_ofld_uld += 1;
4515 }
b8ff05a9 4516 }
636f9d37 4517 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 4518 params[0] = FW_PARAM_PFVF(STAG_START);
4519 params[1] = FW_PARAM_PFVF(STAG_END);
4520 params[2] = FW_PARAM_PFVF(RQ_START);
4521 params[3] = FW_PARAM_PFVF(RQ_END);
4522 params[4] = FW_PARAM_PFVF(PBL_START);
4523 params[5] = FW_PARAM_PFVF(PBL_END);
b2612722 4524 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 4525 params, val);
b8ff05a9
DM		 4526 if (ret < 0)
4527 goto bye;
4528 adap->vres.stag.start = val[0];
4529 adap->vres.stag.size = val[1] - val[0] + 1;
4530 adap->vres.rq.start = val[2];
4531 adap->vres.rq.size = val[3] - val[2] + 1;
4532 adap->vres.pbl.start = val[4];
4533 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab 4534
c68644ef
RR		 4535 params[0] = FW_PARAM_PFVF(SRQ_START);
4536 params[1] = FW_PARAM_PFVF(SRQ_END);
4537 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4538 params, val);
4539 if (!ret) {
4540 adap->vres.srq.start = val[0];
4541 adap->vres.srq.size = val[1] - val[0] + 1;
4542 }
4543 if (adap->vres.srq.size) {
4544 adap->srq = t4_init_srq(adap->vres.srq.size);
4545 if (!adap->srq)
4546 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4547 }
4548
a0881cab
DM		 4549 params[0] = FW_PARAM_PFVF(SQRQ_START);
4550 params[1] = FW_PARAM_PFVF(SQRQ_END);
4551 params[2] = FW_PARAM_PFVF(CQ_START);
4552 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 4553 params[4] = FW_PARAM_PFVF(OCQ_START);
4554 params[5] = FW_PARAM_PFVF(OCQ_END);
b2612722 4555 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
5c937dd3 4556 val);
a0881cab
DM		 4557 if (ret < 0)
4558 goto bye;
4559 adap->vres.qp.start = val[0];
4560 adap->vres.qp.size = val[1] - val[0] + 1;
4561 adap->vres.cq.start = val[2];
4562 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 4563 adap->vres.ocq.start = val[4];
4564 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS		 4565
4566 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4567 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
b2612722 4568 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
5c937dd3 4569 val);
4c2c5763
HS		 4570 if (ret < 0) {
4571 adap->params.max_ordird_qp = 8;
4572 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4573 ret = 0;
4574 } else {
4575 adap->params.max_ordird_qp = val[0];
4576 adap->params.max_ird_adapter = val[1];
4577 }
4578 dev_info(adap->pdev_dev,
4579 "max_ordird_qp %d max_ird_adapter %d\n",
4580 adap->params.max_ordird_qp,
4581 adap->params.max_ird_adapter);
43db9296
RR		 4582
4583 /* Enable write_with_immediate if FW supports it */
4584 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
4585 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4586 val);
4587 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
f3910c62
RR		 4588
4589 /* Enable write_cmpl if FW supports it */
4590 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
4591 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4592 val);
4593 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
0fbc81b3 4594 adap->num_ofld_uld += 2;
b8ff05a9 4595 }
636f9d37 4596 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 4597 params[0] = FW_PARAM_PFVF(ISCSI_START);
4598 params[1] = FW_PARAM_PFVF(ISCSI_END);
b2612722 4599 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
636f9d37 4600 params, val);
b8ff05a9
DM		 4601 if (ret < 0)
4602 goto bye;
4603 adap->vres.iscsi.start = val[0];
4604 adap->vres.iscsi.size = val[1] - val[0] + 1;
0fbc81b3
HS		 4605 /* LIO target and cxgb4i initiaitor */
4606 adap->num_ofld_uld += 2;
b8ff05a9 4607 }
94cdb8bb 4608 if (caps_cmd.cryptocaps) {
e383f248
AG		 4609 if (ntohs(caps_cmd.cryptocaps) &
4610 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) {
4611 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
4612 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4613 2, params, val);
4614 if (ret < 0) {
4615 if (ret != -EINVAL)
4616 goto bye;
4617 } else {
4618 adap->vres.ncrypto_fc = val[0];
4619 }
4620 adap->num_ofld_uld += 1;
4621 }
4622 if (ntohs(caps_cmd.cryptocaps) &
4623 FW_CAPS_CONFIG_TLS_INLINE) {
4624 params[0] = FW_PARAM_PFVF(TLS_START);
4625 params[1] = FW_PARAM_PFVF(TLS_END);
4626 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4627 2, params, val);
4628 if (ret < 0)
72a56ca9 4629 goto bye;
e383f248
AG		 4630 adap->vres.key.start = val[0];
4631 adap->vres.key.size = val[1] - val[0] + 1;
4632 adap->num_uld += 1;
72a56ca9 4633 }
a6ec572b 4634 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
94cdb8bb 4635 }
b8ff05a9
DM		 4636#undef FW_PARAM_PFVF
4637#undef FW_PARAM_DEV
4638
92e7ae71
HS		 4639 /* The MTU/MSS Table is initialized by now, so load their values. If
4640 * we're initializing the adapter, then we'll make any modifications
4641 * we want to the MTU/MSS Table and also initialize the congestion
4642 * parameters.
636f9d37 4643 */
b8ff05a9 4644 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 4645 if (state != DEV_STATE_INIT) {
4646 int i;
4647
4648 /* The default MTU Table contains values 1492 and 1500.
4649 * However, for TCP, it's better to have two values which are
4650 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4651 * This allows us to have a TCP Data Payload which is a
4652 * multiple of 8 regardless of what combination of TCP Options
4653 * are in use (always a multiple of 4 bytes) which is
4654 * important for performance reasons. For instance, if no
4655 * options are in use, then we have a 20-byte IP header and a
4656 * 20-byte TCP header. In this case, a 1500-byte MSS would
4657 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4658 * which is not a multiple of 8. So using an MSS of 1488 in
4659 * this case results in a TCP Data Payload of 1448 bytes which
4660 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4661 * Stamps have been negotiated, then an MTU of 1500 bytes
4662 * results in a TCP Data Payload of 1448 bytes which, as
4663 * above, is a multiple of 8 bytes ...
4664 */
4665 for (i = 0; i < NMTUS; i++)
4666 if (adap->params.mtus[i] == 1492) {
4667 adap->params.mtus[i] = 1488;
4668 break;
4669 }
7ee9ff94 4670
92e7ae71
HS		 4671 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4672 adap->params.b_wnd);
4673 }
df64e4d3 4674 t4_init_sge_params(adap);
636f9d37 4675 adap->flags |= FW_OK;
5ccf9d04 4676 t4_init_tp_params(adap, true);
b8ff05a9
DM		 4677 return 0;
4678
4679 /*
636f9d37
VP		 4680 * Something bad happened. If a command timed out or failed with EIO
4681 * FW does not operate within its spec or something catastrophic
4682 * happened to HW/FW, stop issuing commands.
b8ff05a9 4683 */
636f9d37 4684bye:
8b4e6b3c 4685 adap_free_hma_mem(adap);
4b8e27a8
HS		 4686 kfree(adap->sge.egr_map);
4687 kfree(adap->sge.ingr_map);
4688 kfree(adap->sge.starving_fl);
4689 kfree(adap->sge.txq_maperr);
5b377d11
HS		 4690#ifdef CONFIG_DEBUG_FS
4691 kfree(adap->sge.blocked_fl);
4692#endif
636f9d37
VP		 4693 if (ret != -ETIMEDOUT && ret != -EIO)
4694 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 4695 return ret;
4696}
4697
204dc3c0
DM		 4698/* EEH callbacks */
4699
4700static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4701 pci_channel_state_t state)
4702{
4703 int i;
4704 struct adapter *adap = pci_get_drvdata(pdev);
4705
4706 if (!adap)
4707 goto out;
4708
4709 rtnl_lock();
4710 adap->flags &= ~FW_OK;
4711 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 4712 spin_lock(&adap->stats_lock);
204dc3c0
DM		 4713 for_each_port(adap, i) {
4714 struct net_device *dev = adap->port[i];
025d0973
GP		 4715 if (dev) {
4716 netif_device_detach(dev);
4717 netif_carrier_off(dev);
4718 }
204dc3c0 4719 }
9fe6cb58 4720 spin_unlock(&adap->stats_lock);
b37987e8 4721 disable_interrupts(adap);
204dc3c0
DM		 4722 if (adap->flags & FULL_INIT_DONE)
4723 cxgb_down(adap);
4724 rtnl_unlock();
144be3d9
GS		 4725 if ((adap->flags & DEV_ENABLED)) {
4726 pci_disable_device(pdev);
4727 adap->flags &= ~DEV_ENABLED;
4728 }
204dc3c0
DM		 4729out: return state == pci_channel_io_perm_failure ?
4730 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4731}
4732
4733static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4734{
4735 int i, ret;
4736 struct fw_caps_config_cmd c;
4737 struct adapter *adap = pci_get_drvdata(pdev);
4738
4739 if (!adap) {
4740 pci_restore_state(pdev);
4741 pci_save_state(pdev);
4742 return PCI_ERS_RESULT_RECOVERED;
4743 }
4744
144be3d9
GS		 4745 if (!(adap->flags & DEV_ENABLED)) {
4746 if (pci_enable_device(pdev)) {
4747 dev_err(&pdev->dev, "Cannot reenable PCI "
4748 "device after reset\n");
4749 return PCI_ERS_RESULT_DISCONNECT;
4750 }
4751 adap->flags |= DEV_ENABLED;
204dc3c0
DM		 4752 }
4753
4754 pci_set_master(pdev);
4755 pci_restore_state(pdev);
4756 pci_save_state(pdev);
204dc3c0 4757
8203b509 4758 if (t4_wait_dev_ready(adap->regs) < 0)
204dc3c0 4759 return PCI_ERS_RESULT_DISCONNECT;
b2612722 4760 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
204dc3c0
DM		 4761 return PCI_ERS_RESULT_DISCONNECT;
4762 adap->flags |= FW_OK;
4763 if (adap_init1(adap, &c))
4764 return PCI_ERS_RESULT_DISCONNECT;
4765
4766 for_each_port(adap, i) {
02d805dc
SR		 4767 struct port_info *pi = adap2pinfo(adap, i);
4768 u8 vivld = 0, vin = 0;
204dc3c0 4769
02d805dc
SR		 4770 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
4771 NULL, NULL, &vivld, &vin);
204dc3c0
DM		 4772 if (ret < 0)
4773 return PCI_ERS_RESULT_DISCONNECT;
02d805dc
SR		 4774 pi->viid = ret;
4775 pi->xact_addr_filt = -1;
4776 /* If fw supports returning the VIN as part of FW_VI_CMD,
4777 * save the returned values.
4778 */
4779 if (adap->params.viid_smt_extn_support) {
4780 pi->vivld = vivld;
4781 pi->vin = vin;
4782 } else {
4783 /* Retrieve the values from VIID */
4784 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
4785 pi->vin = FW_VIID_VIN_G(pi->viid);
4786 }
204dc3c0
DM		 4787 }
4788
4789 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4790 adap->params.b_wnd);
1ae970e0 4791 setup_memwin(adap);
204dc3c0
DM		 4792 if (cxgb_up(adap))
4793 return PCI_ERS_RESULT_DISCONNECT;
4794 return PCI_ERS_RESULT_RECOVERED;
4795}
4796
4797static void eeh_resume(struct pci_dev *pdev)
4798{
4799 int i;
4800 struct adapter *adap = pci_get_drvdata(pdev);
4801
4802 if (!adap)
4803 return;
4804
4805 rtnl_lock();
4806 for_each_port(adap, i) {
4807 struct net_device *dev = adap->port[i];
025d0973
GP		 4808 if (dev) {
4809 if (netif_running(dev)) {
4810 link_start(dev);
4811 cxgb_set_rxmode(dev);
4812 }
4813 netif_device_attach(dev);
204dc3c0 4814 }
204dc3c0
DM		 4815 }
4816 rtnl_unlock();
4817}
4818
3646f0e5 4819static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 4820 .error_detected = eeh_err_detected,
4821 .slot_reset = eeh_slot_reset,
4822 .resume = eeh_resume,
4823};
4824
9b86a8d1
HS		 4825/* Return true if the Link Configuration supports "High Speeds" (those greater
4826 * than 1Gb/s).
4827 */
57d8b764 4828static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 4829{
9b86a8d1
HS		 4830 unsigned int speeds, high_speeds;
4831
c3168cab
GG		 4832 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
4833 high_speeds = speeds &
4834 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
9b86a8d1
HS		 4835
4836 return high_speeds != 0;
b8ff05a9
DM		 4837}
4838
b8ff05a9
DM		 4839/*
4840 * Perform default configuration of DMA queues depending on the number and type
4841 * of ports we found and the number of available CPUs. Most settings can be
4842 * modified by the admin prior to actual use.
4843 */
0eaec62a 4844static int cfg_queues(struct adapter *adap)
b8ff05a9
DM		 4845{
4846 struct sge *s = &adap->sge;
0eaec62a
CL		 4847 int i, n10g = 0, qidx = 0;
4848 int niqflint, neq, avail_eth_qsets;
4849 int max_eth_qsets = 32;
688848b1
AB		 4850#ifndef CONFIG_CHELSIO_T4_DCB
4851 int q10g = 0;
4852#endif
b8ff05a9 4853
94cdb8bb
HS		 4854 /* Reduce memory usage in kdump environment, disable all offload.
4855 */
85eacf3f 4856 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
0fbc81b3 4857 adap->params.offload = 0;
94cdb8bb
HS		 4858 adap->params.crypto = 0;
4859 }
4860
0eaec62a
CL		 4861 /* Calculate the number of Ethernet Queue Sets available based on
4862 * resources provisioned for us. We always have an Asynchronous
4863 * Firmware Event Ingress Queue. If we're operating in MSI or Legacy
4864 * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt
4865 * Ingress Queue. Meanwhile, we need two Egress Queues for each
4866 * Queue Set: one for the Free List and one for the Ethernet TX Queue.
4867 *
4868 * Note that we should also take into account all of the various
4869 * Offload Queues. But, in any situation where we're operating in
4870 * a Resource Constrained Provisioning environment, doing any Offload
4871 * at all is problematic ...
4872 */
4873 niqflint = adap->params.pfres.niqflint - 1;
4874 if (!(adap->flags & USING_MSIX))
4875 niqflint--;
4876 neq = adap->params.pfres.neq / 2;
4877 avail_eth_qsets = min(niqflint, neq);
4878
4879 if (avail_eth_qsets > max_eth_qsets)
4880 avail_eth_qsets = max_eth_qsets;
4881
4882 if (avail_eth_qsets < adap->params.nports) {
4883 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n",
4884 avail_eth_qsets, adap->params.nports);
4885 return -ENOMEM;
4886 }
4887
4888 /* Count the number of 10Gb/s or better ports */
4889 for_each_port(adap, i)
4890 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4891
688848b1
AB		 4892#ifdef CONFIG_CHELSIO_T4_DCB
4893 /* For Data Center Bridging support we need to be able to support up
4894 * to 8 Traffic Priorities; each of which will be assigned to its
4895 * own TX Queue in order to prevent Head-Of-Line Blocking.
4896 */
0eaec62a
CL		 4897 if (adap->params.nports * 8 > avail_eth_qsets) {
4898 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
4899 avail_eth_qsets, adap->params.nports * 8);
4900 return -ENOMEM;
688848b1 4901 }
b8ff05a9 4902
688848b1
AB		 4903 for_each_port(adap, i) {
4904 struct port_info *pi = adap2pinfo(adap, i);
4905
4906 pi->first_qset = qidx;
85eacf3f 4907 pi->nqsets = is_kdump_kernel() ? 1 : 8;
688848b1
AB		 4908 qidx += pi->nqsets;
4909 }
4910#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4911 /*
4912 * We default to 1 queue per non-10G port and up to # of cores queues
4913 * per 10G port.
4914 */
4915 if (n10g)
0eaec62a 4916 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 4917 if (q10g > netif_get_num_default_rss_queues())
4918 q10g = netif_get_num_default_rss_queues();
b8ff05a9 4919
85eacf3f
GG		 4920 if (is_kdump_kernel())
4921 q10g = 1;
4922
b8ff05a9
DM		 4923 for_each_port(adap, i) {
4924 struct port_info *pi = adap2pinfo(adap, i);
4925
4926 pi->first_qset = qidx;
57d8b764 4927 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 4928 qidx += pi->nqsets;
4929 }
688848b1 4930#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4931
4932 s->ethqsets = qidx;
4933 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4934
0fbc81b3 4935 if (is_uld(adap)) {
b8ff05a9
DM		 4936 /*
4937 * For offload we use 1 queue/channel if all ports are up to 1G,
4938 * otherwise we divide all available queues amongst the channels
4939 * capped by the number of available cores.
4940 */
4941 if (n10g) {
a56177e1 4942 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
0fbc81b3
HS		 4943 s->ofldqsets = roundup(i, adap->params.nports);
4944 } else {
4945 s->ofldqsets = adap->params.nports;
4946 }
b8ff05a9
DM		 4947 }
4948
4949 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4950 struct sge_eth_rxq *r = &s->ethrxq[i];
4951
c887ad0e 4952 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 4953 r->fl.size = 72;
4954 }
4955
4956 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4957 s->ethtxq[i].q.size = 1024;
4958
4959 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4960 s->ctrlq[i].q.size = 512;
4961
a4569504
AG		 4962 if (!is_t4(adap->params.chip))
4963 s->ptptxq.q.size = 8;
4964
c887ad0e 4965 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
0fbc81b3 4966 init_rspq(adap, &s->intrq, 0, 1, 512, 64);
0eaec62a
CL		 4967
4968 return 0;
b8ff05a9
DM		 4969}
4970
4971/*
4972 * Reduce the number of Ethernet queues across all ports to at most n.
4973 * n provides at least one queue per port.
4974 */
91744948 4975static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 4976{
4977 int i;
4978 struct port_info *pi;
4979
4980 while (n < adap->sge.ethqsets)
4981 for_each_port(adap, i) {
4982 pi = adap2pinfo(adap, i);
4983 if (pi->nqsets > 1) {
4984 pi->nqsets--;
4985 adap->sge.ethqsets--;
4986 if (adap->sge.ethqsets <= n)
4987 break;
4988 }
4989 }
4990
4991 n = 0;
4992 for_each_port(adap, i) {
4993 pi = adap2pinfo(adap, i);
4994 pi->first_qset = n;
4995 n += pi->nqsets;
4996 }
4997}
4998
94cdb8bb
HS		 4999static int get_msix_info(struct adapter *adap)
5000{
5001 struct uld_msix_info *msix_info;
0fbc81b3
HS		 5002 unsigned int max_ingq = 0;
5003
5004 if (is_offload(adap))
5005 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
5006 if (is_pci_uld(adap))
5007 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
5008
5009 if (!max_ingq)
5010 goto out;
94cdb8bb
HS		 5011
5012 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
5013 if (!msix_info)
5014 return -ENOMEM;
5015
5016 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
5017 sizeof(long), GFP_KERNEL);
5018 if (!adap->msix_bmap_ulds.msix_bmap) {
5019 kfree(msix_info);
5020 return -ENOMEM;
5021 }
5022 spin_lock_init(&adap->msix_bmap_ulds.lock);
5023 adap->msix_info_ulds = msix_info;
0fbc81b3 5024out:
94cdb8bb
HS		 5025 return 0;
5026}
5027
5028static void free_msix_info(struct adapter *adap)
5029{
0fbc81b3 5030 if (!(adap->num_uld && adap->num_ofld_uld))
94cdb8bb
HS		 5031 return;
5032
5033 kfree(adap->msix_info_ulds);
5034 kfree(adap->msix_bmap_ulds.msix_bmap);
5035}
5036
b8ff05a9
DM		 5037/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5038#define EXTRA_VECS 2
5039
91744948 5040static int enable_msix(struct adapter *adap)
b8ff05a9 5041{
94cdb8bb
HS		 5042 int ofld_need = 0, uld_need = 0;
5043 int i, j, want, need, allocated;
b8ff05a9
DM		 5044 struct sge *s = &adap->sge;
5045 unsigned int nchan = adap->params.nports;
f36e58e5 5046 struct msix_entry *entries;
94cdb8bb 5047 int max_ingq = MAX_INGQ;
f36e58e5 5048
0fbc81b3
HS		 5049 if (is_pci_uld(adap))
5050 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
5051 if (is_offload(adap))
5052 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
6da2ec56
KC		 5053 entries = kmalloc_array(max_ingq + 1, sizeof(*entries),
5054 GFP_KERNEL);
f36e58e5
HS		 5055 if (!entries)
5056 return -ENOMEM;
b8ff05a9 5057
94cdb8bb 5058 /* map for msix */
0fbc81b3
HS		 5059 if (get_msix_info(adap)) {
5060 adap->params.offload = 0;
94cdb8bb 5061 adap->params.crypto = 0;
0fbc81b3 5062 }
94cdb8bb
HS		 5063
5064 for (i = 0; i < max_ingq + 1; ++i)
b8ff05a9
DM		 5065 entries[i].entry = i;
5066
5067 want = s->max_ethqsets + EXTRA_VECS;
5068 if (is_offload(adap)) {
0fbc81b3
HS		 5069 want += adap->num_ofld_uld * s->ofldqsets;
5070 ofld_need = adap->num_ofld_uld * nchan;
b8ff05a9 5071 }
94cdb8bb 5072 if (is_pci_uld(adap)) {
0fbc81b3
HS		 5073 want += adap->num_uld * s->ofldqsets;
5074 uld_need = adap->num_uld * nchan;
94cdb8bb 5075 }
688848b1
AB		 5076#ifdef CONFIG_CHELSIO_T4_DCB
5077 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
5078 * each port.
5079 */
94cdb8bb 5080 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
688848b1 5081#else
94cdb8bb 5082 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
688848b1 5083#endif
f36e58e5
HS		 5084 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
5085 if (allocated < 0) {
5086 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
5087 " not using MSI-X\n");
5088 kfree(entries);
5089 return allocated;
5090 }
b8ff05a9 5091
f36e58e5 5092 /* Distribute available vectors to the various queue groups.
c32ad224
AG		 5093 * Every group gets its minimum requirement and NIC gets top
5094 * priority for leftovers.
5095 */
94cdb8bb 5096 i = allocated - EXTRA_VECS - ofld_need - uld_need;
c32ad224
AG		 5097 if (i < s->max_ethqsets) {
5098 s->max_ethqsets = i;
5099 if (i < s->ethqsets)
5100 reduce_ethqs(adap, i);
5101 }
0fbc81b3 5102 if (is_uld(adap)) {
94cdb8bb
HS		 5103 if (allocated < want)
5104 s->nqs_per_uld = nchan;
5105 else
0fbc81b3 5106 s->nqs_per_uld = s->ofldqsets;
94cdb8bb
HS		 5107 }
5108
0fbc81b3 5109 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
c32ad224 5110 adap->msix_info[i].vec = entries[i].vector;
0fbc81b3
HS		 5111 if (is_uld(adap)) {
5112 for (j = 0 ; i < allocated; ++i, j++) {
94cdb8bb 5113 adap->msix_info_ulds[j].vec = entries[i].vector;
0fbc81b3
HS		 5114 adap->msix_info_ulds[j].idx = i;
5115 }
94cdb8bb
HS		 5116 adap->msix_bmap_ulds.mapsize = j;
5117 }
43eb4e82 5118 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
0fbc81b3
HS		 5119 "nic %d per uld %d\n",
5120 allocated, s->max_ethqsets, s->nqs_per_uld);
c32ad224 5121
f36e58e5 5122 kfree(entries);
c32ad224 5123 return 0;
b8ff05a9
DM		 5124}
5125
5126#undef EXTRA_VECS
5127
91744948 5128static int init_rss(struct adapter *adap)
671b0060 5129{
c035e183
HS		 5130 unsigned int i;
5131 int err;
5132
5133 err = t4_init_rss_mode(adap, adap->mbox);
5134 if (err)
5135 return err;
671b0060
DM		 5136
5137 for_each_port(adap, i) {
5138 struct port_info *pi = adap2pinfo(adap, i);
5139
5140 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5141 if (!pi->rss)
5142 return -ENOMEM;
671b0060
DM		 5143 }
5144 return 0;
5145}
5146
0de72738
HS		 5147/* Dump basic information about the adapter */
5148static void print_adapter_info(struct adapter *adapter)
5149{
760446f9
GG		 5150 /* Hardware/Firmware/etc. Version/Revision IDs */
5151 t4_dump_version_info(adapter);
0de72738
HS		 5152
5153 /* Software/Hardware configuration */
5154 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5155 is_offload(adapter) ? "R" : "",
5156 ((adapter->flags & USING_MSIX) ? "MSI-X" :
5157 (adapter->flags & USING_MSI) ? "MSI" : ""),
5158 is_offload(adapter) ? "Offload" : "non-Offload");
5159}
5160
91744948 5161static void print_port_info(const struct net_device *dev)
b8ff05a9 5162{
b8ff05a9 5163 char buf[80];
118969ed 5164 char *bufp = buf;
118969ed
DM		 5165 const struct port_info *pi = netdev_priv(dev);
5166 const struct adapter *adap = pi->adapter;
f1a051b9 5167
c3168cab 5168 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5e78f7fd 5169 bufp += sprintf(bufp, "100M/");
c3168cab 5170 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5e78f7fd 5171 bufp += sprintf(bufp, "1G/");
c3168cab 5172 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
118969ed 5173 bufp += sprintf(bufp, "10G/");
c3168cab 5174 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
9b86a8d1 5175 bufp += sprintf(bufp, "25G/");
c3168cab 5176 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
72aca4bf 5177 bufp += sprintf(bufp, "40G/");
c3168cab
GG		 5178 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5179 bufp += sprintf(bufp, "50G/");
5180 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
9b86a8d1 5181 bufp += sprintf(bufp, "100G/");
c3168cab
GG		 5182 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5183 bufp += sprintf(bufp, "200G/");
5184 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5185 bufp += sprintf(bufp, "400G/");
118969ed
DM		 5186 if (bufp != buf)
5187 --bufp;
72aca4bf 5188 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed 5189
0de72738
HS		 5190 netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5191 dev->name, adap->params.vpd.id, adap->name, buf);
b8ff05a9
DM		 5192}
5193
06546391
DM		 5194/*
5195 * Free the following resources:
5196 * - memory used for tables
5197 * - MSI/MSI-X
5198 * - net devices
5199 * - resources FW is holding for us
5200 */
5201static void free_some_resources(struct adapter *adapter)
5202{
5203 unsigned int i;
5204
0e249898 5205 kvfree(adapter->mps_encap);
3bdb376e 5206 kvfree(adapter->smt);
752ade68 5207 kvfree(adapter->l2t);
c68644ef 5208 kvfree(adapter->srq);
b72a32da 5209 t4_cleanup_sched(adapter);
752ade68 5210 kvfree(adapter->tids.tid_tab);
e0f911c8 5211 cxgb4_cleanup_tc_flower(adapter);
d8931847 5212 cxgb4_cleanup_tc_u32(adapter);
4b8e27a8
HS		 5213 kfree(adapter->sge.egr_map);
5214 kfree(adapter->sge.ingr_map);
5215 kfree(adapter->sge.starving_fl);
5216 kfree(adapter->sge.txq_maperr);
5b377d11
HS		 5217#ifdef CONFIG_DEBUG_FS
5218 kfree(adapter->sge.blocked_fl);
5219#endif
06546391
DM		 5220 disable_msi(adapter);
5221
5222 for_each_port(adapter, i)
671b0060 5223 if (adapter->port[i]) {
4f3a0fcf
HS		 5224 struct port_info *pi = adap2pinfo(adapter, i);
5225
5226 if (pi->viid != 0)
5227 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5228 0, pi->viid);
671b0060 5229 kfree(adap2pinfo(adapter, i)->rss);
06546391 5230 free_netdev(adapter->port[i]);
671b0060 5231 }
06546391 5232 if (adapter->flags & FW_OK)
b2612722 5233 t4_fw_bye(adapter, adapter->pf);
06546391
DM		 5234}
5235
2ed28baa 5236#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 5237#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 5238 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 5239#define SEGMENT_SIZE 128
b8ff05a9 5240
e8d45292 5241static int t4_get_chip_type(struct adapter *adap, int ver)
d86bd29e 5242{
e8d45292 5243 u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
46cdc9be 5244
e8d45292 5245 switch (ver) {
d86bd29e 5246 case CHELSIO_T4:
46cdc9be 5247 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
d86bd29e 5248 case CHELSIO_T5:
46cdc9be 5249 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
d86bd29e 5250 case CHELSIO_T6:
46cdc9be 5251 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
d86bd29e 5252 default:
e8d45292 5253 break;
d86bd29e 5254 }
46cdc9be 5255 return -EINVAL;
d86bd29e
HS		 5256}
5257
b6244201 5258#ifdef CONFIG_PCI_IOV
baf50868 5259static void cxgb4_mgmt_setup(struct net_device *dev)
e7b48a32
HS		 5260{
5261 dev->type = ARPHRD_NONE;
5262 dev->mtu = 0;
5263 dev->hard_header_len = 0;
5264 dev->addr_len = 0;
5265 dev->tx_queue_len = 0;
5266 dev->flags |= IFF_NOARP;
5267 dev->priv_flags |= IFF_NO_QUEUE;
5268
5269 /* Initialize the device structure. */
5270 dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5271 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
e7b48a32
HS		 5272}
5273
b6244201
HS		 5274static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5275{
7829451c 5276 struct adapter *adap = pci_get_drvdata(pdev);
b6244201
HS		 5277 int err = 0;
5278 int current_vfs = pci_num_vf(pdev);
5279 u32 pcie_fw;
b6244201 5280
7829451c 5281 pcie_fw = readl(adap->regs + PCIE_FW_A);
7cfac881
AV		 5282 /* Check if fw is initialized */
5283 if (!(pcie_fw & PCIE_FW_INIT_F)) {
5284 dev_warn(&pdev->dev, "Device not initialized\n");
b6244201
HS		 5285 return -EOPNOTSUPP;
5286 }
5287
5288 /* If any of the VF's is already assigned to Guest OS, then
5289 * SRIOV for the same cannot be modified
5290 */
5291 if (current_vfs && pci_vfs_assigned(pdev)) {
5292 dev_err(&pdev->dev,
5293 "Cannot modify SR-IOV while VFs are assigned\n");
baf50868 5294 return current_vfs;
b6244201 5295 }
baf50868
GG		 5296 /* Note that the upper-level code ensures that we're never called with
5297 * a non-zero "num_vfs" when we already have VFs instantiated. But
5298 * it never hurts to code defensively.
b6244201 5299 */
baf50868
GG		 5300 if (num_vfs != 0 && current_vfs != 0)
5301 return -EBUSY;
5302
5303 /* Nothing to do for no change. */
5304 if (num_vfs == current_vfs)
5305 return num_vfs;
5306
5307 /* Disable SRIOV when zero is passed. */
b6244201
HS		 5308 if (!num_vfs) {
5309 pci_disable_sriov(pdev);
baf50868
GG		 5310 /* free VF Management Interface */
5311 unregister_netdev(adap->port[0]);
5312 free_netdev(adap->port[0]);
5313 adap->port[0] = NULL;
5314
661dbeb9 5315 /* free VF resources */
baf50868 5316 adap->num_vfs = 0;
661dbeb9
HS		 5317 kfree(adap->vfinfo);
5318 adap->vfinfo = NULL;
baf50868 5319 return 0;
b6244201
HS		 5320 }
5321
baf50868
GG		 5322 if (!current_vfs) {
5323 struct fw_pfvf_cmd port_cmd, port_rpl;
5324 struct net_device *netdev;
5325 unsigned int pmask, port;
5326 struct pci_dev *pbridge;
5327 struct port_info *pi;
5328 char name[IFNAMSIZ];
5329 u32 devcap2;
5330 u16 flags;
5331 int pos;
5332
5333 /* If we want to instantiate Virtual Functions, then our
5334 * parent bridge's PCI-E needs to support Alternative Routing
5335 * ID (ARI) because our VFs will show up at function offset 8
5336 * and above.
5337 */
5338 pbridge = pdev->bus->self;
5339 pos = pci_find_capability(pbridge, PCI_CAP_ID_EXP);
5340 pci_read_config_word(pbridge, pos + PCI_EXP_FLAGS, &flags);
5341 pci_read_config_dword(pbridge, pos + PCI_EXP_DEVCAP2, &devcap2);
5342
5343 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5344 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5345 /* Our parent bridge does not support ARI so issue a
5346 * warning and skip instantiating the VFs. They
5347 * won't be reachable.
5348 */
5349 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5350 pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5351 PCI_FUNC(pbridge->devfn));
5352 return -ENOTSUPP;
5353 }
5354 memset(&port_cmd, 0, sizeof(port_cmd));
5355 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
5356 FW_CMD_REQUEST_F |
5357 FW_CMD_READ_F |
5358 FW_PFVF_CMD_PFN_V(adap->pf) |
5359 FW_PFVF_CMD_VFN_V(0));
5360 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
5361 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
5362 &port_rpl);
b6244201
HS		 5363 if (err)
5364 return err;
baf50868
GG		 5365 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
5366 port = ffs(pmask) - 1;
5367 /* Allocate VF Management Interface. */
5368 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
5369 adap->pf);
5370 netdev = alloc_netdev(sizeof(struct port_info),
5371 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
5372 if (!netdev)
5373 return -ENOMEM;
7829451c 5374
baf50868
GG		 5375 pi = netdev_priv(netdev);
5376 pi->adapter = adap;
5377 pi->lport = port;
5378 pi->tx_chan = port;
5379 SET_NETDEV_DEV(netdev, &pdev->dev);
5380
5381 adap->port[0] = netdev;
5382 pi->port_id = 0;
5383
5384 err = register_netdev(adap->port[0]);
5385 if (err) {
5386 pr_info("Unable to register VF mgmt netdev %s\n", name);
5387 free_netdev(adap->port[0]);
5388 adap->port[0] = NULL;
e7b48a32 5389 return err;
baf50868
GG		 5390 }
5391 /* Allocate and set up VF Information. */
5392 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
5393 sizeof(struct vf_info), GFP_KERNEL);
5394 if (!adap->vfinfo) {
5395 unregister_netdev(adap->port[0]);
5396 free_netdev(adap->port[0]);
5397 adap->port[0] = NULL;
5398 return -ENOMEM;
5399 }
5400 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
5401 }
5402 /* Instantiate the requested number of VFs. */
5403 err = pci_enable_sriov(pdev, num_vfs);
5404 if (err) {
5405 pr_info("Unable to instantiate %d VFs\n", num_vfs);
5406 if (!current_vfs) {
5407 unregister_netdev(adap->port[0]);
5408 free_netdev(adap->port[0]);
5409 adap->port[0] = NULL;
5410 kfree(adap->vfinfo);
5411 adap->vfinfo = NULL;
5412 }
5413 return err;
b6244201 5414 }
661dbeb9 5415
baf50868 5416 adap->num_vfs = num_vfs;
b6244201
HS		 5417 return num_vfs;
5418}
baf50868 5419#endif /* CONFIG_PCI_IOV */
b6244201 5420
1dd06ae8 5421static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 5422{
e8d45292
GG		 5423 struct net_device *netdev;
5424 struct adapter *adapter;
5425 static int adap_idx = 1;
5426 int s_qpp, qpp, num_seg;
b8ff05a9 5427 struct port_info *pi;
c8f44aff 5428 bool highdma = false;
d86bd29e 5429 enum chip_type chip;
e8d45292
GG		 5430 void __iomem *regs;
5431 int func, chip_ver;
5432 u16 device_id;
5433 int i, err;
5434 u32 whoami;
b8ff05a9
DM		 5435
5436 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
5437
5438 err = pci_request_regions(pdev, KBUILD_MODNAME);
5439 if (err) {
5440 /* Just info, some other driver may have claimed the device. */
5441 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
5442 return err;
5443 }
5444
b8ff05a9
DM		 5445 err = pci_enable_device(pdev);
5446 if (err) {
5447 dev_err(&pdev->dev, "cannot enable PCI device\n");
5448 goto out_release_regions;
5449 }
5450
d6ce2628
HS		 5451 regs = pci_ioremap_bar(pdev, 0);
5452 if (!regs) {
5453 dev_err(&pdev->dev, "cannot map device registers\n");
5454 err = -ENOMEM;
5455 goto out_disable_device;
5456 }
5457
baf50868
GG		 5458 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5459 if (!adapter) {
5460 err = -ENOMEM;
5461 goto out_unmap_bar0;
5462 }
5463
5464 adapter->regs = regs;
8203b509
HS		 5465 err = t4_wait_dev_ready(regs);
5466 if (err < 0)
e729452e 5467 goto out_free_adapter;
8203b509 5468
d6ce2628 5469 /* We control everything through one PF */
e8d45292
GG		 5470 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5471 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
5472 chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
5473 if (chip < 0) {
5474 dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
5475 err = chip;
5476 goto out_free_adapter;
5477 }
5478 chip_ver = CHELSIO_CHIP_VERSION(chip);
5479 func = chip_ver <= CHELSIO_T5 ?
5480 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
baf50868
GG		 5481
5482 adapter->pdev = pdev;
5483 adapter->pdev_dev = &pdev->dev;
5484 adapter->name = pci_name(pdev);
5485 adapter->mbox = func;
5486 adapter->pf = func;
016764de
GG		 5487 adapter->params.chip = chip;
5488 adapter->adap_idx = adap_idx;
baf50868
GG		 5489 adapter->msg_enable = DFLT_MSG_ENABLE;
5490 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5491 (sizeof(struct mbox_cmd) *
5492 T4_OS_LOG_MBOX_CMDS),
5493 GFP_KERNEL);
5494 if (!adapter->mbox_log) {
5495 err = -ENOMEM;
5496 goto out_free_adapter;
5497 }
5498 spin_lock_init(&adapter->mbox_lock);
5499 INIT_LIST_HEAD(&adapter->mlist.list);
aca06eaf 5500 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
baf50868
GG		 5501 pci_set_drvdata(pdev, adapter);
5502
d6ce2628 5503 if (func != ent->driver_data) {
d6ce2628
HS		 5504 pci_disable_device(pdev);
5505 pci_save_state(pdev); /* to restore SR-IOV later */
baf50868 5506 return 0;
d6ce2628
HS		 5507 }
5508
b8ff05a9 5509 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 5510 highdma = true;
b8ff05a9
DM		 5511 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
5512 if (err) {
5513 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
5514 "coherent allocations\n");
baf50868 5515 goto out_free_adapter;
b8ff05a9
DM		 5516 }
5517 } else {
5518 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5519 if (err) {
5520 dev_err(&pdev->dev, "no usable DMA configuration\n");
baf50868 5521 goto out_free_adapter;
b8ff05a9
DM		 5522 }
5523 }
5524
5525 pci_enable_pcie_error_reporting(pdev);
5526 pci_set_master(pdev);
5527 pci_save_state(pdev);
7829451c 5528 adap_idx++;
29aaee65
AB		 5529 adapter->workq = create_singlethread_workqueue("cxgb4");
5530 if (!adapter->workq) {
5531 err = -ENOMEM;
5532 goto out_free_adapter;
5533 }
5534
144be3d9
GS		 5535 /* PCI device has been enabled */
5536 adapter->flags |= DEV_ENABLED;
b8ff05a9
DM		 5537 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
5538
b0ba9d5f
CL		 5539 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
5540 * Ingress Packet Data to Free List Buffers in order to allow for
5541 * chipset performance optimizations between the Root Complex and
5542 * Memory Controllers. (Messages to the associated Ingress Queue
5543 * notifying new Packet Placement in the Free Lists Buffers will be
5544 * send without the Relaxed Ordering Attribute thus guaranteeing that
5545 * all preceding PCIe Transaction Layer Packets will be processed
5546 * first.) But some Root Complexes have various issues with Upstream
5547 * Transaction Layer Packets with the Relaxed Ordering Attribute set.
5548 * The PCIe devices which under the Root Complexes will be cleared the
5549 * Relaxed Ordering bit in the configuration space, So we check our
5550 * PCIe configuration space to see if it's flagged with advice against
5551 * using Relaxed Ordering.
5552 */
5553 if (!pcie_relaxed_ordering_enabled(pdev))
5554 adapter->flags |= ROOT_NO_RELAXED_ORDERING;
5555
b8ff05a9
DM		 5556 spin_lock_init(&adapter->stats_lock);
5557 spin_lock_init(&adapter->tid_release_lock);
e327c225 5558 spin_lock_init(&adapter->win0_lock);
b8ff05a9
DM		 5559
5560 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 5561 INIT_WORK(&adapter->db_full_task, process_db_full);
5562 INIT_WORK(&adapter->db_drop_task, process_db_drop);
8b7372c1 5563 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
b8ff05a9
DM		 5564
5565 err = t4_prep_adapter(adapter);
5566 if (err)
d6ce2628
HS		 5567 goto out_free_adapter;
5568
1dde532d
RL		 5569 if (is_kdump_kernel()) {
5570 /* Collect hardware state and append to /proc/vmcore */
5571 err = cxgb4_cudbg_vmcore_add_dump(adapter);
5572 if (err) {
5573 dev_warn(adapter->pdev_dev,
5574 "Fail collecting vmcore device dump, err: %d. Continuing\n",
5575 err);
5576 err = 0;
5577 }
5578 }
22adfe0a 5579
d14807dd 5580 if (!is_t4(adapter->params.chip)) {
f612b815
HS		 5581 s_qpp = (QUEUESPERPAGEPF0_S +
5582 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
b2612722 5583 adapter->pf);
f612b815
HS		 5584 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
5585 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
22adfe0a
SR		 5586 num_seg = PAGE_SIZE / SEGMENT_SIZE;
5587
5588 /* Each segment size is 128B. Write coalescing is enabled only
5589 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
5590 * queue is less no of segments that can be accommodated in
5591 * a page size.
5592 */
5593 if (qpp > num_seg) {
5594 dev_err(&pdev->dev,
5595 "Incorrect number of egress queues per page\n");
5596 err = -EINVAL;
d6ce2628 5597 goto out_free_adapter;
22adfe0a
SR		 5598 }
5599 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
5600 pci_resource_len(pdev, 2));
5601 if (!adapter->bar2) {
5602 dev_err(&pdev->dev, "cannot map device bar2 region\n");
5603 err = -ENOMEM;
d6ce2628 5604 goto out_free_adapter;
22adfe0a
SR		 5605 }
5606 }
5607
636f9d37 5608 setup_memwin(adapter);
b8ff05a9 5609 err = adap_init0(adapter);
5b377d11
HS		 5610#ifdef CONFIG_DEBUG_FS
5611 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
5612#endif
636f9d37 5613 setup_memwin_rdma(adapter);
b8ff05a9
DM		 5614 if (err)
5615 goto out_unmap_bar;
5616
2a485cf7
HS		 5617 /* configure SGE_STAT_CFG_A to read WC stats */
5618 if (!is_t4(adapter->params.chip))
676d6a75
HS		 5619 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
5620 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
5621 T6_STATMODE_V(0)));
2a485cf7 5622
b539ea60
AV		 5623 /* Initialize hash mac addr list */
5624 INIT_LIST_HEAD(&adapter->mac_hlist);
5625
b8ff05a9 5626 for_each_port(adapter, i) {
b8ff05a9
DM		 5627 netdev = alloc_etherdev_mq(sizeof(struct port_info),
5628 MAX_ETH_QSETS);
5629 if (!netdev) {
5630 err = -ENOMEM;
5631 goto out_free_dev;
5632 }
5633
5634 SET_NETDEV_DEV(netdev, &pdev->dev);
5635
5636 adapter->port[i] = netdev;
5637 pi = netdev_priv(netdev);
5638 pi->adapter = adapter;
5639 pi->xact_addr_filt = -1;
b8ff05a9 5640 pi->port_id = i;
b8ff05a9
DM		 5641 netdev->irq = pdev->irq;
5642
2ed28baa
MM		 5643 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5644 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5645 NETIF_F_RXCSUM | NETIF_F_RXHASH |
d8931847
RL		 5646 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
5647 NETIF_F_HW_TC;
d0a1299c 5648
e8d45292 5649 if (chip_ver > CHELSIO_T5) {
c50ae55e
GG		 5650 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
5651 NETIF_F_IPV6_CSUM |
5652 NETIF_F_RXCSUM |
5653 NETIF_F_GSO_UDP_TUNNEL |
5654 NETIF_F_TSO | NETIF_F_TSO6;
5655
1435d997
AG		 5656 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
5657 NETIF_F_HW_TLS_RECORD;
c50ae55e 5658 }
d0a1299c 5659
c8f44aff
MM		 5660 if (highdma)
5661 netdev->hw_features |= NETIF_F_HIGHDMA;
5662 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 5663 netdev->vlan_features = netdev->features & VLAN_FEAT;
5664
01789349
JP		 5665 netdev->priv_flags |= IFF_UNICAST_FLT;
5666
d894be57 5667 /* MTU range: 81 - 9600 */
a047fbae 5668 netdev->min_mtu = 81; /* accommodate SACK */
d894be57
JW		 5669 netdev->max_mtu = MAX_MTU;
5670
b8ff05a9 5671 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 5672#ifdef CONFIG_CHELSIO_T4_DCB
5673 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5674 cxgb4_dcb_state_init(netdev);
ebddd97a 5675 cxgb4_dcb_version_init(netdev);
688848b1 5676#endif
812034f1 5677 cxgb4_set_ethtool_ops(netdev);
b8ff05a9
DM		 5678 }
5679
ad75b7d3
RL		 5680 cxgb4_init_ethtool_dump(adapter);
5681
b8ff05a9
DM		 5682 pci_set_drvdata(pdev, adapter);
5683
5684 if (adapter->flags & FW_OK) {
060e0c75 5685 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 5686 if (err)
5687 goto out_free_dev;
098ef6c2
HS		 5688 } else if (adapter->params.nports == 1) {
5689 /* If we don't have a connection to the firmware -- possibly
5690 * because of an error -- grab the raw VPD parameters so we
5691 * can set the proper MAC Address on the debug network
5692 * interface that we've created.
5693 */
5694 u8 hw_addr[ETH_ALEN];
5695 u8 *na = adapter->params.vpd.na;
5696
5697 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5698 if (!err) {
5699 for (i = 0; i < ETH_ALEN; i++)
5700 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5701 hex2val(na[2 * i + 1]));
5702 t4_set_hw_addr(adapter, 0, hw_addr);
5703 }
b8ff05a9
DM		 5704 }
5705
0eaec62a
CL		 5706 if (!(adapter->flags & FW_OK))
5707 goto fw_attach_fail;
5708
098ef6c2 5709 /* Configure queues and allocate tables now, they can be needed as
b8ff05a9
DM		 5710 * soon as the first register_netdev completes.
5711 */
0eaec62a
CL		 5712 err = cfg_queues(adapter);
5713 if (err)
5714 goto out_free_dev;
b8ff05a9 5715
3bdb376e
KS		 5716 adapter->smt = t4_init_smt();
5717 if (!adapter->smt) {
5718 /* We tolerate a lack of SMT, giving up some functionality */
5719 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
5720 }
5721
5be9ed8d 5722 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
b8ff05a9
DM		 5723 if (!adapter->l2t) {
5724 /* We tolerate a lack of L2T, giving up some functionality */
5725 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5726 adapter->params.offload = 0;
5727 }
5728
778e1cdd
KC		 5729 adapter->mps_encap = kvcalloc(adapter->params.arch.mps_tcam_size,
5730 sizeof(struct mps_encap_entry),
0e249898
AV		 5731 GFP_KERNEL);
5732 if (!adapter->mps_encap)
5733 dev_warn(&pdev->dev, "could not allocate MPS Encap entries, continuing\n");
5734
b5a02f50 5735#if IS_ENABLED(CONFIG_IPV6)
e8d45292 5736 if (chip_ver <= CHELSIO_T5 &&
eb72f74f
HS		 5737 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5738 /* CLIP functionality is not present in hardware,
5739 * hence disable all offload features
b5a02f50
AB		 5740 */
5741 dev_warn(&pdev->dev,
eb72f74f 5742 "CLIP not enabled in hardware, continuing\n");
b5a02f50 5743 adapter->params.offload = 0;
eb72f74f
HS		 5744 } else {
5745 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5746 adapter->clipt_end);
5747 if (!adapter->clipt) {
5748 /* We tolerate a lack of clip_table, giving up
5749 * some functionality
5750 */
5751 dev_warn(&pdev->dev,
5752 "could not allocate Clip table, continuing\n");
5753 adapter->params.offload = 0;
5754 }
b5a02f50
AB		 5755 }
5756#endif
b72a32da
RL		 5757
5758 for_each_port(adapter, i) {
5759 pi = adap2pinfo(adapter, i);
5760 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5761 if (!pi->sched_tbl)
5762 dev_warn(&pdev->dev,
5763 "could not activate scheduling on port %d\n",
5764 i);
5765 }
5766
578b46b9 5767 if (tid_init(&adapter->tids) < 0) {
b8ff05a9
DM		 5768 dev_warn(&pdev->dev, "could not allocate TID table, "
5769 "continuing\n");
5770 adapter->params.offload = 0;
d8931847 5771 } else {
45da1ca2 5772 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
d8931847
RL		 5773 if (!adapter->tc_u32)
5774 dev_warn(&pdev->dev,
5775 "could not offload tc u32, continuing\n");
62488e4b 5776
79e6d46a
KS		 5777 if (cxgb4_init_tc_flower(adapter))
5778 dev_warn(&pdev->dev,
5779 "could not offload tc flower, continuing\n");
b8ff05a9
DM		 5780 }
5781
5c31254e 5782 if (is_offload(adapter) || is_hashfilter(adapter)) {
9a1bb9f6
HS		 5783 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5784 u32 hash_base, hash_reg;
5785
dfecc759 5786 if (chip_ver <= CHELSIO_T5) {
9a1bb9f6
HS		 5787 hash_reg = LE_DB_TID_HASHBASE_A;
5788 hash_base = t4_read_reg(adapter, hash_reg);
5789 adapter->tids.hash_base = hash_base / 4;
5790 } else {
5791 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5792 hash_base = t4_read_reg(adapter, hash_reg);
5793 adapter->tids.hash_base = hash_base;
5794 }
5795 }
5796 }
5797
f7cabcdd
DM		 5798 /* See what interrupts we'll be using */
5799 if (msi > 1 && enable_msix(adapter) == 0)
5800 adapter->flags |= USING_MSIX;
94cdb8bb 5801 else if (msi > 0 && pci_enable_msi(pdev) == 0) {
f7cabcdd 5802 adapter->flags |= USING_MSI;
94cdb8bb
HS		 5803 if (msi > 1)
5804 free_msix_info(adapter);
5805 }
f7cabcdd 5806
547fd272 5807 /* check for PCI Express bandwidth capabiltites */
57d12fc6 5808 pcie_print_link_status(pdev);
547fd272 5809
671b0060
DM		 5810 err = init_rss(adapter);
5811 if (err)
5812 goto out_free_dev;
5813
843bd7db
AV		 5814 err = setup_fw_sge_queues(adapter);
5815 if (err) {
5816 dev_err(adapter->pdev_dev,
5817 "FW sge queue allocation failed, err %d", err);
5818 goto out_free_dev;
5819 }
5820
0eaec62a 5821fw_attach_fail:
b8ff05a9
DM		 5822 /*
5823 * The card is now ready to go. If any errors occur during device
5824 * registration we do not fail the whole card but rather proceed only
5825 * with the ports we manage to register successfully. However we must
5826 * register at least one net device.
5827 */
5828 for_each_port(adapter, i) {
a57cabe0 5829 pi = adap2pinfo(adapter, i);
d2a007ab 5830 adapter->port[i]->dev_port = pi->lport;
a57cabe0
DM		 5831 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5832 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5833
b1a73af9
SM		 5834 netif_carrier_off(adapter->port[i]);
5835
b8ff05a9
DM		 5836 err = register_netdev(adapter->port[i]);
5837 if (err)
b1a3c2b6 5838 break;
b1a3c2b6
DM		 5839 adapter->chan_map[pi->tx_chan] = i;
5840 print_port_info(adapter->port[i]);
b8ff05a9 5841 }
b1a3c2b6 5842 if (i == 0) {
b8ff05a9
DM		 5843 dev_err(&pdev->dev, "could not register any net devices\n");
5844 goto out_free_dev;
5845 }
b1a3c2b6
DM		 5846 if (err) {
5847 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5848 err = 0;
6403eab1 5849 }
b8ff05a9
DM		 5850
5851 if (cxgb4_debugfs_root) {
5852 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5853 cxgb4_debugfs_root);
5854 setup_debugfs(adapter);
5855 }
5856
6482aa7c
DLR		 5857 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5858 pdev->needs_freset = 1;
5859
0fbc81b3
HS		 5860 if (is_uld(adapter)) {
5861 mutex_lock(&uld_mutex);
5862 list_add_tail(&adapter->list_node, &adapter_list);
5863 mutex_unlock(&uld_mutex);
5864 }
b8ff05a9 5865
9c33e420
AG		 5866 if (!is_t4(adapter->params.chip))
5867 cxgb4_ptp_init(adapter);
5868
ebcd210e 5869 if (IS_REACHABLE(CONFIG_THERMAL) &&
e70a57fa 5870 !is_t4(adapter->params.chip) && (adapter->flags & FW_OK))
b1871915 5871 cxgb4_thermal_init(adapter);
b1871915 5872
0de72738 5873 print_adapter_info(adapter);
7829451c 5874 return 0;
0de72738 5875
b8ff05a9 5876 out_free_dev:
843bd7db 5877 t4_free_sge_resources(adapter);
06546391 5878 free_some_resources(adapter);
94cdb8bb
HS		 5879 if (adapter->flags & USING_MSIX)
5880 free_msix_info(adapter);
0fbc81b3
HS		 5881 if (adapter->num_uld || adapter->num_ofld_uld)
5882 t4_uld_mem_free(adapter);
b8ff05a9 5883 out_unmap_bar:
d14807dd 5884 if (!is_t4(adapter->params.chip))
22adfe0a 5885 iounmap(adapter->bar2);
b8ff05a9 5886 out_free_adapter:
29aaee65
AB		 5887 if (adapter->workq)
5888 destroy_workqueue(adapter->workq);
5889
7f080c3f 5890 kfree(adapter->mbox_log);
b8ff05a9 5891 kfree(adapter);
d6ce2628
HS		 5892 out_unmap_bar0:
5893 iounmap(regs);
b8ff05a9
DM		 5894 out_disable_device:
5895 pci_disable_pcie_error_reporting(pdev);
5896 pci_disable_device(pdev);
5897 out_release_regions:
5898 pci_release_regions(pdev);
b8ff05a9
DM		 5899 return err;
5900}
5901
91744948 5902static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 5903{
5904 struct adapter *adapter = pci_get_drvdata(pdev);
b539ea60 5905 struct hash_mac_addr *entry, *tmp;
b8ff05a9 5906
7829451c
HS		 5907 if (!adapter) {
5908 pci_release_regions(pdev);
5909 return;
5910 }
636f9d37 5911
e1f6198e
GG		 5912 adapter->flags |= SHUTTING_DOWN;
5913
7829451c 5914 if (adapter->pf == 4) {
b8ff05a9
DM		 5915 int i;
5916
29aaee65
AB		 5917 /* Tear down per-adapter Work Queue first since it can contain
5918 * references to our adapter data structure.
5919 */
5920 destroy_workqueue(adapter->workq);
5921
6a146f3a 5922 if (is_uld(adapter)) {
b8ff05a9 5923 detach_ulds(adapter);
6a146f3a
GP		 5924 t4_uld_clean_up(adapter);
5925 }
b8ff05a9 5926
8b4e6b3c
AV		 5927 adap_free_hma_mem(adapter);
5928
b37987e8
HS		 5929 disable_interrupts(adapter);
5930
b8ff05a9 5931 for_each_port(adapter, i)
8f3a7676 5932 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 5933 unregister_netdev(adapter->port[i]);
5934
9f16dc2e 5935 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 5936
9c33e420
AG		 5937 if (!is_t4(adapter->params.chip))
5938 cxgb4_ptp_stop(adapter);
ebcd210e 5939 if (IS_REACHABLE(CONFIG_THERMAL))
e70a57fa 5940 cxgb4_thermal_remove(adapter);
9c33e420 5941
f2b7e78d
VP		 5942 /* If we allocated filters, free up state associated with any
5943 * valid filters ...
5944 */
578b46b9 5945 clear_all_filters(adapter);
f2b7e78d 5946
aaefae9b
DM		 5947 if (adapter->flags & FULL_INIT_DONE)
5948 cxgb_down(adapter);
b8ff05a9 5949
94cdb8bb
HS		 5950 if (adapter->flags & USING_MSIX)
5951 free_msix_info(adapter);
0fbc81b3
HS		 5952 if (adapter->num_uld || adapter->num_ofld_uld)
5953 t4_uld_mem_free(adapter);
06546391 5954 free_some_resources(adapter);
b539ea60
AV		 5955 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
5956 list) {
5957 list_del(&entry->list);
5958 kfree(entry);
5959 }
5960
b5a02f50
AB		 5961#if IS_ENABLED(CONFIG_IPV6)
5962 t4_cleanup_clip_tbl(adapter);
5963#endif
d14807dd 5964 if (!is_t4(adapter->params.chip))
22adfe0a 5965 iounmap(adapter->bar2);
7829451c
HS		 5966 }
5967#ifdef CONFIG_PCI_IOV
5968 else {
baf50868 5969 cxgb4_iov_configure(adapter->pdev, 0);
7829451c
HS		 5970 }
5971#endif
c4e43e14
GG		 5972 iounmap(adapter->regs);
5973 pci_disable_pcie_error_reporting(pdev);
5974 if ((adapter->flags & DEV_ENABLED)) {
5975 pci_disable_device(pdev);
5976 adapter->flags &= ~DEV_ENABLED;
5977 }
5978 pci_release_regions(pdev);
5979 kfree(adapter->mbox_log);
5980 synchronize_rcu();
5981 kfree(adapter);
b8ff05a9
DM		 5982}
5983
0fbc81b3
HS		 5984/* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
5985 * delivery. This is essentially a stripped down version of the PCI remove()
5986 * function where we do the minimal amount of work necessary to shutdown any
5987 * further activity.
5988 */
5989static void shutdown_one(struct pci_dev *pdev)
5990{
5991 struct adapter *adapter = pci_get_drvdata(pdev);
5992
5993 /* As with remove_one() above (see extended comment), we only want do
5994 * do cleanup on PCI Devices which went all the way through init_one()
5995 * ...
5996 */
5997 if (!adapter) {
5998 pci_release_regions(pdev);
5999 return;
6000 }
6001
e1f6198e
GG		 6002 adapter->flags |= SHUTTING_DOWN;
6003
0fbc81b3
HS		 6004 if (adapter->pf == 4) {
6005 int i;
6006
6007 for_each_port(adapter, i)
6008 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6009 cxgb_close(adapter->port[i]);
6010
6a146f3a
GP		 6011 if (is_uld(adapter)) {
6012 detach_ulds(adapter);
6013 t4_uld_clean_up(adapter);
6014 }
6015
0fbc81b3
HS		 6016 disable_interrupts(adapter);
6017 disable_msi(adapter);
6018
6019 t4_sge_stop(adapter);
6020 if (adapter->flags & FW_OK)
6021 t4_fw_bye(adapter, adapter->mbox);
6022 }
0fbc81b3
HS		 6023}
6024
b8ff05a9
DM		 6025static struct pci_driver cxgb4_driver = {
6026 .name = KBUILD_MODNAME,
6027 .id_table = cxgb4_pci_tbl,
6028 .probe = init_one,
91744948 6029 .remove = remove_one,
0fbc81b3 6030 .shutdown = shutdown_one,
b6244201
HS		 6031#ifdef CONFIG_PCI_IOV
6032 .sriov_configure = cxgb4_iov_configure,
6033#endif
204dc3c0 6034 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 6035};
6036
6037static int __init cxgb4_init_module(void)
6038{
6039 int ret;
6040
6041 /* Debugfs support is optional, just warn if this fails */
6042 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6043 if (!cxgb4_debugfs_root)
428ac43f 6044 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 6045
6046 ret = pci_register_driver(&cxgb4_driver);
29aaee65 6047 if (ret < 0)
b8ff05a9 6048 debugfs_remove(cxgb4_debugfs_root);
01bcca68 6049
1bb60376 6050#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 6051 if (!inet6addr_registered) {
6052 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6053 inet6addr_registered = true;
6054 }
1bb60376 6055#endif
01bcca68 6056
b8ff05a9
DM		 6057 return ret;
6058}
6059
6060static void __exit cxgb4_cleanup_module(void)
6061{
1bb60376 6062#if IS_ENABLED(CONFIG_IPV6)
1793c798 6063 if (inet6addr_registered) {
b5a02f50
AB		 6064 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6065 inet6addr_registered = false;
6066 }
1bb60376 6067#endif
b8ff05a9
DM		 6068 pci_unregister_driver(&cxgb4_driver);
6069 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
6070}
6071
6072module_init(cxgb4_init_module);
6073module_exit(cxgb4_cleanup_module);
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