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b8ff05a9 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
b72a32da | 4 | * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. |
b8ff05a9 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
36 | ||
37 | #include <linux/bitmap.h> | |
38 | #include <linux/crc32.h> | |
39 | #include <linux/ctype.h> | |
40 | #include <linux/debugfs.h> | |
41 | #include <linux/err.h> | |
42 | #include <linux/etherdevice.h> | |
43 | #include <linux/firmware.h> | |
01789349 | 44 | #include <linux/if.h> |
b8ff05a9 DM |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/init.h> | |
47 | #include <linux/log2.h> | |
48 | #include <linux/mdio.h> | |
49 | #include <linux/module.h> | |
50 | #include <linux/moduleparam.h> | |
51 | #include <linux/mutex.h> | |
52 | #include <linux/netdevice.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/aer.h> | |
55 | #include <linux/rtnetlink.h> | |
56 | #include <linux/sched.h> | |
57 | #include <linux/seq_file.h> | |
58 | #include <linux/sockios.h> | |
59 | #include <linux/vmalloc.h> | |
60 | #include <linux/workqueue.h> | |
61 | #include <net/neighbour.h> | |
62 | #include <net/netevent.h> | |
01bcca68 | 63 | #include <net/addrconf.h> |
1ef8019b | 64 | #include <net/bonding.h> |
7c0f6ba6 | 65 | #include <linux/uaccess.h> |
c5a8c0f3 | 66 | #include <linux/crash_dump.h> |
846eac3f | 67 | #include <net/udp_tunnel.h> |
b8ff05a9 DM |
68 | |
69 | #include "cxgb4.h" | |
d57fd6ca | 70 | #include "cxgb4_filter.h" |
b8ff05a9 | 71 | #include "t4_regs.h" |
f612b815 | 72 | #include "t4_values.h" |
b8ff05a9 DM |
73 | #include "t4_msg.h" |
74 | #include "t4fw_api.h" | |
cd6c2f12 | 75 | #include "t4fw_version.h" |
688848b1 | 76 | #include "cxgb4_dcb.h" |
c68644ef | 77 | #include "srq.h" |
fd88b31a | 78 | #include "cxgb4_debugfs.h" |
b5a02f50 | 79 | #include "clip_tbl.h" |
b8ff05a9 | 80 | #include "l2t.h" |
3bdb376e | 81 | #include "smt.h" |
b72a32da | 82 | #include "sched.h" |
d8931847 | 83 | #include "cxgb4_tc_u32.h" |
6a345b3d | 84 | #include "cxgb4_tc_flower.h" |
a4569504 | 85 | #include "cxgb4_ptp.h" |
ad75b7d3 | 86 | #include "cxgb4_cudbg.h" |
b8ff05a9 | 87 | |
812034f1 HS |
88 | char cxgb4_driver_name[] = KBUILD_MODNAME; |
89 | ||
01bcca68 VP |
90 | #ifdef DRV_VERSION |
91 | #undef DRV_VERSION | |
92 | #endif | |
3a7f8554 | 93 | #define DRV_VERSION "2.0.0-ko" |
812034f1 | 94 | const char cxgb4_driver_version[] = DRV_VERSION; |
52a5f846 | 95 | #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" |
b8ff05a9 | 96 | |
b8ff05a9 DM |
97 | #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ |
98 | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ | |
99 | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) | |
100 | ||
3fedeab1 HS |
101 | /* Macros needed to support the PCI Device ID Table ... |
102 | */ | |
103 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ | |
768ffc66 | 104 | static const struct pci_device_id cxgb4_pci_tbl[] = { |
baf50868 GG |
105 | #define CXGB4_UNIFIED_PF 0x4 |
106 | ||
107 | #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF | |
b8ff05a9 | 108 | |
3fedeab1 HS |
109 | /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is |
110 | * called for both. | |
111 | */ | |
112 | #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 | |
113 | ||
114 | #define CH_PCI_ID_TABLE_ENTRY(devid) \ | |
baf50868 | 115 | {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF} |
3fedeab1 HS |
116 | |
117 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ | |
118 | { 0, } \ | |
119 | } | |
120 | ||
121 | #include "t4_pci_id_tbl.h" | |
b8ff05a9 | 122 | |
16e47624 | 123 | #define FW4_FNAME "cxgb4/t4fw.bin" |
0a57a536 | 124 | #define FW5_FNAME "cxgb4/t5fw.bin" |
3ccc6cf7 | 125 | #define FW6_FNAME "cxgb4/t6fw.bin" |
16e47624 | 126 | #define FW4_CFNAME "cxgb4/t4-config.txt" |
0a57a536 | 127 | #define FW5_CFNAME "cxgb4/t5-config.txt" |
3ccc6cf7 | 128 | #define FW6_CFNAME "cxgb4/t6-config.txt" |
01b69614 HS |
129 | #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" |
130 | #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" | |
131 | #define PHY_AQ1202_DEVICEID 0x4409 | |
132 | #define PHY_BCM84834_DEVICEID 0x4486 | |
b8ff05a9 DM |
133 | |
134 | MODULE_DESCRIPTION(DRV_DESC); | |
135 | MODULE_AUTHOR("Chelsio Communications"); | |
136 | MODULE_LICENSE("Dual BSD/GPL"); | |
137 | MODULE_VERSION(DRV_VERSION); | |
138 | MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); | |
16e47624 | 139 | MODULE_FIRMWARE(FW4_FNAME); |
0a57a536 | 140 | MODULE_FIRMWARE(FW5_FNAME); |
52a5f846 | 141 | MODULE_FIRMWARE(FW6_FNAME); |
b8ff05a9 | 142 | |
b8ff05a9 DM |
143 | /* |
144 | * The driver uses the best interrupt scheme available on a platform in the | |
145 | * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which | |
146 | * of these schemes the driver may consider as follows: | |
147 | * | |
148 | * msi = 2: choose from among all three options | |
149 | * msi = 1: only consider MSI and INTx interrupts | |
150 | * msi = 0: force INTx interrupts | |
151 | */ | |
152 | static int msi = 2; | |
153 | ||
154 | module_param(msi, int, 0644); | |
155 | MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); | |
156 | ||
636f9d37 VP |
157 | /* |
158 | * Normally we tell the chip to deliver Ingress Packets into our DMA buffers | |
159 | * offset by 2 bytes in order to have the IP headers line up on 4-byte | |
160 | * boundaries. This is a requirement for many architectures which will throw | |
161 | * a machine check fault if an attempt is made to access one of the 4-byte IP | |
162 | * header fields on a non-4-byte boundary. And it's a major performance issue | |
163 | * even on some architectures which allow it like some implementations of the | |
164 | * x86 ISA. However, some architectures don't mind this and for some very | |
165 | * edge-case performance sensitive applications (like forwarding large volumes | |
166 | * of small packets), setting this DMA offset to 0 will decrease the number of | |
167 | * PCI-E Bus transfers enough to measurably affect performance. | |
168 | */ | |
169 | static int rx_dma_offset = 2; | |
170 | ||
688848b1 AB |
171 | /* TX Queue select used to determine what algorithm to use for selecting TX |
172 | * queue. Select between the kernel provided function (select_queue=0) or user | |
173 | * cxgb_select_queue function (select_queue=1) | |
174 | * | |
175 | * Default: select_queue=0 | |
176 | */ | |
177 | static int select_queue; | |
178 | module_param(select_queue, int, 0644); | |
179 | MODULE_PARM_DESC(select_queue, | |
180 | "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); | |
181 | ||
b8ff05a9 DM |
182 | static struct dentry *cxgb4_debugfs_root; |
183 | ||
94cdb8bb HS |
184 | LIST_HEAD(adapter_list); |
185 | DEFINE_MUTEX(uld_mutex); | |
b8ff05a9 DM |
186 | |
187 | static void link_report(struct net_device *dev) | |
188 | { | |
189 | if (!netif_carrier_ok(dev)) | |
190 | netdev_info(dev, "link down\n"); | |
191 | else { | |
192 | static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; | |
193 | ||
85412255 | 194 | const char *s; |
b8ff05a9 DM |
195 | const struct port_info *p = netdev_priv(dev); |
196 | ||
197 | switch (p->link_cfg.speed) { | |
5e78f7fd GG |
198 | case 100: |
199 | s = "100Mbps"; | |
b8ff05a9 | 200 | break; |
e8b39015 | 201 | case 1000: |
5e78f7fd | 202 | s = "1Gbps"; |
b8ff05a9 | 203 | break; |
5e78f7fd GG |
204 | case 10000: |
205 | s = "10Gbps"; | |
206 | break; | |
207 | case 25000: | |
208 | s = "25Gbps"; | |
b8ff05a9 | 209 | break; |
e8b39015 | 210 | case 40000: |
72aca4bf KS |
211 | s = "40Gbps"; |
212 | break; | |
7cbe543c GG |
213 | case 50000: |
214 | s = "50Gbps"; | |
215 | break; | |
5e78f7fd GG |
216 | case 100000: |
217 | s = "100Gbps"; | |
218 | break; | |
85412255 HS |
219 | default: |
220 | pr_info("%s: unsupported speed: %d\n", | |
221 | dev->name, p->link_cfg.speed); | |
222 | return; | |
b8ff05a9 DM |
223 | } |
224 | ||
225 | netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, | |
226 | fc[p->link_cfg.fc]); | |
227 | } | |
228 | } | |
229 | ||
688848b1 AB |
230 | #ifdef CONFIG_CHELSIO_T4_DCB |
231 | /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ | |
232 | static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) | |
233 | { | |
234 | struct port_info *pi = netdev_priv(dev); | |
235 | struct adapter *adap = pi->adapter; | |
236 | struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; | |
237 | int i; | |
238 | ||
239 | /* We use a simple mapping of Port TX Queue Index to DCB | |
240 | * Priority when we're enabling DCB. | |
241 | */ | |
242 | for (i = 0; i < pi->nqsets; i++, txq++) { | |
243 | u32 name, value; | |
244 | int err; | |
245 | ||
5167865a HS |
246 | name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
247 | FW_PARAMS_PARAM_X_V( | |
248 | FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | | |
249 | FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); | |
688848b1 AB |
250 | value = enable ? i : 0xffffffff; |
251 | ||
252 | /* Since we can be called while atomic (from "interrupt | |
253 | * level") we need to issue the Set Parameters Commannd | |
254 | * without sleeping (timeout < 0). | |
255 | */ | |
b2612722 | 256 | err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, |
01b69614 HS |
257 | &name, &value, |
258 | -FW_CMD_MAX_TIMEOUT); | |
688848b1 AB |
259 | |
260 | if (err) | |
261 | dev_err(adap->pdev_dev, | |
262 | "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", | |
263 | enable ? "set" : "unset", pi->port_id, i, -err); | |
10b00466 | 264 | else |
5ce36338 | 265 | txq->dcb_prio = enable ? value : 0; |
688848b1 AB |
266 | } |
267 | } | |
688848b1 | 268 | |
ebddd97a | 269 | int cxgb4_dcb_enabled(const struct net_device *dev) |
218d48e7 | 270 | { |
218d48e7 HS |
271 | struct port_info *pi = netdev_priv(dev); |
272 | ||
273 | if (!pi->dcb.enabled) | |
274 | return 0; | |
275 | ||
276 | return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || | |
277 | (pi->dcb.state == CXGB4_DCB_STATE_HOST)); | |
218d48e7 | 278 | } |
7c70c4f8 | 279 | #endif /* CONFIG_CHELSIO_T4_DCB */ |
218d48e7 | 280 | |
b8ff05a9 DM |
281 | void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) |
282 | { | |
283 | struct net_device *dev = adapter->port[port_id]; | |
284 | ||
285 | /* Skip changes from disabled ports. */ | |
286 | if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { | |
287 | if (link_stat) | |
288 | netif_carrier_on(dev); | |
688848b1 AB |
289 | else { |
290 | #ifdef CONFIG_CHELSIO_T4_DCB | |
218d48e7 | 291 | if (cxgb4_dcb_enabled(dev)) { |
ba581f77 | 292 | cxgb4_dcb_reset(dev); |
218d48e7 HS |
293 | dcb_tx_queue_prio_enable(dev, false); |
294 | } | |
688848b1 | 295 | #endif /* CONFIG_CHELSIO_T4_DCB */ |
b8ff05a9 | 296 | netif_carrier_off(dev); |
688848b1 | 297 | } |
b8ff05a9 DM |
298 | |
299 | link_report(dev); | |
300 | } | |
301 | } | |
302 | ||
8156b0ba | 303 | void t4_os_portmod_changed(struct adapter *adap, int port_id) |
b8ff05a9 DM |
304 | { |
305 | static const char *mod_str[] = { | |
a0881cab | 306 | NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" |
b8ff05a9 DM |
307 | }; |
308 | ||
8156b0ba GG |
309 | struct net_device *dev = adap->port[port_id]; |
310 | struct port_info *pi = netdev_priv(dev); | |
b8ff05a9 DM |
311 | |
312 | if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) | |
313 | netdev_info(dev, "port module unplugged\n"); | |
a0881cab | 314 | else if (pi->mod_type < ARRAY_SIZE(mod_str)) |
b8ff05a9 | 315 | netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); |
be81a2de HS |
316 | else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) |
317 | netdev_info(dev, "%s: unsupported port module inserted\n", | |
318 | dev->name); | |
319 | else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) | |
320 | netdev_info(dev, "%s: unknown port module inserted\n", | |
321 | dev->name); | |
322 | else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) | |
323 | netdev_info(dev, "%s: transceiver module error\n", dev->name); | |
324 | else | |
325 | netdev_info(dev, "%s: unknown module type %d inserted\n", | |
326 | dev->name, pi->mod_type); | |
8156b0ba GG |
327 | |
328 | /* If the interface is running, then we'll need any "sticky" Link | |
329 | * Parameters redone with a new Transceiver Module. | |
330 | */ | |
331 | pi->link_cfg.redo_l1cfg = netif_running(dev); | |
b8ff05a9 DM |
332 | } |
333 | ||
fc08a01a HS |
334 | int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ |
335 | module_param(dbfifo_int_thresh, int, 0644); | |
336 | MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); | |
337 | ||
b8ff05a9 | 338 | /* |
fc08a01a | 339 | * usecs to sleep while draining the dbfifo |
b8ff05a9 | 340 | */ |
fc08a01a HS |
341 | static int dbfifo_drain_delay = 1000; |
342 | module_param(dbfifo_drain_delay, int, 0644); | |
343 | MODULE_PARM_DESC(dbfifo_drain_delay, | |
344 | "usecs to sleep while draining the dbfifo"); | |
345 | ||
346 | static inline int cxgb4_set_addr_hash(struct port_info *pi) | |
b8ff05a9 | 347 | { |
fc08a01a HS |
348 | struct adapter *adap = pi->adapter; |
349 | u64 vec = 0; | |
350 | bool ucast = false; | |
351 | struct hash_mac_addr *entry; | |
352 | ||
353 | /* Calculate the hash vector for the updated list and program it */ | |
354 | list_for_each_entry(entry, &adap->mac_hlist, list) { | |
355 | ucast |= is_unicast_ether_addr(entry->addr); | |
356 | vec |= (1ULL << hash_mac_addr(entry->addr)); | |
357 | } | |
358 | return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, | |
359 | vec, false); | |
360 | } | |
361 | ||
362 | static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) | |
363 | { | |
364 | struct port_info *pi = netdev_priv(netdev); | |
365 | struct adapter *adap = pi->adapter; | |
366 | int ret; | |
b8ff05a9 DM |
367 | u64 mhash = 0; |
368 | u64 uhash = 0; | |
fc08a01a HS |
369 | bool free = false; |
370 | bool ucast = is_unicast_ether_addr(mac_addr); | |
371 | const u8 *maclist[1] = {mac_addr}; | |
372 | struct hash_mac_addr *new_entry; | |
373 | ||
374 | ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist, | |
375 | NULL, ucast ? &uhash : &mhash, false); | |
376 | if (ret < 0) | |
377 | goto out; | |
378 | /* if hash != 0, then add the addr to hash addr list | |
379 | * so on the end we will calculate the hash for the | |
380 | * list and program it | |
381 | */ | |
382 | if (uhash || mhash) { | |
383 | new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); | |
384 | if (!new_entry) | |
385 | return -ENOMEM; | |
386 | ether_addr_copy(new_entry->addr, mac_addr); | |
387 | list_add_tail(&new_entry->list, &adap->mac_hlist); | |
388 | ret = cxgb4_set_addr_hash(pi); | |
b8ff05a9 | 389 | } |
fc08a01a HS |
390 | out: |
391 | return ret < 0 ? ret : 0; | |
392 | } | |
b8ff05a9 | 393 | |
fc08a01a HS |
394 | static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) |
395 | { | |
396 | struct port_info *pi = netdev_priv(netdev); | |
397 | struct adapter *adap = pi->adapter; | |
398 | int ret; | |
399 | const u8 *maclist[1] = {mac_addr}; | |
400 | struct hash_mac_addr *entry, *tmp; | |
b8ff05a9 | 401 | |
fc08a01a HS |
402 | /* If the MAC address to be removed is in the hash addr |
403 | * list, delete it from the list and update hash vector | |
404 | */ | |
405 | list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { | |
406 | if (ether_addr_equal(entry->addr, mac_addr)) { | |
407 | list_del(&entry->list); | |
408 | kfree(entry); | |
409 | return cxgb4_set_addr_hash(pi); | |
b8ff05a9 DM |
410 | } |
411 | } | |
412 | ||
fc08a01a HS |
413 | ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false); |
414 | return ret < 0 ? -EINVAL : 0; | |
b8ff05a9 DM |
415 | } |
416 | ||
417 | /* | |
418 | * Set Rx properties of a port, such as promiscruity, address filters, and MTU. | |
419 | * If @mtu is -1 it is left unchanged. | |
420 | */ | |
421 | static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) | |
422 | { | |
b8ff05a9 | 423 | struct port_info *pi = netdev_priv(dev); |
fc08a01a | 424 | struct adapter *adapter = pi->adapter; |
b8ff05a9 | 425 | |
d01f7abc HS |
426 | __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); |
427 | __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); | |
fc08a01a HS |
428 | |
429 | return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, | |
430 | (dev->flags & IFF_PROMISC) ? 1 : 0, | |
431 | (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, | |
432 | sleep_ok); | |
b8ff05a9 DM |
433 | } |
434 | ||
435 | /** | |
436 | * link_start - enable a port | |
437 | * @dev: the port to enable | |
438 | * | |
439 | * Performs the MAC and PHY actions needed to enable a port. | |
440 | */ | |
441 | static int link_start(struct net_device *dev) | |
442 | { | |
443 | int ret; | |
444 | struct port_info *pi = netdev_priv(dev); | |
b2612722 | 445 | unsigned int mb = pi->adapter->pf; |
b8ff05a9 DM |
446 | |
447 | /* | |
448 | * We do not set address filters and promiscuity here, the stack does | |
449 | * that step explicitly. | |
450 | */ | |
060e0c75 | 451 | ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, |
f646968f | 452 | !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); |
b8ff05a9 | 453 | if (ret == 0) { |
060e0c75 | 454 | ret = t4_change_mac(pi->adapter, mb, pi->viid, |
b8ff05a9 | 455 | pi->xact_addr_filt, dev->dev_addr, true, |
b6bd29e7 | 456 | true); |
b8ff05a9 DM |
457 | if (ret >= 0) { |
458 | pi->xact_addr_filt = ret; | |
459 | ret = 0; | |
460 | } | |
461 | } | |
462 | if (ret == 0) | |
4036da90 | 463 | ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, |
060e0c75 | 464 | &pi->link_cfg); |
30f00847 AB |
465 | if (ret == 0) { |
466 | local_bh_disable(); | |
e2f4f4e9 | 467 | ret = t4_enable_pi_params(pi->adapter, mb, pi, true, |
688848b1 | 468 | true, CXGB4_DCB_ENABLED); |
30f00847 AB |
469 | local_bh_enable(); |
470 | } | |
688848b1 | 471 | |
b8ff05a9 DM |
472 | return ret; |
473 | } | |
474 | ||
688848b1 AB |
475 | #ifdef CONFIG_CHELSIO_T4_DCB |
476 | /* Handle a Data Center Bridging update message from the firmware. */ | |
477 | static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) | |
478 | { | |
2b5fb1f2 | 479 | int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); |
134491fd | 480 | struct net_device *dev = adap->port[adap->chan_map[port]]; |
688848b1 AB |
481 | int old_dcb_enabled = cxgb4_dcb_enabled(dev); |
482 | int new_dcb_enabled; | |
483 | ||
484 | cxgb4_dcb_handle_fw_update(adap, pcmd); | |
485 | new_dcb_enabled = cxgb4_dcb_enabled(dev); | |
486 | ||
487 | /* If the DCB has become enabled or disabled on the port then we're | |
488 | * going to need to set up/tear down DCB Priority parameters for the | |
489 | * TX Queues associated with the port. | |
490 | */ | |
491 | if (new_dcb_enabled != old_dcb_enabled) | |
492 | dcb_tx_queue_prio_enable(dev, new_dcb_enabled); | |
493 | } | |
494 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
495 | ||
f2b7e78d | 496 | /* Response queue handler for the FW event queue. |
b8ff05a9 DM |
497 | */ |
498 | static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, | |
499 | const struct pkt_gl *gl) | |
500 | { | |
501 | u8 opcode = ((const struct rss_header *)rsp)->opcode; | |
502 | ||
503 | rsp++; /* skip RSS header */ | |
b407a4a9 VP |
504 | |
505 | /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. | |
506 | */ | |
507 | if (unlikely(opcode == CPL_FW4_MSG && | |
508 | ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { | |
509 | rsp++; | |
510 | opcode = ((const struct rss_header *)rsp)->opcode; | |
511 | rsp++; | |
512 | if (opcode != CPL_SGE_EGR_UPDATE) { | |
513 | dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" | |
514 | , opcode); | |
515 | goto out; | |
516 | } | |
517 | } | |
518 | ||
b8ff05a9 DM |
519 | if (likely(opcode == CPL_SGE_EGR_UPDATE)) { |
520 | const struct cpl_sge_egr_update *p = (void *)rsp; | |
bdc590b9 | 521 | unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); |
e46dab4d | 522 | struct sge_txq *txq; |
b8ff05a9 | 523 | |
e46dab4d | 524 | txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; |
b8ff05a9 | 525 | txq->restarts++; |
ab677ff4 | 526 | if (txq->q_type == CXGB4_TXQ_ETH) { |
b8ff05a9 DM |
527 | struct sge_eth_txq *eq; |
528 | ||
529 | eq = container_of(txq, struct sge_eth_txq, q); | |
530 | netif_tx_wake_queue(eq->txq); | |
531 | } else { | |
ab677ff4 | 532 | struct sge_uld_txq *oq; |
b8ff05a9 | 533 | |
ab677ff4 | 534 | oq = container_of(txq, struct sge_uld_txq, q); |
b8ff05a9 DM |
535 | tasklet_schedule(&oq->qresume_tsk); |
536 | } | |
537 | } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { | |
538 | const struct cpl_fw6_msg *p = (void *)rsp; | |
539 | ||
688848b1 AB |
540 | #ifdef CONFIG_CHELSIO_T4_DCB |
541 | const struct fw_port_cmd *pcmd = (const void *)p->data; | |
e2ac9628 | 542 | unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); |
688848b1 | 543 | unsigned int action = |
2b5fb1f2 | 544 | FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); |
688848b1 AB |
545 | |
546 | if (cmd == FW_PORT_CMD && | |
c3168cab GG |
547 | (action == FW_PORT_ACTION_GET_PORT_INFO || |
548 | action == FW_PORT_ACTION_GET_PORT_INFO32)) { | |
2b5fb1f2 | 549 | int port = FW_PORT_CMD_PORTID_G( |
688848b1 | 550 | be32_to_cpu(pcmd->op_to_portid)); |
c3168cab GG |
551 | struct net_device *dev; |
552 | int dcbxdis, state_input; | |
553 | ||
554 | dev = q->adap->port[q->adap->chan_map[port]]; | |
555 | dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO | |
90d4c5bb GG |
556 | ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F) |
557 | : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32) | |
558 | & FW_PORT_CMD_DCBXDIS32_F)); | |
c3168cab GG |
559 | state_input = (dcbxdis |
560 | ? CXGB4_DCB_INPUT_FW_DISABLED | |
561 | : CXGB4_DCB_INPUT_FW_ENABLED); | |
688848b1 AB |
562 | |
563 | cxgb4_dcb_state_fsm(dev, state_input); | |
564 | } | |
565 | ||
566 | if (cmd == FW_PORT_CMD && | |
567 | action == FW_PORT_ACTION_L2_DCB_CFG) | |
568 | dcb_rpl(q->adap, pcmd); | |
569 | else | |
570 | #endif | |
571 | if (p->type == 0) | |
572 | t4_handle_fw_rpl(q->adap, p->data); | |
b8ff05a9 DM |
573 | } else if (opcode == CPL_L2T_WRITE_RPL) { |
574 | const struct cpl_l2t_write_rpl *p = (void *)rsp; | |
575 | ||
576 | do_l2t_write_rpl(q->adap, p); | |
3bdb376e KS |
577 | } else if (opcode == CPL_SMT_WRITE_RPL) { |
578 | const struct cpl_smt_write_rpl *p = (void *)rsp; | |
579 | ||
580 | do_smt_write_rpl(q->adap, p); | |
f2b7e78d VP |
581 | } else if (opcode == CPL_SET_TCB_RPL) { |
582 | const struct cpl_set_tcb_rpl *p = (void *)rsp; | |
583 | ||
584 | filter_rpl(q->adap, p); | |
12b276fb KS |
585 | } else if (opcode == CPL_ACT_OPEN_RPL) { |
586 | const struct cpl_act_open_rpl *p = (void *)rsp; | |
587 | ||
588 | hash_filter_rpl(q->adap, p); | |
3b0b3bee KS |
589 | } else if (opcode == CPL_ABORT_RPL_RSS) { |
590 | const struct cpl_abort_rpl_rss *p = (void *)rsp; | |
591 | ||
592 | hash_del_filter_rpl(q->adap, p); | |
c68644ef RR |
593 | } else if (opcode == CPL_SRQ_TABLE_RPL) { |
594 | const struct cpl_srq_table_rpl *p = (void *)rsp; | |
595 | ||
596 | do_srq_table_rpl(q->adap, p); | |
b8ff05a9 DM |
597 | } else |
598 | dev_err(q->adap->pdev_dev, | |
599 | "unexpected CPL %#x on FW event queue\n", opcode); | |
b407a4a9 | 600 | out: |
b8ff05a9 DM |
601 | return 0; |
602 | } | |
603 | ||
b8ff05a9 DM |
604 | static void disable_msi(struct adapter *adapter) |
605 | { | |
606 | if (adapter->flags & USING_MSIX) { | |
607 | pci_disable_msix(adapter->pdev); | |
608 | adapter->flags &= ~USING_MSIX; | |
609 | } else if (adapter->flags & USING_MSI) { | |
610 | pci_disable_msi(adapter->pdev); | |
611 | adapter->flags &= ~USING_MSI; | |
612 | } | |
613 | } | |
614 | ||
615 | /* | |
616 | * Interrupt handler for non-data events used with MSI-X. | |
617 | */ | |
618 | static irqreturn_t t4_nondata_intr(int irq, void *cookie) | |
619 | { | |
620 | struct adapter *adap = cookie; | |
0d804338 | 621 | u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); |
b8ff05a9 | 622 | |
0d804338 | 623 | if (v & PFSW_F) { |
b8ff05a9 | 624 | adap->swintr = 1; |
0d804338 | 625 | t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); |
b8ff05a9 | 626 | } |
c3c7b121 HS |
627 | if (adap->flags & MASTER_PF) |
628 | t4_slow_intr_handler(adap); | |
b8ff05a9 DM |
629 | return IRQ_HANDLED; |
630 | } | |
631 | ||
632 | /* | |
633 | * Name the MSI-X interrupts. | |
634 | */ | |
635 | static void name_msix_vecs(struct adapter *adap) | |
636 | { | |
ba27816c | 637 | int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); |
b8ff05a9 DM |
638 | |
639 | /* non-data interrupts */ | |
b1a3c2b6 | 640 | snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); |
b8ff05a9 DM |
641 | |
642 | /* FW events */ | |
b1a3c2b6 DM |
643 | snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", |
644 | adap->port[0]->name); | |
b8ff05a9 DM |
645 | |
646 | /* Ethernet queues */ | |
647 | for_each_port(adap, j) { | |
648 | struct net_device *d = adap->port[j]; | |
649 | const struct port_info *pi = netdev_priv(d); | |
650 | ||
ba27816c | 651 | for (i = 0; i < pi->nqsets; i++, msi_idx++) |
b8ff05a9 DM |
652 | snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", |
653 | d->name, i); | |
b8ff05a9 | 654 | } |
b8ff05a9 DM |
655 | } |
656 | ||
657 | static int request_msix_queue_irqs(struct adapter *adap) | |
658 | { | |
659 | struct sge *s = &adap->sge; | |
0fbc81b3 | 660 | int err, ethqidx; |
cf38be6d | 661 | int msi_index = 2; |
b8ff05a9 DM |
662 | |
663 | err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, | |
664 | adap->msix_info[1].desc, &s->fw_evtq); | |
665 | if (err) | |
666 | return err; | |
667 | ||
668 | for_each_ethrxq(s, ethqidx) { | |
404d9e3f VP |
669 | err = request_irq(adap->msix_info[msi_index].vec, |
670 | t4_sge_intr_msix, 0, | |
671 | adap->msix_info[msi_index].desc, | |
b8ff05a9 DM |
672 | &s->ethrxq[ethqidx].rspq); |
673 | if (err) | |
674 | goto unwind; | |
404d9e3f | 675 | msi_index++; |
b8ff05a9 | 676 | } |
b8ff05a9 DM |
677 | return 0; |
678 | ||
679 | unwind: | |
b8ff05a9 | 680 | while (--ethqidx >= 0) |
404d9e3f VP |
681 | free_irq(adap->msix_info[--msi_index].vec, |
682 | &s->ethrxq[ethqidx].rspq); | |
b8ff05a9 DM |
683 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); |
684 | return err; | |
685 | } | |
686 | ||
687 | static void free_msix_queue_irqs(struct adapter *adap) | |
688 | { | |
404d9e3f | 689 | int i, msi_index = 2; |
b8ff05a9 DM |
690 | struct sge *s = &adap->sge; |
691 | ||
692 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); | |
693 | for_each_ethrxq(s, i) | |
404d9e3f | 694 | free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); |
b8ff05a9 DM |
695 | } |
696 | ||
671b0060 | 697 | /** |
812034f1 | 698 | * cxgb4_write_rss - write the RSS table for a given port |
671b0060 DM |
699 | * @pi: the port |
700 | * @queues: array of queue indices for RSS | |
701 | * | |
702 | * Sets up the portion of the HW RSS table for the port's VI to distribute | |
703 | * packets to the Rx queues in @queues. | |
c035e183 | 704 | * Should never be called before setting up sge eth rx queues |
671b0060 | 705 | */ |
812034f1 | 706 | int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) |
671b0060 DM |
707 | { |
708 | u16 *rss; | |
709 | int i, err; | |
c035e183 HS |
710 | struct adapter *adapter = pi->adapter; |
711 | const struct sge_eth_rxq *rxq; | |
671b0060 | 712 | |
c035e183 | 713 | rxq = &adapter->sge.ethrxq[pi->first_qset]; |
6da2ec56 | 714 | rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL); |
671b0060 DM |
715 | if (!rss) |
716 | return -ENOMEM; | |
717 | ||
718 | /* map the queue indices to queue ids */ | |
719 | for (i = 0; i < pi->rss_size; i++, queues++) | |
c035e183 | 720 | rss[i] = rxq[*queues].rspq.abs_id; |
671b0060 | 721 | |
b2612722 | 722 | err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, |
060e0c75 | 723 | pi->rss_size, rss, pi->rss_size); |
c035e183 HS |
724 | /* If Tunnel All Lookup isn't specified in the global RSS |
725 | * Configuration, then we need to specify a default Ingress | |
726 | * Queue for any ingress packets which aren't hashed. We'll | |
727 | * use our first ingress queue ... | |
728 | */ | |
729 | if (!err) | |
730 | err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, | |
731 | FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | | |
732 | FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | | |
733 | FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | | |
734 | FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | | |
735 | FW_RSS_VI_CONFIG_CMD_UDPEN_F, | |
736 | rss[0]); | |
671b0060 DM |
737 | kfree(rss); |
738 | return err; | |
739 | } | |
740 | ||
b8ff05a9 DM |
741 | /** |
742 | * setup_rss - configure RSS | |
743 | * @adap: the adapter | |
744 | * | |
671b0060 | 745 | * Sets up RSS for each port. |
b8ff05a9 DM |
746 | */ |
747 | static int setup_rss(struct adapter *adap) | |
748 | { | |
c035e183 | 749 | int i, j, err; |
b8ff05a9 DM |
750 | |
751 | for_each_port(adap, i) { | |
752 | const struct port_info *pi = adap2pinfo(adap, i); | |
b8ff05a9 | 753 | |
c035e183 HS |
754 | /* Fill default values with equal distribution */ |
755 | for (j = 0; j < pi->rss_size; j++) | |
756 | pi->rss[j] = j % pi->nqsets; | |
757 | ||
812034f1 | 758 | err = cxgb4_write_rss(pi, pi->rss); |
b8ff05a9 DM |
759 | if (err) |
760 | return err; | |
761 | } | |
762 | return 0; | |
763 | } | |
764 | ||
e46dab4d DM |
765 | /* |
766 | * Return the channel of the ingress queue with the given qid. | |
767 | */ | |
768 | static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) | |
769 | { | |
770 | qid -= p->ingr_start; | |
771 | return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; | |
772 | } | |
773 | ||
b8ff05a9 DM |
774 | /* |
775 | * Wait until all NAPI handlers are descheduled. | |
776 | */ | |
777 | static void quiesce_rx(struct adapter *adap) | |
778 | { | |
779 | int i; | |
780 | ||
4b8e27a8 | 781 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
782 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
783 | ||
5226b791 | 784 | if (q && q->handler) |
b8ff05a9 DM |
785 | napi_disable(&q->napi); |
786 | } | |
787 | } | |
788 | ||
b37987e8 HS |
789 | /* Disable interrupt and napi handler */ |
790 | static void disable_interrupts(struct adapter *adap) | |
791 | { | |
792 | if (adap->flags & FULL_INIT_DONE) { | |
793 | t4_intr_disable(adap); | |
794 | if (adap->flags & USING_MSIX) { | |
795 | free_msix_queue_irqs(adap); | |
796 | free_irq(adap->msix_info[0].vec, adap); | |
797 | } else { | |
798 | free_irq(adap->pdev->irq, adap); | |
799 | } | |
800 | quiesce_rx(adap); | |
801 | } | |
802 | } | |
803 | ||
b8ff05a9 DM |
804 | /* |
805 | * Enable NAPI scheduling and interrupt generation for all Rx queues. | |
806 | */ | |
807 | static void enable_rx(struct adapter *adap) | |
808 | { | |
809 | int i; | |
810 | ||
4b8e27a8 | 811 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
812 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
813 | ||
814 | if (!q) | |
815 | continue; | |
5226b791 | 816 | if (q->handler) |
b8ff05a9 | 817 | napi_enable(&q->napi); |
5226b791 | 818 | |
b8ff05a9 | 819 | /* 0-increment GTS to start the timer and enable interrupts */ |
f612b815 HS |
820 | t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), |
821 | SEINTARM_V(q->intr_params) | | |
822 | INGRESSQID_V(q->cntxt_id)); | |
b8ff05a9 DM |
823 | } |
824 | } | |
825 | ||
1c6a5b0e | 826 | |
0fbc81b3 | 827 | static int setup_fw_sge_queues(struct adapter *adap) |
b8ff05a9 | 828 | { |
b8ff05a9 | 829 | struct sge *s = &adap->sge; |
0fbc81b3 | 830 | int err = 0; |
b8ff05a9 | 831 | |
4b8e27a8 HS |
832 | bitmap_zero(s->starving_fl, s->egr_sz); |
833 | bitmap_zero(s->txq_maperr, s->egr_sz); | |
b8ff05a9 DM |
834 | |
835 | if (adap->flags & USING_MSIX) | |
94cdb8bb | 836 | adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */ |
b8ff05a9 DM |
837 | else { |
838 | err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, | |
2337ba42 | 839 | NULL, NULL, NULL, -1); |
b8ff05a9 DM |
840 | if (err) |
841 | return err; | |
94cdb8bb | 842 | adap->msi_idx = -((int)s->intrq.abs_id + 1); |
b8ff05a9 DM |
843 | } |
844 | ||
845 | err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], | |
94cdb8bb | 846 | adap->msi_idx, NULL, fwevtq_handler, NULL, -1); |
0fbc81b3 HS |
847 | return err; |
848 | } | |
849 | ||
850 | /** | |
851 | * setup_sge_queues - configure SGE Tx/Rx/response queues | |
852 | * @adap: the adapter | |
853 | * | |
854 | * Determines how many sets of SGE queues to use and initializes them. | |
855 | * We support multiple queue sets per port if we have MSI-X, otherwise | |
856 | * just one queue set per port. | |
857 | */ | |
858 | static int setup_sge_queues(struct adapter *adap) | |
859 | { | |
860 | int err, i, j; | |
861 | struct sge *s = &adap->sge; | |
d427caee | 862 | struct sge_uld_rxq_info *rxq_info = NULL; |
0fbc81b3 | 863 | unsigned int cmplqid = 0; |
b8ff05a9 | 864 | |
d427caee GG |
865 | if (is_uld(adap)) |
866 | rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; | |
867 | ||
b8ff05a9 DM |
868 | for_each_port(adap, i) { |
869 | struct net_device *dev = adap->port[i]; | |
870 | struct port_info *pi = netdev_priv(dev); | |
871 | struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; | |
872 | struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; | |
873 | ||
874 | for (j = 0; j < pi->nqsets; j++, q++) { | |
94cdb8bb HS |
875 | if (adap->msi_idx > 0) |
876 | adap->msi_idx++; | |
b8ff05a9 | 877 | err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, |
94cdb8bb | 878 | adap->msi_idx, &q->fl, |
145ef8a5 | 879 | t4_ethrx_handler, |
2337ba42 | 880 | NULL, |
193c4c28 AV |
881 | t4_get_tp_ch_map(adap, |
882 | pi->tx_chan)); | |
b8ff05a9 DM |
883 | if (err) |
884 | goto freeout; | |
885 | q->rspq.idx = j; | |
886 | memset(&q->stats, 0, sizeof(q->stats)); | |
887 | } | |
888 | for (j = 0; j < pi->nqsets; j++, t++) { | |
889 | err = t4_sge_alloc_eth_txq(adap, t, dev, | |
890 | netdev_get_tx_queue(dev, j), | |
891 | s->fw_evtq.cntxt_id); | |
892 | if (err) | |
893 | goto freeout; | |
894 | } | |
895 | } | |
896 | ||
b8ff05a9 | 897 | for_each_port(adap, i) { |
0fbc81b3 | 898 | /* Note that cmplqid below is 0 if we don't |
b8ff05a9 DM |
899 | * have RDMA queues, and that's the right value. |
900 | */ | |
0fbc81b3 HS |
901 | if (rxq_info) |
902 | cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id; | |
903 | ||
b8ff05a9 | 904 | err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], |
0fbc81b3 | 905 | s->fw_evtq.cntxt_id, cmplqid); |
b8ff05a9 DM |
906 | if (err) |
907 | goto freeout; | |
908 | } | |
909 | ||
a4569504 AG |
910 | if (!is_t4(adap->params.chip)) { |
911 | err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0], | |
912 | netdev_get_tx_queue(adap->port[0], 0) | |
913 | , s->fw_evtq.cntxt_id); | |
914 | if (err) | |
915 | goto freeout; | |
916 | } | |
917 | ||
9bb59b96 | 918 | t4_write_reg(adap, is_t4(adap->params.chip) ? |
837e4a42 HS |
919 | MPS_TRC_RSS_CONTROL_A : |
920 | MPS_T5_TRC_RSS_CONTROL_A, | |
921 | RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | | |
922 | QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); | |
b8ff05a9 | 923 | return 0; |
0fbc81b3 | 924 | freeout: |
0eaec62a | 925 | dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err); |
0fbc81b3 HS |
926 | t4_free_sge_resources(adap); |
927 | return err; | |
b8ff05a9 DM |
928 | } |
929 | ||
688848b1 | 930 | static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, |
4f49dec9 AD |
931 | struct net_device *sb_dev, |
932 | select_queue_fallback_t fallback) | |
688848b1 AB |
933 | { |
934 | int txq; | |
935 | ||
936 | #ifdef CONFIG_CHELSIO_T4_DCB | |
937 | /* If a Data Center Bridging has been successfully negotiated on this | |
938 | * link then we'll use the skb's priority to map it to a TX Queue. | |
939 | * The skb's priority is determined via the VLAN Tag Priority Code | |
940 | * Point field. | |
941 | */ | |
85eacf3f | 942 | if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) { |
688848b1 AB |
943 | u16 vlan_tci; |
944 | int err; | |
945 | ||
946 | err = vlan_get_tag(skb, &vlan_tci); | |
947 | if (unlikely(err)) { | |
948 | if (net_ratelimit()) | |
949 | netdev_warn(dev, | |
950 | "TX Packet without VLAN Tag on DCB Link\n"); | |
951 | txq = 0; | |
952 | } else { | |
953 | txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; | |
84a200b3 VP |
954 | #ifdef CONFIG_CHELSIO_T4_FCOE |
955 | if (skb->protocol == htons(ETH_P_FCOE)) | |
956 | txq = skb->priority & 0x7; | |
957 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
688848b1 AB |
958 | } |
959 | return txq; | |
960 | } | |
961 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
962 | ||
963 | if (select_queue) { | |
964 | txq = (skb_rx_queue_recorded(skb) | |
965 | ? skb_get_rx_queue(skb) | |
966 | : smp_processor_id()); | |
967 | ||
968 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
969 | txq -= dev->real_num_tx_queues; | |
970 | ||
971 | return txq; | |
972 | } | |
973 | ||
8ec56fc3 | 974 | return fallback(dev, skb, NULL) % dev->real_num_tx_queues; |
688848b1 AB |
975 | } |
976 | ||
b8ff05a9 DM |
977 | static int closest_timer(const struct sge *s, int time) |
978 | { | |
979 | int i, delta, match = 0, min_delta = INT_MAX; | |
980 | ||
981 | for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { | |
982 | delta = time - s->timer_val[i]; | |
983 | if (delta < 0) | |
984 | delta = -delta; | |
985 | if (delta < min_delta) { | |
986 | min_delta = delta; | |
987 | match = i; | |
988 | } | |
989 | } | |
990 | return match; | |
991 | } | |
992 | ||
993 | static int closest_thres(const struct sge *s, int thres) | |
994 | { | |
995 | int i, delta, match = 0, min_delta = INT_MAX; | |
996 | ||
997 | for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { | |
998 | delta = thres - s->counter_val[i]; | |
999 | if (delta < 0) | |
1000 | delta = -delta; | |
1001 | if (delta < min_delta) { | |
1002 | min_delta = delta; | |
1003 | match = i; | |
1004 | } | |
1005 | } | |
1006 | return match; | |
1007 | } | |
1008 | ||
b8ff05a9 | 1009 | /** |
812034f1 | 1010 | * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters |
b8ff05a9 DM |
1011 | * @q: the Rx queue |
1012 | * @us: the hold-off time in us, or 0 to disable timer | |
1013 | * @cnt: the hold-off packet count, or 0 to disable counter | |
1014 | * | |
1015 | * Sets an Rx queue's interrupt hold-off time and packet count. At least | |
1016 | * one of the two needs to be enabled for the queue to generate interrupts. | |
1017 | */ | |
812034f1 HS |
1018 | int cxgb4_set_rspq_intr_params(struct sge_rspq *q, |
1019 | unsigned int us, unsigned int cnt) | |
b8ff05a9 | 1020 | { |
c887ad0e HS |
1021 | struct adapter *adap = q->adap; |
1022 | ||
b8ff05a9 DM |
1023 | if ((us | cnt) == 0) |
1024 | cnt = 1; | |
1025 | ||
1026 | if (cnt) { | |
1027 | int err; | |
1028 | u32 v, new_idx; | |
1029 | ||
1030 | new_idx = closest_thres(&adap->sge, cnt); | |
1031 | if (q->desc && q->pktcnt_idx != new_idx) { | |
1032 | /* the queue has already been created, update it */ | |
5167865a HS |
1033 | v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
1034 | FW_PARAMS_PARAM_X_V( | |
1035 | FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | | |
1036 | FW_PARAMS_PARAM_YZ_V(q->cntxt_id); | |
b2612722 HS |
1037 | err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, |
1038 | &v, &new_idx); | |
b8ff05a9 DM |
1039 | if (err) |
1040 | return err; | |
1041 | } | |
1042 | q->pktcnt_idx = new_idx; | |
1043 | } | |
1044 | ||
1045 | us = us == 0 ? 6 : closest_timer(&adap->sge, us); | |
1ecc7b7a | 1046 | q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); |
b8ff05a9 DM |
1047 | return 0; |
1048 | } | |
1049 | ||
c8f44aff | 1050 | static int cxgb_set_features(struct net_device *dev, netdev_features_t features) |
87b6cf51 | 1051 | { |
2ed28baa | 1052 | const struct port_info *pi = netdev_priv(dev); |
c8f44aff | 1053 | netdev_features_t changed = dev->features ^ features; |
19ecae2c | 1054 | int err; |
19ecae2c | 1055 | |
f646968f | 1056 | if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) |
2ed28baa | 1057 | return 0; |
19ecae2c | 1058 | |
b2612722 | 1059 | err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, |
2ed28baa | 1060 | -1, -1, -1, |
f646968f | 1061 | !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); |
2ed28baa | 1062 | if (unlikely(err)) |
f646968f | 1063 | dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; |
19ecae2c | 1064 | return err; |
87b6cf51 DM |
1065 | } |
1066 | ||
91744948 | 1067 | static int setup_debugfs(struct adapter *adap) |
b8ff05a9 | 1068 | { |
b8ff05a9 DM |
1069 | if (IS_ERR_OR_NULL(adap->debugfs_root)) |
1070 | return -1; | |
1071 | ||
fd88b31a HS |
1072 | #ifdef CONFIG_DEBUG_FS |
1073 | t4_setup_debugfs(adap); | |
1074 | #endif | |
b8ff05a9 DM |
1075 | return 0; |
1076 | } | |
1077 | ||
1078 | /* | |
1079 | * upper-layer driver support | |
1080 | */ | |
1081 | ||
1082 | /* | |
1083 | * Allocate an active-open TID and set it to the supplied value. | |
1084 | */ | |
1085 | int cxgb4_alloc_atid(struct tid_info *t, void *data) | |
1086 | { | |
1087 | int atid = -1; | |
1088 | ||
1089 | spin_lock_bh(&t->atid_lock); | |
1090 | if (t->afree) { | |
1091 | union aopen_entry *p = t->afree; | |
1092 | ||
f2b7e78d | 1093 | atid = (p - t->atid_tab) + t->atid_base; |
b8ff05a9 DM |
1094 | t->afree = p->next; |
1095 | p->data = data; | |
1096 | t->atids_in_use++; | |
1097 | } | |
1098 | spin_unlock_bh(&t->atid_lock); | |
1099 | return atid; | |
1100 | } | |
1101 | EXPORT_SYMBOL(cxgb4_alloc_atid); | |
1102 | ||
1103 | /* | |
1104 | * Release an active-open TID. | |
1105 | */ | |
1106 | void cxgb4_free_atid(struct tid_info *t, unsigned int atid) | |
1107 | { | |
f2b7e78d | 1108 | union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; |
b8ff05a9 DM |
1109 | |
1110 | spin_lock_bh(&t->atid_lock); | |
1111 | p->next = t->afree; | |
1112 | t->afree = p; | |
1113 | t->atids_in_use--; | |
1114 | spin_unlock_bh(&t->atid_lock); | |
1115 | } | |
1116 | EXPORT_SYMBOL(cxgb4_free_atid); | |
1117 | ||
1118 | /* | |
1119 | * Allocate a server TID and set it to the supplied value. | |
1120 | */ | |
1121 | int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) | |
1122 | { | |
1123 | int stid; | |
1124 | ||
1125 | spin_lock_bh(&t->stid_lock); | |
1126 | if (family == PF_INET) { | |
1127 | stid = find_first_zero_bit(t->stid_bmap, t->nstids); | |
1128 | if (stid < t->nstids) | |
1129 | __set_bit(stid, t->stid_bmap); | |
1130 | else | |
1131 | stid = -1; | |
1132 | } else { | |
a99c683e | 1133 | stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); |
b8ff05a9 DM |
1134 | if (stid < 0) |
1135 | stid = -1; | |
1136 | } | |
1137 | if (stid >= 0) { | |
1138 | t->stid_tab[stid].data = data; | |
1139 | stid += t->stid_base; | |
15f63b74 KS |
1140 | /* IPv6 requires max of 520 bits or 16 cells in TCAM |
1141 | * This is equivalent to 4 TIDs. With CLIP enabled it | |
1142 | * needs 2 TIDs. | |
1143 | */ | |
1dec4cec | 1144 | if (family == PF_INET6) { |
a99c683e | 1145 | t->stids_in_use += 2; |
1dec4cec GG |
1146 | t->v6_stids_in_use += 2; |
1147 | } else { | |
1148 | t->stids_in_use++; | |
1149 | } | |
b8ff05a9 DM |
1150 | } |
1151 | spin_unlock_bh(&t->stid_lock); | |
1152 | return stid; | |
1153 | } | |
1154 | EXPORT_SYMBOL(cxgb4_alloc_stid); | |
1155 | ||
dca4faeb VP |
1156 | /* Allocate a server filter TID and set it to the supplied value. |
1157 | */ | |
1158 | int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) | |
1159 | { | |
1160 | int stid; | |
1161 | ||
1162 | spin_lock_bh(&t->stid_lock); | |
1163 | if (family == PF_INET) { | |
1164 | stid = find_next_zero_bit(t->stid_bmap, | |
1165 | t->nstids + t->nsftids, t->nstids); | |
1166 | if (stid < (t->nstids + t->nsftids)) | |
1167 | __set_bit(stid, t->stid_bmap); | |
1168 | else | |
1169 | stid = -1; | |
1170 | } else { | |
1171 | stid = -1; | |
1172 | } | |
1173 | if (stid >= 0) { | |
1174 | t->stid_tab[stid].data = data; | |
470c60c4 KS |
1175 | stid -= t->nstids; |
1176 | stid += t->sftid_base; | |
2248b293 | 1177 | t->sftids_in_use++; |
dca4faeb VP |
1178 | } |
1179 | spin_unlock_bh(&t->stid_lock); | |
1180 | return stid; | |
1181 | } | |
1182 | EXPORT_SYMBOL(cxgb4_alloc_sftid); | |
1183 | ||
1184 | /* Release a server TID. | |
b8ff05a9 DM |
1185 | */ |
1186 | void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) | |
1187 | { | |
470c60c4 KS |
1188 | /* Is it a server filter TID? */ |
1189 | if (t->nsftids && (stid >= t->sftid_base)) { | |
1190 | stid -= t->sftid_base; | |
1191 | stid += t->nstids; | |
1192 | } else { | |
1193 | stid -= t->stid_base; | |
1194 | } | |
1195 | ||
b8ff05a9 DM |
1196 | spin_lock_bh(&t->stid_lock); |
1197 | if (family == PF_INET) | |
1198 | __clear_bit(stid, t->stid_bmap); | |
1199 | else | |
a99c683e | 1200 | bitmap_release_region(t->stid_bmap, stid, 1); |
b8ff05a9 | 1201 | t->stid_tab[stid].data = NULL; |
2248b293 | 1202 | if (stid < t->nstids) { |
1dec4cec | 1203 | if (family == PF_INET6) { |
a99c683e | 1204 | t->stids_in_use -= 2; |
1dec4cec GG |
1205 | t->v6_stids_in_use -= 2; |
1206 | } else { | |
1207 | t->stids_in_use--; | |
1208 | } | |
2248b293 HS |
1209 | } else { |
1210 | t->sftids_in_use--; | |
1211 | } | |
1dec4cec | 1212 | |
b8ff05a9 DM |
1213 | spin_unlock_bh(&t->stid_lock); |
1214 | } | |
1215 | EXPORT_SYMBOL(cxgb4_free_stid); | |
1216 | ||
1217 | /* | |
1218 | * Populate a TID_RELEASE WR. Caller must properly size the skb. | |
1219 | */ | |
1220 | static void mk_tid_release(struct sk_buff *skb, unsigned int chan, | |
1221 | unsigned int tid) | |
1222 | { | |
1223 | struct cpl_tid_release *req; | |
1224 | ||
1225 | set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); | |
4df864c1 | 1226 | req = __skb_put(skb, sizeof(*req)); |
b8ff05a9 DM |
1227 | INIT_TP_WR(req, tid); |
1228 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); | |
1229 | } | |
1230 | ||
1231 | /* | |
1232 | * Queue a TID release request and if necessary schedule a work queue to | |
1233 | * process it. | |
1234 | */ | |
31b9c19b | 1235 | static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, |
1236 | unsigned int tid) | |
b8ff05a9 DM |
1237 | { |
1238 | void **p = &t->tid_tab[tid]; | |
1239 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1240 | ||
1241 | spin_lock_bh(&adap->tid_release_lock); | |
1242 | *p = adap->tid_release_head; | |
1243 | /* Low 2 bits encode the Tx channel number */ | |
1244 | adap->tid_release_head = (void **)((uintptr_t)p | chan); | |
1245 | if (!adap->tid_release_task_busy) { | |
1246 | adap->tid_release_task_busy = true; | |
29aaee65 | 1247 | queue_work(adap->workq, &adap->tid_release_task); |
b8ff05a9 DM |
1248 | } |
1249 | spin_unlock_bh(&adap->tid_release_lock); | |
1250 | } | |
b8ff05a9 DM |
1251 | |
1252 | /* | |
1253 | * Process the list of pending TID release requests. | |
1254 | */ | |
1255 | static void process_tid_release_list(struct work_struct *work) | |
1256 | { | |
1257 | struct sk_buff *skb; | |
1258 | struct adapter *adap; | |
1259 | ||
1260 | adap = container_of(work, struct adapter, tid_release_task); | |
1261 | ||
1262 | spin_lock_bh(&adap->tid_release_lock); | |
1263 | while (adap->tid_release_head) { | |
1264 | void **p = adap->tid_release_head; | |
1265 | unsigned int chan = (uintptr_t)p & 3; | |
1266 | p = (void *)p - chan; | |
1267 | ||
1268 | adap->tid_release_head = *p; | |
1269 | *p = NULL; | |
1270 | spin_unlock_bh(&adap->tid_release_lock); | |
1271 | ||
1272 | while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), | |
1273 | GFP_KERNEL))) | |
1274 | schedule_timeout_uninterruptible(1); | |
1275 | ||
1276 | mk_tid_release(skb, chan, p - adap->tids.tid_tab); | |
1277 | t4_ofld_send(adap, skb); | |
1278 | spin_lock_bh(&adap->tid_release_lock); | |
1279 | } | |
1280 | adap->tid_release_task_busy = false; | |
1281 | spin_unlock_bh(&adap->tid_release_lock); | |
1282 | } | |
1283 | ||
1284 | /* | |
1285 | * Release a TID and inform HW. If we are unable to allocate the release | |
1286 | * message we defer to a work queue. | |
1287 | */ | |
1dec4cec GG |
1288 | void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, |
1289 | unsigned short family) | |
b8ff05a9 | 1290 | { |
b8ff05a9 DM |
1291 | struct sk_buff *skb; |
1292 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1293 | ||
9a1bb9f6 HS |
1294 | WARN_ON(tid >= t->ntids); |
1295 | ||
1296 | if (t->tid_tab[tid]) { | |
1297 | t->tid_tab[tid] = NULL; | |
1dec4cec GG |
1298 | atomic_dec(&t->conns_in_use); |
1299 | if (t->hash_base && (tid >= t->hash_base)) { | |
1300 | if (family == AF_INET6) | |
1301 | atomic_sub(2, &t->hash_tids_in_use); | |
1302 | else | |
1303 | atomic_dec(&t->hash_tids_in_use); | |
1304 | } else { | |
1305 | if (family == AF_INET6) | |
1306 | atomic_sub(2, &t->tids_in_use); | |
1307 | else | |
1308 | atomic_dec(&t->tids_in_use); | |
1309 | } | |
9a1bb9f6 HS |
1310 | } |
1311 | ||
b8ff05a9 DM |
1312 | skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); |
1313 | if (likely(skb)) { | |
b8ff05a9 DM |
1314 | mk_tid_release(skb, chan, tid); |
1315 | t4_ofld_send(adap, skb); | |
1316 | } else | |
1317 | cxgb4_queue_tid_release(t, chan, tid); | |
b8ff05a9 DM |
1318 | } |
1319 | EXPORT_SYMBOL(cxgb4_remove_tid); | |
1320 | ||
1321 | /* | |
1322 | * Allocate and initialize the TID tables. Returns 0 on success. | |
1323 | */ | |
1324 | static int tid_init(struct tid_info *t) | |
1325 | { | |
b6f8eaec | 1326 | struct adapter *adap = container_of(t, struct adapter, tids); |
578b46b9 RL |
1327 | unsigned int max_ftids = t->nftids + t->nsftids; |
1328 | unsigned int natids = t->natids; | |
1329 | unsigned int stid_bmap_size; | |
1330 | unsigned int ftid_bmap_size; | |
1331 | size_t size; | |
b8ff05a9 | 1332 | |
dca4faeb | 1333 | stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); |
578b46b9 | 1334 | ftid_bmap_size = BITS_TO_LONGS(t->nftids); |
f2b7e78d VP |
1335 | size = t->ntids * sizeof(*t->tid_tab) + |
1336 | natids * sizeof(*t->atid_tab) + | |
b8ff05a9 | 1337 | t->nstids * sizeof(*t->stid_tab) + |
dca4faeb | 1338 | t->nsftids * sizeof(*t->stid_tab) + |
f2b7e78d | 1339 | stid_bmap_size * sizeof(long) + |
578b46b9 RL |
1340 | max_ftids * sizeof(*t->ftid_tab) + |
1341 | ftid_bmap_size * sizeof(long); | |
f2b7e78d | 1342 | |
752ade68 | 1343 | t->tid_tab = kvzalloc(size, GFP_KERNEL); |
b8ff05a9 DM |
1344 | if (!t->tid_tab) |
1345 | return -ENOMEM; | |
1346 | ||
1347 | t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; | |
1348 | t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; | |
dca4faeb | 1349 | t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; |
f2b7e78d | 1350 | t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; |
578b46b9 | 1351 | t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids]; |
b8ff05a9 DM |
1352 | spin_lock_init(&t->stid_lock); |
1353 | spin_lock_init(&t->atid_lock); | |
578b46b9 | 1354 | spin_lock_init(&t->ftid_lock); |
b8ff05a9 DM |
1355 | |
1356 | t->stids_in_use = 0; | |
1dec4cec | 1357 | t->v6_stids_in_use = 0; |
2248b293 | 1358 | t->sftids_in_use = 0; |
b8ff05a9 DM |
1359 | t->afree = NULL; |
1360 | t->atids_in_use = 0; | |
1361 | atomic_set(&t->tids_in_use, 0); | |
1dec4cec | 1362 | atomic_set(&t->conns_in_use, 0); |
9a1bb9f6 | 1363 | atomic_set(&t->hash_tids_in_use, 0); |
b8ff05a9 DM |
1364 | |
1365 | /* Setup the free list for atid_tab and clear the stid bitmap. */ | |
1366 | if (natids) { | |
1367 | while (--natids) | |
1368 | t->atid_tab[natids - 1].next = &t->atid_tab[natids]; | |
1369 | t->afree = t->atid_tab; | |
1370 | } | |
b6f8eaec | 1371 | |
578b46b9 RL |
1372 | if (is_offload(adap)) { |
1373 | bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); | |
1374 | /* Reserve stid 0 for T4/T5 adapters */ | |
1375 | if (!t->stid_base && | |
1376 | CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) | |
1377 | __set_bit(0, t->stid_bmap); | |
1378 | } | |
1379 | ||
1380 | bitmap_zero(t->ftid_bmap, t->nftids); | |
b8ff05a9 DM |
1381 | return 0; |
1382 | } | |
1383 | ||
1384 | /** | |
1385 | * cxgb4_create_server - create an IP server | |
1386 | * @dev: the device | |
1387 | * @stid: the server TID | |
1388 | * @sip: local IP address to bind server to | |
1389 | * @sport: the server's TCP port | |
1390 | * @queue: queue to direct messages from this server to | |
1391 | * | |
1392 | * Create an IP server for the given port and address. | |
1393 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1394 | */ | |
1395 | int cxgb4_create_server(const struct net_device *dev, unsigned int stid, | |
793dad94 VP |
1396 | __be32 sip, __be16 sport, __be16 vlan, |
1397 | unsigned int queue) | |
b8ff05a9 DM |
1398 | { |
1399 | unsigned int chan; | |
1400 | struct sk_buff *skb; | |
1401 | struct adapter *adap; | |
1402 | struct cpl_pass_open_req *req; | |
80f40c1f | 1403 | int ret; |
b8ff05a9 DM |
1404 | |
1405 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1406 | if (!skb) | |
1407 | return -ENOMEM; | |
1408 | ||
1409 | adap = netdev2adap(dev); | |
4df864c1 | 1410 | req = __skb_put(skb, sizeof(*req)); |
b8ff05a9 DM |
1411 | INIT_TP_WR(req, 0); |
1412 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); | |
1413 | req->local_port = sport; | |
1414 | req->peer_port = htons(0); | |
1415 | req->local_ip = sip; | |
1416 | req->peer_ip = htonl(0); | |
e46dab4d | 1417 | chan = rxq_to_chan(&adap->sge, queue); |
d7990b0c | 1418 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1419 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1420 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1421 | ret = t4_mgmt_tx(adap, skb); |
1422 | return net_xmit_eval(ret); | |
b8ff05a9 DM |
1423 | } |
1424 | EXPORT_SYMBOL(cxgb4_create_server); | |
1425 | ||
80f40c1f VP |
1426 | /* cxgb4_create_server6 - create an IPv6 server |
1427 | * @dev: the device | |
1428 | * @stid: the server TID | |
1429 | * @sip: local IPv6 address to bind server to | |
1430 | * @sport: the server's TCP port | |
1431 | * @queue: queue to direct messages from this server to | |
1432 | * | |
1433 | * Create an IPv6 server for the given port and address. | |
1434 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1435 | */ | |
1436 | int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, | |
1437 | const struct in6_addr *sip, __be16 sport, | |
1438 | unsigned int queue) | |
1439 | { | |
1440 | unsigned int chan; | |
1441 | struct sk_buff *skb; | |
1442 | struct adapter *adap; | |
1443 | struct cpl_pass_open_req6 *req; | |
1444 | int ret; | |
1445 | ||
1446 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1447 | if (!skb) | |
1448 | return -ENOMEM; | |
1449 | ||
1450 | adap = netdev2adap(dev); | |
4df864c1 | 1451 | req = __skb_put(skb, sizeof(*req)); |
80f40c1f VP |
1452 | INIT_TP_WR(req, 0); |
1453 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); | |
1454 | req->local_port = sport; | |
1455 | req->peer_port = htons(0); | |
1456 | req->local_ip_hi = *(__be64 *)(sip->s6_addr); | |
1457 | req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); | |
1458 | req->peer_ip_hi = cpu_to_be64(0); | |
1459 | req->peer_ip_lo = cpu_to_be64(0); | |
1460 | chan = rxq_to_chan(&adap->sge, queue); | |
d7990b0c | 1461 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1462 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1463 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1464 | ret = t4_mgmt_tx(adap, skb); |
1465 | return net_xmit_eval(ret); | |
1466 | } | |
1467 | EXPORT_SYMBOL(cxgb4_create_server6); | |
1468 | ||
1469 | int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, | |
1470 | unsigned int queue, bool ipv6) | |
1471 | { | |
1472 | struct sk_buff *skb; | |
1473 | struct adapter *adap; | |
1474 | struct cpl_close_listsvr_req *req; | |
1475 | int ret; | |
1476 | ||
1477 | adap = netdev2adap(dev); | |
1478 | ||
1479 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1480 | if (!skb) | |
1481 | return -ENOMEM; | |
1482 | ||
4df864c1 | 1483 | req = __skb_put(skb, sizeof(*req)); |
80f40c1f VP |
1484 | INIT_TP_WR(req, 0); |
1485 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); | |
bdc590b9 HS |
1486 | req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : |
1487 | LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); | |
80f40c1f VP |
1488 | ret = t4_mgmt_tx(adap, skb); |
1489 | return net_xmit_eval(ret); | |
1490 | } | |
1491 | EXPORT_SYMBOL(cxgb4_remove_server); | |
1492 | ||
b8ff05a9 DM |
1493 | /** |
1494 | * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU | |
1495 | * @mtus: the HW MTU table | |
1496 | * @mtu: the target MTU | |
1497 | * @idx: index of selected entry in the MTU table | |
1498 | * | |
1499 | * Returns the index and the value in the HW MTU table that is closest to | |
1500 | * but does not exceed @mtu, unless @mtu is smaller than any value in the | |
1501 | * table, in which case that smallest available value is selected. | |
1502 | */ | |
1503 | unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, | |
1504 | unsigned int *idx) | |
1505 | { | |
1506 | unsigned int i = 0; | |
1507 | ||
1508 | while (i < NMTUS - 1 && mtus[i + 1] <= mtu) | |
1509 | ++i; | |
1510 | if (idx) | |
1511 | *idx = i; | |
1512 | return mtus[i]; | |
1513 | } | |
1514 | EXPORT_SYMBOL(cxgb4_best_mtu); | |
1515 | ||
92e7ae71 HS |
1516 | /** |
1517 | * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned | |
1518 | * @mtus: the HW MTU table | |
1519 | * @header_size: Header Size | |
1520 | * @data_size_max: maximum Data Segment Size | |
1521 | * @data_size_align: desired Data Segment Size Alignment (2^N) | |
1522 | * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) | |
1523 | * | |
1524 | * Similar to cxgb4_best_mtu() but instead of searching the Hardware | |
1525 | * MTU Table based solely on a Maximum MTU parameter, we break that | |
1526 | * parameter up into a Header Size and Maximum Data Segment Size, and | |
1527 | * provide a desired Data Segment Size Alignment. If we find an MTU in | |
1528 | * the Hardware MTU Table which will result in a Data Segment Size with | |
1529 | * the requested alignment _and_ that MTU isn't "too far" from the | |
1530 | * closest MTU, then we'll return that rather than the closest MTU. | |
1531 | */ | |
1532 | unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, | |
1533 | unsigned short header_size, | |
1534 | unsigned short data_size_max, | |
1535 | unsigned short data_size_align, | |
1536 | unsigned int *mtu_idxp) | |
1537 | { | |
1538 | unsigned short max_mtu = header_size + data_size_max; | |
1539 | unsigned short data_size_align_mask = data_size_align - 1; | |
1540 | int mtu_idx, aligned_mtu_idx; | |
1541 | ||
1542 | /* Scan the MTU Table till we find an MTU which is larger than our | |
1543 | * Maximum MTU or we reach the end of the table. Along the way, | |
1544 | * record the last MTU found, if any, which will result in a Data | |
1545 | * Segment Length matching the requested alignment. | |
1546 | */ | |
1547 | for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { | |
1548 | unsigned short data_size = mtus[mtu_idx] - header_size; | |
1549 | ||
1550 | /* If this MTU minus the Header Size would result in a | |
1551 | * Data Segment Size of the desired alignment, remember it. | |
1552 | */ | |
1553 | if ((data_size & data_size_align_mask) == 0) | |
1554 | aligned_mtu_idx = mtu_idx; | |
1555 | ||
1556 | /* If we're not at the end of the Hardware MTU Table and the | |
1557 | * next element is larger than our Maximum MTU, drop out of | |
1558 | * the loop. | |
1559 | */ | |
1560 | if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) | |
1561 | break; | |
1562 | } | |
1563 | ||
1564 | /* If we fell out of the loop because we ran to the end of the table, | |
1565 | * then we just have to use the last [largest] entry. | |
1566 | */ | |
1567 | if (mtu_idx == NMTUS) | |
1568 | mtu_idx--; | |
1569 | ||
1570 | /* If we found an MTU which resulted in the requested Data Segment | |
1571 | * Length alignment and that's "not far" from the largest MTU which is | |
1572 | * less than or equal to the maximum MTU, then use that. | |
1573 | */ | |
1574 | if (aligned_mtu_idx >= 0 && | |
1575 | mtu_idx - aligned_mtu_idx <= 1) | |
1576 | mtu_idx = aligned_mtu_idx; | |
1577 | ||
1578 | /* If the caller has passed in an MTU Index pointer, pass the | |
1579 | * MTU Index back. Return the MTU value. | |
1580 | */ | |
1581 | if (mtu_idxp) | |
1582 | *mtu_idxp = mtu_idx; | |
1583 | return mtus[mtu_idx]; | |
1584 | } | |
1585 | EXPORT_SYMBOL(cxgb4_best_aligned_mtu); | |
1586 | ||
27999805 H |
1587 | /** |
1588 | * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI | |
1589 | * @chip: chip type | |
1590 | * @viid: VI id of the given port | |
1591 | * | |
1592 | * Return the SMT index for this VI. | |
1593 | */ | |
1594 | unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid) | |
1595 | { | |
1596 | /* In T4/T5, SMT contains 256 SMAC entries organized in | |
1597 | * 128 rows of 2 entries each. | |
1598 | * In T6, SMT contains 256 SMAC entries in 256 rows. | |
1599 | * TODO: The below code needs to be updated when we add support | |
1600 | * for 256 VFs. | |
1601 | */ | |
1602 | if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) | |
1603 | return ((viid & 0x7f) << 1); | |
1604 | else | |
1605 | return (viid & 0x7f); | |
1606 | } | |
1607 | EXPORT_SYMBOL(cxgb4_tp_smt_idx); | |
1608 | ||
b8ff05a9 DM |
1609 | /** |
1610 | * cxgb4_port_chan - get the HW channel of a port | |
1611 | * @dev: the net device for the port | |
1612 | * | |
1613 | * Return the HW Tx channel of the given port. | |
1614 | */ | |
1615 | unsigned int cxgb4_port_chan(const struct net_device *dev) | |
1616 | { | |
1617 | return netdev2pinfo(dev)->tx_chan; | |
1618 | } | |
1619 | EXPORT_SYMBOL(cxgb4_port_chan); | |
1620 | ||
881806bc VP |
1621 | unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) |
1622 | { | |
1623 | struct adapter *adap = netdev2adap(dev); | |
2cc301d2 | 1624 | u32 v1, v2, lp_count, hp_count; |
881806bc | 1625 | |
f061de42 HS |
1626 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
1627 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 1628 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
1629 | lp_count = LP_COUNT_G(v1); |
1630 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 1631 | } else { |
f061de42 HS |
1632 | lp_count = LP_COUNT_T5_G(v1); |
1633 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
1634 | } |
1635 | return lpfifo ? lp_count : hp_count; | |
881806bc VP |
1636 | } |
1637 | EXPORT_SYMBOL(cxgb4_dbfifo_count); | |
1638 | ||
b8ff05a9 DM |
1639 | /** |
1640 | * cxgb4_port_viid - get the VI id of a port | |
1641 | * @dev: the net device for the port | |
1642 | * | |
1643 | * Return the VI id of the given port. | |
1644 | */ | |
1645 | unsigned int cxgb4_port_viid(const struct net_device *dev) | |
1646 | { | |
1647 | return netdev2pinfo(dev)->viid; | |
1648 | } | |
1649 | EXPORT_SYMBOL(cxgb4_port_viid); | |
1650 | ||
1651 | /** | |
1652 | * cxgb4_port_idx - get the index of a port | |
1653 | * @dev: the net device for the port | |
1654 | * | |
1655 | * Return the index of the given port. | |
1656 | */ | |
1657 | unsigned int cxgb4_port_idx(const struct net_device *dev) | |
1658 | { | |
1659 | return netdev2pinfo(dev)->port_id; | |
1660 | } | |
1661 | EXPORT_SYMBOL(cxgb4_port_idx); | |
1662 | ||
b8ff05a9 DM |
1663 | void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, |
1664 | struct tp_tcp_stats *v6) | |
1665 | { | |
1666 | struct adapter *adap = pci_get_drvdata(pdev); | |
1667 | ||
1668 | spin_lock(&adap->stats_lock); | |
5ccf9d04 | 1669 | t4_tp_get_tcp_stats(adap, v4, v6, false); |
b8ff05a9 DM |
1670 | spin_unlock(&adap->stats_lock); |
1671 | } | |
1672 | EXPORT_SYMBOL(cxgb4_get_tcp_stats); | |
1673 | ||
1674 | void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, | |
1675 | const unsigned int *pgsz_order) | |
1676 | { | |
1677 | struct adapter *adap = netdev2adap(dev); | |
1678 | ||
0d804338 HS |
1679 | t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); |
1680 | t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | | |
1681 | HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | | |
1682 | HPZ3_V(pgsz_order[3])); | |
b8ff05a9 DM |
1683 | } |
1684 | EXPORT_SYMBOL(cxgb4_iscsi_init); | |
1685 | ||
3069ee9b VP |
1686 | int cxgb4_flush_eq_cache(struct net_device *dev) |
1687 | { | |
1688 | struct adapter *adap = netdev2adap(dev); | |
3069ee9b | 1689 | |
736c3b94 | 1690 | return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS); |
3069ee9b VP |
1691 | } |
1692 | EXPORT_SYMBOL(cxgb4_flush_eq_cache); | |
1693 | ||
1694 | static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) | |
1695 | { | |
f061de42 | 1696 | u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; |
3069ee9b VP |
1697 | __be64 indices; |
1698 | int ret; | |
1699 | ||
fc5ab020 HS |
1700 | spin_lock(&adap->win0_lock); |
1701 | ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, | |
1702 | sizeof(indices), (__be32 *)&indices, | |
1703 | T4_MEMORY_READ); | |
1704 | spin_unlock(&adap->win0_lock); | |
3069ee9b | 1705 | if (!ret) { |
404d9e3f VP |
1706 | *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; |
1707 | *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; | |
3069ee9b VP |
1708 | } |
1709 | return ret; | |
1710 | } | |
1711 | ||
1712 | int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, | |
1713 | u16 size) | |
1714 | { | |
1715 | struct adapter *adap = netdev2adap(dev); | |
1716 | u16 hw_pidx, hw_cidx; | |
1717 | int ret; | |
1718 | ||
1719 | ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); | |
1720 | if (ret) | |
1721 | goto out; | |
1722 | ||
1723 | if (pidx != hw_pidx) { | |
1724 | u16 delta; | |
f612b815 | 1725 | u32 val; |
3069ee9b VP |
1726 | |
1727 | if (pidx >= hw_pidx) | |
1728 | delta = pidx - hw_pidx; | |
1729 | else | |
1730 | delta = size - hw_pidx + pidx; | |
f612b815 HS |
1731 | |
1732 | if (is_t4(adap->params.chip)) | |
1733 | val = PIDX_V(delta); | |
1734 | else | |
1735 | val = PIDX_T5_V(delta); | |
3069ee9b | 1736 | wmb(); |
f612b815 HS |
1737 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
1738 | QID_V(qid) | val); | |
3069ee9b VP |
1739 | } |
1740 | out: | |
1741 | return ret; | |
1742 | } | |
1743 | EXPORT_SYMBOL(cxgb4_sync_txq_pidx); | |
1744 | ||
031cf476 HS |
1745 | int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) |
1746 | { | |
6559a7e8 | 1747 | u32 edc0_size, edc1_size, mc0_size, mc1_size, size; |
031cf476 | 1748 | u32 edc0_end, edc1_end, mc0_end, mc1_end; |
8b4e6b3c AV |
1749 | u32 offset, memtype, memaddr; |
1750 | struct adapter *adap; | |
1751 | u32 hma_size = 0; | |
031cf476 HS |
1752 | int ret; |
1753 | ||
1754 | adap = netdev2adap(dev); | |
1755 | ||
1756 | offset = ((stag >> 8) * 32) + adap->vres.stag.start; | |
1757 | ||
1758 | /* Figure out where the offset lands in the Memory Type/Address scheme. | |
1759 | * This code assumes that the memory is laid out starting at offset 0 | |
1760 | * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 | |
1761 | * and EDC1. Some cards will have neither MC0 nor MC1, most cards have | |
1762 | * MC0, and some have both MC0 and MC1. | |
1763 | */ | |
6559a7e8 HS |
1764 | size = t4_read_reg(adap, MA_EDRAM0_BAR_A); |
1765 | edc0_size = EDRAM0_SIZE_G(size) << 20; | |
1766 | size = t4_read_reg(adap, MA_EDRAM1_BAR_A); | |
1767 | edc1_size = EDRAM1_SIZE_G(size) << 20; | |
1768 | size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); | |
1769 | mc0_size = EXT_MEM0_SIZE_G(size) << 20; | |
031cf476 | 1770 | |
8b4e6b3c AV |
1771 | if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) { |
1772 | size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); | |
1773 | hma_size = EXT_MEM1_SIZE_G(size) << 20; | |
1774 | } | |
031cf476 HS |
1775 | edc0_end = edc0_size; |
1776 | edc1_end = edc0_end + edc1_size; | |
1777 | mc0_end = edc1_end + mc0_size; | |
1778 | ||
1779 | if (offset < edc0_end) { | |
1780 | memtype = MEM_EDC0; | |
1781 | memaddr = offset; | |
1782 | } else if (offset < edc1_end) { | |
1783 | memtype = MEM_EDC1; | |
1784 | memaddr = offset - edc0_end; | |
1785 | } else { | |
8b4e6b3c AV |
1786 | if (hma_size && (offset < (edc1_end + hma_size))) { |
1787 | memtype = MEM_HMA; | |
1788 | memaddr = offset - edc1_end; | |
1789 | } else if (offset < mc0_end) { | |
031cf476 HS |
1790 | memtype = MEM_MC0; |
1791 | memaddr = offset - edc1_end; | |
3ccc6cf7 | 1792 | } else if (is_t5(adap->params.chip)) { |
6559a7e8 HS |
1793 | size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); |
1794 | mc1_size = EXT_MEM1_SIZE_G(size) << 20; | |
031cf476 HS |
1795 | mc1_end = mc0_end + mc1_size; |
1796 | if (offset < mc1_end) { | |
1797 | memtype = MEM_MC1; | |
1798 | memaddr = offset - mc0_end; | |
1799 | } else { | |
1800 | /* offset beyond the end of any memory */ | |
1801 | goto err; | |
1802 | } | |
3ccc6cf7 HS |
1803 | } else { |
1804 | /* T4/T6 only has a single memory channel */ | |
1805 | goto err; | |
031cf476 HS |
1806 | } |
1807 | } | |
1808 | ||
1809 | spin_lock(&adap->win0_lock); | |
1810 | ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); | |
1811 | spin_unlock(&adap->win0_lock); | |
1812 | return ret; | |
1813 | ||
1814 | err: | |
1815 | dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", | |
1816 | stag, offset); | |
1817 | return -EINVAL; | |
1818 | } | |
1819 | EXPORT_SYMBOL(cxgb4_read_tpte); | |
1820 | ||
7730b4c7 HS |
1821 | u64 cxgb4_read_sge_timestamp(struct net_device *dev) |
1822 | { | |
1823 | u32 hi, lo; | |
1824 | struct adapter *adap; | |
1825 | ||
1826 | adap = netdev2adap(dev); | |
f612b815 HS |
1827 | lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); |
1828 | hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); | |
7730b4c7 HS |
1829 | |
1830 | return ((u64)hi << 32) | (u64)lo; | |
1831 | } | |
1832 | EXPORT_SYMBOL(cxgb4_read_sge_timestamp); | |
1833 | ||
df64e4d3 HS |
1834 | int cxgb4_bar2_sge_qregs(struct net_device *dev, |
1835 | unsigned int qid, | |
1836 | enum cxgb4_bar2_qtype qtype, | |
66cf188e | 1837 | int user, |
df64e4d3 HS |
1838 | u64 *pbar2_qoffset, |
1839 | unsigned int *pbar2_qid) | |
1840 | { | |
b2612722 | 1841 | return t4_bar2_sge_qregs(netdev2adap(dev), |
df64e4d3 HS |
1842 | qid, |
1843 | (qtype == CXGB4_BAR2_QTYPE_EGRESS | |
1844 | ? T4_BAR2_QTYPE_EGRESS | |
1845 | : T4_BAR2_QTYPE_INGRESS), | |
66cf188e | 1846 | user, |
df64e4d3 HS |
1847 | pbar2_qoffset, |
1848 | pbar2_qid); | |
1849 | } | |
1850 | EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); | |
1851 | ||
b8ff05a9 DM |
1852 | static struct pci_driver cxgb4_driver; |
1853 | ||
1854 | static void check_neigh_update(struct neighbour *neigh) | |
1855 | { | |
1856 | const struct device *parent; | |
1857 | const struct net_device *netdev = neigh->dev; | |
1858 | ||
d0d7b10b | 1859 | if (is_vlan_dev(netdev)) |
b8ff05a9 DM |
1860 | netdev = vlan_dev_real_dev(netdev); |
1861 | parent = netdev->dev.parent; | |
1862 | if (parent && parent->driver == &cxgb4_driver.driver) | |
1863 | t4_l2t_update(dev_get_drvdata(parent), neigh); | |
1864 | } | |
1865 | ||
1866 | static int netevent_cb(struct notifier_block *nb, unsigned long event, | |
1867 | void *data) | |
1868 | { | |
1869 | switch (event) { | |
1870 | case NETEVENT_NEIGH_UPDATE: | |
1871 | check_neigh_update(data); | |
1872 | break; | |
b8ff05a9 DM |
1873 | case NETEVENT_REDIRECT: |
1874 | default: | |
1875 | break; | |
1876 | } | |
1877 | return 0; | |
1878 | } | |
1879 | ||
1880 | static bool netevent_registered; | |
1881 | static struct notifier_block cxgb4_netevent_nb = { | |
1882 | .notifier_call = netevent_cb | |
1883 | }; | |
1884 | ||
3069ee9b VP |
1885 | static void drain_db_fifo(struct adapter *adap, int usecs) |
1886 | { | |
2cc301d2 | 1887 | u32 v1, v2, lp_count, hp_count; |
3069ee9b VP |
1888 | |
1889 | do { | |
f061de42 HS |
1890 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
1891 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 1892 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
1893 | lp_count = LP_COUNT_G(v1); |
1894 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 1895 | } else { |
f061de42 HS |
1896 | lp_count = LP_COUNT_T5_G(v1); |
1897 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
1898 | } |
1899 | ||
1900 | if (lp_count == 0 && hp_count == 0) | |
1901 | break; | |
3069ee9b VP |
1902 | set_current_state(TASK_UNINTERRUPTIBLE); |
1903 | schedule_timeout(usecs_to_jiffies(usecs)); | |
3069ee9b VP |
1904 | } while (1); |
1905 | } | |
1906 | ||
1907 | static void disable_txq_db(struct sge_txq *q) | |
1908 | { | |
05eb2389 SW |
1909 | unsigned long flags; |
1910 | ||
1911 | spin_lock_irqsave(&q->db_lock, flags); | |
3069ee9b | 1912 | q->db_disabled = 1; |
05eb2389 | 1913 | spin_unlock_irqrestore(&q->db_lock, flags); |
3069ee9b VP |
1914 | } |
1915 | ||
05eb2389 | 1916 | static void enable_txq_db(struct adapter *adap, struct sge_txq *q) |
3069ee9b VP |
1917 | { |
1918 | spin_lock_irq(&q->db_lock); | |
05eb2389 SW |
1919 | if (q->db_pidx_inc) { |
1920 | /* Make sure that all writes to the TX descriptors | |
1921 | * are committed before we tell HW about them. | |
1922 | */ | |
1923 | wmb(); | |
f612b815 HS |
1924 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
1925 | QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); | |
05eb2389 SW |
1926 | q->db_pidx_inc = 0; |
1927 | } | |
3069ee9b VP |
1928 | q->db_disabled = 0; |
1929 | spin_unlock_irq(&q->db_lock); | |
1930 | } | |
1931 | ||
1932 | static void disable_dbs(struct adapter *adap) | |
1933 | { | |
1934 | int i; | |
1935 | ||
1936 | for_each_ethrxq(&adap->sge, i) | |
1937 | disable_txq_db(&adap->sge.ethtxq[i].q); | |
ab677ff4 HS |
1938 | if (is_offload(adap)) { |
1939 | struct sge_uld_txq_info *txq_info = | |
1940 | adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
1941 | ||
1942 | if (txq_info) { | |
1943 | for_each_ofldtxq(&adap->sge, i) { | |
1944 | struct sge_uld_txq *txq = &txq_info->uldtxq[i]; | |
1945 | ||
1946 | disable_txq_db(&txq->q); | |
1947 | } | |
1948 | } | |
1949 | } | |
3069ee9b VP |
1950 | for_each_port(adap, i) |
1951 | disable_txq_db(&adap->sge.ctrlq[i].q); | |
1952 | } | |
1953 | ||
1954 | static void enable_dbs(struct adapter *adap) | |
1955 | { | |
1956 | int i; | |
1957 | ||
1958 | for_each_ethrxq(&adap->sge, i) | |
05eb2389 | 1959 | enable_txq_db(adap, &adap->sge.ethtxq[i].q); |
ab677ff4 HS |
1960 | if (is_offload(adap)) { |
1961 | struct sge_uld_txq_info *txq_info = | |
1962 | adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
1963 | ||
1964 | if (txq_info) { | |
1965 | for_each_ofldtxq(&adap->sge, i) { | |
1966 | struct sge_uld_txq *txq = &txq_info->uldtxq[i]; | |
1967 | ||
1968 | enable_txq_db(adap, &txq->q); | |
1969 | } | |
1970 | } | |
1971 | } | |
3069ee9b | 1972 | for_each_port(adap, i) |
05eb2389 SW |
1973 | enable_txq_db(adap, &adap->sge.ctrlq[i].q); |
1974 | } | |
1975 | ||
1976 | static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) | |
1977 | { | |
0fbc81b3 HS |
1978 | enum cxgb4_uld type = CXGB4_ULD_RDMA; |
1979 | ||
1980 | if (adap->uld && adap->uld[type].handle) | |
1981 | adap->uld[type].control(adap->uld[type].handle, cmd); | |
05eb2389 SW |
1982 | } |
1983 | ||
1984 | static void process_db_full(struct work_struct *work) | |
1985 | { | |
1986 | struct adapter *adap; | |
1987 | ||
1988 | adap = container_of(work, struct adapter, db_full_task); | |
1989 | ||
1990 | drain_db_fifo(adap, dbfifo_drain_delay); | |
1991 | enable_dbs(adap); | |
1992 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); | |
3ccc6cf7 HS |
1993 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
1994 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
1995 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, | |
1996 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); | |
1997 | else | |
1998 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
1999 | DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); | |
3069ee9b VP |
2000 | } |
2001 | ||
2002 | static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) | |
2003 | { | |
2004 | u16 hw_pidx, hw_cidx; | |
2005 | int ret; | |
2006 | ||
05eb2389 | 2007 | spin_lock_irq(&q->db_lock); |
3069ee9b VP |
2008 | ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); |
2009 | if (ret) | |
2010 | goto out; | |
2011 | if (q->db_pidx != hw_pidx) { | |
2012 | u16 delta; | |
f612b815 | 2013 | u32 val; |
3069ee9b VP |
2014 | |
2015 | if (q->db_pidx >= hw_pidx) | |
2016 | delta = q->db_pidx - hw_pidx; | |
2017 | else | |
2018 | delta = q->size - hw_pidx + q->db_pidx; | |
f612b815 HS |
2019 | |
2020 | if (is_t4(adap->params.chip)) | |
2021 | val = PIDX_V(delta); | |
2022 | else | |
2023 | val = PIDX_T5_V(delta); | |
3069ee9b | 2024 | wmb(); |
f612b815 HS |
2025 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
2026 | QID_V(q->cntxt_id) | val); | |
3069ee9b VP |
2027 | } |
2028 | out: | |
2029 | q->db_disabled = 0; | |
05eb2389 SW |
2030 | q->db_pidx_inc = 0; |
2031 | spin_unlock_irq(&q->db_lock); | |
3069ee9b VP |
2032 | if (ret) |
2033 | CH_WARN(adap, "DB drop recovery failed.\n"); | |
2034 | } | |
0fbc81b3 | 2035 | |
3069ee9b VP |
2036 | static void recover_all_queues(struct adapter *adap) |
2037 | { | |
2038 | int i; | |
2039 | ||
2040 | for_each_ethrxq(&adap->sge, i) | |
2041 | sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); | |
ab677ff4 HS |
2042 | if (is_offload(adap)) { |
2043 | struct sge_uld_txq_info *txq_info = | |
2044 | adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
2045 | if (txq_info) { | |
2046 | for_each_ofldtxq(&adap->sge, i) { | |
2047 | struct sge_uld_txq *txq = &txq_info->uldtxq[i]; | |
2048 | ||
2049 | sync_txq_pidx(adap, &txq->q); | |
2050 | } | |
2051 | } | |
2052 | } | |
3069ee9b VP |
2053 | for_each_port(adap, i) |
2054 | sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); | |
2055 | } | |
2056 | ||
881806bc VP |
2057 | static void process_db_drop(struct work_struct *work) |
2058 | { | |
2059 | struct adapter *adap; | |
881806bc | 2060 | |
3069ee9b | 2061 | adap = container_of(work, struct adapter, db_drop_task); |
881806bc | 2062 | |
d14807dd | 2063 | if (is_t4(adap->params.chip)) { |
05eb2389 | 2064 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2065 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); |
05eb2389 | 2066 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2067 | recover_all_queues(adap); |
05eb2389 | 2068 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2069 | enable_dbs(adap); |
05eb2389 | 2070 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); |
3ccc6cf7 | 2071 | } else if (is_t5(adap->params.chip)) { |
2cc301d2 SR |
2072 | u32 dropped_db = t4_read_reg(adap, 0x010ac); |
2073 | u16 qid = (dropped_db >> 15) & 0x1ffff; | |
2074 | u16 pidx_inc = dropped_db & 0x1fff; | |
df64e4d3 HS |
2075 | u64 bar2_qoffset; |
2076 | unsigned int bar2_qid; | |
2077 | int ret; | |
2cc301d2 | 2078 | |
b2612722 | 2079 | ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, |
e0456717 | 2080 | 0, &bar2_qoffset, &bar2_qid); |
df64e4d3 HS |
2081 | if (ret) |
2082 | dev_err(adap->pdev_dev, "doorbell drop recovery: " | |
2083 | "qid=%d, pidx_inc=%d\n", qid, pidx_inc); | |
2084 | else | |
f612b815 | 2085 | writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), |
df64e4d3 | 2086 | adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); |
2cc301d2 SR |
2087 | |
2088 | /* Re-enable BAR2 WC */ | |
2089 | t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); | |
2090 | } | |
2091 | ||
3ccc6cf7 HS |
2092 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
2093 | t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); | |
881806bc VP |
2094 | } |
2095 | ||
2096 | void t4_db_full(struct adapter *adap) | |
2097 | { | |
d14807dd | 2098 | if (is_t4(adap->params.chip)) { |
05eb2389 SW |
2099 | disable_dbs(adap); |
2100 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
f612b815 HS |
2101 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, |
2102 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); | |
29aaee65 | 2103 | queue_work(adap->workq, &adap->db_full_task); |
2cc301d2 | 2104 | } |
881806bc VP |
2105 | } |
2106 | ||
2107 | void t4_db_dropped(struct adapter *adap) | |
2108 | { | |
05eb2389 SW |
2109 | if (is_t4(adap->params.chip)) { |
2110 | disable_dbs(adap); | |
2111 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
2112 | } | |
29aaee65 | 2113 | queue_work(adap->workq, &adap->db_drop_task); |
881806bc VP |
2114 | } |
2115 | ||
0fbc81b3 HS |
2116 | void t4_register_netevent_notifier(void) |
2117 | { | |
b8ff05a9 DM |
2118 | if (!netevent_registered) { |
2119 | register_netevent_notifier(&cxgb4_netevent_nb); | |
2120 | netevent_registered = true; | |
2121 | } | |
b8ff05a9 DM |
2122 | } |
2123 | ||
2124 | static void detach_ulds(struct adapter *adap) | |
2125 | { | |
2126 | unsigned int i; | |
2127 | ||
2128 | mutex_lock(&uld_mutex); | |
2129 | list_del(&adap->list_node); | |
6a146f3a | 2130 | |
b8ff05a9 | 2131 | for (i = 0; i < CXGB4_ULD_MAX; i++) |
6a146f3a | 2132 | if (adap->uld && adap->uld[i].handle) |
94cdb8bb HS |
2133 | adap->uld[i].state_change(adap->uld[i].handle, |
2134 | CXGB4_STATE_DETACH); | |
6a146f3a | 2135 | |
b8ff05a9 DM |
2136 | if (netevent_registered && list_empty(&adapter_list)) { |
2137 | unregister_netevent_notifier(&cxgb4_netevent_nb); | |
2138 | netevent_registered = false; | |
2139 | } | |
2140 | mutex_unlock(&uld_mutex); | |
2141 | } | |
2142 | ||
2143 | static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) | |
2144 | { | |
2145 | unsigned int i; | |
2146 | ||
2147 | mutex_lock(&uld_mutex); | |
2148 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
94cdb8bb HS |
2149 | if (adap->uld && adap->uld[i].handle) |
2150 | adap->uld[i].state_change(adap->uld[i].handle, | |
2151 | new_state); | |
b8ff05a9 DM |
2152 | mutex_unlock(&uld_mutex); |
2153 | } | |
2154 | ||
1bb60376 | 2155 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
2156 | static int cxgb4_inet6addr_handler(struct notifier_block *this, |
2157 | unsigned long event, void *data) | |
01bcca68 | 2158 | { |
b5a02f50 AB |
2159 | struct inet6_ifaddr *ifa = data; |
2160 | struct net_device *event_dev = ifa->idev->dev; | |
2161 | const struct device *parent = NULL; | |
2162 | #if IS_ENABLED(CONFIG_BONDING) | |
01bcca68 | 2163 | struct adapter *adap; |
b5a02f50 | 2164 | #endif |
d0d7b10b | 2165 | if (is_vlan_dev(event_dev)) |
b5a02f50 AB |
2166 | event_dev = vlan_dev_real_dev(event_dev); |
2167 | #if IS_ENABLED(CONFIG_BONDING) | |
2168 | if (event_dev->flags & IFF_MASTER) { | |
2169 | list_for_each_entry(adap, &adapter_list, list_node) { | |
2170 | switch (event) { | |
2171 | case NETDEV_UP: | |
2172 | cxgb4_clip_get(adap->port[0], | |
2173 | (const u32 *)ifa, 1); | |
2174 | break; | |
2175 | case NETDEV_DOWN: | |
2176 | cxgb4_clip_release(adap->port[0], | |
2177 | (const u32 *)ifa, 1); | |
2178 | break; | |
2179 | default: | |
2180 | break; | |
2181 | } | |
2182 | } | |
2183 | return NOTIFY_OK; | |
2184 | } | |
2185 | #endif | |
01bcca68 | 2186 | |
b5a02f50 AB |
2187 | if (event_dev) |
2188 | parent = event_dev->dev.parent; | |
01bcca68 | 2189 | |
b5a02f50 | 2190 | if (parent && parent->driver == &cxgb4_driver.driver) { |
01bcca68 VP |
2191 | switch (event) { |
2192 | case NETDEV_UP: | |
b5a02f50 | 2193 | cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2194 | break; |
2195 | case NETDEV_DOWN: | |
b5a02f50 | 2196 | cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2197 | break; |
2198 | default: | |
2199 | break; | |
2200 | } | |
2201 | } | |
b5a02f50 | 2202 | return NOTIFY_OK; |
01bcca68 VP |
2203 | } |
2204 | ||
b5a02f50 | 2205 | static bool inet6addr_registered; |
01bcca68 VP |
2206 | static struct notifier_block cxgb4_inet6addr_notifier = { |
2207 | .notifier_call = cxgb4_inet6addr_handler | |
2208 | }; | |
2209 | ||
01bcca68 VP |
2210 | static void update_clip(const struct adapter *adap) |
2211 | { | |
2212 | int i; | |
2213 | struct net_device *dev; | |
2214 | int ret; | |
2215 | ||
2216 | rcu_read_lock(); | |
2217 | ||
2218 | for (i = 0; i < MAX_NPORTS; i++) { | |
2219 | dev = adap->port[i]; | |
2220 | ret = 0; | |
2221 | ||
2222 | if (dev) | |
b5a02f50 | 2223 | ret = cxgb4_update_root_dev_clip(dev); |
01bcca68 VP |
2224 | |
2225 | if (ret < 0) | |
2226 | break; | |
2227 | } | |
2228 | rcu_read_unlock(); | |
2229 | } | |
1bb60376 | 2230 | #endif /* IS_ENABLED(CONFIG_IPV6) */ |
01bcca68 | 2231 | |
b8ff05a9 DM |
2232 | /** |
2233 | * cxgb_up - enable the adapter | |
2234 | * @adap: adapter being enabled | |
2235 | * | |
2236 | * Called when the first port is enabled, this function performs the | |
2237 | * actions necessary to make an adapter operational, such as completing | |
2238 | * the initialization of HW modules, and enabling interrupts. | |
2239 | * | |
2240 | * Must be called with the rtnl lock held. | |
2241 | */ | |
2242 | static int cxgb_up(struct adapter *adap) | |
2243 | { | |
aaefae9b | 2244 | int err; |
b8ff05a9 | 2245 | |
91060381 | 2246 | mutex_lock(&uld_mutex); |
aaefae9b DM |
2247 | err = setup_sge_queues(adap); |
2248 | if (err) | |
91060381 | 2249 | goto rel_lock; |
aaefae9b DM |
2250 | err = setup_rss(adap); |
2251 | if (err) | |
2252 | goto freeq; | |
b8ff05a9 DM |
2253 | |
2254 | if (adap->flags & USING_MSIX) { | |
aaefae9b | 2255 | name_msix_vecs(adap); |
b8ff05a9 DM |
2256 | err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, |
2257 | adap->msix_info[0].desc, adap); | |
2258 | if (err) | |
2259 | goto irq_err; | |
b8ff05a9 DM |
2260 | err = request_msix_queue_irqs(adap); |
2261 | if (err) { | |
2262 | free_irq(adap->msix_info[0].vec, adap); | |
2263 | goto irq_err; | |
2264 | } | |
2265 | } else { | |
2266 | err = request_irq(adap->pdev->irq, t4_intr_handler(adap), | |
2267 | (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, | |
b1a3c2b6 | 2268 | adap->port[0]->name, adap); |
b8ff05a9 DM |
2269 | if (err) |
2270 | goto irq_err; | |
2271 | } | |
e7519f99 | 2272 | |
b8ff05a9 DM |
2273 | enable_rx(adap); |
2274 | t4_sge_start(adap); | |
2275 | t4_intr_enable(adap); | |
aaefae9b | 2276 | adap->flags |= FULL_INIT_DONE; |
e7519f99 GG |
2277 | mutex_unlock(&uld_mutex); |
2278 | ||
b8ff05a9 | 2279 | notify_ulds(adap, CXGB4_STATE_UP); |
1bb60376 | 2280 | #if IS_ENABLED(CONFIG_IPV6) |
01bcca68 | 2281 | update_clip(adap); |
1bb60376 | 2282 | #endif |
fc08a01a HS |
2283 | /* Initialize hash mac addr list*/ |
2284 | INIT_LIST_HEAD(&adap->mac_hlist); | |
b8ff05a9 | 2285 | return err; |
91060381 | 2286 | |
b8ff05a9 DM |
2287 | irq_err: |
2288 | dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); | |
aaefae9b DM |
2289 | freeq: |
2290 | t4_free_sge_resources(adap); | |
91060381 RR |
2291 | rel_lock: |
2292 | mutex_unlock(&uld_mutex); | |
2293 | return err; | |
b8ff05a9 DM |
2294 | } |
2295 | ||
2296 | static void cxgb_down(struct adapter *adapter) | |
2297 | { | |
b8ff05a9 | 2298 | cancel_work_sync(&adapter->tid_release_task); |
881806bc VP |
2299 | cancel_work_sync(&adapter->db_full_task); |
2300 | cancel_work_sync(&adapter->db_drop_task); | |
b8ff05a9 | 2301 | adapter->tid_release_task_busy = false; |
204dc3c0 | 2302 | adapter->tid_release_head = NULL; |
b8ff05a9 | 2303 | |
aaefae9b DM |
2304 | t4_sge_stop(adapter); |
2305 | t4_free_sge_resources(adapter); | |
2306 | adapter->flags &= ~FULL_INIT_DONE; | |
b8ff05a9 DM |
2307 | } |
2308 | ||
2309 | /* | |
2310 | * net_device operations | |
2311 | */ | |
2312 | static int cxgb_open(struct net_device *dev) | |
2313 | { | |
2314 | int err; | |
2315 | struct port_info *pi = netdev_priv(dev); | |
2316 | struct adapter *adapter = pi->adapter; | |
2317 | ||
6a3c869a DM |
2318 | netif_carrier_off(dev); |
2319 | ||
aaefae9b DM |
2320 | if (!(adapter->flags & FULL_INIT_DONE)) { |
2321 | err = cxgb_up(adapter); | |
2322 | if (err < 0) | |
2323 | return err; | |
2324 | } | |
b8ff05a9 | 2325 | |
2061ec3f GG |
2326 | /* It's possible that the basic port information could have |
2327 | * changed since we first read it. | |
2328 | */ | |
2329 | err = t4_update_port_info(pi); | |
2330 | if (err < 0) | |
2331 | return err; | |
2332 | ||
f68707b8 DM |
2333 | err = link_start(dev); |
2334 | if (!err) | |
2335 | netif_tx_start_all_queues(dev); | |
2336 | return err; | |
b8ff05a9 DM |
2337 | } |
2338 | ||
2339 | static int cxgb_close(struct net_device *dev) | |
2340 | { | |
b8ff05a9 DM |
2341 | struct port_info *pi = netdev_priv(dev); |
2342 | struct adapter *adapter = pi->adapter; | |
ba581f77 | 2343 | int ret; |
b8ff05a9 DM |
2344 | |
2345 | netif_tx_stop_all_queues(dev); | |
2346 | netif_carrier_off(dev); | |
e2f4f4e9 AV |
2347 | ret = t4_enable_pi_params(adapter, adapter->pf, pi, |
2348 | false, false, false); | |
ba581f77 GG |
2349 | #ifdef CONFIG_CHELSIO_T4_DCB |
2350 | cxgb4_dcb_reset(dev); | |
2351 | dcb_tx_queue_prio_enable(dev, false); | |
2352 | #endif | |
2353 | return ret; | |
b8ff05a9 DM |
2354 | } |
2355 | ||
dca4faeb | 2356 | int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, |
793dad94 VP |
2357 | __be32 sip, __be16 sport, __be16 vlan, |
2358 | unsigned int queue, unsigned char port, unsigned char mask) | |
dca4faeb VP |
2359 | { |
2360 | int ret; | |
2361 | struct filter_entry *f; | |
2362 | struct adapter *adap; | |
2363 | int i; | |
2364 | u8 *val; | |
2365 | ||
2366 | adap = netdev2adap(dev); | |
2367 | ||
1cab775c | 2368 | /* Adjust stid to correct filter index */ |
470c60c4 | 2369 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2370 | stid += adap->tids.nftids; |
2371 | ||
dca4faeb VP |
2372 | /* Check to make sure the filter requested is writable ... |
2373 | */ | |
2374 | f = &adap->tids.ftid_tab[stid]; | |
2375 | ret = writable_filter(f); | |
2376 | if (ret) | |
2377 | return ret; | |
2378 | ||
2379 | /* Clear out any old resources being used by the filter before | |
2380 | * we start constructing the new filter. | |
2381 | */ | |
2382 | if (f->valid) | |
2383 | clear_filter(adap, f); | |
2384 | ||
2385 | /* Clear out filter specifications */ | |
2386 | memset(&f->fs, 0, sizeof(struct ch_filter_specification)); | |
2387 | f->fs.val.lport = cpu_to_be16(sport); | |
2388 | f->fs.mask.lport = ~0; | |
2389 | val = (u8 *)&sip; | |
793dad94 | 2390 | if ((val[0] | val[1] | val[2] | val[3]) != 0) { |
dca4faeb VP |
2391 | for (i = 0; i < 4; i++) { |
2392 | f->fs.val.lip[i] = val[i]; | |
2393 | f->fs.mask.lip[i] = ~0; | |
2394 | } | |
0d804338 | 2395 | if (adap->params.tp.vlan_pri_map & PORT_F) { |
793dad94 VP |
2396 | f->fs.val.iport = port; |
2397 | f->fs.mask.iport = mask; | |
2398 | } | |
2399 | } | |
dca4faeb | 2400 | |
0d804338 | 2401 | if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { |
7c89e555 KS |
2402 | f->fs.val.proto = IPPROTO_TCP; |
2403 | f->fs.mask.proto = ~0; | |
2404 | } | |
2405 | ||
dca4faeb VP |
2406 | f->fs.dirsteer = 1; |
2407 | f->fs.iq = queue; | |
2408 | /* Mark filter as locked */ | |
2409 | f->locked = 1; | |
2410 | f->fs.rpttid = 1; | |
2411 | ||
6b254afd GG |
2412 | /* Save the actual tid. We need this to get the corresponding |
2413 | * filter entry structure in filter_rpl. | |
2414 | */ | |
2415 | f->tid = stid + adap->tids.ftid_base; | |
dca4faeb VP |
2416 | ret = set_filter_wr(adap, stid); |
2417 | if (ret) { | |
2418 | clear_filter(adap, f); | |
2419 | return ret; | |
2420 | } | |
2421 | ||
2422 | return 0; | |
2423 | } | |
2424 | EXPORT_SYMBOL(cxgb4_create_server_filter); | |
2425 | ||
2426 | int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, | |
2427 | unsigned int queue, bool ipv6) | |
2428 | { | |
dca4faeb VP |
2429 | struct filter_entry *f; |
2430 | struct adapter *adap; | |
2431 | ||
2432 | adap = netdev2adap(dev); | |
1cab775c VP |
2433 | |
2434 | /* Adjust stid to correct filter index */ | |
470c60c4 | 2435 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2436 | stid += adap->tids.nftids; |
2437 | ||
dca4faeb VP |
2438 | f = &adap->tids.ftid_tab[stid]; |
2439 | /* Unlock the filter */ | |
2440 | f->locked = 0; | |
2441 | ||
8c14846d | 2442 | return delete_filter(adap, stid); |
dca4faeb VP |
2443 | } |
2444 | EXPORT_SYMBOL(cxgb4_remove_server_filter); | |
2445 | ||
bc1f4470 | 2446 | static void cxgb_get_stats(struct net_device *dev, |
2447 | struct rtnl_link_stats64 *ns) | |
b8ff05a9 DM |
2448 | { |
2449 | struct port_stats stats; | |
2450 | struct port_info *p = netdev_priv(dev); | |
2451 | struct adapter *adapter = p->adapter; | |
b8ff05a9 | 2452 | |
9fe6cb58 GS |
2453 | /* Block retrieving statistics during EEH error |
2454 | * recovery. Otherwise, the recovery might fail | |
2455 | * and the PCI device will be removed permanently | |
2456 | */ | |
b8ff05a9 | 2457 | spin_lock(&adapter->stats_lock); |
9fe6cb58 GS |
2458 | if (!netif_device_present(dev)) { |
2459 | spin_unlock(&adapter->stats_lock); | |
bc1f4470 | 2460 | return; |
9fe6cb58 | 2461 | } |
a4cfd929 HS |
2462 | t4_get_port_stats_offset(adapter, p->tx_chan, &stats, |
2463 | &p->stats_base); | |
b8ff05a9 DM |
2464 | spin_unlock(&adapter->stats_lock); |
2465 | ||
2466 | ns->tx_bytes = stats.tx_octets; | |
2467 | ns->tx_packets = stats.tx_frames; | |
2468 | ns->rx_bytes = stats.rx_octets; | |
2469 | ns->rx_packets = stats.rx_frames; | |
2470 | ns->multicast = stats.rx_mcast_frames; | |
2471 | ||
2472 | /* detailed rx_errors */ | |
2473 | ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + | |
2474 | stats.rx_runt; | |
2475 | ns->rx_over_errors = 0; | |
2476 | ns->rx_crc_errors = stats.rx_fcs_err; | |
2477 | ns->rx_frame_errors = stats.rx_symbol_err; | |
b93f79be | 2478 | ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 + |
b8ff05a9 DM |
2479 | stats.rx_ovflow2 + stats.rx_ovflow3 + |
2480 | stats.rx_trunc0 + stats.rx_trunc1 + | |
2481 | stats.rx_trunc2 + stats.rx_trunc3; | |
2482 | ns->rx_missed_errors = 0; | |
2483 | ||
2484 | /* detailed tx_errors */ | |
2485 | ns->tx_aborted_errors = 0; | |
2486 | ns->tx_carrier_errors = 0; | |
2487 | ns->tx_fifo_errors = 0; | |
2488 | ns->tx_heartbeat_errors = 0; | |
2489 | ns->tx_window_errors = 0; | |
2490 | ||
2491 | ns->tx_errors = stats.tx_error_frames; | |
2492 | ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + | |
2493 | ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; | |
b8ff05a9 DM |
2494 | } |
2495 | ||
2496 | static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
2497 | { | |
060e0c75 | 2498 | unsigned int mbox; |
b8ff05a9 DM |
2499 | int ret = 0, prtad, devad; |
2500 | struct port_info *pi = netdev_priv(dev); | |
a4569504 | 2501 | struct adapter *adapter = pi->adapter; |
b8ff05a9 DM |
2502 | struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; |
2503 | ||
2504 | switch (cmd) { | |
2505 | case SIOCGMIIPHY: | |
2506 | if (pi->mdio_addr < 0) | |
2507 | return -EOPNOTSUPP; | |
2508 | data->phy_id = pi->mdio_addr; | |
2509 | break; | |
2510 | case SIOCGMIIREG: | |
2511 | case SIOCSMIIREG: | |
2512 | if (mdio_phy_id_is_c45(data->phy_id)) { | |
2513 | prtad = mdio_phy_id_prtad(data->phy_id); | |
2514 | devad = mdio_phy_id_devad(data->phy_id); | |
2515 | } else if (data->phy_id < 32) { | |
2516 | prtad = data->phy_id; | |
2517 | devad = 0; | |
2518 | data->reg_num &= 0x1f; | |
2519 | } else | |
2520 | return -EINVAL; | |
2521 | ||
b2612722 | 2522 | mbox = pi->adapter->pf; |
b8ff05a9 | 2523 | if (cmd == SIOCGMIIREG) |
060e0c75 | 2524 | ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
2525 | data->reg_num, &data->val_out); |
2526 | else | |
060e0c75 | 2527 | ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
2528 | data->reg_num, data->val_in); |
2529 | break; | |
5e2a5ebc HS |
2530 | case SIOCGHWTSTAMP: |
2531 | return copy_to_user(req->ifr_data, &pi->tstamp_config, | |
2532 | sizeof(pi->tstamp_config)) ? | |
2533 | -EFAULT : 0; | |
2534 | case SIOCSHWTSTAMP: | |
2535 | if (copy_from_user(&pi->tstamp_config, req->ifr_data, | |
2536 | sizeof(pi->tstamp_config))) | |
2537 | return -EFAULT; | |
2538 | ||
a4569504 AG |
2539 | if (!is_t4(adapter->params.chip)) { |
2540 | switch (pi->tstamp_config.tx_type) { | |
2541 | case HWTSTAMP_TX_OFF: | |
2542 | case HWTSTAMP_TX_ON: | |
2543 | break; | |
2544 | default: | |
2545 | return -ERANGE; | |
2546 | } | |
2547 | ||
2548 | switch (pi->tstamp_config.rx_filter) { | |
2549 | case HWTSTAMP_FILTER_NONE: | |
2550 | pi->rxtstamp = false; | |
2551 | break; | |
2552 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
2553 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
2554 | cxgb4_ptprx_timestamping(pi, pi->port_id, | |
2555 | PTP_TS_L4); | |
2556 | break; | |
2557 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
2558 | cxgb4_ptprx_timestamping(pi, pi->port_id, | |
2559 | PTP_TS_L2_L4); | |
2560 | break; | |
2561 | case HWTSTAMP_FILTER_ALL: | |
2562 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
2563 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
2564 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
2565 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
2566 | pi->rxtstamp = true; | |
2567 | break; | |
2568 | default: | |
2569 | pi->tstamp_config.rx_filter = | |
2570 | HWTSTAMP_FILTER_NONE; | |
2571 | return -ERANGE; | |
2572 | } | |
2573 | ||
2574 | if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) && | |
2575 | (pi->tstamp_config.rx_filter == | |
2576 | HWTSTAMP_FILTER_NONE)) { | |
2577 | if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0) | |
2578 | pi->ptp_enable = false; | |
2579 | } | |
2580 | ||
2581 | if (pi->tstamp_config.rx_filter != | |
2582 | HWTSTAMP_FILTER_NONE) { | |
2583 | if (cxgb4_ptp_redirect_rx_packet(adapter, | |
2584 | pi) >= 0) | |
2585 | pi->ptp_enable = true; | |
2586 | } | |
2587 | } else { | |
2588 | /* For T4 Adapters */ | |
2589 | switch (pi->tstamp_config.rx_filter) { | |
2590 | case HWTSTAMP_FILTER_NONE: | |
5e2a5ebc HS |
2591 | pi->rxtstamp = false; |
2592 | break; | |
a4569504 | 2593 | case HWTSTAMP_FILTER_ALL: |
5e2a5ebc HS |
2594 | pi->rxtstamp = true; |
2595 | break; | |
a4569504 AG |
2596 | default: |
2597 | pi->tstamp_config.rx_filter = | |
2598 | HWTSTAMP_FILTER_NONE; | |
5e2a5ebc | 2599 | return -ERANGE; |
a4569504 | 2600 | } |
5e2a5ebc | 2601 | } |
5e2a5ebc HS |
2602 | return copy_to_user(req->ifr_data, &pi->tstamp_config, |
2603 | sizeof(pi->tstamp_config)) ? | |
2604 | -EFAULT : 0; | |
b8ff05a9 DM |
2605 | default: |
2606 | return -EOPNOTSUPP; | |
2607 | } | |
2608 | return ret; | |
2609 | } | |
2610 | ||
2611 | static void cxgb_set_rxmode(struct net_device *dev) | |
2612 | { | |
2613 | /* unfortunately we can't return errors to the stack */ | |
2614 | set_rxmode(dev, -1, false); | |
2615 | } | |
2616 | ||
2617 | static int cxgb_change_mtu(struct net_device *dev, int new_mtu) | |
2618 | { | |
2619 | int ret; | |
2620 | struct port_info *pi = netdev_priv(dev); | |
2621 | ||
b2612722 | 2622 | ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, |
060e0c75 | 2623 | -1, -1, -1, true); |
b8ff05a9 DM |
2624 | if (!ret) |
2625 | dev->mtu = new_mtu; | |
2626 | return ret; | |
2627 | } | |
2628 | ||
858aa65c | 2629 | #ifdef CONFIG_PCI_IOV |
baf50868 | 2630 | static int cxgb4_mgmt_open(struct net_device *dev) |
e7b48a32 HS |
2631 | { |
2632 | /* Turn carrier off since we don't have to transmit anything on this | |
2633 | * interface. | |
2634 | */ | |
2635 | netif_carrier_off(dev); | |
2636 | return 0; | |
2637 | } | |
2638 | ||
661dbeb9 | 2639 | /* Fill MAC address that will be assigned by the FW */ |
baf50868 | 2640 | static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap) |
661dbeb9 | 2641 | { |
661dbeb9 | 2642 | u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN]; |
baf50868 GG |
2643 | unsigned int i, vf, nvfs; |
2644 | u16 a, b; | |
661dbeb9 HS |
2645 | int err; |
2646 | u8 *na; | |
661dbeb9 | 2647 | |
baf50868 GG |
2648 | adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev, |
2649 | PCI_CAP_ID_VPD); | |
661dbeb9 | 2650 | err = t4_get_raw_vpd_params(adap, &adap->params.vpd); |
baf50868 GG |
2651 | if (err) |
2652 | return; | |
2653 | ||
2654 | na = adap->params.vpd.na; | |
2655 | for (i = 0; i < ETH_ALEN; i++) | |
2656 | hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + | |
2657 | hex2val(na[2 * i + 1])); | |
2658 | ||
2659 | a = (hw_addr[0] << 8) | hw_addr[1]; | |
2660 | b = (hw_addr[1] << 8) | hw_addr[2]; | |
2661 | a ^= b; | |
2662 | a |= 0x0200; /* locally assigned Ethernet MAC address */ | |
2663 | a &= ~0x0100; /* not a multicast Ethernet MAC address */ | |
2664 | macaddr[0] = a >> 8; | |
2665 | macaddr[1] = a & 0xff; | |
2666 | ||
2667 | for (i = 2; i < 5; i++) | |
2668 | macaddr[i] = hw_addr[i + 1]; | |
2669 | ||
2670 | for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev); | |
2671 | vf < nvfs; vf++) { | |
2672 | macaddr[5] = adap->pf * 16 + vf; | |
2673 | ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr); | |
661dbeb9 HS |
2674 | } |
2675 | } | |
2676 | ||
baf50868 | 2677 | static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
858aa65c HS |
2678 | { |
2679 | struct port_info *pi = netdev_priv(dev); | |
2680 | struct adapter *adap = pi->adapter; | |
661dbeb9 | 2681 | int ret; |
858aa65c HS |
2682 | |
2683 | /* verify MAC addr is valid */ | |
2684 | if (!is_valid_ether_addr(mac)) { | |
2685 | dev_err(pi->adapter->pdev_dev, | |
2686 | "Invalid Ethernet address %pM for VF %d\n", | |
2687 | mac, vf); | |
2688 | return -EINVAL; | |
2689 | } | |
2690 | ||
2691 | dev_info(pi->adapter->pdev_dev, | |
2692 | "Setting MAC %pM on VF %d\n", mac, vf); | |
661dbeb9 HS |
2693 | ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac); |
2694 | if (!ret) | |
2695 | ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac); | |
2696 | return ret; | |
2697 | } | |
2698 | ||
baf50868 GG |
2699 | static int cxgb4_mgmt_get_vf_config(struct net_device *dev, |
2700 | int vf, struct ifla_vf_info *ivi) | |
661dbeb9 HS |
2701 | { |
2702 | struct port_info *pi = netdev_priv(dev); | |
2703 | struct adapter *adap = pi->adapter; | |
bd79acee | 2704 | struct vf_info *vfinfo; |
661dbeb9 HS |
2705 | |
2706 | if (vf >= adap->num_vfs) | |
2707 | return -EINVAL; | |
bd79acee AV |
2708 | vfinfo = &adap->vfinfo[vf]; |
2709 | ||
661dbeb9 | 2710 | ivi->vf = vf; |
bd79acee | 2711 | ivi->max_tx_rate = vfinfo->tx_rate; |
8ea4fae9 | 2712 | ivi->min_tx_rate = 0; |
bd79acee AV |
2713 | ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr); |
2714 | ivi->vlan = vfinfo->vlan; | |
661dbeb9 | 2715 | return 0; |
858aa65c | 2716 | } |
96fe11f2 | 2717 | |
baf50868 GG |
2718 | static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev, |
2719 | struct netdev_phys_item_id *ppid) | |
96fe11f2 GG |
2720 | { |
2721 | struct port_info *pi = netdev_priv(dev); | |
2722 | unsigned int phy_port_id; | |
2723 | ||
2724 | phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id; | |
2725 | ppid->id_len = sizeof(phy_port_id); | |
2726 | memcpy(ppid->id, &phy_port_id, ppid->id_len); | |
2727 | return 0; | |
2728 | } | |
2729 | ||
baf50868 GG |
2730 | static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf, |
2731 | int min_tx_rate, int max_tx_rate) | |
8ea4fae9 GG |
2732 | { |
2733 | struct port_info *pi = netdev_priv(dev); | |
2734 | struct adapter *adap = pi->adapter; | |
c3168cab | 2735 | unsigned int link_ok, speed, mtu; |
8ea4fae9 GG |
2736 | u32 fw_pfvf, fw_class; |
2737 | int class_id = vf; | |
c3168cab | 2738 | int ret; |
8ea4fae9 GG |
2739 | u16 pktsize; |
2740 | ||
2741 | if (vf >= adap->num_vfs) | |
2742 | return -EINVAL; | |
2743 | ||
2744 | if (min_tx_rate) { | |
2745 | dev_err(adap->pdev_dev, | |
2746 | "Min tx rate (%d) (> 0) for VF %d is Invalid.\n", | |
2747 | min_tx_rate, vf); | |
2748 | return -EINVAL; | |
2749 | } | |
c3168cab | 2750 | |
b5e281ab GG |
2751 | if (max_tx_rate == 0) { |
2752 | /* unbind VF to to any Traffic Class */ | |
2753 | fw_pfvf = | |
2754 | (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | | |
2755 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); | |
2756 | fw_class = 0xffffffff; | |
2757 | ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, | |
2758 | &fw_pfvf, &fw_class); | |
2759 | if (ret) { | |
2760 | dev_err(adap->pdev_dev, | |
2761 | "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n", | |
2762 | ret, adap->pf, vf); | |
2763 | return -EINVAL; | |
2764 | } | |
2765 | dev_info(adap->pdev_dev, | |
2766 | "PF %d VF %d is unbound from TX Rate Limiting\n", | |
2767 | adap->pf, vf); | |
2768 | adap->vfinfo[vf].tx_rate = 0; | |
2769 | return 0; | |
2770 | } | |
2771 | ||
c3168cab | 2772 | ret = t4_get_link_params(pi, &link_ok, &speed, &mtu); |
8ea4fae9 GG |
2773 | if (ret != FW_SUCCESS) { |
2774 | dev_err(adap->pdev_dev, | |
c3168cab | 2775 | "Failed to get link information for VF %d\n", vf); |
8ea4fae9 GG |
2776 | return -EINVAL; |
2777 | } | |
c3168cab | 2778 | |
8ea4fae9 GG |
2779 | if (!link_ok) { |
2780 | dev_err(adap->pdev_dev, "Link down for VF %d\n", vf); | |
2781 | return -EINVAL; | |
2782 | } | |
8ea4fae9 GG |
2783 | |
2784 | if (max_tx_rate > speed) { | |
2785 | dev_err(adap->pdev_dev, | |
2786 | "Max tx rate %d for VF %d can't be > link-speed %u", | |
2787 | max_tx_rate, vf, speed); | |
2788 | return -EINVAL; | |
2789 | } | |
c3168cab GG |
2790 | |
2791 | pktsize = mtu; | |
8ea4fae9 GG |
2792 | /* subtract ethhdr size and 4 bytes crc since, f/w appends it */ |
2793 | pktsize = pktsize - sizeof(struct ethhdr) - 4; | |
2794 | /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */ | |
2795 | pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr); | |
2796 | /* configure Traffic Class for rate-limiting */ | |
2797 | ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET, | |
2798 | SCHED_CLASS_LEVEL_CL_RL, | |
2799 | SCHED_CLASS_MODE_CLASS, | |
2800 | SCHED_CLASS_RATEUNIT_BITS, | |
2801 | SCHED_CLASS_RATEMODE_ABS, | |
c3168cab | 2802 | pi->tx_chan, class_id, 0, |
8ea4fae9 GG |
2803 | max_tx_rate * 1000, 0, pktsize); |
2804 | if (ret) { | |
2805 | dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n", | |
2806 | ret); | |
2807 | return -EINVAL; | |
2808 | } | |
2809 | dev_info(adap->pdev_dev, | |
2810 | "Class %d with MSS %u configured with rate %u\n", | |
2811 | class_id, pktsize, max_tx_rate); | |
2812 | ||
2813 | /* bind VF to configured Traffic Class */ | |
2814 | fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | | |
2815 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); | |
2816 | fw_class = class_id; | |
2817 | ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf, | |
2818 | &fw_class); | |
2819 | if (ret) { | |
2820 | dev_err(adap->pdev_dev, | |
b5e281ab GG |
2821 | "Err %d in binding PF %d VF %d to Traffic Class %d\n", |
2822 | ret, adap->pf, vf, class_id); | |
8ea4fae9 GG |
2823 | return -EINVAL; |
2824 | } | |
2825 | dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n", | |
2826 | adap->pf, vf, class_id); | |
2827 | adap->vfinfo[vf].tx_rate = max_tx_rate; | |
2828 | return 0; | |
2829 | } | |
2830 | ||
9d5fd927 GG |
2831 | static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf, |
2832 | u16 vlan, u8 qos, __be16 vlan_proto) | |
2833 | { | |
2834 | struct port_info *pi = netdev_priv(dev); | |
2835 | struct adapter *adap = pi->adapter; | |
2836 | int ret; | |
2837 | ||
2838 | if (vf >= adap->num_vfs || vlan > 4095 || qos > 7) | |
2839 | return -EINVAL; | |
2840 | ||
2841 | if (vlan_proto != htons(ETH_P_8021Q) || qos != 0) | |
2842 | return -EPROTONOSUPPORT; | |
2843 | ||
2844 | ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan); | |
2845 | if (!ret) { | |
2846 | adap->vfinfo[vf].vlan = vlan; | |
2847 | return 0; | |
2848 | } | |
2849 | ||
2850 | dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n", | |
2851 | ret, (vlan ? "setting" : "clearing"), adap->pf, vf); | |
2852 | return ret; | |
2853 | } | |
2854 | #endif /* CONFIG_PCI_IOV */ | |
858aa65c | 2855 | |
b8ff05a9 DM |
2856 | static int cxgb_set_mac_addr(struct net_device *dev, void *p) |
2857 | { | |
2858 | int ret; | |
2859 | struct sockaddr *addr = p; | |
2860 | struct port_info *pi = netdev_priv(dev); | |
2861 | ||
2862 | if (!is_valid_ether_addr(addr->sa_data)) | |
504f9b5a | 2863 | return -EADDRNOTAVAIL; |
b8ff05a9 | 2864 | |
b2612722 | 2865 | ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, |
060e0c75 | 2866 | pi->xact_addr_filt, addr->sa_data, true, true); |
b8ff05a9 DM |
2867 | if (ret < 0) |
2868 | return ret; | |
2869 | ||
2870 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
2871 | pi->xact_addr_filt = ret; | |
2872 | return 0; | |
2873 | } | |
2874 | ||
b8ff05a9 DM |
2875 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2876 | static void cxgb_netpoll(struct net_device *dev) | |
2877 | { | |
2878 | struct port_info *pi = netdev_priv(dev); | |
2879 | struct adapter *adap = pi->adapter; | |
2880 | ||
2881 | if (adap->flags & USING_MSIX) { | |
2882 | int i; | |
2883 | struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; | |
2884 | ||
2885 | for (i = pi->nqsets; i; i--, rx++) | |
2886 | t4_sge_intr_msix(0, &rx->rspq); | |
2887 | } else | |
2888 | t4_intr_handler(adap)(0, adap); | |
2889 | } | |
2890 | #endif | |
2891 | ||
10a2604e RL |
2892 | static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate) |
2893 | { | |
2894 | struct port_info *pi = netdev_priv(dev); | |
2895 | struct adapter *adap = pi->adapter; | |
2896 | struct sched_class *e; | |
2897 | struct ch_sched_params p; | |
2898 | struct ch_sched_queue qe; | |
2899 | u32 req_rate; | |
2900 | int err = 0; | |
2901 | ||
2902 | if (!can_sched(dev)) | |
2903 | return -ENOTSUPP; | |
2904 | ||
2905 | if (index < 0 || index > pi->nqsets - 1) | |
2906 | return -EINVAL; | |
2907 | ||
2908 | if (!(adap->flags & FULL_INIT_DONE)) { | |
2909 | dev_err(adap->pdev_dev, | |
2910 | "Failed to rate limit on queue %d. Link Down?\n", | |
2911 | index); | |
2912 | return -EINVAL; | |
2913 | } | |
2914 | ||
2915 | /* Convert from Mbps to Kbps */ | |
b3c594ab | 2916 | req_rate = rate * 1000; |
10a2604e | 2917 | |
d185efc1 | 2918 | /* Max rate is 100 Gbps */ |
b3c594ab | 2919 | if (req_rate > SCHED_MAX_RATE_KBPS) { |
10a2604e | 2920 | dev_err(adap->pdev_dev, |
d185efc1 | 2921 | "Invalid rate %u Mbps, Max rate is %u Mbps\n", |
b3c594ab | 2922 | rate, SCHED_MAX_RATE_KBPS / 1000); |
10a2604e RL |
2923 | return -ERANGE; |
2924 | } | |
2925 | ||
2926 | /* First unbind the queue from any existing class */ | |
2927 | memset(&qe, 0, sizeof(qe)); | |
2928 | qe.queue = index; | |
2929 | qe.class = SCHED_CLS_NONE; | |
2930 | ||
2931 | err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE); | |
2932 | if (err) { | |
2933 | dev_err(adap->pdev_dev, | |
2934 | "Unbinding Queue %d on port %d fail. Err: %d\n", | |
2935 | index, pi->port_id, err); | |
2936 | return err; | |
2937 | } | |
2938 | ||
2939 | /* Queue already unbound */ | |
2940 | if (!req_rate) | |
2941 | return 0; | |
2942 | ||
2943 | /* Fetch any available unused or matching scheduling class */ | |
2944 | memset(&p, 0, sizeof(p)); | |
2945 | p.type = SCHED_CLASS_TYPE_PACKET; | |
2946 | p.u.params.level = SCHED_CLASS_LEVEL_CL_RL; | |
2947 | p.u.params.mode = SCHED_CLASS_MODE_CLASS; | |
2948 | p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS; | |
2949 | p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS; | |
2950 | p.u.params.channel = pi->tx_chan; | |
2951 | p.u.params.class = SCHED_CLS_NONE; | |
2952 | p.u.params.minrate = 0; | |
2953 | p.u.params.maxrate = req_rate; | |
2954 | p.u.params.weight = 0; | |
2955 | p.u.params.pktsize = dev->mtu; | |
2956 | ||
2957 | e = cxgb4_sched_class_alloc(dev, &p); | |
2958 | if (!e) | |
2959 | return -ENOMEM; | |
2960 | ||
2961 | /* Bind the queue to a scheduling class */ | |
2962 | memset(&qe, 0, sizeof(qe)); | |
2963 | qe.queue = index; | |
2964 | qe.class = e->idx; | |
2965 | ||
2966 | err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE); | |
2967 | if (err) | |
2968 | dev_err(adap->pdev_dev, | |
2969 | "Queue rate limiting failed. Err: %d\n", err); | |
2970 | return err; | |
2971 | } | |
2972 | ||
6a345b3d KS |
2973 | static int cxgb_setup_tc_flower(struct net_device *dev, |
2974 | struct tc_cls_flower_offload *cls_flower) | |
2975 | { | |
6a345b3d KS |
2976 | switch (cls_flower->command) { |
2977 | case TC_CLSFLOWER_REPLACE: | |
2978 | return cxgb4_tc_flower_replace(dev, cls_flower); | |
2979 | case TC_CLSFLOWER_DESTROY: | |
2980 | return cxgb4_tc_flower_destroy(dev, cls_flower); | |
2981 | case TC_CLSFLOWER_STATS: | |
2982 | return cxgb4_tc_flower_stats(dev, cls_flower); | |
2983 | default: | |
2984 | return -EOPNOTSUPP; | |
2985 | } | |
2986 | } | |
2987 | ||
f7323043 | 2988 | static int cxgb_setup_tc_cls_u32(struct net_device *dev, |
f7323043 JP |
2989 | struct tc_cls_u32_offload *cls_u32) |
2990 | { | |
f7323043 JP |
2991 | switch (cls_u32->command) { |
2992 | case TC_CLSU32_NEW_KNODE: | |
2993 | case TC_CLSU32_REPLACE_KNODE: | |
5fd9fc4e | 2994 | return cxgb4_config_knode(dev, cls_u32); |
f7323043 | 2995 | case TC_CLSU32_DELETE_KNODE: |
5fd9fc4e | 2996 | return cxgb4_delete_knode(dev, cls_u32); |
f7323043 JP |
2997 | default: |
2998 | return -EOPNOTSUPP; | |
2999 | } | |
3000 | } | |
3001 | ||
cd019e91 JP |
3002 | static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
3003 | void *cb_priv) | |
d8931847 | 3004 | { |
cd019e91 | 3005 | struct net_device *dev = cb_priv; |
d8931847 RL |
3006 | struct port_info *pi = netdev2pinfo(dev); |
3007 | struct adapter *adap = netdev2adap(dev); | |
3008 | ||
3009 | if (!(adap->flags & FULL_INIT_DONE)) { | |
3010 | dev_err(adap->pdev_dev, | |
3011 | "Failed to setup tc on port %d. Link Down?\n", | |
3012 | pi->port_id); | |
3013 | return -EINVAL; | |
3014 | } | |
3015 | ||
2a84bbaf | 3016 | if (!tc_cls_can_offload_and_chain0(dev, type_data)) |
44ae12a7 JP |
3017 | return -EOPNOTSUPP; |
3018 | ||
f7323043 JP |
3019 | switch (type) { |
3020 | case TC_SETUP_CLSU32: | |
de4784ca | 3021 | return cxgb_setup_tc_cls_u32(dev, type_data); |
6a345b3d KS |
3022 | case TC_SETUP_CLSFLOWER: |
3023 | return cxgb_setup_tc_flower(dev, type_data); | |
f7323043 JP |
3024 | default: |
3025 | return -EOPNOTSUPP; | |
d8931847 | 3026 | } |
d8931847 RL |
3027 | } |
3028 | ||
cd019e91 JP |
3029 | static int cxgb_setup_tc_block(struct net_device *dev, |
3030 | struct tc_block_offload *f) | |
3031 | { | |
3032 | struct port_info *pi = netdev2pinfo(dev); | |
3033 | ||
3034 | if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) | |
3035 | return -EOPNOTSUPP; | |
3036 | ||
3037 | switch (f->command) { | |
3038 | case TC_BLOCK_BIND: | |
3039 | return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb, | |
60513bd8 | 3040 | pi, dev, f->extack); |
cd019e91 JP |
3041 | case TC_BLOCK_UNBIND: |
3042 | tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi); | |
3043 | return 0; | |
3044 | default: | |
3045 | return -EOPNOTSUPP; | |
3046 | } | |
3047 | } | |
3048 | ||
3049 | static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type, | |
3050 | void *type_data) | |
3051 | { | |
3052 | switch (type) { | |
cd019e91 JP |
3053 | case TC_SETUP_BLOCK: |
3054 | return cxgb_setup_tc_block(dev, type_data); | |
3055 | default: | |
3056 | return -EOPNOTSUPP; | |
3057 | } | |
3058 | } | |
3059 | ||
846eac3f GG |
3060 | static void cxgb_del_udp_tunnel(struct net_device *netdev, |
3061 | struct udp_tunnel_info *ti) | |
3062 | { | |
3063 | struct port_info *pi = netdev_priv(netdev); | |
3064 | struct adapter *adapter = pi->adapter; | |
3065 | unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); | |
3066 | u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; | |
3067 | int ret = 0, i; | |
3068 | ||
3069 | if (chip_ver < CHELSIO_T6) | |
3070 | return; | |
3071 | ||
3072 | switch (ti->type) { | |
3073 | case UDP_TUNNEL_TYPE_VXLAN: | |
3074 | if (!adapter->vxlan_port_cnt || | |
3075 | adapter->vxlan_port != ti->port) | |
3076 | return; /* Invalid VxLAN destination port */ | |
3077 | ||
3078 | adapter->vxlan_port_cnt--; | |
3079 | if (adapter->vxlan_port_cnt) | |
3080 | return; | |
3081 | ||
3082 | adapter->vxlan_port = 0; | |
3083 | t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0); | |
3084 | break; | |
c746fc0e GG |
3085 | case UDP_TUNNEL_TYPE_GENEVE: |
3086 | if (!adapter->geneve_port_cnt || | |
3087 | adapter->geneve_port != ti->port) | |
3088 | return; /* Invalid GENEVE destination port */ | |
3089 | ||
3090 | adapter->geneve_port_cnt--; | |
3091 | if (adapter->geneve_port_cnt) | |
3092 | return; | |
3093 | ||
3094 | adapter->geneve_port = 0; | |
3095 | t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0); | |
942a656f | 3096 | break; |
846eac3f GG |
3097 | default: |
3098 | return; | |
3099 | } | |
3100 | ||
3101 | /* Matchall mac entries can be deleted only after all tunnel ports | |
3102 | * are brought down or removed. | |
3103 | */ | |
3104 | if (!adapter->rawf_cnt) | |
3105 | return; | |
3106 | for_each_port(adapter, i) { | |
3107 | pi = adap2pinfo(adapter, i); | |
3108 | ret = t4_free_raw_mac_filt(adapter, pi->viid, | |
3109 | match_all_mac, match_all_mac, | |
3110 | adapter->rawf_start + | |
3111 | pi->port_id, | |
443e2dab | 3112 | 1, pi->port_id, false); |
846eac3f GG |
3113 | if (ret < 0) { |
3114 | netdev_info(netdev, "Failed to free mac filter entry, for port %d\n", | |
3115 | i); | |
3116 | return; | |
3117 | } | |
3118 | atomic_dec(&adapter->mps_encap[adapter->rawf_start + | |
3119 | pi->port_id].refcnt); | |
3120 | } | |
3121 | } | |
3122 | ||
3123 | static void cxgb_add_udp_tunnel(struct net_device *netdev, | |
3124 | struct udp_tunnel_info *ti) | |
3125 | { | |
3126 | struct port_info *pi = netdev_priv(netdev); | |
3127 | struct adapter *adapter = pi->adapter; | |
3128 | unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); | |
3129 | u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; | |
3130 | int i, ret; | |
3131 | ||
c746fc0e | 3132 | if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt) |
846eac3f GG |
3133 | return; |
3134 | ||
3135 | switch (ti->type) { | |
3136 | case UDP_TUNNEL_TYPE_VXLAN: | |
846eac3f GG |
3137 | /* Callback for adding vxlan port can be called with the same |
3138 | * port for both IPv4 and IPv6. We should not disable the | |
3139 | * offloading when the same port for both protocols is added | |
3140 | * and later one of them is removed. | |
3141 | */ | |
3142 | if (adapter->vxlan_port_cnt && | |
3143 | adapter->vxlan_port == ti->port) { | |
3144 | adapter->vxlan_port_cnt++; | |
3145 | return; | |
3146 | } | |
3147 | ||
3148 | /* We will support only one VxLAN port */ | |
3149 | if (adapter->vxlan_port_cnt) { | |
3150 | netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n", | |
3151 | be16_to_cpu(adapter->vxlan_port), | |
3152 | be16_to_cpu(ti->port)); | |
3153 | return; | |
3154 | } | |
3155 | ||
3156 | adapter->vxlan_port = ti->port; | |
3157 | adapter->vxlan_port_cnt = 1; | |
3158 | ||
3159 | t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, | |
3160 | VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F); | |
3161 | break; | |
c746fc0e GG |
3162 | case UDP_TUNNEL_TYPE_GENEVE: |
3163 | if (adapter->geneve_port_cnt && | |
3164 | adapter->geneve_port == ti->port) { | |
3165 | adapter->geneve_port_cnt++; | |
3166 | return; | |
3167 | } | |
3168 | ||
3169 | /* We will support only one GENEVE port */ | |
3170 | if (adapter->geneve_port_cnt) { | |
3171 | netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n", | |
3172 | be16_to_cpu(adapter->geneve_port), | |
3173 | be16_to_cpu(ti->port)); | |
3174 | return; | |
3175 | } | |
3176 | ||
3177 | adapter->geneve_port = ti->port; | |
3178 | adapter->geneve_port_cnt = 1; | |
3179 | ||
3180 | t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, | |
3181 | GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F); | |
942a656f | 3182 | break; |
846eac3f GG |
3183 | default: |
3184 | return; | |
3185 | } | |
3186 | ||
3187 | /* Create a 'match all' mac filter entry for inner mac, | |
3188 | * if raw mac interface is supported. Once the linux kernel provides | |
3189 | * driver entry points for adding/deleting the inner mac addresses, | |
3190 | * we will remove this 'match all' entry and fallback to adding | |
3191 | * exact match filters. | |
3192 | */ | |
c746fc0e GG |
3193 | for_each_port(adapter, i) { |
3194 | pi = adap2pinfo(adapter, i); | |
3195 | ||
3196 | ret = t4_alloc_raw_mac_filt(adapter, pi->viid, | |
3197 | match_all_mac, | |
3198 | match_all_mac, | |
3199 | adapter->rawf_start + | |
3200 | pi->port_id, | |
443e2dab | 3201 | 1, pi->port_id, false); |
c746fc0e GG |
3202 | if (ret < 0) { |
3203 | netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n", | |
3204 | be16_to_cpu(ti->port)); | |
3205 | cxgb_del_udp_tunnel(netdev, ti); | |
3206 | return; | |
846eac3f | 3207 | } |
c746fc0e | 3208 | atomic_inc(&adapter->mps_encap[ret].refcnt); |
846eac3f GG |
3209 | } |
3210 | } | |
3211 | ||
4621ffd6 GG |
3212 | static netdev_features_t cxgb_features_check(struct sk_buff *skb, |
3213 | struct net_device *dev, | |
3214 | netdev_features_t features) | |
3215 | { | |
3216 | struct port_info *pi = netdev_priv(dev); | |
3217 | struct adapter *adapter = pi->adapter; | |
3218 | ||
3219 | if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) | |
3220 | return features; | |
3221 | ||
3222 | /* Check if hw supports offload for this packet */ | |
3223 | if (!skb->encapsulation || cxgb_encap_offload_supported(skb)) | |
3224 | return features; | |
3225 | ||
3226 | /* Offload is not supported for this encapsulated packet */ | |
3227 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
3228 | } | |
3229 | ||
90592b9a AV |
3230 | static netdev_features_t cxgb_fix_features(struct net_device *dev, |
3231 | netdev_features_t features) | |
3232 | { | |
3233 | /* Disable GRO, if RX_CSUM is disabled */ | |
3234 | if (!(features & NETIF_F_RXCSUM)) | |
3235 | features &= ~NETIF_F_GRO; | |
3236 | ||
3237 | return features; | |
3238 | } | |
3239 | ||
b8ff05a9 DM |
3240 | static const struct net_device_ops cxgb4_netdev_ops = { |
3241 | .ndo_open = cxgb_open, | |
3242 | .ndo_stop = cxgb_close, | |
d5fbda61 | 3243 | .ndo_start_xmit = t4_start_xmit, |
688848b1 | 3244 | .ndo_select_queue = cxgb_select_queue, |
9be793bf | 3245 | .ndo_get_stats64 = cxgb_get_stats, |
b8ff05a9 DM |
3246 | .ndo_set_rx_mode = cxgb_set_rxmode, |
3247 | .ndo_set_mac_address = cxgb_set_mac_addr, | |
2ed28baa | 3248 | .ndo_set_features = cxgb_set_features, |
b8ff05a9 DM |
3249 | .ndo_validate_addr = eth_validate_addr, |
3250 | .ndo_do_ioctl = cxgb_ioctl, | |
3251 | .ndo_change_mtu = cxgb_change_mtu, | |
b8ff05a9 DM |
3252 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3253 | .ndo_poll_controller = cxgb_netpoll, | |
3254 | #endif | |
84a200b3 VP |
3255 | #ifdef CONFIG_CHELSIO_T4_FCOE |
3256 | .ndo_fcoe_enable = cxgb_fcoe_enable, | |
3257 | .ndo_fcoe_disable = cxgb_fcoe_disable, | |
3258 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
10a2604e | 3259 | .ndo_set_tx_maxrate = cxgb_set_tx_maxrate, |
d8931847 | 3260 | .ndo_setup_tc = cxgb_setup_tc, |
846eac3f GG |
3261 | .ndo_udp_tunnel_add = cxgb_add_udp_tunnel, |
3262 | .ndo_udp_tunnel_del = cxgb_del_udp_tunnel, | |
4621ffd6 | 3263 | .ndo_features_check = cxgb_features_check, |
90592b9a | 3264 | .ndo_fix_features = cxgb_fix_features, |
b8ff05a9 DM |
3265 | }; |
3266 | ||
858aa65c | 3267 | #ifdef CONFIG_PCI_IOV |
e7b48a32 | 3268 | static const struct net_device_ops cxgb4_mgmt_netdev_ops = { |
baf50868 GG |
3269 | .ndo_open = cxgb4_mgmt_open, |
3270 | .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac, | |
3271 | .ndo_get_vf_config = cxgb4_mgmt_get_vf_config, | |
3272 | .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate, | |
3273 | .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id, | |
9d5fd927 | 3274 | .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan, |
7829451c | 3275 | }; |
e7b48a32 | 3276 | #endif |
7829451c | 3277 | |
baf50868 GG |
3278 | static void cxgb4_mgmt_get_drvinfo(struct net_device *dev, |
3279 | struct ethtool_drvinfo *info) | |
7829451c HS |
3280 | { |
3281 | struct adapter *adapter = netdev2adap(dev); | |
3282 | ||
3283 | strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver)); | |
3284 | strlcpy(info->version, cxgb4_driver_version, | |
3285 | sizeof(info->version)); | |
3286 | strlcpy(info->bus_info, pci_name(adapter->pdev), | |
3287 | sizeof(info->bus_info)); | |
3288 | } | |
3289 | ||
3290 | static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = { | |
baf50868 | 3291 | .get_drvinfo = cxgb4_mgmt_get_drvinfo, |
7829451c HS |
3292 | }; |
3293 | ||
8b7372c1 GG |
3294 | static void notify_fatal_err(struct work_struct *work) |
3295 | { | |
3296 | struct adapter *adap; | |
3297 | ||
3298 | adap = container_of(work, struct adapter, fatal_err_notify_task); | |
3299 | notify_ulds(adap, CXGB4_STATE_FATAL_ERROR); | |
3300 | } | |
3301 | ||
b8ff05a9 DM |
3302 | void t4_fatal_err(struct adapter *adap) |
3303 | { | |
3be0679b HS |
3304 | int port; |
3305 | ||
025d0973 GP |
3306 | if (pci_channel_offline(adap->pdev)) |
3307 | return; | |
3308 | ||
3be0679b HS |
3309 | /* Disable the SGE since ULDs are going to free resources that |
3310 | * could be exposed to the adapter. RDMA MWs for example... | |
3311 | */ | |
3312 | t4_shutdown_adapter(adap); | |
3313 | for_each_port(adap, port) { | |
3314 | struct net_device *dev = adap->port[port]; | |
3315 | ||
3316 | /* If we get here in very early initialization the network | |
3317 | * devices may not have been set up yet. | |
3318 | */ | |
3319 | if (!dev) | |
3320 | continue; | |
3321 | ||
3322 | netif_tx_stop_all_queues(dev); | |
3323 | netif_carrier_off(dev); | |
3324 | } | |
b8ff05a9 | 3325 | dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); |
8b7372c1 | 3326 | queue_work(adap->workq, &adap->fatal_err_notify_task); |
b8ff05a9 DM |
3327 | } |
3328 | ||
3329 | static void setup_memwin(struct adapter *adap) | |
3330 | { | |
b562fc37 | 3331 | u32 nic_win_base = t4_get_util_window(adap); |
b8ff05a9 | 3332 | |
b562fc37 | 3333 | t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); |
636f9d37 VP |
3334 | } |
3335 | ||
3336 | static void setup_memwin_rdma(struct adapter *adap) | |
3337 | { | |
1ae970e0 | 3338 | if (adap->vres.ocq.size) { |
0abfd152 HS |
3339 | u32 start; |
3340 | unsigned int sz_kb; | |
1ae970e0 | 3341 | |
0abfd152 HS |
3342 | start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); |
3343 | start &= PCI_BASE_ADDRESS_MEM_MASK; | |
3344 | start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); | |
1ae970e0 DM |
3345 | sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; |
3346 | t4_write_reg(adap, | |
f061de42 HS |
3347 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), |
3348 | start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); | |
1ae970e0 | 3349 | t4_write_reg(adap, |
f061de42 | 3350 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), |
1ae970e0 DM |
3351 | adap->vres.ocq.start); |
3352 | t4_read_reg(adap, | |
f061de42 | 3353 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); |
1ae970e0 | 3354 | } |
b8ff05a9 DM |
3355 | } |
3356 | ||
8b4e6b3c AV |
3357 | /* HMA Definitions */ |
3358 | ||
3359 | /* The maximum number of address that can be send in a single FW cmd */ | |
3360 | #define HMA_MAX_ADDR_IN_CMD 5 | |
3361 | ||
3362 | #define HMA_PAGE_SIZE PAGE_SIZE | |
3363 | ||
3364 | #define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */ | |
3365 | ||
3366 | #define HMA_PAGE_ORDER \ | |
3367 | ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \ | |
3368 | ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0) | |
3369 | ||
3370 | /* The minimum and maximum possible HMA sizes that can be specified in the FW | |
3371 | * configuration(in units of MB). | |
3372 | */ | |
3373 | #define HMA_MIN_TOTAL_SIZE 1 | |
3374 | #define HMA_MAX_TOTAL_SIZE \ | |
3375 | (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \ | |
3376 | HMA_MAX_NO_FW_ADDRESS) >> 20) | |
3377 | ||
3378 | static void adap_free_hma_mem(struct adapter *adapter) | |
3379 | { | |
3380 | struct scatterlist *iter; | |
3381 | struct page *page; | |
3382 | int i; | |
3383 | ||
3384 | if (!adapter->hma.sgt) | |
3385 | return; | |
3386 | ||
3387 | if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) { | |
3388 | dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl, | |
3389 | adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL); | |
3390 | adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG; | |
3391 | } | |
3392 | ||
3393 | for_each_sg(adapter->hma.sgt->sgl, iter, | |
3394 | adapter->hma.sgt->orig_nents, i) { | |
3395 | page = sg_page(iter); | |
3396 | if (page) | |
3397 | __free_pages(page, HMA_PAGE_ORDER); | |
3398 | } | |
3399 | ||
3400 | kfree(adapter->hma.phy_addr); | |
3401 | sg_free_table(adapter->hma.sgt); | |
3402 | kfree(adapter->hma.sgt); | |
3403 | adapter->hma.sgt = NULL; | |
3404 | } | |
3405 | ||
3406 | static int adap_config_hma(struct adapter *adapter) | |
3407 | { | |
3408 | struct scatterlist *sgl, *iter; | |
3409 | struct sg_table *sgt; | |
3410 | struct page *newpage; | |
3411 | unsigned int i, j, k; | |
3412 | u32 param, hma_size; | |
3413 | unsigned int ncmds; | |
3414 | size_t page_size; | |
3415 | u32 page_order; | |
3416 | int node, ret; | |
3417 | ||
3418 | /* HMA is supported only for T6+ cards. | |
3419 | * Avoid initializing HMA in kdump kernels. | |
3420 | */ | |
3421 | if (is_kdump_kernel() || | |
3422 | CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) | |
3423 | return 0; | |
3424 | ||
3425 | /* Get the HMA region size required by fw */ | |
3426 | param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | | |
3427 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE)); | |
3428 | ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, | |
3429 | 1, ¶m, &hma_size); | |
3430 | /* An error means card has its own memory or HMA is not supported by | |
3431 | * the firmware. Return without any errors. | |
3432 | */ | |
3433 | if (ret || !hma_size) | |
3434 | return 0; | |
3435 | ||
3436 | if (hma_size < HMA_MIN_TOTAL_SIZE || | |
3437 | hma_size > HMA_MAX_TOTAL_SIZE) { | |
3438 | dev_err(adapter->pdev_dev, | |
3439 | "HMA size %uMB beyond bounds(%u-%lu)MB\n", | |
3440 | hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE); | |
3441 | return -EINVAL; | |
3442 | } | |
3443 | ||
3444 | page_size = HMA_PAGE_SIZE; | |
3445 | page_order = HMA_PAGE_ORDER; | |
3446 | adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL); | |
3447 | if (unlikely(!adapter->hma.sgt)) { | |
3448 | dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n"); | |
3449 | return -ENOMEM; | |
3450 | } | |
3451 | sgt = adapter->hma.sgt; | |
3452 | /* FW returned value will be in MB's | |
3453 | */ | |
3454 | sgt->orig_nents = (hma_size << 20) / (page_size << page_order); | |
3455 | if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) { | |
3456 | dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n"); | |
3457 | kfree(adapter->hma.sgt); | |
3458 | adapter->hma.sgt = NULL; | |
3459 | return -ENOMEM; | |
3460 | } | |
3461 | ||
3462 | sgl = adapter->hma.sgt->sgl; | |
3463 | node = dev_to_node(adapter->pdev_dev); | |
3464 | for_each_sg(sgl, iter, sgt->orig_nents, i) { | |
2b928749 GG |
3465 | newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL | |
3466 | __GFP_ZERO, page_order); | |
8b4e6b3c AV |
3467 | if (!newpage) { |
3468 | dev_err(adapter->pdev_dev, | |
3469 | "Not enough memory for HMA page allocation\n"); | |
3470 | ret = -ENOMEM; | |
3471 | goto free_hma; | |
3472 | } | |
3473 | sg_set_page(iter, newpage, page_size << page_order, 0); | |
3474 | } | |
3475 | ||
3476 | sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents, | |
3477 | DMA_BIDIRECTIONAL); | |
3478 | if (!sgt->nents) { | |
3479 | dev_err(adapter->pdev_dev, | |
3480 | "Not enough memory for HMA DMA mapping"); | |
3481 | ret = -ENOMEM; | |
3482 | goto free_hma; | |
3483 | } | |
3484 | adapter->hma.flags |= HMA_DMA_MAPPED_FLAG; | |
3485 | ||
3486 | adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t), | |
3487 | GFP_KERNEL); | |
3488 | if (unlikely(!adapter->hma.phy_addr)) | |
3489 | goto free_hma; | |
3490 | ||
3491 | for_each_sg(sgl, iter, sgt->nents, i) { | |
3492 | newpage = sg_page(iter); | |
3493 | adapter->hma.phy_addr[i] = sg_dma_address(iter); | |
3494 | } | |
3495 | ||
3496 | ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD); | |
3497 | /* Pass on the addresses to firmware */ | |
3498 | for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) { | |
3499 | struct fw_hma_cmd hma_cmd; | |
3500 | u8 naddr = HMA_MAX_ADDR_IN_CMD; | |
3501 | u8 soc = 0, eoc = 0; | |
3502 | u8 hma_mode = 1; /* Presently we support only Page table mode */ | |
3503 | ||
3504 | soc = (i == 0) ? 1 : 0; | |
3505 | eoc = (i == ncmds - 1) ? 1 : 0; | |
3506 | ||
3507 | /* For last cmd, set naddr corresponding to remaining | |
3508 | * addresses | |
3509 | */ | |
3510 | if (i == ncmds - 1) { | |
3511 | naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD; | |
3512 | naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD; | |
3513 | } | |
3514 | memset(&hma_cmd, 0, sizeof(hma_cmd)); | |
3515 | hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) | | |
3516 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
3517 | hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd)); | |
3518 | ||
3519 | hma_cmd.mode_to_pcie_params = | |
3520 | htonl(FW_HMA_CMD_MODE_V(hma_mode) | | |
3521 | FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc)); | |
3522 | ||
3523 | /* HMA cmd size specified in MB's */ | |
3524 | hma_cmd.naddr_size = | |
3525 | htonl(FW_HMA_CMD_SIZE_V(hma_size) | | |
3526 | FW_HMA_CMD_NADDR_V(naddr)); | |
3527 | ||
3528 | /* Total Page size specified in units of 4K */ | |
3529 | hma_cmd.addr_size_pkd = | |
3530 | htonl(FW_HMA_CMD_ADDR_SIZE_V | |
3531 | ((page_size << page_order) >> 12)); | |
3532 | ||
3533 | /* Fill the 5 addresses */ | |
3534 | for (j = 0; j < naddr; j++) { | |
3535 | hma_cmd.phy_address[j] = | |
3536 | cpu_to_be64(adapter->hma.phy_addr[j + k]); | |
3537 | } | |
3538 | ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd, | |
3539 | sizeof(hma_cmd), &hma_cmd); | |
3540 | if (ret) { | |
3541 | dev_err(adapter->pdev_dev, | |
3542 | "HMA FW command failed with err %d\n", ret); | |
3543 | goto free_hma; | |
3544 | } | |
3545 | } | |
3546 | ||
3547 | if (!ret) | |
3548 | dev_info(adapter->pdev_dev, | |
3549 | "Reserved %uMB host memory for HMA\n", hma_size); | |
3550 | return ret; | |
3551 | ||
3552 | free_hma: | |
3553 | adap_free_hma_mem(adapter); | |
3554 | return ret; | |
3555 | } | |
3556 | ||
02b5fb8e DM |
3557 | static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) |
3558 | { | |
3559 | u32 v; | |
3560 | int ret; | |
3561 | ||
0eaec62a CL |
3562 | /* Now that we've successfully configured and initialized the adapter |
3563 | * can ask the Firmware what resources it has provisioned for us. | |
3564 | */ | |
3565 | ret = t4_get_pfres(adap); | |
3566 | if (ret) { | |
3567 | dev_err(adap->pdev_dev, | |
3568 | "Unable to retrieve resource provisioning information\n"); | |
3569 | return ret; | |
3570 | } | |
3571 | ||
02b5fb8e DM |
3572 | /* get device capabilities */ |
3573 | memset(c, 0, sizeof(*c)); | |
e2ac9628 HS |
3574 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3575 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 3576 | c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); |
b2612722 | 3577 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); |
02b5fb8e DM |
3578 | if (ret < 0) |
3579 | return ret; | |
3580 | ||
e2ac9628 HS |
3581 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3582 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
b2612722 | 3583 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); |
02b5fb8e DM |
3584 | if (ret < 0) |
3585 | return ret; | |
3586 | ||
b2612722 | 3587 | ret = t4_config_glbl_rss(adap, adap->pf, |
02b5fb8e | 3588 | FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, |
b2e1a3f0 HS |
3589 | FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | |
3590 | FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); | |
02b5fb8e DM |
3591 | if (ret < 0) |
3592 | return ret; | |
3593 | ||
b2612722 | 3594 | ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, |
4b8e27a8 HS |
3595 | MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, |
3596 | FW_CMD_CAP_PF); | |
02b5fb8e DM |
3597 | if (ret < 0) |
3598 | return ret; | |
3599 | ||
3600 | t4_sge_init(adap); | |
3601 | ||
02b5fb8e | 3602 | /* tweak some settings */ |
837e4a42 | 3603 | t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); |
0d804338 | 3604 | t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); |
837e4a42 HS |
3605 | t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); |
3606 | v = t4_read_reg(adap, TP_PIO_DATA_A); | |
3607 | t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); | |
060e0c75 | 3608 | |
dca4faeb VP |
3609 | /* first 4 Tx modulation queues point to consecutive Tx channels */ |
3610 | adap->params.tp.tx_modq_map = 0xE4; | |
0d804338 HS |
3611 | t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, |
3612 | TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); | |
dca4faeb VP |
3613 | |
3614 | /* associate each Tx modulation queue with consecutive Tx channels */ | |
3615 | v = 0x84218421; | |
837e4a42 | 3616 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3617 | &v, 1, TP_TX_SCHED_HDR_A); |
837e4a42 | 3618 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3619 | &v, 1, TP_TX_SCHED_FIFO_A); |
837e4a42 | 3620 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3621 | &v, 1, TP_TX_SCHED_PCMD_A); |
dca4faeb VP |
3622 | |
3623 | #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ | |
3624 | if (is_offload(adap)) { | |
0d804338 HS |
3625 | t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, |
3626 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3627 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3628 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3629 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
3630 | t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, | |
3631 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3632 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3633 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3634 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
dca4faeb VP |
3635 | } |
3636 | ||
060e0c75 | 3637 | /* get basic stuff going */ |
b2612722 | 3638 | return t4_early_init(adap, adap->pf); |
02b5fb8e DM |
3639 | } |
3640 | ||
b8ff05a9 DM |
3641 | /* |
3642 | * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. | |
3643 | */ | |
3644 | #define MAX_ATIDS 8192U | |
3645 | ||
636f9d37 VP |
3646 | /* |
3647 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
3648 | * | |
3649 | * If the firmware we're dealing with has Configuration File support, then | |
3650 | * we use that to perform all configuration | |
3651 | */ | |
3652 | ||
3653 | /* | |
3654 | * Tweak configuration based on module parameters, etc. Most of these have | |
3655 | * defaults assigned to them by Firmware Configuration Files (if we're using | |
3656 | * them) but need to be explicitly set if we're using hard-coded | |
3657 | * initialization. But even in the case of using Firmware Configuration | |
3658 | * Files, we'd like to expose the ability to change these via module | |
3659 | * parameters so these are essentially common tweaks/settings for | |
3660 | * Configuration Files and hard-coded initialization ... | |
3661 | */ | |
3662 | static int adap_init0_tweaks(struct adapter *adapter) | |
3663 | { | |
3664 | /* | |
3665 | * Fix up various Host-Dependent Parameters like Page Size, Cache | |
3666 | * Line Size, etc. The firmware default is for a 4KB Page Size and | |
3667 | * 64B Cache Line Size ... | |
3668 | */ | |
3669 | t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); | |
3670 | ||
3671 | /* | |
3672 | * Process module parameters which affect early initialization. | |
3673 | */ | |
3674 | if (rx_dma_offset != 2 && rx_dma_offset != 0) { | |
3675 | dev_err(&adapter->pdev->dev, | |
3676 | "Ignoring illegal rx_dma_offset=%d, using 2\n", | |
3677 | rx_dma_offset); | |
3678 | rx_dma_offset = 2; | |
3679 | } | |
f612b815 HS |
3680 | t4_set_reg_field(adapter, SGE_CONTROL_A, |
3681 | PKTSHIFT_V(PKTSHIFT_M), | |
3682 | PKTSHIFT_V(rx_dma_offset)); | |
636f9d37 VP |
3683 | |
3684 | /* | |
3685 | * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux | |
3686 | * adds the pseudo header itself. | |
3687 | */ | |
837e4a42 HS |
3688 | t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, |
3689 | CSUM_HAS_PSEUDO_HDR_F, 0); | |
636f9d37 VP |
3690 | |
3691 | return 0; | |
3692 | } | |
3693 | ||
01b69614 HS |
3694 | /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips |
3695 | * unto themselves and they contain their own firmware to perform their | |
3696 | * tasks ... | |
3697 | */ | |
3698 | static int phy_aq1202_version(const u8 *phy_fw_data, | |
3699 | size_t phy_fw_size) | |
3700 | { | |
3701 | int offset; | |
3702 | ||
3703 | /* At offset 0x8 you're looking for the primary image's | |
3704 | * starting offset which is 3 Bytes wide | |
3705 | * | |
3706 | * At offset 0xa of the primary image, you look for the offset | |
3707 | * of the DRAM segment which is 3 Bytes wide. | |
3708 | * | |
3709 | * The FW version is at offset 0x27e of the DRAM and is 2 Bytes | |
3710 | * wide | |
3711 | */ | |
3712 | #define be16(__p) (((__p)[0] << 8) | (__p)[1]) | |
3713 | #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) | |
3714 | #define le24(__p) (le16(__p) | ((__p)[2] << 16)) | |
3715 | ||
3716 | offset = le24(phy_fw_data + 0x8) << 12; | |
3717 | offset = le24(phy_fw_data + offset + 0xa); | |
3718 | return be16(phy_fw_data + offset + 0x27e); | |
3719 | ||
3720 | #undef be16 | |
3721 | #undef le16 | |
3722 | #undef le24 | |
3723 | } | |
3724 | ||
3725 | static struct info_10gbt_phy_fw { | |
3726 | unsigned int phy_fw_id; /* PCI Device ID */ | |
3727 | char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ | |
3728 | int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); | |
3729 | int phy_flash; /* Has FLASH for PHY Firmware */ | |
3730 | } phy_info_array[] = { | |
3731 | { | |
3732 | PHY_AQ1202_DEVICEID, | |
3733 | PHY_AQ1202_FIRMWARE, | |
3734 | phy_aq1202_version, | |
3735 | 1, | |
3736 | }, | |
3737 | { | |
3738 | PHY_BCM84834_DEVICEID, | |
3739 | PHY_BCM84834_FIRMWARE, | |
3740 | NULL, | |
3741 | 0, | |
3742 | }, | |
3743 | { 0, NULL, NULL }, | |
3744 | }; | |
3745 | ||
3746 | static struct info_10gbt_phy_fw *find_phy_info(int devid) | |
3747 | { | |
3748 | int i; | |
3749 | ||
3750 | for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { | |
3751 | if (phy_info_array[i].phy_fw_id == devid) | |
3752 | return &phy_info_array[i]; | |
3753 | } | |
3754 | return NULL; | |
3755 | } | |
3756 | ||
3757 | /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to | |
3758 | * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error | |
3759 | * we return a negative error number. If we transfer new firmware we return 1 | |
3760 | * (from t4_load_phy_fw()). If we don't do anything we return 0. | |
3761 | */ | |
3762 | static int adap_init0_phy(struct adapter *adap) | |
3763 | { | |
3764 | const struct firmware *phyf; | |
3765 | int ret; | |
3766 | struct info_10gbt_phy_fw *phy_info; | |
3767 | ||
3768 | /* Use the device ID to determine which PHY file to flash. | |
3769 | */ | |
3770 | phy_info = find_phy_info(adap->pdev->device); | |
3771 | if (!phy_info) { | |
3772 | dev_warn(adap->pdev_dev, | |
3773 | "No PHY Firmware file found for this PHY\n"); | |
3774 | return -EOPNOTSUPP; | |
3775 | } | |
3776 | ||
3777 | /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then | |
3778 | * use that. The adapter firmware provides us with a memory buffer | |
3779 | * where we can load a PHY firmware file from the host if we want to | |
3780 | * override the PHY firmware File in flash. | |
3781 | */ | |
3782 | ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, | |
3783 | adap->pdev_dev); | |
3784 | if (ret < 0) { | |
3785 | /* For adapters without FLASH attached to PHY for their | |
3786 | * firmware, it's obviously a fatal error if we can't get the | |
3787 | * firmware to the adapter. For adapters with PHY firmware | |
3788 | * FLASH storage, it's worth a warning if we can't find the | |
3789 | * PHY Firmware but we'll neuter the error ... | |
3790 | */ | |
3791 | dev_err(adap->pdev_dev, "unable to find PHY Firmware image " | |
3792 | "/lib/firmware/%s, error %d\n", | |
3793 | phy_info->phy_fw_file, -ret); | |
3794 | if (phy_info->phy_flash) { | |
3795 | int cur_phy_fw_ver = 0; | |
3796 | ||
3797 | t4_phy_fw_ver(adap, &cur_phy_fw_ver); | |
3798 | dev_warn(adap->pdev_dev, "continuing with, on-adapter " | |
3799 | "FLASH copy, version %#x\n", cur_phy_fw_ver); | |
3800 | ret = 0; | |
3801 | } | |
3802 | ||
3803 | return ret; | |
3804 | } | |
3805 | ||
3806 | /* Load PHY Firmware onto adapter. | |
3807 | */ | |
3808 | ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, | |
3809 | phy_info->phy_fw_version, | |
3810 | (u8 *)phyf->data, phyf->size); | |
3811 | if (ret < 0) | |
3812 | dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", | |
3813 | -ret); | |
3814 | else if (ret > 0) { | |
3815 | int new_phy_fw_ver = 0; | |
3816 | ||
3817 | if (phy_info->phy_fw_version) | |
3818 | new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, | |
3819 | phyf->size); | |
3820 | dev_info(adap->pdev_dev, "Successfully transferred PHY " | |
3821 | "Firmware /lib/firmware/%s, version %#x\n", | |
3822 | phy_info->phy_fw_file, new_phy_fw_ver); | |
3823 | } | |
3824 | ||
3825 | release_firmware(phyf); | |
3826 | ||
3827 | return ret; | |
3828 | } | |
3829 | ||
636f9d37 VP |
3830 | /* |
3831 | * Attempt to initialize the adapter via a Firmware Configuration File. | |
3832 | */ | |
3833 | static int adap_init0_config(struct adapter *adapter, int reset) | |
3834 | { | |
3835 | struct fw_caps_config_cmd caps_cmd; | |
3836 | const struct firmware *cf; | |
3837 | unsigned long mtype = 0, maddr = 0; | |
3838 | u32 finiver, finicsum, cfcsum; | |
16e47624 HS |
3839 | int ret; |
3840 | int config_issued = 0; | |
0a57a536 | 3841 | char *fw_config_file, fw_config_file_path[256]; |
16e47624 | 3842 | char *config_name = NULL; |
636f9d37 VP |
3843 | |
3844 | /* | |
3845 | * Reset device if necessary. | |
3846 | */ | |
3847 | if (reset) { | |
3848 | ret = t4_fw_reset(adapter, adapter->mbox, | |
0d804338 | 3849 | PIORSTMODE_F | PIORST_F); |
636f9d37 VP |
3850 | if (ret < 0) |
3851 | goto bye; | |
3852 | } | |
3853 | ||
01b69614 HS |
3854 | /* If this is a 10Gb/s-BT adapter make sure the chip-external |
3855 | * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs | |
3856 | * to be performed after any global adapter RESET above since some | |
3857 | * PHYs only have local RAM copies of the PHY firmware. | |
3858 | */ | |
3859 | if (is_10gbt_device(adapter->pdev->device)) { | |
3860 | ret = adap_init0_phy(adapter); | |
3861 | if (ret < 0) | |
3862 | goto bye; | |
3863 | } | |
636f9d37 VP |
3864 | /* |
3865 | * If we have a T4 configuration file under /lib/firmware/cxgb4/, | |
3866 | * then use that. Otherwise, use the configuration file stored | |
3867 | * in the adapter flash ... | |
3868 | */ | |
d14807dd | 3869 | switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { |
0a57a536 | 3870 | case CHELSIO_T4: |
16e47624 | 3871 | fw_config_file = FW4_CFNAME; |
0a57a536 SR |
3872 | break; |
3873 | case CHELSIO_T5: | |
3874 | fw_config_file = FW5_CFNAME; | |
3875 | break; | |
3ccc6cf7 HS |
3876 | case CHELSIO_T6: |
3877 | fw_config_file = FW6_CFNAME; | |
3878 | break; | |
0a57a536 SR |
3879 | default: |
3880 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", | |
3881 | adapter->pdev->device); | |
3882 | ret = -EINVAL; | |
3883 | goto bye; | |
3884 | } | |
3885 | ||
3886 | ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); | |
636f9d37 | 3887 | if (ret < 0) { |
16e47624 | 3888 | config_name = "On FLASH"; |
636f9d37 VP |
3889 | mtype = FW_MEMTYPE_CF_FLASH; |
3890 | maddr = t4_flash_cfg_addr(adapter); | |
3891 | } else { | |
3892 | u32 params[7], val[7]; | |
3893 | ||
16e47624 HS |
3894 | sprintf(fw_config_file_path, |
3895 | "/lib/firmware/%s", fw_config_file); | |
3896 | config_name = fw_config_file_path; | |
3897 | ||
636f9d37 VP |
3898 | if (cf->size >= FLASH_CFG_MAX_SIZE) |
3899 | ret = -ENOMEM; | |
3900 | else { | |
5167865a HS |
3901 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3902 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
636f9d37 | 3903 | ret = t4_query_params(adapter, adapter->mbox, |
b2612722 | 3904 | adapter->pf, 0, 1, params, val); |
636f9d37 VP |
3905 | if (ret == 0) { |
3906 | /* | |
fc5ab020 | 3907 | * For t4_memory_rw() below addresses and |
636f9d37 VP |
3908 | * sizes have to be in terms of multiples of 4 |
3909 | * bytes. So, if the Configuration File isn't | |
3910 | * a multiple of 4 bytes in length we'll have | |
3911 | * to write that out separately since we can't | |
3912 | * guarantee that the bytes following the | |
3913 | * residual byte in the buffer returned by | |
3914 | * request_firmware() are zeroed out ... | |
3915 | */ | |
3916 | size_t resid = cf->size & 0x3; | |
3917 | size_t size = cf->size & ~0x3; | |
3918 | __be32 *data = (__be32 *)cf->data; | |
3919 | ||
5167865a HS |
3920 | mtype = FW_PARAMS_PARAM_Y_G(val[0]); |
3921 | maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; | |
636f9d37 | 3922 | |
fc5ab020 HS |
3923 | spin_lock(&adapter->win0_lock); |
3924 | ret = t4_memory_rw(adapter, 0, mtype, maddr, | |
3925 | size, data, T4_MEMORY_WRITE); | |
636f9d37 VP |
3926 | if (ret == 0 && resid != 0) { |
3927 | union { | |
3928 | __be32 word; | |
3929 | char buf[4]; | |
3930 | } last; | |
3931 | int i; | |
3932 | ||
3933 | last.word = data[size >> 2]; | |
3934 | for (i = resid; i < 4; i++) | |
3935 | last.buf[i] = 0; | |
fc5ab020 HS |
3936 | ret = t4_memory_rw(adapter, 0, mtype, |
3937 | maddr + size, | |
3938 | 4, &last.word, | |
3939 | T4_MEMORY_WRITE); | |
636f9d37 | 3940 | } |
fc5ab020 | 3941 | spin_unlock(&adapter->win0_lock); |
636f9d37 VP |
3942 | } |
3943 | } | |
3944 | ||
3945 | release_firmware(cf); | |
3946 | if (ret) | |
3947 | goto bye; | |
3948 | } | |
3949 | ||
3950 | /* | |
3951 | * Issue a Capability Configuration command to the firmware to get it | |
3952 | * to parse the Configuration File. We don't use t4_fw_config_file() | |
3953 | * because we want the ability to modify various features after we've | |
3954 | * processed the configuration file ... | |
3955 | */ | |
3956 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3957 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3958 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3959 | FW_CMD_REQUEST_F | | |
3960 | FW_CMD_READ_F); | |
ce91a923 | 3961 | caps_cmd.cfvalid_to_len16 = |
5167865a HS |
3962 | htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | |
3963 | FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | | |
3964 | FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | | |
636f9d37 VP |
3965 | FW_LEN16(caps_cmd)); |
3966 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), | |
3967 | &caps_cmd); | |
16e47624 HS |
3968 | |
3969 | /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware | |
3970 | * Configuration File in FLASH), our last gasp effort is to use the | |
3971 | * Firmware Configuration File which is embedded in the firmware. A | |
3972 | * very few early versions of the firmware didn't have one embedded | |
3973 | * but we can ignore those. | |
3974 | */ | |
3975 | if (ret == -ENOENT) { | |
3976 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3977 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3978 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3979 | FW_CMD_REQUEST_F | | |
3980 | FW_CMD_READ_F); | |
16e47624 HS |
3981 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
3982 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, | |
3983 | sizeof(caps_cmd), &caps_cmd); | |
3984 | config_name = "Firmware Default"; | |
3985 | } | |
3986 | ||
3987 | config_issued = 1; | |
636f9d37 VP |
3988 | if (ret < 0) |
3989 | goto bye; | |
3990 | ||
3991 | finiver = ntohl(caps_cmd.finiver); | |
3992 | finicsum = ntohl(caps_cmd.finicsum); | |
3993 | cfcsum = ntohl(caps_cmd.cfcsum); | |
3994 | if (finicsum != cfcsum) | |
3995 | dev_warn(adapter->pdev_dev, "Configuration File checksum "\ | |
3996 | "mismatch: [fini] csum=%#x, computed csum=%#x\n", | |
3997 | finicsum, cfcsum); | |
3998 | ||
636f9d37 VP |
3999 | /* |
4000 | * And now tell the firmware to use the configuration we just loaded. | |
4001 | */ | |
4002 | caps_cmd.op_to_write = | |
e2ac9628 HS |
4003 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
4004 | FW_CMD_REQUEST_F | | |
4005 | FW_CMD_WRITE_F); | |
ce91a923 | 4006 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
4007 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), |
4008 | NULL); | |
4009 | if (ret < 0) | |
4010 | goto bye; | |
4011 | ||
4012 | /* | |
4013 | * Tweak configuration based on system architecture, module | |
4014 | * parameters, etc. | |
4015 | */ | |
4016 | ret = adap_init0_tweaks(adapter); | |
4017 | if (ret < 0) | |
4018 | goto bye; | |
4019 | ||
8b4e6b3c AV |
4020 | /* We will proceed even if HMA init fails. */ |
4021 | ret = adap_config_hma(adapter); | |
4022 | if (ret) | |
4023 | dev_err(adapter->pdev_dev, | |
4024 | "HMA configuration failed with error %d\n", ret); | |
4025 | ||
636f9d37 VP |
4026 | /* |
4027 | * And finally tell the firmware to initialize itself using the | |
4028 | * parameters from the Configuration File. | |
4029 | */ | |
4030 | ret = t4_fw_initialize(adapter, adapter->mbox); | |
4031 | if (ret < 0) | |
4032 | goto bye; | |
4033 | ||
06640310 HS |
4034 | /* Emit Firmware Configuration File information and return |
4035 | * successfully. | |
636f9d37 | 4036 | */ |
636f9d37 | 4037 | dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ |
16e47624 HS |
4038 | "Configuration File \"%s\", version %#x, computed checksum %#x\n", |
4039 | config_name, finiver, cfcsum); | |
636f9d37 VP |
4040 | return 0; |
4041 | ||
4042 | /* | |
4043 | * Something bad happened. Return the error ... (If the "error" | |
4044 | * is that there's no Configuration File on the adapter we don't | |
4045 | * want to issue a warning since this is fairly common.) | |
4046 | */ | |
4047 | bye: | |
16e47624 HS |
4048 | if (config_issued && ret != -ENOENT) |
4049 | dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", | |
4050 | config_name, -ret); | |
636f9d37 VP |
4051 | return ret; |
4052 | } | |
4053 | ||
16e47624 HS |
4054 | static struct fw_info fw_info_array[] = { |
4055 | { | |
4056 | .chip = CHELSIO_T4, | |
4057 | .fs_name = FW4_CFNAME, | |
4058 | .fw_mod_name = FW4_FNAME, | |
4059 | .fw_hdr = { | |
4060 | .chip = FW_HDR_CHIP_T4, | |
4061 | .fw_ver = __cpu_to_be32(FW_VERSION(T4)), | |
4062 | .intfver_nic = FW_INTFVER(T4, NIC), | |
4063 | .intfver_vnic = FW_INTFVER(T4, VNIC), | |
4064 | .intfver_ri = FW_INTFVER(T4, RI), | |
4065 | .intfver_iscsi = FW_INTFVER(T4, ISCSI), | |
4066 | .intfver_fcoe = FW_INTFVER(T4, FCOE), | |
4067 | }, | |
4068 | }, { | |
4069 | .chip = CHELSIO_T5, | |
4070 | .fs_name = FW5_CFNAME, | |
4071 | .fw_mod_name = FW5_FNAME, | |
4072 | .fw_hdr = { | |
4073 | .chip = FW_HDR_CHIP_T5, | |
4074 | .fw_ver = __cpu_to_be32(FW_VERSION(T5)), | |
4075 | .intfver_nic = FW_INTFVER(T5, NIC), | |
4076 | .intfver_vnic = FW_INTFVER(T5, VNIC), | |
4077 | .intfver_ri = FW_INTFVER(T5, RI), | |
4078 | .intfver_iscsi = FW_INTFVER(T5, ISCSI), | |
4079 | .intfver_fcoe = FW_INTFVER(T5, FCOE), | |
4080 | }, | |
3ccc6cf7 HS |
4081 | }, { |
4082 | .chip = CHELSIO_T6, | |
4083 | .fs_name = FW6_CFNAME, | |
4084 | .fw_mod_name = FW6_FNAME, | |
4085 | .fw_hdr = { | |
4086 | .chip = FW_HDR_CHIP_T6, | |
4087 | .fw_ver = __cpu_to_be32(FW_VERSION(T6)), | |
4088 | .intfver_nic = FW_INTFVER(T6, NIC), | |
4089 | .intfver_vnic = FW_INTFVER(T6, VNIC), | |
4090 | .intfver_ofld = FW_INTFVER(T6, OFLD), | |
4091 | .intfver_ri = FW_INTFVER(T6, RI), | |
4092 | .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), | |
4093 | .intfver_iscsi = FW_INTFVER(T6, ISCSI), | |
4094 | .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), | |
4095 | .intfver_fcoe = FW_INTFVER(T6, FCOE), | |
4096 | }, | |
16e47624 | 4097 | } |
3ccc6cf7 | 4098 | |
16e47624 HS |
4099 | }; |
4100 | ||
4101 | static struct fw_info *find_fw_info(int chip) | |
4102 | { | |
4103 | int i; | |
4104 | ||
4105 | for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { | |
4106 | if (fw_info_array[i].chip == chip) | |
4107 | return &fw_info_array[i]; | |
4108 | } | |
4109 | return NULL; | |
4110 | } | |
4111 | ||
b8ff05a9 DM |
4112 | /* |
4113 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
4114 | */ | |
4115 | static int adap_init0(struct adapter *adap) | |
4116 | { | |
4117 | int ret; | |
4118 | u32 v, port_vec; | |
4119 | enum dev_state state; | |
4120 | u32 params[7], val[7]; | |
9a4da2cd | 4121 | struct fw_caps_config_cmd caps_cmd; |
dcf7b6f5 | 4122 | int reset = 1; |
b8ff05a9 | 4123 | |
ae469b68 HS |
4124 | /* Grab Firmware Device Log parameters as early as possible so we have |
4125 | * access to it for debugging, etc. | |
4126 | */ | |
4127 | ret = t4_init_devlog_params(adap); | |
4128 | if (ret < 0) | |
4129 | return ret; | |
4130 | ||
666224d4 | 4131 | /* Contact FW, advertising Master capability */ |
c5a8c0f3 HS |
4132 | ret = t4_fw_hello(adap, adap->mbox, adap->mbox, |
4133 | is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); | |
b8ff05a9 DM |
4134 | if (ret < 0) { |
4135 | dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", | |
4136 | ret); | |
4137 | return ret; | |
4138 | } | |
636f9d37 VP |
4139 | if (ret == adap->mbox) |
4140 | adap->flags |= MASTER_PF; | |
b8ff05a9 | 4141 | |
636f9d37 VP |
4142 | /* |
4143 | * If we're the Master PF Driver and the device is uninitialized, | |
4144 | * then let's consider upgrading the firmware ... (We always want | |
4145 | * to check the firmware version number in order to A. get it for | |
4146 | * later reporting and B. to warn if the currently loaded firmware | |
4147 | * is excessively mismatched relative to the driver.) | |
4148 | */ | |
0de72738 | 4149 | |
760446f9 | 4150 | t4_get_version_info(adap); |
a69265e9 HS |
4151 | ret = t4_check_fw_version(adap); |
4152 | /* If firmware is too old (not supported by driver) force an update. */ | |
21d11bd6 | 4153 | if (ret) |
a69265e9 | 4154 | state = DEV_STATE_UNINIT; |
636f9d37 | 4155 | if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { |
16e47624 HS |
4156 | struct fw_info *fw_info; |
4157 | struct fw_hdr *card_fw; | |
4158 | const struct firmware *fw; | |
4159 | const u8 *fw_data = NULL; | |
4160 | unsigned int fw_size = 0; | |
4161 | ||
4162 | /* This is the firmware whose headers the driver was compiled | |
4163 | * against | |
4164 | */ | |
4165 | fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); | |
4166 | if (fw_info == NULL) { | |
4167 | dev_err(adap->pdev_dev, | |
4168 | "unable to get firmware info for chip %d.\n", | |
4169 | CHELSIO_CHIP_VERSION(adap->params.chip)); | |
4170 | return -EINVAL; | |
636f9d37 | 4171 | } |
16e47624 HS |
4172 | |
4173 | /* allocate memory to read the header of the firmware on the | |
4174 | * card | |
4175 | */ | |
752ade68 | 4176 | card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL); |
d624613e Y |
4177 | if (!card_fw) { |
4178 | ret = -ENOMEM; | |
4179 | goto bye; | |
4180 | } | |
16e47624 HS |
4181 | |
4182 | /* Get FW from from /lib/firmware/ */ | |
4183 | ret = request_firmware(&fw, fw_info->fw_mod_name, | |
4184 | adap->pdev_dev); | |
4185 | if (ret < 0) { | |
4186 | dev_err(adap->pdev_dev, | |
4187 | "unable to load firmware image %s, error %d\n", | |
4188 | fw_info->fw_mod_name, ret); | |
4189 | } else { | |
4190 | fw_data = fw->data; | |
4191 | fw_size = fw->size; | |
4192 | } | |
4193 | ||
4194 | /* upgrade FW logic */ | |
4195 | ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, | |
4196 | state, &reset); | |
4197 | ||
4198 | /* Cleaning up */ | |
0b5b6bee | 4199 | release_firmware(fw); |
752ade68 | 4200 | kvfree(card_fw); |
16e47624 | 4201 | |
636f9d37 | 4202 | if (ret < 0) |
16e47624 | 4203 | goto bye; |
636f9d37 | 4204 | } |
b8ff05a9 | 4205 | |
06640310 HS |
4206 | /* If the firmware is initialized already, emit a simply note to that |
4207 | * effect. Otherwise, it's time to try initializing the adapter. | |
636f9d37 VP |
4208 | */ |
4209 | if (state == DEV_STATE_INIT) { | |
8b4e6b3c AV |
4210 | ret = adap_config_hma(adap); |
4211 | if (ret) | |
4212 | dev_err(adap->pdev_dev, | |
4213 | "HMA configuration failed with error %d\n", | |
4214 | ret); | |
636f9d37 VP |
4215 | dev_info(adap->pdev_dev, "Coming up as %s: "\ |
4216 | "Adapter already initialized\n", | |
4217 | adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); | |
636f9d37 VP |
4218 | } else { |
4219 | dev_info(adap->pdev_dev, "Coming up as MASTER: "\ | |
4220 | "Initializing adapter\n"); | |
06640310 HS |
4221 | |
4222 | /* Find out whether we're dealing with a version of the | |
4223 | * firmware which has configuration file support. | |
636f9d37 | 4224 | */ |
06640310 HS |
4225 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
4226 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
b2612722 | 4227 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, |
06640310 | 4228 | params, val); |
13ee15d3 | 4229 | |
06640310 HS |
4230 | /* If the firmware doesn't support Configuration Files, |
4231 | * return an error. | |
4232 | */ | |
4233 | if (ret < 0) { | |
4234 | dev_err(adap->pdev_dev, "firmware doesn't support " | |
4235 | "Firmware Configuration Files\n"); | |
4236 | goto bye; | |
4237 | } | |
4238 | ||
4239 | /* The firmware provides us with a memory buffer where we can | |
4240 | * load a Configuration File from the host if we want to | |
4241 | * override the Configuration File in flash. | |
4242 | */ | |
4243 | ret = adap_init0_config(adap, reset); | |
4244 | if (ret == -ENOENT) { | |
4245 | dev_err(adap->pdev_dev, "no Configuration File " | |
4246 | "present on adapter.\n"); | |
4247 | goto bye; | |
636f9d37 VP |
4248 | } |
4249 | if (ret < 0) { | |
06640310 HS |
4250 | dev_err(adap->pdev_dev, "could not initialize " |
4251 | "adapter, error %d\n", -ret); | |
636f9d37 VP |
4252 | goto bye; |
4253 | } | |
4254 | } | |
4255 | ||
0eaec62a CL |
4256 | /* Now that we've successfully configured and initialized the adapter |
4257 | * (or found it already initialized), we can ask the Firmware what | |
4258 | * resources it has provisioned for us. | |
4259 | */ | |
4260 | ret = t4_get_pfres(adap); | |
4261 | if (ret) { | |
4262 | dev_err(adap->pdev_dev, | |
4263 | "Unable to retrieve resource provisioning information\n"); | |
4264 | goto bye; | |
4265 | } | |
4266 | ||
4267 | /* Grab VPD parameters. This should be done after we establish a | |
4268 | * connection to the firmware since some of the VPD parameters | |
4269 | * (notably the Core Clock frequency) are retrieved via requests to | |
4270 | * the firmware. On the other hand, we need these fairly early on | |
4271 | * so we do this right after getting ahold of the firmware. | |
4272 | * | |
4273 | * We need to do this after initializing the adapter because someone | |
4274 | * could have FLASHed a new VPD which won't be read by the firmware | |
4275 | * until we do the RESET ... | |
4276 | */ | |
4277 | ret = t4_get_vpd_params(adap, &adap->params.vpd); | |
4278 | if (ret < 0) | |
4279 | goto bye; | |
4280 | ||
4281 | /* Find out what ports are available to us. Note that we need to do | |
4282 | * this before calling adap_init0_no_config() since it needs nports | |
4283 | * and portvec ... | |
4284 | */ | |
4285 | v = | |
4286 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | | |
4287 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); | |
4288 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); | |
4289 | if (ret < 0) | |
4290 | goto bye; | |
4291 | ||
4292 | adap->params.nports = hweight32(port_vec); | |
4293 | adap->params.portvec = port_vec; | |
4294 | ||
06640310 HS |
4295 | /* Give the SGE code a chance to pull in anything that it needs ... |
4296 | * Note that this must be called after we retrieve our VPD parameters | |
4297 | * in order to know how to convert core ticks to seconds, etc. | |
636f9d37 | 4298 | */ |
06640310 HS |
4299 | ret = t4_sge_init(adap); |
4300 | if (ret < 0) | |
4301 | goto bye; | |
636f9d37 | 4302 | |
9a4da2cd VP |
4303 | if (is_bypass_device(adap->pdev->device)) |
4304 | adap->params.bypass = 1; | |
4305 | ||
636f9d37 VP |
4306 | /* |
4307 | * Grab some of our basic fundamental operating parameters. | |
4308 | */ | |
4309 | #define FW_PARAM_DEV(param) \ | |
5167865a HS |
4310 | (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ |
4311 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) | |
636f9d37 | 4312 | |
b8ff05a9 | 4313 | #define FW_PARAM_PFVF(param) \ |
5167865a HS |
4314 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ |
4315 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ | |
4316 | FW_PARAMS_PARAM_Y_V(0) | \ | |
4317 | FW_PARAMS_PARAM_Z_V(0) | |
b8ff05a9 | 4318 | |
636f9d37 | 4319 | params[0] = FW_PARAM_PFVF(EQ_START); |
b8ff05a9 DM |
4320 | params[1] = FW_PARAM_PFVF(L2T_START); |
4321 | params[2] = FW_PARAM_PFVF(L2T_END); | |
4322 | params[3] = FW_PARAM_PFVF(FILTER_START); | |
4323 | params[4] = FW_PARAM_PFVF(FILTER_END); | |
e46dab4d | 4324 | params[5] = FW_PARAM_PFVF(IQFLINT_START); |
b2612722 | 4325 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); |
b8ff05a9 DM |
4326 | if (ret < 0) |
4327 | goto bye; | |
636f9d37 VP |
4328 | adap->sge.egr_start = val[0]; |
4329 | adap->l2t_start = val[1]; | |
4330 | adap->l2t_end = val[2]; | |
b8ff05a9 DM |
4331 | adap->tids.ftid_base = val[3]; |
4332 | adap->tids.nftids = val[4] - val[3] + 1; | |
e46dab4d | 4333 | adap->sge.ingr_start = val[5]; |
b8ff05a9 | 4334 | |
0e249898 AV |
4335 | if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { |
4336 | /* Read the raw mps entries. In T6, the last 2 tcam entries | |
4337 | * are reserved for raw mac addresses (rawf = 2, one per port). | |
4338 | */ | |
4339 | params[0] = FW_PARAM_PFVF(RAWF_START); | |
4340 | params[1] = FW_PARAM_PFVF(RAWF_END); | |
4341 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, | |
4342 | params, val); | |
4343 | if (ret == 0) { | |
4344 | adap->rawf_start = val[0]; | |
4345 | adap->rawf_cnt = val[1] - val[0] + 1; | |
4346 | } | |
4347 | } | |
4348 | ||
4b8e27a8 HS |
4349 | /* qids (ingress/egress) returned from firmware can be anywhere |
4350 | * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. | |
4351 | * Hence driver needs to allocate memory for this range to | |
4352 | * store the queue info. Get the highest IQFLINT/EQ index returned | |
4353 | * in FW_EQ_*_CMD.alloc command. | |
4354 | */ | |
4355 | params[0] = FW_PARAM_PFVF(EQ_END); | |
4356 | params[1] = FW_PARAM_PFVF(IQFLINT_END); | |
b2612722 | 4357 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
4b8e27a8 HS |
4358 | if (ret < 0) |
4359 | goto bye; | |
4360 | adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; | |
4361 | adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; | |
4362 | ||
4363 | adap->sge.egr_map = kcalloc(adap->sge.egr_sz, | |
4364 | sizeof(*adap->sge.egr_map), GFP_KERNEL); | |
4365 | if (!adap->sge.egr_map) { | |
4366 | ret = -ENOMEM; | |
4367 | goto bye; | |
4368 | } | |
4369 | ||
4370 | adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, | |
4371 | sizeof(*adap->sge.ingr_map), GFP_KERNEL); | |
4372 | if (!adap->sge.ingr_map) { | |
4373 | ret = -ENOMEM; | |
4374 | goto bye; | |
4375 | } | |
4376 | ||
4377 | /* Allocate the memory for the vaious egress queue bitmaps | |
5b377d11 | 4378 | * ie starving_fl, txq_maperr and blocked_fl. |
4b8e27a8 HS |
4379 | */ |
4380 | adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
4381 | sizeof(long), GFP_KERNEL); | |
4382 | if (!adap->sge.starving_fl) { | |
4383 | ret = -ENOMEM; | |
4384 | goto bye; | |
4385 | } | |
4386 | ||
4387 | adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
4388 | sizeof(long), GFP_KERNEL); | |
4389 | if (!adap->sge.txq_maperr) { | |
4390 | ret = -ENOMEM; | |
4391 | goto bye; | |
4392 | } | |
4393 | ||
5b377d11 HS |
4394 | #ifdef CONFIG_DEBUG_FS |
4395 | adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
4396 | sizeof(long), GFP_KERNEL); | |
4397 | if (!adap->sge.blocked_fl) { | |
4398 | ret = -ENOMEM; | |
4399 | goto bye; | |
4400 | } | |
4401 | #endif | |
4402 | ||
b5a02f50 AB |
4403 | params[0] = FW_PARAM_PFVF(CLIP_START); |
4404 | params[1] = FW_PARAM_PFVF(CLIP_END); | |
b2612722 | 4405 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
b5a02f50 AB |
4406 | if (ret < 0) |
4407 | goto bye; | |
4408 | adap->clipt_start = val[0]; | |
4409 | adap->clipt_end = val[1]; | |
4410 | ||
b72a32da RL |
4411 | /* We don't yet have a PARAMs calls to retrieve the number of Traffic |
4412 | * Classes supported by the hardware/firmware so we hard code it here | |
4413 | * for now. | |
4414 | */ | |
4415 | adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16; | |
4416 | ||
636f9d37 VP |
4417 | /* query params related to active filter region */ |
4418 | params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); | |
4419 | params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); | |
b2612722 | 4420 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
636f9d37 VP |
4421 | /* If Active filter size is set we enable establishing |
4422 | * offload connection through firmware work request | |
4423 | */ | |
4424 | if ((val[0] != val[1]) && (ret >= 0)) { | |
4425 | adap->flags |= FW_OFLD_CONN; | |
4426 | adap->tids.aftid_base = val[0]; | |
4427 | adap->tids.aftid_end = val[1]; | |
4428 | } | |
4429 | ||
b407a4a9 VP |
4430 | /* If we're running on newer firmware, let it know that we're |
4431 | * prepared to deal with encapsulated CPL messages. Older | |
4432 | * firmware won't understand this and we'll just get | |
4433 | * unencapsulated messages ... | |
4434 | */ | |
4435 | params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); | |
4436 | val[0] = 1; | |
b2612722 | 4437 | (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); |
b407a4a9 | 4438 | |
1ac0f095 KS |
4439 | /* |
4440 | * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL | |
4441 | * capability. Earlier versions of the firmware didn't have the | |
4442 | * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no | |
4443 | * permission to use ULPTX MEMWRITE DSGL. | |
4444 | */ | |
4445 | if (is_t4(adap->params.chip)) { | |
4446 | adap->params.ulptx_memwrite_dsgl = false; | |
4447 | } else { | |
4448 | params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); | |
b2612722 | 4449 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, |
1ac0f095 KS |
4450 | 1, params, val); |
4451 | adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); | |
4452 | } | |
4453 | ||
086de575 SW |
4454 | /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */ |
4455 | params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); | |
4456 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, | |
4457 | 1, params, val); | |
4458 | adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); | |
4459 | ||
0ff90994 KS |
4460 | /* See if FW supports FW_FILTER2 work request */ |
4461 | if (is_t4(adap->params.chip)) { | |
4462 | adap->params.filter2_wr_support = 0; | |
4463 | } else { | |
4464 | params[0] = FW_PARAM_DEV(FILTER2_WR); | |
4465 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, | |
4466 | 1, params, val); | |
4467 | adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); | |
4468 | } | |
4469 | ||
636f9d37 VP |
4470 | /* |
4471 | * Get device capabilities so we can determine what resources we need | |
4472 | * to manage. | |
4473 | */ | |
4474 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
e2ac9628 HS |
4475 | caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
4476 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 4477 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
4478 | ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), |
4479 | &caps_cmd); | |
4480 | if (ret < 0) | |
4481 | goto bye; | |
4482 | ||
5c31254e KS |
4483 | if (caps_cmd.ofldcaps || |
4484 | (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) { | |
b8ff05a9 DM |
4485 | /* query offload-related parameters */ |
4486 | params[0] = FW_PARAM_DEV(NTID); | |
4487 | params[1] = FW_PARAM_PFVF(SERVER_START); | |
4488 | params[2] = FW_PARAM_PFVF(SERVER_END); | |
4489 | params[3] = FW_PARAM_PFVF(TDDP_START); | |
4490 | params[4] = FW_PARAM_PFVF(TDDP_END); | |
4491 | params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); | |
b2612722 | 4492 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 4493 | params, val); |
b8ff05a9 DM |
4494 | if (ret < 0) |
4495 | goto bye; | |
4496 | adap->tids.ntids = val[0]; | |
4497 | adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); | |
4498 | adap->tids.stid_base = val[1]; | |
4499 | adap->tids.nstids = val[2] - val[1] + 1; | |
636f9d37 | 4500 | /* |
dbedd44e | 4501 | * Setup server filter region. Divide the available filter |
636f9d37 VP |
4502 | * region into two parts. Regular filters get 1/3rd and server |
4503 | * filters get 2/3rd part. This is only enabled if workarond | |
4504 | * path is enabled. | |
4505 | * 1. For regular filters. | |
4506 | * 2. Server filter: This are special filters which are used | |
4507 | * to redirect SYN packets to offload queue. | |
4508 | */ | |
4509 | if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { | |
4510 | adap->tids.sftid_base = adap->tids.ftid_base + | |
4511 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
4512 | adap->tids.nsftids = adap->tids.nftids - | |
4513 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
4514 | adap->tids.nftids = adap->tids.sftid_base - | |
4515 | adap->tids.ftid_base; | |
4516 | } | |
b8ff05a9 DM |
4517 | adap->vres.ddp.start = val[3]; |
4518 | adap->vres.ddp.size = val[4] - val[3] + 1; | |
4519 | adap->params.ofldq_wr_cred = val[5]; | |
636f9d37 | 4520 | |
5c31254e | 4521 | if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) { |
004c3cf1 WY |
4522 | ret = init_hash_filter(adap); |
4523 | if (ret < 0) | |
5c31254e KS |
4524 | goto bye; |
4525 | } else { | |
4526 | adap->params.offload = 1; | |
4527 | adap->num_ofld_uld += 1; | |
4528 | } | |
b8ff05a9 | 4529 | } |
636f9d37 | 4530 | if (caps_cmd.rdmacaps) { |
b8ff05a9 DM |
4531 | params[0] = FW_PARAM_PFVF(STAG_START); |
4532 | params[1] = FW_PARAM_PFVF(STAG_END); | |
4533 | params[2] = FW_PARAM_PFVF(RQ_START); | |
4534 | params[3] = FW_PARAM_PFVF(RQ_END); | |
4535 | params[4] = FW_PARAM_PFVF(PBL_START); | |
4536 | params[5] = FW_PARAM_PFVF(PBL_END); | |
b2612722 | 4537 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 4538 | params, val); |
b8ff05a9 DM |
4539 | if (ret < 0) |
4540 | goto bye; | |
4541 | adap->vres.stag.start = val[0]; | |
4542 | adap->vres.stag.size = val[1] - val[0] + 1; | |
4543 | adap->vres.rq.start = val[2]; | |
4544 | adap->vres.rq.size = val[3] - val[2] + 1; | |
4545 | adap->vres.pbl.start = val[4]; | |
4546 | adap->vres.pbl.size = val[5] - val[4] + 1; | |
a0881cab | 4547 | |
c68644ef RR |
4548 | params[0] = FW_PARAM_PFVF(SRQ_START); |
4549 | params[1] = FW_PARAM_PFVF(SRQ_END); | |
4550 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, | |
4551 | params, val); | |
4552 | if (!ret) { | |
4553 | adap->vres.srq.start = val[0]; | |
4554 | adap->vres.srq.size = val[1] - val[0] + 1; | |
4555 | } | |
4556 | if (adap->vres.srq.size) { | |
4557 | adap->srq = t4_init_srq(adap->vres.srq.size); | |
4558 | if (!adap->srq) | |
4559 | dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n"); | |
4560 | } | |
4561 | ||
a0881cab DM |
4562 | params[0] = FW_PARAM_PFVF(SQRQ_START); |
4563 | params[1] = FW_PARAM_PFVF(SQRQ_END); | |
4564 | params[2] = FW_PARAM_PFVF(CQ_START); | |
4565 | params[3] = FW_PARAM_PFVF(CQ_END); | |
1ae970e0 DM |
4566 | params[4] = FW_PARAM_PFVF(OCQ_START); |
4567 | params[5] = FW_PARAM_PFVF(OCQ_END); | |
b2612722 | 4568 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, |
5c937dd3 | 4569 | val); |
a0881cab DM |
4570 | if (ret < 0) |
4571 | goto bye; | |
4572 | adap->vres.qp.start = val[0]; | |
4573 | adap->vres.qp.size = val[1] - val[0] + 1; | |
4574 | adap->vres.cq.start = val[2]; | |
4575 | adap->vres.cq.size = val[3] - val[2] + 1; | |
1ae970e0 DM |
4576 | adap->vres.ocq.start = val[4]; |
4577 | adap->vres.ocq.size = val[5] - val[4] + 1; | |
4c2c5763 HS |
4578 | |
4579 | params[0] = FW_PARAM_DEV(MAXORDIRD_QP); | |
4580 | params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); | |
b2612722 | 4581 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, |
5c937dd3 | 4582 | val); |
4c2c5763 HS |
4583 | if (ret < 0) { |
4584 | adap->params.max_ordird_qp = 8; | |
4585 | adap->params.max_ird_adapter = 32 * adap->tids.ntids; | |
4586 | ret = 0; | |
4587 | } else { | |
4588 | adap->params.max_ordird_qp = val[0]; | |
4589 | adap->params.max_ird_adapter = val[1]; | |
4590 | } | |
4591 | dev_info(adap->pdev_dev, | |
4592 | "max_ordird_qp %d max_ird_adapter %d\n", | |
4593 | adap->params.max_ordird_qp, | |
4594 | adap->params.max_ird_adapter); | |
43db9296 RR |
4595 | |
4596 | /* Enable write_with_immediate if FW supports it */ | |
4597 | params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM); | |
4598 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, | |
4599 | val); | |
4600 | adap->params.write_w_imm_support = (ret == 0 && val[0] != 0); | |
f3910c62 RR |
4601 | |
4602 | /* Enable write_cmpl if FW supports it */ | |
4603 | params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR); | |
4604 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, | |
4605 | val); | |
4606 | adap->params.write_cmpl_support = (ret == 0 && val[0] != 0); | |
0fbc81b3 | 4607 | adap->num_ofld_uld += 2; |
b8ff05a9 | 4608 | } |
636f9d37 | 4609 | if (caps_cmd.iscsicaps) { |
b8ff05a9 DM |
4610 | params[0] = FW_PARAM_PFVF(ISCSI_START); |
4611 | params[1] = FW_PARAM_PFVF(ISCSI_END); | |
b2612722 | 4612 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, |
636f9d37 | 4613 | params, val); |
b8ff05a9 DM |
4614 | if (ret < 0) |
4615 | goto bye; | |
4616 | adap->vres.iscsi.start = val[0]; | |
4617 | adap->vres.iscsi.size = val[1] - val[0] + 1; | |
0fbc81b3 HS |
4618 | /* LIO target and cxgb4i initiaitor */ |
4619 | adap->num_ofld_uld += 2; | |
b8ff05a9 | 4620 | } |
94cdb8bb | 4621 | if (caps_cmd.cryptocaps) { |
e383f248 AG |
4622 | if (ntohs(caps_cmd.cryptocaps) & |
4623 | FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) { | |
4624 | params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE); | |
4625 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, | |
4626 | 2, params, val); | |
4627 | if (ret < 0) { | |
4628 | if (ret != -EINVAL) | |
4629 | goto bye; | |
4630 | } else { | |
4631 | adap->vres.ncrypto_fc = val[0]; | |
4632 | } | |
4633 | adap->num_ofld_uld += 1; | |
4634 | } | |
4635 | if (ntohs(caps_cmd.cryptocaps) & | |
4636 | FW_CAPS_CONFIG_TLS_INLINE) { | |
4637 | params[0] = FW_PARAM_PFVF(TLS_START); | |
4638 | params[1] = FW_PARAM_PFVF(TLS_END); | |
4639 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, | |
4640 | 2, params, val); | |
4641 | if (ret < 0) | |
72a56ca9 | 4642 | goto bye; |
e383f248 AG |
4643 | adap->vres.key.start = val[0]; |
4644 | adap->vres.key.size = val[1] - val[0] + 1; | |
4645 | adap->num_uld += 1; | |
72a56ca9 | 4646 | } |
a6ec572b | 4647 | adap->params.crypto = ntohs(caps_cmd.cryptocaps); |
94cdb8bb | 4648 | } |
b8ff05a9 DM |
4649 | #undef FW_PARAM_PFVF |
4650 | #undef FW_PARAM_DEV | |
4651 | ||
92e7ae71 HS |
4652 | /* The MTU/MSS Table is initialized by now, so load their values. If |
4653 | * we're initializing the adapter, then we'll make any modifications | |
4654 | * we want to the MTU/MSS Table and also initialize the congestion | |
4655 | * parameters. | |
636f9d37 | 4656 | */ |
b8ff05a9 | 4657 | t4_read_mtu_tbl(adap, adap->params.mtus, NULL); |
92e7ae71 HS |
4658 | if (state != DEV_STATE_INIT) { |
4659 | int i; | |
4660 | ||
4661 | /* The default MTU Table contains values 1492 and 1500. | |
4662 | * However, for TCP, it's better to have two values which are | |
4663 | * a multiple of 8 +/- 4 bytes apart near this popular MTU. | |
4664 | * This allows us to have a TCP Data Payload which is a | |
4665 | * multiple of 8 regardless of what combination of TCP Options | |
4666 | * are in use (always a multiple of 4 bytes) which is | |
4667 | * important for performance reasons. For instance, if no | |
4668 | * options are in use, then we have a 20-byte IP header and a | |
4669 | * 20-byte TCP header. In this case, a 1500-byte MSS would | |
4670 | * result in a TCP Data Payload of 1500 - 40 == 1460 bytes | |
4671 | * which is not a multiple of 8. So using an MSS of 1488 in | |
4672 | * this case results in a TCP Data Payload of 1448 bytes which | |
4673 | * is a multiple of 8. On the other hand, if 12-byte TCP Time | |
4674 | * Stamps have been negotiated, then an MTU of 1500 bytes | |
4675 | * results in a TCP Data Payload of 1448 bytes which, as | |
4676 | * above, is a multiple of 8 bytes ... | |
4677 | */ | |
4678 | for (i = 0; i < NMTUS; i++) | |
4679 | if (adap->params.mtus[i] == 1492) { | |
4680 | adap->params.mtus[i] = 1488; | |
4681 | break; | |
4682 | } | |
7ee9ff94 | 4683 | |
92e7ae71 HS |
4684 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, |
4685 | adap->params.b_wnd); | |
4686 | } | |
df64e4d3 | 4687 | t4_init_sge_params(adap); |
636f9d37 | 4688 | adap->flags |= FW_OK; |
5ccf9d04 | 4689 | t4_init_tp_params(adap, true); |
b8ff05a9 DM |
4690 | return 0; |
4691 | ||
4692 | /* | |
636f9d37 VP |
4693 | * Something bad happened. If a command timed out or failed with EIO |
4694 | * FW does not operate within its spec or something catastrophic | |
4695 | * happened to HW/FW, stop issuing commands. | |
b8ff05a9 | 4696 | */ |
636f9d37 | 4697 | bye: |
8b4e6b3c | 4698 | adap_free_hma_mem(adap); |
4b8e27a8 HS |
4699 | kfree(adap->sge.egr_map); |
4700 | kfree(adap->sge.ingr_map); | |
4701 | kfree(adap->sge.starving_fl); | |
4702 | kfree(adap->sge.txq_maperr); | |
5b377d11 HS |
4703 | #ifdef CONFIG_DEBUG_FS |
4704 | kfree(adap->sge.blocked_fl); | |
4705 | #endif | |
636f9d37 VP |
4706 | if (ret != -ETIMEDOUT && ret != -EIO) |
4707 | t4_fw_bye(adap, adap->mbox); | |
b8ff05a9 DM |
4708 | return ret; |
4709 | } | |
4710 | ||
204dc3c0 DM |
4711 | /* EEH callbacks */ |
4712 | ||
4713 | static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, | |
4714 | pci_channel_state_t state) | |
4715 | { | |
4716 | int i; | |
4717 | struct adapter *adap = pci_get_drvdata(pdev); | |
4718 | ||
4719 | if (!adap) | |
4720 | goto out; | |
4721 | ||
4722 | rtnl_lock(); | |
4723 | adap->flags &= ~FW_OK; | |
4724 | notify_ulds(adap, CXGB4_STATE_START_RECOVERY); | |
9fe6cb58 | 4725 | spin_lock(&adap->stats_lock); |
204dc3c0 DM |
4726 | for_each_port(adap, i) { |
4727 | struct net_device *dev = adap->port[i]; | |
025d0973 GP |
4728 | if (dev) { |
4729 | netif_device_detach(dev); | |
4730 | netif_carrier_off(dev); | |
4731 | } | |
204dc3c0 | 4732 | } |
9fe6cb58 | 4733 | spin_unlock(&adap->stats_lock); |
b37987e8 | 4734 | disable_interrupts(adap); |
204dc3c0 DM |
4735 | if (adap->flags & FULL_INIT_DONE) |
4736 | cxgb_down(adap); | |
4737 | rtnl_unlock(); | |
144be3d9 GS |
4738 | if ((adap->flags & DEV_ENABLED)) { |
4739 | pci_disable_device(pdev); | |
4740 | adap->flags &= ~DEV_ENABLED; | |
4741 | } | |
204dc3c0 DM |
4742 | out: return state == pci_channel_io_perm_failure ? |
4743 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
4744 | } | |
4745 | ||
4746 | static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) | |
4747 | { | |
4748 | int i, ret; | |
4749 | struct fw_caps_config_cmd c; | |
4750 | struct adapter *adap = pci_get_drvdata(pdev); | |
4751 | ||
4752 | if (!adap) { | |
4753 | pci_restore_state(pdev); | |
4754 | pci_save_state(pdev); | |
4755 | return PCI_ERS_RESULT_RECOVERED; | |
4756 | } | |
4757 | ||
144be3d9 GS |
4758 | if (!(adap->flags & DEV_ENABLED)) { |
4759 | if (pci_enable_device(pdev)) { | |
4760 | dev_err(&pdev->dev, "Cannot reenable PCI " | |
4761 | "device after reset\n"); | |
4762 | return PCI_ERS_RESULT_DISCONNECT; | |
4763 | } | |
4764 | adap->flags |= DEV_ENABLED; | |
204dc3c0 DM |
4765 | } |
4766 | ||
4767 | pci_set_master(pdev); | |
4768 | pci_restore_state(pdev); | |
4769 | pci_save_state(pdev); | |
4770 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
4771 | ||
8203b509 | 4772 | if (t4_wait_dev_ready(adap->regs) < 0) |
204dc3c0 | 4773 | return PCI_ERS_RESULT_DISCONNECT; |
b2612722 | 4774 | if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) |
204dc3c0 DM |
4775 | return PCI_ERS_RESULT_DISCONNECT; |
4776 | adap->flags |= FW_OK; | |
4777 | if (adap_init1(adap, &c)) | |
4778 | return PCI_ERS_RESULT_DISCONNECT; | |
4779 | ||
4780 | for_each_port(adap, i) { | |
4781 | struct port_info *p = adap2pinfo(adap, i); | |
4782 | ||
b2612722 | 4783 | ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, |
060e0c75 | 4784 | NULL, NULL); |
204dc3c0 DM |
4785 | if (ret < 0) |
4786 | return PCI_ERS_RESULT_DISCONNECT; | |
4787 | p->viid = ret; | |
4788 | p->xact_addr_filt = -1; | |
4789 | } | |
4790 | ||
4791 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, | |
4792 | adap->params.b_wnd); | |
1ae970e0 | 4793 | setup_memwin(adap); |
204dc3c0 DM |
4794 | if (cxgb_up(adap)) |
4795 | return PCI_ERS_RESULT_DISCONNECT; | |
4796 | return PCI_ERS_RESULT_RECOVERED; | |
4797 | } | |
4798 | ||
4799 | static void eeh_resume(struct pci_dev *pdev) | |
4800 | { | |
4801 | int i; | |
4802 | struct adapter *adap = pci_get_drvdata(pdev); | |
4803 | ||
4804 | if (!adap) | |
4805 | return; | |
4806 | ||
4807 | rtnl_lock(); | |
4808 | for_each_port(adap, i) { | |
4809 | struct net_device *dev = adap->port[i]; | |
025d0973 GP |
4810 | if (dev) { |
4811 | if (netif_running(dev)) { | |
4812 | link_start(dev); | |
4813 | cxgb_set_rxmode(dev); | |
4814 | } | |
4815 | netif_device_attach(dev); | |
204dc3c0 | 4816 | } |
204dc3c0 DM |
4817 | } |
4818 | rtnl_unlock(); | |
4819 | } | |
4820 | ||
3646f0e5 | 4821 | static const struct pci_error_handlers cxgb4_eeh = { |
204dc3c0 DM |
4822 | .error_detected = eeh_err_detected, |
4823 | .slot_reset = eeh_slot_reset, | |
4824 | .resume = eeh_resume, | |
4825 | }; | |
4826 | ||
9b86a8d1 HS |
4827 | /* Return true if the Link Configuration supports "High Speeds" (those greater |
4828 | * than 1Gb/s). | |
4829 | */ | |
57d8b764 | 4830 | static inline bool is_x_10g_port(const struct link_config *lc) |
b8ff05a9 | 4831 | { |
9b86a8d1 HS |
4832 | unsigned int speeds, high_speeds; |
4833 | ||
c3168cab GG |
4834 | speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps)); |
4835 | high_speeds = speeds & | |
4836 | ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); | |
9b86a8d1 HS |
4837 | |
4838 | return high_speeds != 0; | |
b8ff05a9 DM |
4839 | } |
4840 | ||
b8ff05a9 DM |
4841 | /* |
4842 | * Perform default configuration of DMA queues depending on the number and type | |
4843 | * of ports we found and the number of available CPUs. Most settings can be | |
4844 | * modified by the admin prior to actual use. | |
4845 | */ | |
0eaec62a | 4846 | static int cfg_queues(struct adapter *adap) |
b8ff05a9 DM |
4847 | { |
4848 | struct sge *s = &adap->sge; | |
0eaec62a CL |
4849 | int i, n10g = 0, qidx = 0; |
4850 | int niqflint, neq, avail_eth_qsets; | |
4851 | int max_eth_qsets = 32; | |
688848b1 AB |
4852 | #ifndef CONFIG_CHELSIO_T4_DCB |
4853 | int q10g = 0; | |
4854 | #endif | |
b8ff05a9 | 4855 | |
94cdb8bb HS |
4856 | /* Reduce memory usage in kdump environment, disable all offload. |
4857 | */ | |
85eacf3f | 4858 | if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) { |
0fbc81b3 | 4859 | adap->params.offload = 0; |
94cdb8bb HS |
4860 | adap->params.crypto = 0; |
4861 | } | |
4862 | ||
0eaec62a CL |
4863 | /* Calculate the number of Ethernet Queue Sets available based on |
4864 | * resources provisioned for us. We always have an Asynchronous | |
4865 | * Firmware Event Ingress Queue. If we're operating in MSI or Legacy | |
4866 | * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt | |
4867 | * Ingress Queue. Meanwhile, we need two Egress Queues for each | |
4868 | * Queue Set: one for the Free List and one for the Ethernet TX Queue. | |
4869 | * | |
4870 | * Note that we should also take into account all of the various | |
4871 | * Offload Queues. But, in any situation where we're operating in | |
4872 | * a Resource Constrained Provisioning environment, doing any Offload | |
4873 | * at all is problematic ... | |
4874 | */ | |
4875 | niqflint = adap->params.pfres.niqflint - 1; | |
4876 | if (!(adap->flags & USING_MSIX)) | |
4877 | niqflint--; | |
4878 | neq = adap->params.pfres.neq / 2; | |
4879 | avail_eth_qsets = min(niqflint, neq); | |
4880 | ||
4881 | if (avail_eth_qsets > max_eth_qsets) | |
4882 | avail_eth_qsets = max_eth_qsets; | |
4883 | ||
4884 | if (avail_eth_qsets < adap->params.nports) { | |
4885 | dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n", | |
4886 | avail_eth_qsets, adap->params.nports); | |
4887 | return -ENOMEM; | |
4888 | } | |
4889 | ||
4890 | /* Count the number of 10Gb/s or better ports */ | |
4891 | for_each_port(adap, i) | |
4892 | n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); | |
4893 | ||
688848b1 AB |
4894 | #ifdef CONFIG_CHELSIO_T4_DCB |
4895 | /* For Data Center Bridging support we need to be able to support up | |
4896 | * to 8 Traffic Priorities; each of which will be assigned to its | |
4897 | * own TX Queue in order to prevent Head-Of-Line Blocking. | |
4898 | */ | |
0eaec62a CL |
4899 | if (adap->params.nports * 8 > avail_eth_qsets) { |
4900 | dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n", | |
4901 | avail_eth_qsets, adap->params.nports * 8); | |
4902 | return -ENOMEM; | |
688848b1 | 4903 | } |
b8ff05a9 | 4904 | |
688848b1 AB |
4905 | for_each_port(adap, i) { |
4906 | struct port_info *pi = adap2pinfo(adap, i); | |
4907 | ||
4908 | pi->first_qset = qidx; | |
85eacf3f | 4909 | pi->nqsets = is_kdump_kernel() ? 1 : 8; |
688848b1 AB |
4910 | qidx += pi->nqsets; |
4911 | } | |
4912 | #else /* !CONFIG_CHELSIO_T4_DCB */ | |
b8ff05a9 DM |
4913 | /* |
4914 | * We default to 1 queue per non-10G port and up to # of cores queues | |
4915 | * per 10G port. | |
4916 | */ | |
4917 | if (n10g) | |
0eaec62a | 4918 | q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g; |
5952dde7 YM |
4919 | if (q10g > netif_get_num_default_rss_queues()) |
4920 | q10g = netif_get_num_default_rss_queues(); | |
b8ff05a9 | 4921 | |
85eacf3f GG |
4922 | if (is_kdump_kernel()) |
4923 | q10g = 1; | |
4924 | ||
b8ff05a9 DM |
4925 | for_each_port(adap, i) { |
4926 | struct port_info *pi = adap2pinfo(adap, i); | |
4927 | ||
4928 | pi->first_qset = qidx; | |
57d8b764 | 4929 | pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; |
b8ff05a9 DM |
4930 | qidx += pi->nqsets; |
4931 | } | |
688848b1 | 4932 | #endif /* !CONFIG_CHELSIO_T4_DCB */ |
b8ff05a9 DM |
4933 | |
4934 | s->ethqsets = qidx; | |
4935 | s->max_ethqsets = qidx; /* MSI-X may lower it later */ | |
4936 | ||
0fbc81b3 | 4937 | if (is_uld(adap)) { |
b8ff05a9 DM |
4938 | /* |
4939 | * For offload we use 1 queue/channel if all ports are up to 1G, | |
4940 | * otherwise we divide all available queues amongst the channels | |
4941 | * capped by the number of available cores. | |
4942 | */ | |
4943 | if (n10g) { | |
a56177e1 | 4944 | i = min_t(int, MAX_OFLD_QSETS, num_online_cpus()); |
0fbc81b3 HS |
4945 | s->ofldqsets = roundup(i, adap->params.nports); |
4946 | } else { | |
4947 | s->ofldqsets = adap->params.nports; | |
4948 | } | |
b8ff05a9 DM |
4949 | } |
4950 | ||
4951 | for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { | |
4952 | struct sge_eth_rxq *r = &s->ethrxq[i]; | |
4953 | ||
c887ad0e | 4954 | init_rspq(adap, &r->rspq, 5, 10, 1024, 64); |
b8ff05a9 DM |
4955 | r->fl.size = 72; |
4956 | } | |
4957 | ||
4958 | for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) | |
4959 | s->ethtxq[i].q.size = 1024; | |
4960 | ||
4961 | for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) | |
4962 | s->ctrlq[i].q.size = 512; | |
4963 | ||
a4569504 AG |
4964 | if (!is_t4(adap->params.chip)) |
4965 | s->ptptxq.q.size = 8; | |
4966 | ||
c887ad0e | 4967 | init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); |
0fbc81b3 | 4968 | init_rspq(adap, &s->intrq, 0, 1, 512, 64); |
0eaec62a CL |
4969 | |
4970 | return 0; | |
b8ff05a9 DM |
4971 | } |
4972 | ||
4973 | /* | |
4974 | * Reduce the number of Ethernet queues across all ports to at most n. | |
4975 | * n provides at least one queue per port. | |
4976 | */ | |
91744948 | 4977 | static void reduce_ethqs(struct adapter *adap, int n) |
b8ff05a9 DM |
4978 | { |
4979 | int i; | |
4980 | struct port_info *pi; | |
4981 | ||
4982 | while (n < adap->sge.ethqsets) | |
4983 | for_each_port(adap, i) { | |
4984 | pi = adap2pinfo(adap, i); | |
4985 | if (pi->nqsets > 1) { | |
4986 | pi->nqsets--; | |
4987 | adap->sge.ethqsets--; | |
4988 | if (adap->sge.ethqsets <= n) | |
4989 | break; | |
4990 | } | |
4991 | } | |
4992 | ||
4993 | n = 0; | |
4994 | for_each_port(adap, i) { | |
4995 | pi = adap2pinfo(adap, i); | |
4996 | pi->first_qset = n; | |
4997 | n += pi->nqsets; | |
4998 | } | |
4999 | } | |
5000 | ||
94cdb8bb HS |
5001 | static int get_msix_info(struct adapter *adap) |
5002 | { | |
5003 | struct uld_msix_info *msix_info; | |
0fbc81b3 HS |
5004 | unsigned int max_ingq = 0; |
5005 | ||
5006 | if (is_offload(adap)) | |
5007 | max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld; | |
5008 | if (is_pci_uld(adap)) | |
5009 | max_ingq += MAX_OFLD_QSETS * adap->num_uld; | |
5010 | ||
5011 | if (!max_ingq) | |
5012 | goto out; | |
94cdb8bb HS |
5013 | |
5014 | msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL); | |
5015 | if (!msix_info) | |
5016 | return -ENOMEM; | |
5017 | ||
5018 | adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq), | |
5019 | sizeof(long), GFP_KERNEL); | |
5020 | if (!adap->msix_bmap_ulds.msix_bmap) { | |
5021 | kfree(msix_info); | |
5022 | return -ENOMEM; | |
5023 | } | |
5024 | spin_lock_init(&adap->msix_bmap_ulds.lock); | |
5025 | adap->msix_info_ulds = msix_info; | |
0fbc81b3 | 5026 | out: |
94cdb8bb HS |
5027 | return 0; |
5028 | } | |
5029 | ||
5030 | static void free_msix_info(struct adapter *adap) | |
5031 | { | |
0fbc81b3 | 5032 | if (!(adap->num_uld && adap->num_ofld_uld)) |
94cdb8bb HS |
5033 | return; |
5034 | ||
5035 | kfree(adap->msix_info_ulds); | |
5036 | kfree(adap->msix_bmap_ulds.msix_bmap); | |
5037 | } | |
5038 | ||
b8ff05a9 DM |
5039 | /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ |
5040 | #define EXTRA_VECS 2 | |
5041 | ||
91744948 | 5042 | static int enable_msix(struct adapter *adap) |
b8ff05a9 | 5043 | { |
94cdb8bb HS |
5044 | int ofld_need = 0, uld_need = 0; |
5045 | int i, j, want, need, allocated; | |
b8ff05a9 DM |
5046 | struct sge *s = &adap->sge; |
5047 | unsigned int nchan = adap->params.nports; | |
f36e58e5 | 5048 | struct msix_entry *entries; |
94cdb8bb | 5049 | int max_ingq = MAX_INGQ; |
f36e58e5 | 5050 | |
0fbc81b3 HS |
5051 | if (is_pci_uld(adap)) |
5052 | max_ingq += (MAX_OFLD_QSETS * adap->num_uld); | |
5053 | if (is_offload(adap)) | |
5054 | max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld); | |
6da2ec56 KC |
5055 | entries = kmalloc_array(max_ingq + 1, sizeof(*entries), |
5056 | GFP_KERNEL); | |
f36e58e5 HS |
5057 | if (!entries) |
5058 | return -ENOMEM; | |
b8ff05a9 | 5059 | |
94cdb8bb | 5060 | /* map for msix */ |
0fbc81b3 HS |
5061 | if (get_msix_info(adap)) { |
5062 | adap->params.offload = 0; | |
94cdb8bb | 5063 | adap->params.crypto = 0; |
0fbc81b3 | 5064 | } |
94cdb8bb HS |
5065 | |
5066 | for (i = 0; i < max_ingq + 1; ++i) | |
b8ff05a9 DM |
5067 | entries[i].entry = i; |
5068 | ||
5069 | want = s->max_ethqsets + EXTRA_VECS; | |
5070 | if (is_offload(adap)) { | |
0fbc81b3 HS |
5071 | want += adap->num_ofld_uld * s->ofldqsets; |
5072 | ofld_need = adap->num_ofld_uld * nchan; | |
b8ff05a9 | 5073 | } |
94cdb8bb | 5074 | if (is_pci_uld(adap)) { |
0fbc81b3 HS |
5075 | want += adap->num_uld * s->ofldqsets; |
5076 | uld_need = adap->num_uld * nchan; | |
94cdb8bb | 5077 | } |
688848b1 AB |
5078 | #ifdef CONFIG_CHELSIO_T4_DCB |
5079 | /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for | |
5080 | * each port. | |
5081 | */ | |
94cdb8bb | 5082 | need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need; |
688848b1 | 5083 | #else |
94cdb8bb | 5084 | need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need; |
688848b1 | 5085 | #endif |
f36e58e5 HS |
5086 | allocated = pci_enable_msix_range(adap->pdev, entries, need, want); |
5087 | if (allocated < 0) { | |
5088 | dev_info(adap->pdev_dev, "not enough MSI-X vectors left," | |
5089 | " not using MSI-X\n"); | |
5090 | kfree(entries); | |
5091 | return allocated; | |
5092 | } | |
b8ff05a9 | 5093 | |
f36e58e5 | 5094 | /* Distribute available vectors to the various queue groups. |
c32ad224 AG |
5095 | * Every group gets its minimum requirement and NIC gets top |
5096 | * priority for leftovers. | |
5097 | */ | |
94cdb8bb | 5098 | i = allocated - EXTRA_VECS - ofld_need - uld_need; |
c32ad224 AG |
5099 | if (i < s->max_ethqsets) { |
5100 | s->max_ethqsets = i; | |
5101 | if (i < s->ethqsets) | |
5102 | reduce_ethqs(adap, i); | |
5103 | } | |
0fbc81b3 | 5104 | if (is_uld(adap)) { |
94cdb8bb HS |
5105 | if (allocated < want) |
5106 | s->nqs_per_uld = nchan; | |
5107 | else | |
0fbc81b3 | 5108 | s->nqs_per_uld = s->ofldqsets; |
94cdb8bb HS |
5109 | } |
5110 | ||
0fbc81b3 | 5111 | for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i) |
c32ad224 | 5112 | adap->msix_info[i].vec = entries[i].vector; |
0fbc81b3 HS |
5113 | if (is_uld(adap)) { |
5114 | for (j = 0 ; i < allocated; ++i, j++) { | |
94cdb8bb | 5115 | adap->msix_info_ulds[j].vec = entries[i].vector; |
0fbc81b3 HS |
5116 | adap->msix_info_ulds[j].idx = i; |
5117 | } | |
94cdb8bb HS |
5118 | adap->msix_bmap_ulds.mapsize = j; |
5119 | } | |
43eb4e82 | 5120 | dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " |
0fbc81b3 HS |
5121 | "nic %d per uld %d\n", |
5122 | allocated, s->max_ethqsets, s->nqs_per_uld); | |
c32ad224 | 5123 | |
f36e58e5 | 5124 | kfree(entries); |
c32ad224 | 5125 | return 0; |
b8ff05a9 DM |
5126 | } |
5127 | ||
5128 | #undef EXTRA_VECS | |
5129 | ||
91744948 | 5130 | static int init_rss(struct adapter *adap) |
671b0060 | 5131 | { |
c035e183 HS |
5132 | unsigned int i; |
5133 | int err; | |
5134 | ||
5135 | err = t4_init_rss_mode(adap, adap->mbox); | |
5136 | if (err) | |
5137 | return err; | |
671b0060 DM |
5138 | |
5139 | for_each_port(adap, i) { | |
5140 | struct port_info *pi = adap2pinfo(adap, i); | |
5141 | ||
5142 | pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); | |
5143 | if (!pi->rss) | |
5144 | return -ENOMEM; | |
671b0060 DM |
5145 | } |
5146 | return 0; | |
5147 | } | |
5148 | ||
0de72738 HS |
5149 | /* Dump basic information about the adapter */ |
5150 | static void print_adapter_info(struct adapter *adapter) | |
5151 | { | |
760446f9 GG |
5152 | /* Hardware/Firmware/etc. Version/Revision IDs */ |
5153 | t4_dump_version_info(adapter); | |
0de72738 HS |
5154 | |
5155 | /* Software/Hardware configuration */ | |
5156 | dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", | |
5157 | is_offload(adapter) ? "R" : "", | |
5158 | ((adapter->flags & USING_MSIX) ? "MSI-X" : | |
5159 | (adapter->flags & USING_MSI) ? "MSI" : ""), | |
5160 | is_offload(adapter) ? "Offload" : "non-Offload"); | |
5161 | } | |
5162 | ||
91744948 | 5163 | static void print_port_info(const struct net_device *dev) |
b8ff05a9 | 5164 | { |
b8ff05a9 | 5165 | char buf[80]; |
118969ed | 5166 | char *bufp = buf; |
118969ed DM |
5167 | const struct port_info *pi = netdev_priv(dev); |
5168 | const struct adapter *adap = pi->adapter; | |
f1a051b9 | 5169 | |
c3168cab | 5170 | if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) |
5e78f7fd | 5171 | bufp += sprintf(bufp, "100M/"); |
c3168cab | 5172 | if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) |
5e78f7fd | 5173 | bufp += sprintf(bufp, "1G/"); |
c3168cab | 5174 | if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) |
118969ed | 5175 | bufp += sprintf(bufp, "10G/"); |
c3168cab | 5176 | if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) |
9b86a8d1 | 5177 | bufp += sprintf(bufp, "25G/"); |
c3168cab | 5178 | if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) |
72aca4bf | 5179 | bufp += sprintf(bufp, "40G/"); |
c3168cab GG |
5180 | if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) |
5181 | bufp += sprintf(bufp, "50G/"); | |
5182 | if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) | |
9b86a8d1 | 5183 | bufp += sprintf(bufp, "100G/"); |
c3168cab GG |
5184 | if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G) |
5185 | bufp += sprintf(bufp, "200G/"); | |
5186 | if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G) | |
5187 | bufp += sprintf(bufp, "400G/"); | |
118969ed DM |
5188 | if (bufp != buf) |
5189 | --bufp; | |
72aca4bf | 5190 | sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); |
118969ed | 5191 | |
0de72738 HS |
5192 | netdev_info(dev, "%s: Chelsio %s (%s) %s\n", |
5193 | dev->name, adap->params.vpd.id, adap->name, buf); | |
b8ff05a9 DM |
5194 | } |
5195 | ||
06546391 DM |
5196 | /* |
5197 | * Free the following resources: | |
5198 | * - memory used for tables | |
5199 | * - MSI/MSI-X | |
5200 | * - net devices | |
5201 | * - resources FW is holding for us | |
5202 | */ | |
5203 | static void free_some_resources(struct adapter *adapter) | |
5204 | { | |
5205 | unsigned int i; | |
5206 | ||
0e249898 | 5207 | kvfree(adapter->mps_encap); |
3bdb376e | 5208 | kvfree(adapter->smt); |
752ade68 | 5209 | kvfree(adapter->l2t); |
c68644ef | 5210 | kvfree(adapter->srq); |
b72a32da | 5211 | t4_cleanup_sched(adapter); |
752ade68 | 5212 | kvfree(adapter->tids.tid_tab); |
e0f911c8 | 5213 | cxgb4_cleanup_tc_flower(adapter); |
d8931847 | 5214 | cxgb4_cleanup_tc_u32(adapter); |
4b8e27a8 HS |
5215 | kfree(adapter->sge.egr_map); |
5216 | kfree(adapter->sge.ingr_map); | |
5217 | kfree(adapter->sge.starving_fl); | |
5218 | kfree(adapter->sge.txq_maperr); | |
5b377d11 HS |
5219 | #ifdef CONFIG_DEBUG_FS |
5220 | kfree(adapter->sge.blocked_fl); | |
5221 | #endif | |
06546391 DM |
5222 | disable_msi(adapter); |
5223 | ||
5224 | for_each_port(adapter, i) | |
671b0060 | 5225 | if (adapter->port[i]) { |
4f3a0fcf HS |
5226 | struct port_info *pi = adap2pinfo(adapter, i); |
5227 | ||
5228 | if (pi->viid != 0) | |
5229 | t4_free_vi(adapter, adapter->mbox, adapter->pf, | |
5230 | 0, pi->viid); | |
671b0060 | 5231 | kfree(adap2pinfo(adapter, i)->rss); |
06546391 | 5232 | free_netdev(adapter->port[i]); |
671b0060 | 5233 | } |
06546391 | 5234 | if (adapter->flags & FW_OK) |
b2612722 | 5235 | t4_fw_bye(adapter, adapter->pf); |
06546391 DM |
5236 | } |
5237 | ||
2ed28baa | 5238 | #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) |
35d35682 | 5239 | #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ |
b8ff05a9 | 5240 | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) |
22adfe0a | 5241 | #define SEGMENT_SIZE 128 |
b8ff05a9 | 5242 | |
e8d45292 | 5243 | static int t4_get_chip_type(struct adapter *adap, int ver) |
d86bd29e | 5244 | { |
e8d45292 | 5245 | u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A)); |
46cdc9be | 5246 | |
e8d45292 | 5247 | switch (ver) { |
d86bd29e | 5248 | case CHELSIO_T4: |
46cdc9be | 5249 | return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); |
d86bd29e | 5250 | case CHELSIO_T5: |
46cdc9be | 5251 | return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); |
d86bd29e | 5252 | case CHELSIO_T6: |
46cdc9be | 5253 | return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); |
d86bd29e | 5254 | default: |
e8d45292 | 5255 | break; |
d86bd29e | 5256 | } |
46cdc9be | 5257 | return -EINVAL; |
d86bd29e HS |
5258 | } |
5259 | ||
b6244201 | 5260 | #ifdef CONFIG_PCI_IOV |
baf50868 | 5261 | static void cxgb4_mgmt_setup(struct net_device *dev) |
e7b48a32 HS |
5262 | { |
5263 | dev->type = ARPHRD_NONE; | |
5264 | dev->mtu = 0; | |
5265 | dev->hard_header_len = 0; | |
5266 | dev->addr_len = 0; | |
5267 | dev->tx_queue_len = 0; | |
5268 | dev->flags |= IFF_NOARP; | |
5269 | dev->priv_flags |= IFF_NO_QUEUE; | |
5270 | ||
5271 | /* Initialize the device structure. */ | |
5272 | dev->netdev_ops = &cxgb4_mgmt_netdev_ops; | |
5273 | dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops; | |
e7b48a32 HS |
5274 | } |
5275 | ||
b6244201 HS |
5276 | static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) |
5277 | { | |
7829451c | 5278 | struct adapter *adap = pci_get_drvdata(pdev); |
b6244201 HS |
5279 | int err = 0; |
5280 | int current_vfs = pci_num_vf(pdev); | |
5281 | u32 pcie_fw; | |
b6244201 | 5282 | |
7829451c | 5283 | pcie_fw = readl(adap->regs + PCIE_FW_A); |
7cfac881 AV |
5284 | /* Check if fw is initialized */ |
5285 | if (!(pcie_fw & PCIE_FW_INIT_F)) { | |
5286 | dev_warn(&pdev->dev, "Device not initialized\n"); | |
b6244201 HS |
5287 | return -EOPNOTSUPP; |
5288 | } | |
5289 | ||
5290 | /* If any of the VF's is already assigned to Guest OS, then | |
5291 | * SRIOV for the same cannot be modified | |
5292 | */ | |
5293 | if (current_vfs && pci_vfs_assigned(pdev)) { | |
5294 | dev_err(&pdev->dev, | |
5295 | "Cannot modify SR-IOV while VFs are assigned\n"); | |
baf50868 | 5296 | return current_vfs; |
b6244201 | 5297 | } |
baf50868 GG |
5298 | /* Note that the upper-level code ensures that we're never called with |
5299 | * a non-zero "num_vfs" when we already have VFs instantiated. But | |
5300 | * it never hurts to code defensively. | |
b6244201 | 5301 | */ |
baf50868 GG |
5302 | if (num_vfs != 0 && current_vfs != 0) |
5303 | return -EBUSY; | |
5304 | ||
5305 | /* Nothing to do for no change. */ | |
5306 | if (num_vfs == current_vfs) | |
5307 | return num_vfs; | |
5308 | ||
5309 | /* Disable SRIOV when zero is passed. */ | |
b6244201 HS |
5310 | if (!num_vfs) { |
5311 | pci_disable_sriov(pdev); | |
baf50868 GG |
5312 | /* free VF Management Interface */ |
5313 | unregister_netdev(adap->port[0]); | |
5314 | free_netdev(adap->port[0]); | |
5315 | adap->port[0] = NULL; | |
5316 | ||
661dbeb9 | 5317 | /* free VF resources */ |
baf50868 | 5318 | adap->num_vfs = 0; |
661dbeb9 HS |
5319 | kfree(adap->vfinfo); |
5320 | adap->vfinfo = NULL; | |
baf50868 | 5321 | return 0; |
b6244201 HS |
5322 | } |
5323 | ||
baf50868 GG |
5324 | if (!current_vfs) { |
5325 | struct fw_pfvf_cmd port_cmd, port_rpl; | |
5326 | struct net_device *netdev; | |
5327 | unsigned int pmask, port; | |
5328 | struct pci_dev *pbridge; | |
5329 | struct port_info *pi; | |
5330 | char name[IFNAMSIZ]; | |
5331 | u32 devcap2; | |
5332 | u16 flags; | |
5333 | int pos; | |
5334 | ||
5335 | /* If we want to instantiate Virtual Functions, then our | |
5336 | * parent bridge's PCI-E needs to support Alternative Routing | |
5337 | * ID (ARI) because our VFs will show up at function offset 8 | |
5338 | * and above. | |
5339 | */ | |
5340 | pbridge = pdev->bus->self; | |
5341 | pos = pci_find_capability(pbridge, PCI_CAP_ID_EXP); | |
5342 | pci_read_config_word(pbridge, pos + PCI_EXP_FLAGS, &flags); | |
5343 | pci_read_config_dword(pbridge, pos + PCI_EXP_DEVCAP2, &devcap2); | |
5344 | ||
5345 | if ((flags & PCI_EXP_FLAGS_VERS) < 2 || | |
5346 | !(devcap2 & PCI_EXP_DEVCAP2_ARI)) { | |
5347 | /* Our parent bridge does not support ARI so issue a | |
5348 | * warning and skip instantiating the VFs. They | |
5349 | * won't be reachable. | |
5350 | */ | |
5351 | dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n", | |
5352 | pbridge->bus->number, PCI_SLOT(pbridge->devfn), | |
5353 | PCI_FUNC(pbridge->devfn)); | |
5354 | return -ENOTSUPP; | |
5355 | } | |
5356 | memset(&port_cmd, 0, sizeof(port_cmd)); | |
5357 | port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | | |
5358 | FW_CMD_REQUEST_F | | |
5359 | FW_CMD_READ_F | | |
5360 | FW_PFVF_CMD_PFN_V(adap->pf) | | |
5361 | FW_PFVF_CMD_VFN_V(0)); | |
5362 | port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd)); | |
5363 | err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd), | |
5364 | &port_rpl); | |
b6244201 HS |
5365 | if (err) |
5366 | return err; | |
baf50868 GG |
5367 | pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq)); |
5368 | port = ffs(pmask) - 1; | |
5369 | /* Allocate VF Management Interface. */ | |
5370 | snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx, | |
5371 | adap->pf); | |
5372 | netdev = alloc_netdev(sizeof(struct port_info), | |
5373 | name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup); | |
5374 | if (!netdev) | |
5375 | return -ENOMEM; | |
7829451c | 5376 | |
baf50868 GG |
5377 | pi = netdev_priv(netdev); |
5378 | pi->adapter = adap; | |
5379 | pi->lport = port; | |
5380 | pi->tx_chan = port; | |
5381 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
5382 | ||
5383 | adap->port[0] = netdev; | |
5384 | pi->port_id = 0; | |
5385 | ||
5386 | err = register_netdev(adap->port[0]); | |
5387 | if (err) { | |
5388 | pr_info("Unable to register VF mgmt netdev %s\n", name); | |
5389 | free_netdev(adap->port[0]); | |
5390 | adap->port[0] = NULL; | |
e7b48a32 | 5391 | return err; |
baf50868 GG |
5392 | } |
5393 | /* Allocate and set up VF Information. */ | |
5394 | adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev), | |
5395 | sizeof(struct vf_info), GFP_KERNEL); | |
5396 | if (!adap->vfinfo) { | |
5397 | unregister_netdev(adap->port[0]); | |
5398 | free_netdev(adap->port[0]); | |
5399 | adap->port[0] = NULL; | |
5400 | return -ENOMEM; | |
5401 | } | |
5402 | cxgb4_mgmt_fill_vf_station_mac_addr(adap); | |
5403 | } | |
5404 | /* Instantiate the requested number of VFs. */ | |
5405 | err = pci_enable_sriov(pdev, num_vfs); | |
5406 | if (err) { | |
5407 | pr_info("Unable to instantiate %d VFs\n", num_vfs); | |
5408 | if (!current_vfs) { | |
5409 | unregister_netdev(adap->port[0]); | |
5410 | free_netdev(adap->port[0]); | |
5411 | adap->port[0] = NULL; | |
5412 | kfree(adap->vfinfo); | |
5413 | adap->vfinfo = NULL; | |
5414 | } | |
5415 | return err; | |
b6244201 | 5416 | } |
661dbeb9 | 5417 | |
baf50868 | 5418 | adap->num_vfs = num_vfs; |
b6244201 HS |
5419 | return num_vfs; |
5420 | } | |
baf50868 | 5421 | #endif /* CONFIG_PCI_IOV */ |
b6244201 | 5422 | |
1dd06ae8 | 5423 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
b8ff05a9 | 5424 | { |
e8d45292 GG |
5425 | struct net_device *netdev; |
5426 | struct adapter *adapter; | |
5427 | static int adap_idx = 1; | |
5428 | int s_qpp, qpp, num_seg; | |
b8ff05a9 | 5429 | struct port_info *pi; |
c8f44aff | 5430 | bool highdma = false; |
d86bd29e | 5431 | enum chip_type chip; |
e8d45292 GG |
5432 | void __iomem *regs; |
5433 | int func, chip_ver; | |
5434 | u16 device_id; | |
5435 | int i, err; | |
5436 | u32 whoami; | |
b8ff05a9 DM |
5437 | |
5438 | printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); | |
5439 | ||
5440 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
5441 | if (err) { | |
5442 | /* Just info, some other driver may have claimed the device. */ | |
5443 | dev_info(&pdev->dev, "cannot obtain PCI resources\n"); | |
5444 | return err; | |
5445 | } | |
5446 | ||
b8ff05a9 DM |
5447 | err = pci_enable_device(pdev); |
5448 | if (err) { | |
5449 | dev_err(&pdev->dev, "cannot enable PCI device\n"); | |
5450 | goto out_release_regions; | |
5451 | } | |
5452 | ||
d6ce2628 HS |
5453 | regs = pci_ioremap_bar(pdev, 0); |
5454 | if (!regs) { | |
5455 | dev_err(&pdev->dev, "cannot map device registers\n"); | |
5456 | err = -ENOMEM; | |
5457 | goto out_disable_device; | |
5458 | } | |
5459 | ||
baf50868 GG |
5460 | adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); |
5461 | if (!adapter) { | |
5462 | err = -ENOMEM; | |
5463 | goto out_unmap_bar0; | |
5464 | } | |
5465 | ||
5466 | adapter->regs = regs; | |
8203b509 HS |
5467 | err = t4_wait_dev_ready(regs); |
5468 | if (err < 0) | |
e729452e | 5469 | goto out_free_adapter; |
8203b509 | 5470 | |
d6ce2628 | 5471 | /* We control everything through one PF */ |
e8d45292 GG |
5472 | whoami = t4_read_reg(adapter, PL_WHOAMI_A); |
5473 | pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); | |
5474 | chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id)); | |
5475 | if (chip < 0) { | |
5476 | dev_err(&pdev->dev, "Device %d is not supported\n", device_id); | |
5477 | err = chip; | |
5478 | goto out_free_adapter; | |
5479 | } | |
5480 | chip_ver = CHELSIO_CHIP_VERSION(chip); | |
5481 | func = chip_ver <= CHELSIO_T5 ? | |
5482 | SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); | |
baf50868 GG |
5483 | |
5484 | adapter->pdev = pdev; | |
5485 | adapter->pdev_dev = &pdev->dev; | |
5486 | adapter->name = pci_name(pdev); | |
5487 | adapter->mbox = func; | |
5488 | adapter->pf = func; | |
016764de GG |
5489 | adapter->params.chip = chip; |
5490 | adapter->adap_idx = adap_idx; | |
baf50868 GG |
5491 | adapter->msg_enable = DFLT_MSG_ENABLE; |
5492 | adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + | |
5493 | (sizeof(struct mbox_cmd) * | |
5494 | T4_OS_LOG_MBOX_CMDS), | |
5495 | GFP_KERNEL); | |
5496 | if (!adapter->mbox_log) { | |
5497 | err = -ENOMEM; | |
5498 | goto out_free_adapter; | |
5499 | } | |
5500 | spin_lock_init(&adapter->mbox_lock); | |
5501 | INIT_LIST_HEAD(&adapter->mlist.list); | |
aca06eaf | 5502 | adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; |
baf50868 GG |
5503 | pci_set_drvdata(pdev, adapter); |
5504 | ||
d6ce2628 | 5505 | if (func != ent->driver_data) { |
d6ce2628 HS |
5506 | pci_disable_device(pdev); |
5507 | pci_save_state(pdev); /* to restore SR-IOV later */ | |
baf50868 | 5508 | return 0; |
d6ce2628 HS |
5509 | } |
5510 | ||
b8ff05a9 | 5511 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
c8f44aff | 5512 | highdma = true; |
b8ff05a9 DM |
5513 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
5514 | if (err) { | |
5515 | dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " | |
5516 | "coherent allocations\n"); | |
baf50868 | 5517 | goto out_free_adapter; |
b8ff05a9 DM |
5518 | } |
5519 | } else { | |
5520 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
5521 | if (err) { | |
5522 | dev_err(&pdev->dev, "no usable DMA configuration\n"); | |
baf50868 | 5523 | goto out_free_adapter; |
b8ff05a9 DM |
5524 | } |
5525 | } | |
5526 | ||
5527 | pci_enable_pcie_error_reporting(pdev); | |
5528 | pci_set_master(pdev); | |
5529 | pci_save_state(pdev); | |
7829451c | 5530 | adap_idx++; |
29aaee65 AB |
5531 | adapter->workq = create_singlethread_workqueue("cxgb4"); |
5532 | if (!adapter->workq) { | |
5533 | err = -ENOMEM; | |
5534 | goto out_free_adapter; | |
5535 | } | |
5536 | ||
144be3d9 GS |
5537 | /* PCI device has been enabled */ |
5538 | adapter->flags |= DEV_ENABLED; | |
b8ff05a9 DM |
5539 | memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); |
5540 | ||
b0ba9d5f CL |
5541 | /* If possible, we use PCIe Relaxed Ordering Attribute to deliver |
5542 | * Ingress Packet Data to Free List Buffers in order to allow for | |
5543 | * chipset performance optimizations between the Root Complex and | |
5544 | * Memory Controllers. (Messages to the associated Ingress Queue | |
5545 | * notifying new Packet Placement in the Free Lists Buffers will be | |
5546 | * send without the Relaxed Ordering Attribute thus guaranteeing that | |
5547 | * all preceding PCIe Transaction Layer Packets will be processed | |
5548 | * first.) But some Root Complexes have various issues with Upstream | |
5549 | * Transaction Layer Packets with the Relaxed Ordering Attribute set. | |
5550 | * The PCIe devices which under the Root Complexes will be cleared the | |
5551 | * Relaxed Ordering bit in the configuration space, So we check our | |
5552 | * PCIe configuration space to see if it's flagged with advice against | |
5553 | * using Relaxed Ordering. | |
5554 | */ | |
5555 | if (!pcie_relaxed_ordering_enabled(pdev)) | |
5556 | adapter->flags |= ROOT_NO_RELAXED_ORDERING; | |
5557 | ||
b8ff05a9 DM |
5558 | spin_lock_init(&adapter->stats_lock); |
5559 | spin_lock_init(&adapter->tid_release_lock); | |
e327c225 | 5560 | spin_lock_init(&adapter->win0_lock); |
b8ff05a9 DM |
5561 | |
5562 | INIT_WORK(&adapter->tid_release_task, process_tid_release_list); | |
881806bc VP |
5563 | INIT_WORK(&adapter->db_full_task, process_db_full); |
5564 | INIT_WORK(&adapter->db_drop_task, process_db_drop); | |
8b7372c1 | 5565 | INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err); |
b8ff05a9 DM |
5566 | |
5567 | err = t4_prep_adapter(adapter); | |
5568 | if (err) | |
d6ce2628 HS |
5569 | goto out_free_adapter; |
5570 | ||
1dde532d RL |
5571 | if (is_kdump_kernel()) { |
5572 | /* Collect hardware state and append to /proc/vmcore */ | |
5573 | err = cxgb4_cudbg_vmcore_add_dump(adapter); | |
5574 | if (err) { | |
5575 | dev_warn(adapter->pdev_dev, | |
5576 | "Fail collecting vmcore device dump, err: %d. Continuing\n", | |
5577 | err); | |
5578 | err = 0; | |
5579 | } | |
5580 | } | |
22adfe0a | 5581 | |
d14807dd | 5582 | if (!is_t4(adapter->params.chip)) { |
f612b815 HS |
5583 | s_qpp = (QUEUESPERPAGEPF0_S + |
5584 | (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * | |
b2612722 | 5585 | adapter->pf); |
f612b815 HS |
5586 | qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, |
5587 | SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); | |
22adfe0a SR |
5588 | num_seg = PAGE_SIZE / SEGMENT_SIZE; |
5589 | ||
5590 | /* Each segment size is 128B. Write coalescing is enabled only | |
5591 | * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the | |
5592 | * queue is less no of segments that can be accommodated in | |
5593 | * a page size. | |
5594 | */ | |
5595 | if (qpp > num_seg) { | |
5596 | dev_err(&pdev->dev, | |
5597 | "Incorrect number of egress queues per page\n"); | |
5598 | err = -EINVAL; | |
d6ce2628 | 5599 | goto out_free_adapter; |
22adfe0a SR |
5600 | } |
5601 | adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), | |
5602 | pci_resource_len(pdev, 2)); | |
5603 | if (!adapter->bar2) { | |
5604 | dev_err(&pdev->dev, "cannot map device bar2 region\n"); | |
5605 | err = -ENOMEM; | |
d6ce2628 | 5606 | goto out_free_adapter; |
22adfe0a SR |
5607 | } |
5608 | } | |
5609 | ||
636f9d37 | 5610 | setup_memwin(adapter); |
b8ff05a9 | 5611 | err = adap_init0(adapter); |
5b377d11 HS |
5612 | #ifdef CONFIG_DEBUG_FS |
5613 | bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); | |
5614 | #endif | |
636f9d37 | 5615 | setup_memwin_rdma(adapter); |
b8ff05a9 DM |
5616 | if (err) |
5617 | goto out_unmap_bar; | |
5618 | ||
2a485cf7 HS |
5619 | /* configure SGE_STAT_CFG_A to read WC stats */ |
5620 | if (!is_t4(adapter->params.chip)) | |
676d6a75 HS |
5621 | t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | |
5622 | (is_t5(adapter->params.chip) ? STATMODE_V(0) : | |
5623 | T6_STATMODE_V(0))); | |
2a485cf7 | 5624 | |
b8ff05a9 | 5625 | for_each_port(adapter, i) { |
b8ff05a9 DM |
5626 | netdev = alloc_etherdev_mq(sizeof(struct port_info), |
5627 | MAX_ETH_QSETS); | |
5628 | if (!netdev) { | |
5629 | err = -ENOMEM; | |
5630 | goto out_free_dev; | |
5631 | } | |
5632 | ||
5633 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
5634 | ||
5635 | adapter->port[i] = netdev; | |
5636 | pi = netdev_priv(netdev); | |
5637 | pi->adapter = adapter; | |
5638 | pi->xact_addr_filt = -1; | |
b8ff05a9 | 5639 | pi->port_id = i; |
b8ff05a9 DM |
5640 | netdev->irq = pdev->irq; |
5641 | ||
2ed28baa MM |
5642 | netdev->hw_features = NETIF_F_SG | TSO_FLAGS | |
5643 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
5644 | NETIF_F_RXCSUM | NETIF_F_RXHASH | | |
d8931847 RL |
5645 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | |
5646 | NETIF_F_HW_TC; | |
d0a1299c | 5647 | |
e8d45292 | 5648 | if (chip_ver > CHELSIO_T5) { |
c50ae55e GG |
5649 | netdev->hw_enc_features |= NETIF_F_IP_CSUM | |
5650 | NETIF_F_IPV6_CSUM | | |
5651 | NETIF_F_RXCSUM | | |
5652 | NETIF_F_GSO_UDP_TUNNEL | | |
5653 | NETIF_F_TSO | NETIF_F_TSO6; | |
5654 | ||
d0a1299c | 5655 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL; |
c50ae55e | 5656 | } |
d0a1299c | 5657 | |
c8f44aff MM |
5658 | if (highdma) |
5659 | netdev->hw_features |= NETIF_F_HIGHDMA; | |
5660 | netdev->features |= netdev->hw_features; | |
b8ff05a9 DM |
5661 | netdev->vlan_features = netdev->features & VLAN_FEAT; |
5662 | ||
01789349 JP |
5663 | netdev->priv_flags |= IFF_UNICAST_FLT; |
5664 | ||
d894be57 | 5665 | /* MTU range: 81 - 9600 */ |
a047fbae | 5666 | netdev->min_mtu = 81; /* accommodate SACK */ |
d894be57 JW |
5667 | netdev->max_mtu = MAX_MTU; |
5668 | ||
b8ff05a9 | 5669 | netdev->netdev_ops = &cxgb4_netdev_ops; |
688848b1 AB |
5670 | #ifdef CONFIG_CHELSIO_T4_DCB |
5671 | netdev->dcbnl_ops = &cxgb4_dcb_ops; | |
5672 | cxgb4_dcb_state_init(netdev); | |
ebddd97a | 5673 | cxgb4_dcb_version_init(netdev); |
688848b1 | 5674 | #endif |
812034f1 | 5675 | cxgb4_set_ethtool_ops(netdev); |
b8ff05a9 DM |
5676 | } |
5677 | ||
ad75b7d3 RL |
5678 | cxgb4_init_ethtool_dump(adapter); |
5679 | ||
b8ff05a9 DM |
5680 | pci_set_drvdata(pdev, adapter); |
5681 | ||
5682 | if (adapter->flags & FW_OK) { | |
060e0c75 | 5683 | err = t4_port_init(adapter, func, func, 0); |
b8ff05a9 DM |
5684 | if (err) |
5685 | goto out_free_dev; | |
098ef6c2 HS |
5686 | } else if (adapter->params.nports == 1) { |
5687 | /* If we don't have a connection to the firmware -- possibly | |
5688 | * because of an error -- grab the raw VPD parameters so we | |
5689 | * can set the proper MAC Address on the debug network | |
5690 | * interface that we've created. | |
5691 | */ | |
5692 | u8 hw_addr[ETH_ALEN]; | |
5693 | u8 *na = adapter->params.vpd.na; | |
5694 | ||
5695 | err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); | |
5696 | if (!err) { | |
5697 | for (i = 0; i < ETH_ALEN; i++) | |
5698 | hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + | |
5699 | hex2val(na[2 * i + 1])); | |
5700 | t4_set_hw_addr(adapter, 0, hw_addr); | |
5701 | } | |
b8ff05a9 DM |
5702 | } |
5703 | ||
0eaec62a CL |
5704 | if (!(adapter->flags & FW_OK)) |
5705 | goto fw_attach_fail; | |
5706 | ||
098ef6c2 | 5707 | /* Configure queues and allocate tables now, they can be needed as |
b8ff05a9 DM |
5708 | * soon as the first register_netdev completes. |
5709 | */ | |
0eaec62a CL |
5710 | err = cfg_queues(adapter); |
5711 | if (err) | |
5712 | goto out_free_dev; | |
b8ff05a9 | 5713 | |
3bdb376e KS |
5714 | adapter->smt = t4_init_smt(); |
5715 | if (!adapter->smt) { | |
5716 | /* We tolerate a lack of SMT, giving up some functionality */ | |
5717 | dev_warn(&pdev->dev, "could not allocate SMT, continuing\n"); | |
5718 | } | |
5719 | ||
5be9ed8d | 5720 | adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); |
b8ff05a9 DM |
5721 | if (!adapter->l2t) { |
5722 | /* We tolerate a lack of L2T, giving up some functionality */ | |
5723 | dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); | |
5724 | adapter->params.offload = 0; | |
5725 | } | |
5726 | ||
778e1cdd KC |
5727 | adapter->mps_encap = kvcalloc(adapter->params.arch.mps_tcam_size, |
5728 | sizeof(struct mps_encap_entry), | |
0e249898 AV |
5729 | GFP_KERNEL); |
5730 | if (!adapter->mps_encap) | |
5731 | dev_warn(&pdev->dev, "could not allocate MPS Encap entries, continuing\n"); | |
5732 | ||
b5a02f50 | 5733 | #if IS_ENABLED(CONFIG_IPV6) |
e8d45292 | 5734 | if (chip_ver <= CHELSIO_T5 && |
eb72f74f HS |
5735 | (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { |
5736 | /* CLIP functionality is not present in hardware, | |
5737 | * hence disable all offload features | |
b5a02f50 AB |
5738 | */ |
5739 | dev_warn(&pdev->dev, | |
eb72f74f | 5740 | "CLIP not enabled in hardware, continuing\n"); |
b5a02f50 | 5741 | adapter->params.offload = 0; |
eb72f74f HS |
5742 | } else { |
5743 | adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, | |
5744 | adapter->clipt_end); | |
5745 | if (!adapter->clipt) { | |
5746 | /* We tolerate a lack of clip_table, giving up | |
5747 | * some functionality | |
5748 | */ | |
5749 | dev_warn(&pdev->dev, | |
5750 | "could not allocate Clip table, continuing\n"); | |
5751 | adapter->params.offload = 0; | |
5752 | } | |
b5a02f50 AB |
5753 | } |
5754 | #endif | |
b72a32da RL |
5755 | |
5756 | for_each_port(adapter, i) { | |
5757 | pi = adap2pinfo(adapter, i); | |
5758 | pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls); | |
5759 | if (!pi->sched_tbl) | |
5760 | dev_warn(&pdev->dev, | |
5761 | "could not activate scheduling on port %d\n", | |
5762 | i); | |
5763 | } | |
5764 | ||
578b46b9 | 5765 | if (tid_init(&adapter->tids) < 0) { |
b8ff05a9 DM |
5766 | dev_warn(&pdev->dev, "could not allocate TID table, " |
5767 | "continuing\n"); | |
5768 | adapter->params.offload = 0; | |
d8931847 | 5769 | } else { |
45da1ca2 | 5770 | adapter->tc_u32 = cxgb4_init_tc_u32(adapter); |
d8931847 RL |
5771 | if (!adapter->tc_u32) |
5772 | dev_warn(&pdev->dev, | |
5773 | "could not offload tc u32, continuing\n"); | |
62488e4b | 5774 | |
79e6d46a KS |
5775 | if (cxgb4_init_tc_flower(adapter)) |
5776 | dev_warn(&pdev->dev, | |
5777 | "could not offload tc flower, continuing\n"); | |
b8ff05a9 DM |
5778 | } |
5779 | ||
5c31254e | 5780 | if (is_offload(adapter) || is_hashfilter(adapter)) { |
9a1bb9f6 HS |
5781 | if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { |
5782 | u32 hash_base, hash_reg; | |
5783 | ||
dfecc759 | 5784 | if (chip_ver <= CHELSIO_T5) { |
9a1bb9f6 HS |
5785 | hash_reg = LE_DB_TID_HASHBASE_A; |
5786 | hash_base = t4_read_reg(adapter, hash_reg); | |
5787 | adapter->tids.hash_base = hash_base / 4; | |
5788 | } else { | |
5789 | hash_reg = T6_LE_DB_HASH_TID_BASE_A; | |
5790 | hash_base = t4_read_reg(adapter, hash_reg); | |
5791 | adapter->tids.hash_base = hash_base; | |
5792 | } | |
5793 | } | |
5794 | } | |
5795 | ||
f7cabcdd DM |
5796 | /* See what interrupts we'll be using */ |
5797 | if (msi > 1 && enable_msix(adapter) == 0) | |
5798 | adapter->flags |= USING_MSIX; | |
94cdb8bb | 5799 | else if (msi > 0 && pci_enable_msi(pdev) == 0) { |
f7cabcdd | 5800 | adapter->flags |= USING_MSI; |
94cdb8bb HS |
5801 | if (msi > 1) |
5802 | free_msix_info(adapter); | |
5803 | } | |
f7cabcdd | 5804 | |
547fd272 | 5805 | /* check for PCI Express bandwidth capabiltites */ |
57d12fc6 | 5806 | pcie_print_link_status(pdev); |
547fd272 | 5807 | |
671b0060 DM |
5808 | err = init_rss(adapter); |
5809 | if (err) | |
5810 | goto out_free_dev; | |
5811 | ||
843bd7db AV |
5812 | err = setup_fw_sge_queues(adapter); |
5813 | if (err) { | |
5814 | dev_err(adapter->pdev_dev, | |
5815 | "FW sge queue allocation failed, err %d", err); | |
5816 | goto out_free_dev; | |
5817 | } | |
5818 | ||
0eaec62a | 5819 | fw_attach_fail: |
b8ff05a9 DM |
5820 | /* |
5821 | * The card is now ready to go. If any errors occur during device | |
5822 | * registration we do not fail the whole card but rather proceed only | |
5823 | * with the ports we manage to register successfully. However we must | |
5824 | * register at least one net device. | |
5825 | */ | |
5826 | for_each_port(adapter, i) { | |
a57cabe0 | 5827 | pi = adap2pinfo(adapter, i); |
d2a007ab | 5828 | adapter->port[i]->dev_port = pi->lport; |
a57cabe0 DM |
5829 | netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); |
5830 | netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); | |
5831 | ||
b1a73af9 SM |
5832 | netif_carrier_off(adapter->port[i]); |
5833 | ||
b8ff05a9 DM |
5834 | err = register_netdev(adapter->port[i]); |
5835 | if (err) | |
b1a3c2b6 | 5836 | break; |
b1a3c2b6 DM |
5837 | adapter->chan_map[pi->tx_chan] = i; |
5838 | print_port_info(adapter->port[i]); | |
b8ff05a9 | 5839 | } |
b1a3c2b6 | 5840 | if (i == 0) { |
b8ff05a9 DM |
5841 | dev_err(&pdev->dev, "could not register any net devices\n"); |
5842 | goto out_free_dev; | |
5843 | } | |
b1a3c2b6 DM |
5844 | if (err) { |
5845 | dev_warn(&pdev->dev, "only %d net devices registered\n", i); | |
5846 | err = 0; | |
6403eab1 | 5847 | } |
b8ff05a9 DM |
5848 | |
5849 | if (cxgb4_debugfs_root) { | |
5850 | adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), | |
5851 | cxgb4_debugfs_root); | |
5852 | setup_debugfs(adapter); | |
5853 | } | |
5854 | ||
6482aa7c DLR |
5855 | /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ |
5856 | pdev->needs_freset = 1; | |
5857 | ||
0fbc81b3 HS |
5858 | if (is_uld(adapter)) { |
5859 | mutex_lock(&uld_mutex); | |
5860 | list_add_tail(&adapter->list_node, &adapter_list); | |
5861 | mutex_unlock(&uld_mutex); | |
5862 | } | |
b8ff05a9 | 5863 | |
9c33e420 AG |
5864 | if (!is_t4(adapter->params.chip)) |
5865 | cxgb4_ptp_init(adapter); | |
5866 | ||
b1871915 GG |
5867 | #ifdef CONFIG_THERMAL |
5868 | if (!is_t4(adapter->params.chip) && (adapter->flags & FW_OK)) | |
5869 | cxgb4_thermal_init(adapter); | |
5870 | #endif /* CONFIG_THERMAL */ | |
5871 | ||
0de72738 | 5872 | print_adapter_info(adapter); |
7829451c | 5873 | return 0; |
0de72738 | 5874 | |
b8ff05a9 | 5875 | out_free_dev: |
843bd7db | 5876 | t4_free_sge_resources(adapter); |
06546391 | 5877 | free_some_resources(adapter); |
94cdb8bb HS |
5878 | if (adapter->flags & USING_MSIX) |
5879 | free_msix_info(adapter); | |
0fbc81b3 HS |
5880 | if (adapter->num_uld || adapter->num_ofld_uld) |
5881 | t4_uld_mem_free(adapter); | |
b8ff05a9 | 5882 | out_unmap_bar: |
d14807dd | 5883 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5884 | iounmap(adapter->bar2); |
b8ff05a9 | 5885 | out_free_adapter: |
29aaee65 AB |
5886 | if (adapter->workq) |
5887 | destroy_workqueue(adapter->workq); | |
5888 | ||
7f080c3f | 5889 | kfree(adapter->mbox_log); |
b8ff05a9 | 5890 | kfree(adapter); |
d6ce2628 HS |
5891 | out_unmap_bar0: |
5892 | iounmap(regs); | |
b8ff05a9 DM |
5893 | out_disable_device: |
5894 | pci_disable_pcie_error_reporting(pdev); | |
5895 | pci_disable_device(pdev); | |
5896 | out_release_regions: | |
5897 | pci_release_regions(pdev); | |
b8ff05a9 DM |
5898 | return err; |
5899 | } | |
5900 | ||
91744948 | 5901 | static void remove_one(struct pci_dev *pdev) |
b8ff05a9 DM |
5902 | { |
5903 | struct adapter *adapter = pci_get_drvdata(pdev); | |
5904 | ||
7829451c HS |
5905 | if (!adapter) { |
5906 | pci_release_regions(pdev); | |
5907 | return; | |
5908 | } | |
636f9d37 | 5909 | |
e1f6198e GG |
5910 | adapter->flags |= SHUTTING_DOWN; |
5911 | ||
7829451c | 5912 | if (adapter->pf == 4) { |
b8ff05a9 DM |
5913 | int i; |
5914 | ||
29aaee65 AB |
5915 | /* Tear down per-adapter Work Queue first since it can contain |
5916 | * references to our adapter data structure. | |
5917 | */ | |
5918 | destroy_workqueue(adapter->workq); | |
5919 | ||
6a146f3a | 5920 | if (is_uld(adapter)) { |
b8ff05a9 | 5921 | detach_ulds(adapter); |
6a146f3a GP |
5922 | t4_uld_clean_up(adapter); |
5923 | } | |
b8ff05a9 | 5924 | |
8b4e6b3c AV |
5925 | adap_free_hma_mem(adapter); |
5926 | ||
b37987e8 HS |
5927 | disable_interrupts(adapter); |
5928 | ||
b8ff05a9 | 5929 | for_each_port(adapter, i) |
8f3a7676 | 5930 | if (adapter->port[i]->reg_state == NETREG_REGISTERED) |
b8ff05a9 DM |
5931 | unregister_netdev(adapter->port[i]); |
5932 | ||
9f16dc2e | 5933 | debugfs_remove_recursive(adapter->debugfs_root); |
b8ff05a9 | 5934 | |
9c33e420 AG |
5935 | if (!is_t4(adapter->params.chip)) |
5936 | cxgb4_ptp_stop(adapter); | |
b1871915 GG |
5937 | #ifdef CONFIG_THERMAL |
5938 | cxgb4_thermal_remove(adapter); | |
5939 | #endif | |
9c33e420 | 5940 | |
f2b7e78d VP |
5941 | /* If we allocated filters, free up state associated with any |
5942 | * valid filters ... | |
5943 | */ | |
578b46b9 | 5944 | clear_all_filters(adapter); |
f2b7e78d | 5945 | |
aaefae9b DM |
5946 | if (adapter->flags & FULL_INIT_DONE) |
5947 | cxgb_down(adapter); | |
b8ff05a9 | 5948 | |
94cdb8bb HS |
5949 | if (adapter->flags & USING_MSIX) |
5950 | free_msix_info(adapter); | |
0fbc81b3 HS |
5951 | if (adapter->num_uld || adapter->num_ofld_uld) |
5952 | t4_uld_mem_free(adapter); | |
06546391 | 5953 | free_some_resources(adapter); |
b5a02f50 AB |
5954 | #if IS_ENABLED(CONFIG_IPV6) |
5955 | t4_cleanup_clip_tbl(adapter); | |
5956 | #endif | |
d14807dd | 5957 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5958 | iounmap(adapter->bar2); |
7829451c HS |
5959 | } |
5960 | #ifdef CONFIG_PCI_IOV | |
5961 | else { | |
baf50868 | 5962 | cxgb4_iov_configure(adapter->pdev, 0); |
7829451c HS |
5963 | } |
5964 | #endif | |
c4e43e14 GG |
5965 | iounmap(adapter->regs); |
5966 | pci_disable_pcie_error_reporting(pdev); | |
5967 | if ((adapter->flags & DEV_ENABLED)) { | |
5968 | pci_disable_device(pdev); | |
5969 | adapter->flags &= ~DEV_ENABLED; | |
5970 | } | |
5971 | pci_release_regions(pdev); | |
5972 | kfree(adapter->mbox_log); | |
5973 | synchronize_rcu(); | |
5974 | kfree(adapter); | |
b8ff05a9 DM |
5975 | } |
5976 | ||
0fbc81b3 HS |
5977 | /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt |
5978 | * delivery. This is essentially a stripped down version of the PCI remove() | |
5979 | * function where we do the minimal amount of work necessary to shutdown any | |
5980 | * further activity. | |
5981 | */ | |
5982 | static void shutdown_one(struct pci_dev *pdev) | |
5983 | { | |
5984 | struct adapter *adapter = pci_get_drvdata(pdev); | |
5985 | ||
5986 | /* As with remove_one() above (see extended comment), we only want do | |
5987 | * do cleanup on PCI Devices which went all the way through init_one() | |
5988 | * ... | |
5989 | */ | |
5990 | if (!adapter) { | |
5991 | pci_release_regions(pdev); | |
5992 | return; | |
5993 | } | |
5994 | ||
e1f6198e GG |
5995 | adapter->flags |= SHUTTING_DOWN; |
5996 | ||
0fbc81b3 HS |
5997 | if (adapter->pf == 4) { |
5998 | int i; | |
5999 | ||
6000 | for_each_port(adapter, i) | |
6001 | if (adapter->port[i]->reg_state == NETREG_REGISTERED) | |
6002 | cxgb_close(adapter->port[i]); | |
6003 | ||
6a146f3a GP |
6004 | if (is_uld(adapter)) { |
6005 | detach_ulds(adapter); | |
6006 | t4_uld_clean_up(adapter); | |
6007 | } | |
6008 | ||
0fbc81b3 HS |
6009 | disable_interrupts(adapter); |
6010 | disable_msi(adapter); | |
6011 | ||
6012 | t4_sge_stop(adapter); | |
6013 | if (adapter->flags & FW_OK) | |
6014 | t4_fw_bye(adapter, adapter->mbox); | |
6015 | } | |
0fbc81b3 HS |
6016 | } |
6017 | ||
b8ff05a9 DM |
6018 | static struct pci_driver cxgb4_driver = { |
6019 | .name = KBUILD_MODNAME, | |
6020 | .id_table = cxgb4_pci_tbl, | |
6021 | .probe = init_one, | |
91744948 | 6022 | .remove = remove_one, |
0fbc81b3 | 6023 | .shutdown = shutdown_one, |
b6244201 HS |
6024 | #ifdef CONFIG_PCI_IOV |
6025 | .sriov_configure = cxgb4_iov_configure, | |
6026 | #endif | |
204dc3c0 | 6027 | .err_handler = &cxgb4_eeh, |
b8ff05a9 DM |
6028 | }; |
6029 | ||
6030 | static int __init cxgb4_init_module(void) | |
6031 | { | |
6032 | int ret; | |
6033 | ||
6034 | /* Debugfs support is optional, just warn if this fails */ | |
6035 | cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); | |
6036 | if (!cxgb4_debugfs_root) | |
428ac43f | 6037 | pr_warn("could not create debugfs entry, continuing\n"); |
b8ff05a9 DM |
6038 | |
6039 | ret = pci_register_driver(&cxgb4_driver); | |
29aaee65 | 6040 | if (ret < 0) |
b8ff05a9 | 6041 | debugfs_remove(cxgb4_debugfs_root); |
01bcca68 | 6042 | |
1bb60376 | 6043 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
6044 | if (!inet6addr_registered) { |
6045 | register_inet6addr_notifier(&cxgb4_inet6addr_notifier); | |
6046 | inet6addr_registered = true; | |
6047 | } | |
1bb60376 | 6048 | #endif |
01bcca68 | 6049 | |
b8ff05a9 DM |
6050 | return ret; |
6051 | } | |
6052 | ||
6053 | static void __exit cxgb4_cleanup_module(void) | |
6054 | { | |
1bb60376 | 6055 | #if IS_ENABLED(CONFIG_IPV6) |
1793c798 | 6056 | if (inet6addr_registered) { |
b5a02f50 AB |
6057 | unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); |
6058 | inet6addr_registered = false; | |
6059 | } | |
1bb60376 | 6060 | #endif |
b8ff05a9 DM |
6061 | pci_unregister_driver(&cxgb4_driver); |
6062 | debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ | |
6063 | } | |
6064 | ||
6065 | module_init(cxgb4_init_module); | |
6066 | module_exit(cxgb4_cleanup_module); |