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cxgb4: Add MPS TCAM refcounting for raw mac filters
[thirdparty/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
b72a32da 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
1ef8019b 64#include <net/bonding.h>
7c0f6ba6 65#include <linux/uaccess.h>
c5a8c0f3 66#include <linux/crash_dump.h>
846eac3f 67#include <net/udp_tunnel.h>
b8ff05a9
DM		 68
69#include "cxgb4.h"
d57fd6ca 70#include "cxgb4_filter.h"
b8ff05a9 71#include "t4_regs.h"
f612b815 72#include "t4_values.h"
b8ff05a9
DM		 73#include "t4_msg.h"
74#include "t4fw_api.h"
cd6c2f12 75#include "t4fw_version.h"
688848b1 76#include "cxgb4_dcb.h"
c68644ef 77#include "srq.h"
fd88b31a 78#include "cxgb4_debugfs.h"
b5a02f50 79#include "clip_tbl.h"
b8ff05a9 80#include "l2t.h"
3bdb376e 81#include "smt.h"
b72a32da 82#include "sched.h"
d8931847 83#include "cxgb4_tc_u32.h"
6a345b3d 84#include "cxgb4_tc_flower.h"
a4569504 85#include "cxgb4_ptp.h"
ad75b7d3 86#include "cxgb4_cudbg.h"
b8ff05a9 87
812034f1
HS		 88char cxgb4_driver_name[] = KBUILD_MODNAME;
89
01bcca68
VP		 90#ifdef DRV_VERSION
91#undef DRV_VERSION
92#endif
3a7f8554 93#define DRV_VERSION "2.0.0-ko"
812034f1 94const char cxgb4_driver_version[] = DRV_VERSION;
52a5f846 95#define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
b8ff05a9 96
b8ff05a9
DM		 97#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
98 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
99 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
100
3fedeab1
HS		 101/* Macros needed to support the PCI Device ID Table ...
102 */
103#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
768ffc66 104 static const struct pci_device_id cxgb4_pci_tbl[] = {
baf50868
GG		 105#define CXGB4_UNIFIED_PF 0x4
106
107#define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
b8ff05a9 108
3fedeab1
HS		 109/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
110 * called for both.
111 */
112#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
113
114#define CH_PCI_ID_TABLE_ENTRY(devid) \
baf50868 115 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
3fedeab1
HS		 116
117#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
118 { 0, } \
119 }
120
121#include "t4_pci_id_tbl.h"
b8ff05a9 122
16e47624 123#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 124#define FW5_FNAME "cxgb4/t5fw.bin"
3ccc6cf7 125#define FW6_FNAME "cxgb4/t6fw.bin"
16e47624 126#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 127#define FW5_CFNAME "cxgb4/t5-config.txt"
3ccc6cf7 128#define FW6_CFNAME "cxgb4/t6-config.txt"
01b69614
HS		 129#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
130#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
131#define PHY_AQ1202_DEVICEID 0x4409
132#define PHY_BCM84834_DEVICEID 0x4486
b8ff05a9
DM		 133
134MODULE_DESCRIPTION(DRV_DESC);
135MODULE_AUTHOR("Chelsio Communications");
136MODULE_LICENSE("Dual BSD/GPL");
137MODULE_VERSION(DRV_VERSION);
138MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 139MODULE_FIRMWARE(FW4_FNAME);
0a57a536 140MODULE_FIRMWARE(FW5_FNAME);
52a5f846 141MODULE_FIRMWARE(FW6_FNAME);
b8ff05a9 142
b8ff05a9
DM		 143/*
144 * The driver uses the best interrupt scheme available on a platform in the
145 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
146 * of these schemes the driver may consider as follows:
147 *
148 * msi = 2: choose from among all three options
149 * msi = 1: only consider MSI and INTx interrupts
150 * msi = 0: force INTx interrupts
151 */
152static int msi = 2;
153
154module_param(msi, int, 0644);
155MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
156
636f9d37
VP		 157/*
158 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
159 * offset by 2 bytes in order to have the IP headers line up on 4-byte
160 * boundaries. This is a requirement for many architectures which will throw
161 * a machine check fault if an attempt is made to access one of the 4-byte IP
162 * header fields on a non-4-byte boundary. And it's a major performance issue
163 * even on some architectures which allow it like some implementations of the
164 * x86 ISA. However, some architectures don't mind this and for some very
165 * edge-case performance sensitive applications (like forwarding large volumes
166 * of small packets), setting this DMA offset to 0 will decrease the number of
167 * PCI-E Bus transfers enough to measurably affect performance.
168 */
169static int rx_dma_offset = 2;
170
688848b1
AB		 171/* TX Queue select used to determine what algorithm to use for selecting TX
172 * queue. Select between the kernel provided function (select_queue=0) or user
173 * cxgb_select_queue function (select_queue=1)
174 *
175 * Default: select_queue=0
176 */
177static int select_queue;
178module_param(select_queue, int, 0644);
179MODULE_PARM_DESC(select_queue,
180 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
181
b8ff05a9
DM		 182static struct dentry *cxgb4_debugfs_root;
183
94cdb8bb
HS		 184LIST_HEAD(adapter_list);
185DEFINE_MUTEX(uld_mutex);
b8ff05a9
DM		 186
187static void link_report(struct net_device *dev)
188{
189 if (!netif_carrier_ok(dev))
190 netdev_info(dev, "link down\n");
191 else {
192 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
193
85412255 194 const char *s;
b8ff05a9
DM		 195 const struct port_info *p = netdev_priv(dev);
196
197 switch (p->link_cfg.speed) {
5e78f7fd
GG		 198 case 100:
199 s = "100Mbps";
b8ff05a9 200 break;
e8b39015 201 case 1000:
5e78f7fd 202 s = "1Gbps";
b8ff05a9 203 break;
5e78f7fd
GG		 204 case 10000:
205 s = "10Gbps";
206 break;
207 case 25000:
208 s = "25Gbps";
b8ff05a9 209 break;
e8b39015 210 case 40000:
72aca4bf
KS		 211 s = "40Gbps";
212 break;
7cbe543c
GG		 213 case 50000:
214 s = "50Gbps";
215 break;
5e78f7fd
GG		 216 case 100000:
217 s = "100Gbps";
218 break;
85412255
HS		 219 default:
220 pr_info("%s: unsupported speed: %d\n",
221 dev->name, p->link_cfg.speed);
222 return;
b8ff05a9
DM		 223 }
224
225 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
226 fc[p->link_cfg.fc]);
227 }
228}
229
688848b1
AB		 230#ifdef CONFIG_CHELSIO_T4_DCB
231/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
232static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
233{
234 struct port_info *pi = netdev_priv(dev);
235 struct adapter *adap = pi->adapter;
236 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
237 int i;
238
239 /* We use a simple mapping of Port TX Queue Index to DCB
240 * Priority when we're enabling DCB.
241 */
242 for (i = 0; i < pi->nqsets; i++, txq++) {
243 u32 name, value;
244 int err;
245
5167865a
HS		 246 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
247 FW_PARAMS_PARAM_X_V(
248 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
249 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
688848b1
AB		 250 value = enable ? i : 0xffffffff;
251
252 /* Since we can be called while atomic (from "interrupt
253 * level") we need to issue the Set Parameters Commannd
254 * without sleeping (timeout < 0).
255 */
b2612722 256 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
01b69614
HS		 257 &name, &value,
258 -FW_CMD_MAX_TIMEOUT);
688848b1
AB		 259
260 if (err)
261 dev_err(adap->pdev_dev,
262 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
263 enable ? "set" : "unset", pi->port_id, i, -err);
10b00466 264 else
5ce36338 265 txq->dcb_prio = enable ? value : 0;
688848b1
AB		 266 }
267}
688848b1 268
ebddd97a 269int cxgb4_dcb_enabled(const struct net_device *dev)
218d48e7 270{
218d48e7
HS		 271 struct port_info *pi = netdev_priv(dev);
272
273 if (!pi->dcb.enabled)
274 return 0;
275
276 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
277 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
218d48e7 278}
7c70c4f8 279#endif /* CONFIG_CHELSIO_T4_DCB */
218d48e7 280
b8ff05a9
DM		 281void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
282{
283 struct net_device *dev = adapter->port[port_id];
284
285 /* Skip changes from disabled ports. */
286 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
287 if (link_stat)
288 netif_carrier_on(dev);
688848b1
AB		 289 else {
290#ifdef CONFIG_CHELSIO_T4_DCB
218d48e7 291 if (cxgb4_dcb_enabled(dev)) {
ba581f77 292 cxgb4_dcb_reset(dev);
218d48e7
HS		 293 dcb_tx_queue_prio_enable(dev, false);
294 }
688848b1 295#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 296 netif_carrier_off(dev);
688848b1 297 }
b8ff05a9
DM		 298
299 link_report(dev);
300 }
301}
302
8156b0ba 303void t4_os_portmod_changed(struct adapter *adap, int port_id)
b8ff05a9
DM		 304{
305 static const char *mod_str[] = {
a0881cab 306 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 307 };
308
8156b0ba
GG		 309 struct net_device *dev = adap->port[port_id];
310 struct port_info *pi = netdev_priv(dev);
b8ff05a9
DM		 311
312 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
313 netdev_info(dev, "port module unplugged\n");
a0881cab 314 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9 315 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
be81a2de
HS		 316 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
317 netdev_info(dev, "%s: unsupported port module inserted\n",
318 dev->name);
319 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
320 netdev_info(dev, "%s: unknown port module inserted\n",
321 dev->name);
322 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
323 netdev_info(dev, "%s: transceiver module error\n", dev->name);
324 else
325 netdev_info(dev, "%s: unknown module type %d inserted\n",
326 dev->name, pi->mod_type);
8156b0ba
GG		 327
328 /* If the interface is running, then we'll need any "sticky" Link
329 * Parameters redone with a new Transceiver Module.
330 */
331 pi->link_cfg.redo_l1cfg = netif_running(dev);
b8ff05a9
DM		 332}
333
fc08a01a
HS		 334int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
335module_param(dbfifo_int_thresh, int, 0644);
336MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
337
b8ff05a9 338/*
fc08a01a 339 * usecs to sleep while draining the dbfifo
b8ff05a9 340 */
fc08a01a
HS		 341static int dbfifo_drain_delay = 1000;
342module_param(dbfifo_drain_delay, int, 0644);
343MODULE_PARM_DESC(dbfifo_drain_delay,
344 "usecs to sleep while draining the dbfifo");
345
346static inline int cxgb4_set_addr_hash(struct port_info *pi)
b8ff05a9 347{
fc08a01a
HS		 348 struct adapter *adap = pi->adapter;
349 u64 vec = 0;
350 bool ucast = false;
351 struct hash_mac_addr *entry;
352
353 /* Calculate the hash vector for the updated list and program it */
354 list_for_each_entry(entry, &adap->mac_hlist, list) {
355 ucast |= is_unicast_ether_addr(entry->addr);
356 vec |= (1ULL << hash_mac_addr(entry->addr));
357 }
358 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
359 vec, false);
360}
361
362static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
363{
364 struct port_info *pi = netdev_priv(netdev);
365 struct adapter *adap = pi->adapter;
366 int ret;
b8ff05a9
DM		 367 u64 mhash = 0;
368 u64 uhash = 0;
fc08a01a
HS		 369 bool free = false;
370 bool ucast = is_unicast_ether_addr(mac_addr);
371 const u8 *maclist[1] = {mac_addr};
372 struct hash_mac_addr *new_entry;
373
374 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
375 NULL, ucast ? &uhash : &mhash, false);
376 if (ret < 0)
377 goto out;
378 /* if hash != 0, then add the addr to hash addr list
379 * so on the end we will calculate the hash for the
380 * list and program it
381 */
382 if (uhash || mhash) {
383 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
384 if (!new_entry)
385 return -ENOMEM;
386 ether_addr_copy(new_entry->addr, mac_addr);
387 list_add_tail(&new_entry->list, &adap->mac_hlist);
388 ret = cxgb4_set_addr_hash(pi);
b8ff05a9 389 }
fc08a01a
HS		 390out:
391 return ret < 0 ? ret : 0;
392}
b8ff05a9 393
fc08a01a
HS		 394static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
395{
396 struct port_info *pi = netdev_priv(netdev);
397 struct adapter *adap = pi->adapter;
398 int ret;
399 const u8 *maclist[1] = {mac_addr};
400 struct hash_mac_addr *entry, *tmp;
b8ff05a9 401
fc08a01a
HS		 402 /* If the MAC address to be removed is in the hash addr
403 * list, delete it from the list and update hash vector
404 */
405 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
406 if (ether_addr_equal(entry->addr, mac_addr)) {
407 list_del(&entry->list);
408 kfree(entry);
409 return cxgb4_set_addr_hash(pi);
b8ff05a9
DM		 410 }
411 }
412
fc08a01a
HS		 413 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
414 return ret < 0 ? -EINVAL : 0;
b8ff05a9
DM		 415}
416
417/*
418 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
419 * If @mtu is -1 it is left unchanged.
420 */
421static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
422{
b8ff05a9 423 struct port_info *pi = netdev_priv(dev);
fc08a01a 424 struct adapter *adapter = pi->adapter;
b8ff05a9 425
d01f7abc
HS		 426 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
427 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
fc08a01a
HS		 428
429 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
430 (dev->flags & IFF_PROMISC) ? 1 : 0,
431 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
432 sleep_ok);
b8ff05a9
DM		 433}
434
435/**
3f8cfd0d
AV		 436 * cxgb4_change_mac - Update match filter for a MAC address.
437 * @pi: the port_info
438 * @viid: the VI id
439 * @tcam_idx: TCAM index of existing filter for old value of MAC address,
440 * or -1
441 * @addr: the new MAC address value
442 * @persist: whether a new MAC allocation should be persistent
443 * @add_smt: if true also add the address to the HW SMT
444 *
445 * Modifies an MPS filter and sets it to the new MAC address if
446 * @tcam_idx >= 0, or adds the MAC address to a new filter if
447 * @tcam_idx < 0. In the latter case the address is added persistently
448 * if @persist is %true.
449 * Addresses are programmed to hash region, if tcam runs out of entries.
450 *
451 */
452static int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
453 int *tcam_idx, const u8 *addr, bool persist,
454 u8 *smt_idx)
455{
456 struct adapter *adapter = pi->adapter;
457 struct hash_mac_addr *entry, *new_entry;
458 int ret;
459
460 ret = t4_change_mac(adapter, adapter->mbox, viid,
461 *tcam_idx, addr, persist, smt_idx);
462 /* We ran out of TCAM entries. try programming hash region. */
463 if (ret == -ENOMEM) {
464 /* If the MAC address to be updated is in the hash addr
465 * list, update it from the list
466 */
467 list_for_each_entry(entry, &adapter->mac_hlist, list) {
468 if (entry->iface_mac) {
469 ether_addr_copy(entry->addr, addr);
470 goto set_hash;
471 }
472 }
473 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
474 if (!new_entry)
475 return -ENOMEM;
476 ether_addr_copy(new_entry->addr, addr);
477 new_entry->iface_mac = true;
478 list_add_tail(&new_entry->list, &adapter->mac_hlist);
479set_hash:
480 ret = cxgb4_set_addr_hash(pi);
481 } else if (ret >= 0) {
482 *tcam_idx = ret;
483 ret = 0;
484 }
485
486 return ret;
487}
488
489/*
b8ff05a9
DM		 490 * link_start - enable a port
491 * @dev: the port to enable
492 *
493 * Performs the MAC and PHY actions needed to enable a port.
494 */
495static int link_start(struct net_device *dev)
496{
497 int ret;
498 struct port_info *pi = netdev_priv(dev);
b2612722 499 unsigned int mb = pi->adapter->pf;
b8ff05a9
DM		 500
501 /*
502 * We do not set address filters and promiscuity here, the stack does
503 * that step explicitly.
504 */
060e0c75 505 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 506 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
3f8cfd0d
AV		 507 if (ret == 0)
508 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
509 dev->dev_addr, true, &pi->smt_idx);
b8ff05a9 510 if (ret == 0)
4036da90 511 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
060e0c75 512 &pi->link_cfg);
30f00847
AB		 513 if (ret == 0) {
514 local_bh_disable();
e2f4f4e9 515 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
688848b1 516 true, CXGB4_DCB_ENABLED);
30f00847
AB		 517 local_bh_enable();
518 }
688848b1 519
b8ff05a9
DM		 520 return ret;
521}
522
688848b1
AB		 523#ifdef CONFIG_CHELSIO_T4_DCB
524/* Handle a Data Center Bridging update message from the firmware. */
525static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
526{
2b5fb1f2 527 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
134491fd 528 struct net_device *dev = adap->port[adap->chan_map[port]];
688848b1
AB		 529 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
530 int new_dcb_enabled;
531
532 cxgb4_dcb_handle_fw_update(adap, pcmd);
533 new_dcb_enabled = cxgb4_dcb_enabled(dev);
534
535 /* If the DCB has become enabled or disabled on the port then we're
536 * going to need to set up/tear down DCB Priority parameters for the
537 * TX Queues associated with the port.
538 */
539 if (new_dcb_enabled != old_dcb_enabled)
540 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
541}
542#endif /* CONFIG_CHELSIO_T4_DCB */
543
f2b7e78d 544/* Response queue handler for the FW event queue.
b8ff05a9
DM		 545 */
546static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
547 const struct pkt_gl *gl)
548{
549 u8 opcode = ((const struct rss_header *)rsp)->opcode;
550
551 rsp++; /* skip RSS header */
b407a4a9
VP		 552
553 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
554 */
555 if (unlikely(opcode == CPL_FW4_MSG &&
556 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
557 rsp++;
558 opcode = ((const struct rss_header *)rsp)->opcode;
559 rsp++;
560 if (opcode != CPL_SGE_EGR_UPDATE) {
561 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
562 , opcode);
563 goto out;
564 }
565 }
566
b8ff05a9
DM		 567 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
568 const struct cpl_sge_egr_update *p = (void *)rsp;
bdc590b9 569 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
e46dab4d 570 struct sge_txq *txq;
b8ff05a9 571
e46dab4d 572 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 573 txq->restarts++;
ab677ff4 574 if (txq->q_type == CXGB4_TXQ_ETH) {
b8ff05a9
DM		 575 struct sge_eth_txq *eq;
576
577 eq = container_of(txq, struct sge_eth_txq, q);
d429005f 578 t4_sge_eth_txq_egress_update(q->adap, eq, -1);
b8ff05a9 579 } else {
ab677ff4 580 struct sge_uld_txq *oq;
b8ff05a9 581
ab677ff4 582 oq = container_of(txq, struct sge_uld_txq, q);
b8ff05a9
DM		 583 tasklet_schedule(&oq->qresume_tsk);
584 }
585 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
586 const struct cpl_fw6_msg *p = (void *)rsp;
587
688848b1
AB		 588#ifdef CONFIG_CHELSIO_T4_DCB
589 const struct fw_port_cmd *pcmd = (const void *)p->data;
e2ac9628 590 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
688848b1 591 unsigned int action =
2b5fb1f2 592 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
688848b1
AB		 593
594 if (cmd == FW_PORT_CMD &&
c3168cab
GG		 595 (action == FW_PORT_ACTION_GET_PORT_INFO ||
596 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
2b5fb1f2 597 int port = FW_PORT_CMD_PORTID_G(
688848b1 598 be32_to_cpu(pcmd->op_to_portid));
c3168cab
GG		 599 struct net_device *dev;
600 int dcbxdis, state_input;
601
602 dev = q->adap->port[q->adap->chan_map[port]];
603 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
90d4c5bb
GG		 604 ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
605 : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
606 & FW_PORT_CMD_DCBXDIS32_F));
c3168cab
GG		 607 state_input = (dcbxdis
608 ? CXGB4_DCB_INPUT_FW_DISABLED
609 : CXGB4_DCB_INPUT_FW_ENABLED);
688848b1
AB		 610
611 cxgb4_dcb_state_fsm(dev, state_input);
612 }
613
614 if (cmd == FW_PORT_CMD &&
615 action == FW_PORT_ACTION_L2_DCB_CFG)
616 dcb_rpl(q->adap, pcmd);
617 else
618#endif
619 if (p->type == 0)
620 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 621 } else if (opcode == CPL_L2T_WRITE_RPL) {
622 const struct cpl_l2t_write_rpl *p = (void *)rsp;
623
624 do_l2t_write_rpl(q->adap, p);
3bdb376e
KS		 625 } else if (opcode == CPL_SMT_WRITE_RPL) {
626 const struct cpl_smt_write_rpl *p = (void *)rsp;
627
628 do_smt_write_rpl(q->adap, p);
f2b7e78d
VP		 629 } else if (opcode == CPL_SET_TCB_RPL) {
630 const struct cpl_set_tcb_rpl *p = (void *)rsp;
631
632 filter_rpl(q->adap, p);
12b276fb
KS		 633 } else if (opcode == CPL_ACT_OPEN_RPL) {
634 const struct cpl_act_open_rpl *p = (void *)rsp;
635
636 hash_filter_rpl(q->adap, p);
3b0b3bee
KS		 637 } else if (opcode == CPL_ABORT_RPL_RSS) {
638 const struct cpl_abort_rpl_rss *p = (void *)rsp;
639
640 hash_del_filter_rpl(q->adap, p);
c68644ef
RR		 641 } else if (opcode == CPL_SRQ_TABLE_RPL) {
642 const struct cpl_srq_table_rpl *p = (void *)rsp;
643
644 do_srq_table_rpl(q->adap, p);
b8ff05a9
DM		 645 } else
646 dev_err(q->adap->pdev_dev,
647 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 648out:
b8ff05a9
DM		 649 return 0;
650}
651
b8ff05a9
DM		 652static void disable_msi(struct adapter *adapter)
653{
80f61f19 654 if (adapter->flags & CXGB4_USING_MSIX) {
b8ff05a9 655 pci_disable_msix(adapter->pdev);
80f61f19
AV		 656 adapter->flags &= ~CXGB4_USING_MSIX;
657 } else if (adapter->flags & CXGB4_USING_MSI) {
b8ff05a9 658 pci_disable_msi(adapter->pdev);
80f61f19 659 adapter->flags &= ~CXGB4_USING_MSI;
b8ff05a9
DM		 660 }
661}
662
663/*
664 * Interrupt handler for non-data events used with MSI-X.
665 */
666static irqreturn_t t4_nondata_intr(int irq, void *cookie)
667{
668 struct adapter *adap = cookie;
0d804338 669 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
b8ff05a9 670
0d804338 671 if (v & PFSW_F) {
b8ff05a9 672 adap->swintr = 1;
0d804338 673 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
b8ff05a9 674 }
80f61f19 675 if (adap->flags & CXGB4_MASTER_PF)
c3c7b121 676 t4_slow_intr_handler(adap);
b8ff05a9
DM		 677 return IRQ_HANDLED;
678}
679
680/*
681 * Name the MSI-X interrupts.
682 */
683static void name_msix_vecs(struct adapter *adap)
684{
ba27816c 685 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 686
687 /* non-data interrupts */
b1a3c2b6 688 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 689
690 /* FW events */
b1a3c2b6
DM		 691 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
692 adap->port[0]->name);
b8ff05a9
DM		 693
694 /* Ethernet queues */
695 for_each_port(adap, j) {
696 struct net_device *d = adap->port[j];
697 const struct port_info *pi = netdev_priv(d);
698
ba27816c 699 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 700 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
701 d->name, i);
b8ff05a9 702 }
b8ff05a9
DM		 703}
704
c9765074
NK		 705int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
706 cpumask_var_t *aff_mask, int idx)
707{
708 int rv;
709
710 if (!zalloc_cpumask_var(aff_mask, GFP_KERNEL)) {
711 dev_err(adap->pdev_dev, "alloc_cpumask_var failed\n");
712 return -ENOMEM;
713 }
714
715 cpumask_set_cpu(cpumask_local_spread(idx, dev_to_node(adap->pdev_dev)),
716 *aff_mask);
717
718 rv = irq_set_affinity_hint(vec, *aff_mask);
719 if (rv)
720 dev_warn(adap->pdev_dev,
721 "irq_set_affinity_hint %u failed %d\n",
722 vec, rv);
723
724 return 0;
725}
726
727void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask)
728{
729 irq_set_affinity_hint(vec, NULL);
730 free_cpumask_var(aff_mask);
731}
732
b8ff05a9
DM		 733static int request_msix_queue_irqs(struct adapter *adap)
734{
735 struct sge *s = &adap->sge;
c9765074 736 struct msix_info *minfo;
0fbc81b3 737 int err, ethqidx;
cf38be6d 738 int msi_index = 2;
b8ff05a9
DM		 739
740 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
741 adap->msix_info[1].desc, &s->fw_evtq);
742 if (err)
743 return err;
744
745 for_each_ethrxq(s, ethqidx) {
c9765074
NK		 746 minfo = &adap->msix_info[msi_index];
747 err = request_irq(minfo->vec,
404d9e3f 748 t4_sge_intr_msix, 0,
c9765074 749 minfo->desc,
b8ff05a9
DM		 750 &s->ethrxq[ethqidx].rspq);
751 if (err)
752 goto unwind;
c9765074
NK		 753
754 cxgb4_set_msix_aff(adap, minfo->vec,
755 &minfo->aff_mask, ethqidx);
404d9e3f 756 msi_index++;
b8ff05a9 757 }
b8ff05a9
DM		 758 return 0;
759
760unwind:
c9765074
NK		 761 while (--ethqidx >= 0) {
762 msi_index--;
763 minfo = &adap->msix_info[msi_index];
764 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
765 free_irq(minfo->vec, &s->ethrxq[ethqidx].rspq);
766 }
b8ff05a9
DM		 767 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
768 return err;
769}
770
771static void free_msix_queue_irqs(struct adapter *adap)
772{
b8ff05a9 773 struct sge *s = &adap->sge;
c9765074
NK		 774 struct msix_info *minfo;
775 int i, msi_index = 2;
b8ff05a9
DM		 776
777 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
c9765074
NK		 778 for_each_ethrxq(s, i) {
779 minfo = &adap->msix_info[msi_index++];
780 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask);
781 free_irq(minfo->vec, &s->ethrxq[i].rspq);
782 }
b8ff05a9
DM		 783}
784
a248384e
VP		 785static int setup_ppod_edram(struct adapter *adap)
786{
787 unsigned int param, val;
788 int ret;
789
790 /* Driver sends FW_PARAMS_PARAM_DEV_PPOD_EDRAM read command to check
791 * if firmware supports ppod edram feature or not. If firmware
792 * returns 1, then driver can enable this feature by sending
793 * FW_PARAMS_PARAM_DEV_PPOD_EDRAM write command with value 1 to
794 * enable ppod edram feature.
795 */
796 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
797 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PPOD_EDRAM));
798
799 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
800 if (ret < 0) {
801 dev_warn(adap->pdev_dev,
802 "querying PPOD_EDRAM support failed: %d\n",
803 ret);
804 return -1;
805 }
806
807 if (val != 1)
808 return -1;
809
810 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
811 if (ret < 0) {
812 dev_err(adap->pdev_dev,
813 "setting PPOD_EDRAM failed: %d\n", ret);
814 return -1;
815 }
816 return 0;
817}
818
671b0060 819/**
812034f1 820 * cxgb4_write_rss - write the RSS table for a given port
671b0060
DM		 821 * @pi: the port
822 * @queues: array of queue indices for RSS
823 *
824 * Sets up the portion of the HW RSS table for the port's VI to distribute
825 * packets to the Rx queues in @queues.
c035e183 826 * Should never be called before setting up sge eth rx queues
671b0060 827 */
812034f1 828int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
671b0060
DM		 829{
830 u16 *rss;
831 int i, err;
c035e183
HS		 832 struct adapter *adapter = pi->adapter;
833 const struct sge_eth_rxq *rxq;
671b0060 834
c035e183 835 rxq = &adapter->sge.ethrxq[pi->first_qset];
6da2ec56 836 rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
671b0060
DM		 837 if (!rss)
838 return -ENOMEM;
839
840 /* map the queue indices to queue ids */
841 for (i = 0; i < pi->rss_size; i++, queues++)
c035e183 842 rss[i] = rxq[*queues].rspq.abs_id;
671b0060 843
b2612722 844 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
060e0c75 845 pi->rss_size, rss, pi->rss_size);
c035e183
HS		 846 /* If Tunnel All Lookup isn't specified in the global RSS
847 * Configuration, then we need to specify a default Ingress
848 * Queue for any ingress packets which aren't hashed. We'll
849 * use our first ingress queue ...
850 */
851 if (!err)
852 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
853 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
854 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
855 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
856 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
857 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
858 rss[0]);
671b0060
DM		 859 kfree(rss);
860 return err;
861}
862
b8ff05a9
DM		 863/**
864 * setup_rss - configure RSS
865 * @adap: the adapter
866 *
671b0060 867 * Sets up RSS for each port.
b8ff05a9
DM		 868 */
869static int setup_rss(struct adapter *adap)
870{
c035e183 871 int i, j, err;
b8ff05a9
DM		 872
873 for_each_port(adap, i) {
874 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 875
c035e183
HS		 876 /* Fill default values with equal distribution */
877 for (j = 0; j < pi->rss_size; j++)
878 pi->rss[j] = j % pi->nqsets;
879
812034f1 880 err = cxgb4_write_rss(pi, pi->rss);
b8ff05a9
DM		 881 if (err)
882 return err;
883 }
884 return 0;
885}
886
e46dab4d
DM		 887/*
888 * Return the channel of the ingress queue with the given qid.
889 */
890static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
891{
892 qid -= p->ingr_start;
893 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
894}
895
b8ff05a9
DM		 896/*
897 * Wait until all NAPI handlers are descheduled.
898 */
899static void quiesce_rx(struct adapter *adap)
900{
901 int i;
902
4b8e27a8 903 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 904 struct sge_rspq *q = adap->sge.ingr_map[i];
905
5226b791 906 if (q && q->handler)
b8ff05a9
DM		 907 napi_disable(&q->napi);
908 }
909}
910
b37987e8
HS		 911/* Disable interrupt and napi handler */
912static void disable_interrupts(struct adapter *adap)
913{
80f61f19 914 if (adap->flags & CXGB4_FULL_INIT_DONE) {
b37987e8 915 t4_intr_disable(adap);
80f61f19 916 if (adap->flags & CXGB4_USING_MSIX) {
b37987e8
HS		 917 free_msix_queue_irqs(adap);
918 free_irq(adap->msix_info[0].vec, adap);
919 } else {
920 free_irq(adap->pdev->irq, adap);
921 }
922 quiesce_rx(adap);
923 }
924}
925
b8ff05a9
DM		 926/*
927 * Enable NAPI scheduling and interrupt generation for all Rx queues.
928 */
929static void enable_rx(struct adapter *adap)
930{
931 int i;
932
4b8e27a8 933 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 934 struct sge_rspq *q = adap->sge.ingr_map[i];
935
936 if (!q)
937 continue;
5226b791 938 if (q->handler)
b8ff05a9 939 napi_enable(&q->napi);
5226b791 940
b8ff05a9 941 /* 0-increment GTS to start the timer and enable interrupts */
f612b815
HS		 942 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
943 SEINTARM_V(q->intr_params) |
944 INGRESSQID_V(q->cntxt_id));
b8ff05a9
DM		 945 }
946}
947
1c6a5b0e 948
0fbc81b3 949static int setup_fw_sge_queues(struct adapter *adap)
b8ff05a9 950{
b8ff05a9 951 struct sge *s = &adap->sge;
0fbc81b3 952 int err = 0;
b8ff05a9 953
4b8e27a8
HS		 954 bitmap_zero(s->starving_fl, s->egr_sz);
955 bitmap_zero(s->txq_maperr, s->egr_sz);
b8ff05a9 956
80f61f19 957 if (adap->flags & CXGB4_USING_MSIX)
94cdb8bb 958 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */
b8ff05a9
DM		 959 else {
960 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
2337ba42 961 NULL, NULL, NULL, -1);
b8ff05a9
DM		 962 if (err)
963 return err;
94cdb8bb 964 adap->msi_idx = -((int)s->intrq.abs_id + 1);
b8ff05a9
DM		 965 }
966
967 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
94cdb8bb 968 adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
0fbc81b3
HS		 969 return err;
970}
971
972/**
973 * setup_sge_queues - configure SGE Tx/Rx/response queues
974 * @adap: the adapter
975 *
976 * Determines how many sets of SGE queues to use and initializes them.
977 * We support multiple queue sets per port if we have MSI-X, otherwise
978 * just one queue set per port.
979 */
980static int setup_sge_queues(struct adapter *adap)
981{
982 int err, i, j;
983 struct sge *s = &adap->sge;
d427caee 984 struct sge_uld_rxq_info *rxq_info = NULL;
0fbc81b3 985 unsigned int cmplqid = 0;
b8ff05a9 986
d427caee
GG		 987 if (is_uld(adap))
988 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
989
b8ff05a9
DM		 990 for_each_port(adap, i) {
991 struct net_device *dev = adap->port[i];
992 struct port_info *pi = netdev_priv(dev);
993 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
994 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
995
996 for (j = 0; j < pi->nqsets; j++, q++) {
94cdb8bb
HS		 997 if (adap->msi_idx > 0)
998 adap->msi_idx++;
b8ff05a9 999 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
94cdb8bb 1000 adap->msi_idx, &q->fl,
145ef8a5 1001 t4_ethrx_handler,
2337ba42 1002 NULL,
193c4c28
AV		 1003 t4_get_tp_ch_map(adap,
1004 pi->tx_chan));
b8ff05a9
DM		 1005 if (err)
1006 goto freeout;
1007 q->rspq.idx = j;
1008 memset(&q->stats, 0, sizeof(q->stats));
1009 }
d429005f
VK		 1010
1011 q = &s->ethrxq[pi->first_qset];
1012 for (j = 0; j < pi->nqsets; j++, t++, q++) {
b8ff05a9
DM		 1013 err = t4_sge_alloc_eth_txq(adap, t, dev,
1014 netdev_get_tx_queue(dev, j),
d429005f 1015 q->rspq.cntxt_id,
80f61f19 1016 !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
b8ff05a9
DM		 1017 if (err)
1018 goto freeout;
1019 }
1020 }
1021
b8ff05a9 1022 for_each_port(adap, i) {
0fbc81b3 1023 /* Note that cmplqid below is 0 if we don't
b8ff05a9
DM		 1024 * have RDMA queues, and that's the right value.
1025 */
0fbc81b3
HS		 1026 if (rxq_info)
1027 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
1028
b8ff05a9 1029 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
0fbc81b3 1030 s->fw_evtq.cntxt_id, cmplqid);
b8ff05a9
DM		 1031 if (err)
1032 goto freeout;
1033 }
1034
a4569504
AG		 1035 if (!is_t4(adap->params.chip)) {
1036 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
1037 netdev_get_tx_queue(adap->port[0], 0)
d429005f 1038 , s->fw_evtq.cntxt_id, false);
a4569504
AG		 1039 if (err)
1040 goto freeout;
1041 }
1042
9bb59b96 1043 t4_write_reg(adap, is_t4(adap->params.chip) ?
837e4a42
HS		 1044 MPS_TRC_RSS_CONTROL_A :
1045 MPS_T5_TRC_RSS_CONTROL_A,
1046 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1047 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
b8ff05a9 1048 return 0;
0fbc81b3 1049freeout:
0eaec62a 1050 dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
0fbc81b3
HS		 1051 t4_free_sge_resources(adap);
1052 return err;
b8ff05a9
DM		 1053}
1054
688848b1 1055static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
a350ecce 1056 struct net_device *sb_dev)
688848b1
AB		 1057{
1058 int txq;
1059
1060#ifdef CONFIG_CHELSIO_T4_DCB
1061 /* If a Data Center Bridging has been successfully negotiated on this
1062 * link then we'll use the skb's priority to map it to a TX Queue.
1063 * The skb's priority is determined via the VLAN Tag Priority Code
1064 * Point field.
1065 */
85eacf3f 1066 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
688848b1
AB		 1067 u16 vlan_tci;
1068 int err;
1069
1070 err = vlan_get_tag(skb, &vlan_tci);
1071 if (unlikely(err)) {
1072 if (net_ratelimit())
1073 netdev_warn(dev,
1074 "TX Packet without VLAN Tag on DCB Link\n");
1075 txq = 0;
1076 } else {
1077 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
84a200b3
VP		 1078#ifdef CONFIG_CHELSIO_T4_FCOE
1079 if (skb->protocol == htons(ETH_P_FCOE))
1080 txq = skb->priority & 0x7;
1081#endif /* CONFIG_CHELSIO_T4_FCOE */
688848b1
AB		 1082 }
1083 return txq;
1084 }
1085#endif /* CONFIG_CHELSIO_T4_DCB */
1086
1087 if (select_queue) {
1088 txq = (skb_rx_queue_recorded(skb)
1089 ? skb_get_rx_queue(skb)
1090 : smp_processor_id());
1091
1092 while (unlikely(txq >= dev->real_num_tx_queues))
1093 txq -= dev->real_num_tx_queues;
1094
1095 return txq;
1096 }
1097
a350ecce 1098 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
688848b1
AB		 1099}
1100
b8ff05a9
DM		 1101static int closest_timer(const struct sge *s, int time)
1102{
1103 int i, delta, match = 0, min_delta = INT_MAX;
1104
1105 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1106 delta = time - s->timer_val[i];
1107 if (delta < 0)
1108 delta = -delta;
1109 if (delta < min_delta) {
1110 min_delta = delta;
1111 match = i;
1112 }
1113 }
1114 return match;
1115}
1116
1117static int closest_thres(const struct sge *s, int thres)
1118{
1119 int i, delta, match = 0, min_delta = INT_MAX;
1120
1121 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1122 delta = thres - s->counter_val[i];
1123 if (delta < 0)
1124 delta = -delta;
1125 if (delta < min_delta) {
1126 min_delta = delta;
1127 match = i;
1128 }
1129 }
1130 return match;
1131}
1132
b8ff05a9 1133/**
812034f1 1134 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 1135 * @q: the Rx queue
1136 * @us: the hold-off time in us, or 0 to disable timer
1137 * @cnt: the hold-off packet count, or 0 to disable counter
1138 *
1139 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1140 * one of the two needs to be enabled for the queue to generate interrupts.
1141 */
812034f1
HS		 1142int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1143 unsigned int us, unsigned int cnt)
b8ff05a9 1144{
c887ad0e
HS		 1145 struct adapter *adap = q->adap;
1146
b8ff05a9
DM		 1147 if ((us | cnt) == 0)
1148 cnt = 1;
1149
1150 if (cnt) {
1151 int err;
1152 u32 v, new_idx;
1153
1154 new_idx = closest_thres(&adap->sge, cnt);
1155 if (q->desc && q->pktcnt_idx != new_idx) {
1156 /* the queue has already been created, update it */
5167865a
HS		 1157 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1158 FW_PARAMS_PARAM_X_V(
1159 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1160 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
b2612722
HS		 1161 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1162 &v, &new_idx);
b8ff05a9
DM		 1163 if (err)
1164 return err;
1165 }
1166 q->pktcnt_idx = new_idx;
1167 }
1168
1169 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1ecc7b7a 1170 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
b8ff05a9
DM		 1171 return 0;
1172}
1173
c8f44aff 1174static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 1175{
2ed28baa 1176 const struct port_info *pi = netdev_priv(dev);
c8f44aff 1177 netdev_features_t changed = dev->features ^ features;
19ecae2c 1178 int err;
19ecae2c 1179
f646968f 1180 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 1181 return 0;
19ecae2c 1182
b2612722 1183 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
2ed28baa 1184 -1, -1, -1,
f646968f 1185 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 1186 if (unlikely(err))
f646968f 1187 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 1188 return err;
87b6cf51
DM		 1189}
1190
91744948 1191static int setup_debugfs(struct adapter *adap)
b8ff05a9 1192{
b8ff05a9
DM		 1193 if (IS_ERR_OR_NULL(adap->debugfs_root))
1194 return -1;
1195
fd88b31a
HS		 1196#ifdef CONFIG_DEBUG_FS
1197 t4_setup_debugfs(adap);
1198#endif
b8ff05a9
DM		 1199 return 0;
1200}
1201
1202/*
1203 * upper-layer driver support
1204 */
1205
1206/*
1207 * Allocate an active-open TID and set it to the supplied value.
1208 */
1209int cxgb4_alloc_atid(struct tid_info *t, void *data)
1210{
1211 int atid = -1;
1212
1213 spin_lock_bh(&t->atid_lock);
1214 if (t->afree) {
1215 union aopen_entry *p = t->afree;
1216
f2b7e78d 1217 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 1218 t->afree = p->next;
1219 p->data = data;
1220 t->atids_in_use++;
1221 }
1222 spin_unlock_bh(&t->atid_lock);
1223 return atid;
1224}
1225EXPORT_SYMBOL(cxgb4_alloc_atid);
1226
1227/*
1228 * Release an active-open TID.
1229 */
1230void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1231{
f2b7e78d 1232 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 1233
1234 spin_lock_bh(&t->atid_lock);
1235 p->next = t->afree;
1236 t->afree = p;
1237 t->atids_in_use--;
1238 spin_unlock_bh(&t->atid_lock);
1239}
1240EXPORT_SYMBOL(cxgb4_free_atid);
1241
1242/*
1243 * Allocate a server TID and set it to the supplied value.
1244 */
1245int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1246{
1247 int stid;
1248
1249 spin_lock_bh(&t->stid_lock);
1250 if (family == PF_INET) {
1251 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1252 if (stid < t->nstids)
1253 __set_bit(stid, t->stid_bmap);
1254 else
1255 stid = -1;
1256 } else {
a99c683e 1257 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
b8ff05a9
DM		 1258 if (stid < 0)
1259 stid = -1;
1260 }
1261 if (stid >= 0) {
1262 t->stid_tab[stid].data = data;
1263 stid += t->stid_base;
15f63b74
KS		 1264 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1265 * This is equivalent to 4 TIDs. With CLIP enabled it
1266 * needs 2 TIDs.
1267 */
1dec4cec 1268 if (family == PF_INET6) {
a99c683e 1269 t->stids_in_use += 2;
1dec4cec
GG		 1270 t->v6_stids_in_use += 2;
1271 } else {
1272 t->stids_in_use++;
1273 }
b8ff05a9
DM		 1274 }
1275 spin_unlock_bh(&t->stid_lock);
1276 return stid;
1277}
1278EXPORT_SYMBOL(cxgb4_alloc_stid);
1279
dca4faeb
VP		 1280/* Allocate a server filter TID and set it to the supplied value.
1281 */
1282int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1283{
1284 int stid;
1285
1286 spin_lock_bh(&t->stid_lock);
1287 if (family == PF_INET) {
1288 stid = find_next_zero_bit(t->stid_bmap,
1289 t->nstids + t->nsftids, t->nstids);
1290 if (stid < (t->nstids + t->nsftids))
1291 __set_bit(stid, t->stid_bmap);
1292 else
1293 stid = -1;
1294 } else {
1295 stid = -1;
1296 }
1297 if (stid >= 0) {
1298 t->stid_tab[stid].data = data;
470c60c4
KS		 1299 stid -= t->nstids;
1300 stid += t->sftid_base;
2248b293 1301 t->sftids_in_use++;
dca4faeb
VP		 1302 }
1303 spin_unlock_bh(&t->stid_lock);
1304 return stid;
1305}
1306EXPORT_SYMBOL(cxgb4_alloc_sftid);
1307
1308/* Release a server TID.
b8ff05a9
DM		 1309 */
1310void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1311{
470c60c4
KS		 1312 /* Is it a server filter TID? */
1313 if (t->nsftids && (stid >= t->sftid_base)) {
1314 stid -= t->sftid_base;
1315 stid += t->nstids;
1316 } else {
1317 stid -= t->stid_base;
1318 }
1319
b8ff05a9
DM		 1320 spin_lock_bh(&t->stid_lock);
1321 if (family == PF_INET)
1322 __clear_bit(stid, t->stid_bmap);
1323 else
a99c683e 1324 bitmap_release_region(t->stid_bmap, stid, 1);
b8ff05a9 1325 t->stid_tab[stid].data = NULL;
2248b293 1326 if (stid < t->nstids) {
1dec4cec 1327 if (family == PF_INET6) {
a99c683e 1328 t->stids_in_use -= 2;
1dec4cec
GG		 1329 t->v6_stids_in_use -= 2;
1330 } else {
1331 t->stids_in_use--;
1332 }
2248b293
HS		 1333 } else {
1334 t->sftids_in_use--;
1335 }
1dec4cec 1336
b8ff05a9
DM		 1337 spin_unlock_bh(&t->stid_lock);
1338}
1339EXPORT_SYMBOL(cxgb4_free_stid);
1340
1341/*
1342 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1343 */
1344static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1345 unsigned int tid)
1346{
1347 struct cpl_tid_release *req;
1348
1349 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
4df864c1 1350 req = __skb_put(skb, sizeof(*req));
b8ff05a9
DM		 1351 INIT_TP_WR(req, tid);
1352 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1353}
1354
1355/*
1356 * Queue a TID release request and if necessary schedule a work queue to
1357 * process it.
1358 */
31b9c19b 1359static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1360 unsigned int tid)
b8ff05a9
DM		 1361{
1362 void **p = &t->tid_tab[tid];
1363 struct adapter *adap = container_of(t, struct adapter, tids);
1364
1365 spin_lock_bh(&adap->tid_release_lock);
1366 *p = adap->tid_release_head;
1367 /* Low 2 bits encode the Tx channel number */
1368 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1369 if (!adap->tid_release_task_busy) {
1370 adap->tid_release_task_busy = true;
29aaee65 1371 queue_work(adap->workq, &adap->tid_release_task);
b8ff05a9
DM		 1372 }
1373 spin_unlock_bh(&adap->tid_release_lock);
1374}
b8ff05a9
DM		 1375
1376/*
1377 * Process the list of pending TID release requests.
1378 */
1379static void process_tid_release_list(struct work_struct *work)
1380{
1381 struct sk_buff *skb;
1382 struct adapter *adap;
1383
1384 adap = container_of(work, struct adapter, tid_release_task);
1385
1386 spin_lock_bh(&adap->tid_release_lock);
1387 while (adap->tid_release_head) {
1388 void **p = adap->tid_release_head;
1389 unsigned int chan = (uintptr_t)p & 3;
1390 p = (void *)p - chan;
1391
1392 adap->tid_release_head = *p;
1393 *p = NULL;
1394 spin_unlock_bh(&adap->tid_release_lock);
1395
1396 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1397 GFP_KERNEL)))
1398 schedule_timeout_uninterruptible(1);
1399
1400 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1401 t4_ofld_send(adap, skb);
1402 spin_lock_bh(&adap->tid_release_lock);
1403 }
1404 adap->tid_release_task_busy = false;
1405 spin_unlock_bh(&adap->tid_release_lock);
1406}
1407
1408/*
1409 * Release a TID and inform HW. If we are unable to allocate the release
1410 * message we defer to a work queue.
1411 */
1dec4cec
GG		 1412void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1413 unsigned short family)
b8ff05a9 1414{
b8ff05a9
DM		 1415 struct sk_buff *skb;
1416 struct adapter *adap = container_of(t, struct adapter, tids);
1417
9a1bb9f6
HS		 1418 WARN_ON(tid >= t->ntids);
1419
1420 if (t->tid_tab[tid]) {
1421 t->tid_tab[tid] = NULL;
1dec4cec
GG		 1422 atomic_dec(&t->conns_in_use);
1423 if (t->hash_base && (tid >= t->hash_base)) {
1424 if (family == AF_INET6)
1425 atomic_sub(2, &t->hash_tids_in_use);
1426 else
1427 atomic_dec(&t->hash_tids_in_use);
1428 } else {
1429 if (family == AF_INET6)
1430 atomic_sub(2, &t->tids_in_use);
1431 else
1432 atomic_dec(&t->tids_in_use);
1433 }
9a1bb9f6
HS		 1434 }
1435
b8ff05a9
DM		 1436 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1437 if (likely(skb)) {
b8ff05a9
DM		 1438 mk_tid_release(skb, chan, tid);
1439 t4_ofld_send(adap, skb);
1440 } else
1441 cxgb4_queue_tid_release(t, chan, tid);
b8ff05a9
DM		 1442}
1443EXPORT_SYMBOL(cxgb4_remove_tid);
1444
1445/*
1446 * Allocate and initialize the TID tables. Returns 0 on success.
1447 */
1448static int tid_init(struct tid_info *t)
1449{
b6f8eaec 1450 struct adapter *adap = container_of(t, struct adapter, tids);
578b46b9
RL		 1451 unsigned int max_ftids = t->nftids + t->nsftids;
1452 unsigned int natids = t->natids;
1453 unsigned int stid_bmap_size;
1454 unsigned int ftid_bmap_size;
1455 size_t size;
b8ff05a9 1456
dca4faeb 1457 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
578b46b9 1458 ftid_bmap_size = BITS_TO_LONGS(t->nftids);
f2b7e78d
VP		 1459 size = t->ntids * sizeof(*t->tid_tab) +
1460 natids * sizeof(*t->atid_tab) +
b8ff05a9 1461 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 1462 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 1463 stid_bmap_size * sizeof(long) +
578b46b9
RL		 1464 max_ftids * sizeof(*t->ftid_tab) +
1465 ftid_bmap_size * sizeof(long);
f2b7e78d 1466
752ade68 1467 t->tid_tab = kvzalloc(size, GFP_KERNEL);
b8ff05a9
DM		 1468 if (!t->tid_tab)
1469 return -ENOMEM;
1470
1471 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1472 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 1473 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 1474 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
578b46b9 1475 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
b8ff05a9
DM		 1476 spin_lock_init(&t->stid_lock);
1477 spin_lock_init(&t->atid_lock);
578b46b9 1478 spin_lock_init(&t->ftid_lock);
b8ff05a9
DM		 1479
1480 t->stids_in_use = 0;
1dec4cec 1481 t->v6_stids_in_use = 0;
2248b293 1482 t->sftids_in_use = 0;
b8ff05a9
DM		 1483 t->afree = NULL;
1484 t->atids_in_use = 0;
1485 atomic_set(&t->tids_in_use, 0);
1dec4cec 1486 atomic_set(&t->conns_in_use, 0);
9a1bb9f6 1487 atomic_set(&t->hash_tids_in_use, 0);
b8ff05a9
DM		 1488
1489 /* Setup the free list for atid_tab and clear the stid bitmap. */
1490 if (natids) {
1491 while (--natids)
1492 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1493 t->afree = t->atid_tab;
1494 }
b6f8eaec 1495
578b46b9
RL		 1496 if (is_offload(adap)) {
1497 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1498 /* Reserve stid 0 for T4/T5 adapters */
1499 if (!t->stid_base &&
1500 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1501 __set_bit(0, t->stid_bmap);
1502 }
1503
1504 bitmap_zero(t->ftid_bmap, t->nftids);
b8ff05a9
DM		 1505 return 0;
1506}
1507
1508/**
1509 * cxgb4_create_server - create an IP server
1510 * @dev: the device
1511 * @stid: the server TID
1512 * @sip: local IP address to bind server to
1513 * @sport: the server's TCP port
1514 * @queue: queue to direct messages from this server to
1515 *
1516 * Create an IP server for the given port and address.
1517 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1518 */
1519int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 1520 __be32 sip, __be16 sport, __be16 vlan,
1521 unsigned int queue)
b8ff05a9
DM		 1522{
1523 unsigned int chan;
1524 struct sk_buff *skb;
1525 struct adapter *adap;
1526 struct cpl_pass_open_req *req;
80f40c1f 1527 int ret;
b8ff05a9
DM		 1528
1529 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1530 if (!skb)
1531 return -ENOMEM;
1532
1533 adap = netdev2adap(dev);
4df864c1 1534 req = __skb_put(skb, sizeof(*req));
b8ff05a9
DM		 1535 INIT_TP_WR(req, 0);
1536 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1537 req->local_port = sport;
1538 req->peer_port = htons(0);
1539 req->local_ip = sip;
1540 req->peer_ip = htonl(0);
e46dab4d 1541 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1542 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1543 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1544 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1545 ret = t4_mgmt_tx(adap, skb);
1546 return net_xmit_eval(ret);
b8ff05a9
DM		 1547}
1548EXPORT_SYMBOL(cxgb4_create_server);
1549
80f40c1f
VP		 1550/* cxgb4_create_server6 - create an IPv6 server
1551 * @dev: the device
1552 * @stid: the server TID
1553 * @sip: local IPv6 address to bind server to
1554 * @sport: the server's TCP port
1555 * @queue: queue to direct messages from this server to
1556 *
1557 * Create an IPv6 server for the given port and address.
1558 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1559 */
1560int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1561 const struct in6_addr *sip, __be16 sport,
1562 unsigned int queue)
1563{
1564 unsigned int chan;
1565 struct sk_buff *skb;
1566 struct adapter *adap;
1567 struct cpl_pass_open_req6 *req;
1568 int ret;
1569
1570 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1571 if (!skb)
1572 return -ENOMEM;
1573
1574 adap = netdev2adap(dev);
4df864c1 1575 req = __skb_put(skb, sizeof(*req));
80f40c1f
VP		 1576 INIT_TP_WR(req, 0);
1577 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1578 req->local_port = sport;
1579 req->peer_port = htons(0);
1580 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1581 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1582 req->peer_ip_hi = cpu_to_be64(0);
1583 req->peer_ip_lo = cpu_to_be64(0);
1584 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1585 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1586 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1587 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1588 ret = t4_mgmt_tx(adap, skb);
1589 return net_xmit_eval(ret);
1590}
1591EXPORT_SYMBOL(cxgb4_create_server6);
1592
1593int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1594 unsigned int queue, bool ipv6)
1595{
1596 struct sk_buff *skb;
1597 struct adapter *adap;
1598 struct cpl_close_listsvr_req *req;
1599 int ret;
1600
1601 adap = netdev2adap(dev);
1602
1603 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1604 if (!skb)
1605 return -ENOMEM;
1606
4df864c1 1607 req = __skb_put(skb, sizeof(*req));
80f40c1f
VP		 1608 INIT_TP_WR(req, 0);
1609 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
bdc590b9
HS		 1610 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1611 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
80f40c1f
VP		 1612 ret = t4_mgmt_tx(adap, skb);
1613 return net_xmit_eval(ret);
1614}
1615EXPORT_SYMBOL(cxgb4_remove_server);
1616
b8ff05a9
DM		 1617/**
1618 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1619 * @mtus: the HW MTU table
1620 * @mtu: the target MTU
1621 * @idx: index of selected entry in the MTU table
1622 *
1623 * Returns the index and the value in the HW MTU table that is closest to
1624 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1625 * table, in which case that smallest available value is selected.
1626 */
1627unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1628 unsigned int *idx)
1629{
1630 unsigned int i = 0;
1631
1632 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1633 ++i;
1634 if (idx)
1635 *idx = i;
1636 return mtus[i];
1637}
1638EXPORT_SYMBOL(cxgb4_best_mtu);
1639
92e7ae71
HS		 1640/**
1641 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1642 * @mtus: the HW MTU table
1643 * @header_size: Header Size
1644 * @data_size_max: maximum Data Segment Size
1645 * @data_size_align: desired Data Segment Size Alignment (2^N)
1646 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1647 *
1648 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1649 * MTU Table based solely on a Maximum MTU parameter, we break that
1650 * parameter up into a Header Size and Maximum Data Segment Size, and
1651 * provide a desired Data Segment Size Alignment. If we find an MTU in
1652 * the Hardware MTU Table which will result in a Data Segment Size with
1653 * the requested alignment _and_ that MTU isn't "too far" from the
1654 * closest MTU, then we'll return that rather than the closest MTU.
1655 */
1656unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1657 unsigned short header_size,
1658 unsigned short data_size_max,
1659 unsigned short data_size_align,
1660 unsigned int *mtu_idxp)
1661{
1662 unsigned short max_mtu = header_size + data_size_max;
1663 unsigned short data_size_align_mask = data_size_align - 1;
1664 int mtu_idx, aligned_mtu_idx;
1665
1666 /* Scan the MTU Table till we find an MTU which is larger than our
1667 * Maximum MTU or we reach the end of the table. Along the way,
1668 * record the last MTU found, if any, which will result in a Data
1669 * Segment Length matching the requested alignment.
1670 */
1671 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1672 unsigned short data_size = mtus[mtu_idx] - header_size;
1673
1674 /* If this MTU minus the Header Size would result in a
1675 * Data Segment Size of the desired alignment, remember it.
1676 */
1677 if ((data_size & data_size_align_mask) == 0)
1678 aligned_mtu_idx = mtu_idx;
1679
1680 /* If we're not at the end of the Hardware MTU Table and the
1681 * next element is larger than our Maximum MTU, drop out of
1682 * the loop.
1683 */
1684 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1685 break;
1686 }
1687
1688 /* If we fell out of the loop because we ran to the end of the table,
1689 * then we just have to use the last [largest] entry.
1690 */
1691 if (mtu_idx == NMTUS)
1692 mtu_idx--;
1693
1694 /* If we found an MTU which resulted in the requested Data Segment
1695 * Length alignment and that's "not far" from the largest MTU which is
1696 * less than or equal to the maximum MTU, then use that.
1697 */
1698 if (aligned_mtu_idx >= 0 &&
1699 mtu_idx - aligned_mtu_idx <= 1)
1700 mtu_idx = aligned_mtu_idx;
1701
1702 /* If the caller has passed in an MTU Index pointer, pass the
1703 * MTU Index back. Return the MTU value.
1704 */
1705 if (mtu_idxp)
1706 *mtu_idxp = mtu_idx;
1707 return mtus[mtu_idx];
1708}
1709EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1710
b8ff05a9
DM		 1711/**
1712 * cxgb4_port_chan - get the HW channel of a port
1713 * @dev: the net device for the port
1714 *
1715 * Return the HW Tx channel of the given port.
1716 */
1717unsigned int cxgb4_port_chan(const struct net_device *dev)
1718{
1719 return netdev2pinfo(dev)->tx_chan;
1720}
1721EXPORT_SYMBOL(cxgb4_port_chan);
1722
74dd5aa1
VK		 1723/**
1724 * cxgb4_port_e2cchan - get the HW c-channel of a port
1725 * @dev: the net device for the port
1726 *
1727 * Return the HW RX c-channel of the given port.
1728 */
1729unsigned int cxgb4_port_e2cchan(const struct net_device *dev)
1730{
1731 return netdev2pinfo(dev)->rx_cchan;
1732}
1733EXPORT_SYMBOL(cxgb4_port_e2cchan);
1734
881806bc
VP		 1735unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1736{
1737 struct adapter *adap = netdev2adap(dev);
2cc301d2 1738 u32 v1, v2, lp_count, hp_count;
881806bc 1739
f061de42
HS		 1740 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1741 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1742 if (is_t4(adap->params.chip)) {
f061de42
HS		 1743 lp_count = LP_COUNT_G(v1);
1744 hp_count = HP_COUNT_G(v1);
2cc301d2 1745 } else {
f061de42
HS		 1746 lp_count = LP_COUNT_T5_G(v1);
1747 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1748 }
1749 return lpfifo ? lp_count : hp_count;
881806bc
VP		 1750}
1751EXPORT_SYMBOL(cxgb4_dbfifo_count);
1752
b8ff05a9
DM		 1753/**
1754 * cxgb4_port_viid - get the VI id of a port
1755 * @dev: the net device for the port
1756 *
1757 * Return the VI id of the given port.
1758 */
1759unsigned int cxgb4_port_viid(const struct net_device *dev)
1760{
1761 return netdev2pinfo(dev)->viid;
1762}
1763EXPORT_SYMBOL(cxgb4_port_viid);
1764
1765/**
1766 * cxgb4_port_idx - get the index of a port
1767 * @dev: the net device for the port
1768 *
1769 * Return the index of the given port.
1770 */
1771unsigned int cxgb4_port_idx(const struct net_device *dev)
1772{
1773 return netdev2pinfo(dev)->port_id;
1774}
1775EXPORT_SYMBOL(cxgb4_port_idx);
1776
b8ff05a9
DM		 1777void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1778 struct tp_tcp_stats *v6)
1779{
1780 struct adapter *adap = pci_get_drvdata(pdev);
1781
1782 spin_lock(&adap->stats_lock);
5ccf9d04 1783 t4_tp_get_tcp_stats(adap, v4, v6, false);
b8ff05a9
DM		 1784 spin_unlock(&adap->stats_lock);
1785}
1786EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1787
1788void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1789 const unsigned int *pgsz_order)
1790{
1791 struct adapter *adap = netdev2adap(dev);
1792
0d804338
HS		 1793 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1794 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1795 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1796 HPZ3_V(pgsz_order[3]));
b8ff05a9
DM		 1797}
1798EXPORT_SYMBOL(cxgb4_iscsi_init);
1799
3069ee9b
VP		 1800int cxgb4_flush_eq_cache(struct net_device *dev)
1801{
1802 struct adapter *adap = netdev2adap(dev);
3069ee9b 1803
736c3b94 1804 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
3069ee9b
VP		 1805}
1806EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1807
1808static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1809{
f061de42 1810 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
3069ee9b
VP		 1811 __be64 indices;
1812 int ret;
1813
fc5ab020
HS		 1814 spin_lock(&adap->win0_lock);
1815 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1816 sizeof(indices), (__be32 *)&indices,
1817 T4_MEMORY_READ);
1818 spin_unlock(&adap->win0_lock);
3069ee9b 1819 if (!ret) {
404d9e3f
VP		 1820 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1821 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 1822 }
1823 return ret;
1824}
1825
1826int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1827 u16 size)
1828{
1829 struct adapter *adap = netdev2adap(dev);
1830 u16 hw_pidx, hw_cidx;
1831 int ret;
1832
1833 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1834 if (ret)
1835 goto out;
1836
1837 if (pidx != hw_pidx) {
1838 u16 delta;
f612b815 1839 u32 val;
3069ee9b
VP		 1840
1841 if (pidx >= hw_pidx)
1842 delta = pidx - hw_pidx;
1843 else
1844 delta = size - hw_pidx + pidx;
f612b815
HS		 1845
1846 if (is_t4(adap->params.chip))
1847 val = PIDX_V(delta);
1848 else
1849 val = PIDX_T5_V(delta);
3069ee9b 1850 wmb();
f612b815
HS		 1851 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1852 QID_V(qid) | val);
3069ee9b
VP		 1853 }
1854out:
1855 return ret;
1856}
1857EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1858
031cf476
HS		 1859int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1860{
6559a7e8 1861 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
031cf476 1862 u32 edc0_end, edc1_end, mc0_end, mc1_end;
8b4e6b3c
AV		 1863 u32 offset, memtype, memaddr;
1864 struct adapter *adap;
1865 u32 hma_size = 0;
031cf476
HS		 1866 int ret;
1867
1868 adap = netdev2adap(dev);
1869
1870 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1871
1872 /* Figure out where the offset lands in the Memory Type/Address scheme.
1873 * This code assumes that the memory is laid out starting at offset 0
1874 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1875 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
1876 * MC0, and some have both MC0 and MC1.
1877 */
6559a7e8
HS		 1878 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1879 edc0_size = EDRAM0_SIZE_G(size) << 20;
1880 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1881 edc1_size = EDRAM1_SIZE_G(size) << 20;
1882 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1883 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
031cf476 1884
8b4e6b3c
AV		 1885 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1886 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1887 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1888 }
031cf476
HS		 1889 edc0_end = edc0_size;
1890 edc1_end = edc0_end + edc1_size;
1891 mc0_end = edc1_end + mc0_size;
1892
1893 if (offset < edc0_end) {
1894 memtype = MEM_EDC0;
1895 memaddr = offset;
1896 } else if (offset < edc1_end) {
1897 memtype = MEM_EDC1;
1898 memaddr = offset - edc0_end;
1899 } else {
8b4e6b3c
AV		 1900 if (hma_size && (offset < (edc1_end + hma_size))) {
1901 memtype = MEM_HMA;
1902 memaddr = offset - edc1_end;
1903 } else if (offset < mc0_end) {
031cf476
HS		 1904 memtype = MEM_MC0;
1905 memaddr = offset - edc1_end;
3ccc6cf7 1906 } else if (is_t5(adap->params.chip)) {
6559a7e8
HS		 1907 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1908 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
031cf476
HS		 1909 mc1_end = mc0_end + mc1_size;
1910 if (offset < mc1_end) {
1911 memtype = MEM_MC1;
1912 memaddr = offset - mc0_end;
1913 } else {
1914 /* offset beyond the end of any memory */
1915 goto err;
1916 }
3ccc6cf7
HS		 1917 } else {
1918 /* T4/T6 only has a single memory channel */
1919 goto err;
031cf476
HS		 1920 }
1921 }
1922
1923 spin_lock(&adap->win0_lock);
1924 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1925 spin_unlock(&adap->win0_lock);
1926 return ret;
1927
1928err:
1929 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1930 stag, offset);
1931 return -EINVAL;
1932}
1933EXPORT_SYMBOL(cxgb4_read_tpte);
1934
7730b4c7
HS		 1935u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1936{
1937 u32 hi, lo;
1938 struct adapter *adap;
1939
1940 adap = netdev2adap(dev);
f612b815
HS		 1941 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1942 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
7730b4c7
HS		 1943
1944 return ((u64)hi << 32) | (u64)lo;
1945}
1946EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1947
df64e4d3
HS		 1948int cxgb4_bar2_sge_qregs(struct net_device *dev,
1949 unsigned int qid,
1950 enum cxgb4_bar2_qtype qtype,
66cf188e 1951 int user,
df64e4d3
HS		 1952 u64 *pbar2_qoffset,
1953 unsigned int *pbar2_qid)
1954{
b2612722 1955 return t4_bar2_sge_qregs(netdev2adap(dev),
df64e4d3
HS		 1956 qid,
1957 (qtype == CXGB4_BAR2_QTYPE_EGRESS
1958 ? T4_BAR2_QTYPE_EGRESS
1959 : T4_BAR2_QTYPE_INGRESS),
66cf188e 1960 user,
df64e4d3
HS		 1961 pbar2_qoffset,
1962 pbar2_qid);
1963}
1964EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1965
b8ff05a9
DM		 1966static struct pci_driver cxgb4_driver;
1967
1968static void check_neigh_update(struct neighbour *neigh)
1969{
1970 const struct device *parent;
1971 const struct net_device *netdev = neigh->dev;
1972
d0d7b10b 1973 if (is_vlan_dev(netdev))
b8ff05a9
DM		 1974 netdev = vlan_dev_real_dev(netdev);
1975 parent = netdev->dev.parent;
1976 if (parent && parent->driver == &cxgb4_driver.driver)
1977 t4_l2t_update(dev_get_drvdata(parent), neigh);
1978}
1979
1980static int netevent_cb(struct notifier_block *nb, unsigned long event,
1981 void *data)
1982{
1983 switch (event) {
1984 case NETEVENT_NEIGH_UPDATE:
1985 check_neigh_update(data);
1986 break;
b8ff05a9
DM		 1987 case NETEVENT_REDIRECT:
1988 default:
1989 break;
1990 }
1991 return 0;
1992}
1993
1994static bool netevent_registered;
1995static struct notifier_block cxgb4_netevent_nb = {
1996 .notifier_call = netevent_cb
1997};
1998
3069ee9b
VP		 1999static void drain_db_fifo(struct adapter *adap, int usecs)
2000{
2cc301d2 2001 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 2002
2003 do {
f061de42
HS		 2004 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2005 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 2006 if (is_t4(adap->params.chip)) {
f061de42
HS		 2007 lp_count = LP_COUNT_G(v1);
2008 hp_count = HP_COUNT_G(v1);
2cc301d2 2009 } else {
f061de42
HS		 2010 lp_count = LP_COUNT_T5_G(v1);
2011 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 2012 }
2013
2014 if (lp_count == 0 && hp_count == 0)
2015 break;
3069ee9b
VP		 2016 set_current_state(TASK_UNINTERRUPTIBLE);
2017 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 2018 } while (1);
2019}
2020
2021static void disable_txq_db(struct sge_txq *q)
2022{
05eb2389
SW		 2023 unsigned long flags;
2024
2025 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 2026 q->db_disabled = 1;
05eb2389 2027 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 2028}
2029
05eb2389 2030static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 2031{
2032 spin_lock_irq(&q->db_lock);
05eb2389
SW		 2033 if (q->db_pidx_inc) {
2034 /* Make sure that all writes to the TX descriptors
2035 * are committed before we tell HW about them.
2036 */
2037 wmb();
f612b815
HS		 2038 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2039 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
05eb2389
SW		 2040 q->db_pidx_inc = 0;
2041 }
3069ee9b
VP		 2042 q->db_disabled = 0;
2043 spin_unlock_irq(&q->db_lock);
2044}
2045
2046static void disable_dbs(struct adapter *adap)
2047{
2048 int i;
2049
2050 for_each_ethrxq(&adap->sge, i)
2051 disable_txq_db(&adap->sge.ethtxq[i].q);
ab677ff4
HS		 2052 if (is_offload(adap)) {
2053 struct sge_uld_txq_info *txq_info =
2054 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2055
2056 if (txq_info) {
2057 for_each_ofldtxq(&adap->sge, i) {
2058 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2059
2060 disable_txq_db(&txq->q);
2061 }
2062 }
2063 }
3069ee9b
VP		 2064 for_each_port(adap, i)
2065 disable_txq_db(&adap->sge.ctrlq[i].q);
2066}
2067
2068static void enable_dbs(struct adapter *adap)
2069{
2070 int i;
2071
2072 for_each_ethrxq(&adap->sge, i)
05eb2389 2073 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
ab677ff4
HS		 2074 if (is_offload(adap)) {
2075 struct sge_uld_txq_info *txq_info =
2076 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2077
2078 if (txq_info) {
2079 for_each_ofldtxq(&adap->sge, i) {
2080 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2081
2082 enable_txq_db(adap, &txq->q);
2083 }
2084 }
2085 }
3069ee9b 2086 for_each_port(adap, i)
05eb2389
SW		 2087 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2088}
2089
2090static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2091{
0fbc81b3
HS		 2092 enum cxgb4_uld type = CXGB4_ULD_RDMA;
2093
2094 if (adap->uld && adap->uld[type].handle)
2095 adap->uld[type].control(adap->uld[type].handle, cmd);
05eb2389
SW		 2096}
2097
2098static void process_db_full(struct work_struct *work)
2099{
2100 struct adapter *adap;
2101
2102 adap = container_of(work, struct adapter, db_full_task);
2103
2104 drain_db_fifo(adap, dbfifo_drain_delay);
2105 enable_dbs(adap);
2106 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7
HS		 2107 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2108 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2109 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2110 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2111 else
2112 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2113 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
3069ee9b
VP		 2114}
2115
2116static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2117{
2118 u16 hw_pidx, hw_cidx;
2119 int ret;
2120
05eb2389 2121 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 2122 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2123 if (ret)
2124 goto out;
2125 if (q->db_pidx != hw_pidx) {
2126 u16 delta;
f612b815 2127 u32 val;
3069ee9b
VP		 2128
2129 if (q->db_pidx >= hw_pidx)
2130 delta = q->db_pidx - hw_pidx;
2131 else
2132 delta = q->size - hw_pidx + q->db_pidx;
f612b815
HS		 2133
2134 if (is_t4(adap->params.chip))
2135 val = PIDX_V(delta);
2136 else
2137 val = PIDX_T5_V(delta);
3069ee9b 2138 wmb();
f612b815
HS		 2139 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2140 QID_V(q->cntxt_id) | val);
3069ee9b
VP		 2141 }
2142out:
2143 q->db_disabled = 0;
05eb2389
SW		 2144 q->db_pidx_inc = 0;
2145 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 2146 if (ret)
2147 CH_WARN(adap, "DB drop recovery failed.\n");
2148}
0fbc81b3 2149
3069ee9b
VP		 2150static void recover_all_queues(struct adapter *adap)
2151{
2152 int i;
2153
2154 for_each_ethrxq(&adap->sge, i)
2155 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
ab677ff4
HS		 2156 if (is_offload(adap)) {
2157 struct sge_uld_txq_info *txq_info =
2158 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2159 if (txq_info) {
2160 for_each_ofldtxq(&adap->sge, i) {
2161 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2162
2163 sync_txq_pidx(adap, &txq->q);
2164 }
2165 }
2166 }
3069ee9b
VP		 2167 for_each_port(adap, i)
2168 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2169}
2170
881806bc
VP		 2171static void process_db_drop(struct work_struct *work)
2172{
2173 struct adapter *adap;
881806bc 2174
3069ee9b 2175 adap = container_of(work, struct adapter, db_drop_task);
881806bc 2176
d14807dd 2177 if (is_t4(adap->params.chip)) {
05eb2389 2178 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2179 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 2180 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2181 recover_all_queues(adap);
05eb2389 2182 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2183 enable_dbs(adap);
05eb2389 2184 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7 2185 } else if (is_t5(adap->params.chip)) {
2cc301d2
SR		 2186 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2187 u16 qid = (dropped_db >> 15) & 0x1ffff;
2188 u16 pidx_inc = dropped_db & 0x1fff;
df64e4d3
HS		 2189 u64 bar2_qoffset;
2190 unsigned int bar2_qid;
2191 int ret;
2cc301d2 2192
b2612722 2193 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
e0456717 2194 0, &bar2_qoffset, &bar2_qid);
df64e4d3
HS		 2195 if (ret)
2196 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2197 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2198 else
f612b815 2199 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
df64e4d3 2200 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2cc301d2
SR		 2201
2202 /* Re-enable BAR2 WC */
2203 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2204 }
2205
3ccc6cf7
HS		 2206 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2207 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
881806bc
VP		 2208}
2209
2210void t4_db_full(struct adapter *adap)
2211{
d14807dd 2212 if (is_t4(adap->params.chip)) {
05eb2389
SW		 2213 disable_dbs(adap);
2214 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
f612b815
HS		 2215 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2216 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
29aaee65 2217 queue_work(adap->workq, &adap->db_full_task);
2cc301d2 2218 }
881806bc
VP		 2219}
2220
2221void t4_db_dropped(struct adapter *adap)
2222{
05eb2389
SW		 2223 if (is_t4(adap->params.chip)) {
2224 disable_dbs(adap);
2225 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2226 }
29aaee65 2227 queue_work(adap->workq, &adap->db_drop_task);
881806bc
VP		 2228}
2229
0fbc81b3
HS		 2230void t4_register_netevent_notifier(void)
2231{
b8ff05a9
DM		 2232 if (!netevent_registered) {
2233 register_netevent_notifier(&cxgb4_netevent_nb);
2234 netevent_registered = true;
2235 }
b8ff05a9
DM		 2236}
2237
2238static void detach_ulds(struct adapter *adap)
2239{
2240 unsigned int i;
2241
2242 mutex_lock(&uld_mutex);
2243 list_del(&adap->list_node);
6a146f3a 2244
b8ff05a9 2245 for (i = 0; i < CXGB4_ULD_MAX; i++)
6a146f3a 2246 if (adap->uld && adap->uld[i].handle)
94cdb8bb
HS		 2247 adap->uld[i].state_change(adap->uld[i].handle,
2248 CXGB4_STATE_DETACH);
6a146f3a 2249
b8ff05a9
DM		 2250 if (netevent_registered && list_empty(&adapter_list)) {
2251 unregister_netevent_notifier(&cxgb4_netevent_nb);
2252 netevent_registered = false;
2253 }
2254 mutex_unlock(&uld_mutex);
2255}
2256
2257static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2258{
2259 unsigned int i;
2260
2261 mutex_lock(&uld_mutex);
2262 for (i = 0; i < CXGB4_ULD_MAX; i++)
94cdb8bb
HS		 2263 if (adap->uld && adap->uld[i].handle)
2264 adap->uld[i].state_change(adap->uld[i].handle,
2265 new_state);
b8ff05a9
DM		 2266 mutex_unlock(&uld_mutex);
2267}
2268
1bb60376 2269#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 2270static int cxgb4_inet6addr_handler(struct notifier_block *this,
2271 unsigned long event, void *data)
01bcca68 2272{
b5a02f50
AB		 2273 struct inet6_ifaddr *ifa = data;
2274 struct net_device *event_dev = ifa->idev->dev;
2275 const struct device *parent = NULL;
2276#if IS_ENABLED(CONFIG_BONDING)
01bcca68 2277 struct adapter *adap;
b5a02f50 2278#endif
d0d7b10b 2279 if (is_vlan_dev(event_dev))
b5a02f50
AB		 2280 event_dev = vlan_dev_real_dev(event_dev);
2281#if IS_ENABLED(CONFIG_BONDING)
2282 if (event_dev->flags & IFF_MASTER) {
2283 list_for_each_entry(adap, &adapter_list, list_node) {
2284 switch (event) {
2285 case NETDEV_UP:
2286 cxgb4_clip_get(adap->port[0],
2287 (const u32 *)ifa, 1);
2288 break;
2289 case NETDEV_DOWN:
2290 cxgb4_clip_release(adap->port[0],
2291 (const u32 *)ifa, 1);
2292 break;
2293 default:
2294 break;
2295 }
2296 }
2297 return NOTIFY_OK;
2298 }
2299#endif
01bcca68 2300
b5a02f50
AB		 2301 if (event_dev)
2302 parent = event_dev->dev.parent;
01bcca68 2303
b5a02f50 2304 if (parent && parent->driver == &cxgb4_driver.driver) {
01bcca68
VP		 2305 switch (event) {
2306 case NETDEV_UP:
b5a02f50 2307 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2308 break;
2309 case NETDEV_DOWN:
b5a02f50 2310 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2311 break;
2312 default:
2313 break;
2314 }
2315 }
b5a02f50 2316 return NOTIFY_OK;
01bcca68
VP		 2317}
2318
b5a02f50 2319static bool inet6addr_registered;
01bcca68
VP		 2320static struct notifier_block cxgb4_inet6addr_notifier = {
2321 .notifier_call = cxgb4_inet6addr_handler
2322};
2323
01bcca68
VP		 2324static void update_clip(const struct adapter *adap)
2325{
2326 int i;
2327 struct net_device *dev;
2328 int ret;
2329
2330 rcu_read_lock();
2331
2332 for (i = 0; i < MAX_NPORTS; i++) {
2333 dev = adap->port[i];
2334 ret = 0;
2335
2336 if (dev)
b5a02f50 2337 ret = cxgb4_update_root_dev_clip(dev);
01bcca68
VP		 2338
2339 if (ret < 0)
2340 break;
2341 }
2342 rcu_read_unlock();
2343}
1bb60376 2344#endif /* IS_ENABLED(CONFIG_IPV6) */
01bcca68 2345
b8ff05a9
DM		 2346/**
2347 * cxgb_up - enable the adapter
2348 * @adap: adapter being enabled
2349 *
2350 * Called when the first port is enabled, this function performs the
2351 * actions necessary to make an adapter operational, such as completing
2352 * the initialization of HW modules, and enabling interrupts.
2353 *
2354 * Must be called with the rtnl lock held.
2355 */
2356static int cxgb_up(struct adapter *adap)
2357{
aaefae9b 2358 int err;
b8ff05a9 2359
91060381 2360 mutex_lock(&uld_mutex);
aaefae9b
DM		 2361 err = setup_sge_queues(adap);
2362 if (err)
91060381 2363 goto rel_lock;
aaefae9b
DM		 2364 err = setup_rss(adap);
2365 if (err)
2366 goto freeq;
b8ff05a9 2367
80f61f19 2368 if (adap->flags & CXGB4_USING_MSIX) {
aaefae9b 2369 name_msix_vecs(adap);
b8ff05a9
DM		 2370 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2371 adap->msix_info[0].desc, adap);
2372 if (err)
2373 goto irq_err;
b8ff05a9
DM		 2374 err = request_msix_queue_irqs(adap);
2375 if (err) {
2376 free_irq(adap->msix_info[0].vec, adap);
2377 goto irq_err;
2378 }
2379 } else {
2380 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
80f61f19
AV		 2381 (adap->flags & CXGB4_USING_MSI) ? 0
2382 : IRQF_SHARED,
b1a3c2b6 2383 adap->port[0]->name, adap);
b8ff05a9
DM		 2384 if (err)
2385 goto irq_err;
2386 }
e7519f99 2387
b8ff05a9
DM		 2388 enable_rx(adap);
2389 t4_sge_start(adap);
2390 t4_intr_enable(adap);
80f61f19 2391 adap->flags |= CXGB4_FULL_INIT_DONE;
e7519f99
GG		 2392 mutex_unlock(&uld_mutex);
2393
b8ff05a9 2394 notify_ulds(adap, CXGB4_STATE_UP);
1bb60376 2395#if IS_ENABLED(CONFIG_IPV6)
01bcca68 2396 update_clip(adap);
1bb60376 2397#endif
b8ff05a9 2398 return err;
91060381 2399
b8ff05a9
DM		 2400 irq_err:
2401 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 2402 freeq:
2403 t4_free_sge_resources(adap);
91060381
RR		 2404 rel_lock:
2405 mutex_unlock(&uld_mutex);
2406 return err;
b8ff05a9
DM		 2407}
2408
2409static void cxgb_down(struct adapter *adapter)
2410{
b8ff05a9 2411 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 2412 cancel_work_sync(&adapter->db_full_task);
2413 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 2414 adapter->tid_release_task_busy = false;
204dc3c0 2415 adapter->tid_release_head = NULL;
b8ff05a9 2416
aaefae9b
DM		 2417 t4_sge_stop(adapter);
2418 t4_free_sge_resources(adapter);
2a8d84bf 2419
80f61f19 2420 adapter->flags &= ~CXGB4_FULL_INIT_DONE;
b8ff05a9
DM		 2421}
2422
2423/*
2424 * net_device operations
2425 */
2426static int cxgb_open(struct net_device *dev)
2427{
2428 int err;
2429 struct port_info *pi = netdev_priv(dev);
2430 struct adapter *adapter = pi->adapter;
2431
6a3c869a
DM		 2432 netif_carrier_off(dev);
2433
80f61f19 2434 if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) {
aaefae9b
DM		 2435 err = cxgb_up(adapter);
2436 if (err < 0)
2437 return err;
2438 }
b8ff05a9 2439
2061ec3f
GG		 2440 /* It's possible that the basic port information could have
2441 * changed since we first read it.
2442 */
2443 err = t4_update_port_info(pi);
2444 if (err < 0)
2445 return err;
2446
f68707b8
DM		 2447 err = link_start(dev);
2448 if (!err)
2449 netif_tx_start_all_queues(dev);
2450 return err;
b8ff05a9
DM		 2451}
2452
2453static int cxgb_close(struct net_device *dev)
2454{
b8ff05a9
DM		 2455 struct port_info *pi = netdev_priv(dev);
2456 struct adapter *adapter = pi->adapter;
ba581f77 2457 int ret;
b8ff05a9
DM		 2458
2459 netif_tx_stop_all_queues(dev);
2460 netif_carrier_off(dev);
e2f4f4e9
AV		 2461 ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2462 false, false, false);
ba581f77
GG		 2463#ifdef CONFIG_CHELSIO_T4_DCB
2464 cxgb4_dcb_reset(dev);
2465 dcb_tx_queue_prio_enable(dev, false);
2466#endif
2467 return ret;
b8ff05a9
DM		 2468}
2469
dca4faeb 2470int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 2471 __be32 sip, __be16 sport, __be16 vlan,
2472 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 2473{
2474 int ret;
2475 struct filter_entry *f;
2476 struct adapter *adap;
2477 int i;
2478 u8 *val;
2479
2480 adap = netdev2adap(dev);
2481
1cab775c 2482 /* Adjust stid to correct filter index */
470c60c4 2483 stid -= adap->tids.sftid_base;
1cab775c
VP		 2484 stid += adap->tids.nftids;
2485
dca4faeb
VP		 2486 /* Check to make sure the filter requested is writable ...
2487 */
2488 f = &adap->tids.ftid_tab[stid];
2489 ret = writable_filter(f);
2490 if (ret)
2491 return ret;
2492
2493 /* Clear out any old resources being used by the filter before
2494 * we start constructing the new filter.
2495 */
2496 if (f->valid)
2497 clear_filter(adap, f);
2498
2499 /* Clear out filter specifications */
2500 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2501 f->fs.val.lport = cpu_to_be16(sport);
2502 f->fs.mask.lport = ~0;
2503 val = (u8 *)&sip;
793dad94 2504 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 2505 for (i = 0; i < 4; i++) {
2506 f->fs.val.lip[i] = val[i];
2507 f->fs.mask.lip[i] = ~0;
2508 }
0d804338 2509 if (adap->params.tp.vlan_pri_map & PORT_F) {
793dad94
VP		 2510 f->fs.val.iport = port;
2511 f->fs.mask.iport = mask;
2512 }
2513 }
dca4faeb 2514
0d804338 2515 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
7c89e555
KS		 2516 f->fs.val.proto = IPPROTO_TCP;
2517 f->fs.mask.proto = ~0;
2518 }
2519
dca4faeb
VP		 2520 f->fs.dirsteer = 1;
2521 f->fs.iq = queue;
2522 /* Mark filter as locked */
2523 f->locked = 1;
2524 f->fs.rpttid = 1;
2525
6b254afd
GG		 2526 /* Save the actual tid. We need this to get the corresponding
2527 * filter entry structure in filter_rpl.
2528 */
2529 f->tid = stid + adap->tids.ftid_base;
dca4faeb
VP		 2530 ret = set_filter_wr(adap, stid);
2531 if (ret) {
2532 clear_filter(adap, f);
2533 return ret;
2534 }
2535
2536 return 0;
2537}
2538EXPORT_SYMBOL(cxgb4_create_server_filter);
2539
2540int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2541 unsigned int queue, bool ipv6)
2542{
dca4faeb
VP		 2543 struct filter_entry *f;
2544 struct adapter *adap;
2545
2546 adap = netdev2adap(dev);
1cab775c
VP		 2547
2548 /* Adjust stid to correct filter index */
470c60c4 2549 stid -= adap->tids.sftid_base;
1cab775c
VP		 2550 stid += adap->tids.nftids;
2551
dca4faeb
VP		 2552 f = &adap->tids.ftid_tab[stid];
2553 /* Unlock the filter */
2554 f->locked = 0;
2555
8c14846d 2556 return delete_filter(adap, stid);
dca4faeb
VP		 2557}
2558EXPORT_SYMBOL(cxgb4_remove_server_filter);
2559
bc1f4470 2560static void cxgb_get_stats(struct net_device *dev,
2561 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 2562{
2563 struct port_stats stats;
2564 struct port_info *p = netdev_priv(dev);
2565 struct adapter *adapter = p->adapter;
b8ff05a9 2566
9fe6cb58
GS		 2567 /* Block retrieving statistics during EEH error
2568 * recovery. Otherwise, the recovery might fail
2569 * and the PCI device will be removed permanently
2570 */
b8ff05a9 2571 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 2572 if (!netif_device_present(dev)) {
2573 spin_unlock(&adapter->stats_lock);
bc1f4470 2574 return;
9fe6cb58 2575 }
a4cfd929
HS		 2576 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2577 &p->stats_base);
b8ff05a9
DM		 2578 spin_unlock(&adapter->stats_lock);
2579
2580 ns->tx_bytes = stats.tx_octets;
2581 ns->tx_packets = stats.tx_frames;
2582 ns->rx_bytes = stats.rx_octets;
2583 ns->rx_packets = stats.rx_frames;
2584 ns->multicast = stats.rx_mcast_frames;
2585
2586 /* detailed rx_errors */
2587 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2588 stats.rx_runt;
2589 ns->rx_over_errors = 0;
2590 ns->rx_crc_errors = stats.rx_fcs_err;
2591 ns->rx_frame_errors = stats.rx_symbol_err;
b93f79be 2592 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 +
b8ff05a9
DM		 2593 stats.rx_ovflow2 + stats.rx_ovflow3 +
2594 stats.rx_trunc0 + stats.rx_trunc1 +
2595 stats.rx_trunc2 + stats.rx_trunc3;
2596 ns->rx_missed_errors = 0;
2597
2598 /* detailed tx_errors */
2599 ns->tx_aborted_errors = 0;
2600 ns->tx_carrier_errors = 0;
2601 ns->tx_fifo_errors = 0;
2602 ns->tx_heartbeat_errors = 0;
2603 ns->tx_window_errors = 0;
2604
2605 ns->tx_errors = stats.tx_error_frames;
2606 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2607 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
b8ff05a9
DM		 2608}
2609
2610static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2611{
060e0c75 2612 unsigned int mbox;
b8ff05a9
DM		 2613 int ret = 0, prtad, devad;
2614 struct port_info *pi = netdev_priv(dev);
a4569504 2615 struct adapter *adapter = pi->adapter;
b8ff05a9
DM		 2616 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2617
2618 switch (cmd) {
2619 case SIOCGMIIPHY:
2620 if (pi->mdio_addr < 0)
2621 return -EOPNOTSUPP;
2622 data->phy_id = pi->mdio_addr;
2623 break;
2624 case SIOCGMIIREG:
2625 case SIOCSMIIREG:
2626 if (mdio_phy_id_is_c45(data->phy_id)) {
2627 prtad = mdio_phy_id_prtad(data->phy_id);
2628 devad = mdio_phy_id_devad(data->phy_id);
2629 } else if (data->phy_id < 32) {
2630 prtad = data->phy_id;
2631 devad = 0;
2632 data->reg_num &= 0x1f;
2633 } else
2634 return -EINVAL;
2635
b2612722 2636 mbox = pi->adapter->pf;
b8ff05a9 2637 if (cmd == SIOCGMIIREG)
060e0c75 2638 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2639 data->reg_num, &data->val_out);
2640 else
060e0c75 2641 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2642 data->reg_num, data->val_in);
2643 break;
5e2a5ebc
HS		 2644 case SIOCGHWTSTAMP:
2645 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2646 sizeof(pi->tstamp_config)) ?
2647 -EFAULT : 0;
2648 case SIOCSHWTSTAMP:
2649 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2650 sizeof(pi->tstamp_config)))
2651 return -EFAULT;
2652
a4569504
AG		 2653 if (!is_t4(adapter->params.chip)) {
2654 switch (pi->tstamp_config.tx_type) {
2655 case HWTSTAMP_TX_OFF:
2656 case HWTSTAMP_TX_ON:
2657 break;
2658 default:
2659 return -ERANGE;
2660 }
2661
2662 switch (pi->tstamp_config.rx_filter) {
2663 case HWTSTAMP_FILTER_NONE:
2664 pi->rxtstamp = false;
2665 break;
2666 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2667 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2668 cxgb4_ptprx_timestamping(pi, pi->port_id,
2669 PTP_TS_L4);
2670 break;
2671 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2672 cxgb4_ptprx_timestamping(pi, pi->port_id,
2673 PTP_TS_L2_L4);
2674 break;
2675 case HWTSTAMP_FILTER_ALL:
2676 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2677 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2678 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2679 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2680 pi->rxtstamp = true;
2681 break;
2682 default:
2683 pi->tstamp_config.rx_filter =
2684 HWTSTAMP_FILTER_NONE;
2685 return -ERANGE;
2686 }
2687
2688 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2689 (pi->tstamp_config.rx_filter ==
2690 HWTSTAMP_FILTER_NONE)) {
2691 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2692 pi->ptp_enable = false;
2693 }
2694
2695 if (pi->tstamp_config.rx_filter !=
2696 HWTSTAMP_FILTER_NONE) {
2697 if (cxgb4_ptp_redirect_rx_packet(adapter,
2698 pi) >= 0)
2699 pi->ptp_enable = true;
2700 }
2701 } else {
2702 /* For T4 Adapters */
2703 switch (pi->tstamp_config.rx_filter) {
2704 case HWTSTAMP_FILTER_NONE:
5e2a5ebc
HS		 2705 pi->rxtstamp = false;
2706 break;
a4569504 2707 case HWTSTAMP_FILTER_ALL:
5e2a5ebc
HS		 2708 pi->rxtstamp = true;
2709 break;
a4569504
AG		 2710 default:
2711 pi->tstamp_config.rx_filter =
2712 HWTSTAMP_FILTER_NONE;
5e2a5ebc 2713 return -ERANGE;
a4569504 2714 }
5e2a5ebc 2715 }
5e2a5ebc
HS		 2716 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2717 sizeof(pi->tstamp_config)) ?
2718 -EFAULT : 0;
b8ff05a9
DM		 2719 default:
2720 return -EOPNOTSUPP;
2721 }
2722 return ret;
2723}
2724
2725static void cxgb_set_rxmode(struct net_device *dev)
2726{
2727 /* unfortunately we can't return errors to the stack */
2728 set_rxmode(dev, -1, false);
2729}
2730
2731static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2732{
2733 int ret;
2734 struct port_info *pi = netdev_priv(dev);
2735
b2612722 2736 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
060e0c75 2737 -1, -1, -1, true);
b8ff05a9
DM		 2738 if (!ret)
2739 dev->mtu = new_mtu;
2740 return ret;
2741}
2742
858aa65c 2743#ifdef CONFIG_PCI_IOV
baf50868 2744static int cxgb4_mgmt_open(struct net_device *dev)
e7b48a32
HS		 2745{
2746 /* Turn carrier off since we don't have to transmit anything on this
2747 * interface.
2748 */
2749 netif_carrier_off(dev);
2750 return 0;
2751}
2752
661dbeb9 2753/* Fill MAC address that will be assigned by the FW */
baf50868 2754static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
661dbeb9 2755{
661dbeb9 2756 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
baf50868
GG		 2757 unsigned int i, vf, nvfs;
2758 u16 a, b;
661dbeb9
HS		 2759 int err;
2760 u8 *na;
661dbeb9 2761
baf50868
GG		 2762 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2763 PCI_CAP_ID_VPD);
661dbeb9 2764 err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
baf50868
GG		 2765 if (err)
2766 return;
2767
2768 na = adap->params.vpd.na;
2769 for (i = 0; i < ETH_ALEN; i++)
2770 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2771 hex2val(na[2 * i + 1]));
2772
2773 a = (hw_addr[0] << 8) | hw_addr[1];
2774 b = (hw_addr[1] << 8) | hw_addr[2];
2775 a ^= b;
2776 a |= 0x0200; /* locally assigned Ethernet MAC address */
2777 a &= ~0x0100; /* not a multicast Ethernet MAC address */
2778 macaddr[0] = a >> 8;
2779 macaddr[1] = a & 0xff;
2780
2781 for (i = 2; i < 5; i++)
2782 macaddr[i] = hw_addr[i + 1];
2783
2784 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2785 vf < nvfs; vf++) {
1b974aa4 2786 macaddr[5] = adap->pf * nvfs + vf;
baf50868 2787 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
661dbeb9
HS		 2788 }
2789}
2790
baf50868 2791static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
858aa65c
HS		 2792{
2793 struct port_info *pi = netdev_priv(dev);
2794 struct adapter *adap = pi->adapter;
661dbeb9 2795 int ret;
858aa65c
HS		 2796
2797 /* verify MAC addr is valid */
2798 if (!is_valid_ether_addr(mac)) {
2799 dev_err(pi->adapter->pdev_dev,
2800 "Invalid Ethernet address %pM for VF %d\n",
2801 mac, vf);
2802 return -EINVAL;
2803 }
2804
2805 dev_info(pi->adapter->pdev_dev,
2806 "Setting MAC %pM on VF %d\n", mac, vf);
661dbeb9
HS		 2807 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2808 if (!ret)
2809 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2810 return ret;
2811}
2812
baf50868
GG		 2813static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2814 int vf, struct ifla_vf_info *ivi)
661dbeb9
HS		 2815{
2816 struct port_info *pi = netdev_priv(dev);
2817 struct adapter *adap = pi->adapter;
bd79acee 2818 struct vf_info *vfinfo;
661dbeb9
HS		 2819
2820 if (vf >= adap->num_vfs)
2821 return -EINVAL;
bd79acee
AV		 2822 vfinfo = &adap->vfinfo[vf];
2823
661dbeb9 2824 ivi->vf = vf;
bd79acee 2825 ivi->max_tx_rate = vfinfo->tx_rate;
8ea4fae9 2826 ivi->min_tx_rate = 0;
bd79acee
AV		 2827 ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2828 ivi->vlan = vfinfo->vlan;
8b965f3f 2829 ivi->linkstate = vfinfo->link_state;
661dbeb9 2830 return 0;
858aa65c 2831}
96fe11f2 2832
baf50868
GG		 2833static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2834 struct netdev_phys_item_id *ppid)
96fe11f2
GG		 2835{
2836 struct port_info *pi = netdev_priv(dev);
2837 unsigned int phy_port_id;
2838
2839 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2840 ppid->id_len = sizeof(phy_port_id);
2841 memcpy(ppid->id, &phy_port_id, ppid->id_len);
2842 return 0;
2843}
2844
baf50868
GG		 2845static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2846 int min_tx_rate, int max_tx_rate)
8ea4fae9
GG		 2847{
2848 struct port_info *pi = netdev_priv(dev);
2849 struct adapter *adap = pi->adapter;
c3168cab 2850 unsigned int link_ok, speed, mtu;
8ea4fae9
GG		 2851 u32 fw_pfvf, fw_class;
2852 int class_id = vf;
c3168cab 2853 int ret;
8ea4fae9
GG		 2854 u16 pktsize;
2855
2856 if (vf >= adap->num_vfs)
2857 return -EINVAL;
2858
2859 if (min_tx_rate) {
2860 dev_err(adap->pdev_dev,
2861 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2862 min_tx_rate, vf);
2863 return -EINVAL;
2864 }
c3168cab 2865
b5e281ab
GG		 2866 if (max_tx_rate == 0) {
2867 /* unbind VF to to any Traffic Class */
2868 fw_pfvf =
2869 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2870 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2871 fw_class = 0xffffffff;
2872 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2873 &fw_pfvf, &fw_class);
2874 if (ret) {
2875 dev_err(adap->pdev_dev,
2876 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2877 ret, adap->pf, vf);
2878 return -EINVAL;
2879 }
2880 dev_info(adap->pdev_dev,
2881 "PF %d VF %d is unbound from TX Rate Limiting\n",
2882 adap->pf, vf);
2883 adap->vfinfo[vf].tx_rate = 0;
2884 return 0;
2885 }
2886
c3168cab 2887 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
8ea4fae9
GG		 2888 if (ret != FW_SUCCESS) {
2889 dev_err(adap->pdev_dev,
c3168cab 2890 "Failed to get link information for VF %d\n", vf);
8ea4fae9
GG		 2891 return -EINVAL;
2892 }
c3168cab 2893
8ea4fae9
GG		 2894 if (!link_ok) {
2895 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2896 return -EINVAL;
2897 }
8ea4fae9
GG		 2898
2899 if (max_tx_rate > speed) {
2900 dev_err(adap->pdev_dev,
2901 "Max tx rate %d for VF %d can't be > link-speed %u",
2902 max_tx_rate, vf, speed);
2903 return -EINVAL;
2904 }
c3168cab
GG		 2905
2906 pktsize = mtu;
8ea4fae9
GG		 2907 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2908 pktsize = pktsize - sizeof(struct ethhdr) - 4;
2909 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2910 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2911 /* configure Traffic Class for rate-limiting */
2912 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2913 SCHED_CLASS_LEVEL_CL_RL,
2914 SCHED_CLASS_MODE_CLASS,
2915 SCHED_CLASS_RATEUNIT_BITS,
2916 SCHED_CLASS_RATEMODE_ABS,
c3168cab 2917 pi->tx_chan, class_id, 0,
8ea4fae9
GG		 2918 max_tx_rate * 1000, 0, pktsize);
2919 if (ret) {
2920 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2921 ret);
2922 return -EINVAL;
2923 }
2924 dev_info(adap->pdev_dev,
2925 "Class %d with MSS %u configured with rate %u\n",
2926 class_id, pktsize, max_tx_rate);
2927
2928 /* bind VF to configured Traffic Class */
2929 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2930 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2931 fw_class = class_id;
2932 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2933 &fw_class);
2934 if (ret) {
2935 dev_err(adap->pdev_dev,
b5e281ab
GG		 2936 "Err %d in binding PF %d VF %d to Traffic Class %d\n",
2937 ret, adap->pf, vf, class_id);
8ea4fae9
GG		 2938 return -EINVAL;
2939 }
2940 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2941 adap->pf, vf, class_id);
2942 adap->vfinfo[vf].tx_rate = max_tx_rate;
2943 return 0;
2944}
2945
9d5fd927
GG		 2946static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
2947 u16 vlan, u8 qos, __be16 vlan_proto)
2948{
2949 struct port_info *pi = netdev_priv(dev);
2950 struct adapter *adap = pi->adapter;
2951 int ret;
2952
2953 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
2954 return -EINVAL;
2955
2956 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
2957 return -EPROTONOSUPPORT;
2958
2959 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
2960 if (!ret) {
2961 adap->vfinfo[vf].vlan = vlan;
2962 return 0;
2963 }
2964
2965 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
2966 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
2967 return ret;
2968}
8b965f3f
AV		 2969
2970static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf,
2971 int link)
2972{
2973 struct port_info *pi = netdev_priv(dev);
2974 struct adapter *adap = pi->adapter;
2975 u32 param, val;
2976 int ret = 0;
2977
2978 if (vf >= adap->num_vfs)
2979 return -EINVAL;
2980
2981 switch (link) {
2982 case IFLA_VF_LINK_STATE_AUTO:
2983 val = FW_VF_LINK_STATE_AUTO;
2984 break;
2985
2986 case IFLA_VF_LINK_STATE_ENABLE:
2987 val = FW_VF_LINK_STATE_ENABLE;
2988 break;
2989
2990 case IFLA_VF_LINK_STATE_DISABLE:
2991 val = FW_VF_LINK_STATE_DISABLE;
2992 break;
2993
2994 default:
2995 return -EINVAL;
2996 }
2997
2998 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2999 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE));
3000 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
3001 &param, &val);
3002 if (ret) {
3003 dev_err(adap->pdev_dev,
3004 "Error %d in setting PF %d VF %d link state\n",
3005 ret, adap->pf, vf);
3006 return -EINVAL;
3007 }
3008
3009 adap->vfinfo[vf].link_state = link;
3010 return ret;
3011}
9d5fd927 3012#endif /* CONFIG_PCI_IOV */
858aa65c 3013
b8ff05a9
DM		 3014static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3015{
3016 int ret;
3017 struct sockaddr *addr = p;
3018 struct port_info *pi = netdev_priv(dev);
3019
3020 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 3021 return -EADDRNOTAVAIL;
b8ff05a9 3022
3f8cfd0d
AV		 3023 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
3024 addr->sa_data, true, &pi->smt_idx);
b8ff05a9
DM		 3025 if (ret < 0)
3026 return ret;
3027
3028 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3029 pi->xact_addr_filt = ret;
3030 return 0;
3031}
3032
b8ff05a9
DM		 3033#ifdef CONFIG_NET_POLL_CONTROLLER
3034static void cxgb_netpoll(struct net_device *dev)
3035{
3036 struct port_info *pi = netdev_priv(dev);
3037 struct adapter *adap = pi->adapter;
3038
80f61f19 3039 if (adap->flags & CXGB4_USING_MSIX) {
b8ff05a9
DM		 3040 int i;
3041 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3042
3043 for (i = pi->nqsets; i; i--, rx++)
3044 t4_sge_intr_msix(0, &rx->rspq);
3045 } else
3046 t4_intr_handler(adap)(0, adap);
3047}
3048#endif
3049
10a2604e
RL		 3050static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
3051{
3052 struct port_info *pi = netdev_priv(dev);
3053 struct adapter *adap = pi->adapter;
3054 struct sched_class *e;
3055 struct ch_sched_params p;
3056 struct ch_sched_queue qe;
3057 u32 req_rate;
3058 int err = 0;
3059
3060 if (!can_sched(dev))
3061 return -ENOTSUPP;
3062
3063 if (index < 0 || index > pi->nqsets - 1)
3064 return -EINVAL;
3065
80f61f19 3066 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
10a2604e
RL		 3067 dev_err(adap->pdev_dev,
3068 "Failed to rate limit on queue %d. Link Down?\n",
3069 index);
3070 return -EINVAL;
3071 }
3072
3073 /* Convert from Mbps to Kbps */
b3c594ab 3074 req_rate = rate * 1000;
10a2604e 3075
d185efc1 3076 /* Max rate is 100 Gbps */
b3c594ab 3077 if (req_rate > SCHED_MAX_RATE_KBPS) {
10a2604e 3078 dev_err(adap->pdev_dev,
d185efc1 3079 "Invalid rate %u Mbps, Max rate is %u Mbps\n",
b3c594ab 3080 rate, SCHED_MAX_RATE_KBPS / 1000);
10a2604e
RL		 3081 return -ERANGE;
3082 }
3083
3084 /* First unbind the queue from any existing class */
3085 memset(&qe, 0, sizeof(qe));
3086 qe.queue = index;
3087 qe.class = SCHED_CLS_NONE;
3088
3089 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
3090 if (err) {
3091 dev_err(adap->pdev_dev,
3092 "Unbinding Queue %d on port %d fail. Err: %d\n",
3093 index, pi->port_id, err);
3094 return err;
3095 }
3096
3097 /* Queue already unbound */
3098 if (!req_rate)
3099 return 0;
3100
3101 /* Fetch any available unused or matching scheduling class */
3102 memset(&p, 0, sizeof(p));
3103 p.type = SCHED_CLASS_TYPE_PACKET;
3104 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL;
3105 p.u.params.mode = SCHED_CLASS_MODE_CLASS;
3106 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
3107 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
3108 p.u.params.channel = pi->tx_chan;
3109 p.u.params.class = SCHED_CLS_NONE;
3110 p.u.params.minrate = 0;
3111 p.u.params.maxrate = req_rate;
3112 p.u.params.weight = 0;
3113 p.u.params.pktsize = dev->mtu;
3114
3115 e = cxgb4_sched_class_alloc(dev, &p);
3116 if (!e)
3117 return -ENOMEM;
3118
3119 /* Bind the queue to a scheduling class */
3120 memset(&qe, 0, sizeof(qe));
3121 qe.queue = index;
3122 qe.class = e->idx;
3123
3124 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
3125 if (err)
3126 dev_err(adap->pdev_dev,
3127 "Queue rate limiting failed. Err: %d\n", err);
3128 return err;
3129}
3130
6a345b3d
KS		 3131static int cxgb_setup_tc_flower(struct net_device *dev,
3132 struct tc_cls_flower_offload *cls_flower)
3133{
6a345b3d
KS		 3134 switch (cls_flower->command) {
3135 case TC_CLSFLOWER_REPLACE:
3136 return cxgb4_tc_flower_replace(dev, cls_flower);
3137 case TC_CLSFLOWER_DESTROY:
3138 return cxgb4_tc_flower_destroy(dev, cls_flower);
3139 case TC_CLSFLOWER_STATS:
3140 return cxgb4_tc_flower_stats(dev, cls_flower);
3141 default:
3142 return -EOPNOTSUPP;
3143 }
3144}
3145
f7323043 3146static int cxgb_setup_tc_cls_u32(struct net_device *dev,
f7323043
JP		 3147 struct tc_cls_u32_offload *cls_u32)
3148{
f7323043
JP		 3149 switch (cls_u32->command) {
3150 case TC_CLSU32_NEW_KNODE:
3151 case TC_CLSU32_REPLACE_KNODE:
5fd9fc4e 3152 return cxgb4_config_knode(dev, cls_u32);
f7323043 3153 case TC_CLSU32_DELETE_KNODE:
5fd9fc4e 3154 return cxgb4_delete_knode(dev, cls_u32);
f7323043
JP		 3155 default:
3156 return -EOPNOTSUPP;
3157 }
3158}
3159
cd019e91
JP		 3160static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3161 void *cb_priv)
d8931847 3162{
cd019e91 3163 struct net_device *dev = cb_priv;
d8931847
RL		 3164 struct port_info *pi = netdev2pinfo(dev);
3165 struct adapter *adap = netdev2adap(dev);
3166
80f61f19 3167 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
d8931847
RL		 3168 dev_err(adap->pdev_dev,
3169 "Failed to setup tc on port %d. Link Down?\n",
3170 pi->port_id);
3171 return -EINVAL;
3172 }
3173
2a84bbaf 3174 if (!tc_cls_can_offload_and_chain0(dev, type_data))
44ae12a7
JP		 3175 return -EOPNOTSUPP;
3176
f7323043
JP		 3177 switch (type) {
3178 case TC_SETUP_CLSU32:
de4784ca 3179 return cxgb_setup_tc_cls_u32(dev, type_data);
6a345b3d
KS		 3180 case TC_SETUP_CLSFLOWER:
3181 return cxgb_setup_tc_flower(dev, type_data);
f7323043
JP		 3182 default:
3183 return -EOPNOTSUPP;
d8931847 3184 }
d8931847
RL		 3185}
3186
cd019e91
JP		 3187static int cxgb_setup_tc_block(struct net_device *dev,
3188 struct tc_block_offload *f)
3189{
3190 struct port_info *pi = netdev2pinfo(dev);
3191
3192 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3193 return -EOPNOTSUPP;
3194
3195 switch (f->command) {
3196 case TC_BLOCK_BIND:
3197 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb,
60513bd8 3198 pi, dev, f->extack);
cd019e91
JP		 3199 case TC_BLOCK_UNBIND:
3200 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi);
3201 return 0;
3202 default:
3203 return -EOPNOTSUPP;
3204 }
3205}
3206
3207static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3208 void *type_data)
3209{
3210 switch (type) {
cd019e91
JP		 3211 case TC_SETUP_BLOCK:
3212 return cxgb_setup_tc_block(dev, type_data);
3213 default:
3214 return -EOPNOTSUPP;
3215 }
3216}
3217
846eac3f
GG		 3218static void cxgb_del_udp_tunnel(struct net_device *netdev,
3219 struct udp_tunnel_info *ti)
3220{
3221 struct port_info *pi = netdev_priv(netdev);
3222 struct adapter *adapter = pi->adapter;
3223 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3224 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3225 int ret = 0, i;
3226
3227 if (chip_ver < CHELSIO_T6)
3228 return;
3229
3230 switch (ti->type) {
3231 case UDP_TUNNEL_TYPE_VXLAN:
3232 if (!adapter->vxlan_port_cnt ||
3233 adapter->vxlan_port != ti->port)
3234 return; /* Invalid VxLAN destination port */
3235
3236 adapter->vxlan_port_cnt--;
3237 if (adapter->vxlan_port_cnt)
3238 return;
3239
3240 adapter->vxlan_port = 0;
3241 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3242 break;
c746fc0e
GG		 3243 case UDP_TUNNEL_TYPE_GENEVE:
3244 if (!adapter->geneve_port_cnt ||
3245 adapter->geneve_port != ti->port)
3246 return; /* Invalid GENEVE destination port */
3247
3248 adapter->geneve_port_cnt--;
3249 if (adapter->geneve_port_cnt)
3250 return;
3251
3252 adapter->geneve_port = 0;
3253 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
942a656f 3254 break;
846eac3f
GG		 3255 default:
3256 return;
3257 }
3258
3259 /* Matchall mac entries can be deleted only after all tunnel ports
3260 * are brought down or removed.
3261 */
3262 if (!adapter->rawf_cnt)
3263 return;
3264 for_each_port(adapter, i) {
3265 pi = adap2pinfo(adapter, i);
3266 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3267 match_all_mac, match_all_mac,
3268 adapter->rawf_start +
3269 pi->port_id,
443e2dab 3270 1, pi->port_id, false);
846eac3f
GG		 3271 if (ret < 0) {
3272 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3273 i);
3274 return;
3275 }
846eac3f
GG		 3276 }
3277}
3278
3279static void cxgb_add_udp_tunnel(struct net_device *netdev,
3280 struct udp_tunnel_info *ti)
3281{
3282 struct port_info *pi = netdev_priv(netdev);
3283 struct adapter *adapter = pi->adapter;
3284 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3285 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3286 int i, ret;
3287
c746fc0e 3288 if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
846eac3f
GG		 3289 return;
3290
3291 switch (ti->type) {
3292 case UDP_TUNNEL_TYPE_VXLAN:
846eac3f
GG		 3293 /* Callback for adding vxlan port can be called with the same
3294 * port for both IPv4 and IPv6. We should not disable the
3295 * offloading when the same port for both protocols is added
3296 * and later one of them is removed.
3297 */
3298 if (adapter->vxlan_port_cnt &&
3299 adapter->vxlan_port == ti->port) {
3300 adapter->vxlan_port_cnt++;
3301 return;
3302 }
3303
3304 /* We will support only one VxLAN port */
3305 if (adapter->vxlan_port_cnt) {
3306 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3307 be16_to_cpu(adapter->vxlan_port),
3308 be16_to_cpu(ti->port));
3309 return;
3310 }
3311
3312 adapter->vxlan_port = ti->port;
3313 adapter->vxlan_port_cnt = 1;
3314
3315 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3316 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3317 break;
c746fc0e
GG		 3318 case UDP_TUNNEL_TYPE_GENEVE:
3319 if (adapter->geneve_port_cnt &&
3320 adapter->geneve_port == ti->port) {
3321 adapter->geneve_port_cnt++;
3322 return;
3323 }
3324
3325 /* We will support only one GENEVE port */
3326 if (adapter->geneve_port_cnt) {
3327 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3328 be16_to_cpu(adapter->geneve_port),
3329 be16_to_cpu(ti->port));
3330 return;
3331 }
3332
3333 adapter->geneve_port = ti->port;
3334 adapter->geneve_port_cnt = 1;
3335
3336 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3337 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
942a656f 3338 break;
846eac3f
GG		 3339 default:
3340 return;
3341 }
3342
3343 /* Create a 'match all' mac filter entry for inner mac,
3344 * if raw mac interface is supported. Once the linux kernel provides
3345 * driver entry points for adding/deleting the inner mac addresses,
3346 * we will remove this 'match all' entry and fallback to adding
3347 * exact match filters.
3348 */
c746fc0e
GG		 3349 for_each_port(adapter, i) {
3350 pi = adap2pinfo(adapter, i);
3351
3352 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3353 match_all_mac,
3354 match_all_mac,
3355 adapter->rawf_start +
3356 pi->port_id,
443e2dab 3357 1, pi->port_id, false);
c746fc0e
GG		 3358 if (ret < 0) {
3359 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3360 be16_to_cpu(ti->port));
3361 cxgb_del_udp_tunnel(netdev, ti);
3362 return;
846eac3f
GG		 3363 }
3364 }
3365}
3366
4621ffd6
GG		 3367static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3368 struct net_device *dev,
3369 netdev_features_t features)
3370{
3371 struct port_info *pi = netdev_priv(dev);
3372 struct adapter *adapter = pi->adapter;
3373
3374 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3375 return features;
3376
3377 /* Check if hw supports offload for this packet */
3378 if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3379 return features;
3380
3381 /* Offload is not supported for this encapsulated packet */
3382 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3383}
3384
90592b9a
AV		 3385static netdev_features_t cxgb_fix_features(struct net_device *dev,
3386 netdev_features_t features)
3387{
3388 /* Disable GRO, if RX_CSUM is disabled */
3389 if (!(features & NETIF_F_RXCSUM))
3390 features &= ~NETIF_F_GRO;
3391
3392 return features;
3393}
3394
b8ff05a9
DM		 3395static const struct net_device_ops cxgb4_netdev_ops = {
3396 .ndo_open = cxgb_open,
3397 .ndo_stop = cxgb_close,
d5fbda61 3398 .ndo_start_xmit = t4_start_xmit,
688848b1 3399 .ndo_select_queue = cxgb_select_queue,
9be793bf 3400 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 3401 .ndo_set_rx_mode = cxgb_set_rxmode,
3402 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 3403 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 3404 .ndo_validate_addr = eth_validate_addr,
3405 .ndo_do_ioctl = cxgb_ioctl,
3406 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 3407#ifdef CONFIG_NET_POLL_CONTROLLER
3408 .ndo_poll_controller = cxgb_netpoll,
3409#endif
84a200b3
VP		 3410#ifdef CONFIG_CHELSIO_T4_FCOE
3411 .ndo_fcoe_enable = cxgb_fcoe_enable,
3412 .ndo_fcoe_disable = cxgb_fcoe_disable,
3413#endif /* CONFIG_CHELSIO_T4_FCOE */
10a2604e 3414 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate,
d8931847 3415 .ndo_setup_tc = cxgb_setup_tc,
846eac3f
GG		 3416 .ndo_udp_tunnel_add = cxgb_add_udp_tunnel,
3417 .ndo_udp_tunnel_del = cxgb_del_udp_tunnel,
4621ffd6 3418 .ndo_features_check = cxgb_features_check,
90592b9a 3419 .ndo_fix_features = cxgb_fix_features,
b8ff05a9
DM		 3420};
3421
858aa65c 3422#ifdef CONFIG_PCI_IOV
e7b48a32 3423static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
8b965f3f
AV		 3424 .ndo_open = cxgb4_mgmt_open,
3425 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac,
3426 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config,
3427 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate,
3428 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id,
3429 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan,
3430 .ndo_set_vf_link_state = cxgb4_mgmt_set_vf_link_state,
7829451c 3431};
e7b48a32 3432#endif
7829451c 3433
baf50868
GG		 3434static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3435 struct ethtool_drvinfo *info)
7829451c
HS		 3436{
3437 struct adapter *adapter = netdev2adap(dev);
3438
3439 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3440 strlcpy(info->version, cxgb4_driver_version,
3441 sizeof(info->version));
3442 strlcpy(info->bus_info, pci_name(adapter->pdev),
3443 sizeof(info->bus_info));
3444}
3445
3446static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
baf50868 3447 .get_drvinfo = cxgb4_mgmt_get_drvinfo,
7829451c
HS		 3448};
3449
8b7372c1
GG		 3450static void notify_fatal_err(struct work_struct *work)
3451{
3452 struct adapter *adap;
3453
3454 adap = container_of(work, struct adapter, fatal_err_notify_task);
3455 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3456}
3457
b8ff05a9
DM		 3458void t4_fatal_err(struct adapter *adap)
3459{
3be0679b
HS		 3460 int port;
3461
025d0973
GP		 3462 if (pci_channel_offline(adap->pdev))
3463 return;
3464
3be0679b
HS		 3465 /* Disable the SGE since ULDs are going to free resources that
3466 * could be exposed to the adapter. RDMA MWs for example...
3467 */
3468 t4_shutdown_adapter(adap);
3469 for_each_port(adap, port) {
3470 struct net_device *dev = adap->port[port];
3471
3472 /* If we get here in very early initialization the network
3473 * devices may not have been set up yet.
3474 */
3475 if (!dev)
3476 continue;
3477
3478 netif_tx_stop_all_queues(dev);
3479 netif_carrier_off(dev);
3480 }
b8ff05a9 3481 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
8b7372c1 3482 queue_work(adap->workq, &adap->fatal_err_notify_task);
b8ff05a9
DM		 3483}
3484
3485static void setup_memwin(struct adapter *adap)
3486{
b562fc37 3487 u32 nic_win_base = t4_get_util_window(adap);
b8ff05a9 3488
b562fc37 3489 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
636f9d37
VP		 3490}
3491
3492static void setup_memwin_rdma(struct adapter *adap)
3493{
1ae970e0 3494 if (adap->vres.ocq.size) {
0abfd152
HS		 3495 u32 start;
3496 unsigned int sz_kb;
1ae970e0 3497
0abfd152
HS		 3498 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3499 start &= PCI_BASE_ADDRESS_MEM_MASK;
3500 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 3501 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3502 t4_write_reg(adap,
f061de42
HS		 3503 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3504 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
1ae970e0 3505 t4_write_reg(adap,
f061de42 3506 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
1ae970e0
DM		 3507 adap->vres.ocq.start);
3508 t4_read_reg(adap,
f061de42 3509 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
1ae970e0 3510 }
b8ff05a9
DM		 3511}
3512
8b4e6b3c
AV		 3513/* HMA Definitions */
3514
3515/* The maximum number of address that can be send in a single FW cmd */
3516#define HMA_MAX_ADDR_IN_CMD 5
3517
3518#define HMA_PAGE_SIZE PAGE_SIZE
3519
3520#define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */
3521
3522#define HMA_PAGE_ORDER \
3523 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \
3524 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3525
3526/* The minimum and maximum possible HMA sizes that can be specified in the FW
3527 * configuration(in units of MB).
3528 */
3529#define HMA_MIN_TOTAL_SIZE 1
3530#define HMA_MAX_TOTAL_SIZE \
3531 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \
3532 HMA_MAX_NO_FW_ADDRESS) >> 20)
3533
3534static void adap_free_hma_mem(struct adapter *adapter)
3535{
3536 struct scatterlist *iter;
3537 struct page *page;
3538 int i;
3539
3540 if (!adapter->hma.sgt)
3541 return;
3542
3543 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3544 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3545 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3546 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3547 }
3548
3549 for_each_sg(adapter->hma.sgt->sgl, iter,
3550 adapter->hma.sgt->orig_nents, i) {
3551 page = sg_page(iter);
3552 if (page)
3553 __free_pages(page, HMA_PAGE_ORDER);
3554 }
3555
3556 kfree(adapter->hma.phy_addr);
3557 sg_free_table(adapter->hma.sgt);
3558 kfree(adapter->hma.sgt);
3559 adapter->hma.sgt = NULL;
3560}
3561
3562static int adap_config_hma(struct adapter *adapter)
3563{
3564 struct scatterlist *sgl, *iter;
3565 struct sg_table *sgt;
3566 struct page *newpage;
3567 unsigned int i, j, k;
3568 u32 param, hma_size;
3569 unsigned int ncmds;
3570 size_t page_size;
3571 u32 page_order;
3572 int node, ret;
3573
3574 /* HMA is supported only for T6+ cards.
3575 * Avoid initializing HMA in kdump kernels.
3576 */
3577 if (is_kdump_kernel() ||
3578 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3579 return 0;
3580
3581 /* Get the HMA region size required by fw */
3582 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3583 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3584 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3585 1, &param, &hma_size);
3586 /* An error means card has its own memory or HMA is not supported by
3587 * the firmware. Return without any errors.
3588 */
3589 if (ret || !hma_size)
3590 return 0;
3591
3592 if (hma_size < HMA_MIN_TOTAL_SIZE ||
3593 hma_size > HMA_MAX_TOTAL_SIZE) {
3594 dev_err(adapter->pdev_dev,
3595 "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3596 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3597 return -EINVAL;
3598 }
3599
3600 page_size = HMA_PAGE_SIZE;
3601 page_order = HMA_PAGE_ORDER;
3602 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3603 if (unlikely(!adapter->hma.sgt)) {
3604 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3605 return -ENOMEM;
3606 }
3607 sgt = adapter->hma.sgt;
3608 /* FW returned value will be in MB's
3609 */
3610 sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3611 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3612 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3613 kfree(adapter->hma.sgt);
3614 adapter->hma.sgt = NULL;
3615 return -ENOMEM;
3616 }
3617
3618 sgl = adapter->hma.sgt->sgl;
3619 node = dev_to_node(adapter->pdev_dev);
3620 for_each_sg(sgl, iter, sgt->orig_nents, i) {
2b928749
GG		 3621 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
3622 __GFP_ZERO, page_order);
8b4e6b3c
AV		 3623 if (!newpage) {
3624 dev_err(adapter->pdev_dev,
3625 "Not enough memory for HMA page allocation\n");
3626 ret = -ENOMEM;
3627 goto free_hma;
3628 }
3629 sg_set_page(iter, newpage, page_size << page_order, 0);
3630 }
3631
3632 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3633 DMA_BIDIRECTIONAL);
3634 if (!sgt->nents) {
3635 dev_err(adapter->pdev_dev,
3636 "Not enough memory for HMA DMA mapping");
3637 ret = -ENOMEM;
3638 goto free_hma;
3639 }
3640 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3641
3642 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3643 GFP_KERNEL);
3644 if (unlikely(!adapter->hma.phy_addr))
3645 goto free_hma;
3646
3647 for_each_sg(sgl, iter, sgt->nents, i) {
3648 newpage = sg_page(iter);
3649 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3650 }
3651
3652 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3653 /* Pass on the addresses to firmware */
3654 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3655 struct fw_hma_cmd hma_cmd;
3656 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3657 u8 soc = 0, eoc = 0;
3658 u8 hma_mode = 1; /* Presently we support only Page table mode */
3659
3660 soc = (i == 0) ? 1 : 0;
3661 eoc = (i == ncmds - 1) ? 1 : 0;
3662
3663 /* For last cmd, set naddr corresponding to remaining
3664 * addresses
3665 */
3666 if (i == ncmds - 1) {
3667 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3668 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3669 }
3670 memset(&hma_cmd, 0, sizeof(hma_cmd));
3671 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3672 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3673 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3674
3675 hma_cmd.mode_to_pcie_params =
3676 htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3677 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3678
3679 /* HMA cmd size specified in MB's */
3680 hma_cmd.naddr_size =
3681 htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3682 FW_HMA_CMD_NADDR_V(naddr));
3683
3684 /* Total Page size specified in units of 4K */
3685 hma_cmd.addr_size_pkd =
3686 htonl(FW_HMA_CMD_ADDR_SIZE_V
3687 ((page_size << page_order) >> 12));
3688
3689 /* Fill the 5 addresses */
3690 for (j = 0; j < naddr; j++) {
3691 hma_cmd.phy_address[j] =
3692 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3693 }
3694 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3695 sizeof(hma_cmd), &hma_cmd);
3696 if (ret) {
3697 dev_err(adapter->pdev_dev,
3698 "HMA FW command failed with err %d\n", ret);
3699 goto free_hma;
3700 }
3701 }
3702
3703 if (!ret)
3704 dev_info(adapter->pdev_dev,
3705 "Reserved %uMB host memory for HMA\n", hma_size);
3706 return ret;
3707
3708free_hma:
3709 adap_free_hma_mem(adapter);
3710 return ret;
3711}
3712
02b5fb8e
DM		 3713static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3714{
3715 u32 v;
3716 int ret;
3717
0eaec62a
CL		 3718 /* Now that we've successfully configured and initialized the adapter
3719 * can ask the Firmware what resources it has provisioned for us.
3720 */
3721 ret = t4_get_pfres(adap);
3722 if (ret) {
3723 dev_err(adap->pdev_dev,
3724 "Unable to retrieve resource provisioning information\n");
3725 return ret;
3726 }
3727
02b5fb8e
DM		 3728 /* get device capabilities */
3729 memset(c, 0, sizeof(*c));
e2ac9628
HS		 3730 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3731 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3732 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
b2612722 3733 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
02b5fb8e
DM		 3734 if (ret < 0)
3735 return ret;
3736
e2ac9628
HS		 3737 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3738 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
b2612722 3739 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
02b5fb8e
DM		 3740 if (ret < 0)
3741 return ret;
3742
b2612722 3743 ret = t4_config_glbl_rss(adap, adap->pf,
02b5fb8e 3744 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
b2e1a3f0
HS		 3745 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3746 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
02b5fb8e
DM		 3747 if (ret < 0)
3748 return ret;
3749
b2612722 3750 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
4b8e27a8
HS		 3751 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3752 FW_CMD_CAP_PF);
02b5fb8e
DM		 3753 if (ret < 0)
3754 return ret;
3755
3756 t4_sge_init(adap);
3757
02b5fb8e 3758 /* tweak some settings */
837e4a42 3759 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
0d804338 3760 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
837e4a42
HS		 3761 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3762 v = t4_read_reg(adap, TP_PIO_DATA_A);
3763 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
060e0c75 3764
dca4faeb
VP		 3765 /* first 4 Tx modulation queues point to consecutive Tx channels */
3766 adap->params.tp.tx_modq_map = 0xE4;
0d804338
HS		 3767 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3768 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
dca4faeb
VP		 3769
3770 /* associate each Tx modulation queue with consecutive Tx channels */
3771 v = 0x84218421;
837e4a42 3772 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3773 &v, 1, TP_TX_SCHED_HDR_A);
837e4a42 3774 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3775 &v, 1, TP_TX_SCHED_FIFO_A);
837e4a42 3776 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3777 &v, 1, TP_TX_SCHED_PCMD_A);
dca4faeb
VP		 3778
3779#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3780 if (is_offload(adap)) {
0d804338
HS		 3781 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3782 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3783 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3784 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3785 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3786 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3787 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3788 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3789 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3790 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
dca4faeb
VP		 3791 }
3792
060e0c75 3793 /* get basic stuff going */
b2612722 3794 return t4_early_init(adap, adap->pf);
02b5fb8e
DM		 3795}
3796
b8ff05a9
DM		 3797/*
3798 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3799 */
3800#define MAX_ATIDS 8192U
3801
636f9d37
VP		 3802/*
3803 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3804 *
3805 * If the firmware we're dealing with has Configuration File support, then
3806 * we use that to perform all configuration
3807 */
3808
3809/*
3810 * Tweak configuration based on module parameters, etc. Most of these have
3811 * defaults assigned to them by Firmware Configuration Files (if we're using
3812 * them) but need to be explicitly set if we're using hard-coded
3813 * initialization. But even in the case of using Firmware Configuration
3814 * Files, we'd like to expose the ability to change these via module
3815 * parameters so these are essentially common tweaks/settings for
3816 * Configuration Files and hard-coded initialization ...
3817 */
3818static int adap_init0_tweaks(struct adapter *adapter)
3819{
3820 /*
3821 * Fix up various Host-Dependent Parameters like Page Size, Cache
3822 * Line Size, etc. The firmware default is for a 4KB Page Size and
3823 * 64B Cache Line Size ...
3824 */
3825 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3826
3827 /*
3828 * Process module parameters which affect early initialization.
3829 */
3830 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3831 dev_err(&adapter->pdev->dev,
3832 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3833 rx_dma_offset);
3834 rx_dma_offset = 2;
3835 }
f612b815
HS		 3836 t4_set_reg_field(adapter, SGE_CONTROL_A,
3837 PKTSHIFT_V(PKTSHIFT_M),
3838 PKTSHIFT_V(rx_dma_offset));
636f9d37
VP		 3839
3840 /*
3841 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3842 * adds the pseudo header itself.
3843 */
837e4a42
HS		 3844 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3845 CSUM_HAS_PSEUDO_HDR_F, 0);
636f9d37
VP		 3846
3847 return 0;
3848}
3849
01b69614
HS		 3850/* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3851 * unto themselves and they contain their own firmware to perform their
3852 * tasks ...
3853 */
3854static int phy_aq1202_version(const u8 *phy_fw_data,
3855 size_t phy_fw_size)
3856{
3857 int offset;
3858
3859 /* At offset 0x8 you're looking for the primary image's
3860 * starting offset which is 3 Bytes wide
3861 *
3862 * At offset 0xa of the primary image, you look for the offset
3863 * of the DRAM segment which is 3 Bytes wide.
3864 *
3865 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3866 * wide
3867 */
3868 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3869 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3870 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3871
3872 offset = le24(phy_fw_data + 0x8) << 12;
3873 offset = le24(phy_fw_data + offset + 0xa);
3874 return be16(phy_fw_data + offset + 0x27e);
3875
3876 #undef be16
3877 #undef le16
3878 #undef le24
3879}
3880
3881static struct info_10gbt_phy_fw {
3882 unsigned int phy_fw_id; /* PCI Device ID */
3883 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3884 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3885 int phy_flash; /* Has FLASH for PHY Firmware */
3886} phy_info_array[] = {
3887 {
3888 PHY_AQ1202_DEVICEID,
3889 PHY_AQ1202_FIRMWARE,
3890 phy_aq1202_version,
3891 1,
3892 },
3893 {
3894 PHY_BCM84834_DEVICEID,
3895 PHY_BCM84834_FIRMWARE,
3896 NULL,
3897 0,
3898 },
3899 { 0, NULL, NULL },
3900};
3901
3902static struct info_10gbt_phy_fw *find_phy_info(int devid)
3903{
3904 int i;
3905
3906 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3907 if (phy_info_array[i].phy_fw_id == devid)
3908 return &phy_info_array[i];
3909 }
3910 return NULL;
3911}
3912
3913/* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3914 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3915 * we return a negative error number. If we transfer new firmware we return 1
3916 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3917 */
3918static int adap_init0_phy(struct adapter *adap)
3919{
3920 const struct firmware *phyf;
3921 int ret;
3922 struct info_10gbt_phy_fw *phy_info;
3923
3924 /* Use the device ID to determine which PHY file to flash.
3925 */
3926 phy_info = find_phy_info(adap->pdev->device);
3927 if (!phy_info) {
3928 dev_warn(adap->pdev_dev,
3929 "No PHY Firmware file found for this PHY\n");
3930 return -EOPNOTSUPP;
3931 }
3932
3933 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3934 * use that. The adapter firmware provides us with a memory buffer
3935 * where we can load a PHY firmware file from the host if we want to
3936 * override the PHY firmware File in flash.
3937 */
3938 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3939 adap->pdev_dev);
3940 if (ret < 0) {
3941 /* For adapters without FLASH attached to PHY for their
3942 * firmware, it's obviously a fatal error if we can't get the
3943 * firmware to the adapter. For adapters with PHY firmware
3944 * FLASH storage, it's worth a warning if we can't find the
3945 * PHY Firmware but we'll neuter the error ...
3946 */
3947 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3948 "/lib/firmware/%s, error %d\n",
3949 phy_info->phy_fw_file, -ret);
3950 if (phy_info->phy_flash) {
3951 int cur_phy_fw_ver = 0;
3952
3953 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3954 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3955 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3956 ret = 0;
3957 }
3958
3959 return ret;
3960 }
3961
3962 /* Load PHY Firmware onto adapter.
3963 */
3964 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3965 phy_info->phy_fw_version,
3966 (u8 *)phyf->data, phyf->size);
3967 if (ret < 0)
3968 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3969 -ret);
3970 else if (ret > 0) {
3971 int new_phy_fw_ver = 0;
3972
3973 if (phy_info->phy_fw_version)
3974 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3975 phyf->size);
3976 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3977 "Firmware /lib/firmware/%s, version %#x\n",
3978 phy_info->phy_fw_file, new_phy_fw_ver);
3979 }
3980
3981 release_firmware(phyf);
3982
3983 return ret;
3984}
3985
636f9d37
VP		 3986/*
3987 * Attempt to initialize the adapter via a Firmware Configuration File.
3988 */
3989static int adap_init0_config(struct adapter *adapter, int reset)
3990{
74dd5aa1
VK		 3991 char *fw_config_file, fw_config_file_path[256];
3992 u32 finiver, finicsum, cfcsum, param, val;
636f9d37 3993 struct fw_caps_config_cmd caps_cmd;
636f9d37 3994 unsigned long mtype = 0, maddr = 0;
74dd5aa1 3995 const struct firmware *cf;
16e47624 3996 char *config_name = NULL;
74dd5aa1
VK		 3997 int config_issued = 0;
3998 int ret;
636f9d37
VP		 3999
4000 /*
4001 * Reset device if necessary.
4002 */
4003 if (reset) {
4004 ret = t4_fw_reset(adapter, adapter->mbox,
0d804338 4005 PIORSTMODE_F | PIORST_F);
636f9d37
VP		 4006 if (ret < 0)
4007 goto bye;
4008 }
4009
01b69614
HS		 4010 /* If this is a 10Gb/s-BT adapter make sure the chip-external
4011 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
4012 * to be performed after any global adapter RESET above since some
4013 * PHYs only have local RAM copies of the PHY firmware.
4014 */
4015 if (is_10gbt_device(adapter->pdev->device)) {
4016 ret = adap_init0_phy(adapter);
4017 if (ret < 0)
4018 goto bye;
4019 }
636f9d37
VP		 4020 /*
4021 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
4022 * then use that. Otherwise, use the configuration file stored
4023 * in the adapter flash ...
4024 */
d14807dd 4025 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 4026 case CHELSIO_T4:
16e47624 4027 fw_config_file = FW4_CFNAME;
0a57a536
SR		 4028 break;
4029 case CHELSIO_T5:
4030 fw_config_file = FW5_CFNAME;
4031 break;
3ccc6cf7
HS		 4032 case CHELSIO_T6:
4033 fw_config_file = FW6_CFNAME;
4034 break;
0a57a536
SR		 4035 default:
4036 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
4037 adapter->pdev->device);
4038 ret = -EINVAL;
4039 goto bye;
4040 }
4041
4042 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 4043 if (ret < 0) {
16e47624 4044 config_name = "On FLASH";
636f9d37
VP		 4045 mtype = FW_MEMTYPE_CF_FLASH;
4046 maddr = t4_flash_cfg_addr(adapter);
4047 } else {
4048 u32 params[7], val[7];
4049
16e47624
HS		 4050 sprintf(fw_config_file_path,
4051 "/lib/firmware/%s", fw_config_file);
4052 config_name = fw_config_file_path;
4053
636f9d37
VP		 4054 if (cf->size >= FLASH_CFG_MAX_SIZE)
4055 ret = -ENOMEM;
4056 else {
5167865a
HS		 4057 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4058 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
636f9d37 4059 ret = t4_query_params(adapter, adapter->mbox,
b2612722 4060 adapter->pf, 0, 1, params, val);
636f9d37
VP		 4061 if (ret == 0) {
4062 /*
fc5ab020 4063 * For t4_memory_rw() below addresses and
636f9d37
VP		 4064 * sizes have to be in terms of multiples of 4
4065 * bytes. So, if the Configuration File isn't
4066 * a multiple of 4 bytes in length we'll have
4067 * to write that out separately since we can't
4068 * guarantee that the bytes following the
4069 * residual byte in the buffer returned by
4070 * request_firmware() are zeroed out ...
4071 */
4072 size_t resid = cf->size & 0x3;
4073 size_t size = cf->size & ~0x3;
4074 __be32 *data = (__be32 *)cf->data;
4075
5167865a
HS		 4076 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
4077 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
636f9d37 4078
fc5ab020
HS		 4079 spin_lock(&adapter->win0_lock);
4080 ret = t4_memory_rw(adapter, 0, mtype, maddr,
4081 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 4082 if (ret == 0 && resid != 0) {
4083 union {
4084 __be32 word;
4085 char buf[4];
4086 } last;
4087 int i;
4088
4089 last.word = data[size >> 2];
4090 for (i = resid; i < 4; i++)
4091 last.buf[i] = 0;
fc5ab020
HS		 4092 ret = t4_memory_rw(adapter, 0, mtype,
4093 maddr + size,
4094 4, &last.word,
4095 T4_MEMORY_WRITE);
636f9d37 4096 }
fc5ab020 4097 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 4098 }
4099 }
4100
4101 release_firmware(cf);
4102 if (ret)
4103 goto bye;
4104 }
4105
74dd5aa1
VK		 4106 val = 0;
4107
4108 /* Ofld + Hash filter is supported. Older fw will fail this request and
4109 * it is fine.
4110 */
4111 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4112 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD));
4113 ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0,
4114 1, &param, &val);
4115
4116 /* FW doesn't know about Hash filter + ofld support,
4117 * it's not a problem, don't return an error.
4118 */
4119 if (ret < 0) {
4120 dev_warn(adapter->pdev_dev,
4121 "Hash filter with ofld is not supported by FW\n");
4122 }
4123
636f9d37
VP		 4124 /*
4125 * Issue a Capability Configuration command to the firmware to get it
4126 * to parse the Configuration File. We don't use t4_fw_config_file()
4127 * because we want the ability to modify various features after we've
4128 * processed the configuration file ...
4129 */
4130 memset(&caps_cmd, 0, sizeof(caps_cmd));
4131 caps_cmd.op_to_write =
e2ac9628
HS		 4132 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4133 FW_CMD_REQUEST_F |
4134 FW_CMD_READ_F);
ce91a923 4135 caps_cmd.cfvalid_to_len16 =
5167865a
HS		 4136 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
4137 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
4138 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
636f9d37
VP		 4139 FW_LEN16(caps_cmd));
4140 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4141 &caps_cmd);
16e47624
HS		 4142
4143 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
4144 * Configuration File in FLASH), our last gasp effort is to use the
4145 * Firmware Configuration File which is embedded in the firmware. A
4146 * very few early versions of the firmware didn't have one embedded
4147 * but we can ignore those.
4148 */
4149 if (ret == -ENOENT) {
4150 memset(&caps_cmd, 0, sizeof(caps_cmd));
4151 caps_cmd.op_to_write =
e2ac9628
HS		 4152 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4153 FW_CMD_REQUEST_F |
4154 FW_CMD_READ_F);
16e47624
HS		 4155 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4156 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
4157 sizeof(caps_cmd), &caps_cmd);
4158 config_name = "Firmware Default";
4159 }
4160
4161 config_issued = 1;
636f9d37
VP		 4162 if (ret < 0)
4163 goto bye;
4164
4165 finiver = ntohl(caps_cmd.finiver);
4166 finicsum = ntohl(caps_cmd.finicsum);
4167 cfcsum = ntohl(caps_cmd.cfcsum);
4168 if (finicsum != cfcsum)
4169 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
4170 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
4171 finicsum, cfcsum);
4172
636f9d37
VP		 4173 /*
4174 * And now tell the firmware to use the configuration we just loaded.
4175 */
4176 caps_cmd.op_to_write =
e2ac9628
HS		 4177 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4178 FW_CMD_REQUEST_F |
4179 FW_CMD_WRITE_F);
ce91a923 4180 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 4181 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4182 NULL);
4183 if (ret < 0)
4184 goto bye;
4185
4186 /*
4187 * Tweak configuration based on system architecture, module
4188 * parameters, etc.
4189 */
4190 ret = adap_init0_tweaks(adapter);
4191 if (ret < 0)
4192 goto bye;
4193
8b4e6b3c
AV		 4194 /* We will proceed even if HMA init fails. */
4195 ret = adap_config_hma(adapter);
4196 if (ret)
4197 dev_err(adapter->pdev_dev,
4198 "HMA configuration failed with error %d\n", ret);
4199
a248384e
VP		 4200 if (is_t6(adapter->params.chip)) {
4201 ret = setup_ppod_edram(adapter);
4202 if (!ret)
4203 dev_info(adapter->pdev_dev, "Successfully enabled "
4204 "ppod edram feature\n");
4205 }
4206
636f9d37
VP		 4207 /*
4208 * And finally tell the firmware to initialize itself using the
4209 * parameters from the Configuration File.
4210 */
4211 ret = t4_fw_initialize(adapter, adapter->mbox);
4212 if (ret < 0)
4213 goto bye;
4214
06640310
HS		 4215 /* Emit Firmware Configuration File information and return
4216 * successfully.
636f9d37 4217 */
636f9d37 4218 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 4219 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
4220 config_name, finiver, cfcsum);
636f9d37
VP		 4221 return 0;
4222
4223 /*
4224 * Something bad happened. Return the error ... (If the "error"
4225 * is that there's no Configuration File on the adapter we don't
4226 * want to issue a warning since this is fairly common.)
4227 */
4228bye:
16e47624
HS		 4229 if (config_issued && ret != -ENOENT)
4230 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4231 config_name, -ret);
636f9d37
VP		 4232 return ret;
4233}
4234
16e47624
HS		 4235static struct fw_info fw_info_array[] = {
4236 {
4237 .chip = CHELSIO_T4,
4238 .fs_name = FW4_CFNAME,
4239 .fw_mod_name = FW4_FNAME,
4240 .fw_hdr = {
4241 .chip = FW_HDR_CHIP_T4,
4242 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4243 .intfver_nic = FW_INTFVER(T4, NIC),
4244 .intfver_vnic = FW_INTFVER(T4, VNIC),
4245 .intfver_ri = FW_INTFVER(T4, RI),
4246 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4247 .intfver_fcoe = FW_INTFVER(T4, FCOE),
4248 },
4249 }, {
4250 .chip = CHELSIO_T5,
4251 .fs_name = FW5_CFNAME,
4252 .fw_mod_name = FW5_FNAME,
4253 .fw_hdr = {
4254 .chip = FW_HDR_CHIP_T5,
4255 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4256 .intfver_nic = FW_INTFVER(T5, NIC),
4257 .intfver_vnic = FW_INTFVER(T5, VNIC),
4258 .intfver_ri = FW_INTFVER(T5, RI),
4259 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4260 .intfver_fcoe = FW_INTFVER(T5, FCOE),
4261 },
3ccc6cf7
HS		 4262 }, {
4263 .chip = CHELSIO_T6,
4264 .fs_name = FW6_CFNAME,
4265 .fw_mod_name = FW6_FNAME,
4266 .fw_hdr = {
4267 .chip = FW_HDR_CHIP_T6,
4268 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4269 .intfver_nic = FW_INTFVER(T6, NIC),
4270 .intfver_vnic = FW_INTFVER(T6, VNIC),
4271 .intfver_ofld = FW_INTFVER(T6, OFLD),
4272 .intfver_ri = FW_INTFVER(T6, RI),
4273 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4274 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4275 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4276 .intfver_fcoe = FW_INTFVER(T6, FCOE),
4277 },
16e47624 4278 }
3ccc6cf7 4279
16e47624
HS		 4280};
4281
4282static struct fw_info *find_fw_info(int chip)
4283{
4284 int i;
4285
4286 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4287 if (fw_info_array[i].chip == chip)
4288 return &fw_info_array[i];
4289 }
4290 return NULL;
4291}
4292
b8ff05a9
DM		 4293/*
4294 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4295 */
4296static int adap_init0(struct adapter *adap)
4297{
4298 int ret;
4299 u32 v, port_vec;
4300 enum dev_state state;
4301 u32 params[7], val[7];
9a4da2cd 4302 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 4303 int reset = 1;
b8ff05a9 4304
ae469b68
HS		 4305 /* Grab Firmware Device Log parameters as early as possible so we have
4306 * access to it for debugging, etc.
4307 */
4308 ret = t4_init_devlog_params(adap);
4309 if (ret < 0)
4310 return ret;
4311
666224d4 4312 /* Contact FW, advertising Master capability */
c5a8c0f3
HS		 4313 ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4314 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
b8ff05a9
DM		 4315 if (ret < 0) {
4316 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4317 ret);
4318 return ret;
4319 }
636f9d37 4320 if (ret == adap->mbox)
80f61f19 4321 adap->flags |= CXGB4_MASTER_PF;
b8ff05a9 4322
636f9d37
VP		 4323 /*
4324 * If we're the Master PF Driver and the device is uninitialized,
4325 * then let's consider upgrading the firmware ... (We always want
4326 * to check the firmware version number in order to A. get it for
4327 * later reporting and B. to warn if the currently loaded firmware
4328 * is excessively mismatched relative to the driver.)
4329 */
0de72738 4330
760446f9 4331 t4_get_version_info(adap);
a69265e9
HS		 4332 ret = t4_check_fw_version(adap);
4333 /* If firmware is too old (not supported by driver) force an update. */
21d11bd6 4334 if (ret)
a69265e9 4335 state = DEV_STATE_UNINIT;
80f61f19 4336 if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 4337 struct fw_info *fw_info;
4338 struct fw_hdr *card_fw;
4339 const struct firmware *fw;
4340 const u8 *fw_data = NULL;
4341 unsigned int fw_size = 0;
4342
4343 /* This is the firmware whose headers the driver was compiled
4344 * against
4345 */
4346 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4347 if (fw_info == NULL) {
4348 dev_err(adap->pdev_dev,
4349 "unable to get firmware info for chip %d.\n",
4350 CHELSIO_CHIP_VERSION(adap->params.chip));
4351 return -EINVAL;
636f9d37 4352 }
16e47624
HS		 4353
4354 /* allocate memory to read the header of the firmware on the
4355 * card
4356 */
752ade68 4357 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
d624613e
Y		 4358 if (!card_fw) {
4359 ret = -ENOMEM;
4360 goto bye;
4361 }
16e47624
HS		 4362
4363 /* Get FW from from /lib/firmware/ */
4364 ret = request_firmware(&fw, fw_info->fw_mod_name,
4365 adap->pdev_dev);
4366 if (ret < 0) {
4367 dev_err(adap->pdev_dev,
4368 "unable to load firmware image %s, error %d\n",
4369 fw_info->fw_mod_name, ret);
4370 } else {
4371 fw_data = fw->data;
4372 fw_size = fw->size;
4373 }
4374
4375 /* upgrade FW logic */
4376 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4377 state, &reset);
4378
4379 /* Cleaning up */
0b5b6bee 4380 release_firmware(fw);
752ade68 4381 kvfree(card_fw);
16e47624 4382
636f9d37 4383 if (ret < 0)
16e47624 4384 goto bye;
636f9d37 4385 }
b8ff05a9 4386
06640310
HS		 4387 /* If the firmware is initialized already, emit a simply note to that
4388 * effect. Otherwise, it's time to try initializing the adapter.
636f9d37
VP		 4389 */
4390 if (state == DEV_STATE_INIT) {
8b4e6b3c
AV		 4391 ret = adap_config_hma(adap);
4392 if (ret)
4393 dev_err(adap->pdev_dev,
4394 "HMA configuration failed with error %d\n",
4395 ret);
636f9d37
VP		 4396 dev_info(adap->pdev_dev, "Coming up as %s: "\
4397 "Adapter already initialized\n",
80f61f19 4398 adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE");
636f9d37
VP		 4399 } else {
4400 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4401 "Initializing adapter\n");
06640310
HS		 4402
4403 /* Find out whether we're dealing with a version of the
4404 * firmware which has configuration file support.
636f9d37 4405 */
06640310
HS		 4406 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4407 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
b2612722 4408 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
06640310 4409 params, val);
13ee15d3 4410
06640310
HS		 4411 /* If the firmware doesn't support Configuration Files,
4412 * return an error.
4413 */
4414 if (ret < 0) {
4415 dev_err(adap->pdev_dev, "firmware doesn't support "
4416 "Firmware Configuration Files\n");
4417 goto bye;
4418 }
4419
4420 /* The firmware provides us with a memory buffer where we can
4421 * load a Configuration File from the host if we want to
4422 * override the Configuration File in flash.
4423 */
4424 ret = adap_init0_config(adap, reset);
4425 if (ret == -ENOENT) {
4426 dev_err(adap->pdev_dev, "no Configuration File "
4427 "present on adapter.\n");
4428 goto bye;
636f9d37
VP		 4429 }
4430 if (ret < 0) {
06640310
HS		 4431 dev_err(adap->pdev_dev, "could not initialize "
4432 "adapter, error %d\n", -ret);
636f9d37
VP		 4433 goto bye;
4434 }
4435 }
4436
0eaec62a
CL		 4437 /* Now that we've successfully configured and initialized the adapter
4438 * (or found it already initialized), we can ask the Firmware what
4439 * resources it has provisioned for us.
4440 */
4441 ret = t4_get_pfres(adap);
4442 if (ret) {
4443 dev_err(adap->pdev_dev,
4444 "Unable to retrieve resource provisioning information\n");
4445 goto bye;
4446 }
4447
4448 /* Grab VPD parameters. This should be done after we establish a
4449 * connection to the firmware since some of the VPD parameters
4450 * (notably the Core Clock frequency) are retrieved via requests to
4451 * the firmware. On the other hand, we need these fairly early on
4452 * so we do this right after getting ahold of the firmware.
4453 *
4454 * We need to do this after initializing the adapter because someone
4455 * could have FLASHed a new VPD which won't be read by the firmware
4456 * until we do the RESET ...
4457 */
4458 ret = t4_get_vpd_params(adap, &adap->params.vpd);
4459 if (ret < 0)
4460 goto bye;
4461
4462 /* Find out what ports are available to us. Note that we need to do
4463 * this before calling adap_init0_no_config() since it needs nports
4464 * and portvec ...
4465 */
4466 v =
4467 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4468 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
4469 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
4470 if (ret < 0)
4471 goto bye;
4472
4473 adap->params.nports = hweight32(port_vec);
4474 adap->params.portvec = port_vec;
4475
06640310
HS		 4476 /* Give the SGE code a chance to pull in anything that it needs ...
4477 * Note that this must be called after we retrieve our VPD parameters
4478 * in order to know how to convert core ticks to seconds, etc.
636f9d37 4479 */
06640310
HS		 4480 ret = t4_sge_init(adap);
4481 if (ret < 0)
4482 goto bye;
636f9d37 4483
d429005f
VK		 4484 /* Grab the SGE Doorbell Queue Timer values. If successful, that
4485 * indicates that the Firmware and Hardware support this.
4486 */
543a1b85
VK		 4487 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4488 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
4489 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4490 1, params, val);
4491
4492 if (!ret) {
4493 adap->sge.dbqtimer_tick = val[0];
4494 ret = t4_read_sge_dbqtimers(adap,
4495 ARRAY_SIZE(adap->sge.dbqtimer_val),
4496 adap->sge.dbqtimer_val);
4497 }
4498
d429005f 4499 if (!ret)
80f61f19 4500 adap->flags |= CXGB4_SGE_DBQ_TIMER;
d429005f 4501
9a4da2cd
VP		 4502 if (is_bypass_device(adap->pdev->device))
4503 adap->params.bypass = 1;
4504
636f9d37
VP		 4505 /*
4506 * Grab some of our basic fundamental operating parameters.
4507 */
4508#define FW_PARAM_DEV(param) \
5167865a
HS		 4509 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
4510 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
636f9d37 4511
b8ff05a9 4512#define FW_PARAM_PFVF(param) \
5167865a
HS		 4513 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
4514 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
4515 FW_PARAMS_PARAM_Y_V(0) | \
4516 FW_PARAMS_PARAM_Z_V(0)
b8ff05a9 4517
636f9d37 4518 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 4519 params[1] = FW_PARAM_PFVF(L2T_START);
4520 params[2] = FW_PARAM_PFVF(L2T_END);
4521 params[3] = FW_PARAM_PFVF(FILTER_START);
4522 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 4523 params[5] = FW_PARAM_PFVF(IQFLINT_START);
b2612722 4524 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
b8ff05a9
DM		 4525 if (ret < 0)
4526 goto bye;
636f9d37
VP		 4527 adap->sge.egr_start = val[0];
4528 adap->l2t_start = val[1];
4529 adap->l2t_end = val[2];
b8ff05a9
DM		 4530 adap->tids.ftid_base = val[3];
4531 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 4532 adap->sge.ingr_start = val[5];
b8ff05a9 4533
0e249898
AV		 4534 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4535 /* Read the raw mps entries. In T6, the last 2 tcam entries
4536 * are reserved for raw mac addresses (rawf = 2, one per port).
4537 */
4538 params[0] = FW_PARAM_PFVF(RAWF_START);
4539 params[1] = FW_PARAM_PFVF(RAWF_END);
4540 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4541 params, val);
4542 if (ret == 0) {
4543 adap->rawf_start = val[0];
4544 adap->rawf_cnt = val[1] - val[0] + 1;
4545 }
4546 }
4547
4b8e27a8
HS		 4548 /* qids (ingress/egress) returned from firmware can be anywhere
4549 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4550 * Hence driver needs to allocate memory for this range to
4551 * store the queue info. Get the highest IQFLINT/EQ index returned
4552 * in FW_EQ_*_CMD.alloc command.
4553 */
4554 params[0] = FW_PARAM_PFVF(EQ_END);
4555 params[1] = FW_PARAM_PFVF(IQFLINT_END);
b2612722 4556 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4b8e27a8
HS		 4557 if (ret < 0)
4558 goto bye;
4559 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4560 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4561
4562 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4563 sizeof(*adap->sge.egr_map), GFP_KERNEL);
4564 if (!adap->sge.egr_map) {
4565 ret = -ENOMEM;
4566 goto bye;
4567 }
4568
4569 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4570 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4571 if (!adap->sge.ingr_map) {
4572 ret = -ENOMEM;
4573 goto bye;
4574 }
4575
4576 /* Allocate the memory for the vaious egress queue bitmaps
5b377d11 4577 * ie starving_fl, txq_maperr and blocked_fl.
4b8e27a8
HS		 4578 */
4579 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4580 sizeof(long), GFP_KERNEL);
4581 if (!adap->sge.starving_fl) {
4582 ret = -ENOMEM;
4583 goto bye;
4584 }
4585
4586 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4587 sizeof(long), GFP_KERNEL);
4588 if (!adap->sge.txq_maperr) {
4589 ret = -ENOMEM;
4590 goto bye;
4591 }
4592
5b377d11
HS		 4593#ifdef CONFIG_DEBUG_FS
4594 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4595 sizeof(long), GFP_KERNEL);
4596 if (!adap->sge.blocked_fl) {
4597 ret = -ENOMEM;
4598 goto bye;
4599 }
4600#endif
4601
b5a02f50
AB		 4602 params[0] = FW_PARAM_PFVF(CLIP_START);
4603 params[1] = FW_PARAM_PFVF(CLIP_END);
b2612722 4604 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
b5a02f50
AB		 4605 if (ret < 0)
4606 goto bye;
4607 adap->clipt_start = val[0];
4608 adap->clipt_end = val[1];
4609
b72a32da
RL		 4610 /* We don't yet have a PARAMs calls to retrieve the number of Traffic
4611 * Classes supported by the hardware/firmware so we hard code it here
4612 * for now.
4613 */
4614 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4615
636f9d37
VP		 4616 /* query params related to active filter region */
4617 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4618 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
b2612722 4619 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
636f9d37
VP		 4620 /* If Active filter size is set we enable establishing
4621 * offload connection through firmware work request
4622 */
4623 if ((val[0] != val[1]) && (ret >= 0)) {
80f61f19 4624 adap->flags |= CXGB4_FW_OFLD_CONN;
636f9d37
VP		 4625 adap->tids.aftid_base = val[0];
4626 adap->tids.aftid_end = val[1];
4627 }
4628
b407a4a9
VP		 4629 /* If we're running on newer firmware, let it know that we're
4630 * prepared to deal with encapsulated CPL messages. Older
4631 * firmware won't understand this and we'll just get
4632 * unencapsulated messages ...
4633 */
4634 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4635 val[0] = 1;
b2612722 4636 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
b407a4a9 4637
1ac0f095
KS		 4638 /*
4639 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4640 * capability. Earlier versions of the firmware didn't have the
4641 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4642 * permission to use ULPTX MEMWRITE DSGL.
4643 */
4644 if (is_t4(adap->params.chip)) {
4645 adap->params.ulptx_memwrite_dsgl = false;
4646 } else {
4647 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
b2612722 4648 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1ac0f095
KS		 4649 1, params, val);
4650 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4651 }
4652
086de575
SW		 4653 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4654 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4655 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4656 1, params, val);
4657 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4658
0ff90994
KS		 4659 /* See if FW supports FW_FILTER2 work request */
4660 if (is_t4(adap->params.chip)) {
4661 adap->params.filter2_wr_support = 0;
4662 } else {
4663 params[0] = FW_PARAM_DEV(FILTER2_WR);
4664 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4665 1, params, val);
4666 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4667 }
4668
02d805dc
SR		 4669 /* Check if FW supports returning vin and smt index.
4670 * If this is not supported, driver will interpret
4671 * these values from viid.
4672 */
4673 params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4674 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4675 1, params, val);
4676 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
4677
636f9d37
VP		 4678 /*
4679 * Get device capabilities so we can determine what resources we need
4680 * to manage.
4681 */
4682 memset(&caps_cmd, 0, sizeof(caps_cmd));
e2ac9628
HS		 4683 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4684 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 4685 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 4686 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4687 &caps_cmd);
4688 if (ret < 0)
4689 goto bye;
4690
74dd5aa1
VK		 4691 /* hash filter has some mandatory register settings to be tested and for
4692 * that it needs to test whether offload is enabled or not, hence
4693 * checking and setting it here.
4694 */
4695 if (caps_cmd.ofldcaps)
4696 adap->params.offload = 1;
4697
5c31254e
KS		 4698 if (caps_cmd.ofldcaps ||
4699 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) {
b8ff05a9
DM		 4700 /* query offload-related parameters */
4701 params[0] = FW_PARAM_DEV(NTID);
4702 params[1] = FW_PARAM_PFVF(SERVER_START);
4703 params[2] = FW_PARAM_PFVF(SERVER_END);
4704 params[3] = FW_PARAM_PFVF(TDDP_START);
4705 params[4] = FW_PARAM_PFVF(TDDP_END);
4706 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
b2612722 4707 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 4708 params, val);
b8ff05a9
DM		 4709 if (ret < 0)
4710 goto bye;
4711 adap->tids.ntids = val[0];
4712 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4713 adap->tids.stid_base = val[1];
4714 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37 4715 /*
dbedd44e 4716 * Setup server filter region. Divide the available filter
636f9d37
VP		 4717 * region into two parts. Regular filters get 1/3rd and server
4718 * filters get 2/3rd part. This is only enabled if workarond
4719 * path is enabled.
4720 * 1. For regular filters.
4721 * 2. Server filter: This are special filters which are used
4722 * to redirect SYN packets to offload queue.
4723 */
80f61f19 4724 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) {
636f9d37
VP		 4725 adap->tids.sftid_base = adap->tids.ftid_base +
4726 DIV_ROUND_UP(adap->tids.nftids, 3);
4727 adap->tids.nsftids = adap->tids.nftids -
4728 DIV_ROUND_UP(adap->tids.nftids, 3);
4729 adap->tids.nftids = adap->tids.sftid_base -
4730 adap->tids.ftid_base;
4731 }
b8ff05a9
DM		 4732 adap->vres.ddp.start = val[3];
4733 adap->vres.ddp.size = val[4] - val[3] + 1;
4734 adap->params.ofldq_wr_cred = val[5];
636f9d37 4735
5c31254e 4736 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
74dd5aa1 4737 init_hash_filter(adap);
5c31254e 4738 } else {
5c31254e
KS		 4739 adap->num_ofld_uld += 1;
4740 }
b8ff05a9 4741 }
636f9d37 4742 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 4743 params[0] = FW_PARAM_PFVF(STAG_START);
4744 params[1] = FW_PARAM_PFVF(STAG_END);
4745 params[2] = FW_PARAM_PFVF(RQ_START);
4746 params[3] = FW_PARAM_PFVF(RQ_END);
4747 params[4] = FW_PARAM_PFVF(PBL_START);
4748 params[5] = FW_PARAM_PFVF(PBL_END);
b2612722 4749 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 4750 params, val);
b8ff05a9
DM		 4751 if (ret < 0)
4752 goto bye;
4753 adap->vres.stag.start = val[0];
4754 adap->vres.stag.size = val[1] - val[0] + 1;
4755 adap->vres.rq.start = val[2];
4756 adap->vres.rq.size = val[3] - val[2] + 1;
4757 adap->vres.pbl.start = val[4];
4758 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab 4759
c68644ef
RR		 4760 params[0] = FW_PARAM_PFVF(SRQ_START);
4761 params[1] = FW_PARAM_PFVF(SRQ_END);
4762 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4763 params, val);
4764 if (!ret) {
4765 adap->vres.srq.start = val[0];
4766 adap->vres.srq.size = val[1] - val[0] + 1;
4767 }
4768 if (adap->vres.srq.size) {
4769 adap->srq = t4_init_srq(adap->vres.srq.size);
4770 if (!adap->srq)
4771 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4772 }
4773
a0881cab
DM		 4774 params[0] = FW_PARAM_PFVF(SQRQ_START);
4775 params[1] = FW_PARAM_PFVF(SQRQ_END);
4776 params[2] = FW_PARAM_PFVF(CQ_START);
4777 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 4778 params[4] = FW_PARAM_PFVF(OCQ_START);
4779 params[5] = FW_PARAM_PFVF(OCQ_END);
b2612722 4780 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
5c937dd3 4781 val);
a0881cab
DM		 4782 if (ret < 0)
4783 goto bye;
4784 adap->vres.qp.start = val[0];
4785 adap->vres.qp.size = val[1] - val[0] + 1;
4786 adap->vres.cq.start = val[2];
4787 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 4788 adap->vres.ocq.start = val[4];
4789 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS		 4790
4791 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4792 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
b2612722 4793 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
5c937dd3 4794 val);
4c2c5763
HS		 4795 if (ret < 0) {
4796 adap->params.max_ordird_qp = 8;
4797 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4798 ret = 0;
4799 } else {
4800 adap->params.max_ordird_qp = val[0];
4801 adap->params.max_ird_adapter = val[1];
4802 }
4803 dev_info(adap->pdev_dev,
4804 "max_ordird_qp %d max_ird_adapter %d\n",
4805 adap->params.max_ordird_qp,
4806 adap->params.max_ird_adapter);
43db9296
RR		 4807
4808 /* Enable write_with_immediate if FW supports it */
4809 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
4810 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4811 val);
4812 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
f3910c62
RR		 4813
4814 /* Enable write_cmpl if FW supports it */
4815 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
4816 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4817 val);
4818 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
0fbc81b3 4819 adap->num_ofld_uld += 2;
b8ff05a9 4820 }
636f9d37 4821 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 4822 params[0] = FW_PARAM_PFVF(ISCSI_START);
4823 params[1] = FW_PARAM_PFVF(ISCSI_END);
b2612722 4824 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
636f9d37 4825 params, val);
b8ff05a9
DM		 4826 if (ret < 0)
4827 goto bye;
4828 adap->vres.iscsi.start = val[0];
4829 adap->vres.iscsi.size = val[1] - val[0] + 1;
a248384e
VP		 4830 if (is_t6(adap->params.chip)) {
4831 params[0] = FW_PARAM_PFVF(PPOD_EDRAM_START);
4832 params[1] = FW_PARAM_PFVF(PPOD_EDRAM_END);
4833 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4834 params, val);
4835 if (!ret) {
4836 adap->vres.ppod_edram.start = val[0];
4837 adap->vres.ppod_edram.size =
4838 val[1] - val[0] + 1;
4839
4840 dev_info(adap->pdev_dev,
4841 "ppod edram start 0x%x end 0x%x size 0x%x\n",
4842 val[0], val[1],
4843 adap->vres.ppod_edram.size);
4844 }
4845 }
0fbc81b3
HS		 4846 /* LIO target and cxgb4i initiaitor */
4847 adap->num_ofld_uld += 2;
b8ff05a9 4848 }
94cdb8bb 4849 if (caps_cmd.cryptocaps) {
e383f248
AG		 4850 if (ntohs(caps_cmd.cryptocaps) &
4851 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) {
4852 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
4853 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4854 2, params, val);
4855 if (ret < 0) {
4856 if (ret != -EINVAL)
4857 goto bye;
4858 } else {
4859 adap->vres.ncrypto_fc = val[0];
4860 }
4861 adap->num_ofld_uld += 1;
4862 }
4863 if (ntohs(caps_cmd.cryptocaps) &
4864 FW_CAPS_CONFIG_TLS_INLINE) {
4865 params[0] = FW_PARAM_PFVF(TLS_START);
4866 params[1] = FW_PARAM_PFVF(TLS_END);
4867 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4868 2, params, val);
4869 if (ret < 0)
72a56ca9 4870 goto bye;
e383f248
AG		 4871 adap->vres.key.start = val[0];
4872 adap->vres.key.size = val[1] - val[0] + 1;
4873 adap->num_uld += 1;
72a56ca9 4874 }
a6ec572b 4875 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
94cdb8bb 4876 }
b8ff05a9
DM		 4877#undef FW_PARAM_PFVF
4878#undef FW_PARAM_DEV
4879
92e7ae71
HS		 4880 /* The MTU/MSS Table is initialized by now, so load their values. If
4881 * we're initializing the adapter, then we'll make any modifications
4882 * we want to the MTU/MSS Table and also initialize the congestion
4883 * parameters.
636f9d37 4884 */
b8ff05a9 4885 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 4886 if (state != DEV_STATE_INIT) {
4887 int i;
4888
4889 /* The default MTU Table contains values 1492 and 1500.
4890 * However, for TCP, it's better to have two values which are
4891 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4892 * This allows us to have a TCP Data Payload which is a
4893 * multiple of 8 regardless of what combination of TCP Options
4894 * are in use (always a multiple of 4 bytes) which is
4895 * important for performance reasons. For instance, if no
4896 * options are in use, then we have a 20-byte IP header and a
4897 * 20-byte TCP header. In this case, a 1500-byte MSS would
4898 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4899 * which is not a multiple of 8. So using an MSS of 1488 in
4900 * this case results in a TCP Data Payload of 1448 bytes which
4901 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4902 * Stamps have been negotiated, then an MTU of 1500 bytes
4903 * results in a TCP Data Payload of 1448 bytes which, as
4904 * above, is a multiple of 8 bytes ...
4905 */
4906 for (i = 0; i < NMTUS; i++)
4907 if (adap->params.mtus[i] == 1492) {
4908 adap->params.mtus[i] = 1488;
4909 break;
4910 }
7ee9ff94 4911
92e7ae71
HS		 4912 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4913 adap->params.b_wnd);
4914 }
df64e4d3 4915 t4_init_sge_params(adap);
80f61f19 4916 adap->flags |= CXGB4_FW_OK;
5ccf9d04 4917 t4_init_tp_params(adap, true);
b8ff05a9
DM		 4918 return 0;
4919
4920 /*
636f9d37
VP		 4921 * Something bad happened. If a command timed out or failed with EIO
4922 * FW does not operate within its spec or something catastrophic
4923 * happened to HW/FW, stop issuing commands.
b8ff05a9 4924 */
636f9d37 4925bye:
8b4e6b3c 4926 adap_free_hma_mem(adap);
4b8e27a8
HS		 4927 kfree(adap->sge.egr_map);
4928 kfree(adap->sge.ingr_map);
4929 kfree(adap->sge.starving_fl);
4930 kfree(adap->sge.txq_maperr);
5b377d11
HS		 4931#ifdef CONFIG_DEBUG_FS
4932 kfree(adap->sge.blocked_fl);
4933#endif
636f9d37
VP		 4934 if (ret != -ETIMEDOUT && ret != -EIO)
4935 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 4936 return ret;
4937}
4938
204dc3c0
DM		 4939/* EEH callbacks */
4940
4941static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4942 pci_channel_state_t state)
4943{
4944 int i;
4945 struct adapter *adap = pci_get_drvdata(pdev);
4946
4947 if (!adap)
4948 goto out;
4949
4950 rtnl_lock();
80f61f19 4951 adap->flags &= ~CXGB4_FW_OK;
204dc3c0 4952 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 4953 spin_lock(&adap->stats_lock);
204dc3c0
DM		 4954 for_each_port(adap, i) {
4955 struct net_device *dev = adap->port[i];
025d0973
GP		 4956 if (dev) {
4957 netif_device_detach(dev);
4958 netif_carrier_off(dev);
4959 }
204dc3c0 4960 }
9fe6cb58 4961 spin_unlock(&adap->stats_lock);
b37987e8 4962 disable_interrupts(adap);
80f61f19 4963 if (adap->flags & CXGB4_FULL_INIT_DONE)
204dc3c0
DM		 4964 cxgb_down(adap);
4965 rtnl_unlock();
80f61f19 4966 if ((adap->flags & CXGB4_DEV_ENABLED)) {
144be3d9 4967 pci_disable_device(pdev);
80f61f19 4968 adap->flags &= ~CXGB4_DEV_ENABLED;
144be3d9 4969 }
204dc3c0
DM		 4970out: return state == pci_channel_io_perm_failure ?
4971 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4972}
4973
4974static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4975{
4976 int i, ret;
4977 struct fw_caps_config_cmd c;
4978 struct adapter *adap = pci_get_drvdata(pdev);
4979
4980 if (!adap) {
4981 pci_restore_state(pdev);
4982 pci_save_state(pdev);
4983 return PCI_ERS_RESULT_RECOVERED;
4984 }
4985
80f61f19 4986 if (!(adap->flags & CXGB4_DEV_ENABLED)) {
144be3d9
GS		 4987 if (pci_enable_device(pdev)) {
4988 dev_err(&pdev->dev, "Cannot reenable PCI "
4989 "device after reset\n");
4990 return PCI_ERS_RESULT_DISCONNECT;
4991 }
80f61f19 4992 adap->flags |= CXGB4_DEV_ENABLED;
204dc3c0
DM		 4993 }
4994
4995 pci_set_master(pdev);
4996 pci_restore_state(pdev);
4997 pci_save_state(pdev);
204dc3c0 4998
8203b509 4999 if (t4_wait_dev_ready(adap->regs) < 0)
204dc3c0 5000 return PCI_ERS_RESULT_DISCONNECT;
b2612722 5001 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
204dc3c0 5002 return PCI_ERS_RESULT_DISCONNECT;
80f61f19 5003 adap->flags |= CXGB4_FW_OK;
204dc3c0
DM		 5004 if (adap_init1(adap, &c))
5005 return PCI_ERS_RESULT_DISCONNECT;
5006
5007 for_each_port(adap, i) {
02d805dc
SR		 5008 struct port_info *pi = adap2pinfo(adap, i);
5009 u8 vivld = 0, vin = 0;
204dc3c0 5010
02d805dc
SR		 5011 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
5012 NULL, NULL, &vivld, &vin);
204dc3c0
DM		 5013 if (ret < 0)
5014 return PCI_ERS_RESULT_DISCONNECT;
02d805dc
SR		 5015 pi->viid = ret;
5016 pi->xact_addr_filt = -1;
5017 /* If fw supports returning the VIN as part of FW_VI_CMD,
5018 * save the returned values.
5019 */
5020 if (adap->params.viid_smt_extn_support) {
5021 pi->vivld = vivld;
5022 pi->vin = vin;
5023 } else {
5024 /* Retrieve the values from VIID */
5025 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
5026 pi->vin = FW_VIID_VIN_G(pi->viid);
5027 }
204dc3c0
DM		 5028 }
5029
5030 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5031 adap->params.b_wnd);
1ae970e0 5032 setup_memwin(adap);
204dc3c0
DM		 5033 if (cxgb_up(adap))
5034 return PCI_ERS_RESULT_DISCONNECT;
5035 return PCI_ERS_RESULT_RECOVERED;
5036}
5037
5038static void eeh_resume(struct pci_dev *pdev)
5039{
5040 int i;
5041 struct adapter *adap = pci_get_drvdata(pdev);
5042
5043 if (!adap)
5044 return;
5045
5046 rtnl_lock();
5047 for_each_port(adap, i) {
5048 struct net_device *dev = adap->port[i];
025d0973
GP		 5049 if (dev) {
5050 if (netif_running(dev)) {
5051 link_start(dev);
5052 cxgb_set_rxmode(dev);
5053 }
5054 netif_device_attach(dev);
204dc3c0 5055 }
204dc3c0
DM		 5056 }
5057 rtnl_unlock();
5058}
5059
3646f0e5 5060static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 5061 .error_detected = eeh_err_detected,
5062 .slot_reset = eeh_slot_reset,
5063 .resume = eeh_resume,
5064};
5065
9b86a8d1
HS		 5066/* Return true if the Link Configuration supports "High Speeds" (those greater
5067 * than 1Gb/s).
5068 */
57d8b764 5069static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 5070{
9b86a8d1
HS		 5071 unsigned int speeds, high_speeds;
5072
c3168cab
GG		 5073 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
5074 high_speeds = speeds &
5075 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
9b86a8d1
HS		 5076
5077 return high_speeds != 0;
b8ff05a9
DM		 5078}
5079
b8ff05a9
DM		 5080/*
5081 * Perform default configuration of DMA queues depending on the number and type
5082 * of ports we found and the number of available CPUs. Most settings can be
5083 * modified by the admin prior to actual use.
5084 */
0eaec62a 5085static int cfg_queues(struct adapter *adap)
b8ff05a9
DM		 5086{
5087 struct sge *s = &adap->sge;
0eaec62a
CL		 5088 int i, n10g = 0, qidx = 0;
5089 int niqflint, neq, avail_eth_qsets;
5090 int max_eth_qsets = 32;
688848b1
AB		 5091#ifndef CONFIG_CHELSIO_T4_DCB
5092 int q10g = 0;
5093#endif
b8ff05a9 5094
94cdb8bb
HS		 5095 /* Reduce memory usage in kdump environment, disable all offload.
5096 */
85eacf3f 5097 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
0fbc81b3 5098 adap->params.offload = 0;
94cdb8bb
HS		 5099 adap->params.crypto = 0;
5100 }
5101
0eaec62a
CL		 5102 /* Calculate the number of Ethernet Queue Sets available based on
5103 * resources provisioned for us. We always have an Asynchronous
5104 * Firmware Event Ingress Queue. If we're operating in MSI or Legacy
5105 * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt
5106 * Ingress Queue. Meanwhile, we need two Egress Queues for each
5107 * Queue Set: one for the Free List and one for the Ethernet TX Queue.
5108 *
5109 * Note that we should also take into account all of the various
5110 * Offload Queues. But, in any situation where we're operating in
5111 * a Resource Constrained Provisioning environment, doing any Offload
5112 * at all is problematic ...
5113 */
5114 niqflint = adap->params.pfres.niqflint - 1;
80f61f19 5115 if (!(adap->flags & CXGB4_USING_MSIX))
0eaec62a
CL		 5116 niqflint--;
5117 neq = adap->params.pfres.neq / 2;
5118 avail_eth_qsets = min(niqflint, neq);
5119
5120 if (avail_eth_qsets > max_eth_qsets)
5121 avail_eth_qsets = max_eth_qsets;
5122
5123 if (avail_eth_qsets < adap->params.nports) {
5124 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n",
5125 avail_eth_qsets, adap->params.nports);
5126 return -ENOMEM;
5127 }
5128
5129 /* Count the number of 10Gb/s or better ports */
5130 for_each_port(adap, i)
5131 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
5132
688848b1
AB		 5133#ifdef CONFIG_CHELSIO_T4_DCB
5134 /* For Data Center Bridging support we need to be able to support up
5135 * to 8 Traffic Priorities; each of which will be assigned to its
5136 * own TX Queue in order to prevent Head-Of-Line Blocking.
5137 */
0eaec62a
CL		 5138 if (adap->params.nports * 8 > avail_eth_qsets) {
5139 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
5140 avail_eth_qsets, adap->params.nports * 8);
5141 return -ENOMEM;
688848b1 5142 }
b8ff05a9 5143
688848b1
AB		 5144 for_each_port(adap, i) {
5145 struct port_info *pi = adap2pinfo(adap, i);
5146
5147 pi->first_qset = qidx;
85eacf3f 5148 pi->nqsets = is_kdump_kernel() ? 1 : 8;
688848b1
AB		 5149 qidx += pi->nqsets;
5150 }
5151#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 5152 /*
5153 * We default to 1 queue per non-10G port and up to # of cores queues
5154 * per 10G port.
5155 */
5156 if (n10g)
0eaec62a 5157 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 5158 if (q10g > netif_get_num_default_rss_queues())
5159 q10g = netif_get_num_default_rss_queues();
b8ff05a9 5160
85eacf3f
GG		 5161 if (is_kdump_kernel())
5162 q10g = 1;
5163
b8ff05a9
DM		 5164 for_each_port(adap, i) {
5165 struct port_info *pi = adap2pinfo(adap, i);
5166
5167 pi->first_qset = qidx;
57d8b764 5168 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 5169 qidx += pi->nqsets;
5170 }
688848b1 5171#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 5172
5173 s->ethqsets = qidx;
5174 s->max_ethqsets = qidx; /* MSI-X may lower it later */
5175
0fbc81b3 5176 if (is_uld(adap)) {
b8ff05a9
DM		 5177 /*
5178 * For offload we use 1 queue/channel if all ports are up to 1G,
5179 * otherwise we divide all available queues amongst the channels
5180 * capped by the number of available cores.
5181 */
5182 if (n10g) {
a56177e1 5183 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
0fbc81b3
HS		 5184 s->ofldqsets = roundup(i, adap->params.nports);
5185 } else {
5186 s->ofldqsets = adap->params.nports;
5187 }
b8ff05a9
DM		 5188 }
5189
5190 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
5191 struct sge_eth_rxq *r = &s->ethrxq[i];
5192
c887ad0e 5193 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 5194 r->fl.size = 72;
5195 }
5196
5197 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
5198 s->ethtxq[i].q.size = 1024;
5199
5200 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
5201 s->ctrlq[i].q.size = 512;
5202
a4569504
AG		 5203 if (!is_t4(adap->params.chip))
5204 s->ptptxq.q.size = 8;
5205
c887ad0e 5206 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
0fbc81b3 5207 init_rspq(adap, &s->intrq, 0, 1, 512, 64);
0eaec62a
CL		 5208
5209 return 0;
b8ff05a9
DM		 5210}
5211
5212/*
5213 * Reduce the number of Ethernet queues across all ports to at most n.
5214 * n provides at least one queue per port.
5215 */
91744948 5216static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 5217{
5218 int i;
5219 struct port_info *pi;
5220
5221 while (n < adap->sge.ethqsets)
5222 for_each_port(adap, i) {
5223 pi = adap2pinfo(adap, i);
5224 if (pi->nqsets > 1) {
5225 pi->nqsets--;
5226 adap->sge.ethqsets--;
5227 if (adap->sge.ethqsets <= n)
5228 break;
5229 }
5230 }
5231
5232 n = 0;
5233 for_each_port(adap, i) {
5234 pi = adap2pinfo(adap, i);
5235 pi->first_qset = n;
5236 n += pi->nqsets;
5237 }
5238}
5239
94cdb8bb
HS		 5240static int get_msix_info(struct adapter *adap)
5241{
5242 struct uld_msix_info *msix_info;
0fbc81b3
HS		 5243 unsigned int max_ingq = 0;
5244
5245 if (is_offload(adap))
5246 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
5247 if (is_pci_uld(adap))
5248 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
5249
5250 if (!max_ingq)
5251 goto out;
94cdb8bb
HS		 5252
5253 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
5254 if (!msix_info)
5255 return -ENOMEM;
5256
5257 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
5258 sizeof(long), GFP_KERNEL);
5259 if (!adap->msix_bmap_ulds.msix_bmap) {
5260 kfree(msix_info);
5261 return -ENOMEM;
5262 }
5263 spin_lock_init(&adap->msix_bmap_ulds.lock);
5264 adap->msix_info_ulds = msix_info;
0fbc81b3 5265out:
94cdb8bb
HS		 5266 return 0;
5267}
5268
5269static void free_msix_info(struct adapter *adap)
5270{
0fbc81b3 5271 if (!(adap->num_uld && adap->num_ofld_uld))
94cdb8bb
HS		 5272 return;
5273
5274 kfree(adap->msix_info_ulds);
5275 kfree(adap->msix_bmap_ulds.msix_bmap);
5276}
5277
b8ff05a9
DM		 5278/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5279#define EXTRA_VECS 2
5280
91744948 5281static int enable_msix(struct adapter *adap)
b8ff05a9 5282{
94cdb8bb
HS		 5283 int ofld_need = 0, uld_need = 0;
5284 int i, j, want, need, allocated;
b8ff05a9
DM		 5285 struct sge *s = &adap->sge;
5286 unsigned int nchan = adap->params.nports;
f36e58e5 5287 struct msix_entry *entries;
94cdb8bb 5288 int max_ingq = MAX_INGQ;
f36e58e5 5289
0fbc81b3
HS		 5290 if (is_pci_uld(adap))
5291 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
5292 if (is_offload(adap))
5293 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
6da2ec56
KC		 5294 entries = kmalloc_array(max_ingq + 1, sizeof(*entries),
5295 GFP_KERNEL);
f36e58e5
HS		 5296 if (!entries)
5297 return -ENOMEM;
b8ff05a9 5298
94cdb8bb 5299 /* map for msix */
0fbc81b3
HS		 5300 if (get_msix_info(adap)) {
5301 adap->params.offload = 0;
94cdb8bb 5302 adap->params.crypto = 0;
0fbc81b3 5303 }
94cdb8bb
HS		 5304
5305 for (i = 0; i < max_ingq + 1; ++i)
b8ff05a9
DM		 5306 entries[i].entry = i;
5307
5308 want = s->max_ethqsets + EXTRA_VECS;
5309 if (is_offload(adap)) {
0fbc81b3
HS		 5310 want += adap->num_ofld_uld * s->ofldqsets;
5311 ofld_need = adap->num_ofld_uld * nchan;
b8ff05a9 5312 }
94cdb8bb 5313 if (is_pci_uld(adap)) {
0fbc81b3
HS		 5314 want += adap->num_uld * s->ofldqsets;
5315 uld_need = adap->num_uld * nchan;
94cdb8bb 5316 }
688848b1
AB		 5317#ifdef CONFIG_CHELSIO_T4_DCB
5318 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
5319 * each port.
5320 */
94cdb8bb 5321 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
688848b1 5322#else
94cdb8bb 5323 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
688848b1 5324#endif
f36e58e5
HS		 5325 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
5326 if (allocated < 0) {
5327 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
5328 " not using MSI-X\n");
5329 kfree(entries);
5330 return allocated;
5331 }
b8ff05a9 5332
f36e58e5 5333 /* Distribute available vectors to the various queue groups.
c32ad224
AG		 5334 * Every group gets its minimum requirement and NIC gets top
5335 * priority for leftovers.
5336 */
94cdb8bb 5337 i = allocated - EXTRA_VECS - ofld_need - uld_need;
c32ad224
AG		 5338 if (i < s->max_ethqsets) {
5339 s->max_ethqsets = i;
5340 if (i < s->ethqsets)
5341 reduce_ethqs(adap, i);
5342 }
0fbc81b3 5343 if (is_uld(adap)) {
94cdb8bb
HS		 5344 if (allocated < want)
5345 s->nqs_per_uld = nchan;
5346 else
0fbc81b3 5347 s->nqs_per_uld = s->ofldqsets;
94cdb8bb
HS		 5348 }
5349
0fbc81b3 5350 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
c32ad224 5351 adap->msix_info[i].vec = entries[i].vector;
0fbc81b3
HS		 5352 if (is_uld(adap)) {
5353 for (j = 0 ; i < allocated; ++i, j++) {
94cdb8bb 5354 adap->msix_info_ulds[j].vec = entries[i].vector;
0fbc81b3
HS		 5355 adap->msix_info_ulds[j].idx = i;
5356 }
94cdb8bb
HS		 5357 adap->msix_bmap_ulds.mapsize = j;
5358 }
43eb4e82 5359 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
0fbc81b3
HS		 5360 "nic %d per uld %d\n",
5361 allocated, s->max_ethqsets, s->nqs_per_uld);
c32ad224 5362
f36e58e5 5363 kfree(entries);
c32ad224 5364 return 0;
b8ff05a9
DM		 5365}
5366
5367#undef EXTRA_VECS
5368
91744948 5369static int init_rss(struct adapter *adap)
671b0060 5370{
c035e183
HS		 5371 unsigned int i;
5372 int err;
5373
5374 err = t4_init_rss_mode(adap, adap->mbox);
5375 if (err)
5376 return err;
671b0060
DM		 5377
5378 for_each_port(adap, i) {
5379 struct port_info *pi = adap2pinfo(adap, i);
5380
5381 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5382 if (!pi->rss)
5383 return -ENOMEM;
671b0060
DM		 5384 }
5385 return 0;
5386}
5387
0de72738
HS		 5388/* Dump basic information about the adapter */
5389static void print_adapter_info(struct adapter *adapter)
5390{
760446f9
GG		 5391 /* Hardware/Firmware/etc. Version/Revision IDs */
5392 t4_dump_version_info(adapter);
0de72738
HS		 5393
5394 /* Software/Hardware configuration */
5395 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5396 is_offload(adapter) ? "R" : "",
80f61f19
AV		 5397 ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
5398 (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
0de72738
HS		 5399 is_offload(adapter) ? "Offload" : "non-Offload");
5400}
5401
91744948 5402static void print_port_info(const struct net_device *dev)
b8ff05a9 5403{
b8ff05a9 5404 char buf[80];
118969ed 5405 char *bufp = buf;
118969ed
DM		 5406 const struct port_info *pi = netdev_priv(dev);
5407 const struct adapter *adap = pi->adapter;
f1a051b9 5408
c3168cab 5409 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5e78f7fd 5410 bufp += sprintf(bufp, "100M/");
c3168cab 5411 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5e78f7fd 5412 bufp += sprintf(bufp, "1G/");
c3168cab 5413 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
118969ed 5414 bufp += sprintf(bufp, "10G/");
c3168cab 5415 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
9b86a8d1 5416 bufp += sprintf(bufp, "25G/");
c3168cab 5417 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
72aca4bf 5418 bufp += sprintf(bufp, "40G/");
c3168cab
GG		 5419 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5420 bufp += sprintf(bufp, "50G/");
5421 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
9b86a8d1 5422 bufp += sprintf(bufp, "100G/");
c3168cab
GG		 5423 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5424 bufp += sprintf(bufp, "200G/");
5425 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5426 bufp += sprintf(bufp, "400G/");
118969ed
DM		 5427 if (bufp != buf)
5428 --bufp;
72aca4bf 5429 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed 5430
0de72738
HS		 5431 netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5432 dev->name, adap->params.vpd.id, adap->name, buf);
b8ff05a9
DM		 5433}
5434
06546391
DM		 5435/*
5436 * Free the following resources:
5437 * - memory used for tables
5438 * - MSI/MSI-X
5439 * - net devices
5440 * - resources FW is holding for us
5441 */
5442static void free_some_resources(struct adapter *adapter)
5443{
5444 unsigned int i;
5445
3bdb376e 5446 kvfree(adapter->smt);
752ade68 5447 kvfree(adapter->l2t);
c68644ef 5448 kvfree(adapter->srq);
b72a32da 5449 t4_cleanup_sched(adapter);
752ade68 5450 kvfree(adapter->tids.tid_tab);
e0f911c8 5451 cxgb4_cleanup_tc_flower(adapter);
d8931847 5452 cxgb4_cleanup_tc_u32(adapter);
4b8e27a8
HS		 5453 kfree(adapter->sge.egr_map);
5454 kfree(adapter->sge.ingr_map);
5455 kfree(adapter->sge.starving_fl);
5456 kfree(adapter->sge.txq_maperr);
5b377d11
HS		 5457#ifdef CONFIG_DEBUG_FS
5458 kfree(adapter->sge.blocked_fl);
5459#endif
06546391
DM		 5460 disable_msi(adapter);
5461
5462 for_each_port(adapter, i)
671b0060 5463 if (adapter->port[i]) {
4f3a0fcf
HS		 5464 struct port_info *pi = adap2pinfo(adapter, i);
5465
5466 if (pi->viid != 0)
5467 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5468 0, pi->viid);
671b0060 5469 kfree(adap2pinfo(adapter, i)->rss);
06546391 5470 free_netdev(adapter->port[i]);
671b0060 5471 }
80f61f19 5472 if (adapter->flags & CXGB4_FW_OK)
b2612722 5473 t4_fw_bye(adapter, adapter->pf);
06546391
DM		 5474}
5475
2ed28baa 5476#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 5477#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
012475e3 5478 NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 5479#define SEGMENT_SIZE 128
b8ff05a9 5480
e8d45292 5481static int t4_get_chip_type(struct adapter *adap, int ver)
d86bd29e 5482{
e8d45292 5483 u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
46cdc9be 5484
e8d45292 5485 switch (ver) {
d86bd29e 5486 case CHELSIO_T4:
46cdc9be 5487 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
d86bd29e 5488 case CHELSIO_T5:
46cdc9be 5489 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
d86bd29e 5490 case CHELSIO_T6:
46cdc9be 5491 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
d86bd29e 5492 default:
e8d45292 5493 break;
d86bd29e 5494 }
46cdc9be 5495 return -EINVAL;
d86bd29e
HS		 5496}
5497
b6244201 5498#ifdef CONFIG_PCI_IOV
baf50868 5499static void cxgb4_mgmt_setup(struct net_device *dev)
e7b48a32
HS		 5500{
5501 dev->type = ARPHRD_NONE;
5502 dev->mtu = 0;
5503 dev->hard_header_len = 0;
5504 dev->addr_len = 0;
5505 dev->tx_queue_len = 0;
5506 dev->flags |= IFF_NOARP;
5507 dev->priv_flags |= IFF_NO_QUEUE;
5508
5509 /* Initialize the device structure. */
5510 dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5511 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
e7b48a32
HS		 5512}
5513
b6244201
HS		 5514static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5515{
7829451c 5516 struct adapter *adap = pci_get_drvdata(pdev);
b6244201
HS		 5517 int err = 0;
5518 int current_vfs = pci_num_vf(pdev);
5519 u32 pcie_fw;
b6244201 5520
7829451c 5521 pcie_fw = readl(adap->regs + PCIE_FW_A);
7cfac881
AV		 5522 /* Check if fw is initialized */
5523 if (!(pcie_fw & PCIE_FW_INIT_F)) {
5524 dev_warn(&pdev->dev, "Device not initialized\n");
b6244201
HS		 5525 return -EOPNOTSUPP;
5526 }
5527
5528 /* If any of the VF's is already assigned to Guest OS, then
5529 * SRIOV for the same cannot be modified
5530 */
5531 if (current_vfs && pci_vfs_assigned(pdev)) {
5532 dev_err(&pdev->dev,
5533 "Cannot modify SR-IOV while VFs are assigned\n");
baf50868 5534 return current_vfs;
b6244201 5535 }
baf50868
GG		 5536 /* Note that the upper-level code ensures that we're never called with
5537 * a non-zero "num_vfs" when we already have VFs instantiated. But
5538 * it never hurts to code defensively.
b6244201 5539 */
baf50868
GG		 5540 if (num_vfs != 0 && current_vfs != 0)
5541 return -EBUSY;
5542
5543 /* Nothing to do for no change. */
5544 if (num_vfs == current_vfs)
5545 return num_vfs;
5546
5547 /* Disable SRIOV when zero is passed. */
b6244201
HS		 5548 if (!num_vfs) {
5549 pci_disable_sriov(pdev);
baf50868
GG		 5550 /* free VF Management Interface */
5551 unregister_netdev(adap->port[0]);
5552 free_netdev(adap->port[0]);
5553 adap->port[0] = NULL;
5554
661dbeb9 5555 /* free VF resources */
baf50868 5556 adap->num_vfs = 0;
661dbeb9
HS		 5557 kfree(adap->vfinfo);
5558 adap->vfinfo = NULL;
baf50868 5559 return 0;
b6244201
HS		 5560 }
5561
baf50868
GG		 5562 if (!current_vfs) {
5563 struct fw_pfvf_cmd port_cmd, port_rpl;
5564 struct net_device *netdev;
5565 unsigned int pmask, port;
5566 struct pci_dev *pbridge;
5567 struct port_info *pi;
5568 char name[IFNAMSIZ];
5569 u32 devcap2;
5570 u16 flags;
5571 int pos;
5572
5573 /* If we want to instantiate Virtual Functions, then our
5574 * parent bridge's PCI-E needs to support Alternative Routing
5575 * ID (ARI) because our VFs will show up at function offset 8
5576 * and above.
5577 */
5578 pbridge = pdev->bus->self;
5579 pos = pci_find_capability(pbridge, PCI_CAP_ID_EXP);
5580 pci_read_config_word(pbridge, pos + PCI_EXP_FLAGS, &flags);
5581 pci_read_config_dword(pbridge, pos + PCI_EXP_DEVCAP2, &devcap2);
5582
5583 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5584 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5585 /* Our parent bridge does not support ARI so issue a
5586 * warning and skip instantiating the VFs. They
5587 * won't be reachable.
5588 */
5589 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5590 pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5591 PCI_FUNC(pbridge->devfn));
5592 return -ENOTSUPP;
5593 }
5594 memset(&port_cmd, 0, sizeof(port_cmd));
5595 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
5596 FW_CMD_REQUEST_F |
5597 FW_CMD_READ_F |
5598 FW_PFVF_CMD_PFN_V(adap->pf) |
5599 FW_PFVF_CMD_VFN_V(0));
5600 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
5601 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
5602 &port_rpl);
b6244201
HS		 5603 if (err)
5604 return err;
baf50868
GG		 5605 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
5606 port = ffs(pmask) - 1;
5607 /* Allocate VF Management Interface. */
5608 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
5609 adap->pf);
5610 netdev = alloc_netdev(sizeof(struct port_info),
5611 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
5612 if (!netdev)
5613 return -ENOMEM;
7829451c 5614
baf50868
GG		 5615 pi = netdev_priv(netdev);
5616 pi->adapter = adap;
5617 pi->lport = port;
5618 pi->tx_chan = port;
5619 SET_NETDEV_DEV(netdev, &pdev->dev);
5620
5621 adap->port[0] = netdev;
5622 pi->port_id = 0;
5623
5624 err = register_netdev(adap->port[0]);
5625 if (err) {
5626 pr_info("Unable to register VF mgmt netdev %s\n", name);
5627 free_netdev(adap->port[0]);
5628 adap->port[0] = NULL;
e7b48a32 5629 return err;
baf50868
GG		 5630 }
5631 /* Allocate and set up VF Information. */
5632 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
5633 sizeof(struct vf_info), GFP_KERNEL);
5634 if (!adap->vfinfo) {
5635 unregister_netdev(adap->port[0]);
5636 free_netdev(adap->port[0]);
5637 adap->port[0] = NULL;
5638 return -ENOMEM;
5639 }
5640 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
5641 }
5642 /* Instantiate the requested number of VFs. */
5643 err = pci_enable_sriov(pdev, num_vfs);
5644 if (err) {
5645 pr_info("Unable to instantiate %d VFs\n", num_vfs);
5646 if (!current_vfs) {
5647 unregister_netdev(adap->port[0]);
5648 free_netdev(adap->port[0]);
5649 adap->port[0] = NULL;
5650 kfree(adap->vfinfo);
5651 adap->vfinfo = NULL;
5652 }
5653 return err;
b6244201 5654 }
661dbeb9 5655
baf50868 5656 adap->num_vfs = num_vfs;
b6244201
HS		 5657 return num_vfs;
5658}
baf50868 5659#endif /* CONFIG_PCI_IOV */
b6244201 5660
1dd06ae8 5661static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 5662{
e8d45292
GG		 5663 struct net_device *netdev;
5664 struct adapter *adapter;
5665 static int adap_idx = 1;
5666 int s_qpp, qpp, num_seg;
b8ff05a9 5667 struct port_info *pi;
c8f44aff 5668 bool highdma = false;
d86bd29e 5669 enum chip_type chip;
e8d45292
GG		 5670 void __iomem *regs;
5671 int func, chip_ver;
5672 u16 device_id;
5673 int i, err;
5674 u32 whoami;
b8ff05a9
DM		 5675
5676 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
5677
5678 err = pci_request_regions(pdev, KBUILD_MODNAME);
5679 if (err) {
5680 /* Just info, some other driver may have claimed the device. */
5681 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
5682 return err;
5683 }
5684
b8ff05a9
DM		 5685 err = pci_enable_device(pdev);
5686 if (err) {
5687 dev_err(&pdev->dev, "cannot enable PCI device\n");
5688 goto out_release_regions;
5689 }
5690
d6ce2628
HS		 5691 regs = pci_ioremap_bar(pdev, 0);
5692 if (!regs) {
5693 dev_err(&pdev->dev, "cannot map device registers\n");
5694 err = -ENOMEM;
5695 goto out_disable_device;
5696 }
5697
baf50868
GG		 5698 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5699 if (!adapter) {
5700 err = -ENOMEM;
5701 goto out_unmap_bar0;
5702 }
5703
5704 adapter->regs = regs;
8203b509
HS		 5705 err = t4_wait_dev_ready(regs);
5706 if (err < 0)
e729452e 5707 goto out_free_adapter;
8203b509 5708
d6ce2628 5709 /* We control everything through one PF */
e8d45292
GG		 5710 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5711 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
5712 chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
5713 if (chip < 0) {
5714 dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
5715 err = chip;
5716 goto out_free_adapter;
5717 }
5718 chip_ver = CHELSIO_CHIP_VERSION(chip);
5719 func = chip_ver <= CHELSIO_T5 ?
5720 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
baf50868
GG		 5721
5722 adapter->pdev = pdev;
5723 adapter->pdev_dev = &pdev->dev;
5724 adapter->name = pci_name(pdev);
5725 adapter->mbox = func;
5726 adapter->pf = func;
016764de
GG		 5727 adapter->params.chip = chip;
5728 adapter->adap_idx = adap_idx;
baf50868
GG		 5729 adapter->msg_enable = DFLT_MSG_ENABLE;
5730 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5731 (sizeof(struct mbox_cmd) *
5732 T4_OS_LOG_MBOX_CMDS),
5733 GFP_KERNEL);
5734 if (!adapter->mbox_log) {
5735 err = -ENOMEM;
5736 goto out_free_adapter;
5737 }
5738 spin_lock_init(&adapter->mbox_lock);
5739 INIT_LIST_HEAD(&adapter->mlist.list);
aca06eaf 5740 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
baf50868
GG		 5741 pci_set_drvdata(pdev, adapter);
5742
d6ce2628 5743 if (func != ent->driver_data) {
d6ce2628
HS		 5744 pci_disable_device(pdev);
5745 pci_save_state(pdev); /* to restore SR-IOV later */
baf50868 5746 return 0;
d6ce2628
HS		 5747 }
5748
b8ff05a9 5749 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 5750 highdma = true;
b8ff05a9
DM		 5751 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
5752 if (err) {
5753 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
5754 "coherent allocations\n");
baf50868 5755 goto out_free_adapter;
b8ff05a9
DM		 5756 }
5757 } else {
5758 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5759 if (err) {
5760 dev_err(&pdev->dev, "no usable DMA configuration\n");
baf50868 5761 goto out_free_adapter;
b8ff05a9
DM		 5762 }
5763 }
5764
5765 pci_enable_pcie_error_reporting(pdev);
5766 pci_set_master(pdev);
5767 pci_save_state(pdev);
7829451c 5768 adap_idx++;
29aaee65
AB		 5769 adapter->workq = create_singlethread_workqueue("cxgb4");
5770 if (!adapter->workq) {
5771 err = -ENOMEM;
5772 goto out_free_adapter;
5773 }
5774
144be3d9 5775 /* PCI device has been enabled */
80f61f19 5776 adapter->flags |= CXGB4_DEV_ENABLED;
b8ff05a9
DM		 5777 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
5778
b0ba9d5f
CL		 5779 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
5780 * Ingress Packet Data to Free List Buffers in order to allow for
5781 * chipset performance optimizations between the Root Complex and
5782 * Memory Controllers. (Messages to the associated Ingress Queue
5783 * notifying new Packet Placement in the Free Lists Buffers will be
5784 * send without the Relaxed Ordering Attribute thus guaranteeing that
5785 * all preceding PCIe Transaction Layer Packets will be processed
5786 * first.) But some Root Complexes have various issues with Upstream
5787 * Transaction Layer Packets with the Relaxed Ordering Attribute set.
5788 * The PCIe devices which under the Root Complexes will be cleared the
5789 * Relaxed Ordering bit in the configuration space, So we check our
5790 * PCIe configuration space to see if it's flagged with advice against
5791 * using Relaxed Ordering.
5792 */
5793 if (!pcie_relaxed_ordering_enabled(pdev))
80f61f19 5794 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
b0ba9d5f 5795
b8ff05a9
DM		 5796 spin_lock_init(&adapter->stats_lock);
5797 spin_lock_init(&adapter->tid_release_lock);
e327c225 5798 spin_lock_init(&adapter->win0_lock);
b8ff05a9
DM		 5799
5800 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 5801 INIT_WORK(&adapter->db_full_task, process_db_full);
5802 INIT_WORK(&adapter->db_drop_task, process_db_drop);
8b7372c1 5803 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
b8ff05a9
DM		 5804
5805 err = t4_prep_adapter(adapter);
5806 if (err)
d6ce2628
HS		 5807 goto out_free_adapter;
5808
1dde532d
RL		 5809 if (is_kdump_kernel()) {
5810 /* Collect hardware state and append to /proc/vmcore */
5811 err = cxgb4_cudbg_vmcore_add_dump(adapter);
5812 if (err) {
5813 dev_warn(adapter->pdev_dev,
5814 "Fail collecting vmcore device dump, err: %d. Continuing\n",
5815 err);
5816 err = 0;
5817 }
5818 }
22adfe0a 5819
d14807dd 5820 if (!is_t4(adapter->params.chip)) {
f612b815
HS		 5821 s_qpp = (QUEUESPERPAGEPF0_S +
5822 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
b2612722 5823 adapter->pf);
f612b815
HS		 5824 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
5825 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
22adfe0a
SR		 5826 num_seg = PAGE_SIZE / SEGMENT_SIZE;
5827
5828 /* Each segment size is 128B. Write coalescing is enabled only
5829 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
5830 * queue is less no of segments that can be accommodated in
5831 * a page size.
5832 */
5833 if (qpp > num_seg) {
5834 dev_err(&pdev->dev,
5835 "Incorrect number of egress queues per page\n");
5836 err = -EINVAL;
d6ce2628 5837 goto out_free_adapter;
22adfe0a
SR		 5838 }
5839 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
5840 pci_resource_len(pdev, 2));
5841 if (!adapter->bar2) {
5842 dev_err(&pdev->dev, "cannot map device bar2 region\n");
5843 err = -ENOMEM;
d6ce2628 5844 goto out_free_adapter;
22adfe0a
SR		 5845 }
5846 }
5847
636f9d37 5848 setup_memwin(adapter);
b8ff05a9 5849 err = adap_init0(adapter);
5b377d11
HS		 5850#ifdef CONFIG_DEBUG_FS
5851 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
5852#endif
636f9d37 5853 setup_memwin_rdma(adapter);
b8ff05a9
DM		 5854 if (err)
5855 goto out_unmap_bar;
5856
2a485cf7
HS		 5857 /* configure SGE_STAT_CFG_A to read WC stats */
5858 if (!is_t4(adapter->params.chip))
676d6a75
HS		 5859 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
5860 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
5861 T6_STATMODE_V(0)));
2a485cf7 5862
b539ea60
AV		 5863 /* Initialize hash mac addr list */
5864 INIT_LIST_HEAD(&adapter->mac_hlist);
5865
b8ff05a9 5866 for_each_port(adapter, i) {
b8ff05a9
DM		 5867 netdev = alloc_etherdev_mq(sizeof(struct port_info),
5868 MAX_ETH_QSETS);
5869 if (!netdev) {
5870 err = -ENOMEM;
5871 goto out_free_dev;
5872 }
5873
5874 SET_NETDEV_DEV(netdev, &pdev->dev);
5875
5876 adapter->port[i] = netdev;
5877 pi = netdev_priv(netdev);
5878 pi->adapter = adapter;
5879 pi->xact_addr_filt = -1;
b8ff05a9 5880 pi->port_id = i;
b8ff05a9
DM		 5881 netdev->irq = pdev->irq;
5882
2ed28baa
MM		 5883 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5884 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
012475e3 5885 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO |
d8931847
RL		 5886 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
5887 NETIF_F_HW_TC;
d0a1299c 5888
e8d45292 5889 if (chip_ver > CHELSIO_T5) {
c50ae55e
GG		 5890 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
5891 NETIF_F_IPV6_CSUM |
5892 NETIF_F_RXCSUM |
5893 NETIF_F_GSO_UDP_TUNNEL |
64f40cdd 5894 NETIF_F_GSO_UDP_TUNNEL_CSUM |
c50ae55e
GG		 5895 NETIF_F_TSO | NETIF_F_TSO6;
5896
1435d997 5897 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
64f40cdd 5898 NETIF_F_GSO_UDP_TUNNEL_CSUM |
1435d997 5899 NETIF_F_HW_TLS_RECORD;
c50ae55e 5900 }
d0a1299c 5901
c8f44aff
MM		 5902 if (highdma)
5903 netdev->hw_features |= NETIF_F_HIGHDMA;
5904 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 5905 netdev->vlan_features = netdev->features & VLAN_FEAT;
5906
01789349
JP		 5907 netdev->priv_flags |= IFF_UNICAST_FLT;
5908
d894be57 5909 /* MTU range: 81 - 9600 */
a047fbae 5910 netdev->min_mtu = 81; /* accommodate SACK */
d894be57
JW		 5911 netdev->max_mtu = MAX_MTU;
5912
b8ff05a9 5913 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 5914#ifdef CONFIG_CHELSIO_T4_DCB
5915 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5916 cxgb4_dcb_state_init(netdev);
ebddd97a 5917 cxgb4_dcb_version_init(netdev);
688848b1 5918#endif
812034f1 5919 cxgb4_set_ethtool_ops(netdev);
b8ff05a9
DM		 5920 }
5921
ad75b7d3
RL		 5922 cxgb4_init_ethtool_dump(adapter);
5923
b8ff05a9
DM		 5924 pci_set_drvdata(pdev, adapter);
5925
80f61f19 5926 if (adapter->flags & CXGB4_FW_OK) {
060e0c75 5927 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 5928 if (err)
5929 goto out_free_dev;
098ef6c2
HS		 5930 } else if (adapter->params.nports == 1) {
5931 /* If we don't have a connection to the firmware -- possibly
5932 * because of an error -- grab the raw VPD parameters so we
5933 * can set the proper MAC Address on the debug network
5934 * interface that we've created.
5935 */
5936 u8 hw_addr[ETH_ALEN];
5937 u8 *na = adapter->params.vpd.na;
5938
5939 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5940 if (!err) {
5941 for (i = 0; i < ETH_ALEN; i++)
5942 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5943 hex2val(na[2 * i + 1]));
5944 t4_set_hw_addr(adapter, 0, hw_addr);
5945 }
b8ff05a9
DM		 5946 }
5947
80f61f19 5948 if (!(adapter->flags & CXGB4_FW_OK))
0eaec62a
CL		 5949 goto fw_attach_fail;
5950
098ef6c2 5951 /* Configure queues and allocate tables now, they can be needed as
b8ff05a9
DM		 5952 * soon as the first register_netdev completes.
5953 */
0eaec62a
CL		 5954 err = cfg_queues(adapter);
5955 if (err)
5956 goto out_free_dev;
b8ff05a9 5957
3bdb376e
KS		 5958 adapter->smt = t4_init_smt();
5959 if (!adapter->smt) {
5960 /* We tolerate a lack of SMT, giving up some functionality */
5961 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
5962 }
5963
5be9ed8d 5964 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
b8ff05a9
DM		 5965 if (!adapter->l2t) {
5966 /* We tolerate a lack of L2T, giving up some functionality */
5967 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5968 adapter->params.offload = 0;
5969 }
5970
b5a02f50 5971#if IS_ENABLED(CONFIG_IPV6)
e8d45292 5972 if (chip_ver <= CHELSIO_T5 &&
eb72f74f
HS		 5973 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5974 /* CLIP functionality is not present in hardware,
5975 * hence disable all offload features
b5a02f50
AB		 5976 */
5977 dev_warn(&pdev->dev,
eb72f74f 5978 "CLIP not enabled in hardware, continuing\n");
b5a02f50 5979 adapter->params.offload = 0;
eb72f74f
HS		 5980 } else {
5981 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5982 adapter->clipt_end);
5983 if (!adapter->clipt) {
5984 /* We tolerate a lack of clip_table, giving up
5985 * some functionality
5986 */
5987 dev_warn(&pdev->dev,
5988 "could not allocate Clip table, continuing\n");
5989 adapter->params.offload = 0;
5990 }
b5a02f50
AB		 5991 }
5992#endif
b72a32da
RL		 5993
5994 for_each_port(adapter, i) {
5995 pi = adap2pinfo(adapter, i);
5996 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5997 if (!pi->sched_tbl)
5998 dev_warn(&pdev->dev,
5999 "could not activate scheduling on port %d\n",
6000 i);
6001 }
6002
578b46b9 6003 if (tid_init(&adapter->tids) < 0) {
b8ff05a9
DM		 6004 dev_warn(&pdev->dev, "could not allocate TID table, "
6005 "continuing\n");
6006 adapter->params.offload = 0;
d8931847 6007 } else {
45da1ca2 6008 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
d8931847
RL		 6009 if (!adapter->tc_u32)
6010 dev_warn(&pdev->dev,
6011 "could not offload tc u32, continuing\n");
62488e4b 6012
79e6d46a
KS		 6013 if (cxgb4_init_tc_flower(adapter))
6014 dev_warn(&pdev->dev,
6015 "could not offload tc flower, continuing\n");
b8ff05a9
DM		 6016 }
6017
5c31254e 6018 if (is_offload(adapter) || is_hashfilter(adapter)) {
9a1bb9f6
HS		 6019 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
6020 u32 hash_base, hash_reg;
6021
dfecc759 6022 if (chip_ver <= CHELSIO_T5) {
9a1bb9f6
HS		 6023 hash_reg = LE_DB_TID_HASHBASE_A;
6024 hash_base = t4_read_reg(adapter, hash_reg);
6025 adapter->tids.hash_base = hash_base / 4;
6026 } else {
6027 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
6028 hash_base = t4_read_reg(adapter, hash_reg);
6029 adapter->tids.hash_base = hash_base;
6030 }
6031 }
6032 }
6033
f7cabcdd
DM		 6034 /* See what interrupts we'll be using */
6035 if (msi > 1 && enable_msix(adapter) == 0)
80f61f19 6036 adapter->flags |= CXGB4_USING_MSIX;
94cdb8bb 6037 else if (msi > 0 && pci_enable_msi(pdev) == 0) {
80f61f19 6038 adapter->flags |= CXGB4_USING_MSI;
94cdb8bb
HS		 6039 if (msi > 1)
6040 free_msix_info(adapter);
6041 }
f7cabcdd 6042
547fd272 6043 /* check for PCI Express bandwidth capabiltites */
57d12fc6 6044 pcie_print_link_status(pdev);
547fd272 6045
28b38705
RR		 6046 cxgb4_init_mps_ref_entries(adapter);
6047
671b0060
DM		 6048 err = init_rss(adapter);
6049 if (err)
6050 goto out_free_dev;
6051
843bd7db
AV		 6052 err = setup_fw_sge_queues(adapter);
6053 if (err) {
6054 dev_err(adapter->pdev_dev,
6055 "FW sge queue allocation failed, err %d", err);
6056 goto out_free_dev;
6057 }
6058
0eaec62a 6059fw_attach_fail:
b8ff05a9
DM		 6060 /*
6061 * The card is now ready to go. If any errors occur during device
6062 * registration we do not fail the whole card but rather proceed only
6063 * with the ports we manage to register successfully. However we must
6064 * register at least one net device.
6065 */
6066 for_each_port(adapter, i) {
a57cabe0 6067 pi = adap2pinfo(adapter, i);
d2a007ab 6068 adapter->port[i]->dev_port = pi->lport;
a57cabe0
DM		 6069 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6070 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6071
b1a73af9
SM		 6072 netif_carrier_off(adapter->port[i]);
6073
b8ff05a9
DM		 6074 err = register_netdev(adapter->port[i]);
6075 if (err)
b1a3c2b6 6076 break;
b1a3c2b6
DM		 6077 adapter->chan_map[pi->tx_chan] = i;
6078 print_port_info(adapter->port[i]);
b8ff05a9 6079 }
b1a3c2b6 6080 if (i == 0) {
b8ff05a9
DM		 6081 dev_err(&pdev->dev, "could not register any net devices\n");
6082 goto out_free_dev;
6083 }
b1a3c2b6
DM		 6084 if (err) {
6085 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6086 err = 0;
6403eab1 6087 }
b8ff05a9
DM		 6088
6089 if (cxgb4_debugfs_root) {
6090 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6091 cxgb4_debugfs_root);
6092 setup_debugfs(adapter);
6093 }
6094
6482aa7c
DLR		 6095 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6096 pdev->needs_freset = 1;
6097
0fbc81b3
HS		 6098 if (is_uld(adapter)) {
6099 mutex_lock(&uld_mutex);
6100 list_add_tail(&adapter->list_node, &adapter_list);
6101 mutex_unlock(&uld_mutex);
6102 }
b8ff05a9 6103
9c33e420
AG		 6104 if (!is_t4(adapter->params.chip))
6105 cxgb4_ptp_init(adapter);
6106
ebcd210e 6107 if (IS_REACHABLE(CONFIG_THERMAL) &&
80f61f19 6108 !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK))
b1871915 6109 cxgb4_thermal_init(adapter);
b1871915 6110
0de72738 6111 print_adapter_info(adapter);
7829451c 6112 return 0;
0de72738 6113
b8ff05a9 6114 out_free_dev:
843bd7db 6115 t4_free_sge_resources(adapter);
06546391 6116 free_some_resources(adapter);
80f61f19 6117 if (adapter->flags & CXGB4_USING_MSIX)
94cdb8bb 6118 free_msix_info(adapter);
0fbc81b3
HS		 6119 if (adapter->num_uld || adapter->num_ofld_uld)
6120 t4_uld_mem_free(adapter);
b8ff05a9 6121 out_unmap_bar:
d14807dd 6122 if (!is_t4(adapter->params.chip))
22adfe0a 6123 iounmap(adapter->bar2);
b8ff05a9 6124 out_free_adapter:
29aaee65
AB		 6125 if (adapter->workq)
6126 destroy_workqueue(adapter->workq);
6127
7f080c3f 6128 kfree(adapter->mbox_log);
b8ff05a9 6129 kfree(adapter);
d6ce2628
HS		 6130 out_unmap_bar0:
6131 iounmap(regs);
b8ff05a9
DM		 6132 out_disable_device:
6133 pci_disable_pcie_error_reporting(pdev);
6134 pci_disable_device(pdev);
6135 out_release_regions:
6136 pci_release_regions(pdev);
b8ff05a9
DM		 6137 return err;
6138}
6139
91744948 6140static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 6141{
6142 struct adapter *adapter = pci_get_drvdata(pdev);
b539ea60 6143 struct hash_mac_addr *entry, *tmp;
b8ff05a9 6144
7829451c
HS		 6145 if (!adapter) {
6146 pci_release_regions(pdev);
6147 return;
6148 }
636f9d37 6149
b1a79360
VK		 6150 /* If we allocated filters, free up state associated with any
6151 * valid filters ...
6152 */
6153 clear_all_filters(adapter);
6154
80f61f19 6155 adapter->flags |= CXGB4_SHUTTING_DOWN;
e1f6198e 6156
7829451c 6157 if (adapter->pf == 4) {
b8ff05a9
DM		 6158 int i;
6159
29aaee65
AB		 6160 /* Tear down per-adapter Work Queue first since it can contain
6161 * references to our adapter data structure.
6162 */
6163 destroy_workqueue(adapter->workq);
6164
6a146f3a 6165 if (is_uld(adapter)) {
b8ff05a9 6166 detach_ulds(adapter);
6a146f3a
GP		 6167 t4_uld_clean_up(adapter);
6168 }
b8ff05a9 6169
8b4e6b3c
AV		 6170 adap_free_hma_mem(adapter);
6171
b37987e8
HS		 6172 disable_interrupts(adapter);
6173
28b38705
RR		 6174 cxgb4_free_mps_ref_entries(adapter);
6175
b8ff05a9 6176 for_each_port(adapter, i)
8f3a7676 6177 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 6178 unregister_netdev(adapter->port[i]);
6179
9f16dc2e 6180 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 6181
9c33e420
AG		 6182 if (!is_t4(adapter->params.chip))
6183 cxgb4_ptp_stop(adapter);
ebcd210e 6184 if (IS_REACHABLE(CONFIG_THERMAL))
e70a57fa 6185 cxgb4_thermal_remove(adapter);
9c33e420 6186
80f61f19 6187 if (adapter->flags & CXGB4_FULL_INIT_DONE)
aaefae9b 6188 cxgb_down(adapter);
b8ff05a9 6189
80f61f19 6190 if (adapter->flags & CXGB4_USING_MSIX)
94cdb8bb 6191 free_msix_info(adapter);
0fbc81b3
HS		 6192 if (adapter->num_uld || adapter->num_ofld_uld)
6193 t4_uld_mem_free(adapter);
06546391 6194 free_some_resources(adapter);
b539ea60
AV		 6195 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
6196 list) {
6197 list_del(&entry->list);
6198 kfree(entry);
6199 }
6200
b5a02f50
AB		 6201#if IS_ENABLED(CONFIG_IPV6)
6202 t4_cleanup_clip_tbl(adapter);
6203#endif
d14807dd 6204 if (!is_t4(adapter->params.chip))
22adfe0a 6205 iounmap(adapter->bar2);
7829451c
HS		 6206 }
6207#ifdef CONFIG_PCI_IOV
6208 else {
baf50868 6209 cxgb4_iov_configure(adapter->pdev, 0);
7829451c
HS		 6210 }
6211#endif
c4e43e14
GG		 6212 iounmap(adapter->regs);
6213 pci_disable_pcie_error_reporting(pdev);
80f61f19 6214 if ((adapter->flags & CXGB4_DEV_ENABLED)) {
c4e43e14 6215 pci_disable_device(pdev);
80f61f19 6216 adapter->flags &= ~CXGB4_DEV_ENABLED;
c4e43e14
GG		 6217 }
6218 pci_release_regions(pdev);
6219 kfree(adapter->mbox_log);
6220 synchronize_rcu();
6221 kfree(adapter);
b8ff05a9
DM		 6222}
6223
0fbc81b3
HS		 6224/* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
6225 * delivery. This is essentially a stripped down version of the PCI remove()
6226 * function where we do the minimal amount of work necessary to shutdown any
6227 * further activity.
6228 */
6229static void shutdown_one(struct pci_dev *pdev)
6230{
6231 struct adapter *adapter = pci_get_drvdata(pdev);
6232
6233 /* As with remove_one() above (see extended comment), we only want do
6234 * do cleanup on PCI Devices which went all the way through init_one()
6235 * ...
6236 */
6237 if (!adapter) {
6238 pci_release_regions(pdev);
6239 return;
6240 }
6241
80f61f19 6242 adapter->flags |= CXGB4_SHUTTING_DOWN;
e1f6198e 6243
0fbc81b3
HS		 6244 if (adapter->pf == 4) {
6245 int i;
6246
6247 for_each_port(adapter, i)
6248 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6249 cxgb_close(adapter->port[i]);
6250
6a146f3a
GP		 6251 if (is_uld(adapter)) {
6252 detach_ulds(adapter);
6253 t4_uld_clean_up(adapter);
6254 }
6255
0fbc81b3
HS		 6256 disable_interrupts(adapter);
6257 disable_msi(adapter);
6258
6259 t4_sge_stop(adapter);
80f61f19 6260 if (adapter->flags & CXGB4_FW_OK)
0fbc81b3
HS		 6261 t4_fw_bye(adapter, adapter->mbox);
6262 }
0fbc81b3
HS		 6263}
6264
b8ff05a9
DM		 6265static struct pci_driver cxgb4_driver = {
6266 .name = KBUILD_MODNAME,
6267 .id_table = cxgb4_pci_tbl,
6268 .probe = init_one,
91744948 6269 .remove = remove_one,
0fbc81b3 6270 .shutdown = shutdown_one,
b6244201
HS		 6271#ifdef CONFIG_PCI_IOV
6272 .sriov_configure = cxgb4_iov_configure,
6273#endif
204dc3c0 6274 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 6275};
6276
6277static int __init cxgb4_init_module(void)
6278{
6279 int ret;
6280
6281 /* Debugfs support is optional, just warn if this fails */
6282 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6283 if (!cxgb4_debugfs_root)
428ac43f 6284 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 6285
6286 ret = pci_register_driver(&cxgb4_driver);
29aaee65 6287 if (ret < 0)
a3147770 6288 goto err_pci;
01bcca68 6289
1bb60376 6290#if IS_ENABLED(CONFIG_IPV6)
b5a02f50 6291 if (!inet6addr_registered) {
a3147770
Y		 6292 ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6293 if (ret)
6294 pci_unregister_driver(&cxgb4_driver);
6295 else
6296 inet6addr_registered = true;
b5a02f50 6297 }
1bb60376 6298#endif
01bcca68 6299
a3147770
Y		 6300 if (ret == 0)
6301 return ret;
6302
6303err_pci:
6304 debugfs_remove(cxgb4_debugfs_root);
6305
b8ff05a9
DM		 6306 return ret;
6307}
6308
6309static void __exit cxgb4_cleanup_module(void)
6310{
1bb60376 6311#if IS_ENABLED(CONFIG_IPV6)
1793c798 6312 if (inet6addr_registered) {
b5a02f50
AB		 6313 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6314 inet6addr_registered = false;
6315 }
1bb60376 6316#endif
b8ff05a9
DM		 6317 pci_unregister_driver(&cxgb4_driver);
6318 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
6319}
6320
6321module_init(cxgb4_init_module);
6322module_exit(cxgb4_cleanup_module);
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