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b8ff05a9 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
b72a32da | 4 | * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. |
b8ff05a9 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
36 | ||
37 | #include <linux/bitmap.h> | |
38 | #include <linux/crc32.h> | |
39 | #include <linux/ctype.h> | |
40 | #include <linux/debugfs.h> | |
41 | #include <linux/err.h> | |
42 | #include <linux/etherdevice.h> | |
43 | #include <linux/firmware.h> | |
01789349 | 44 | #include <linux/if.h> |
b8ff05a9 DM |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/init.h> | |
47 | #include <linux/log2.h> | |
48 | #include <linux/mdio.h> | |
49 | #include <linux/module.h> | |
50 | #include <linux/moduleparam.h> | |
51 | #include <linux/mutex.h> | |
52 | #include <linux/netdevice.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/aer.h> | |
55 | #include <linux/rtnetlink.h> | |
56 | #include <linux/sched.h> | |
57 | #include <linux/seq_file.h> | |
58 | #include <linux/sockios.h> | |
59 | #include <linux/vmalloc.h> | |
60 | #include <linux/workqueue.h> | |
61 | #include <net/neighbour.h> | |
62 | #include <net/netevent.h> | |
01bcca68 | 63 | #include <net/addrconf.h> |
1ef8019b | 64 | #include <net/bonding.h> |
b5a02f50 | 65 | #include <net/addrconf.h> |
7c0f6ba6 | 66 | #include <linux/uaccess.h> |
c5a8c0f3 | 67 | #include <linux/crash_dump.h> |
b8ff05a9 DM |
68 | |
69 | #include "cxgb4.h" | |
d57fd6ca | 70 | #include "cxgb4_filter.h" |
b8ff05a9 | 71 | #include "t4_regs.h" |
f612b815 | 72 | #include "t4_values.h" |
b8ff05a9 DM |
73 | #include "t4_msg.h" |
74 | #include "t4fw_api.h" | |
cd6c2f12 | 75 | #include "t4fw_version.h" |
688848b1 | 76 | #include "cxgb4_dcb.h" |
fd88b31a | 77 | #include "cxgb4_debugfs.h" |
b5a02f50 | 78 | #include "clip_tbl.h" |
b8ff05a9 | 79 | #include "l2t.h" |
b72a32da | 80 | #include "sched.h" |
d8931847 | 81 | #include "cxgb4_tc_u32.h" |
a4569504 | 82 | #include "cxgb4_ptp.h" |
b8ff05a9 | 83 | |
812034f1 HS |
84 | char cxgb4_driver_name[] = KBUILD_MODNAME; |
85 | ||
01bcca68 VP |
86 | #ifdef DRV_VERSION |
87 | #undef DRV_VERSION | |
88 | #endif | |
3a7f8554 | 89 | #define DRV_VERSION "2.0.0-ko" |
812034f1 | 90 | const char cxgb4_driver_version[] = DRV_VERSION; |
52a5f846 | 91 | #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" |
b8ff05a9 | 92 | |
b8ff05a9 DM |
93 | #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ |
94 | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ | |
95 | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) | |
96 | ||
3fedeab1 HS |
97 | /* Macros needed to support the PCI Device ID Table ... |
98 | */ | |
99 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ | |
768ffc66 | 100 | static const struct pci_device_id cxgb4_pci_tbl[] = { |
3fedeab1 | 101 | #define CH_PCI_DEVICE_ID_FUNCTION 0x4 |
b8ff05a9 | 102 | |
3fedeab1 HS |
103 | /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is |
104 | * called for both. | |
105 | */ | |
106 | #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 | |
107 | ||
108 | #define CH_PCI_ID_TABLE_ENTRY(devid) \ | |
109 | {PCI_VDEVICE(CHELSIO, (devid)), 4} | |
110 | ||
111 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ | |
112 | { 0, } \ | |
113 | } | |
114 | ||
115 | #include "t4_pci_id_tbl.h" | |
b8ff05a9 | 116 | |
16e47624 | 117 | #define FW4_FNAME "cxgb4/t4fw.bin" |
0a57a536 | 118 | #define FW5_FNAME "cxgb4/t5fw.bin" |
3ccc6cf7 | 119 | #define FW6_FNAME "cxgb4/t6fw.bin" |
16e47624 | 120 | #define FW4_CFNAME "cxgb4/t4-config.txt" |
0a57a536 | 121 | #define FW5_CFNAME "cxgb4/t5-config.txt" |
3ccc6cf7 | 122 | #define FW6_CFNAME "cxgb4/t6-config.txt" |
01b69614 HS |
123 | #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" |
124 | #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" | |
125 | #define PHY_AQ1202_DEVICEID 0x4409 | |
126 | #define PHY_BCM84834_DEVICEID 0x4486 | |
b8ff05a9 DM |
127 | |
128 | MODULE_DESCRIPTION(DRV_DESC); | |
129 | MODULE_AUTHOR("Chelsio Communications"); | |
130 | MODULE_LICENSE("Dual BSD/GPL"); | |
131 | MODULE_VERSION(DRV_VERSION); | |
132 | MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); | |
16e47624 | 133 | MODULE_FIRMWARE(FW4_FNAME); |
0a57a536 | 134 | MODULE_FIRMWARE(FW5_FNAME); |
52a5f846 | 135 | MODULE_FIRMWARE(FW6_FNAME); |
b8ff05a9 | 136 | |
b8ff05a9 DM |
137 | /* |
138 | * The driver uses the best interrupt scheme available on a platform in the | |
139 | * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which | |
140 | * of these schemes the driver may consider as follows: | |
141 | * | |
142 | * msi = 2: choose from among all three options | |
143 | * msi = 1: only consider MSI and INTx interrupts | |
144 | * msi = 0: force INTx interrupts | |
145 | */ | |
146 | static int msi = 2; | |
147 | ||
148 | module_param(msi, int, 0644); | |
149 | MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); | |
150 | ||
636f9d37 VP |
151 | /* |
152 | * Normally we tell the chip to deliver Ingress Packets into our DMA buffers | |
153 | * offset by 2 bytes in order to have the IP headers line up on 4-byte | |
154 | * boundaries. This is a requirement for many architectures which will throw | |
155 | * a machine check fault if an attempt is made to access one of the 4-byte IP | |
156 | * header fields on a non-4-byte boundary. And it's a major performance issue | |
157 | * even on some architectures which allow it like some implementations of the | |
158 | * x86 ISA. However, some architectures don't mind this and for some very | |
159 | * edge-case performance sensitive applications (like forwarding large volumes | |
160 | * of small packets), setting this DMA offset to 0 will decrease the number of | |
161 | * PCI-E Bus transfers enough to measurably affect performance. | |
162 | */ | |
163 | static int rx_dma_offset = 2; | |
164 | ||
688848b1 AB |
165 | /* TX Queue select used to determine what algorithm to use for selecting TX |
166 | * queue. Select between the kernel provided function (select_queue=0) or user | |
167 | * cxgb_select_queue function (select_queue=1) | |
168 | * | |
169 | * Default: select_queue=0 | |
170 | */ | |
171 | static int select_queue; | |
172 | module_param(select_queue, int, 0644); | |
173 | MODULE_PARM_DESC(select_queue, | |
174 | "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); | |
175 | ||
b8ff05a9 DM |
176 | static struct dentry *cxgb4_debugfs_root; |
177 | ||
94cdb8bb HS |
178 | LIST_HEAD(adapter_list); |
179 | DEFINE_MUTEX(uld_mutex); | |
b8ff05a9 DM |
180 | |
181 | static void link_report(struct net_device *dev) | |
182 | { | |
183 | if (!netif_carrier_ok(dev)) | |
184 | netdev_info(dev, "link down\n"); | |
185 | else { | |
186 | static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; | |
187 | ||
85412255 | 188 | const char *s; |
b8ff05a9 DM |
189 | const struct port_info *p = netdev_priv(dev); |
190 | ||
191 | switch (p->link_cfg.speed) { | |
5e78f7fd GG |
192 | case 100: |
193 | s = "100Mbps"; | |
b8ff05a9 | 194 | break; |
e8b39015 | 195 | case 1000: |
5e78f7fd | 196 | s = "1Gbps"; |
b8ff05a9 | 197 | break; |
5e78f7fd GG |
198 | case 10000: |
199 | s = "10Gbps"; | |
200 | break; | |
201 | case 25000: | |
202 | s = "25Gbps"; | |
b8ff05a9 | 203 | break; |
e8b39015 | 204 | case 40000: |
72aca4bf KS |
205 | s = "40Gbps"; |
206 | break; | |
5e78f7fd GG |
207 | case 100000: |
208 | s = "100Gbps"; | |
209 | break; | |
85412255 HS |
210 | default: |
211 | pr_info("%s: unsupported speed: %d\n", | |
212 | dev->name, p->link_cfg.speed); | |
213 | return; | |
b8ff05a9 DM |
214 | } |
215 | ||
216 | netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, | |
217 | fc[p->link_cfg.fc]); | |
218 | } | |
219 | } | |
220 | ||
688848b1 AB |
221 | #ifdef CONFIG_CHELSIO_T4_DCB |
222 | /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ | |
223 | static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) | |
224 | { | |
225 | struct port_info *pi = netdev_priv(dev); | |
226 | struct adapter *adap = pi->adapter; | |
227 | struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; | |
228 | int i; | |
229 | ||
230 | /* We use a simple mapping of Port TX Queue Index to DCB | |
231 | * Priority when we're enabling DCB. | |
232 | */ | |
233 | for (i = 0; i < pi->nqsets; i++, txq++) { | |
234 | u32 name, value; | |
235 | int err; | |
236 | ||
5167865a HS |
237 | name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
238 | FW_PARAMS_PARAM_X_V( | |
239 | FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | | |
240 | FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); | |
688848b1 AB |
241 | value = enable ? i : 0xffffffff; |
242 | ||
243 | /* Since we can be called while atomic (from "interrupt | |
244 | * level") we need to issue the Set Parameters Commannd | |
245 | * without sleeping (timeout < 0). | |
246 | */ | |
b2612722 | 247 | err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, |
01b69614 HS |
248 | &name, &value, |
249 | -FW_CMD_MAX_TIMEOUT); | |
688848b1 AB |
250 | |
251 | if (err) | |
252 | dev_err(adap->pdev_dev, | |
253 | "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", | |
254 | enable ? "set" : "unset", pi->port_id, i, -err); | |
10b00466 AB |
255 | else |
256 | txq->dcb_prio = value; | |
688848b1 AB |
257 | } |
258 | } | |
688848b1 | 259 | |
50935857 | 260 | static int cxgb4_dcb_enabled(const struct net_device *dev) |
218d48e7 | 261 | { |
218d48e7 HS |
262 | struct port_info *pi = netdev_priv(dev); |
263 | ||
264 | if (!pi->dcb.enabled) | |
265 | return 0; | |
266 | ||
267 | return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || | |
268 | (pi->dcb.state == CXGB4_DCB_STATE_HOST)); | |
218d48e7 | 269 | } |
7c70c4f8 | 270 | #endif /* CONFIG_CHELSIO_T4_DCB */ |
218d48e7 | 271 | |
b8ff05a9 DM |
272 | void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) |
273 | { | |
274 | struct net_device *dev = adapter->port[port_id]; | |
275 | ||
276 | /* Skip changes from disabled ports. */ | |
277 | if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { | |
278 | if (link_stat) | |
279 | netif_carrier_on(dev); | |
688848b1 AB |
280 | else { |
281 | #ifdef CONFIG_CHELSIO_T4_DCB | |
218d48e7 HS |
282 | if (cxgb4_dcb_enabled(dev)) { |
283 | cxgb4_dcb_state_init(dev); | |
284 | dcb_tx_queue_prio_enable(dev, false); | |
285 | } | |
688848b1 | 286 | #endif /* CONFIG_CHELSIO_T4_DCB */ |
b8ff05a9 | 287 | netif_carrier_off(dev); |
688848b1 | 288 | } |
b8ff05a9 DM |
289 | |
290 | link_report(dev); | |
291 | } | |
292 | } | |
293 | ||
294 | void t4_os_portmod_changed(const struct adapter *adap, int port_id) | |
295 | { | |
296 | static const char *mod_str[] = { | |
a0881cab | 297 | NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" |
b8ff05a9 DM |
298 | }; |
299 | ||
300 | const struct net_device *dev = adap->port[port_id]; | |
301 | const struct port_info *pi = netdev_priv(dev); | |
302 | ||
303 | if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) | |
304 | netdev_info(dev, "port module unplugged\n"); | |
a0881cab | 305 | else if (pi->mod_type < ARRAY_SIZE(mod_str)) |
b8ff05a9 | 306 | netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); |
be81a2de HS |
307 | else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) |
308 | netdev_info(dev, "%s: unsupported port module inserted\n", | |
309 | dev->name); | |
310 | else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) | |
311 | netdev_info(dev, "%s: unknown port module inserted\n", | |
312 | dev->name); | |
313 | else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) | |
314 | netdev_info(dev, "%s: transceiver module error\n", dev->name); | |
315 | else | |
316 | netdev_info(dev, "%s: unknown module type %d inserted\n", | |
317 | dev->name, pi->mod_type); | |
b8ff05a9 DM |
318 | } |
319 | ||
fc08a01a HS |
320 | int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ |
321 | module_param(dbfifo_int_thresh, int, 0644); | |
322 | MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); | |
323 | ||
b8ff05a9 | 324 | /* |
fc08a01a | 325 | * usecs to sleep while draining the dbfifo |
b8ff05a9 | 326 | */ |
fc08a01a HS |
327 | static int dbfifo_drain_delay = 1000; |
328 | module_param(dbfifo_drain_delay, int, 0644); | |
329 | MODULE_PARM_DESC(dbfifo_drain_delay, | |
330 | "usecs to sleep while draining the dbfifo"); | |
331 | ||
332 | static inline int cxgb4_set_addr_hash(struct port_info *pi) | |
b8ff05a9 | 333 | { |
fc08a01a HS |
334 | struct adapter *adap = pi->adapter; |
335 | u64 vec = 0; | |
336 | bool ucast = false; | |
337 | struct hash_mac_addr *entry; | |
338 | ||
339 | /* Calculate the hash vector for the updated list and program it */ | |
340 | list_for_each_entry(entry, &adap->mac_hlist, list) { | |
341 | ucast |= is_unicast_ether_addr(entry->addr); | |
342 | vec |= (1ULL << hash_mac_addr(entry->addr)); | |
343 | } | |
344 | return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, | |
345 | vec, false); | |
346 | } | |
347 | ||
348 | static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) | |
349 | { | |
350 | struct port_info *pi = netdev_priv(netdev); | |
351 | struct adapter *adap = pi->adapter; | |
352 | int ret; | |
b8ff05a9 DM |
353 | u64 mhash = 0; |
354 | u64 uhash = 0; | |
fc08a01a HS |
355 | bool free = false; |
356 | bool ucast = is_unicast_ether_addr(mac_addr); | |
357 | const u8 *maclist[1] = {mac_addr}; | |
358 | struct hash_mac_addr *new_entry; | |
359 | ||
360 | ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist, | |
361 | NULL, ucast ? &uhash : &mhash, false); | |
362 | if (ret < 0) | |
363 | goto out; | |
364 | /* if hash != 0, then add the addr to hash addr list | |
365 | * so on the end we will calculate the hash for the | |
366 | * list and program it | |
367 | */ | |
368 | if (uhash || mhash) { | |
369 | new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); | |
370 | if (!new_entry) | |
371 | return -ENOMEM; | |
372 | ether_addr_copy(new_entry->addr, mac_addr); | |
373 | list_add_tail(&new_entry->list, &adap->mac_hlist); | |
374 | ret = cxgb4_set_addr_hash(pi); | |
b8ff05a9 | 375 | } |
fc08a01a HS |
376 | out: |
377 | return ret < 0 ? ret : 0; | |
378 | } | |
b8ff05a9 | 379 | |
fc08a01a HS |
380 | static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) |
381 | { | |
382 | struct port_info *pi = netdev_priv(netdev); | |
383 | struct adapter *adap = pi->adapter; | |
384 | int ret; | |
385 | const u8 *maclist[1] = {mac_addr}; | |
386 | struct hash_mac_addr *entry, *tmp; | |
b8ff05a9 | 387 | |
fc08a01a HS |
388 | /* If the MAC address to be removed is in the hash addr |
389 | * list, delete it from the list and update hash vector | |
390 | */ | |
391 | list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { | |
392 | if (ether_addr_equal(entry->addr, mac_addr)) { | |
393 | list_del(&entry->list); | |
394 | kfree(entry); | |
395 | return cxgb4_set_addr_hash(pi); | |
b8ff05a9 DM |
396 | } |
397 | } | |
398 | ||
fc08a01a HS |
399 | ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false); |
400 | return ret < 0 ? -EINVAL : 0; | |
b8ff05a9 DM |
401 | } |
402 | ||
403 | /* | |
404 | * Set Rx properties of a port, such as promiscruity, address filters, and MTU. | |
405 | * If @mtu is -1 it is left unchanged. | |
406 | */ | |
407 | static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) | |
408 | { | |
b8ff05a9 | 409 | struct port_info *pi = netdev_priv(dev); |
fc08a01a | 410 | struct adapter *adapter = pi->adapter; |
b8ff05a9 | 411 | |
d01f7abc HS |
412 | __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); |
413 | __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); | |
fc08a01a HS |
414 | |
415 | return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, | |
416 | (dev->flags & IFF_PROMISC) ? 1 : 0, | |
417 | (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, | |
418 | sleep_ok); | |
b8ff05a9 DM |
419 | } |
420 | ||
421 | /** | |
422 | * link_start - enable a port | |
423 | * @dev: the port to enable | |
424 | * | |
425 | * Performs the MAC and PHY actions needed to enable a port. | |
426 | */ | |
427 | static int link_start(struct net_device *dev) | |
428 | { | |
429 | int ret; | |
430 | struct port_info *pi = netdev_priv(dev); | |
b2612722 | 431 | unsigned int mb = pi->adapter->pf; |
b8ff05a9 DM |
432 | |
433 | /* | |
434 | * We do not set address filters and promiscuity here, the stack does | |
435 | * that step explicitly. | |
436 | */ | |
060e0c75 | 437 | ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, |
f646968f | 438 | !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); |
b8ff05a9 | 439 | if (ret == 0) { |
060e0c75 | 440 | ret = t4_change_mac(pi->adapter, mb, pi->viid, |
b8ff05a9 | 441 | pi->xact_addr_filt, dev->dev_addr, true, |
b6bd29e7 | 442 | true); |
b8ff05a9 DM |
443 | if (ret >= 0) { |
444 | pi->xact_addr_filt = ret; | |
445 | ret = 0; | |
446 | } | |
447 | } | |
448 | if (ret == 0) | |
4036da90 | 449 | ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, |
060e0c75 | 450 | &pi->link_cfg); |
30f00847 AB |
451 | if (ret == 0) { |
452 | local_bh_disable(); | |
688848b1 AB |
453 | ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true, |
454 | true, CXGB4_DCB_ENABLED); | |
30f00847 AB |
455 | local_bh_enable(); |
456 | } | |
688848b1 | 457 | |
b8ff05a9 DM |
458 | return ret; |
459 | } | |
460 | ||
688848b1 AB |
461 | #ifdef CONFIG_CHELSIO_T4_DCB |
462 | /* Handle a Data Center Bridging update message from the firmware. */ | |
463 | static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) | |
464 | { | |
2b5fb1f2 | 465 | int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); |
134491fd | 466 | struct net_device *dev = adap->port[adap->chan_map[port]]; |
688848b1 AB |
467 | int old_dcb_enabled = cxgb4_dcb_enabled(dev); |
468 | int new_dcb_enabled; | |
469 | ||
470 | cxgb4_dcb_handle_fw_update(adap, pcmd); | |
471 | new_dcb_enabled = cxgb4_dcb_enabled(dev); | |
472 | ||
473 | /* If the DCB has become enabled or disabled on the port then we're | |
474 | * going to need to set up/tear down DCB Priority parameters for the | |
475 | * TX Queues associated with the port. | |
476 | */ | |
477 | if (new_dcb_enabled != old_dcb_enabled) | |
478 | dcb_tx_queue_prio_enable(dev, new_dcb_enabled); | |
479 | } | |
480 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
481 | ||
f2b7e78d | 482 | /* Response queue handler for the FW event queue. |
b8ff05a9 DM |
483 | */ |
484 | static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, | |
485 | const struct pkt_gl *gl) | |
486 | { | |
487 | u8 opcode = ((const struct rss_header *)rsp)->opcode; | |
488 | ||
489 | rsp++; /* skip RSS header */ | |
b407a4a9 VP |
490 | |
491 | /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. | |
492 | */ | |
493 | if (unlikely(opcode == CPL_FW4_MSG && | |
494 | ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { | |
495 | rsp++; | |
496 | opcode = ((const struct rss_header *)rsp)->opcode; | |
497 | rsp++; | |
498 | if (opcode != CPL_SGE_EGR_UPDATE) { | |
499 | dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" | |
500 | , opcode); | |
501 | goto out; | |
502 | } | |
503 | } | |
504 | ||
b8ff05a9 DM |
505 | if (likely(opcode == CPL_SGE_EGR_UPDATE)) { |
506 | const struct cpl_sge_egr_update *p = (void *)rsp; | |
bdc590b9 | 507 | unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); |
e46dab4d | 508 | struct sge_txq *txq; |
b8ff05a9 | 509 | |
e46dab4d | 510 | txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; |
b8ff05a9 | 511 | txq->restarts++; |
ab677ff4 | 512 | if (txq->q_type == CXGB4_TXQ_ETH) { |
b8ff05a9 DM |
513 | struct sge_eth_txq *eq; |
514 | ||
515 | eq = container_of(txq, struct sge_eth_txq, q); | |
516 | netif_tx_wake_queue(eq->txq); | |
517 | } else { | |
ab677ff4 | 518 | struct sge_uld_txq *oq; |
b8ff05a9 | 519 | |
ab677ff4 | 520 | oq = container_of(txq, struct sge_uld_txq, q); |
b8ff05a9 DM |
521 | tasklet_schedule(&oq->qresume_tsk); |
522 | } | |
523 | } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { | |
524 | const struct cpl_fw6_msg *p = (void *)rsp; | |
525 | ||
688848b1 AB |
526 | #ifdef CONFIG_CHELSIO_T4_DCB |
527 | const struct fw_port_cmd *pcmd = (const void *)p->data; | |
e2ac9628 | 528 | unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); |
688848b1 | 529 | unsigned int action = |
2b5fb1f2 | 530 | FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); |
688848b1 AB |
531 | |
532 | if (cmd == FW_PORT_CMD && | |
533 | action == FW_PORT_ACTION_GET_PORT_INFO) { | |
2b5fb1f2 | 534 | int port = FW_PORT_CMD_PORTID_G( |
688848b1 | 535 | be32_to_cpu(pcmd->op_to_portid)); |
134491fd HS |
536 | struct net_device *dev = |
537 | q->adap->port[q->adap->chan_map[port]]; | |
688848b1 | 538 | int state_input = ((pcmd->u.info.dcbxdis_pkd & |
2b5fb1f2 | 539 | FW_PORT_CMD_DCBXDIS_F) |
688848b1 AB |
540 | ? CXGB4_DCB_INPUT_FW_DISABLED |
541 | : CXGB4_DCB_INPUT_FW_ENABLED); | |
542 | ||
543 | cxgb4_dcb_state_fsm(dev, state_input); | |
544 | } | |
545 | ||
546 | if (cmd == FW_PORT_CMD && | |
547 | action == FW_PORT_ACTION_L2_DCB_CFG) | |
548 | dcb_rpl(q->adap, pcmd); | |
549 | else | |
550 | #endif | |
551 | if (p->type == 0) | |
552 | t4_handle_fw_rpl(q->adap, p->data); | |
b8ff05a9 DM |
553 | } else if (opcode == CPL_L2T_WRITE_RPL) { |
554 | const struct cpl_l2t_write_rpl *p = (void *)rsp; | |
555 | ||
556 | do_l2t_write_rpl(q->adap, p); | |
f2b7e78d VP |
557 | } else if (opcode == CPL_SET_TCB_RPL) { |
558 | const struct cpl_set_tcb_rpl *p = (void *)rsp; | |
559 | ||
560 | filter_rpl(q->adap, p); | |
b8ff05a9 DM |
561 | } else |
562 | dev_err(q->adap->pdev_dev, | |
563 | "unexpected CPL %#x on FW event queue\n", opcode); | |
b407a4a9 | 564 | out: |
b8ff05a9 DM |
565 | return 0; |
566 | } | |
567 | ||
b8ff05a9 DM |
568 | static void disable_msi(struct adapter *adapter) |
569 | { | |
570 | if (adapter->flags & USING_MSIX) { | |
571 | pci_disable_msix(adapter->pdev); | |
572 | adapter->flags &= ~USING_MSIX; | |
573 | } else if (adapter->flags & USING_MSI) { | |
574 | pci_disable_msi(adapter->pdev); | |
575 | adapter->flags &= ~USING_MSI; | |
576 | } | |
577 | } | |
578 | ||
579 | /* | |
580 | * Interrupt handler for non-data events used with MSI-X. | |
581 | */ | |
582 | static irqreturn_t t4_nondata_intr(int irq, void *cookie) | |
583 | { | |
584 | struct adapter *adap = cookie; | |
0d804338 | 585 | u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); |
b8ff05a9 | 586 | |
0d804338 | 587 | if (v & PFSW_F) { |
b8ff05a9 | 588 | adap->swintr = 1; |
0d804338 | 589 | t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); |
b8ff05a9 | 590 | } |
c3c7b121 HS |
591 | if (adap->flags & MASTER_PF) |
592 | t4_slow_intr_handler(adap); | |
b8ff05a9 DM |
593 | return IRQ_HANDLED; |
594 | } | |
595 | ||
596 | /* | |
597 | * Name the MSI-X interrupts. | |
598 | */ | |
599 | static void name_msix_vecs(struct adapter *adap) | |
600 | { | |
ba27816c | 601 | int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); |
b8ff05a9 DM |
602 | |
603 | /* non-data interrupts */ | |
b1a3c2b6 | 604 | snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); |
b8ff05a9 DM |
605 | |
606 | /* FW events */ | |
b1a3c2b6 DM |
607 | snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", |
608 | adap->port[0]->name); | |
b8ff05a9 DM |
609 | |
610 | /* Ethernet queues */ | |
611 | for_each_port(adap, j) { | |
612 | struct net_device *d = adap->port[j]; | |
613 | const struct port_info *pi = netdev_priv(d); | |
614 | ||
ba27816c | 615 | for (i = 0; i < pi->nqsets; i++, msi_idx++) |
b8ff05a9 DM |
616 | snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", |
617 | d->name, i); | |
b8ff05a9 | 618 | } |
b8ff05a9 DM |
619 | } |
620 | ||
621 | static int request_msix_queue_irqs(struct adapter *adap) | |
622 | { | |
623 | struct sge *s = &adap->sge; | |
0fbc81b3 | 624 | int err, ethqidx; |
cf38be6d | 625 | int msi_index = 2; |
b8ff05a9 DM |
626 | |
627 | err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, | |
628 | adap->msix_info[1].desc, &s->fw_evtq); | |
629 | if (err) | |
630 | return err; | |
631 | ||
632 | for_each_ethrxq(s, ethqidx) { | |
404d9e3f VP |
633 | err = request_irq(adap->msix_info[msi_index].vec, |
634 | t4_sge_intr_msix, 0, | |
635 | adap->msix_info[msi_index].desc, | |
b8ff05a9 DM |
636 | &s->ethrxq[ethqidx].rspq); |
637 | if (err) | |
638 | goto unwind; | |
404d9e3f | 639 | msi_index++; |
b8ff05a9 | 640 | } |
b8ff05a9 DM |
641 | return 0; |
642 | ||
643 | unwind: | |
b8ff05a9 | 644 | while (--ethqidx >= 0) |
404d9e3f VP |
645 | free_irq(adap->msix_info[--msi_index].vec, |
646 | &s->ethrxq[ethqidx].rspq); | |
b8ff05a9 DM |
647 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); |
648 | return err; | |
649 | } | |
650 | ||
651 | static void free_msix_queue_irqs(struct adapter *adap) | |
652 | { | |
404d9e3f | 653 | int i, msi_index = 2; |
b8ff05a9 DM |
654 | struct sge *s = &adap->sge; |
655 | ||
656 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); | |
657 | for_each_ethrxq(s, i) | |
404d9e3f | 658 | free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); |
b8ff05a9 DM |
659 | } |
660 | ||
671b0060 | 661 | /** |
812034f1 | 662 | * cxgb4_write_rss - write the RSS table for a given port |
671b0060 DM |
663 | * @pi: the port |
664 | * @queues: array of queue indices for RSS | |
665 | * | |
666 | * Sets up the portion of the HW RSS table for the port's VI to distribute | |
667 | * packets to the Rx queues in @queues. | |
c035e183 | 668 | * Should never be called before setting up sge eth rx queues |
671b0060 | 669 | */ |
812034f1 | 670 | int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) |
671b0060 DM |
671 | { |
672 | u16 *rss; | |
673 | int i, err; | |
c035e183 HS |
674 | struct adapter *adapter = pi->adapter; |
675 | const struct sge_eth_rxq *rxq; | |
671b0060 | 676 | |
c035e183 | 677 | rxq = &adapter->sge.ethrxq[pi->first_qset]; |
671b0060 DM |
678 | rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL); |
679 | if (!rss) | |
680 | return -ENOMEM; | |
681 | ||
682 | /* map the queue indices to queue ids */ | |
683 | for (i = 0; i < pi->rss_size; i++, queues++) | |
c035e183 | 684 | rss[i] = rxq[*queues].rspq.abs_id; |
671b0060 | 685 | |
b2612722 | 686 | err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, |
060e0c75 | 687 | pi->rss_size, rss, pi->rss_size); |
c035e183 HS |
688 | /* If Tunnel All Lookup isn't specified in the global RSS |
689 | * Configuration, then we need to specify a default Ingress | |
690 | * Queue for any ingress packets which aren't hashed. We'll | |
691 | * use our first ingress queue ... | |
692 | */ | |
693 | if (!err) | |
694 | err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, | |
695 | FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | | |
696 | FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | | |
697 | FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | | |
698 | FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | | |
699 | FW_RSS_VI_CONFIG_CMD_UDPEN_F, | |
700 | rss[0]); | |
671b0060 DM |
701 | kfree(rss); |
702 | return err; | |
703 | } | |
704 | ||
b8ff05a9 DM |
705 | /** |
706 | * setup_rss - configure RSS | |
707 | * @adap: the adapter | |
708 | * | |
671b0060 | 709 | * Sets up RSS for each port. |
b8ff05a9 DM |
710 | */ |
711 | static int setup_rss(struct adapter *adap) | |
712 | { | |
c035e183 | 713 | int i, j, err; |
b8ff05a9 DM |
714 | |
715 | for_each_port(adap, i) { | |
716 | const struct port_info *pi = adap2pinfo(adap, i); | |
b8ff05a9 | 717 | |
c035e183 HS |
718 | /* Fill default values with equal distribution */ |
719 | for (j = 0; j < pi->rss_size; j++) | |
720 | pi->rss[j] = j % pi->nqsets; | |
721 | ||
812034f1 | 722 | err = cxgb4_write_rss(pi, pi->rss); |
b8ff05a9 DM |
723 | if (err) |
724 | return err; | |
725 | } | |
726 | return 0; | |
727 | } | |
728 | ||
e46dab4d DM |
729 | /* |
730 | * Return the channel of the ingress queue with the given qid. | |
731 | */ | |
732 | static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) | |
733 | { | |
734 | qid -= p->ingr_start; | |
735 | return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; | |
736 | } | |
737 | ||
b8ff05a9 DM |
738 | /* |
739 | * Wait until all NAPI handlers are descheduled. | |
740 | */ | |
741 | static void quiesce_rx(struct adapter *adap) | |
742 | { | |
743 | int i; | |
744 | ||
4b8e27a8 | 745 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
746 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
747 | ||
5226b791 | 748 | if (q && q->handler) |
b8ff05a9 DM |
749 | napi_disable(&q->napi); |
750 | } | |
751 | } | |
752 | ||
b37987e8 HS |
753 | /* Disable interrupt and napi handler */ |
754 | static void disable_interrupts(struct adapter *adap) | |
755 | { | |
756 | if (adap->flags & FULL_INIT_DONE) { | |
757 | t4_intr_disable(adap); | |
758 | if (adap->flags & USING_MSIX) { | |
759 | free_msix_queue_irqs(adap); | |
760 | free_irq(adap->msix_info[0].vec, adap); | |
761 | } else { | |
762 | free_irq(adap->pdev->irq, adap); | |
763 | } | |
764 | quiesce_rx(adap); | |
765 | } | |
766 | } | |
767 | ||
b8ff05a9 DM |
768 | /* |
769 | * Enable NAPI scheduling and interrupt generation for all Rx queues. | |
770 | */ | |
771 | static void enable_rx(struct adapter *adap) | |
772 | { | |
773 | int i; | |
774 | ||
4b8e27a8 | 775 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
776 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
777 | ||
778 | if (!q) | |
779 | continue; | |
5226b791 | 780 | if (q->handler) |
b8ff05a9 | 781 | napi_enable(&q->napi); |
5226b791 | 782 | |
b8ff05a9 | 783 | /* 0-increment GTS to start the timer and enable interrupts */ |
f612b815 HS |
784 | t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), |
785 | SEINTARM_V(q->intr_params) | | |
786 | INGRESSQID_V(q->cntxt_id)); | |
b8ff05a9 DM |
787 | } |
788 | } | |
789 | ||
1c6a5b0e | 790 | |
0fbc81b3 | 791 | static int setup_fw_sge_queues(struct adapter *adap) |
b8ff05a9 | 792 | { |
b8ff05a9 | 793 | struct sge *s = &adap->sge; |
0fbc81b3 | 794 | int err = 0; |
b8ff05a9 | 795 | |
4b8e27a8 HS |
796 | bitmap_zero(s->starving_fl, s->egr_sz); |
797 | bitmap_zero(s->txq_maperr, s->egr_sz); | |
b8ff05a9 DM |
798 | |
799 | if (adap->flags & USING_MSIX) | |
94cdb8bb | 800 | adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */ |
b8ff05a9 DM |
801 | else { |
802 | err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, | |
2337ba42 | 803 | NULL, NULL, NULL, -1); |
b8ff05a9 DM |
804 | if (err) |
805 | return err; | |
94cdb8bb | 806 | adap->msi_idx = -((int)s->intrq.abs_id + 1); |
b8ff05a9 DM |
807 | } |
808 | ||
809 | err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], | |
94cdb8bb | 810 | adap->msi_idx, NULL, fwevtq_handler, NULL, -1); |
0fbc81b3 HS |
811 | if (err) |
812 | t4_free_sge_resources(adap); | |
813 | return err; | |
814 | } | |
815 | ||
816 | /** | |
817 | * setup_sge_queues - configure SGE Tx/Rx/response queues | |
818 | * @adap: the adapter | |
819 | * | |
820 | * Determines how many sets of SGE queues to use and initializes them. | |
821 | * We support multiple queue sets per port if we have MSI-X, otherwise | |
822 | * just one queue set per port. | |
823 | */ | |
824 | static int setup_sge_queues(struct adapter *adap) | |
825 | { | |
826 | int err, i, j; | |
827 | struct sge *s = &adap->sge; | |
d427caee | 828 | struct sge_uld_rxq_info *rxq_info = NULL; |
0fbc81b3 | 829 | unsigned int cmplqid = 0; |
b8ff05a9 | 830 | |
d427caee GG |
831 | if (is_uld(adap)) |
832 | rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; | |
833 | ||
b8ff05a9 DM |
834 | for_each_port(adap, i) { |
835 | struct net_device *dev = adap->port[i]; | |
836 | struct port_info *pi = netdev_priv(dev); | |
837 | struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; | |
838 | struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; | |
839 | ||
840 | for (j = 0; j < pi->nqsets; j++, q++) { | |
94cdb8bb HS |
841 | if (adap->msi_idx > 0) |
842 | adap->msi_idx++; | |
b8ff05a9 | 843 | err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, |
94cdb8bb | 844 | adap->msi_idx, &q->fl, |
145ef8a5 | 845 | t4_ethrx_handler, |
2337ba42 | 846 | NULL, |
193c4c28 AV |
847 | t4_get_tp_ch_map(adap, |
848 | pi->tx_chan)); | |
b8ff05a9 DM |
849 | if (err) |
850 | goto freeout; | |
851 | q->rspq.idx = j; | |
852 | memset(&q->stats, 0, sizeof(q->stats)); | |
853 | } | |
854 | for (j = 0; j < pi->nqsets; j++, t++) { | |
855 | err = t4_sge_alloc_eth_txq(adap, t, dev, | |
856 | netdev_get_tx_queue(dev, j), | |
857 | s->fw_evtq.cntxt_id); | |
858 | if (err) | |
859 | goto freeout; | |
860 | } | |
861 | } | |
862 | ||
b8ff05a9 | 863 | for_each_port(adap, i) { |
0fbc81b3 | 864 | /* Note that cmplqid below is 0 if we don't |
b8ff05a9 DM |
865 | * have RDMA queues, and that's the right value. |
866 | */ | |
0fbc81b3 HS |
867 | if (rxq_info) |
868 | cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id; | |
869 | ||
b8ff05a9 | 870 | err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], |
0fbc81b3 | 871 | s->fw_evtq.cntxt_id, cmplqid); |
b8ff05a9 DM |
872 | if (err) |
873 | goto freeout; | |
874 | } | |
875 | ||
a4569504 AG |
876 | if (!is_t4(adap->params.chip)) { |
877 | err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0], | |
878 | netdev_get_tx_queue(adap->port[0], 0) | |
879 | , s->fw_evtq.cntxt_id); | |
880 | if (err) | |
881 | goto freeout; | |
882 | } | |
883 | ||
9bb59b96 | 884 | t4_write_reg(adap, is_t4(adap->params.chip) ? |
837e4a42 HS |
885 | MPS_TRC_RSS_CONTROL_A : |
886 | MPS_T5_TRC_RSS_CONTROL_A, | |
887 | RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | | |
888 | QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); | |
b8ff05a9 | 889 | return 0; |
0fbc81b3 HS |
890 | freeout: |
891 | t4_free_sge_resources(adap); | |
892 | return err; | |
b8ff05a9 DM |
893 | } |
894 | ||
688848b1 AB |
895 | static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, |
896 | void *accel_priv, select_queue_fallback_t fallback) | |
897 | { | |
898 | int txq; | |
899 | ||
900 | #ifdef CONFIG_CHELSIO_T4_DCB | |
901 | /* If a Data Center Bridging has been successfully negotiated on this | |
902 | * link then we'll use the skb's priority to map it to a TX Queue. | |
903 | * The skb's priority is determined via the VLAN Tag Priority Code | |
904 | * Point field. | |
905 | */ | |
85eacf3f | 906 | if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) { |
688848b1 AB |
907 | u16 vlan_tci; |
908 | int err; | |
909 | ||
910 | err = vlan_get_tag(skb, &vlan_tci); | |
911 | if (unlikely(err)) { | |
912 | if (net_ratelimit()) | |
913 | netdev_warn(dev, | |
914 | "TX Packet without VLAN Tag on DCB Link\n"); | |
915 | txq = 0; | |
916 | } else { | |
917 | txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; | |
84a200b3 VP |
918 | #ifdef CONFIG_CHELSIO_T4_FCOE |
919 | if (skb->protocol == htons(ETH_P_FCOE)) | |
920 | txq = skb->priority & 0x7; | |
921 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
688848b1 AB |
922 | } |
923 | return txq; | |
924 | } | |
925 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
926 | ||
927 | if (select_queue) { | |
928 | txq = (skb_rx_queue_recorded(skb) | |
929 | ? skb_get_rx_queue(skb) | |
930 | : smp_processor_id()); | |
931 | ||
932 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
933 | txq -= dev->real_num_tx_queues; | |
934 | ||
935 | return txq; | |
936 | } | |
937 | ||
938 | return fallback(dev, skb) % dev->real_num_tx_queues; | |
939 | } | |
940 | ||
b8ff05a9 DM |
941 | static int closest_timer(const struct sge *s, int time) |
942 | { | |
943 | int i, delta, match = 0, min_delta = INT_MAX; | |
944 | ||
945 | for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { | |
946 | delta = time - s->timer_val[i]; | |
947 | if (delta < 0) | |
948 | delta = -delta; | |
949 | if (delta < min_delta) { | |
950 | min_delta = delta; | |
951 | match = i; | |
952 | } | |
953 | } | |
954 | return match; | |
955 | } | |
956 | ||
957 | static int closest_thres(const struct sge *s, int thres) | |
958 | { | |
959 | int i, delta, match = 0, min_delta = INT_MAX; | |
960 | ||
961 | for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { | |
962 | delta = thres - s->counter_val[i]; | |
963 | if (delta < 0) | |
964 | delta = -delta; | |
965 | if (delta < min_delta) { | |
966 | min_delta = delta; | |
967 | match = i; | |
968 | } | |
969 | } | |
970 | return match; | |
971 | } | |
972 | ||
b8ff05a9 | 973 | /** |
812034f1 | 974 | * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters |
b8ff05a9 DM |
975 | * @q: the Rx queue |
976 | * @us: the hold-off time in us, or 0 to disable timer | |
977 | * @cnt: the hold-off packet count, or 0 to disable counter | |
978 | * | |
979 | * Sets an Rx queue's interrupt hold-off time and packet count. At least | |
980 | * one of the two needs to be enabled for the queue to generate interrupts. | |
981 | */ | |
812034f1 HS |
982 | int cxgb4_set_rspq_intr_params(struct sge_rspq *q, |
983 | unsigned int us, unsigned int cnt) | |
b8ff05a9 | 984 | { |
c887ad0e HS |
985 | struct adapter *adap = q->adap; |
986 | ||
b8ff05a9 DM |
987 | if ((us | cnt) == 0) |
988 | cnt = 1; | |
989 | ||
990 | if (cnt) { | |
991 | int err; | |
992 | u32 v, new_idx; | |
993 | ||
994 | new_idx = closest_thres(&adap->sge, cnt); | |
995 | if (q->desc && q->pktcnt_idx != new_idx) { | |
996 | /* the queue has already been created, update it */ | |
5167865a HS |
997 | v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
998 | FW_PARAMS_PARAM_X_V( | |
999 | FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | | |
1000 | FW_PARAMS_PARAM_YZ_V(q->cntxt_id); | |
b2612722 HS |
1001 | err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, |
1002 | &v, &new_idx); | |
b8ff05a9 DM |
1003 | if (err) |
1004 | return err; | |
1005 | } | |
1006 | q->pktcnt_idx = new_idx; | |
1007 | } | |
1008 | ||
1009 | us = us == 0 ? 6 : closest_timer(&adap->sge, us); | |
1ecc7b7a | 1010 | q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); |
b8ff05a9 DM |
1011 | return 0; |
1012 | } | |
1013 | ||
c8f44aff | 1014 | static int cxgb_set_features(struct net_device *dev, netdev_features_t features) |
87b6cf51 | 1015 | { |
2ed28baa | 1016 | const struct port_info *pi = netdev_priv(dev); |
c8f44aff | 1017 | netdev_features_t changed = dev->features ^ features; |
19ecae2c | 1018 | int err; |
19ecae2c | 1019 | |
f646968f | 1020 | if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) |
2ed28baa | 1021 | return 0; |
19ecae2c | 1022 | |
b2612722 | 1023 | err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, |
2ed28baa | 1024 | -1, -1, -1, |
f646968f | 1025 | !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); |
2ed28baa | 1026 | if (unlikely(err)) |
f646968f | 1027 | dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; |
19ecae2c | 1028 | return err; |
87b6cf51 DM |
1029 | } |
1030 | ||
91744948 | 1031 | static int setup_debugfs(struct adapter *adap) |
b8ff05a9 | 1032 | { |
b8ff05a9 DM |
1033 | if (IS_ERR_OR_NULL(adap->debugfs_root)) |
1034 | return -1; | |
1035 | ||
fd88b31a HS |
1036 | #ifdef CONFIG_DEBUG_FS |
1037 | t4_setup_debugfs(adap); | |
1038 | #endif | |
b8ff05a9 DM |
1039 | return 0; |
1040 | } | |
1041 | ||
1042 | /* | |
1043 | * upper-layer driver support | |
1044 | */ | |
1045 | ||
1046 | /* | |
1047 | * Allocate an active-open TID and set it to the supplied value. | |
1048 | */ | |
1049 | int cxgb4_alloc_atid(struct tid_info *t, void *data) | |
1050 | { | |
1051 | int atid = -1; | |
1052 | ||
1053 | spin_lock_bh(&t->atid_lock); | |
1054 | if (t->afree) { | |
1055 | union aopen_entry *p = t->afree; | |
1056 | ||
f2b7e78d | 1057 | atid = (p - t->atid_tab) + t->atid_base; |
b8ff05a9 DM |
1058 | t->afree = p->next; |
1059 | p->data = data; | |
1060 | t->atids_in_use++; | |
1061 | } | |
1062 | spin_unlock_bh(&t->atid_lock); | |
1063 | return atid; | |
1064 | } | |
1065 | EXPORT_SYMBOL(cxgb4_alloc_atid); | |
1066 | ||
1067 | /* | |
1068 | * Release an active-open TID. | |
1069 | */ | |
1070 | void cxgb4_free_atid(struct tid_info *t, unsigned int atid) | |
1071 | { | |
f2b7e78d | 1072 | union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; |
b8ff05a9 DM |
1073 | |
1074 | spin_lock_bh(&t->atid_lock); | |
1075 | p->next = t->afree; | |
1076 | t->afree = p; | |
1077 | t->atids_in_use--; | |
1078 | spin_unlock_bh(&t->atid_lock); | |
1079 | } | |
1080 | EXPORT_SYMBOL(cxgb4_free_atid); | |
1081 | ||
1082 | /* | |
1083 | * Allocate a server TID and set it to the supplied value. | |
1084 | */ | |
1085 | int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) | |
1086 | { | |
1087 | int stid; | |
1088 | ||
1089 | spin_lock_bh(&t->stid_lock); | |
1090 | if (family == PF_INET) { | |
1091 | stid = find_first_zero_bit(t->stid_bmap, t->nstids); | |
1092 | if (stid < t->nstids) | |
1093 | __set_bit(stid, t->stid_bmap); | |
1094 | else | |
1095 | stid = -1; | |
1096 | } else { | |
a99c683e | 1097 | stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); |
b8ff05a9 DM |
1098 | if (stid < 0) |
1099 | stid = -1; | |
1100 | } | |
1101 | if (stid >= 0) { | |
1102 | t->stid_tab[stid].data = data; | |
1103 | stid += t->stid_base; | |
15f63b74 KS |
1104 | /* IPv6 requires max of 520 bits or 16 cells in TCAM |
1105 | * This is equivalent to 4 TIDs. With CLIP enabled it | |
1106 | * needs 2 TIDs. | |
1107 | */ | |
1dec4cec | 1108 | if (family == PF_INET6) { |
a99c683e | 1109 | t->stids_in_use += 2; |
1dec4cec GG |
1110 | t->v6_stids_in_use += 2; |
1111 | } else { | |
1112 | t->stids_in_use++; | |
1113 | } | |
b8ff05a9 DM |
1114 | } |
1115 | spin_unlock_bh(&t->stid_lock); | |
1116 | return stid; | |
1117 | } | |
1118 | EXPORT_SYMBOL(cxgb4_alloc_stid); | |
1119 | ||
dca4faeb VP |
1120 | /* Allocate a server filter TID and set it to the supplied value. |
1121 | */ | |
1122 | int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) | |
1123 | { | |
1124 | int stid; | |
1125 | ||
1126 | spin_lock_bh(&t->stid_lock); | |
1127 | if (family == PF_INET) { | |
1128 | stid = find_next_zero_bit(t->stid_bmap, | |
1129 | t->nstids + t->nsftids, t->nstids); | |
1130 | if (stid < (t->nstids + t->nsftids)) | |
1131 | __set_bit(stid, t->stid_bmap); | |
1132 | else | |
1133 | stid = -1; | |
1134 | } else { | |
1135 | stid = -1; | |
1136 | } | |
1137 | if (stid >= 0) { | |
1138 | t->stid_tab[stid].data = data; | |
470c60c4 KS |
1139 | stid -= t->nstids; |
1140 | stid += t->sftid_base; | |
2248b293 | 1141 | t->sftids_in_use++; |
dca4faeb VP |
1142 | } |
1143 | spin_unlock_bh(&t->stid_lock); | |
1144 | return stid; | |
1145 | } | |
1146 | EXPORT_SYMBOL(cxgb4_alloc_sftid); | |
1147 | ||
1148 | /* Release a server TID. | |
b8ff05a9 DM |
1149 | */ |
1150 | void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) | |
1151 | { | |
470c60c4 KS |
1152 | /* Is it a server filter TID? */ |
1153 | if (t->nsftids && (stid >= t->sftid_base)) { | |
1154 | stid -= t->sftid_base; | |
1155 | stid += t->nstids; | |
1156 | } else { | |
1157 | stid -= t->stid_base; | |
1158 | } | |
1159 | ||
b8ff05a9 DM |
1160 | spin_lock_bh(&t->stid_lock); |
1161 | if (family == PF_INET) | |
1162 | __clear_bit(stid, t->stid_bmap); | |
1163 | else | |
a99c683e | 1164 | bitmap_release_region(t->stid_bmap, stid, 1); |
b8ff05a9 | 1165 | t->stid_tab[stid].data = NULL; |
2248b293 | 1166 | if (stid < t->nstids) { |
1dec4cec | 1167 | if (family == PF_INET6) { |
a99c683e | 1168 | t->stids_in_use -= 2; |
1dec4cec GG |
1169 | t->v6_stids_in_use -= 2; |
1170 | } else { | |
1171 | t->stids_in_use--; | |
1172 | } | |
2248b293 HS |
1173 | } else { |
1174 | t->sftids_in_use--; | |
1175 | } | |
1dec4cec | 1176 | |
b8ff05a9 DM |
1177 | spin_unlock_bh(&t->stid_lock); |
1178 | } | |
1179 | EXPORT_SYMBOL(cxgb4_free_stid); | |
1180 | ||
1181 | /* | |
1182 | * Populate a TID_RELEASE WR. Caller must properly size the skb. | |
1183 | */ | |
1184 | static void mk_tid_release(struct sk_buff *skb, unsigned int chan, | |
1185 | unsigned int tid) | |
1186 | { | |
1187 | struct cpl_tid_release *req; | |
1188 | ||
1189 | set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); | |
4df864c1 | 1190 | req = __skb_put(skb, sizeof(*req)); |
b8ff05a9 DM |
1191 | INIT_TP_WR(req, tid); |
1192 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); | |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * Queue a TID release request and if necessary schedule a work queue to | |
1197 | * process it. | |
1198 | */ | |
31b9c19b | 1199 | static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, |
1200 | unsigned int tid) | |
b8ff05a9 DM |
1201 | { |
1202 | void **p = &t->tid_tab[tid]; | |
1203 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1204 | ||
1205 | spin_lock_bh(&adap->tid_release_lock); | |
1206 | *p = adap->tid_release_head; | |
1207 | /* Low 2 bits encode the Tx channel number */ | |
1208 | adap->tid_release_head = (void **)((uintptr_t)p | chan); | |
1209 | if (!adap->tid_release_task_busy) { | |
1210 | adap->tid_release_task_busy = true; | |
29aaee65 | 1211 | queue_work(adap->workq, &adap->tid_release_task); |
b8ff05a9 DM |
1212 | } |
1213 | spin_unlock_bh(&adap->tid_release_lock); | |
1214 | } | |
b8ff05a9 DM |
1215 | |
1216 | /* | |
1217 | * Process the list of pending TID release requests. | |
1218 | */ | |
1219 | static void process_tid_release_list(struct work_struct *work) | |
1220 | { | |
1221 | struct sk_buff *skb; | |
1222 | struct adapter *adap; | |
1223 | ||
1224 | adap = container_of(work, struct adapter, tid_release_task); | |
1225 | ||
1226 | spin_lock_bh(&adap->tid_release_lock); | |
1227 | while (adap->tid_release_head) { | |
1228 | void **p = adap->tid_release_head; | |
1229 | unsigned int chan = (uintptr_t)p & 3; | |
1230 | p = (void *)p - chan; | |
1231 | ||
1232 | adap->tid_release_head = *p; | |
1233 | *p = NULL; | |
1234 | spin_unlock_bh(&adap->tid_release_lock); | |
1235 | ||
1236 | while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), | |
1237 | GFP_KERNEL))) | |
1238 | schedule_timeout_uninterruptible(1); | |
1239 | ||
1240 | mk_tid_release(skb, chan, p - adap->tids.tid_tab); | |
1241 | t4_ofld_send(adap, skb); | |
1242 | spin_lock_bh(&adap->tid_release_lock); | |
1243 | } | |
1244 | adap->tid_release_task_busy = false; | |
1245 | spin_unlock_bh(&adap->tid_release_lock); | |
1246 | } | |
1247 | ||
1248 | /* | |
1249 | * Release a TID and inform HW. If we are unable to allocate the release | |
1250 | * message we defer to a work queue. | |
1251 | */ | |
1dec4cec GG |
1252 | void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, |
1253 | unsigned short family) | |
b8ff05a9 | 1254 | { |
b8ff05a9 DM |
1255 | struct sk_buff *skb; |
1256 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1257 | ||
9a1bb9f6 HS |
1258 | WARN_ON(tid >= t->ntids); |
1259 | ||
1260 | if (t->tid_tab[tid]) { | |
1261 | t->tid_tab[tid] = NULL; | |
1dec4cec GG |
1262 | atomic_dec(&t->conns_in_use); |
1263 | if (t->hash_base && (tid >= t->hash_base)) { | |
1264 | if (family == AF_INET6) | |
1265 | atomic_sub(2, &t->hash_tids_in_use); | |
1266 | else | |
1267 | atomic_dec(&t->hash_tids_in_use); | |
1268 | } else { | |
1269 | if (family == AF_INET6) | |
1270 | atomic_sub(2, &t->tids_in_use); | |
1271 | else | |
1272 | atomic_dec(&t->tids_in_use); | |
1273 | } | |
9a1bb9f6 HS |
1274 | } |
1275 | ||
b8ff05a9 DM |
1276 | skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); |
1277 | if (likely(skb)) { | |
b8ff05a9 DM |
1278 | mk_tid_release(skb, chan, tid); |
1279 | t4_ofld_send(adap, skb); | |
1280 | } else | |
1281 | cxgb4_queue_tid_release(t, chan, tid); | |
b8ff05a9 DM |
1282 | } |
1283 | EXPORT_SYMBOL(cxgb4_remove_tid); | |
1284 | ||
1285 | /* | |
1286 | * Allocate and initialize the TID tables. Returns 0 on success. | |
1287 | */ | |
1288 | static int tid_init(struct tid_info *t) | |
1289 | { | |
b6f8eaec | 1290 | struct adapter *adap = container_of(t, struct adapter, tids); |
578b46b9 RL |
1291 | unsigned int max_ftids = t->nftids + t->nsftids; |
1292 | unsigned int natids = t->natids; | |
1293 | unsigned int stid_bmap_size; | |
1294 | unsigned int ftid_bmap_size; | |
1295 | size_t size; | |
b8ff05a9 | 1296 | |
dca4faeb | 1297 | stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); |
578b46b9 | 1298 | ftid_bmap_size = BITS_TO_LONGS(t->nftids); |
f2b7e78d VP |
1299 | size = t->ntids * sizeof(*t->tid_tab) + |
1300 | natids * sizeof(*t->atid_tab) + | |
b8ff05a9 | 1301 | t->nstids * sizeof(*t->stid_tab) + |
dca4faeb | 1302 | t->nsftids * sizeof(*t->stid_tab) + |
f2b7e78d | 1303 | stid_bmap_size * sizeof(long) + |
578b46b9 RL |
1304 | max_ftids * sizeof(*t->ftid_tab) + |
1305 | ftid_bmap_size * sizeof(long); | |
f2b7e78d | 1306 | |
752ade68 | 1307 | t->tid_tab = kvzalloc(size, GFP_KERNEL); |
b8ff05a9 DM |
1308 | if (!t->tid_tab) |
1309 | return -ENOMEM; | |
1310 | ||
1311 | t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; | |
1312 | t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; | |
dca4faeb | 1313 | t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; |
f2b7e78d | 1314 | t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; |
578b46b9 | 1315 | t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids]; |
b8ff05a9 DM |
1316 | spin_lock_init(&t->stid_lock); |
1317 | spin_lock_init(&t->atid_lock); | |
578b46b9 | 1318 | spin_lock_init(&t->ftid_lock); |
b8ff05a9 DM |
1319 | |
1320 | t->stids_in_use = 0; | |
1dec4cec | 1321 | t->v6_stids_in_use = 0; |
2248b293 | 1322 | t->sftids_in_use = 0; |
b8ff05a9 DM |
1323 | t->afree = NULL; |
1324 | t->atids_in_use = 0; | |
1325 | atomic_set(&t->tids_in_use, 0); | |
1dec4cec | 1326 | atomic_set(&t->conns_in_use, 0); |
9a1bb9f6 | 1327 | atomic_set(&t->hash_tids_in_use, 0); |
b8ff05a9 DM |
1328 | |
1329 | /* Setup the free list for atid_tab and clear the stid bitmap. */ | |
1330 | if (natids) { | |
1331 | while (--natids) | |
1332 | t->atid_tab[natids - 1].next = &t->atid_tab[natids]; | |
1333 | t->afree = t->atid_tab; | |
1334 | } | |
b6f8eaec | 1335 | |
578b46b9 RL |
1336 | if (is_offload(adap)) { |
1337 | bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); | |
1338 | /* Reserve stid 0 for T4/T5 adapters */ | |
1339 | if (!t->stid_base && | |
1340 | CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) | |
1341 | __set_bit(0, t->stid_bmap); | |
1342 | } | |
1343 | ||
1344 | bitmap_zero(t->ftid_bmap, t->nftids); | |
b8ff05a9 DM |
1345 | return 0; |
1346 | } | |
1347 | ||
1348 | /** | |
1349 | * cxgb4_create_server - create an IP server | |
1350 | * @dev: the device | |
1351 | * @stid: the server TID | |
1352 | * @sip: local IP address to bind server to | |
1353 | * @sport: the server's TCP port | |
1354 | * @queue: queue to direct messages from this server to | |
1355 | * | |
1356 | * Create an IP server for the given port and address. | |
1357 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1358 | */ | |
1359 | int cxgb4_create_server(const struct net_device *dev, unsigned int stid, | |
793dad94 VP |
1360 | __be32 sip, __be16 sport, __be16 vlan, |
1361 | unsigned int queue) | |
b8ff05a9 DM |
1362 | { |
1363 | unsigned int chan; | |
1364 | struct sk_buff *skb; | |
1365 | struct adapter *adap; | |
1366 | struct cpl_pass_open_req *req; | |
80f40c1f | 1367 | int ret; |
b8ff05a9 DM |
1368 | |
1369 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1370 | if (!skb) | |
1371 | return -ENOMEM; | |
1372 | ||
1373 | adap = netdev2adap(dev); | |
4df864c1 | 1374 | req = __skb_put(skb, sizeof(*req)); |
b8ff05a9 DM |
1375 | INIT_TP_WR(req, 0); |
1376 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); | |
1377 | req->local_port = sport; | |
1378 | req->peer_port = htons(0); | |
1379 | req->local_ip = sip; | |
1380 | req->peer_ip = htonl(0); | |
e46dab4d | 1381 | chan = rxq_to_chan(&adap->sge, queue); |
d7990b0c | 1382 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1383 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1384 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1385 | ret = t4_mgmt_tx(adap, skb); |
1386 | return net_xmit_eval(ret); | |
b8ff05a9 DM |
1387 | } |
1388 | EXPORT_SYMBOL(cxgb4_create_server); | |
1389 | ||
80f40c1f VP |
1390 | /* cxgb4_create_server6 - create an IPv6 server |
1391 | * @dev: the device | |
1392 | * @stid: the server TID | |
1393 | * @sip: local IPv6 address to bind server to | |
1394 | * @sport: the server's TCP port | |
1395 | * @queue: queue to direct messages from this server to | |
1396 | * | |
1397 | * Create an IPv6 server for the given port and address. | |
1398 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1399 | */ | |
1400 | int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, | |
1401 | const struct in6_addr *sip, __be16 sport, | |
1402 | unsigned int queue) | |
1403 | { | |
1404 | unsigned int chan; | |
1405 | struct sk_buff *skb; | |
1406 | struct adapter *adap; | |
1407 | struct cpl_pass_open_req6 *req; | |
1408 | int ret; | |
1409 | ||
1410 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1411 | if (!skb) | |
1412 | return -ENOMEM; | |
1413 | ||
1414 | adap = netdev2adap(dev); | |
4df864c1 | 1415 | req = __skb_put(skb, sizeof(*req)); |
80f40c1f VP |
1416 | INIT_TP_WR(req, 0); |
1417 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); | |
1418 | req->local_port = sport; | |
1419 | req->peer_port = htons(0); | |
1420 | req->local_ip_hi = *(__be64 *)(sip->s6_addr); | |
1421 | req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); | |
1422 | req->peer_ip_hi = cpu_to_be64(0); | |
1423 | req->peer_ip_lo = cpu_to_be64(0); | |
1424 | chan = rxq_to_chan(&adap->sge, queue); | |
d7990b0c | 1425 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1426 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1427 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1428 | ret = t4_mgmt_tx(adap, skb); |
1429 | return net_xmit_eval(ret); | |
1430 | } | |
1431 | EXPORT_SYMBOL(cxgb4_create_server6); | |
1432 | ||
1433 | int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, | |
1434 | unsigned int queue, bool ipv6) | |
1435 | { | |
1436 | struct sk_buff *skb; | |
1437 | struct adapter *adap; | |
1438 | struct cpl_close_listsvr_req *req; | |
1439 | int ret; | |
1440 | ||
1441 | adap = netdev2adap(dev); | |
1442 | ||
1443 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1444 | if (!skb) | |
1445 | return -ENOMEM; | |
1446 | ||
4df864c1 | 1447 | req = __skb_put(skb, sizeof(*req)); |
80f40c1f VP |
1448 | INIT_TP_WR(req, 0); |
1449 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); | |
bdc590b9 HS |
1450 | req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : |
1451 | LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); | |
80f40c1f VP |
1452 | ret = t4_mgmt_tx(adap, skb); |
1453 | return net_xmit_eval(ret); | |
1454 | } | |
1455 | EXPORT_SYMBOL(cxgb4_remove_server); | |
1456 | ||
b8ff05a9 DM |
1457 | /** |
1458 | * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU | |
1459 | * @mtus: the HW MTU table | |
1460 | * @mtu: the target MTU | |
1461 | * @idx: index of selected entry in the MTU table | |
1462 | * | |
1463 | * Returns the index and the value in the HW MTU table that is closest to | |
1464 | * but does not exceed @mtu, unless @mtu is smaller than any value in the | |
1465 | * table, in which case that smallest available value is selected. | |
1466 | */ | |
1467 | unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, | |
1468 | unsigned int *idx) | |
1469 | { | |
1470 | unsigned int i = 0; | |
1471 | ||
1472 | while (i < NMTUS - 1 && mtus[i + 1] <= mtu) | |
1473 | ++i; | |
1474 | if (idx) | |
1475 | *idx = i; | |
1476 | return mtus[i]; | |
1477 | } | |
1478 | EXPORT_SYMBOL(cxgb4_best_mtu); | |
1479 | ||
92e7ae71 HS |
1480 | /** |
1481 | * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned | |
1482 | * @mtus: the HW MTU table | |
1483 | * @header_size: Header Size | |
1484 | * @data_size_max: maximum Data Segment Size | |
1485 | * @data_size_align: desired Data Segment Size Alignment (2^N) | |
1486 | * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) | |
1487 | * | |
1488 | * Similar to cxgb4_best_mtu() but instead of searching the Hardware | |
1489 | * MTU Table based solely on a Maximum MTU parameter, we break that | |
1490 | * parameter up into a Header Size and Maximum Data Segment Size, and | |
1491 | * provide a desired Data Segment Size Alignment. If we find an MTU in | |
1492 | * the Hardware MTU Table which will result in a Data Segment Size with | |
1493 | * the requested alignment _and_ that MTU isn't "too far" from the | |
1494 | * closest MTU, then we'll return that rather than the closest MTU. | |
1495 | */ | |
1496 | unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, | |
1497 | unsigned short header_size, | |
1498 | unsigned short data_size_max, | |
1499 | unsigned short data_size_align, | |
1500 | unsigned int *mtu_idxp) | |
1501 | { | |
1502 | unsigned short max_mtu = header_size + data_size_max; | |
1503 | unsigned short data_size_align_mask = data_size_align - 1; | |
1504 | int mtu_idx, aligned_mtu_idx; | |
1505 | ||
1506 | /* Scan the MTU Table till we find an MTU which is larger than our | |
1507 | * Maximum MTU or we reach the end of the table. Along the way, | |
1508 | * record the last MTU found, if any, which will result in a Data | |
1509 | * Segment Length matching the requested alignment. | |
1510 | */ | |
1511 | for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { | |
1512 | unsigned short data_size = mtus[mtu_idx] - header_size; | |
1513 | ||
1514 | /* If this MTU minus the Header Size would result in a | |
1515 | * Data Segment Size of the desired alignment, remember it. | |
1516 | */ | |
1517 | if ((data_size & data_size_align_mask) == 0) | |
1518 | aligned_mtu_idx = mtu_idx; | |
1519 | ||
1520 | /* If we're not at the end of the Hardware MTU Table and the | |
1521 | * next element is larger than our Maximum MTU, drop out of | |
1522 | * the loop. | |
1523 | */ | |
1524 | if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) | |
1525 | break; | |
1526 | } | |
1527 | ||
1528 | /* If we fell out of the loop because we ran to the end of the table, | |
1529 | * then we just have to use the last [largest] entry. | |
1530 | */ | |
1531 | if (mtu_idx == NMTUS) | |
1532 | mtu_idx--; | |
1533 | ||
1534 | /* If we found an MTU which resulted in the requested Data Segment | |
1535 | * Length alignment and that's "not far" from the largest MTU which is | |
1536 | * less than or equal to the maximum MTU, then use that. | |
1537 | */ | |
1538 | if (aligned_mtu_idx >= 0 && | |
1539 | mtu_idx - aligned_mtu_idx <= 1) | |
1540 | mtu_idx = aligned_mtu_idx; | |
1541 | ||
1542 | /* If the caller has passed in an MTU Index pointer, pass the | |
1543 | * MTU Index back. Return the MTU value. | |
1544 | */ | |
1545 | if (mtu_idxp) | |
1546 | *mtu_idxp = mtu_idx; | |
1547 | return mtus[mtu_idx]; | |
1548 | } | |
1549 | EXPORT_SYMBOL(cxgb4_best_aligned_mtu); | |
1550 | ||
27999805 H |
1551 | /** |
1552 | * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI | |
1553 | * @chip: chip type | |
1554 | * @viid: VI id of the given port | |
1555 | * | |
1556 | * Return the SMT index for this VI. | |
1557 | */ | |
1558 | unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid) | |
1559 | { | |
1560 | /* In T4/T5, SMT contains 256 SMAC entries organized in | |
1561 | * 128 rows of 2 entries each. | |
1562 | * In T6, SMT contains 256 SMAC entries in 256 rows. | |
1563 | * TODO: The below code needs to be updated when we add support | |
1564 | * for 256 VFs. | |
1565 | */ | |
1566 | if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) | |
1567 | return ((viid & 0x7f) << 1); | |
1568 | else | |
1569 | return (viid & 0x7f); | |
1570 | } | |
1571 | EXPORT_SYMBOL(cxgb4_tp_smt_idx); | |
1572 | ||
b8ff05a9 DM |
1573 | /** |
1574 | * cxgb4_port_chan - get the HW channel of a port | |
1575 | * @dev: the net device for the port | |
1576 | * | |
1577 | * Return the HW Tx channel of the given port. | |
1578 | */ | |
1579 | unsigned int cxgb4_port_chan(const struct net_device *dev) | |
1580 | { | |
1581 | return netdev2pinfo(dev)->tx_chan; | |
1582 | } | |
1583 | EXPORT_SYMBOL(cxgb4_port_chan); | |
1584 | ||
881806bc VP |
1585 | unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) |
1586 | { | |
1587 | struct adapter *adap = netdev2adap(dev); | |
2cc301d2 | 1588 | u32 v1, v2, lp_count, hp_count; |
881806bc | 1589 | |
f061de42 HS |
1590 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
1591 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 1592 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
1593 | lp_count = LP_COUNT_G(v1); |
1594 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 1595 | } else { |
f061de42 HS |
1596 | lp_count = LP_COUNT_T5_G(v1); |
1597 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
1598 | } |
1599 | return lpfifo ? lp_count : hp_count; | |
881806bc VP |
1600 | } |
1601 | EXPORT_SYMBOL(cxgb4_dbfifo_count); | |
1602 | ||
b8ff05a9 DM |
1603 | /** |
1604 | * cxgb4_port_viid - get the VI id of a port | |
1605 | * @dev: the net device for the port | |
1606 | * | |
1607 | * Return the VI id of the given port. | |
1608 | */ | |
1609 | unsigned int cxgb4_port_viid(const struct net_device *dev) | |
1610 | { | |
1611 | return netdev2pinfo(dev)->viid; | |
1612 | } | |
1613 | EXPORT_SYMBOL(cxgb4_port_viid); | |
1614 | ||
1615 | /** | |
1616 | * cxgb4_port_idx - get the index of a port | |
1617 | * @dev: the net device for the port | |
1618 | * | |
1619 | * Return the index of the given port. | |
1620 | */ | |
1621 | unsigned int cxgb4_port_idx(const struct net_device *dev) | |
1622 | { | |
1623 | return netdev2pinfo(dev)->port_id; | |
1624 | } | |
1625 | EXPORT_SYMBOL(cxgb4_port_idx); | |
1626 | ||
b8ff05a9 DM |
1627 | void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, |
1628 | struct tp_tcp_stats *v6) | |
1629 | { | |
1630 | struct adapter *adap = pci_get_drvdata(pdev); | |
1631 | ||
1632 | spin_lock(&adap->stats_lock); | |
1633 | t4_tp_get_tcp_stats(adap, v4, v6); | |
1634 | spin_unlock(&adap->stats_lock); | |
1635 | } | |
1636 | EXPORT_SYMBOL(cxgb4_get_tcp_stats); | |
1637 | ||
1638 | void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, | |
1639 | const unsigned int *pgsz_order) | |
1640 | { | |
1641 | struct adapter *adap = netdev2adap(dev); | |
1642 | ||
0d804338 HS |
1643 | t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); |
1644 | t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | | |
1645 | HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | | |
1646 | HPZ3_V(pgsz_order[3])); | |
b8ff05a9 DM |
1647 | } |
1648 | EXPORT_SYMBOL(cxgb4_iscsi_init); | |
1649 | ||
3069ee9b VP |
1650 | int cxgb4_flush_eq_cache(struct net_device *dev) |
1651 | { | |
1652 | struct adapter *adap = netdev2adap(dev); | |
3069ee9b | 1653 | |
5d700ecb | 1654 | return t4_sge_ctxt_flush(adap, adap->mbox); |
3069ee9b VP |
1655 | } |
1656 | EXPORT_SYMBOL(cxgb4_flush_eq_cache); | |
1657 | ||
1658 | static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) | |
1659 | { | |
f061de42 | 1660 | u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; |
3069ee9b VP |
1661 | __be64 indices; |
1662 | int ret; | |
1663 | ||
fc5ab020 HS |
1664 | spin_lock(&adap->win0_lock); |
1665 | ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, | |
1666 | sizeof(indices), (__be32 *)&indices, | |
1667 | T4_MEMORY_READ); | |
1668 | spin_unlock(&adap->win0_lock); | |
3069ee9b | 1669 | if (!ret) { |
404d9e3f VP |
1670 | *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; |
1671 | *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; | |
3069ee9b VP |
1672 | } |
1673 | return ret; | |
1674 | } | |
1675 | ||
1676 | int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, | |
1677 | u16 size) | |
1678 | { | |
1679 | struct adapter *adap = netdev2adap(dev); | |
1680 | u16 hw_pidx, hw_cidx; | |
1681 | int ret; | |
1682 | ||
1683 | ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); | |
1684 | if (ret) | |
1685 | goto out; | |
1686 | ||
1687 | if (pidx != hw_pidx) { | |
1688 | u16 delta; | |
f612b815 | 1689 | u32 val; |
3069ee9b VP |
1690 | |
1691 | if (pidx >= hw_pidx) | |
1692 | delta = pidx - hw_pidx; | |
1693 | else | |
1694 | delta = size - hw_pidx + pidx; | |
f612b815 HS |
1695 | |
1696 | if (is_t4(adap->params.chip)) | |
1697 | val = PIDX_V(delta); | |
1698 | else | |
1699 | val = PIDX_T5_V(delta); | |
3069ee9b | 1700 | wmb(); |
f612b815 HS |
1701 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
1702 | QID_V(qid) | val); | |
3069ee9b VP |
1703 | } |
1704 | out: | |
1705 | return ret; | |
1706 | } | |
1707 | EXPORT_SYMBOL(cxgb4_sync_txq_pidx); | |
1708 | ||
031cf476 HS |
1709 | int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) |
1710 | { | |
1711 | struct adapter *adap; | |
1712 | u32 offset, memtype, memaddr; | |
6559a7e8 | 1713 | u32 edc0_size, edc1_size, mc0_size, mc1_size, size; |
031cf476 HS |
1714 | u32 edc0_end, edc1_end, mc0_end, mc1_end; |
1715 | int ret; | |
1716 | ||
1717 | adap = netdev2adap(dev); | |
1718 | ||
1719 | offset = ((stag >> 8) * 32) + adap->vres.stag.start; | |
1720 | ||
1721 | /* Figure out where the offset lands in the Memory Type/Address scheme. | |
1722 | * This code assumes that the memory is laid out starting at offset 0 | |
1723 | * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 | |
1724 | * and EDC1. Some cards will have neither MC0 nor MC1, most cards have | |
1725 | * MC0, and some have both MC0 and MC1. | |
1726 | */ | |
6559a7e8 HS |
1727 | size = t4_read_reg(adap, MA_EDRAM0_BAR_A); |
1728 | edc0_size = EDRAM0_SIZE_G(size) << 20; | |
1729 | size = t4_read_reg(adap, MA_EDRAM1_BAR_A); | |
1730 | edc1_size = EDRAM1_SIZE_G(size) << 20; | |
1731 | size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); | |
1732 | mc0_size = EXT_MEM0_SIZE_G(size) << 20; | |
031cf476 HS |
1733 | |
1734 | edc0_end = edc0_size; | |
1735 | edc1_end = edc0_end + edc1_size; | |
1736 | mc0_end = edc1_end + mc0_size; | |
1737 | ||
1738 | if (offset < edc0_end) { | |
1739 | memtype = MEM_EDC0; | |
1740 | memaddr = offset; | |
1741 | } else if (offset < edc1_end) { | |
1742 | memtype = MEM_EDC1; | |
1743 | memaddr = offset - edc0_end; | |
1744 | } else { | |
1745 | if (offset < mc0_end) { | |
1746 | memtype = MEM_MC0; | |
1747 | memaddr = offset - edc1_end; | |
3ccc6cf7 | 1748 | } else if (is_t5(adap->params.chip)) { |
6559a7e8 HS |
1749 | size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); |
1750 | mc1_size = EXT_MEM1_SIZE_G(size) << 20; | |
031cf476 HS |
1751 | mc1_end = mc0_end + mc1_size; |
1752 | if (offset < mc1_end) { | |
1753 | memtype = MEM_MC1; | |
1754 | memaddr = offset - mc0_end; | |
1755 | } else { | |
1756 | /* offset beyond the end of any memory */ | |
1757 | goto err; | |
1758 | } | |
3ccc6cf7 HS |
1759 | } else { |
1760 | /* T4/T6 only has a single memory channel */ | |
1761 | goto err; | |
031cf476 HS |
1762 | } |
1763 | } | |
1764 | ||
1765 | spin_lock(&adap->win0_lock); | |
1766 | ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); | |
1767 | spin_unlock(&adap->win0_lock); | |
1768 | return ret; | |
1769 | ||
1770 | err: | |
1771 | dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", | |
1772 | stag, offset); | |
1773 | return -EINVAL; | |
1774 | } | |
1775 | EXPORT_SYMBOL(cxgb4_read_tpte); | |
1776 | ||
7730b4c7 HS |
1777 | u64 cxgb4_read_sge_timestamp(struct net_device *dev) |
1778 | { | |
1779 | u32 hi, lo; | |
1780 | struct adapter *adap; | |
1781 | ||
1782 | adap = netdev2adap(dev); | |
f612b815 HS |
1783 | lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); |
1784 | hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); | |
7730b4c7 HS |
1785 | |
1786 | return ((u64)hi << 32) | (u64)lo; | |
1787 | } | |
1788 | EXPORT_SYMBOL(cxgb4_read_sge_timestamp); | |
1789 | ||
df64e4d3 HS |
1790 | int cxgb4_bar2_sge_qregs(struct net_device *dev, |
1791 | unsigned int qid, | |
1792 | enum cxgb4_bar2_qtype qtype, | |
66cf188e | 1793 | int user, |
df64e4d3 HS |
1794 | u64 *pbar2_qoffset, |
1795 | unsigned int *pbar2_qid) | |
1796 | { | |
b2612722 | 1797 | return t4_bar2_sge_qregs(netdev2adap(dev), |
df64e4d3 HS |
1798 | qid, |
1799 | (qtype == CXGB4_BAR2_QTYPE_EGRESS | |
1800 | ? T4_BAR2_QTYPE_EGRESS | |
1801 | : T4_BAR2_QTYPE_INGRESS), | |
66cf188e | 1802 | user, |
df64e4d3 HS |
1803 | pbar2_qoffset, |
1804 | pbar2_qid); | |
1805 | } | |
1806 | EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); | |
1807 | ||
b8ff05a9 DM |
1808 | static struct pci_driver cxgb4_driver; |
1809 | ||
1810 | static void check_neigh_update(struct neighbour *neigh) | |
1811 | { | |
1812 | const struct device *parent; | |
1813 | const struct net_device *netdev = neigh->dev; | |
1814 | ||
d0d7b10b | 1815 | if (is_vlan_dev(netdev)) |
b8ff05a9 DM |
1816 | netdev = vlan_dev_real_dev(netdev); |
1817 | parent = netdev->dev.parent; | |
1818 | if (parent && parent->driver == &cxgb4_driver.driver) | |
1819 | t4_l2t_update(dev_get_drvdata(parent), neigh); | |
1820 | } | |
1821 | ||
1822 | static int netevent_cb(struct notifier_block *nb, unsigned long event, | |
1823 | void *data) | |
1824 | { | |
1825 | switch (event) { | |
1826 | case NETEVENT_NEIGH_UPDATE: | |
1827 | check_neigh_update(data); | |
1828 | break; | |
b8ff05a9 DM |
1829 | case NETEVENT_REDIRECT: |
1830 | default: | |
1831 | break; | |
1832 | } | |
1833 | return 0; | |
1834 | } | |
1835 | ||
1836 | static bool netevent_registered; | |
1837 | static struct notifier_block cxgb4_netevent_nb = { | |
1838 | .notifier_call = netevent_cb | |
1839 | }; | |
1840 | ||
3069ee9b VP |
1841 | static void drain_db_fifo(struct adapter *adap, int usecs) |
1842 | { | |
2cc301d2 | 1843 | u32 v1, v2, lp_count, hp_count; |
3069ee9b VP |
1844 | |
1845 | do { | |
f061de42 HS |
1846 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
1847 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 1848 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
1849 | lp_count = LP_COUNT_G(v1); |
1850 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 1851 | } else { |
f061de42 HS |
1852 | lp_count = LP_COUNT_T5_G(v1); |
1853 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
1854 | } |
1855 | ||
1856 | if (lp_count == 0 && hp_count == 0) | |
1857 | break; | |
3069ee9b VP |
1858 | set_current_state(TASK_UNINTERRUPTIBLE); |
1859 | schedule_timeout(usecs_to_jiffies(usecs)); | |
3069ee9b VP |
1860 | } while (1); |
1861 | } | |
1862 | ||
1863 | static void disable_txq_db(struct sge_txq *q) | |
1864 | { | |
05eb2389 SW |
1865 | unsigned long flags; |
1866 | ||
1867 | spin_lock_irqsave(&q->db_lock, flags); | |
3069ee9b | 1868 | q->db_disabled = 1; |
05eb2389 | 1869 | spin_unlock_irqrestore(&q->db_lock, flags); |
3069ee9b VP |
1870 | } |
1871 | ||
05eb2389 | 1872 | static void enable_txq_db(struct adapter *adap, struct sge_txq *q) |
3069ee9b VP |
1873 | { |
1874 | spin_lock_irq(&q->db_lock); | |
05eb2389 SW |
1875 | if (q->db_pidx_inc) { |
1876 | /* Make sure that all writes to the TX descriptors | |
1877 | * are committed before we tell HW about them. | |
1878 | */ | |
1879 | wmb(); | |
f612b815 HS |
1880 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
1881 | QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); | |
05eb2389 SW |
1882 | q->db_pidx_inc = 0; |
1883 | } | |
3069ee9b VP |
1884 | q->db_disabled = 0; |
1885 | spin_unlock_irq(&q->db_lock); | |
1886 | } | |
1887 | ||
1888 | static void disable_dbs(struct adapter *adap) | |
1889 | { | |
1890 | int i; | |
1891 | ||
1892 | for_each_ethrxq(&adap->sge, i) | |
1893 | disable_txq_db(&adap->sge.ethtxq[i].q); | |
ab677ff4 HS |
1894 | if (is_offload(adap)) { |
1895 | struct sge_uld_txq_info *txq_info = | |
1896 | adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
1897 | ||
1898 | if (txq_info) { | |
1899 | for_each_ofldtxq(&adap->sge, i) { | |
1900 | struct sge_uld_txq *txq = &txq_info->uldtxq[i]; | |
1901 | ||
1902 | disable_txq_db(&txq->q); | |
1903 | } | |
1904 | } | |
1905 | } | |
3069ee9b VP |
1906 | for_each_port(adap, i) |
1907 | disable_txq_db(&adap->sge.ctrlq[i].q); | |
1908 | } | |
1909 | ||
1910 | static void enable_dbs(struct adapter *adap) | |
1911 | { | |
1912 | int i; | |
1913 | ||
1914 | for_each_ethrxq(&adap->sge, i) | |
05eb2389 | 1915 | enable_txq_db(adap, &adap->sge.ethtxq[i].q); |
ab677ff4 HS |
1916 | if (is_offload(adap)) { |
1917 | struct sge_uld_txq_info *txq_info = | |
1918 | adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
1919 | ||
1920 | if (txq_info) { | |
1921 | for_each_ofldtxq(&adap->sge, i) { | |
1922 | struct sge_uld_txq *txq = &txq_info->uldtxq[i]; | |
1923 | ||
1924 | enable_txq_db(adap, &txq->q); | |
1925 | } | |
1926 | } | |
1927 | } | |
3069ee9b | 1928 | for_each_port(adap, i) |
05eb2389 SW |
1929 | enable_txq_db(adap, &adap->sge.ctrlq[i].q); |
1930 | } | |
1931 | ||
1932 | static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) | |
1933 | { | |
0fbc81b3 HS |
1934 | enum cxgb4_uld type = CXGB4_ULD_RDMA; |
1935 | ||
1936 | if (adap->uld && adap->uld[type].handle) | |
1937 | adap->uld[type].control(adap->uld[type].handle, cmd); | |
05eb2389 SW |
1938 | } |
1939 | ||
1940 | static void process_db_full(struct work_struct *work) | |
1941 | { | |
1942 | struct adapter *adap; | |
1943 | ||
1944 | adap = container_of(work, struct adapter, db_full_task); | |
1945 | ||
1946 | drain_db_fifo(adap, dbfifo_drain_delay); | |
1947 | enable_dbs(adap); | |
1948 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); | |
3ccc6cf7 HS |
1949 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
1950 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
1951 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, | |
1952 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); | |
1953 | else | |
1954 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
1955 | DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); | |
3069ee9b VP |
1956 | } |
1957 | ||
1958 | static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) | |
1959 | { | |
1960 | u16 hw_pidx, hw_cidx; | |
1961 | int ret; | |
1962 | ||
05eb2389 | 1963 | spin_lock_irq(&q->db_lock); |
3069ee9b VP |
1964 | ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); |
1965 | if (ret) | |
1966 | goto out; | |
1967 | if (q->db_pidx != hw_pidx) { | |
1968 | u16 delta; | |
f612b815 | 1969 | u32 val; |
3069ee9b VP |
1970 | |
1971 | if (q->db_pidx >= hw_pidx) | |
1972 | delta = q->db_pidx - hw_pidx; | |
1973 | else | |
1974 | delta = q->size - hw_pidx + q->db_pidx; | |
f612b815 HS |
1975 | |
1976 | if (is_t4(adap->params.chip)) | |
1977 | val = PIDX_V(delta); | |
1978 | else | |
1979 | val = PIDX_T5_V(delta); | |
3069ee9b | 1980 | wmb(); |
f612b815 HS |
1981 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
1982 | QID_V(q->cntxt_id) | val); | |
3069ee9b VP |
1983 | } |
1984 | out: | |
1985 | q->db_disabled = 0; | |
05eb2389 SW |
1986 | q->db_pidx_inc = 0; |
1987 | spin_unlock_irq(&q->db_lock); | |
3069ee9b VP |
1988 | if (ret) |
1989 | CH_WARN(adap, "DB drop recovery failed.\n"); | |
1990 | } | |
0fbc81b3 | 1991 | |
3069ee9b VP |
1992 | static void recover_all_queues(struct adapter *adap) |
1993 | { | |
1994 | int i; | |
1995 | ||
1996 | for_each_ethrxq(&adap->sge, i) | |
1997 | sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); | |
ab677ff4 HS |
1998 | if (is_offload(adap)) { |
1999 | struct sge_uld_txq_info *txq_info = | |
2000 | adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
2001 | if (txq_info) { | |
2002 | for_each_ofldtxq(&adap->sge, i) { | |
2003 | struct sge_uld_txq *txq = &txq_info->uldtxq[i]; | |
2004 | ||
2005 | sync_txq_pidx(adap, &txq->q); | |
2006 | } | |
2007 | } | |
2008 | } | |
3069ee9b VP |
2009 | for_each_port(adap, i) |
2010 | sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); | |
2011 | } | |
2012 | ||
881806bc VP |
2013 | static void process_db_drop(struct work_struct *work) |
2014 | { | |
2015 | struct adapter *adap; | |
881806bc | 2016 | |
3069ee9b | 2017 | adap = container_of(work, struct adapter, db_drop_task); |
881806bc | 2018 | |
d14807dd | 2019 | if (is_t4(adap->params.chip)) { |
05eb2389 | 2020 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2021 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); |
05eb2389 | 2022 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2023 | recover_all_queues(adap); |
05eb2389 | 2024 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2025 | enable_dbs(adap); |
05eb2389 | 2026 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); |
3ccc6cf7 | 2027 | } else if (is_t5(adap->params.chip)) { |
2cc301d2 SR |
2028 | u32 dropped_db = t4_read_reg(adap, 0x010ac); |
2029 | u16 qid = (dropped_db >> 15) & 0x1ffff; | |
2030 | u16 pidx_inc = dropped_db & 0x1fff; | |
df64e4d3 HS |
2031 | u64 bar2_qoffset; |
2032 | unsigned int bar2_qid; | |
2033 | int ret; | |
2cc301d2 | 2034 | |
b2612722 | 2035 | ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, |
e0456717 | 2036 | 0, &bar2_qoffset, &bar2_qid); |
df64e4d3 HS |
2037 | if (ret) |
2038 | dev_err(adap->pdev_dev, "doorbell drop recovery: " | |
2039 | "qid=%d, pidx_inc=%d\n", qid, pidx_inc); | |
2040 | else | |
f612b815 | 2041 | writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), |
df64e4d3 | 2042 | adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); |
2cc301d2 SR |
2043 | |
2044 | /* Re-enable BAR2 WC */ | |
2045 | t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); | |
2046 | } | |
2047 | ||
3ccc6cf7 HS |
2048 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
2049 | t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); | |
881806bc VP |
2050 | } |
2051 | ||
2052 | void t4_db_full(struct adapter *adap) | |
2053 | { | |
d14807dd | 2054 | if (is_t4(adap->params.chip)) { |
05eb2389 SW |
2055 | disable_dbs(adap); |
2056 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
f612b815 HS |
2057 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, |
2058 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); | |
29aaee65 | 2059 | queue_work(adap->workq, &adap->db_full_task); |
2cc301d2 | 2060 | } |
881806bc VP |
2061 | } |
2062 | ||
2063 | void t4_db_dropped(struct adapter *adap) | |
2064 | { | |
05eb2389 SW |
2065 | if (is_t4(adap->params.chip)) { |
2066 | disable_dbs(adap); | |
2067 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
2068 | } | |
29aaee65 | 2069 | queue_work(adap->workq, &adap->db_drop_task); |
881806bc VP |
2070 | } |
2071 | ||
0fbc81b3 HS |
2072 | void t4_register_netevent_notifier(void) |
2073 | { | |
b8ff05a9 DM |
2074 | if (!netevent_registered) { |
2075 | register_netevent_notifier(&cxgb4_netevent_nb); | |
2076 | netevent_registered = true; | |
2077 | } | |
b8ff05a9 DM |
2078 | } |
2079 | ||
2080 | static void detach_ulds(struct adapter *adap) | |
2081 | { | |
2082 | unsigned int i; | |
2083 | ||
2084 | mutex_lock(&uld_mutex); | |
2085 | list_del(&adap->list_node); | |
6a146f3a | 2086 | |
b8ff05a9 | 2087 | for (i = 0; i < CXGB4_ULD_MAX; i++) |
6a146f3a | 2088 | if (adap->uld && adap->uld[i].handle) |
94cdb8bb HS |
2089 | adap->uld[i].state_change(adap->uld[i].handle, |
2090 | CXGB4_STATE_DETACH); | |
6a146f3a | 2091 | |
b8ff05a9 DM |
2092 | if (netevent_registered && list_empty(&adapter_list)) { |
2093 | unregister_netevent_notifier(&cxgb4_netevent_nb); | |
2094 | netevent_registered = false; | |
2095 | } | |
2096 | mutex_unlock(&uld_mutex); | |
2097 | } | |
2098 | ||
2099 | static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) | |
2100 | { | |
2101 | unsigned int i; | |
2102 | ||
2103 | mutex_lock(&uld_mutex); | |
2104 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
94cdb8bb HS |
2105 | if (adap->uld && adap->uld[i].handle) |
2106 | adap->uld[i].state_change(adap->uld[i].handle, | |
2107 | new_state); | |
b8ff05a9 DM |
2108 | mutex_unlock(&uld_mutex); |
2109 | } | |
2110 | ||
1bb60376 | 2111 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
2112 | static int cxgb4_inet6addr_handler(struct notifier_block *this, |
2113 | unsigned long event, void *data) | |
01bcca68 | 2114 | { |
b5a02f50 AB |
2115 | struct inet6_ifaddr *ifa = data; |
2116 | struct net_device *event_dev = ifa->idev->dev; | |
2117 | const struct device *parent = NULL; | |
2118 | #if IS_ENABLED(CONFIG_BONDING) | |
01bcca68 | 2119 | struct adapter *adap; |
b5a02f50 | 2120 | #endif |
d0d7b10b | 2121 | if (is_vlan_dev(event_dev)) |
b5a02f50 AB |
2122 | event_dev = vlan_dev_real_dev(event_dev); |
2123 | #if IS_ENABLED(CONFIG_BONDING) | |
2124 | if (event_dev->flags & IFF_MASTER) { | |
2125 | list_for_each_entry(adap, &adapter_list, list_node) { | |
2126 | switch (event) { | |
2127 | case NETDEV_UP: | |
2128 | cxgb4_clip_get(adap->port[0], | |
2129 | (const u32 *)ifa, 1); | |
2130 | break; | |
2131 | case NETDEV_DOWN: | |
2132 | cxgb4_clip_release(adap->port[0], | |
2133 | (const u32 *)ifa, 1); | |
2134 | break; | |
2135 | default: | |
2136 | break; | |
2137 | } | |
2138 | } | |
2139 | return NOTIFY_OK; | |
2140 | } | |
2141 | #endif | |
01bcca68 | 2142 | |
b5a02f50 AB |
2143 | if (event_dev) |
2144 | parent = event_dev->dev.parent; | |
01bcca68 | 2145 | |
b5a02f50 | 2146 | if (parent && parent->driver == &cxgb4_driver.driver) { |
01bcca68 VP |
2147 | switch (event) { |
2148 | case NETDEV_UP: | |
b5a02f50 | 2149 | cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2150 | break; |
2151 | case NETDEV_DOWN: | |
b5a02f50 | 2152 | cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2153 | break; |
2154 | default: | |
2155 | break; | |
2156 | } | |
2157 | } | |
b5a02f50 | 2158 | return NOTIFY_OK; |
01bcca68 VP |
2159 | } |
2160 | ||
b5a02f50 | 2161 | static bool inet6addr_registered; |
01bcca68 VP |
2162 | static struct notifier_block cxgb4_inet6addr_notifier = { |
2163 | .notifier_call = cxgb4_inet6addr_handler | |
2164 | }; | |
2165 | ||
01bcca68 VP |
2166 | static void update_clip(const struct adapter *adap) |
2167 | { | |
2168 | int i; | |
2169 | struct net_device *dev; | |
2170 | int ret; | |
2171 | ||
2172 | rcu_read_lock(); | |
2173 | ||
2174 | for (i = 0; i < MAX_NPORTS; i++) { | |
2175 | dev = adap->port[i]; | |
2176 | ret = 0; | |
2177 | ||
2178 | if (dev) | |
b5a02f50 | 2179 | ret = cxgb4_update_root_dev_clip(dev); |
01bcca68 VP |
2180 | |
2181 | if (ret < 0) | |
2182 | break; | |
2183 | } | |
2184 | rcu_read_unlock(); | |
2185 | } | |
1bb60376 | 2186 | #endif /* IS_ENABLED(CONFIG_IPV6) */ |
01bcca68 | 2187 | |
b8ff05a9 DM |
2188 | /** |
2189 | * cxgb_up - enable the adapter | |
2190 | * @adap: adapter being enabled | |
2191 | * | |
2192 | * Called when the first port is enabled, this function performs the | |
2193 | * actions necessary to make an adapter operational, such as completing | |
2194 | * the initialization of HW modules, and enabling interrupts. | |
2195 | * | |
2196 | * Must be called with the rtnl lock held. | |
2197 | */ | |
2198 | static int cxgb_up(struct adapter *adap) | |
2199 | { | |
aaefae9b | 2200 | int err; |
b8ff05a9 | 2201 | |
91060381 | 2202 | mutex_lock(&uld_mutex); |
aaefae9b DM |
2203 | err = setup_sge_queues(adap); |
2204 | if (err) | |
91060381 | 2205 | goto rel_lock; |
aaefae9b DM |
2206 | err = setup_rss(adap); |
2207 | if (err) | |
2208 | goto freeq; | |
b8ff05a9 DM |
2209 | |
2210 | if (adap->flags & USING_MSIX) { | |
aaefae9b | 2211 | name_msix_vecs(adap); |
b8ff05a9 DM |
2212 | err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, |
2213 | adap->msix_info[0].desc, adap); | |
2214 | if (err) | |
2215 | goto irq_err; | |
b8ff05a9 DM |
2216 | err = request_msix_queue_irqs(adap); |
2217 | if (err) { | |
2218 | free_irq(adap->msix_info[0].vec, adap); | |
2219 | goto irq_err; | |
2220 | } | |
2221 | } else { | |
2222 | err = request_irq(adap->pdev->irq, t4_intr_handler(adap), | |
2223 | (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, | |
b1a3c2b6 | 2224 | adap->port[0]->name, adap); |
b8ff05a9 DM |
2225 | if (err) |
2226 | goto irq_err; | |
2227 | } | |
e7519f99 | 2228 | |
b8ff05a9 DM |
2229 | enable_rx(adap); |
2230 | t4_sge_start(adap); | |
2231 | t4_intr_enable(adap); | |
aaefae9b | 2232 | adap->flags |= FULL_INIT_DONE; |
e7519f99 GG |
2233 | mutex_unlock(&uld_mutex); |
2234 | ||
b8ff05a9 | 2235 | notify_ulds(adap, CXGB4_STATE_UP); |
1bb60376 | 2236 | #if IS_ENABLED(CONFIG_IPV6) |
01bcca68 | 2237 | update_clip(adap); |
1bb60376 | 2238 | #endif |
fc08a01a HS |
2239 | /* Initialize hash mac addr list*/ |
2240 | INIT_LIST_HEAD(&adap->mac_hlist); | |
b8ff05a9 | 2241 | return err; |
91060381 | 2242 | |
b8ff05a9 DM |
2243 | irq_err: |
2244 | dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); | |
aaefae9b DM |
2245 | freeq: |
2246 | t4_free_sge_resources(adap); | |
91060381 RR |
2247 | rel_lock: |
2248 | mutex_unlock(&uld_mutex); | |
2249 | return err; | |
b8ff05a9 DM |
2250 | } |
2251 | ||
2252 | static void cxgb_down(struct adapter *adapter) | |
2253 | { | |
b8ff05a9 | 2254 | cancel_work_sync(&adapter->tid_release_task); |
881806bc VP |
2255 | cancel_work_sync(&adapter->db_full_task); |
2256 | cancel_work_sync(&adapter->db_drop_task); | |
b8ff05a9 | 2257 | adapter->tid_release_task_busy = false; |
204dc3c0 | 2258 | adapter->tid_release_head = NULL; |
b8ff05a9 | 2259 | |
aaefae9b DM |
2260 | t4_sge_stop(adapter); |
2261 | t4_free_sge_resources(adapter); | |
2262 | adapter->flags &= ~FULL_INIT_DONE; | |
b8ff05a9 DM |
2263 | } |
2264 | ||
2265 | /* | |
2266 | * net_device operations | |
2267 | */ | |
2268 | static int cxgb_open(struct net_device *dev) | |
2269 | { | |
2270 | int err; | |
2271 | struct port_info *pi = netdev_priv(dev); | |
2272 | struct adapter *adapter = pi->adapter; | |
2273 | ||
6a3c869a DM |
2274 | netif_carrier_off(dev); |
2275 | ||
aaefae9b DM |
2276 | if (!(adapter->flags & FULL_INIT_DONE)) { |
2277 | err = cxgb_up(adapter); | |
2278 | if (err < 0) | |
2279 | return err; | |
2280 | } | |
b8ff05a9 | 2281 | |
2061ec3f GG |
2282 | /* It's possible that the basic port information could have |
2283 | * changed since we first read it. | |
2284 | */ | |
2285 | err = t4_update_port_info(pi); | |
2286 | if (err < 0) | |
2287 | return err; | |
2288 | ||
f68707b8 DM |
2289 | err = link_start(dev); |
2290 | if (!err) | |
2291 | netif_tx_start_all_queues(dev); | |
2292 | return err; | |
b8ff05a9 DM |
2293 | } |
2294 | ||
2295 | static int cxgb_close(struct net_device *dev) | |
2296 | { | |
b8ff05a9 DM |
2297 | struct port_info *pi = netdev_priv(dev); |
2298 | struct adapter *adapter = pi->adapter; | |
2299 | ||
2300 | netif_tx_stop_all_queues(dev); | |
2301 | netif_carrier_off(dev); | |
b2612722 | 2302 | return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false); |
b8ff05a9 DM |
2303 | } |
2304 | ||
dca4faeb | 2305 | int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, |
793dad94 VP |
2306 | __be32 sip, __be16 sport, __be16 vlan, |
2307 | unsigned int queue, unsigned char port, unsigned char mask) | |
dca4faeb VP |
2308 | { |
2309 | int ret; | |
2310 | struct filter_entry *f; | |
2311 | struct adapter *adap; | |
2312 | int i; | |
2313 | u8 *val; | |
2314 | ||
2315 | adap = netdev2adap(dev); | |
2316 | ||
1cab775c | 2317 | /* Adjust stid to correct filter index */ |
470c60c4 | 2318 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2319 | stid += adap->tids.nftids; |
2320 | ||
dca4faeb VP |
2321 | /* Check to make sure the filter requested is writable ... |
2322 | */ | |
2323 | f = &adap->tids.ftid_tab[stid]; | |
2324 | ret = writable_filter(f); | |
2325 | if (ret) | |
2326 | return ret; | |
2327 | ||
2328 | /* Clear out any old resources being used by the filter before | |
2329 | * we start constructing the new filter. | |
2330 | */ | |
2331 | if (f->valid) | |
2332 | clear_filter(adap, f); | |
2333 | ||
2334 | /* Clear out filter specifications */ | |
2335 | memset(&f->fs, 0, sizeof(struct ch_filter_specification)); | |
2336 | f->fs.val.lport = cpu_to_be16(sport); | |
2337 | f->fs.mask.lport = ~0; | |
2338 | val = (u8 *)&sip; | |
793dad94 | 2339 | if ((val[0] | val[1] | val[2] | val[3]) != 0) { |
dca4faeb VP |
2340 | for (i = 0; i < 4; i++) { |
2341 | f->fs.val.lip[i] = val[i]; | |
2342 | f->fs.mask.lip[i] = ~0; | |
2343 | } | |
0d804338 | 2344 | if (adap->params.tp.vlan_pri_map & PORT_F) { |
793dad94 VP |
2345 | f->fs.val.iport = port; |
2346 | f->fs.mask.iport = mask; | |
2347 | } | |
2348 | } | |
dca4faeb | 2349 | |
0d804338 | 2350 | if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { |
7c89e555 KS |
2351 | f->fs.val.proto = IPPROTO_TCP; |
2352 | f->fs.mask.proto = ~0; | |
2353 | } | |
2354 | ||
dca4faeb VP |
2355 | f->fs.dirsteer = 1; |
2356 | f->fs.iq = queue; | |
2357 | /* Mark filter as locked */ | |
2358 | f->locked = 1; | |
2359 | f->fs.rpttid = 1; | |
2360 | ||
6b254afd GG |
2361 | /* Save the actual tid. We need this to get the corresponding |
2362 | * filter entry structure in filter_rpl. | |
2363 | */ | |
2364 | f->tid = stid + adap->tids.ftid_base; | |
dca4faeb VP |
2365 | ret = set_filter_wr(adap, stid); |
2366 | if (ret) { | |
2367 | clear_filter(adap, f); | |
2368 | return ret; | |
2369 | } | |
2370 | ||
2371 | return 0; | |
2372 | } | |
2373 | EXPORT_SYMBOL(cxgb4_create_server_filter); | |
2374 | ||
2375 | int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, | |
2376 | unsigned int queue, bool ipv6) | |
2377 | { | |
dca4faeb VP |
2378 | struct filter_entry *f; |
2379 | struct adapter *adap; | |
2380 | ||
2381 | adap = netdev2adap(dev); | |
1cab775c VP |
2382 | |
2383 | /* Adjust stid to correct filter index */ | |
470c60c4 | 2384 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2385 | stid += adap->tids.nftids; |
2386 | ||
dca4faeb VP |
2387 | f = &adap->tids.ftid_tab[stid]; |
2388 | /* Unlock the filter */ | |
2389 | f->locked = 0; | |
2390 | ||
8c14846d | 2391 | return delete_filter(adap, stid); |
dca4faeb VP |
2392 | } |
2393 | EXPORT_SYMBOL(cxgb4_remove_server_filter); | |
2394 | ||
bc1f4470 | 2395 | static void cxgb_get_stats(struct net_device *dev, |
2396 | struct rtnl_link_stats64 *ns) | |
b8ff05a9 DM |
2397 | { |
2398 | struct port_stats stats; | |
2399 | struct port_info *p = netdev_priv(dev); | |
2400 | struct adapter *adapter = p->adapter; | |
b8ff05a9 | 2401 | |
9fe6cb58 GS |
2402 | /* Block retrieving statistics during EEH error |
2403 | * recovery. Otherwise, the recovery might fail | |
2404 | * and the PCI device will be removed permanently | |
2405 | */ | |
b8ff05a9 | 2406 | spin_lock(&adapter->stats_lock); |
9fe6cb58 GS |
2407 | if (!netif_device_present(dev)) { |
2408 | spin_unlock(&adapter->stats_lock); | |
bc1f4470 | 2409 | return; |
9fe6cb58 | 2410 | } |
a4cfd929 HS |
2411 | t4_get_port_stats_offset(adapter, p->tx_chan, &stats, |
2412 | &p->stats_base); | |
b8ff05a9 DM |
2413 | spin_unlock(&adapter->stats_lock); |
2414 | ||
2415 | ns->tx_bytes = stats.tx_octets; | |
2416 | ns->tx_packets = stats.tx_frames; | |
2417 | ns->rx_bytes = stats.rx_octets; | |
2418 | ns->rx_packets = stats.rx_frames; | |
2419 | ns->multicast = stats.rx_mcast_frames; | |
2420 | ||
2421 | /* detailed rx_errors */ | |
2422 | ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + | |
2423 | stats.rx_runt; | |
2424 | ns->rx_over_errors = 0; | |
2425 | ns->rx_crc_errors = stats.rx_fcs_err; | |
2426 | ns->rx_frame_errors = stats.rx_symbol_err; | |
b93f79be | 2427 | ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 + |
b8ff05a9 DM |
2428 | stats.rx_ovflow2 + stats.rx_ovflow3 + |
2429 | stats.rx_trunc0 + stats.rx_trunc1 + | |
2430 | stats.rx_trunc2 + stats.rx_trunc3; | |
2431 | ns->rx_missed_errors = 0; | |
2432 | ||
2433 | /* detailed tx_errors */ | |
2434 | ns->tx_aborted_errors = 0; | |
2435 | ns->tx_carrier_errors = 0; | |
2436 | ns->tx_fifo_errors = 0; | |
2437 | ns->tx_heartbeat_errors = 0; | |
2438 | ns->tx_window_errors = 0; | |
2439 | ||
2440 | ns->tx_errors = stats.tx_error_frames; | |
2441 | ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + | |
2442 | ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; | |
b8ff05a9 DM |
2443 | } |
2444 | ||
2445 | static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
2446 | { | |
060e0c75 | 2447 | unsigned int mbox; |
b8ff05a9 DM |
2448 | int ret = 0, prtad, devad; |
2449 | struct port_info *pi = netdev_priv(dev); | |
a4569504 | 2450 | struct adapter *adapter = pi->adapter; |
b8ff05a9 DM |
2451 | struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; |
2452 | ||
2453 | switch (cmd) { | |
2454 | case SIOCGMIIPHY: | |
2455 | if (pi->mdio_addr < 0) | |
2456 | return -EOPNOTSUPP; | |
2457 | data->phy_id = pi->mdio_addr; | |
2458 | break; | |
2459 | case SIOCGMIIREG: | |
2460 | case SIOCSMIIREG: | |
2461 | if (mdio_phy_id_is_c45(data->phy_id)) { | |
2462 | prtad = mdio_phy_id_prtad(data->phy_id); | |
2463 | devad = mdio_phy_id_devad(data->phy_id); | |
2464 | } else if (data->phy_id < 32) { | |
2465 | prtad = data->phy_id; | |
2466 | devad = 0; | |
2467 | data->reg_num &= 0x1f; | |
2468 | } else | |
2469 | return -EINVAL; | |
2470 | ||
b2612722 | 2471 | mbox = pi->adapter->pf; |
b8ff05a9 | 2472 | if (cmd == SIOCGMIIREG) |
060e0c75 | 2473 | ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
2474 | data->reg_num, &data->val_out); |
2475 | else | |
060e0c75 | 2476 | ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
2477 | data->reg_num, data->val_in); |
2478 | break; | |
5e2a5ebc HS |
2479 | case SIOCGHWTSTAMP: |
2480 | return copy_to_user(req->ifr_data, &pi->tstamp_config, | |
2481 | sizeof(pi->tstamp_config)) ? | |
2482 | -EFAULT : 0; | |
2483 | case SIOCSHWTSTAMP: | |
2484 | if (copy_from_user(&pi->tstamp_config, req->ifr_data, | |
2485 | sizeof(pi->tstamp_config))) | |
2486 | return -EFAULT; | |
2487 | ||
a4569504 AG |
2488 | if (!is_t4(adapter->params.chip)) { |
2489 | switch (pi->tstamp_config.tx_type) { | |
2490 | case HWTSTAMP_TX_OFF: | |
2491 | case HWTSTAMP_TX_ON: | |
2492 | break; | |
2493 | default: | |
2494 | return -ERANGE; | |
2495 | } | |
2496 | ||
2497 | switch (pi->tstamp_config.rx_filter) { | |
2498 | case HWTSTAMP_FILTER_NONE: | |
2499 | pi->rxtstamp = false; | |
2500 | break; | |
2501 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
2502 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
2503 | cxgb4_ptprx_timestamping(pi, pi->port_id, | |
2504 | PTP_TS_L4); | |
2505 | break; | |
2506 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
2507 | cxgb4_ptprx_timestamping(pi, pi->port_id, | |
2508 | PTP_TS_L2_L4); | |
2509 | break; | |
2510 | case HWTSTAMP_FILTER_ALL: | |
2511 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
2512 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
2513 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
2514 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
2515 | pi->rxtstamp = true; | |
2516 | break; | |
2517 | default: | |
2518 | pi->tstamp_config.rx_filter = | |
2519 | HWTSTAMP_FILTER_NONE; | |
2520 | return -ERANGE; | |
2521 | } | |
2522 | ||
2523 | if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) && | |
2524 | (pi->tstamp_config.rx_filter == | |
2525 | HWTSTAMP_FILTER_NONE)) { | |
2526 | if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0) | |
2527 | pi->ptp_enable = false; | |
2528 | } | |
2529 | ||
2530 | if (pi->tstamp_config.rx_filter != | |
2531 | HWTSTAMP_FILTER_NONE) { | |
2532 | if (cxgb4_ptp_redirect_rx_packet(adapter, | |
2533 | pi) >= 0) | |
2534 | pi->ptp_enable = true; | |
2535 | } | |
2536 | } else { | |
2537 | /* For T4 Adapters */ | |
2538 | switch (pi->tstamp_config.rx_filter) { | |
2539 | case HWTSTAMP_FILTER_NONE: | |
5e2a5ebc HS |
2540 | pi->rxtstamp = false; |
2541 | break; | |
a4569504 | 2542 | case HWTSTAMP_FILTER_ALL: |
5e2a5ebc HS |
2543 | pi->rxtstamp = true; |
2544 | break; | |
a4569504 AG |
2545 | default: |
2546 | pi->tstamp_config.rx_filter = | |
2547 | HWTSTAMP_FILTER_NONE; | |
5e2a5ebc | 2548 | return -ERANGE; |
a4569504 | 2549 | } |
5e2a5ebc | 2550 | } |
5e2a5ebc HS |
2551 | return copy_to_user(req->ifr_data, &pi->tstamp_config, |
2552 | sizeof(pi->tstamp_config)) ? | |
2553 | -EFAULT : 0; | |
b8ff05a9 DM |
2554 | default: |
2555 | return -EOPNOTSUPP; | |
2556 | } | |
2557 | return ret; | |
2558 | } | |
2559 | ||
2560 | static void cxgb_set_rxmode(struct net_device *dev) | |
2561 | { | |
2562 | /* unfortunately we can't return errors to the stack */ | |
2563 | set_rxmode(dev, -1, false); | |
2564 | } | |
2565 | ||
2566 | static int cxgb_change_mtu(struct net_device *dev, int new_mtu) | |
2567 | { | |
2568 | int ret; | |
2569 | struct port_info *pi = netdev_priv(dev); | |
2570 | ||
b2612722 | 2571 | ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, |
060e0c75 | 2572 | -1, -1, -1, true); |
b8ff05a9 DM |
2573 | if (!ret) |
2574 | dev->mtu = new_mtu; | |
2575 | return ret; | |
2576 | } | |
2577 | ||
858aa65c | 2578 | #ifdef CONFIG_PCI_IOV |
e7b48a32 HS |
2579 | static int dummy_open(struct net_device *dev) |
2580 | { | |
2581 | /* Turn carrier off since we don't have to transmit anything on this | |
2582 | * interface. | |
2583 | */ | |
2584 | netif_carrier_off(dev); | |
2585 | return 0; | |
2586 | } | |
2587 | ||
661dbeb9 HS |
2588 | /* Fill MAC address that will be assigned by the FW */ |
2589 | static void fill_vf_station_mac_addr(struct adapter *adap) | |
2590 | { | |
2591 | unsigned int i; | |
2592 | u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN]; | |
2593 | int err; | |
2594 | u8 *na; | |
2595 | u16 a, b; | |
2596 | ||
2597 | err = t4_get_raw_vpd_params(adap, &adap->params.vpd); | |
2598 | if (!err) { | |
2599 | na = adap->params.vpd.na; | |
2600 | for (i = 0; i < ETH_ALEN; i++) | |
2601 | hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + | |
2602 | hex2val(na[2 * i + 1])); | |
2603 | a = (hw_addr[0] << 8) | hw_addr[1]; | |
2604 | b = (hw_addr[1] << 8) | hw_addr[2]; | |
2605 | a ^= b; | |
2606 | a |= 0x0200; /* locally assigned Ethernet MAC address */ | |
2607 | a &= ~0x0100; /* not a multicast Ethernet MAC address */ | |
2608 | macaddr[0] = a >> 8; | |
2609 | macaddr[1] = a & 0xff; | |
2610 | ||
2611 | for (i = 2; i < 5; i++) | |
2612 | macaddr[i] = hw_addr[i + 1]; | |
2613 | ||
2614 | for (i = 0; i < adap->num_vfs; i++) { | |
2615 | macaddr[5] = adap->pf * 16 + i; | |
2616 | ether_addr_copy(adap->vfinfo[i].vf_mac_addr, macaddr); | |
2617 | } | |
2618 | } | |
2619 | } | |
2620 | ||
858aa65c HS |
2621 | static int cxgb_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
2622 | { | |
2623 | struct port_info *pi = netdev_priv(dev); | |
2624 | struct adapter *adap = pi->adapter; | |
661dbeb9 | 2625 | int ret; |
858aa65c HS |
2626 | |
2627 | /* verify MAC addr is valid */ | |
2628 | if (!is_valid_ether_addr(mac)) { | |
2629 | dev_err(pi->adapter->pdev_dev, | |
2630 | "Invalid Ethernet address %pM for VF %d\n", | |
2631 | mac, vf); | |
2632 | return -EINVAL; | |
2633 | } | |
2634 | ||
2635 | dev_info(pi->adapter->pdev_dev, | |
2636 | "Setting MAC %pM on VF %d\n", mac, vf); | |
661dbeb9 HS |
2637 | ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac); |
2638 | if (!ret) | |
2639 | ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac); | |
2640 | return ret; | |
2641 | } | |
2642 | ||
2643 | static int cxgb_get_vf_config(struct net_device *dev, | |
2644 | int vf, struct ifla_vf_info *ivi) | |
2645 | { | |
2646 | struct port_info *pi = netdev_priv(dev); | |
2647 | struct adapter *adap = pi->adapter; | |
2648 | ||
2649 | if (vf >= adap->num_vfs) | |
2650 | return -EINVAL; | |
2651 | ivi->vf = vf; | |
8ea4fae9 GG |
2652 | ivi->max_tx_rate = adap->vfinfo[vf].tx_rate; |
2653 | ivi->min_tx_rate = 0; | |
661dbeb9 HS |
2654 | ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr); |
2655 | return 0; | |
858aa65c | 2656 | } |
96fe11f2 GG |
2657 | |
2658 | static int cxgb_get_phys_port_id(struct net_device *dev, | |
2659 | struct netdev_phys_item_id *ppid) | |
2660 | { | |
2661 | struct port_info *pi = netdev_priv(dev); | |
2662 | unsigned int phy_port_id; | |
2663 | ||
2664 | phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id; | |
2665 | ppid->id_len = sizeof(phy_port_id); | |
2666 | memcpy(ppid->id, &phy_port_id, ppid->id_len); | |
2667 | return 0; | |
2668 | } | |
2669 | ||
8ea4fae9 GG |
2670 | static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, |
2671 | int max_tx_rate) | |
2672 | { | |
2673 | struct port_info *pi = netdev_priv(dev); | |
2674 | struct adapter *adap = pi->adapter; | |
2675 | struct fw_port_cmd port_cmd, port_rpl; | |
2676 | u32 link_status, speed = 0; | |
2677 | u32 fw_pfvf, fw_class; | |
2678 | int class_id = vf; | |
2679 | int link_ok, ret; | |
2680 | u16 pktsize; | |
2681 | ||
2682 | if (vf >= adap->num_vfs) | |
2683 | return -EINVAL; | |
2684 | ||
2685 | if (min_tx_rate) { | |
2686 | dev_err(adap->pdev_dev, | |
2687 | "Min tx rate (%d) (> 0) for VF %d is Invalid.\n", | |
2688 | min_tx_rate, vf); | |
2689 | return -EINVAL; | |
2690 | } | |
2691 | /* Retrieve link details for VF port */ | |
2692 | memset(&port_cmd, 0, sizeof(port_cmd)); | |
2693 | port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | | |
2694 | FW_CMD_REQUEST_F | | |
2695 | FW_CMD_READ_F | | |
2696 | FW_PORT_CMD_PORTID_V(pi->port_id)); | |
2697 | port_cmd.action_to_len16 = | |
2698 | cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) | | |
2699 | FW_LEN16(port_cmd)); | |
2700 | ret = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd), | |
2701 | &port_rpl); | |
2702 | if (ret != FW_SUCCESS) { | |
2703 | dev_err(adap->pdev_dev, | |
2704 | "Failed to get link status for VF %d\n", vf); | |
2705 | return -EINVAL; | |
2706 | } | |
2707 | link_status = be32_to_cpu(port_rpl.u.info.lstatus_to_modtype); | |
2708 | link_ok = (link_status & FW_PORT_CMD_LSTATUS_F) != 0; | |
2709 | if (!link_ok) { | |
2710 | dev_err(adap->pdev_dev, "Link down for VF %d\n", vf); | |
2711 | return -EINVAL; | |
2712 | } | |
2713 | /* Determine link speed */ | |
2714 | if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M)) | |
2715 | speed = 100; | |
2716 | else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G)) | |
2717 | speed = 1000; | |
2718 | else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G)) | |
2719 | speed = 10000; | |
2720 | else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G)) | |
2721 | speed = 25000; | |
2722 | else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G)) | |
2723 | speed = 40000; | |
2724 | else if (link_status & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G)) | |
2725 | speed = 100000; | |
2726 | ||
2727 | if (max_tx_rate > speed) { | |
2728 | dev_err(adap->pdev_dev, | |
2729 | "Max tx rate %d for VF %d can't be > link-speed %u", | |
2730 | max_tx_rate, vf, speed); | |
2731 | return -EINVAL; | |
2732 | } | |
2733 | pktsize = be16_to_cpu(port_rpl.u.info.mtu); | |
2734 | /* subtract ethhdr size and 4 bytes crc since, f/w appends it */ | |
2735 | pktsize = pktsize - sizeof(struct ethhdr) - 4; | |
2736 | /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */ | |
2737 | pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr); | |
2738 | /* configure Traffic Class for rate-limiting */ | |
2739 | ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET, | |
2740 | SCHED_CLASS_LEVEL_CL_RL, | |
2741 | SCHED_CLASS_MODE_CLASS, | |
2742 | SCHED_CLASS_RATEUNIT_BITS, | |
2743 | SCHED_CLASS_RATEMODE_ABS, | |
2744 | pi->port_id, class_id, 0, | |
2745 | max_tx_rate * 1000, 0, pktsize); | |
2746 | if (ret) { | |
2747 | dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n", | |
2748 | ret); | |
2749 | return -EINVAL; | |
2750 | } | |
2751 | dev_info(adap->pdev_dev, | |
2752 | "Class %d with MSS %u configured with rate %u\n", | |
2753 | class_id, pktsize, max_tx_rate); | |
2754 | ||
2755 | /* bind VF to configured Traffic Class */ | |
2756 | fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | | |
2757 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); | |
2758 | fw_class = class_id; | |
2759 | ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf, | |
2760 | &fw_class); | |
2761 | if (ret) { | |
2762 | dev_err(adap->pdev_dev, | |
2763 | "Err %d in binding VF %d to Traffic Class %d\n", | |
2764 | ret, vf, class_id); | |
2765 | return -EINVAL; | |
2766 | } | |
2767 | dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n", | |
2768 | adap->pf, vf, class_id); | |
2769 | adap->vfinfo[vf].tx_rate = max_tx_rate; | |
2770 | return 0; | |
2771 | } | |
2772 | ||
858aa65c HS |
2773 | #endif |
2774 | ||
b8ff05a9 DM |
2775 | static int cxgb_set_mac_addr(struct net_device *dev, void *p) |
2776 | { | |
2777 | int ret; | |
2778 | struct sockaddr *addr = p; | |
2779 | struct port_info *pi = netdev_priv(dev); | |
2780 | ||
2781 | if (!is_valid_ether_addr(addr->sa_data)) | |
504f9b5a | 2782 | return -EADDRNOTAVAIL; |
b8ff05a9 | 2783 | |
b2612722 | 2784 | ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, |
060e0c75 | 2785 | pi->xact_addr_filt, addr->sa_data, true, true); |
b8ff05a9 DM |
2786 | if (ret < 0) |
2787 | return ret; | |
2788 | ||
2789 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
2790 | pi->xact_addr_filt = ret; | |
2791 | return 0; | |
2792 | } | |
2793 | ||
b8ff05a9 DM |
2794 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2795 | static void cxgb_netpoll(struct net_device *dev) | |
2796 | { | |
2797 | struct port_info *pi = netdev_priv(dev); | |
2798 | struct adapter *adap = pi->adapter; | |
2799 | ||
2800 | if (adap->flags & USING_MSIX) { | |
2801 | int i; | |
2802 | struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; | |
2803 | ||
2804 | for (i = pi->nqsets; i; i--, rx++) | |
2805 | t4_sge_intr_msix(0, &rx->rspq); | |
2806 | } else | |
2807 | t4_intr_handler(adap)(0, adap); | |
2808 | } | |
2809 | #endif | |
2810 | ||
10a2604e RL |
2811 | static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate) |
2812 | { | |
2813 | struct port_info *pi = netdev_priv(dev); | |
2814 | struct adapter *adap = pi->adapter; | |
2815 | struct sched_class *e; | |
2816 | struct ch_sched_params p; | |
2817 | struct ch_sched_queue qe; | |
2818 | u32 req_rate; | |
2819 | int err = 0; | |
2820 | ||
2821 | if (!can_sched(dev)) | |
2822 | return -ENOTSUPP; | |
2823 | ||
2824 | if (index < 0 || index > pi->nqsets - 1) | |
2825 | return -EINVAL; | |
2826 | ||
2827 | if (!(adap->flags & FULL_INIT_DONE)) { | |
2828 | dev_err(adap->pdev_dev, | |
2829 | "Failed to rate limit on queue %d. Link Down?\n", | |
2830 | index); | |
2831 | return -EINVAL; | |
2832 | } | |
2833 | ||
2834 | /* Convert from Mbps to Kbps */ | |
2835 | req_rate = rate << 10; | |
2836 | ||
2837 | /* Max rate is 10 Gbps */ | |
2838 | if (req_rate >= SCHED_MAX_RATE_KBPS) { | |
2839 | dev_err(adap->pdev_dev, | |
2840 | "Invalid rate %u Mbps, Max rate is %u Gbps\n", | |
2841 | rate, SCHED_MAX_RATE_KBPS); | |
2842 | return -ERANGE; | |
2843 | } | |
2844 | ||
2845 | /* First unbind the queue from any existing class */ | |
2846 | memset(&qe, 0, sizeof(qe)); | |
2847 | qe.queue = index; | |
2848 | qe.class = SCHED_CLS_NONE; | |
2849 | ||
2850 | err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE); | |
2851 | if (err) { | |
2852 | dev_err(adap->pdev_dev, | |
2853 | "Unbinding Queue %d on port %d fail. Err: %d\n", | |
2854 | index, pi->port_id, err); | |
2855 | return err; | |
2856 | } | |
2857 | ||
2858 | /* Queue already unbound */ | |
2859 | if (!req_rate) | |
2860 | return 0; | |
2861 | ||
2862 | /* Fetch any available unused or matching scheduling class */ | |
2863 | memset(&p, 0, sizeof(p)); | |
2864 | p.type = SCHED_CLASS_TYPE_PACKET; | |
2865 | p.u.params.level = SCHED_CLASS_LEVEL_CL_RL; | |
2866 | p.u.params.mode = SCHED_CLASS_MODE_CLASS; | |
2867 | p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS; | |
2868 | p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS; | |
2869 | p.u.params.channel = pi->tx_chan; | |
2870 | p.u.params.class = SCHED_CLS_NONE; | |
2871 | p.u.params.minrate = 0; | |
2872 | p.u.params.maxrate = req_rate; | |
2873 | p.u.params.weight = 0; | |
2874 | p.u.params.pktsize = dev->mtu; | |
2875 | ||
2876 | e = cxgb4_sched_class_alloc(dev, &p); | |
2877 | if (!e) | |
2878 | return -ENOMEM; | |
2879 | ||
2880 | /* Bind the queue to a scheduling class */ | |
2881 | memset(&qe, 0, sizeof(qe)); | |
2882 | qe.queue = index; | |
2883 | qe.class = e->idx; | |
2884 | ||
2885 | err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE); | |
2886 | if (err) | |
2887 | dev_err(adap->pdev_dev, | |
2888 | "Queue rate limiting failed. Err: %d\n", err); | |
2889 | return err; | |
2890 | } | |
2891 | ||
f7323043 JP |
2892 | static int cxgb_setup_tc_cls_u32(struct net_device *dev, |
2893 | enum tc_setup_type type, | |
2894 | u32 handle, u32 chain_index, __be16 proto, | |
2895 | struct tc_cls_u32_offload *cls_u32) | |
2896 | { | |
2897 | if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS) || | |
2898 | chain_index) | |
2899 | return -EOPNOTSUPP; | |
2900 | ||
2901 | switch (cls_u32->command) { | |
2902 | case TC_CLSU32_NEW_KNODE: | |
2903 | case TC_CLSU32_REPLACE_KNODE: | |
2904 | return cxgb4_config_knode(dev, proto, cls_u32); | |
2905 | case TC_CLSU32_DELETE_KNODE: | |
2906 | return cxgb4_delete_knode(dev, proto, cls_u32); | |
2907 | default: | |
2908 | return -EOPNOTSUPP; | |
2909 | } | |
2910 | } | |
2911 | ||
2572ac53 JP |
2912 | static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type, |
2913 | u32 handle, u32 chain_index, __be16 proto, | |
2914 | struct tc_to_netdev *tc) | |
d8931847 RL |
2915 | { |
2916 | struct port_info *pi = netdev2pinfo(dev); | |
2917 | struct adapter *adap = netdev2adap(dev); | |
2918 | ||
2919 | if (!(adap->flags & FULL_INIT_DONE)) { | |
2920 | dev_err(adap->pdev_dev, | |
2921 | "Failed to setup tc on port %d. Link Down?\n", | |
2922 | pi->port_id); | |
2923 | return -EINVAL; | |
2924 | } | |
2925 | ||
f7323043 JP |
2926 | switch (type) { |
2927 | case TC_SETUP_CLSU32: | |
2928 | return cxgb_setup_tc_cls_u32(dev, type, handle, chain_index, | |
2929 | proto, tc->cls_u32); | |
2930 | default: | |
2931 | return -EOPNOTSUPP; | |
d8931847 | 2932 | } |
d8931847 RL |
2933 | } |
2934 | ||
90592b9a AV |
2935 | static netdev_features_t cxgb_fix_features(struct net_device *dev, |
2936 | netdev_features_t features) | |
2937 | { | |
2938 | /* Disable GRO, if RX_CSUM is disabled */ | |
2939 | if (!(features & NETIF_F_RXCSUM)) | |
2940 | features &= ~NETIF_F_GRO; | |
2941 | ||
2942 | return features; | |
2943 | } | |
2944 | ||
b8ff05a9 DM |
2945 | static const struct net_device_ops cxgb4_netdev_ops = { |
2946 | .ndo_open = cxgb_open, | |
2947 | .ndo_stop = cxgb_close, | |
2948 | .ndo_start_xmit = t4_eth_xmit, | |
688848b1 | 2949 | .ndo_select_queue = cxgb_select_queue, |
9be793bf | 2950 | .ndo_get_stats64 = cxgb_get_stats, |
b8ff05a9 DM |
2951 | .ndo_set_rx_mode = cxgb_set_rxmode, |
2952 | .ndo_set_mac_address = cxgb_set_mac_addr, | |
2ed28baa | 2953 | .ndo_set_features = cxgb_set_features, |
b8ff05a9 DM |
2954 | .ndo_validate_addr = eth_validate_addr, |
2955 | .ndo_do_ioctl = cxgb_ioctl, | |
2956 | .ndo_change_mtu = cxgb_change_mtu, | |
b8ff05a9 DM |
2957 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2958 | .ndo_poll_controller = cxgb_netpoll, | |
2959 | #endif | |
84a200b3 VP |
2960 | #ifdef CONFIG_CHELSIO_T4_FCOE |
2961 | .ndo_fcoe_enable = cxgb_fcoe_enable, | |
2962 | .ndo_fcoe_disable = cxgb_fcoe_disable, | |
2963 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
10a2604e | 2964 | .ndo_set_tx_maxrate = cxgb_set_tx_maxrate, |
d8931847 | 2965 | .ndo_setup_tc = cxgb_setup_tc, |
90592b9a | 2966 | .ndo_fix_features = cxgb_fix_features, |
b8ff05a9 DM |
2967 | }; |
2968 | ||
858aa65c | 2969 | #ifdef CONFIG_PCI_IOV |
e7b48a32 HS |
2970 | static const struct net_device_ops cxgb4_mgmt_netdev_ops = { |
2971 | .ndo_open = dummy_open, | |
858aa65c | 2972 | .ndo_set_vf_mac = cxgb_set_vf_mac, |
661dbeb9 | 2973 | .ndo_get_vf_config = cxgb_get_vf_config, |
8ea4fae9 | 2974 | .ndo_set_vf_rate = cxgb_set_vf_rate, |
96fe11f2 | 2975 | .ndo_get_phys_port_id = cxgb_get_phys_port_id, |
7829451c | 2976 | }; |
e7b48a32 | 2977 | #endif |
7829451c HS |
2978 | |
2979 | static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
2980 | { | |
2981 | struct adapter *adapter = netdev2adap(dev); | |
2982 | ||
2983 | strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver)); | |
2984 | strlcpy(info->version, cxgb4_driver_version, | |
2985 | sizeof(info->version)); | |
2986 | strlcpy(info->bus_info, pci_name(adapter->pdev), | |
2987 | sizeof(info->bus_info)); | |
2988 | } | |
2989 | ||
2990 | static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = { | |
2991 | .get_drvinfo = get_drvinfo, | |
2992 | }; | |
2993 | ||
b8ff05a9 DM |
2994 | void t4_fatal_err(struct adapter *adap) |
2995 | { | |
3be0679b HS |
2996 | int port; |
2997 | ||
025d0973 GP |
2998 | if (pci_channel_offline(adap->pdev)) |
2999 | return; | |
3000 | ||
3be0679b HS |
3001 | /* Disable the SGE since ULDs are going to free resources that |
3002 | * could be exposed to the adapter. RDMA MWs for example... | |
3003 | */ | |
3004 | t4_shutdown_adapter(adap); | |
3005 | for_each_port(adap, port) { | |
3006 | struct net_device *dev = adap->port[port]; | |
3007 | ||
3008 | /* If we get here in very early initialization the network | |
3009 | * devices may not have been set up yet. | |
3010 | */ | |
3011 | if (!dev) | |
3012 | continue; | |
3013 | ||
3014 | netif_tx_stop_all_queues(dev); | |
3015 | netif_carrier_off(dev); | |
3016 | } | |
b8ff05a9 DM |
3017 | dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); |
3018 | } | |
3019 | ||
3020 | static void setup_memwin(struct adapter *adap) | |
3021 | { | |
b562fc37 | 3022 | u32 nic_win_base = t4_get_util_window(adap); |
b8ff05a9 | 3023 | |
b562fc37 | 3024 | t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); |
636f9d37 VP |
3025 | } |
3026 | ||
3027 | static void setup_memwin_rdma(struct adapter *adap) | |
3028 | { | |
1ae970e0 | 3029 | if (adap->vres.ocq.size) { |
0abfd152 HS |
3030 | u32 start; |
3031 | unsigned int sz_kb; | |
1ae970e0 | 3032 | |
0abfd152 HS |
3033 | start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); |
3034 | start &= PCI_BASE_ADDRESS_MEM_MASK; | |
3035 | start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); | |
1ae970e0 DM |
3036 | sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; |
3037 | t4_write_reg(adap, | |
f061de42 HS |
3038 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), |
3039 | start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); | |
1ae970e0 | 3040 | t4_write_reg(adap, |
f061de42 | 3041 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), |
1ae970e0 DM |
3042 | adap->vres.ocq.start); |
3043 | t4_read_reg(adap, | |
f061de42 | 3044 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); |
1ae970e0 | 3045 | } |
b8ff05a9 DM |
3046 | } |
3047 | ||
02b5fb8e DM |
3048 | static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) |
3049 | { | |
3050 | u32 v; | |
3051 | int ret; | |
3052 | ||
3053 | /* get device capabilities */ | |
3054 | memset(c, 0, sizeof(*c)); | |
e2ac9628 HS |
3055 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3056 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 3057 | c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); |
b2612722 | 3058 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); |
02b5fb8e DM |
3059 | if (ret < 0) |
3060 | return ret; | |
3061 | ||
e2ac9628 HS |
3062 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3063 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
b2612722 | 3064 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); |
02b5fb8e DM |
3065 | if (ret < 0) |
3066 | return ret; | |
3067 | ||
b2612722 | 3068 | ret = t4_config_glbl_rss(adap, adap->pf, |
02b5fb8e | 3069 | FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, |
b2e1a3f0 HS |
3070 | FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | |
3071 | FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); | |
02b5fb8e DM |
3072 | if (ret < 0) |
3073 | return ret; | |
3074 | ||
b2612722 | 3075 | ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, |
4b8e27a8 HS |
3076 | MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, |
3077 | FW_CMD_CAP_PF); | |
02b5fb8e DM |
3078 | if (ret < 0) |
3079 | return ret; | |
3080 | ||
3081 | t4_sge_init(adap); | |
3082 | ||
02b5fb8e | 3083 | /* tweak some settings */ |
837e4a42 | 3084 | t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); |
0d804338 | 3085 | t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); |
837e4a42 HS |
3086 | t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); |
3087 | v = t4_read_reg(adap, TP_PIO_DATA_A); | |
3088 | t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); | |
060e0c75 | 3089 | |
dca4faeb VP |
3090 | /* first 4 Tx modulation queues point to consecutive Tx channels */ |
3091 | adap->params.tp.tx_modq_map = 0xE4; | |
0d804338 HS |
3092 | t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, |
3093 | TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); | |
dca4faeb VP |
3094 | |
3095 | /* associate each Tx modulation queue with consecutive Tx channels */ | |
3096 | v = 0x84218421; | |
837e4a42 | 3097 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3098 | &v, 1, TP_TX_SCHED_HDR_A); |
837e4a42 | 3099 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3100 | &v, 1, TP_TX_SCHED_FIFO_A); |
837e4a42 | 3101 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3102 | &v, 1, TP_TX_SCHED_PCMD_A); |
dca4faeb VP |
3103 | |
3104 | #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ | |
3105 | if (is_offload(adap)) { | |
0d804338 HS |
3106 | t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, |
3107 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3108 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3109 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3110 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
3111 | t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, | |
3112 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3113 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3114 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3115 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
dca4faeb VP |
3116 | } |
3117 | ||
060e0c75 | 3118 | /* get basic stuff going */ |
b2612722 | 3119 | return t4_early_init(adap, adap->pf); |
02b5fb8e DM |
3120 | } |
3121 | ||
b8ff05a9 DM |
3122 | /* |
3123 | * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. | |
3124 | */ | |
3125 | #define MAX_ATIDS 8192U | |
3126 | ||
636f9d37 VP |
3127 | /* |
3128 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
3129 | * | |
3130 | * If the firmware we're dealing with has Configuration File support, then | |
3131 | * we use that to perform all configuration | |
3132 | */ | |
3133 | ||
3134 | /* | |
3135 | * Tweak configuration based on module parameters, etc. Most of these have | |
3136 | * defaults assigned to them by Firmware Configuration Files (if we're using | |
3137 | * them) but need to be explicitly set if we're using hard-coded | |
3138 | * initialization. But even in the case of using Firmware Configuration | |
3139 | * Files, we'd like to expose the ability to change these via module | |
3140 | * parameters so these are essentially common tweaks/settings for | |
3141 | * Configuration Files and hard-coded initialization ... | |
3142 | */ | |
3143 | static int adap_init0_tweaks(struct adapter *adapter) | |
3144 | { | |
3145 | /* | |
3146 | * Fix up various Host-Dependent Parameters like Page Size, Cache | |
3147 | * Line Size, etc. The firmware default is for a 4KB Page Size and | |
3148 | * 64B Cache Line Size ... | |
3149 | */ | |
3150 | t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); | |
3151 | ||
3152 | /* | |
3153 | * Process module parameters which affect early initialization. | |
3154 | */ | |
3155 | if (rx_dma_offset != 2 && rx_dma_offset != 0) { | |
3156 | dev_err(&adapter->pdev->dev, | |
3157 | "Ignoring illegal rx_dma_offset=%d, using 2\n", | |
3158 | rx_dma_offset); | |
3159 | rx_dma_offset = 2; | |
3160 | } | |
f612b815 HS |
3161 | t4_set_reg_field(adapter, SGE_CONTROL_A, |
3162 | PKTSHIFT_V(PKTSHIFT_M), | |
3163 | PKTSHIFT_V(rx_dma_offset)); | |
636f9d37 VP |
3164 | |
3165 | /* | |
3166 | * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux | |
3167 | * adds the pseudo header itself. | |
3168 | */ | |
837e4a42 HS |
3169 | t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, |
3170 | CSUM_HAS_PSEUDO_HDR_F, 0); | |
636f9d37 VP |
3171 | |
3172 | return 0; | |
3173 | } | |
3174 | ||
01b69614 HS |
3175 | /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips |
3176 | * unto themselves and they contain their own firmware to perform their | |
3177 | * tasks ... | |
3178 | */ | |
3179 | static int phy_aq1202_version(const u8 *phy_fw_data, | |
3180 | size_t phy_fw_size) | |
3181 | { | |
3182 | int offset; | |
3183 | ||
3184 | /* At offset 0x8 you're looking for the primary image's | |
3185 | * starting offset which is 3 Bytes wide | |
3186 | * | |
3187 | * At offset 0xa of the primary image, you look for the offset | |
3188 | * of the DRAM segment which is 3 Bytes wide. | |
3189 | * | |
3190 | * The FW version is at offset 0x27e of the DRAM and is 2 Bytes | |
3191 | * wide | |
3192 | */ | |
3193 | #define be16(__p) (((__p)[0] << 8) | (__p)[1]) | |
3194 | #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) | |
3195 | #define le24(__p) (le16(__p) | ((__p)[2] << 16)) | |
3196 | ||
3197 | offset = le24(phy_fw_data + 0x8) << 12; | |
3198 | offset = le24(phy_fw_data + offset + 0xa); | |
3199 | return be16(phy_fw_data + offset + 0x27e); | |
3200 | ||
3201 | #undef be16 | |
3202 | #undef le16 | |
3203 | #undef le24 | |
3204 | } | |
3205 | ||
3206 | static struct info_10gbt_phy_fw { | |
3207 | unsigned int phy_fw_id; /* PCI Device ID */ | |
3208 | char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ | |
3209 | int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); | |
3210 | int phy_flash; /* Has FLASH for PHY Firmware */ | |
3211 | } phy_info_array[] = { | |
3212 | { | |
3213 | PHY_AQ1202_DEVICEID, | |
3214 | PHY_AQ1202_FIRMWARE, | |
3215 | phy_aq1202_version, | |
3216 | 1, | |
3217 | }, | |
3218 | { | |
3219 | PHY_BCM84834_DEVICEID, | |
3220 | PHY_BCM84834_FIRMWARE, | |
3221 | NULL, | |
3222 | 0, | |
3223 | }, | |
3224 | { 0, NULL, NULL }, | |
3225 | }; | |
3226 | ||
3227 | static struct info_10gbt_phy_fw *find_phy_info(int devid) | |
3228 | { | |
3229 | int i; | |
3230 | ||
3231 | for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { | |
3232 | if (phy_info_array[i].phy_fw_id == devid) | |
3233 | return &phy_info_array[i]; | |
3234 | } | |
3235 | return NULL; | |
3236 | } | |
3237 | ||
3238 | /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to | |
3239 | * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error | |
3240 | * we return a negative error number. If we transfer new firmware we return 1 | |
3241 | * (from t4_load_phy_fw()). If we don't do anything we return 0. | |
3242 | */ | |
3243 | static int adap_init0_phy(struct adapter *adap) | |
3244 | { | |
3245 | const struct firmware *phyf; | |
3246 | int ret; | |
3247 | struct info_10gbt_phy_fw *phy_info; | |
3248 | ||
3249 | /* Use the device ID to determine which PHY file to flash. | |
3250 | */ | |
3251 | phy_info = find_phy_info(adap->pdev->device); | |
3252 | if (!phy_info) { | |
3253 | dev_warn(adap->pdev_dev, | |
3254 | "No PHY Firmware file found for this PHY\n"); | |
3255 | return -EOPNOTSUPP; | |
3256 | } | |
3257 | ||
3258 | /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then | |
3259 | * use that. The adapter firmware provides us with a memory buffer | |
3260 | * where we can load a PHY firmware file from the host if we want to | |
3261 | * override the PHY firmware File in flash. | |
3262 | */ | |
3263 | ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, | |
3264 | adap->pdev_dev); | |
3265 | if (ret < 0) { | |
3266 | /* For adapters without FLASH attached to PHY for their | |
3267 | * firmware, it's obviously a fatal error if we can't get the | |
3268 | * firmware to the adapter. For adapters with PHY firmware | |
3269 | * FLASH storage, it's worth a warning if we can't find the | |
3270 | * PHY Firmware but we'll neuter the error ... | |
3271 | */ | |
3272 | dev_err(adap->pdev_dev, "unable to find PHY Firmware image " | |
3273 | "/lib/firmware/%s, error %d\n", | |
3274 | phy_info->phy_fw_file, -ret); | |
3275 | if (phy_info->phy_flash) { | |
3276 | int cur_phy_fw_ver = 0; | |
3277 | ||
3278 | t4_phy_fw_ver(adap, &cur_phy_fw_ver); | |
3279 | dev_warn(adap->pdev_dev, "continuing with, on-adapter " | |
3280 | "FLASH copy, version %#x\n", cur_phy_fw_ver); | |
3281 | ret = 0; | |
3282 | } | |
3283 | ||
3284 | return ret; | |
3285 | } | |
3286 | ||
3287 | /* Load PHY Firmware onto adapter. | |
3288 | */ | |
3289 | ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, | |
3290 | phy_info->phy_fw_version, | |
3291 | (u8 *)phyf->data, phyf->size); | |
3292 | if (ret < 0) | |
3293 | dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", | |
3294 | -ret); | |
3295 | else if (ret > 0) { | |
3296 | int new_phy_fw_ver = 0; | |
3297 | ||
3298 | if (phy_info->phy_fw_version) | |
3299 | new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, | |
3300 | phyf->size); | |
3301 | dev_info(adap->pdev_dev, "Successfully transferred PHY " | |
3302 | "Firmware /lib/firmware/%s, version %#x\n", | |
3303 | phy_info->phy_fw_file, new_phy_fw_ver); | |
3304 | } | |
3305 | ||
3306 | release_firmware(phyf); | |
3307 | ||
3308 | return ret; | |
3309 | } | |
3310 | ||
636f9d37 VP |
3311 | /* |
3312 | * Attempt to initialize the adapter via a Firmware Configuration File. | |
3313 | */ | |
3314 | static int adap_init0_config(struct adapter *adapter, int reset) | |
3315 | { | |
3316 | struct fw_caps_config_cmd caps_cmd; | |
3317 | const struct firmware *cf; | |
3318 | unsigned long mtype = 0, maddr = 0; | |
3319 | u32 finiver, finicsum, cfcsum; | |
16e47624 HS |
3320 | int ret; |
3321 | int config_issued = 0; | |
0a57a536 | 3322 | char *fw_config_file, fw_config_file_path[256]; |
16e47624 | 3323 | char *config_name = NULL; |
636f9d37 VP |
3324 | |
3325 | /* | |
3326 | * Reset device if necessary. | |
3327 | */ | |
3328 | if (reset) { | |
3329 | ret = t4_fw_reset(adapter, adapter->mbox, | |
0d804338 | 3330 | PIORSTMODE_F | PIORST_F); |
636f9d37 VP |
3331 | if (ret < 0) |
3332 | goto bye; | |
3333 | } | |
3334 | ||
01b69614 HS |
3335 | /* If this is a 10Gb/s-BT adapter make sure the chip-external |
3336 | * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs | |
3337 | * to be performed after any global adapter RESET above since some | |
3338 | * PHYs only have local RAM copies of the PHY firmware. | |
3339 | */ | |
3340 | if (is_10gbt_device(adapter->pdev->device)) { | |
3341 | ret = adap_init0_phy(adapter); | |
3342 | if (ret < 0) | |
3343 | goto bye; | |
3344 | } | |
636f9d37 VP |
3345 | /* |
3346 | * If we have a T4 configuration file under /lib/firmware/cxgb4/, | |
3347 | * then use that. Otherwise, use the configuration file stored | |
3348 | * in the adapter flash ... | |
3349 | */ | |
d14807dd | 3350 | switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { |
0a57a536 | 3351 | case CHELSIO_T4: |
16e47624 | 3352 | fw_config_file = FW4_CFNAME; |
0a57a536 SR |
3353 | break; |
3354 | case CHELSIO_T5: | |
3355 | fw_config_file = FW5_CFNAME; | |
3356 | break; | |
3ccc6cf7 HS |
3357 | case CHELSIO_T6: |
3358 | fw_config_file = FW6_CFNAME; | |
3359 | break; | |
0a57a536 SR |
3360 | default: |
3361 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", | |
3362 | adapter->pdev->device); | |
3363 | ret = -EINVAL; | |
3364 | goto bye; | |
3365 | } | |
3366 | ||
3367 | ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); | |
636f9d37 | 3368 | if (ret < 0) { |
16e47624 | 3369 | config_name = "On FLASH"; |
636f9d37 VP |
3370 | mtype = FW_MEMTYPE_CF_FLASH; |
3371 | maddr = t4_flash_cfg_addr(adapter); | |
3372 | } else { | |
3373 | u32 params[7], val[7]; | |
3374 | ||
16e47624 HS |
3375 | sprintf(fw_config_file_path, |
3376 | "/lib/firmware/%s", fw_config_file); | |
3377 | config_name = fw_config_file_path; | |
3378 | ||
636f9d37 VP |
3379 | if (cf->size >= FLASH_CFG_MAX_SIZE) |
3380 | ret = -ENOMEM; | |
3381 | else { | |
5167865a HS |
3382 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3383 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
636f9d37 | 3384 | ret = t4_query_params(adapter, adapter->mbox, |
b2612722 | 3385 | adapter->pf, 0, 1, params, val); |
636f9d37 VP |
3386 | if (ret == 0) { |
3387 | /* | |
fc5ab020 | 3388 | * For t4_memory_rw() below addresses and |
636f9d37 VP |
3389 | * sizes have to be in terms of multiples of 4 |
3390 | * bytes. So, if the Configuration File isn't | |
3391 | * a multiple of 4 bytes in length we'll have | |
3392 | * to write that out separately since we can't | |
3393 | * guarantee that the bytes following the | |
3394 | * residual byte in the buffer returned by | |
3395 | * request_firmware() are zeroed out ... | |
3396 | */ | |
3397 | size_t resid = cf->size & 0x3; | |
3398 | size_t size = cf->size & ~0x3; | |
3399 | __be32 *data = (__be32 *)cf->data; | |
3400 | ||
5167865a HS |
3401 | mtype = FW_PARAMS_PARAM_Y_G(val[0]); |
3402 | maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; | |
636f9d37 | 3403 | |
fc5ab020 HS |
3404 | spin_lock(&adapter->win0_lock); |
3405 | ret = t4_memory_rw(adapter, 0, mtype, maddr, | |
3406 | size, data, T4_MEMORY_WRITE); | |
636f9d37 VP |
3407 | if (ret == 0 && resid != 0) { |
3408 | union { | |
3409 | __be32 word; | |
3410 | char buf[4]; | |
3411 | } last; | |
3412 | int i; | |
3413 | ||
3414 | last.word = data[size >> 2]; | |
3415 | for (i = resid; i < 4; i++) | |
3416 | last.buf[i] = 0; | |
fc5ab020 HS |
3417 | ret = t4_memory_rw(adapter, 0, mtype, |
3418 | maddr + size, | |
3419 | 4, &last.word, | |
3420 | T4_MEMORY_WRITE); | |
636f9d37 | 3421 | } |
fc5ab020 | 3422 | spin_unlock(&adapter->win0_lock); |
636f9d37 VP |
3423 | } |
3424 | } | |
3425 | ||
3426 | release_firmware(cf); | |
3427 | if (ret) | |
3428 | goto bye; | |
3429 | } | |
3430 | ||
3431 | /* | |
3432 | * Issue a Capability Configuration command to the firmware to get it | |
3433 | * to parse the Configuration File. We don't use t4_fw_config_file() | |
3434 | * because we want the ability to modify various features after we've | |
3435 | * processed the configuration file ... | |
3436 | */ | |
3437 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3438 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3439 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3440 | FW_CMD_REQUEST_F | | |
3441 | FW_CMD_READ_F); | |
ce91a923 | 3442 | caps_cmd.cfvalid_to_len16 = |
5167865a HS |
3443 | htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | |
3444 | FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | | |
3445 | FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | | |
636f9d37 VP |
3446 | FW_LEN16(caps_cmd)); |
3447 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), | |
3448 | &caps_cmd); | |
16e47624 HS |
3449 | |
3450 | /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware | |
3451 | * Configuration File in FLASH), our last gasp effort is to use the | |
3452 | * Firmware Configuration File which is embedded in the firmware. A | |
3453 | * very few early versions of the firmware didn't have one embedded | |
3454 | * but we can ignore those. | |
3455 | */ | |
3456 | if (ret == -ENOENT) { | |
3457 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3458 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3459 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3460 | FW_CMD_REQUEST_F | | |
3461 | FW_CMD_READ_F); | |
16e47624 HS |
3462 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
3463 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, | |
3464 | sizeof(caps_cmd), &caps_cmd); | |
3465 | config_name = "Firmware Default"; | |
3466 | } | |
3467 | ||
3468 | config_issued = 1; | |
636f9d37 VP |
3469 | if (ret < 0) |
3470 | goto bye; | |
3471 | ||
3472 | finiver = ntohl(caps_cmd.finiver); | |
3473 | finicsum = ntohl(caps_cmd.finicsum); | |
3474 | cfcsum = ntohl(caps_cmd.cfcsum); | |
3475 | if (finicsum != cfcsum) | |
3476 | dev_warn(adapter->pdev_dev, "Configuration File checksum "\ | |
3477 | "mismatch: [fini] csum=%#x, computed csum=%#x\n", | |
3478 | finicsum, cfcsum); | |
3479 | ||
636f9d37 VP |
3480 | /* |
3481 | * And now tell the firmware to use the configuration we just loaded. | |
3482 | */ | |
3483 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3484 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3485 | FW_CMD_REQUEST_F | | |
3486 | FW_CMD_WRITE_F); | |
ce91a923 | 3487 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
3488 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), |
3489 | NULL); | |
3490 | if (ret < 0) | |
3491 | goto bye; | |
3492 | ||
3493 | /* | |
3494 | * Tweak configuration based on system architecture, module | |
3495 | * parameters, etc. | |
3496 | */ | |
3497 | ret = adap_init0_tweaks(adapter); | |
3498 | if (ret < 0) | |
3499 | goto bye; | |
3500 | ||
3501 | /* | |
3502 | * And finally tell the firmware to initialize itself using the | |
3503 | * parameters from the Configuration File. | |
3504 | */ | |
3505 | ret = t4_fw_initialize(adapter, adapter->mbox); | |
3506 | if (ret < 0) | |
3507 | goto bye; | |
3508 | ||
06640310 HS |
3509 | /* Emit Firmware Configuration File information and return |
3510 | * successfully. | |
636f9d37 | 3511 | */ |
636f9d37 | 3512 | dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ |
16e47624 HS |
3513 | "Configuration File \"%s\", version %#x, computed checksum %#x\n", |
3514 | config_name, finiver, cfcsum); | |
636f9d37 VP |
3515 | return 0; |
3516 | ||
3517 | /* | |
3518 | * Something bad happened. Return the error ... (If the "error" | |
3519 | * is that there's no Configuration File on the adapter we don't | |
3520 | * want to issue a warning since this is fairly common.) | |
3521 | */ | |
3522 | bye: | |
16e47624 HS |
3523 | if (config_issued && ret != -ENOENT) |
3524 | dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", | |
3525 | config_name, -ret); | |
636f9d37 VP |
3526 | return ret; |
3527 | } | |
3528 | ||
16e47624 HS |
3529 | static struct fw_info fw_info_array[] = { |
3530 | { | |
3531 | .chip = CHELSIO_T4, | |
3532 | .fs_name = FW4_CFNAME, | |
3533 | .fw_mod_name = FW4_FNAME, | |
3534 | .fw_hdr = { | |
3535 | .chip = FW_HDR_CHIP_T4, | |
3536 | .fw_ver = __cpu_to_be32(FW_VERSION(T4)), | |
3537 | .intfver_nic = FW_INTFVER(T4, NIC), | |
3538 | .intfver_vnic = FW_INTFVER(T4, VNIC), | |
3539 | .intfver_ri = FW_INTFVER(T4, RI), | |
3540 | .intfver_iscsi = FW_INTFVER(T4, ISCSI), | |
3541 | .intfver_fcoe = FW_INTFVER(T4, FCOE), | |
3542 | }, | |
3543 | }, { | |
3544 | .chip = CHELSIO_T5, | |
3545 | .fs_name = FW5_CFNAME, | |
3546 | .fw_mod_name = FW5_FNAME, | |
3547 | .fw_hdr = { | |
3548 | .chip = FW_HDR_CHIP_T5, | |
3549 | .fw_ver = __cpu_to_be32(FW_VERSION(T5)), | |
3550 | .intfver_nic = FW_INTFVER(T5, NIC), | |
3551 | .intfver_vnic = FW_INTFVER(T5, VNIC), | |
3552 | .intfver_ri = FW_INTFVER(T5, RI), | |
3553 | .intfver_iscsi = FW_INTFVER(T5, ISCSI), | |
3554 | .intfver_fcoe = FW_INTFVER(T5, FCOE), | |
3555 | }, | |
3ccc6cf7 HS |
3556 | }, { |
3557 | .chip = CHELSIO_T6, | |
3558 | .fs_name = FW6_CFNAME, | |
3559 | .fw_mod_name = FW6_FNAME, | |
3560 | .fw_hdr = { | |
3561 | .chip = FW_HDR_CHIP_T6, | |
3562 | .fw_ver = __cpu_to_be32(FW_VERSION(T6)), | |
3563 | .intfver_nic = FW_INTFVER(T6, NIC), | |
3564 | .intfver_vnic = FW_INTFVER(T6, VNIC), | |
3565 | .intfver_ofld = FW_INTFVER(T6, OFLD), | |
3566 | .intfver_ri = FW_INTFVER(T6, RI), | |
3567 | .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), | |
3568 | .intfver_iscsi = FW_INTFVER(T6, ISCSI), | |
3569 | .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), | |
3570 | .intfver_fcoe = FW_INTFVER(T6, FCOE), | |
3571 | }, | |
16e47624 | 3572 | } |
3ccc6cf7 | 3573 | |
16e47624 HS |
3574 | }; |
3575 | ||
3576 | static struct fw_info *find_fw_info(int chip) | |
3577 | { | |
3578 | int i; | |
3579 | ||
3580 | for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { | |
3581 | if (fw_info_array[i].chip == chip) | |
3582 | return &fw_info_array[i]; | |
3583 | } | |
3584 | return NULL; | |
3585 | } | |
3586 | ||
b8ff05a9 DM |
3587 | /* |
3588 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
3589 | */ | |
3590 | static int adap_init0(struct adapter *adap) | |
3591 | { | |
3592 | int ret; | |
3593 | u32 v, port_vec; | |
3594 | enum dev_state state; | |
3595 | u32 params[7], val[7]; | |
9a4da2cd | 3596 | struct fw_caps_config_cmd caps_cmd; |
dcf7b6f5 | 3597 | int reset = 1; |
b8ff05a9 | 3598 | |
ae469b68 HS |
3599 | /* Grab Firmware Device Log parameters as early as possible so we have |
3600 | * access to it for debugging, etc. | |
3601 | */ | |
3602 | ret = t4_init_devlog_params(adap); | |
3603 | if (ret < 0) | |
3604 | return ret; | |
3605 | ||
666224d4 | 3606 | /* Contact FW, advertising Master capability */ |
c5a8c0f3 HS |
3607 | ret = t4_fw_hello(adap, adap->mbox, adap->mbox, |
3608 | is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); | |
b8ff05a9 DM |
3609 | if (ret < 0) { |
3610 | dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", | |
3611 | ret); | |
3612 | return ret; | |
3613 | } | |
636f9d37 VP |
3614 | if (ret == adap->mbox) |
3615 | adap->flags |= MASTER_PF; | |
b8ff05a9 | 3616 | |
636f9d37 VP |
3617 | /* |
3618 | * If we're the Master PF Driver and the device is uninitialized, | |
3619 | * then let's consider upgrading the firmware ... (We always want | |
3620 | * to check the firmware version number in order to A. get it for | |
3621 | * later reporting and B. to warn if the currently loaded firmware | |
3622 | * is excessively mismatched relative to the driver.) | |
3623 | */ | |
0de72738 | 3624 | |
760446f9 | 3625 | t4_get_version_info(adap); |
a69265e9 HS |
3626 | ret = t4_check_fw_version(adap); |
3627 | /* If firmware is too old (not supported by driver) force an update. */ | |
21d11bd6 | 3628 | if (ret) |
a69265e9 | 3629 | state = DEV_STATE_UNINIT; |
636f9d37 | 3630 | if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { |
16e47624 HS |
3631 | struct fw_info *fw_info; |
3632 | struct fw_hdr *card_fw; | |
3633 | const struct firmware *fw; | |
3634 | const u8 *fw_data = NULL; | |
3635 | unsigned int fw_size = 0; | |
3636 | ||
3637 | /* This is the firmware whose headers the driver was compiled | |
3638 | * against | |
3639 | */ | |
3640 | fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); | |
3641 | if (fw_info == NULL) { | |
3642 | dev_err(adap->pdev_dev, | |
3643 | "unable to get firmware info for chip %d.\n", | |
3644 | CHELSIO_CHIP_VERSION(adap->params.chip)); | |
3645 | return -EINVAL; | |
636f9d37 | 3646 | } |
16e47624 HS |
3647 | |
3648 | /* allocate memory to read the header of the firmware on the | |
3649 | * card | |
3650 | */ | |
752ade68 | 3651 | card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL); |
16e47624 HS |
3652 | |
3653 | /* Get FW from from /lib/firmware/ */ | |
3654 | ret = request_firmware(&fw, fw_info->fw_mod_name, | |
3655 | adap->pdev_dev); | |
3656 | if (ret < 0) { | |
3657 | dev_err(adap->pdev_dev, | |
3658 | "unable to load firmware image %s, error %d\n", | |
3659 | fw_info->fw_mod_name, ret); | |
3660 | } else { | |
3661 | fw_data = fw->data; | |
3662 | fw_size = fw->size; | |
3663 | } | |
3664 | ||
3665 | /* upgrade FW logic */ | |
3666 | ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, | |
3667 | state, &reset); | |
3668 | ||
3669 | /* Cleaning up */ | |
0b5b6bee | 3670 | release_firmware(fw); |
752ade68 | 3671 | kvfree(card_fw); |
16e47624 | 3672 | |
636f9d37 | 3673 | if (ret < 0) |
16e47624 | 3674 | goto bye; |
636f9d37 | 3675 | } |
b8ff05a9 | 3676 | |
636f9d37 VP |
3677 | /* |
3678 | * Grab VPD parameters. This should be done after we establish a | |
3679 | * connection to the firmware since some of the VPD parameters | |
3680 | * (notably the Core Clock frequency) are retrieved via requests to | |
3681 | * the firmware. On the other hand, we need these fairly early on | |
3682 | * so we do this right after getting ahold of the firmware. | |
3683 | */ | |
098ef6c2 | 3684 | ret = t4_get_vpd_params(adap, &adap->params.vpd); |
a0881cab DM |
3685 | if (ret < 0) |
3686 | goto bye; | |
a0881cab | 3687 | |
636f9d37 | 3688 | /* |
13ee15d3 VP |
3689 | * Find out what ports are available to us. Note that we need to do |
3690 | * this before calling adap_init0_no_config() since it needs nports | |
3691 | * and portvec ... | |
636f9d37 VP |
3692 | */ |
3693 | v = | |
5167865a HS |
3694 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3695 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); | |
b2612722 | 3696 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); |
a0881cab DM |
3697 | if (ret < 0) |
3698 | goto bye; | |
3699 | ||
636f9d37 VP |
3700 | adap->params.nports = hweight32(port_vec); |
3701 | adap->params.portvec = port_vec; | |
3702 | ||
06640310 HS |
3703 | /* If the firmware is initialized already, emit a simply note to that |
3704 | * effect. Otherwise, it's time to try initializing the adapter. | |
636f9d37 VP |
3705 | */ |
3706 | if (state == DEV_STATE_INIT) { | |
3707 | dev_info(adap->pdev_dev, "Coming up as %s: "\ | |
3708 | "Adapter already initialized\n", | |
3709 | adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); | |
636f9d37 VP |
3710 | } else { |
3711 | dev_info(adap->pdev_dev, "Coming up as MASTER: "\ | |
3712 | "Initializing adapter\n"); | |
06640310 HS |
3713 | |
3714 | /* Find out whether we're dealing with a version of the | |
3715 | * firmware which has configuration file support. | |
636f9d37 | 3716 | */ |
06640310 HS |
3717 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3718 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
b2612722 | 3719 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, |
06640310 | 3720 | params, val); |
13ee15d3 | 3721 | |
06640310 HS |
3722 | /* If the firmware doesn't support Configuration Files, |
3723 | * return an error. | |
3724 | */ | |
3725 | if (ret < 0) { | |
3726 | dev_err(adap->pdev_dev, "firmware doesn't support " | |
3727 | "Firmware Configuration Files\n"); | |
3728 | goto bye; | |
3729 | } | |
3730 | ||
3731 | /* The firmware provides us with a memory buffer where we can | |
3732 | * load a Configuration File from the host if we want to | |
3733 | * override the Configuration File in flash. | |
3734 | */ | |
3735 | ret = adap_init0_config(adap, reset); | |
3736 | if (ret == -ENOENT) { | |
3737 | dev_err(adap->pdev_dev, "no Configuration File " | |
3738 | "present on adapter.\n"); | |
3739 | goto bye; | |
636f9d37 VP |
3740 | } |
3741 | if (ret < 0) { | |
06640310 HS |
3742 | dev_err(adap->pdev_dev, "could not initialize " |
3743 | "adapter, error %d\n", -ret); | |
636f9d37 VP |
3744 | goto bye; |
3745 | } | |
3746 | } | |
3747 | ||
06640310 HS |
3748 | /* Give the SGE code a chance to pull in anything that it needs ... |
3749 | * Note that this must be called after we retrieve our VPD parameters | |
3750 | * in order to know how to convert core ticks to seconds, etc. | |
636f9d37 | 3751 | */ |
06640310 HS |
3752 | ret = t4_sge_init(adap); |
3753 | if (ret < 0) | |
3754 | goto bye; | |
636f9d37 | 3755 | |
9a4da2cd VP |
3756 | if (is_bypass_device(adap->pdev->device)) |
3757 | adap->params.bypass = 1; | |
3758 | ||
636f9d37 VP |
3759 | /* |
3760 | * Grab some of our basic fundamental operating parameters. | |
3761 | */ | |
3762 | #define FW_PARAM_DEV(param) \ | |
5167865a HS |
3763 | (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ |
3764 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) | |
636f9d37 | 3765 | |
b8ff05a9 | 3766 | #define FW_PARAM_PFVF(param) \ |
5167865a HS |
3767 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ |
3768 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ | |
3769 | FW_PARAMS_PARAM_Y_V(0) | \ | |
3770 | FW_PARAMS_PARAM_Z_V(0) | |
b8ff05a9 | 3771 | |
636f9d37 | 3772 | params[0] = FW_PARAM_PFVF(EQ_START); |
b8ff05a9 DM |
3773 | params[1] = FW_PARAM_PFVF(L2T_START); |
3774 | params[2] = FW_PARAM_PFVF(L2T_END); | |
3775 | params[3] = FW_PARAM_PFVF(FILTER_START); | |
3776 | params[4] = FW_PARAM_PFVF(FILTER_END); | |
e46dab4d | 3777 | params[5] = FW_PARAM_PFVF(IQFLINT_START); |
b2612722 | 3778 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); |
b8ff05a9 DM |
3779 | if (ret < 0) |
3780 | goto bye; | |
636f9d37 VP |
3781 | adap->sge.egr_start = val[0]; |
3782 | adap->l2t_start = val[1]; | |
3783 | adap->l2t_end = val[2]; | |
b8ff05a9 DM |
3784 | adap->tids.ftid_base = val[3]; |
3785 | adap->tids.nftids = val[4] - val[3] + 1; | |
e46dab4d | 3786 | adap->sge.ingr_start = val[5]; |
b8ff05a9 | 3787 | |
4b8e27a8 HS |
3788 | /* qids (ingress/egress) returned from firmware can be anywhere |
3789 | * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. | |
3790 | * Hence driver needs to allocate memory for this range to | |
3791 | * store the queue info. Get the highest IQFLINT/EQ index returned | |
3792 | * in FW_EQ_*_CMD.alloc command. | |
3793 | */ | |
3794 | params[0] = FW_PARAM_PFVF(EQ_END); | |
3795 | params[1] = FW_PARAM_PFVF(IQFLINT_END); | |
b2612722 | 3796 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
4b8e27a8 HS |
3797 | if (ret < 0) |
3798 | goto bye; | |
3799 | adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; | |
3800 | adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; | |
3801 | ||
3802 | adap->sge.egr_map = kcalloc(adap->sge.egr_sz, | |
3803 | sizeof(*adap->sge.egr_map), GFP_KERNEL); | |
3804 | if (!adap->sge.egr_map) { | |
3805 | ret = -ENOMEM; | |
3806 | goto bye; | |
3807 | } | |
3808 | ||
3809 | adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, | |
3810 | sizeof(*adap->sge.ingr_map), GFP_KERNEL); | |
3811 | if (!adap->sge.ingr_map) { | |
3812 | ret = -ENOMEM; | |
3813 | goto bye; | |
3814 | } | |
3815 | ||
3816 | /* Allocate the memory for the vaious egress queue bitmaps | |
5b377d11 | 3817 | * ie starving_fl, txq_maperr and blocked_fl. |
4b8e27a8 HS |
3818 | */ |
3819 | adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3820 | sizeof(long), GFP_KERNEL); | |
3821 | if (!adap->sge.starving_fl) { | |
3822 | ret = -ENOMEM; | |
3823 | goto bye; | |
3824 | } | |
3825 | ||
3826 | adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3827 | sizeof(long), GFP_KERNEL); | |
3828 | if (!adap->sge.txq_maperr) { | |
3829 | ret = -ENOMEM; | |
3830 | goto bye; | |
3831 | } | |
3832 | ||
5b377d11 HS |
3833 | #ifdef CONFIG_DEBUG_FS |
3834 | adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3835 | sizeof(long), GFP_KERNEL); | |
3836 | if (!adap->sge.blocked_fl) { | |
3837 | ret = -ENOMEM; | |
3838 | goto bye; | |
3839 | } | |
3840 | #endif | |
3841 | ||
b5a02f50 AB |
3842 | params[0] = FW_PARAM_PFVF(CLIP_START); |
3843 | params[1] = FW_PARAM_PFVF(CLIP_END); | |
b2612722 | 3844 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
b5a02f50 AB |
3845 | if (ret < 0) |
3846 | goto bye; | |
3847 | adap->clipt_start = val[0]; | |
3848 | adap->clipt_end = val[1]; | |
3849 | ||
b72a32da RL |
3850 | /* We don't yet have a PARAMs calls to retrieve the number of Traffic |
3851 | * Classes supported by the hardware/firmware so we hard code it here | |
3852 | * for now. | |
3853 | */ | |
3854 | adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16; | |
3855 | ||
636f9d37 VP |
3856 | /* query params related to active filter region */ |
3857 | params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); | |
3858 | params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); | |
b2612722 | 3859 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
636f9d37 VP |
3860 | /* If Active filter size is set we enable establishing |
3861 | * offload connection through firmware work request | |
3862 | */ | |
3863 | if ((val[0] != val[1]) && (ret >= 0)) { | |
3864 | adap->flags |= FW_OFLD_CONN; | |
3865 | adap->tids.aftid_base = val[0]; | |
3866 | adap->tids.aftid_end = val[1]; | |
3867 | } | |
3868 | ||
b407a4a9 VP |
3869 | /* If we're running on newer firmware, let it know that we're |
3870 | * prepared to deal with encapsulated CPL messages. Older | |
3871 | * firmware won't understand this and we'll just get | |
3872 | * unencapsulated messages ... | |
3873 | */ | |
3874 | params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); | |
3875 | val[0] = 1; | |
b2612722 | 3876 | (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); |
b407a4a9 | 3877 | |
1ac0f095 KS |
3878 | /* |
3879 | * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL | |
3880 | * capability. Earlier versions of the firmware didn't have the | |
3881 | * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no | |
3882 | * permission to use ULPTX MEMWRITE DSGL. | |
3883 | */ | |
3884 | if (is_t4(adap->params.chip)) { | |
3885 | adap->params.ulptx_memwrite_dsgl = false; | |
3886 | } else { | |
3887 | params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); | |
b2612722 | 3888 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, |
1ac0f095 KS |
3889 | 1, params, val); |
3890 | adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); | |
3891 | } | |
3892 | ||
086de575 SW |
3893 | /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */ |
3894 | params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); | |
3895 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, | |
3896 | 1, params, val); | |
3897 | adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); | |
3898 | ||
636f9d37 VP |
3899 | /* |
3900 | * Get device capabilities so we can determine what resources we need | |
3901 | * to manage. | |
3902 | */ | |
3903 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
e2ac9628 HS |
3904 | caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3905 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 3906 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
3907 | ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), |
3908 | &caps_cmd); | |
3909 | if (ret < 0) | |
3910 | goto bye; | |
3911 | ||
13ee15d3 | 3912 | if (caps_cmd.ofldcaps) { |
b8ff05a9 DM |
3913 | /* query offload-related parameters */ |
3914 | params[0] = FW_PARAM_DEV(NTID); | |
3915 | params[1] = FW_PARAM_PFVF(SERVER_START); | |
3916 | params[2] = FW_PARAM_PFVF(SERVER_END); | |
3917 | params[3] = FW_PARAM_PFVF(TDDP_START); | |
3918 | params[4] = FW_PARAM_PFVF(TDDP_END); | |
3919 | params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); | |
b2612722 | 3920 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 3921 | params, val); |
b8ff05a9 DM |
3922 | if (ret < 0) |
3923 | goto bye; | |
3924 | adap->tids.ntids = val[0]; | |
3925 | adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); | |
3926 | adap->tids.stid_base = val[1]; | |
3927 | adap->tids.nstids = val[2] - val[1] + 1; | |
636f9d37 | 3928 | /* |
dbedd44e | 3929 | * Setup server filter region. Divide the available filter |
636f9d37 VP |
3930 | * region into two parts. Regular filters get 1/3rd and server |
3931 | * filters get 2/3rd part. This is only enabled if workarond | |
3932 | * path is enabled. | |
3933 | * 1. For regular filters. | |
3934 | * 2. Server filter: This are special filters which are used | |
3935 | * to redirect SYN packets to offload queue. | |
3936 | */ | |
3937 | if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { | |
3938 | adap->tids.sftid_base = adap->tids.ftid_base + | |
3939 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
3940 | adap->tids.nsftids = adap->tids.nftids - | |
3941 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
3942 | adap->tids.nftids = adap->tids.sftid_base - | |
3943 | adap->tids.ftid_base; | |
3944 | } | |
b8ff05a9 DM |
3945 | adap->vres.ddp.start = val[3]; |
3946 | adap->vres.ddp.size = val[4] - val[3] + 1; | |
3947 | adap->params.ofldq_wr_cred = val[5]; | |
636f9d37 | 3948 | |
b8ff05a9 | 3949 | adap->params.offload = 1; |
0fbc81b3 | 3950 | adap->num_ofld_uld += 1; |
b8ff05a9 | 3951 | } |
636f9d37 | 3952 | if (caps_cmd.rdmacaps) { |
b8ff05a9 DM |
3953 | params[0] = FW_PARAM_PFVF(STAG_START); |
3954 | params[1] = FW_PARAM_PFVF(STAG_END); | |
3955 | params[2] = FW_PARAM_PFVF(RQ_START); | |
3956 | params[3] = FW_PARAM_PFVF(RQ_END); | |
3957 | params[4] = FW_PARAM_PFVF(PBL_START); | |
3958 | params[5] = FW_PARAM_PFVF(PBL_END); | |
b2612722 | 3959 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 3960 | params, val); |
b8ff05a9 DM |
3961 | if (ret < 0) |
3962 | goto bye; | |
3963 | adap->vres.stag.start = val[0]; | |
3964 | adap->vres.stag.size = val[1] - val[0] + 1; | |
3965 | adap->vres.rq.start = val[2]; | |
3966 | adap->vres.rq.size = val[3] - val[2] + 1; | |
3967 | adap->vres.pbl.start = val[4]; | |
3968 | adap->vres.pbl.size = val[5] - val[4] + 1; | |
a0881cab DM |
3969 | |
3970 | params[0] = FW_PARAM_PFVF(SQRQ_START); | |
3971 | params[1] = FW_PARAM_PFVF(SQRQ_END); | |
3972 | params[2] = FW_PARAM_PFVF(CQ_START); | |
3973 | params[3] = FW_PARAM_PFVF(CQ_END); | |
1ae970e0 DM |
3974 | params[4] = FW_PARAM_PFVF(OCQ_START); |
3975 | params[5] = FW_PARAM_PFVF(OCQ_END); | |
b2612722 | 3976 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, |
5c937dd3 | 3977 | val); |
a0881cab DM |
3978 | if (ret < 0) |
3979 | goto bye; | |
3980 | adap->vres.qp.start = val[0]; | |
3981 | adap->vres.qp.size = val[1] - val[0] + 1; | |
3982 | adap->vres.cq.start = val[2]; | |
3983 | adap->vres.cq.size = val[3] - val[2] + 1; | |
1ae970e0 DM |
3984 | adap->vres.ocq.start = val[4]; |
3985 | adap->vres.ocq.size = val[5] - val[4] + 1; | |
4c2c5763 HS |
3986 | |
3987 | params[0] = FW_PARAM_DEV(MAXORDIRD_QP); | |
3988 | params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); | |
b2612722 | 3989 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, |
5c937dd3 | 3990 | val); |
4c2c5763 HS |
3991 | if (ret < 0) { |
3992 | adap->params.max_ordird_qp = 8; | |
3993 | adap->params.max_ird_adapter = 32 * adap->tids.ntids; | |
3994 | ret = 0; | |
3995 | } else { | |
3996 | adap->params.max_ordird_qp = val[0]; | |
3997 | adap->params.max_ird_adapter = val[1]; | |
3998 | } | |
3999 | dev_info(adap->pdev_dev, | |
4000 | "max_ordird_qp %d max_ird_adapter %d\n", | |
4001 | adap->params.max_ordird_qp, | |
4002 | adap->params.max_ird_adapter); | |
0fbc81b3 | 4003 | adap->num_ofld_uld += 2; |
b8ff05a9 | 4004 | } |
636f9d37 | 4005 | if (caps_cmd.iscsicaps) { |
b8ff05a9 DM |
4006 | params[0] = FW_PARAM_PFVF(ISCSI_START); |
4007 | params[1] = FW_PARAM_PFVF(ISCSI_END); | |
b2612722 | 4008 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, |
636f9d37 | 4009 | params, val); |
b8ff05a9 DM |
4010 | if (ret < 0) |
4011 | goto bye; | |
4012 | adap->vres.iscsi.start = val[0]; | |
4013 | adap->vres.iscsi.size = val[1] - val[0] + 1; | |
0fbc81b3 HS |
4014 | /* LIO target and cxgb4i initiaitor */ |
4015 | adap->num_ofld_uld += 2; | |
b8ff05a9 | 4016 | } |
94cdb8bb HS |
4017 | if (caps_cmd.cryptocaps) { |
4018 | /* Should query params here...TODO */ | |
72a56ca9 HJ |
4019 | params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE); |
4020 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, | |
4021 | params, val); | |
4022 | if (ret < 0) { | |
4023 | if (ret != -EINVAL) | |
4024 | goto bye; | |
4025 | } else { | |
4026 | adap->vres.ncrypto_fc = val[0]; | |
4027 | } | |
94cdb8bb HS |
4028 | adap->params.crypto |= ULP_CRYPTO_LOOKASIDE; |
4029 | adap->num_uld += 1; | |
4030 | } | |
b8ff05a9 DM |
4031 | #undef FW_PARAM_PFVF |
4032 | #undef FW_PARAM_DEV | |
4033 | ||
92e7ae71 HS |
4034 | /* The MTU/MSS Table is initialized by now, so load their values. If |
4035 | * we're initializing the adapter, then we'll make any modifications | |
4036 | * we want to the MTU/MSS Table and also initialize the congestion | |
4037 | * parameters. | |
636f9d37 | 4038 | */ |
b8ff05a9 | 4039 | t4_read_mtu_tbl(adap, adap->params.mtus, NULL); |
92e7ae71 HS |
4040 | if (state != DEV_STATE_INIT) { |
4041 | int i; | |
4042 | ||
4043 | /* The default MTU Table contains values 1492 and 1500. | |
4044 | * However, for TCP, it's better to have two values which are | |
4045 | * a multiple of 8 +/- 4 bytes apart near this popular MTU. | |
4046 | * This allows us to have a TCP Data Payload which is a | |
4047 | * multiple of 8 regardless of what combination of TCP Options | |
4048 | * are in use (always a multiple of 4 bytes) which is | |
4049 | * important for performance reasons. For instance, if no | |
4050 | * options are in use, then we have a 20-byte IP header and a | |
4051 | * 20-byte TCP header. In this case, a 1500-byte MSS would | |
4052 | * result in a TCP Data Payload of 1500 - 40 == 1460 bytes | |
4053 | * which is not a multiple of 8. So using an MSS of 1488 in | |
4054 | * this case results in a TCP Data Payload of 1448 bytes which | |
4055 | * is a multiple of 8. On the other hand, if 12-byte TCP Time | |
4056 | * Stamps have been negotiated, then an MTU of 1500 bytes | |
4057 | * results in a TCP Data Payload of 1448 bytes which, as | |
4058 | * above, is a multiple of 8 bytes ... | |
4059 | */ | |
4060 | for (i = 0; i < NMTUS; i++) | |
4061 | if (adap->params.mtus[i] == 1492) { | |
4062 | adap->params.mtus[i] = 1488; | |
4063 | break; | |
4064 | } | |
7ee9ff94 | 4065 | |
92e7ae71 HS |
4066 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, |
4067 | adap->params.b_wnd); | |
4068 | } | |
df64e4d3 | 4069 | t4_init_sge_params(adap); |
636f9d37 | 4070 | adap->flags |= FW_OK; |
c1e9af0c | 4071 | t4_init_tp_params(adap); |
b8ff05a9 DM |
4072 | return 0; |
4073 | ||
4074 | /* | |
636f9d37 VP |
4075 | * Something bad happened. If a command timed out or failed with EIO |
4076 | * FW does not operate within its spec or something catastrophic | |
4077 | * happened to HW/FW, stop issuing commands. | |
b8ff05a9 | 4078 | */ |
636f9d37 | 4079 | bye: |
4b8e27a8 HS |
4080 | kfree(adap->sge.egr_map); |
4081 | kfree(adap->sge.ingr_map); | |
4082 | kfree(adap->sge.starving_fl); | |
4083 | kfree(adap->sge.txq_maperr); | |
5b377d11 HS |
4084 | #ifdef CONFIG_DEBUG_FS |
4085 | kfree(adap->sge.blocked_fl); | |
4086 | #endif | |
636f9d37 VP |
4087 | if (ret != -ETIMEDOUT && ret != -EIO) |
4088 | t4_fw_bye(adap, adap->mbox); | |
b8ff05a9 DM |
4089 | return ret; |
4090 | } | |
4091 | ||
204dc3c0 DM |
4092 | /* EEH callbacks */ |
4093 | ||
4094 | static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, | |
4095 | pci_channel_state_t state) | |
4096 | { | |
4097 | int i; | |
4098 | struct adapter *adap = pci_get_drvdata(pdev); | |
4099 | ||
4100 | if (!adap) | |
4101 | goto out; | |
4102 | ||
4103 | rtnl_lock(); | |
4104 | adap->flags &= ~FW_OK; | |
4105 | notify_ulds(adap, CXGB4_STATE_START_RECOVERY); | |
9fe6cb58 | 4106 | spin_lock(&adap->stats_lock); |
204dc3c0 DM |
4107 | for_each_port(adap, i) { |
4108 | struct net_device *dev = adap->port[i]; | |
025d0973 GP |
4109 | if (dev) { |
4110 | netif_device_detach(dev); | |
4111 | netif_carrier_off(dev); | |
4112 | } | |
204dc3c0 | 4113 | } |
9fe6cb58 | 4114 | spin_unlock(&adap->stats_lock); |
b37987e8 | 4115 | disable_interrupts(adap); |
204dc3c0 DM |
4116 | if (adap->flags & FULL_INIT_DONE) |
4117 | cxgb_down(adap); | |
4118 | rtnl_unlock(); | |
144be3d9 GS |
4119 | if ((adap->flags & DEV_ENABLED)) { |
4120 | pci_disable_device(pdev); | |
4121 | adap->flags &= ~DEV_ENABLED; | |
4122 | } | |
204dc3c0 DM |
4123 | out: return state == pci_channel_io_perm_failure ? |
4124 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
4125 | } | |
4126 | ||
4127 | static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) | |
4128 | { | |
4129 | int i, ret; | |
4130 | struct fw_caps_config_cmd c; | |
4131 | struct adapter *adap = pci_get_drvdata(pdev); | |
4132 | ||
4133 | if (!adap) { | |
4134 | pci_restore_state(pdev); | |
4135 | pci_save_state(pdev); | |
4136 | return PCI_ERS_RESULT_RECOVERED; | |
4137 | } | |
4138 | ||
144be3d9 GS |
4139 | if (!(adap->flags & DEV_ENABLED)) { |
4140 | if (pci_enable_device(pdev)) { | |
4141 | dev_err(&pdev->dev, "Cannot reenable PCI " | |
4142 | "device after reset\n"); | |
4143 | return PCI_ERS_RESULT_DISCONNECT; | |
4144 | } | |
4145 | adap->flags |= DEV_ENABLED; | |
204dc3c0 DM |
4146 | } |
4147 | ||
4148 | pci_set_master(pdev); | |
4149 | pci_restore_state(pdev); | |
4150 | pci_save_state(pdev); | |
4151 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
4152 | ||
8203b509 | 4153 | if (t4_wait_dev_ready(adap->regs) < 0) |
204dc3c0 | 4154 | return PCI_ERS_RESULT_DISCONNECT; |
b2612722 | 4155 | if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) |
204dc3c0 DM |
4156 | return PCI_ERS_RESULT_DISCONNECT; |
4157 | adap->flags |= FW_OK; | |
4158 | if (adap_init1(adap, &c)) | |
4159 | return PCI_ERS_RESULT_DISCONNECT; | |
4160 | ||
4161 | for_each_port(adap, i) { | |
4162 | struct port_info *p = adap2pinfo(adap, i); | |
4163 | ||
b2612722 | 4164 | ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, |
060e0c75 | 4165 | NULL, NULL); |
204dc3c0 DM |
4166 | if (ret < 0) |
4167 | return PCI_ERS_RESULT_DISCONNECT; | |
4168 | p->viid = ret; | |
4169 | p->xact_addr_filt = -1; | |
4170 | } | |
4171 | ||
4172 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, | |
4173 | adap->params.b_wnd); | |
1ae970e0 | 4174 | setup_memwin(adap); |
204dc3c0 DM |
4175 | if (cxgb_up(adap)) |
4176 | return PCI_ERS_RESULT_DISCONNECT; | |
4177 | return PCI_ERS_RESULT_RECOVERED; | |
4178 | } | |
4179 | ||
4180 | static void eeh_resume(struct pci_dev *pdev) | |
4181 | { | |
4182 | int i; | |
4183 | struct adapter *adap = pci_get_drvdata(pdev); | |
4184 | ||
4185 | if (!adap) | |
4186 | return; | |
4187 | ||
4188 | rtnl_lock(); | |
4189 | for_each_port(adap, i) { | |
4190 | struct net_device *dev = adap->port[i]; | |
025d0973 GP |
4191 | if (dev) { |
4192 | if (netif_running(dev)) { | |
4193 | link_start(dev); | |
4194 | cxgb_set_rxmode(dev); | |
4195 | } | |
4196 | netif_device_attach(dev); | |
204dc3c0 | 4197 | } |
204dc3c0 DM |
4198 | } |
4199 | rtnl_unlock(); | |
4200 | } | |
4201 | ||
3646f0e5 | 4202 | static const struct pci_error_handlers cxgb4_eeh = { |
204dc3c0 DM |
4203 | .error_detected = eeh_err_detected, |
4204 | .slot_reset = eeh_slot_reset, | |
4205 | .resume = eeh_resume, | |
4206 | }; | |
4207 | ||
9b86a8d1 HS |
4208 | /* Return true if the Link Configuration supports "High Speeds" (those greater |
4209 | * than 1Gb/s). | |
4210 | */ | |
57d8b764 | 4211 | static inline bool is_x_10g_port(const struct link_config *lc) |
b8ff05a9 | 4212 | { |
9b86a8d1 HS |
4213 | unsigned int speeds, high_speeds; |
4214 | ||
4215 | speeds = FW_PORT_CAP_SPEED_V(FW_PORT_CAP_SPEED_G(lc->supported)); | |
4216 | high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G); | |
4217 | ||
4218 | return high_speeds != 0; | |
b8ff05a9 DM |
4219 | } |
4220 | ||
b8ff05a9 DM |
4221 | /* |
4222 | * Perform default configuration of DMA queues depending on the number and type | |
4223 | * of ports we found and the number of available CPUs. Most settings can be | |
4224 | * modified by the admin prior to actual use. | |
4225 | */ | |
91744948 | 4226 | static void cfg_queues(struct adapter *adap) |
b8ff05a9 DM |
4227 | { |
4228 | struct sge *s = &adap->sge; | |
ab677ff4 | 4229 | int i = 0, n10g = 0, qidx = 0; |
688848b1 AB |
4230 | #ifndef CONFIG_CHELSIO_T4_DCB |
4231 | int q10g = 0; | |
4232 | #endif | |
b8ff05a9 | 4233 | |
94cdb8bb HS |
4234 | /* Reduce memory usage in kdump environment, disable all offload. |
4235 | */ | |
85eacf3f | 4236 | if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) { |
0fbc81b3 | 4237 | adap->params.offload = 0; |
94cdb8bb HS |
4238 | adap->params.crypto = 0; |
4239 | } | |
4240 | ||
ab677ff4 | 4241 | n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); |
688848b1 AB |
4242 | #ifdef CONFIG_CHELSIO_T4_DCB |
4243 | /* For Data Center Bridging support we need to be able to support up | |
4244 | * to 8 Traffic Priorities; each of which will be assigned to its | |
4245 | * own TX Queue in order to prevent Head-Of-Line Blocking. | |
4246 | */ | |
4247 | if (adap->params.nports * 8 > MAX_ETH_QSETS) { | |
4248 | dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n", | |
4249 | MAX_ETH_QSETS, adap->params.nports * 8); | |
4250 | BUG_ON(1); | |
4251 | } | |
b8ff05a9 | 4252 | |
688848b1 AB |
4253 | for_each_port(adap, i) { |
4254 | struct port_info *pi = adap2pinfo(adap, i); | |
4255 | ||
4256 | pi->first_qset = qidx; | |
85eacf3f | 4257 | pi->nqsets = is_kdump_kernel() ? 1 : 8; |
688848b1 AB |
4258 | qidx += pi->nqsets; |
4259 | } | |
4260 | #else /* !CONFIG_CHELSIO_T4_DCB */ | |
b8ff05a9 DM |
4261 | /* |
4262 | * We default to 1 queue per non-10G port and up to # of cores queues | |
4263 | * per 10G port. | |
4264 | */ | |
4265 | if (n10g) | |
4266 | q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; | |
5952dde7 YM |
4267 | if (q10g > netif_get_num_default_rss_queues()) |
4268 | q10g = netif_get_num_default_rss_queues(); | |
b8ff05a9 | 4269 | |
85eacf3f GG |
4270 | if (is_kdump_kernel()) |
4271 | q10g = 1; | |
4272 | ||
b8ff05a9 DM |
4273 | for_each_port(adap, i) { |
4274 | struct port_info *pi = adap2pinfo(adap, i); | |
4275 | ||
4276 | pi->first_qset = qidx; | |
57d8b764 | 4277 | pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; |
b8ff05a9 DM |
4278 | qidx += pi->nqsets; |
4279 | } | |
688848b1 | 4280 | #endif /* !CONFIG_CHELSIO_T4_DCB */ |
b8ff05a9 DM |
4281 | |
4282 | s->ethqsets = qidx; | |
4283 | s->max_ethqsets = qidx; /* MSI-X may lower it later */ | |
4284 | ||
0fbc81b3 | 4285 | if (is_uld(adap)) { |
b8ff05a9 DM |
4286 | /* |
4287 | * For offload we use 1 queue/channel if all ports are up to 1G, | |
4288 | * otherwise we divide all available queues amongst the channels | |
4289 | * capped by the number of available cores. | |
4290 | */ | |
4291 | if (n10g) { | |
a56177e1 | 4292 | i = min_t(int, MAX_OFLD_QSETS, num_online_cpus()); |
0fbc81b3 HS |
4293 | s->ofldqsets = roundup(i, adap->params.nports); |
4294 | } else { | |
4295 | s->ofldqsets = adap->params.nports; | |
4296 | } | |
b8ff05a9 DM |
4297 | } |
4298 | ||
4299 | for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { | |
4300 | struct sge_eth_rxq *r = &s->ethrxq[i]; | |
4301 | ||
c887ad0e | 4302 | init_rspq(adap, &r->rspq, 5, 10, 1024, 64); |
b8ff05a9 DM |
4303 | r->fl.size = 72; |
4304 | } | |
4305 | ||
4306 | for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) | |
4307 | s->ethtxq[i].q.size = 1024; | |
4308 | ||
4309 | for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) | |
4310 | s->ctrlq[i].q.size = 512; | |
4311 | ||
a4569504 AG |
4312 | if (!is_t4(adap->params.chip)) |
4313 | s->ptptxq.q.size = 8; | |
4314 | ||
c887ad0e | 4315 | init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); |
0fbc81b3 | 4316 | init_rspq(adap, &s->intrq, 0, 1, 512, 64); |
b8ff05a9 DM |
4317 | } |
4318 | ||
4319 | /* | |
4320 | * Reduce the number of Ethernet queues across all ports to at most n. | |
4321 | * n provides at least one queue per port. | |
4322 | */ | |
91744948 | 4323 | static void reduce_ethqs(struct adapter *adap, int n) |
b8ff05a9 DM |
4324 | { |
4325 | int i; | |
4326 | struct port_info *pi; | |
4327 | ||
4328 | while (n < adap->sge.ethqsets) | |
4329 | for_each_port(adap, i) { | |
4330 | pi = adap2pinfo(adap, i); | |
4331 | if (pi->nqsets > 1) { | |
4332 | pi->nqsets--; | |
4333 | adap->sge.ethqsets--; | |
4334 | if (adap->sge.ethqsets <= n) | |
4335 | break; | |
4336 | } | |
4337 | } | |
4338 | ||
4339 | n = 0; | |
4340 | for_each_port(adap, i) { | |
4341 | pi = adap2pinfo(adap, i); | |
4342 | pi->first_qset = n; | |
4343 | n += pi->nqsets; | |
4344 | } | |
4345 | } | |
4346 | ||
94cdb8bb HS |
4347 | static int get_msix_info(struct adapter *adap) |
4348 | { | |
4349 | struct uld_msix_info *msix_info; | |
0fbc81b3 HS |
4350 | unsigned int max_ingq = 0; |
4351 | ||
4352 | if (is_offload(adap)) | |
4353 | max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld; | |
4354 | if (is_pci_uld(adap)) | |
4355 | max_ingq += MAX_OFLD_QSETS * adap->num_uld; | |
4356 | ||
4357 | if (!max_ingq) | |
4358 | goto out; | |
94cdb8bb HS |
4359 | |
4360 | msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL); | |
4361 | if (!msix_info) | |
4362 | return -ENOMEM; | |
4363 | ||
4364 | adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq), | |
4365 | sizeof(long), GFP_KERNEL); | |
4366 | if (!adap->msix_bmap_ulds.msix_bmap) { | |
4367 | kfree(msix_info); | |
4368 | return -ENOMEM; | |
4369 | } | |
4370 | spin_lock_init(&adap->msix_bmap_ulds.lock); | |
4371 | adap->msix_info_ulds = msix_info; | |
0fbc81b3 | 4372 | out: |
94cdb8bb HS |
4373 | return 0; |
4374 | } | |
4375 | ||
4376 | static void free_msix_info(struct adapter *adap) | |
4377 | { | |
0fbc81b3 | 4378 | if (!(adap->num_uld && adap->num_ofld_uld)) |
94cdb8bb HS |
4379 | return; |
4380 | ||
4381 | kfree(adap->msix_info_ulds); | |
4382 | kfree(adap->msix_bmap_ulds.msix_bmap); | |
4383 | } | |
4384 | ||
b8ff05a9 DM |
4385 | /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ |
4386 | #define EXTRA_VECS 2 | |
4387 | ||
91744948 | 4388 | static int enable_msix(struct adapter *adap) |
b8ff05a9 | 4389 | { |
94cdb8bb HS |
4390 | int ofld_need = 0, uld_need = 0; |
4391 | int i, j, want, need, allocated; | |
b8ff05a9 DM |
4392 | struct sge *s = &adap->sge; |
4393 | unsigned int nchan = adap->params.nports; | |
f36e58e5 | 4394 | struct msix_entry *entries; |
94cdb8bb | 4395 | int max_ingq = MAX_INGQ; |
f36e58e5 | 4396 | |
0fbc81b3 HS |
4397 | if (is_pci_uld(adap)) |
4398 | max_ingq += (MAX_OFLD_QSETS * adap->num_uld); | |
4399 | if (is_offload(adap)) | |
4400 | max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld); | |
94cdb8bb | 4401 | entries = kmalloc(sizeof(*entries) * (max_ingq + 1), |
f36e58e5 HS |
4402 | GFP_KERNEL); |
4403 | if (!entries) | |
4404 | return -ENOMEM; | |
b8ff05a9 | 4405 | |
94cdb8bb | 4406 | /* map for msix */ |
0fbc81b3 HS |
4407 | if (get_msix_info(adap)) { |
4408 | adap->params.offload = 0; | |
94cdb8bb | 4409 | adap->params.crypto = 0; |
0fbc81b3 | 4410 | } |
94cdb8bb HS |
4411 | |
4412 | for (i = 0; i < max_ingq + 1; ++i) | |
b8ff05a9 DM |
4413 | entries[i].entry = i; |
4414 | ||
4415 | want = s->max_ethqsets + EXTRA_VECS; | |
4416 | if (is_offload(adap)) { | |
0fbc81b3 HS |
4417 | want += adap->num_ofld_uld * s->ofldqsets; |
4418 | ofld_need = adap->num_ofld_uld * nchan; | |
b8ff05a9 | 4419 | } |
94cdb8bb | 4420 | if (is_pci_uld(adap)) { |
0fbc81b3 HS |
4421 | want += adap->num_uld * s->ofldqsets; |
4422 | uld_need = adap->num_uld * nchan; | |
94cdb8bb | 4423 | } |
688848b1 AB |
4424 | #ifdef CONFIG_CHELSIO_T4_DCB |
4425 | /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for | |
4426 | * each port. | |
4427 | */ | |
94cdb8bb | 4428 | need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need; |
688848b1 | 4429 | #else |
94cdb8bb | 4430 | need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need; |
688848b1 | 4431 | #endif |
f36e58e5 HS |
4432 | allocated = pci_enable_msix_range(adap->pdev, entries, need, want); |
4433 | if (allocated < 0) { | |
4434 | dev_info(adap->pdev_dev, "not enough MSI-X vectors left," | |
4435 | " not using MSI-X\n"); | |
4436 | kfree(entries); | |
4437 | return allocated; | |
4438 | } | |
b8ff05a9 | 4439 | |
f36e58e5 | 4440 | /* Distribute available vectors to the various queue groups. |
c32ad224 AG |
4441 | * Every group gets its minimum requirement and NIC gets top |
4442 | * priority for leftovers. | |
4443 | */ | |
94cdb8bb | 4444 | i = allocated - EXTRA_VECS - ofld_need - uld_need; |
c32ad224 AG |
4445 | if (i < s->max_ethqsets) { |
4446 | s->max_ethqsets = i; | |
4447 | if (i < s->ethqsets) | |
4448 | reduce_ethqs(adap, i); | |
4449 | } | |
0fbc81b3 | 4450 | if (is_uld(adap)) { |
94cdb8bb HS |
4451 | if (allocated < want) |
4452 | s->nqs_per_uld = nchan; | |
4453 | else | |
0fbc81b3 | 4454 | s->nqs_per_uld = s->ofldqsets; |
94cdb8bb HS |
4455 | } |
4456 | ||
0fbc81b3 | 4457 | for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i) |
c32ad224 | 4458 | adap->msix_info[i].vec = entries[i].vector; |
0fbc81b3 HS |
4459 | if (is_uld(adap)) { |
4460 | for (j = 0 ; i < allocated; ++i, j++) { | |
94cdb8bb | 4461 | adap->msix_info_ulds[j].vec = entries[i].vector; |
0fbc81b3 HS |
4462 | adap->msix_info_ulds[j].idx = i; |
4463 | } | |
94cdb8bb HS |
4464 | adap->msix_bmap_ulds.mapsize = j; |
4465 | } | |
43eb4e82 | 4466 | dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " |
0fbc81b3 HS |
4467 | "nic %d per uld %d\n", |
4468 | allocated, s->max_ethqsets, s->nqs_per_uld); | |
c32ad224 | 4469 | |
f36e58e5 | 4470 | kfree(entries); |
c32ad224 | 4471 | return 0; |
b8ff05a9 DM |
4472 | } |
4473 | ||
4474 | #undef EXTRA_VECS | |
4475 | ||
91744948 | 4476 | static int init_rss(struct adapter *adap) |
671b0060 | 4477 | { |
c035e183 HS |
4478 | unsigned int i; |
4479 | int err; | |
4480 | ||
4481 | err = t4_init_rss_mode(adap, adap->mbox); | |
4482 | if (err) | |
4483 | return err; | |
671b0060 DM |
4484 | |
4485 | for_each_port(adap, i) { | |
4486 | struct port_info *pi = adap2pinfo(adap, i); | |
4487 | ||
4488 | pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); | |
4489 | if (!pi->rss) | |
4490 | return -ENOMEM; | |
671b0060 DM |
4491 | } |
4492 | return 0; | |
4493 | } | |
4494 | ||
547fd272 HS |
4495 | static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap, |
4496 | enum pci_bus_speed *speed, | |
4497 | enum pcie_link_width *width) | |
4498 | { | |
4499 | u32 lnkcap1, lnkcap2; | |
4500 | int err1, err2; | |
4501 | ||
4502 | #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ | |
4503 | ||
4504 | *speed = PCI_SPEED_UNKNOWN; | |
4505 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4506 | ||
4507 | err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP, | |
4508 | &lnkcap1); | |
4509 | err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2, | |
4510 | &lnkcap2); | |
4511 | if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ | |
4512 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
4513 | *speed = PCIE_SPEED_8_0GT; | |
4514 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
4515 | *speed = PCIE_SPEED_5_0GT; | |
4516 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
4517 | *speed = PCIE_SPEED_2_5GT; | |
4518 | } | |
4519 | if (!err1) { | |
4520 | *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; | |
4521 | if (!lnkcap2) { /* pre-r3.0 */ | |
4522 | if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) | |
4523 | *speed = PCIE_SPEED_5_0GT; | |
4524 | else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) | |
4525 | *speed = PCIE_SPEED_2_5GT; | |
4526 | } | |
4527 | } | |
4528 | ||
4529 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
4530 | return err1 ? err1 : err2 ? err2 : -EINVAL; | |
4531 | return 0; | |
4532 | } | |
4533 | ||
4534 | static void cxgb4_check_pcie_caps(struct adapter *adap) | |
4535 | { | |
4536 | enum pcie_link_width width, width_cap; | |
4537 | enum pci_bus_speed speed, speed_cap; | |
4538 | ||
4539 | #define PCIE_SPEED_STR(speed) \ | |
4540 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ | |
4541 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ | |
4542 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ | |
4543 | "Unknown") | |
4544 | ||
4545 | if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) { | |
4546 | dev_warn(adap->pdev_dev, | |
4547 | "Unable to determine PCIe device BW capabilities\n"); | |
4548 | return; | |
4549 | } | |
4550 | ||
4551 | if (pcie_get_minimum_link(adap->pdev, &speed, &width) || | |
4552 | speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { | |
4553 | dev_warn(adap->pdev_dev, | |
4554 | "Unable to determine PCI Express bandwidth.\n"); | |
4555 | return; | |
4556 | } | |
4557 | ||
4558 | dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n", | |
4559 | PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); | |
4560 | dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n", | |
4561 | width, width_cap); | |
4562 | if (speed < speed_cap || width < width_cap) | |
4563 | dev_info(adap->pdev_dev, | |
4564 | "A slot with more lanes and/or higher speed is " | |
4565 | "suggested for optimal performance.\n"); | |
4566 | } | |
4567 | ||
0de72738 HS |
4568 | /* Dump basic information about the adapter */ |
4569 | static void print_adapter_info(struct adapter *adapter) | |
4570 | { | |
760446f9 GG |
4571 | /* Hardware/Firmware/etc. Version/Revision IDs */ |
4572 | t4_dump_version_info(adapter); | |
0de72738 HS |
4573 | |
4574 | /* Software/Hardware configuration */ | |
4575 | dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", | |
4576 | is_offload(adapter) ? "R" : "", | |
4577 | ((adapter->flags & USING_MSIX) ? "MSI-X" : | |
4578 | (adapter->flags & USING_MSI) ? "MSI" : ""), | |
4579 | is_offload(adapter) ? "Offload" : "non-Offload"); | |
4580 | } | |
4581 | ||
91744948 | 4582 | static void print_port_info(const struct net_device *dev) |
b8ff05a9 | 4583 | { |
b8ff05a9 | 4584 | char buf[80]; |
118969ed | 4585 | char *bufp = buf; |
f1a051b9 | 4586 | const char *spd = ""; |
118969ed DM |
4587 | const struct port_info *pi = netdev_priv(dev); |
4588 | const struct adapter *adap = pi->adapter; | |
f1a051b9 DM |
4589 | |
4590 | if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) | |
4591 | spd = " 2.5 GT/s"; | |
4592 | else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) | |
4593 | spd = " 5 GT/s"; | |
d2e752db RD |
4594 | else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) |
4595 | spd = " 8 GT/s"; | |
b8ff05a9 | 4596 | |
118969ed | 4597 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M) |
5e78f7fd | 4598 | bufp += sprintf(bufp, "100M/"); |
118969ed | 4599 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) |
5e78f7fd | 4600 | bufp += sprintf(bufp, "1G/"); |
118969ed DM |
4601 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) |
4602 | bufp += sprintf(bufp, "10G/"); | |
9b86a8d1 HS |
4603 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) |
4604 | bufp += sprintf(bufp, "25G/"); | |
72aca4bf KS |
4605 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) |
4606 | bufp += sprintf(bufp, "40G/"); | |
9b86a8d1 HS |
4607 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) |
4608 | bufp += sprintf(bufp, "100G/"); | |
118969ed DM |
4609 | if (bufp != buf) |
4610 | --bufp; | |
72aca4bf | 4611 | sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); |
118969ed | 4612 | |
0de72738 HS |
4613 | netdev_info(dev, "%s: Chelsio %s (%s) %s\n", |
4614 | dev->name, adap->params.vpd.id, adap->name, buf); | |
b8ff05a9 DM |
4615 | } |
4616 | ||
91744948 | 4617 | static void enable_pcie_relaxed_ordering(struct pci_dev *dev) |
ef306b50 | 4618 | { |
e5c8ae5f | 4619 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); |
ef306b50 DM |
4620 | } |
4621 | ||
06546391 DM |
4622 | /* |
4623 | * Free the following resources: | |
4624 | * - memory used for tables | |
4625 | * - MSI/MSI-X | |
4626 | * - net devices | |
4627 | * - resources FW is holding for us | |
4628 | */ | |
4629 | static void free_some_resources(struct adapter *adapter) | |
4630 | { | |
4631 | unsigned int i; | |
4632 | ||
752ade68 | 4633 | kvfree(adapter->l2t); |
b72a32da | 4634 | t4_cleanup_sched(adapter); |
752ade68 | 4635 | kvfree(adapter->tids.tid_tab); |
d8931847 | 4636 | cxgb4_cleanup_tc_u32(adapter); |
4b8e27a8 HS |
4637 | kfree(adapter->sge.egr_map); |
4638 | kfree(adapter->sge.ingr_map); | |
4639 | kfree(adapter->sge.starving_fl); | |
4640 | kfree(adapter->sge.txq_maperr); | |
5b377d11 HS |
4641 | #ifdef CONFIG_DEBUG_FS |
4642 | kfree(adapter->sge.blocked_fl); | |
4643 | #endif | |
06546391 DM |
4644 | disable_msi(adapter); |
4645 | ||
4646 | for_each_port(adapter, i) | |
671b0060 | 4647 | if (adapter->port[i]) { |
4f3a0fcf HS |
4648 | struct port_info *pi = adap2pinfo(adapter, i); |
4649 | ||
4650 | if (pi->viid != 0) | |
4651 | t4_free_vi(adapter, adapter->mbox, adapter->pf, | |
4652 | 0, pi->viid); | |
671b0060 | 4653 | kfree(adap2pinfo(adapter, i)->rss); |
06546391 | 4654 | free_netdev(adapter->port[i]); |
671b0060 | 4655 | } |
06546391 | 4656 | if (adapter->flags & FW_OK) |
b2612722 | 4657 | t4_fw_bye(adapter, adapter->pf); |
06546391 DM |
4658 | } |
4659 | ||
2ed28baa | 4660 | #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) |
35d35682 | 4661 | #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ |
b8ff05a9 | 4662 | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) |
22adfe0a | 4663 | #define SEGMENT_SIZE 128 |
b8ff05a9 | 4664 | |
d86bd29e HS |
4665 | static int get_chip_type(struct pci_dev *pdev, u32 pl_rev) |
4666 | { | |
d86bd29e HS |
4667 | u16 device_id; |
4668 | ||
4669 | /* Retrieve adapter's device ID */ | |
4670 | pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); | |
46cdc9be | 4671 | |
4672 | switch (device_id >> 12) { | |
d86bd29e | 4673 | case CHELSIO_T4: |
46cdc9be | 4674 | return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); |
d86bd29e | 4675 | case CHELSIO_T5: |
46cdc9be | 4676 | return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); |
d86bd29e | 4677 | case CHELSIO_T6: |
46cdc9be | 4678 | return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); |
d86bd29e HS |
4679 | default: |
4680 | dev_err(&pdev->dev, "Device %d is not supported\n", | |
4681 | device_id); | |
d86bd29e | 4682 | } |
46cdc9be | 4683 | return -EINVAL; |
d86bd29e HS |
4684 | } |
4685 | ||
b6244201 | 4686 | #ifdef CONFIG_PCI_IOV |
e7b48a32 HS |
4687 | static void dummy_setup(struct net_device *dev) |
4688 | { | |
4689 | dev->type = ARPHRD_NONE; | |
4690 | dev->mtu = 0; | |
4691 | dev->hard_header_len = 0; | |
4692 | dev->addr_len = 0; | |
4693 | dev->tx_queue_len = 0; | |
4694 | dev->flags |= IFF_NOARP; | |
4695 | dev->priv_flags |= IFF_NO_QUEUE; | |
4696 | ||
4697 | /* Initialize the device structure. */ | |
4698 | dev->netdev_ops = &cxgb4_mgmt_netdev_ops; | |
4699 | dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops; | |
cf124db5 | 4700 | dev->needs_free_netdev = true; |
e7b48a32 HS |
4701 | } |
4702 | ||
4703 | static int config_mgmt_dev(struct pci_dev *pdev) | |
4704 | { | |
4705 | struct adapter *adap = pci_get_drvdata(pdev); | |
4706 | struct net_device *netdev; | |
4707 | struct port_info *pi; | |
4708 | char name[IFNAMSIZ]; | |
4709 | int err; | |
4710 | ||
4711 | snprintf(name, IFNAMSIZ, "mgmtpf%d%d", adap->adap_idx, adap->pf); | |
038c35a8 GG |
4712 | netdev = alloc_netdev(sizeof(struct port_info), name, NET_NAME_UNKNOWN, |
4713 | dummy_setup); | |
e7b48a32 HS |
4714 | if (!netdev) |
4715 | return -ENOMEM; | |
4716 | ||
4717 | pi = netdev_priv(netdev); | |
4718 | pi->adapter = adap; | |
96fe11f2 | 4719 | pi->port_id = adap->pf % adap->params.nports; |
e7b48a32 HS |
4720 | SET_NETDEV_DEV(netdev, &pdev->dev); |
4721 | ||
4722 | adap->port[0] = netdev; | |
4723 | ||
4724 | err = register_netdev(adap->port[0]); | |
4725 | if (err) { | |
4726 | pr_info("Unable to register VF mgmt netdev %s\n", name); | |
4727 | free_netdev(adap->port[0]); | |
4728 | adap->port[0] = NULL; | |
4729 | return err; | |
4730 | } | |
4731 | return 0; | |
4732 | } | |
4733 | ||
b6244201 HS |
4734 | static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) |
4735 | { | |
7829451c | 4736 | struct adapter *adap = pci_get_drvdata(pdev); |
b6244201 HS |
4737 | int err = 0; |
4738 | int current_vfs = pci_num_vf(pdev); | |
4739 | u32 pcie_fw; | |
b6244201 | 4740 | |
7829451c | 4741 | pcie_fw = readl(adap->regs + PCIE_FW_A); |
b6244201 HS |
4742 | /* Check if cxgb4 is the MASTER and fw is initialized */ |
4743 | if (!(pcie_fw & PCIE_FW_INIT_F) || | |
4744 | !(pcie_fw & PCIE_FW_MASTER_VLD_F) || | |
4745 | PCIE_FW_MASTER_G(pcie_fw) != 4) { | |
4746 | dev_warn(&pdev->dev, | |
4747 | "cxgb4 driver needs to be MASTER to support SRIOV\n"); | |
4748 | return -EOPNOTSUPP; | |
4749 | } | |
4750 | ||
4751 | /* If any of the VF's is already assigned to Guest OS, then | |
4752 | * SRIOV for the same cannot be modified | |
4753 | */ | |
4754 | if (current_vfs && pci_vfs_assigned(pdev)) { | |
4755 | dev_err(&pdev->dev, | |
4756 | "Cannot modify SR-IOV while VFs are assigned\n"); | |
4757 | num_vfs = current_vfs; | |
4758 | return num_vfs; | |
4759 | } | |
4760 | ||
4761 | /* Disable SRIOV when zero is passed. | |
4762 | * One needs to disable SRIOV before modifying it, else | |
4763 | * stack throws the below warning: | |
4764 | * " 'n' VFs already enabled. Disable before enabling 'm' VFs." | |
4765 | */ | |
4766 | if (!num_vfs) { | |
4767 | pci_disable_sriov(pdev); | |
e7b48a32 | 4768 | if (adap->port[0]) { |
7829451c | 4769 | unregister_netdev(adap->port[0]); |
e7b48a32 HS |
4770 | adap->port[0] = NULL; |
4771 | } | |
661dbeb9 HS |
4772 | /* free VF resources */ |
4773 | kfree(adap->vfinfo); | |
4774 | adap->vfinfo = NULL; | |
4775 | adap->num_vfs = 0; | |
b6244201 HS |
4776 | return num_vfs; |
4777 | } | |
4778 | ||
4779 | if (num_vfs != current_vfs) { | |
4780 | err = pci_enable_sriov(pdev, num_vfs); | |
4781 | if (err) | |
4782 | return err; | |
7829451c | 4783 | |
661dbeb9 | 4784 | adap->num_vfs = num_vfs; |
e7b48a32 HS |
4785 | err = config_mgmt_dev(pdev); |
4786 | if (err) | |
4787 | return err; | |
b6244201 | 4788 | } |
661dbeb9 HS |
4789 | |
4790 | adap->vfinfo = kcalloc(adap->num_vfs, | |
4791 | sizeof(struct vf_info), GFP_KERNEL); | |
4792 | if (adap->vfinfo) | |
4793 | fill_vf_station_mac_addr(adap); | |
b6244201 HS |
4794 | return num_vfs; |
4795 | } | |
4796 | #endif | |
4797 | ||
1dd06ae8 | 4798 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
b8ff05a9 | 4799 | { |
22adfe0a | 4800 | int func, i, err, s_qpp, qpp, num_seg; |
b8ff05a9 | 4801 | struct port_info *pi; |
c8f44aff | 4802 | bool highdma = false; |
b8ff05a9 | 4803 | struct adapter *adapter = NULL; |
7829451c | 4804 | struct net_device *netdev; |
d6ce2628 | 4805 | void __iomem *regs; |
d86bd29e HS |
4806 | u32 whoami, pl_rev; |
4807 | enum chip_type chip; | |
7829451c | 4808 | static int adap_idx = 1; |
0a327889 | 4809 | #ifdef CONFIG_PCI_IOV |
96fe11f2 | 4810 | u32 v, port_vec; |
0a327889 | 4811 | #endif |
b8ff05a9 DM |
4812 | |
4813 | printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); | |
4814 | ||
4815 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
4816 | if (err) { | |
4817 | /* Just info, some other driver may have claimed the device. */ | |
4818 | dev_info(&pdev->dev, "cannot obtain PCI resources\n"); | |
4819 | return err; | |
4820 | } | |
4821 | ||
b8ff05a9 DM |
4822 | err = pci_enable_device(pdev); |
4823 | if (err) { | |
4824 | dev_err(&pdev->dev, "cannot enable PCI device\n"); | |
4825 | goto out_release_regions; | |
4826 | } | |
4827 | ||
d6ce2628 HS |
4828 | regs = pci_ioremap_bar(pdev, 0); |
4829 | if (!regs) { | |
4830 | dev_err(&pdev->dev, "cannot map device registers\n"); | |
4831 | err = -ENOMEM; | |
4832 | goto out_disable_device; | |
4833 | } | |
4834 | ||
8203b509 HS |
4835 | err = t4_wait_dev_ready(regs); |
4836 | if (err < 0) | |
4837 | goto out_unmap_bar0; | |
4838 | ||
d6ce2628 | 4839 | /* We control everything through one PF */ |
d86bd29e HS |
4840 | whoami = readl(regs + PL_WHOAMI_A); |
4841 | pl_rev = REV_G(readl(regs + PL_REV_A)); | |
4842 | chip = get_chip_type(pdev, pl_rev); | |
4843 | func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? | |
4844 | SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); | |
d6ce2628 | 4845 | if (func != ent->driver_data) { |
7829451c | 4846 | #ifndef CONFIG_PCI_IOV |
d6ce2628 | 4847 | iounmap(regs); |
7829451c | 4848 | #endif |
d6ce2628 HS |
4849 | pci_disable_device(pdev); |
4850 | pci_save_state(pdev); /* to restore SR-IOV later */ | |
4851 | goto sriov; | |
4852 | } | |
4853 | ||
b8ff05a9 | 4854 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
c8f44aff | 4855 | highdma = true; |
b8ff05a9 DM |
4856 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
4857 | if (err) { | |
4858 | dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " | |
4859 | "coherent allocations\n"); | |
d6ce2628 | 4860 | goto out_unmap_bar0; |
b8ff05a9 DM |
4861 | } |
4862 | } else { | |
4863 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
4864 | if (err) { | |
4865 | dev_err(&pdev->dev, "no usable DMA configuration\n"); | |
d6ce2628 | 4866 | goto out_unmap_bar0; |
b8ff05a9 DM |
4867 | } |
4868 | } | |
4869 | ||
4870 | pci_enable_pcie_error_reporting(pdev); | |
ef306b50 | 4871 | enable_pcie_relaxed_ordering(pdev); |
b8ff05a9 DM |
4872 | pci_set_master(pdev); |
4873 | pci_save_state(pdev); | |
4874 | ||
4875 | adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); | |
4876 | if (!adapter) { | |
4877 | err = -ENOMEM; | |
d6ce2628 | 4878 | goto out_unmap_bar0; |
b8ff05a9 | 4879 | } |
7829451c | 4880 | adap_idx++; |
b8ff05a9 | 4881 | |
29aaee65 AB |
4882 | adapter->workq = create_singlethread_workqueue("cxgb4"); |
4883 | if (!adapter->workq) { | |
4884 | err = -ENOMEM; | |
4885 | goto out_free_adapter; | |
4886 | } | |
4887 | ||
7f080c3f HS |
4888 | adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + |
4889 | (sizeof(struct mbox_cmd) * | |
4890 | T4_OS_LOG_MBOX_CMDS), | |
4891 | GFP_KERNEL); | |
4892 | if (!adapter->mbox_log) { | |
4893 | err = -ENOMEM; | |
4894 | goto out_free_adapter; | |
4895 | } | |
4896 | adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; | |
4897 | ||
144be3d9 GS |
4898 | /* PCI device has been enabled */ |
4899 | adapter->flags |= DEV_ENABLED; | |
4900 | ||
d6ce2628 | 4901 | adapter->regs = regs; |
b8ff05a9 DM |
4902 | adapter->pdev = pdev; |
4903 | adapter->pdev_dev = &pdev->dev; | |
0de72738 | 4904 | adapter->name = pci_name(pdev); |
3069ee9b | 4905 | adapter->mbox = func; |
b2612722 | 4906 | adapter->pf = func; |
ea1e76f7 | 4907 | adapter->msg_enable = DFLT_MSG_ENABLE; |
b8ff05a9 DM |
4908 | memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); |
4909 | ||
4910 | spin_lock_init(&adapter->stats_lock); | |
4911 | spin_lock_init(&adapter->tid_release_lock); | |
e327c225 | 4912 | spin_lock_init(&adapter->win0_lock); |
4055ae5e HS |
4913 | spin_lock_init(&adapter->mbox_lock); |
4914 | ||
4915 | INIT_LIST_HEAD(&adapter->mlist.list); | |
b8ff05a9 DM |
4916 | |
4917 | INIT_WORK(&adapter->tid_release_task, process_tid_release_list); | |
881806bc VP |
4918 | INIT_WORK(&adapter->db_full_task, process_db_full); |
4919 | INIT_WORK(&adapter->db_drop_task, process_db_drop); | |
b8ff05a9 DM |
4920 | |
4921 | err = t4_prep_adapter(adapter); | |
4922 | if (err) | |
d6ce2628 HS |
4923 | goto out_free_adapter; |
4924 | ||
22adfe0a | 4925 | |
d14807dd | 4926 | if (!is_t4(adapter->params.chip)) { |
f612b815 HS |
4927 | s_qpp = (QUEUESPERPAGEPF0_S + |
4928 | (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * | |
b2612722 | 4929 | adapter->pf); |
f612b815 HS |
4930 | qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, |
4931 | SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); | |
22adfe0a SR |
4932 | num_seg = PAGE_SIZE / SEGMENT_SIZE; |
4933 | ||
4934 | /* Each segment size is 128B. Write coalescing is enabled only | |
4935 | * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the | |
4936 | * queue is less no of segments that can be accommodated in | |
4937 | * a page size. | |
4938 | */ | |
4939 | if (qpp > num_seg) { | |
4940 | dev_err(&pdev->dev, | |
4941 | "Incorrect number of egress queues per page\n"); | |
4942 | err = -EINVAL; | |
d6ce2628 | 4943 | goto out_free_adapter; |
22adfe0a SR |
4944 | } |
4945 | adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), | |
4946 | pci_resource_len(pdev, 2)); | |
4947 | if (!adapter->bar2) { | |
4948 | dev_err(&pdev->dev, "cannot map device bar2 region\n"); | |
4949 | err = -ENOMEM; | |
d6ce2628 | 4950 | goto out_free_adapter; |
22adfe0a SR |
4951 | } |
4952 | } | |
4953 | ||
636f9d37 | 4954 | setup_memwin(adapter); |
b8ff05a9 | 4955 | err = adap_init0(adapter); |
5b377d11 HS |
4956 | #ifdef CONFIG_DEBUG_FS |
4957 | bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); | |
4958 | #endif | |
636f9d37 | 4959 | setup_memwin_rdma(adapter); |
b8ff05a9 DM |
4960 | if (err) |
4961 | goto out_unmap_bar; | |
4962 | ||
2a485cf7 HS |
4963 | /* configure SGE_STAT_CFG_A to read WC stats */ |
4964 | if (!is_t4(adapter->params.chip)) | |
676d6a75 HS |
4965 | t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | |
4966 | (is_t5(adapter->params.chip) ? STATMODE_V(0) : | |
4967 | T6_STATMODE_V(0))); | |
2a485cf7 | 4968 | |
b8ff05a9 | 4969 | for_each_port(adapter, i) { |
b8ff05a9 DM |
4970 | netdev = alloc_etherdev_mq(sizeof(struct port_info), |
4971 | MAX_ETH_QSETS); | |
4972 | if (!netdev) { | |
4973 | err = -ENOMEM; | |
4974 | goto out_free_dev; | |
4975 | } | |
4976 | ||
4977 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
4978 | ||
4979 | adapter->port[i] = netdev; | |
4980 | pi = netdev_priv(netdev); | |
4981 | pi->adapter = adapter; | |
4982 | pi->xact_addr_filt = -1; | |
b8ff05a9 | 4983 | pi->port_id = i; |
b8ff05a9 DM |
4984 | netdev->irq = pdev->irq; |
4985 | ||
2ed28baa MM |
4986 | netdev->hw_features = NETIF_F_SG | TSO_FLAGS | |
4987 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
4988 | NETIF_F_RXCSUM | NETIF_F_RXHASH | | |
d8931847 RL |
4989 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | |
4990 | NETIF_F_HW_TC; | |
c8f44aff MM |
4991 | if (highdma) |
4992 | netdev->hw_features |= NETIF_F_HIGHDMA; | |
4993 | netdev->features |= netdev->hw_features; | |
b8ff05a9 DM |
4994 | netdev->vlan_features = netdev->features & VLAN_FEAT; |
4995 | ||
01789349 JP |
4996 | netdev->priv_flags |= IFF_UNICAST_FLT; |
4997 | ||
d894be57 JW |
4998 | /* MTU range: 81 - 9600 */ |
4999 | netdev->min_mtu = 81; | |
5000 | netdev->max_mtu = MAX_MTU; | |
5001 | ||
b8ff05a9 | 5002 | netdev->netdev_ops = &cxgb4_netdev_ops; |
688848b1 AB |
5003 | #ifdef CONFIG_CHELSIO_T4_DCB |
5004 | netdev->dcbnl_ops = &cxgb4_dcb_ops; | |
5005 | cxgb4_dcb_state_init(netdev); | |
5006 | #endif | |
812034f1 | 5007 | cxgb4_set_ethtool_ops(netdev); |
b8ff05a9 DM |
5008 | } |
5009 | ||
5010 | pci_set_drvdata(pdev, adapter); | |
5011 | ||
5012 | if (adapter->flags & FW_OK) { | |
060e0c75 | 5013 | err = t4_port_init(adapter, func, func, 0); |
b8ff05a9 DM |
5014 | if (err) |
5015 | goto out_free_dev; | |
098ef6c2 HS |
5016 | } else if (adapter->params.nports == 1) { |
5017 | /* If we don't have a connection to the firmware -- possibly | |
5018 | * because of an error -- grab the raw VPD parameters so we | |
5019 | * can set the proper MAC Address on the debug network | |
5020 | * interface that we've created. | |
5021 | */ | |
5022 | u8 hw_addr[ETH_ALEN]; | |
5023 | u8 *na = adapter->params.vpd.na; | |
5024 | ||
5025 | err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); | |
5026 | if (!err) { | |
5027 | for (i = 0; i < ETH_ALEN; i++) | |
5028 | hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + | |
5029 | hex2val(na[2 * i + 1])); | |
5030 | t4_set_hw_addr(adapter, 0, hw_addr); | |
5031 | } | |
b8ff05a9 DM |
5032 | } |
5033 | ||
098ef6c2 | 5034 | /* Configure queues and allocate tables now, they can be needed as |
b8ff05a9 DM |
5035 | * soon as the first register_netdev completes. |
5036 | */ | |
5037 | cfg_queues(adapter); | |
5038 | ||
5be9ed8d | 5039 | adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); |
b8ff05a9 DM |
5040 | if (!adapter->l2t) { |
5041 | /* We tolerate a lack of L2T, giving up some functionality */ | |
5042 | dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); | |
5043 | adapter->params.offload = 0; | |
5044 | } | |
5045 | ||
b5a02f50 | 5046 | #if IS_ENABLED(CONFIG_IPV6) |
eb72f74f HS |
5047 | if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) && |
5048 | (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { | |
5049 | /* CLIP functionality is not present in hardware, | |
5050 | * hence disable all offload features | |
b5a02f50 AB |
5051 | */ |
5052 | dev_warn(&pdev->dev, | |
eb72f74f | 5053 | "CLIP not enabled in hardware, continuing\n"); |
b5a02f50 | 5054 | adapter->params.offload = 0; |
eb72f74f HS |
5055 | } else { |
5056 | adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, | |
5057 | adapter->clipt_end); | |
5058 | if (!adapter->clipt) { | |
5059 | /* We tolerate a lack of clip_table, giving up | |
5060 | * some functionality | |
5061 | */ | |
5062 | dev_warn(&pdev->dev, | |
5063 | "could not allocate Clip table, continuing\n"); | |
5064 | adapter->params.offload = 0; | |
5065 | } | |
b5a02f50 AB |
5066 | } |
5067 | #endif | |
b72a32da RL |
5068 | |
5069 | for_each_port(adapter, i) { | |
5070 | pi = adap2pinfo(adapter, i); | |
5071 | pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls); | |
5072 | if (!pi->sched_tbl) | |
5073 | dev_warn(&pdev->dev, | |
5074 | "could not activate scheduling on port %d\n", | |
5075 | i); | |
5076 | } | |
5077 | ||
578b46b9 | 5078 | if (tid_init(&adapter->tids) < 0) { |
b8ff05a9 DM |
5079 | dev_warn(&pdev->dev, "could not allocate TID table, " |
5080 | "continuing\n"); | |
5081 | adapter->params.offload = 0; | |
d8931847 | 5082 | } else { |
45da1ca2 | 5083 | adapter->tc_u32 = cxgb4_init_tc_u32(adapter); |
d8931847 RL |
5084 | if (!adapter->tc_u32) |
5085 | dev_warn(&pdev->dev, | |
5086 | "could not offload tc u32, continuing\n"); | |
b8ff05a9 DM |
5087 | } |
5088 | ||
9a1bb9f6 HS |
5089 | if (is_offload(adapter)) { |
5090 | if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { | |
5091 | u32 hash_base, hash_reg; | |
5092 | ||
5093 | if (chip <= CHELSIO_T5) { | |
5094 | hash_reg = LE_DB_TID_HASHBASE_A; | |
5095 | hash_base = t4_read_reg(adapter, hash_reg); | |
5096 | adapter->tids.hash_base = hash_base / 4; | |
5097 | } else { | |
5098 | hash_reg = T6_LE_DB_HASH_TID_BASE_A; | |
5099 | hash_base = t4_read_reg(adapter, hash_reg); | |
5100 | adapter->tids.hash_base = hash_base; | |
5101 | } | |
5102 | } | |
5103 | } | |
5104 | ||
f7cabcdd DM |
5105 | /* See what interrupts we'll be using */ |
5106 | if (msi > 1 && enable_msix(adapter) == 0) | |
5107 | adapter->flags |= USING_MSIX; | |
94cdb8bb | 5108 | else if (msi > 0 && pci_enable_msi(pdev) == 0) { |
f7cabcdd | 5109 | adapter->flags |= USING_MSI; |
94cdb8bb HS |
5110 | if (msi > 1) |
5111 | free_msix_info(adapter); | |
5112 | } | |
f7cabcdd | 5113 | |
547fd272 HS |
5114 | /* check for PCI Express bandwidth capabiltites */ |
5115 | cxgb4_check_pcie_caps(adapter); | |
5116 | ||
671b0060 DM |
5117 | err = init_rss(adapter); |
5118 | if (err) | |
5119 | goto out_free_dev; | |
5120 | ||
b8ff05a9 DM |
5121 | /* |
5122 | * The card is now ready to go. If any errors occur during device | |
5123 | * registration we do not fail the whole card but rather proceed only | |
5124 | * with the ports we manage to register successfully. However we must | |
5125 | * register at least one net device. | |
5126 | */ | |
5127 | for_each_port(adapter, i) { | |
a57cabe0 | 5128 | pi = adap2pinfo(adapter, i); |
d2a007ab | 5129 | adapter->port[i]->dev_port = pi->lport; |
a57cabe0 DM |
5130 | netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); |
5131 | netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); | |
5132 | ||
b1a73af9 SM |
5133 | netif_carrier_off(adapter->port[i]); |
5134 | ||
b8ff05a9 DM |
5135 | err = register_netdev(adapter->port[i]); |
5136 | if (err) | |
b1a3c2b6 | 5137 | break; |
b1a3c2b6 DM |
5138 | adapter->chan_map[pi->tx_chan] = i; |
5139 | print_port_info(adapter->port[i]); | |
b8ff05a9 | 5140 | } |
b1a3c2b6 | 5141 | if (i == 0) { |
b8ff05a9 DM |
5142 | dev_err(&pdev->dev, "could not register any net devices\n"); |
5143 | goto out_free_dev; | |
5144 | } | |
b1a3c2b6 DM |
5145 | if (err) { |
5146 | dev_warn(&pdev->dev, "only %d net devices registered\n", i); | |
5147 | err = 0; | |
6403eab1 | 5148 | } |
b8ff05a9 DM |
5149 | |
5150 | if (cxgb4_debugfs_root) { | |
5151 | adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), | |
5152 | cxgb4_debugfs_root); | |
5153 | setup_debugfs(adapter); | |
5154 | } | |
5155 | ||
6482aa7c DLR |
5156 | /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ |
5157 | pdev->needs_freset = 1; | |
5158 | ||
0fbc81b3 HS |
5159 | if (is_uld(adapter)) { |
5160 | mutex_lock(&uld_mutex); | |
5161 | list_add_tail(&adapter->list_node, &adapter_list); | |
5162 | mutex_unlock(&uld_mutex); | |
5163 | } | |
b8ff05a9 | 5164 | |
9c33e420 AG |
5165 | if (!is_t4(adapter->params.chip)) |
5166 | cxgb4_ptp_init(adapter); | |
5167 | ||
0de72738 | 5168 | print_adapter_info(adapter); |
0fbc81b3 | 5169 | setup_fw_sge_queues(adapter); |
7829451c | 5170 | return 0; |
0de72738 | 5171 | |
8e1e6059 | 5172 | sriov: |
b8ff05a9 | 5173 | #ifdef CONFIG_PCI_IOV |
7829451c HS |
5174 | adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); |
5175 | if (!adapter) { | |
5176 | err = -ENOMEM; | |
5177 | goto free_pci_region; | |
5178 | } | |
5179 | ||
7829451c HS |
5180 | adapter->pdev = pdev; |
5181 | adapter->pdev_dev = &pdev->dev; | |
5182 | adapter->name = pci_name(pdev); | |
5183 | adapter->mbox = func; | |
5184 | adapter->pf = func; | |
5185 | adapter->regs = regs; | |
e7b48a32 | 5186 | adapter->adap_idx = adap_idx; |
7829451c HS |
5187 | adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + |
5188 | (sizeof(struct mbox_cmd) * | |
5189 | T4_OS_LOG_MBOX_CMDS), | |
5190 | GFP_KERNEL); | |
5191 | if (!adapter->mbox_log) { | |
5192 | err = -ENOMEM; | |
e7b48a32 | 5193 | goto free_adapter; |
7829451c | 5194 | } |
038c35a8 GG |
5195 | spin_lock_init(&adapter->mbox_lock); |
5196 | INIT_LIST_HEAD(&adapter->mlist.list); | |
96fe11f2 GG |
5197 | |
5198 | v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | | |
5199 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); | |
5200 | err = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 1, | |
5201 | &v, &port_vec); | |
5202 | if (err < 0) { | |
5203 | dev_err(adapter->pdev_dev, "Could not fetch port params\n"); | |
d0417849 | 5204 | goto free_mbox_log; |
96fe11f2 GG |
5205 | } |
5206 | ||
5207 | adapter->params.nports = hweight32(port_vec); | |
7829451c | 5208 | pci_set_drvdata(pdev, adapter); |
7829451c HS |
5209 | return 0; |
5210 | ||
d0417849 GG |
5211 | free_mbox_log: |
5212 | kfree(adapter->mbox_log); | |
7829451c HS |
5213 | free_adapter: |
5214 | kfree(adapter); | |
5215 | free_pci_region: | |
5216 | iounmap(regs); | |
5217 | pci_disable_sriov(pdev); | |
5218 | pci_release_regions(pdev); | |
5219 | return err; | |
5220 | #else | |
b8ff05a9 | 5221 | return 0; |
7829451c | 5222 | #endif |
b8ff05a9 DM |
5223 | |
5224 | out_free_dev: | |
06546391 | 5225 | free_some_resources(adapter); |
94cdb8bb HS |
5226 | if (adapter->flags & USING_MSIX) |
5227 | free_msix_info(adapter); | |
0fbc81b3 HS |
5228 | if (adapter->num_uld || adapter->num_ofld_uld) |
5229 | t4_uld_mem_free(adapter); | |
b8ff05a9 | 5230 | out_unmap_bar: |
d14807dd | 5231 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5232 | iounmap(adapter->bar2); |
b8ff05a9 | 5233 | out_free_adapter: |
29aaee65 AB |
5234 | if (adapter->workq) |
5235 | destroy_workqueue(adapter->workq); | |
5236 | ||
7f080c3f | 5237 | kfree(adapter->mbox_log); |
b8ff05a9 | 5238 | kfree(adapter); |
d6ce2628 HS |
5239 | out_unmap_bar0: |
5240 | iounmap(regs); | |
b8ff05a9 DM |
5241 | out_disable_device: |
5242 | pci_disable_pcie_error_reporting(pdev); | |
5243 | pci_disable_device(pdev); | |
5244 | out_release_regions: | |
5245 | pci_release_regions(pdev); | |
b8ff05a9 DM |
5246 | return err; |
5247 | } | |
5248 | ||
91744948 | 5249 | static void remove_one(struct pci_dev *pdev) |
b8ff05a9 DM |
5250 | { |
5251 | struct adapter *adapter = pci_get_drvdata(pdev); | |
5252 | ||
7829451c HS |
5253 | if (!adapter) { |
5254 | pci_release_regions(pdev); | |
5255 | return; | |
5256 | } | |
636f9d37 | 5257 | |
7829451c | 5258 | if (adapter->pf == 4) { |
b8ff05a9 DM |
5259 | int i; |
5260 | ||
29aaee65 AB |
5261 | /* Tear down per-adapter Work Queue first since it can contain |
5262 | * references to our adapter data structure. | |
5263 | */ | |
5264 | destroy_workqueue(adapter->workq); | |
5265 | ||
6a146f3a | 5266 | if (is_uld(adapter)) { |
b8ff05a9 | 5267 | detach_ulds(adapter); |
6a146f3a GP |
5268 | t4_uld_clean_up(adapter); |
5269 | } | |
b8ff05a9 | 5270 | |
b37987e8 HS |
5271 | disable_interrupts(adapter); |
5272 | ||
b8ff05a9 | 5273 | for_each_port(adapter, i) |
8f3a7676 | 5274 | if (adapter->port[i]->reg_state == NETREG_REGISTERED) |
b8ff05a9 DM |
5275 | unregister_netdev(adapter->port[i]); |
5276 | ||
9f16dc2e | 5277 | debugfs_remove_recursive(adapter->debugfs_root); |
b8ff05a9 | 5278 | |
9c33e420 AG |
5279 | if (!is_t4(adapter->params.chip)) |
5280 | cxgb4_ptp_stop(adapter); | |
5281 | ||
f2b7e78d VP |
5282 | /* If we allocated filters, free up state associated with any |
5283 | * valid filters ... | |
5284 | */ | |
578b46b9 | 5285 | clear_all_filters(adapter); |
f2b7e78d | 5286 | |
aaefae9b DM |
5287 | if (adapter->flags & FULL_INIT_DONE) |
5288 | cxgb_down(adapter); | |
b8ff05a9 | 5289 | |
94cdb8bb HS |
5290 | if (adapter->flags & USING_MSIX) |
5291 | free_msix_info(adapter); | |
0fbc81b3 HS |
5292 | if (adapter->num_uld || adapter->num_ofld_uld) |
5293 | t4_uld_mem_free(adapter); | |
06546391 | 5294 | free_some_resources(adapter); |
b5a02f50 AB |
5295 | #if IS_ENABLED(CONFIG_IPV6) |
5296 | t4_cleanup_clip_tbl(adapter); | |
5297 | #endif | |
b8ff05a9 | 5298 | iounmap(adapter->regs); |
d14807dd | 5299 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5300 | iounmap(adapter->bar2); |
b8ff05a9 | 5301 | pci_disable_pcie_error_reporting(pdev); |
144be3d9 GS |
5302 | if ((adapter->flags & DEV_ENABLED)) { |
5303 | pci_disable_device(pdev); | |
5304 | adapter->flags &= ~DEV_ENABLED; | |
5305 | } | |
b8ff05a9 | 5306 | pci_release_regions(pdev); |
7f080c3f | 5307 | kfree(adapter->mbox_log); |
ee9a33b2 | 5308 | synchronize_rcu(); |
8b662fe7 | 5309 | kfree(adapter); |
7829451c HS |
5310 | } |
5311 | #ifdef CONFIG_PCI_IOV | |
5312 | else { | |
e7b48a32 | 5313 | if (adapter->port[0]) |
7829451c | 5314 | unregister_netdev(adapter->port[0]); |
7829451c | 5315 | iounmap(adapter->regs); |
661dbeb9 | 5316 | kfree(adapter->vfinfo); |
d0417849 | 5317 | kfree(adapter->mbox_log); |
7829451c HS |
5318 | kfree(adapter); |
5319 | pci_disable_sriov(pdev); | |
b8ff05a9 | 5320 | pci_release_regions(pdev); |
7829451c HS |
5321 | } |
5322 | #endif | |
b8ff05a9 DM |
5323 | } |
5324 | ||
0fbc81b3 HS |
5325 | /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt |
5326 | * delivery. This is essentially a stripped down version of the PCI remove() | |
5327 | * function where we do the minimal amount of work necessary to shutdown any | |
5328 | * further activity. | |
5329 | */ | |
5330 | static void shutdown_one(struct pci_dev *pdev) | |
5331 | { | |
5332 | struct adapter *adapter = pci_get_drvdata(pdev); | |
5333 | ||
5334 | /* As with remove_one() above (see extended comment), we only want do | |
5335 | * do cleanup on PCI Devices which went all the way through init_one() | |
5336 | * ... | |
5337 | */ | |
5338 | if (!adapter) { | |
5339 | pci_release_regions(pdev); | |
5340 | return; | |
5341 | } | |
5342 | ||
5343 | if (adapter->pf == 4) { | |
5344 | int i; | |
5345 | ||
5346 | for_each_port(adapter, i) | |
5347 | if (adapter->port[i]->reg_state == NETREG_REGISTERED) | |
5348 | cxgb_close(adapter->port[i]); | |
5349 | ||
6a146f3a GP |
5350 | if (is_uld(adapter)) { |
5351 | detach_ulds(adapter); | |
5352 | t4_uld_clean_up(adapter); | |
5353 | } | |
5354 | ||
0fbc81b3 HS |
5355 | disable_interrupts(adapter); |
5356 | disable_msi(adapter); | |
5357 | ||
5358 | t4_sge_stop(adapter); | |
5359 | if (adapter->flags & FW_OK) | |
5360 | t4_fw_bye(adapter, adapter->mbox); | |
5361 | } | |
5362 | #ifdef CONFIG_PCI_IOV | |
5363 | else { | |
5364 | if (adapter->port[0]) | |
5365 | unregister_netdev(adapter->port[0]); | |
5366 | iounmap(adapter->regs); | |
5367 | kfree(adapter->vfinfo); | |
d0417849 | 5368 | kfree(adapter->mbox_log); |
0fbc81b3 HS |
5369 | kfree(adapter); |
5370 | pci_disable_sriov(pdev); | |
5371 | pci_release_regions(pdev); | |
5372 | } | |
5373 | #endif | |
5374 | } | |
5375 | ||
b8ff05a9 DM |
5376 | static struct pci_driver cxgb4_driver = { |
5377 | .name = KBUILD_MODNAME, | |
5378 | .id_table = cxgb4_pci_tbl, | |
5379 | .probe = init_one, | |
91744948 | 5380 | .remove = remove_one, |
0fbc81b3 | 5381 | .shutdown = shutdown_one, |
b6244201 HS |
5382 | #ifdef CONFIG_PCI_IOV |
5383 | .sriov_configure = cxgb4_iov_configure, | |
5384 | #endif | |
204dc3c0 | 5385 | .err_handler = &cxgb4_eeh, |
b8ff05a9 DM |
5386 | }; |
5387 | ||
5388 | static int __init cxgb4_init_module(void) | |
5389 | { | |
5390 | int ret; | |
5391 | ||
5392 | /* Debugfs support is optional, just warn if this fails */ | |
5393 | cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); | |
5394 | if (!cxgb4_debugfs_root) | |
428ac43f | 5395 | pr_warn("could not create debugfs entry, continuing\n"); |
b8ff05a9 DM |
5396 | |
5397 | ret = pci_register_driver(&cxgb4_driver); | |
29aaee65 | 5398 | if (ret < 0) |
b8ff05a9 | 5399 | debugfs_remove(cxgb4_debugfs_root); |
01bcca68 | 5400 | |
1bb60376 | 5401 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
5402 | if (!inet6addr_registered) { |
5403 | register_inet6addr_notifier(&cxgb4_inet6addr_notifier); | |
5404 | inet6addr_registered = true; | |
5405 | } | |
1bb60376 | 5406 | #endif |
01bcca68 | 5407 | |
b8ff05a9 DM |
5408 | return ret; |
5409 | } | |
5410 | ||
5411 | static void __exit cxgb4_cleanup_module(void) | |
5412 | { | |
1bb60376 | 5413 | #if IS_ENABLED(CONFIG_IPV6) |
1793c798 | 5414 | if (inet6addr_registered) { |
b5a02f50 AB |
5415 | unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); |
5416 | inet6addr_registered = false; | |
5417 | } | |
1bb60376 | 5418 | #endif |
b8ff05a9 DM |
5419 | pci_unregister_driver(&cxgb4_driver); |
5420 | debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ | |
5421 | } | |
5422 | ||
5423 | module_init(cxgb4_init_module); | |
5424 | module_exit(cxgb4_cleanup_module); |