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cxgb4: Setup FW queues before registering netdev
[thirdparty/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
b72a32da 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
1ef8019b 64#include <net/bonding.h>
b5a02f50 65#include <net/addrconf.h>
7c0f6ba6 66#include <linux/uaccess.h>
c5a8c0f3 67#include <linux/crash_dump.h>
846eac3f 68#include <net/udp_tunnel.h>
b8ff05a9
DM		 69
70#include "cxgb4.h"
d57fd6ca 71#include "cxgb4_filter.h"
b8ff05a9 72#include "t4_regs.h"
f612b815 73#include "t4_values.h"
b8ff05a9
DM		 74#include "t4_msg.h"
75#include "t4fw_api.h"
cd6c2f12 76#include "t4fw_version.h"
688848b1 77#include "cxgb4_dcb.h"
c68644ef 78#include "srq.h"
fd88b31a 79#include "cxgb4_debugfs.h"
b5a02f50 80#include "clip_tbl.h"
b8ff05a9 81#include "l2t.h"
3bdb376e 82#include "smt.h"
b72a32da 83#include "sched.h"
d8931847 84#include "cxgb4_tc_u32.h"
6a345b3d 85#include "cxgb4_tc_flower.h"
a4569504 86#include "cxgb4_ptp.h"
ad75b7d3 87#include "cxgb4_cudbg.h"
b8ff05a9 88
812034f1
HS		 89char cxgb4_driver_name[] = KBUILD_MODNAME;
90
01bcca68
VP		 91#ifdef DRV_VERSION
92#undef DRV_VERSION
93#endif
3a7f8554 94#define DRV_VERSION "2.0.0-ko"
812034f1 95const char cxgb4_driver_version[] = DRV_VERSION;
52a5f846 96#define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
b8ff05a9 97
b8ff05a9
DM		 98#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
99 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
100 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
101
3fedeab1
HS		 102/* Macros needed to support the PCI Device ID Table ...
103 */
104#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
768ffc66 105 static const struct pci_device_id cxgb4_pci_tbl[] = {
baf50868
GG		 106#define CXGB4_UNIFIED_PF 0x4
107
108#define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
b8ff05a9 109
3fedeab1
HS		 110/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
111 * called for both.
112 */
113#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
114
115#define CH_PCI_ID_TABLE_ENTRY(devid) \
baf50868 116 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
3fedeab1
HS		 117
118#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
119 { 0, } \
120 }
121
122#include "t4_pci_id_tbl.h"
b8ff05a9 123
16e47624 124#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 125#define FW5_FNAME "cxgb4/t5fw.bin"
3ccc6cf7 126#define FW6_FNAME "cxgb4/t6fw.bin"
16e47624 127#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 128#define FW5_CFNAME "cxgb4/t5-config.txt"
3ccc6cf7 129#define FW6_CFNAME "cxgb4/t6-config.txt"
01b69614
HS		 130#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
131#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
132#define PHY_AQ1202_DEVICEID 0x4409
133#define PHY_BCM84834_DEVICEID 0x4486
b8ff05a9
DM		 134
135MODULE_DESCRIPTION(DRV_DESC);
136MODULE_AUTHOR("Chelsio Communications");
137MODULE_LICENSE("Dual BSD/GPL");
138MODULE_VERSION(DRV_VERSION);
139MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 140MODULE_FIRMWARE(FW4_FNAME);
0a57a536 141MODULE_FIRMWARE(FW5_FNAME);
52a5f846 142MODULE_FIRMWARE(FW6_FNAME);
b8ff05a9 143
b8ff05a9
DM		 144/*
145 * The driver uses the best interrupt scheme available on a platform in the
146 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
147 * of these schemes the driver may consider as follows:
148 *
149 * msi = 2: choose from among all three options
150 * msi = 1: only consider MSI and INTx interrupts
151 * msi = 0: force INTx interrupts
152 */
153static int msi = 2;
154
155module_param(msi, int, 0644);
156MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
157
636f9d37
VP		 158/*
159 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
160 * offset by 2 bytes in order to have the IP headers line up on 4-byte
161 * boundaries. This is a requirement for many architectures which will throw
162 * a machine check fault if an attempt is made to access one of the 4-byte IP
163 * header fields on a non-4-byte boundary. And it's a major performance issue
164 * even on some architectures which allow it like some implementations of the
165 * x86 ISA. However, some architectures don't mind this and for some very
166 * edge-case performance sensitive applications (like forwarding large volumes
167 * of small packets), setting this DMA offset to 0 will decrease the number of
168 * PCI-E Bus transfers enough to measurably affect performance.
169 */
170static int rx_dma_offset = 2;
171
688848b1
AB		 172/* TX Queue select used to determine what algorithm to use for selecting TX
173 * queue. Select between the kernel provided function (select_queue=0) or user
174 * cxgb_select_queue function (select_queue=1)
175 *
176 * Default: select_queue=0
177 */
178static int select_queue;
179module_param(select_queue, int, 0644);
180MODULE_PARM_DESC(select_queue,
181 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
182
b8ff05a9
DM		 183static struct dentry *cxgb4_debugfs_root;
184
94cdb8bb
HS		 185LIST_HEAD(adapter_list);
186DEFINE_MUTEX(uld_mutex);
b8ff05a9
DM		 187
188static void link_report(struct net_device *dev)
189{
190 if (!netif_carrier_ok(dev))
191 netdev_info(dev, "link down\n");
192 else {
193 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
194
85412255 195 const char *s;
b8ff05a9
DM		 196 const struct port_info *p = netdev_priv(dev);
197
198 switch (p->link_cfg.speed) {
5e78f7fd
GG		 199 case 100:
200 s = "100Mbps";
b8ff05a9 201 break;
e8b39015 202 case 1000:
5e78f7fd 203 s = "1Gbps";
b8ff05a9 204 break;
5e78f7fd
GG		 205 case 10000:
206 s = "10Gbps";
207 break;
208 case 25000:
209 s = "25Gbps";
b8ff05a9 210 break;
e8b39015 211 case 40000:
72aca4bf
KS		 212 s = "40Gbps";
213 break;
7cbe543c
GG		 214 case 50000:
215 s = "50Gbps";
216 break;
5e78f7fd
GG		 217 case 100000:
218 s = "100Gbps";
219 break;
85412255
HS		 220 default:
221 pr_info("%s: unsupported speed: %d\n",
222 dev->name, p->link_cfg.speed);
223 return;
b8ff05a9
DM		 224 }
225
226 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
227 fc[p->link_cfg.fc]);
228 }
229}
230
688848b1
AB		 231#ifdef CONFIG_CHELSIO_T4_DCB
232/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
233static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
234{
235 struct port_info *pi = netdev_priv(dev);
236 struct adapter *adap = pi->adapter;
237 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
238 int i;
239
240 /* We use a simple mapping of Port TX Queue Index to DCB
241 * Priority when we're enabling DCB.
242 */
243 for (i = 0; i < pi->nqsets; i++, txq++) {
244 u32 name, value;
245 int err;
246
5167865a
HS		 247 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
248 FW_PARAMS_PARAM_X_V(
249 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
250 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
688848b1
AB		 251 value = enable ? i : 0xffffffff;
252
253 /* Since we can be called while atomic (from "interrupt
254 * level") we need to issue the Set Parameters Commannd
255 * without sleeping (timeout < 0).
256 */
b2612722 257 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
01b69614
HS		 258 &name, &value,
259 -FW_CMD_MAX_TIMEOUT);
688848b1
AB		 260
261 if (err)
262 dev_err(adap->pdev_dev,
263 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
264 enable ? "set" : "unset", pi->port_id, i, -err);
10b00466
AB		 265 else
266 txq->dcb_prio = value;
688848b1
AB		 267 }
268}
688848b1 269
50935857 270static int cxgb4_dcb_enabled(const struct net_device *dev)
218d48e7 271{
218d48e7
HS		 272 struct port_info *pi = netdev_priv(dev);
273
274 if (!pi->dcb.enabled)
275 return 0;
276
277 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
278 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
218d48e7 279}
7c70c4f8 280#endif /* CONFIG_CHELSIO_T4_DCB */
218d48e7 281
b8ff05a9
DM		 282void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
283{
284 struct net_device *dev = adapter->port[port_id];
285
286 /* Skip changes from disabled ports. */
287 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
288 if (link_stat)
289 netif_carrier_on(dev);
688848b1
AB		 290 else {
291#ifdef CONFIG_CHELSIO_T4_DCB
218d48e7 292 if (cxgb4_dcb_enabled(dev)) {
ba581f77 293 cxgb4_dcb_reset(dev);
218d48e7
HS		 294 dcb_tx_queue_prio_enable(dev, false);
295 }
688848b1 296#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 297 netif_carrier_off(dev);
688848b1 298 }
b8ff05a9
DM		 299
300 link_report(dev);
301 }
302}
303
304void t4_os_portmod_changed(const struct adapter *adap, int port_id)
305{
306 static const char *mod_str[] = {
a0881cab 307 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 308 };
309
310 const struct net_device *dev = adap->port[port_id];
311 const struct port_info *pi = netdev_priv(dev);
312
313 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
314 netdev_info(dev, "port module unplugged\n");
a0881cab 315 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9 316 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
be81a2de
HS		 317 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
318 netdev_info(dev, "%s: unsupported port module inserted\n",
319 dev->name);
320 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
321 netdev_info(dev, "%s: unknown port module inserted\n",
322 dev->name);
323 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
324 netdev_info(dev, "%s: transceiver module error\n", dev->name);
325 else
326 netdev_info(dev, "%s: unknown module type %d inserted\n",
327 dev->name, pi->mod_type);
b8ff05a9
DM		 328}
329
fc08a01a
HS		 330int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
331module_param(dbfifo_int_thresh, int, 0644);
332MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
333
b8ff05a9 334/*
fc08a01a 335 * usecs to sleep while draining the dbfifo
b8ff05a9 336 */
fc08a01a
HS		 337static int dbfifo_drain_delay = 1000;
338module_param(dbfifo_drain_delay, int, 0644);
339MODULE_PARM_DESC(dbfifo_drain_delay,
340 "usecs to sleep while draining the dbfifo");
341
342static inline int cxgb4_set_addr_hash(struct port_info *pi)
b8ff05a9 343{
fc08a01a
HS		 344 struct adapter *adap = pi->adapter;
345 u64 vec = 0;
346 bool ucast = false;
347 struct hash_mac_addr *entry;
348
349 /* Calculate the hash vector for the updated list and program it */
350 list_for_each_entry(entry, &adap->mac_hlist, list) {
351 ucast |= is_unicast_ether_addr(entry->addr);
352 vec |= (1ULL << hash_mac_addr(entry->addr));
353 }
354 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
355 vec, false);
356}
357
358static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
359{
360 struct port_info *pi = netdev_priv(netdev);
361 struct adapter *adap = pi->adapter;
362 int ret;
b8ff05a9
DM		 363 u64 mhash = 0;
364 u64 uhash = 0;
fc08a01a
HS		 365 bool free = false;
366 bool ucast = is_unicast_ether_addr(mac_addr);
367 const u8 *maclist[1] = {mac_addr};
368 struct hash_mac_addr *new_entry;
369
370 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
371 NULL, ucast ? &uhash : &mhash, false);
372 if (ret < 0)
373 goto out;
374 /* if hash != 0, then add the addr to hash addr list
375 * so on the end we will calculate the hash for the
376 * list and program it
377 */
378 if (uhash || mhash) {
379 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
380 if (!new_entry)
381 return -ENOMEM;
382 ether_addr_copy(new_entry->addr, mac_addr);
383 list_add_tail(&new_entry->list, &adap->mac_hlist);
384 ret = cxgb4_set_addr_hash(pi);
b8ff05a9 385 }
fc08a01a
HS		 386out:
387 return ret < 0 ? ret : 0;
388}
b8ff05a9 389
fc08a01a
HS		 390static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
391{
392 struct port_info *pi = netdev_priv(netdev);
393 struct adapter *adap = pi->adapter;
394 int ret;
395 const u8 *maclist[1] = {mac_addr};
396 struct hash_mac_addr *entry, *tmp;
b8ff05a9 397
fc08a01a
HS		 398 /* If the MAC address to be removed is in the hash addr
399 * list, delete it from the list and update hash vector
400 */
401 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
402 if (ether_addr_equal(entry->addr, mac_addr)) {
403 list_del(&entry->list);
404 kfree(entry);
405 return cxgb4_set_addr_hash(pi);
b8ff05a9
DM		 406 }
407 }
408
fc08a01a
HS		 409 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
410 return ret < 0 ? -EINVAL : 0;
b8ff05a9
DM		 411}
412
413/*
414 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
415 * If @mtu is -1 it is left unchanged.
416 */
417static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
418{
b8ff05a9 419 struct port_info *pi = netdev_priv(dev);
fc08a01a 420 struct adapter *adapter = pi->adapter;
b8ff05a9 421
d01f7abc
HS		 422 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
423 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
fc08a01a
HS		 424
425 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
426 (dev->flags & IFF_PROMISC) ? 1 : 0,
427 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
428 sleep_ok);
b8ff05a9
DM		 429}
430
431/**
432 * link_start - enable a port
433 * @dev: the port to enable
434 *
435 * Performs the MAC and PHY actions needed to enable a port.
436 */
437static int link_start(struct net_device *dev)
438{
439 int ret;
440 struct port_info *pi = netdev_priv(dev);
b2612722 441 unsigned int mb = pi->adapter->pf;
b8ff05a9
DM		 442
443 /*
444 * We do not set address filters and promiscuity here, the stack does
445 * that step explicitly.
446 */
060e0c75 447 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 448 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 449 if (ret == 0) {
060e0c75 450 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 451 pi->xact_addr_filt, dev->dev_addr, true,
b6bd29e7 452 true);
b8ff05a9
DM		 453 if (ret >= 0) {
454 pi->xact_addr_filt = ret;
455 ret = 0;
456 }
457 }
458 if (ret == 0)
4036da90 459 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
060e0c75 460 &pi->link_cfg);
30f00847
AB		 461 if (ret == 0) {
462 local_bh_disable();
688848b1
AB		 463 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
464 true, CXGB4_DCB_ENABLED);
30f00847
AB		 465 local_bh_enable();
466 }
688848b1 467
b8ff05a9
DM		 468 return ret;
469}
470
688848b1
AB		 471#ifdef CONFIG_CHELSIO_T4_DCB
472/* Handle a Data Center Bridging update message from the firmware. */
473static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
474{
2b5fb1f2 475 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
134491fd 476 struct net_device *dev = adap->port[adap->chan_map[port]];
688848b1
AB		 477 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
478 int new_dcb_enabled;
479
480 cxgb4_dcb_handle_fw_update(adap, pcmd);
481 new_dcb_enabled = cxgb4_dcb_enabled(dev);
482
483 /* If the DCB has become enabled or disabled on the port then we're
484 * going to need to set up/tear down DCB Priority parameters for the
485 * TX Queues associated with the port.
486 */
487 if (new_dcb_enabled != old_dcb_enabled)
488 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
489}
490#endif /* CONFIG_CHELSIO_T4_DCB */
491
f2b7e78d 492/* Response queue handler for the FW event queue.
b8ff05a9
DM		 493 */
494static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
495 const struct pkt_gl *gl)
496{
497 u8 opcode = ((const struct rss_header *)rsp)->opcode;
498
499 rsp++; /* skip RSS header */
b407a4a9
VP		 500
501 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
502 */
503 if (unlikely(opcode == CPL_FW4_MSG &&
504 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
505 rsp++;
506 opcode = ((const struct rss_header *)rsp)->opcode;
507 rsp++;
508 if (opcode != CPL_SGE_EGR_UPDATE) {
509 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
510 , opcode);
511 goto out;
512 }
513 }
514
b8ff05a9
DM		 515 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
516 const struct cpl_sge_egr_update *p = (void *)rsp;
bdc590b9 517 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
e46dab4d 518 struct sge_txq *txq;
b8ff05a9 519
e46dab4d 520 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 521 txq->restarts++;
ab677ff4 522 if (txq->q_type == CXGB4_TXQ_ETH) {
b8ff05a9
DM		 523 struct sge_eth_txq *eq;
524
525 eq = container_of(txq, struct sge_eth_txq, q);
526 netif_tx_wake_queue(eq->txq);
527 } else {
ab677ff4 528 struct sge_uld_txq *oq;
b8ff05a9 529
ab677ff4 530 oq = container_of(txq, struct sge_uld_txq, q);
b8ff05a9
DM		 531 tasklet_schedule(&oq->qresume_tsk);
532 }
533 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
534 const struct cpl_fw6_msg *p = (void *)rsp;
535
688848b1
AB		 536#ifdef CONFIG_CHELSIO_T4_DCB
537 const struct fw_port_cmd *pcmd = (const void *)p->data;
e2ac9628 538 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
688848b1 539 unsigned int action =
2b5fb1f2 540 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
688848b1
AB		 541
542 if (cmd == FW_PORT_CMD &&
c3168cab
GG		 543 (action == FW_PORT_ACTION_GET_PORT_INFO ||
544 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
2b5fb1f2 545 int port = FW_PORT_CMD_PORTID_G(
688848b1 546 be32_to_cpu(pcmd->op_to_portid));
c3168cab
GG		 547 struct net_device *dev;
548 int dcbxdis, state_input;
549
550 dev = q->adap->port[q->adap->chan_map[port]];
551 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
552 ? !!(pcmd->u.info.dcbxdis_pkd &
553 FW_PORT_CMD_DCBXDIS_F)
554 : !!(pcmd->u.info32.lstatus32_to_cbllen32 &
555 FW_PORT_CMD_DCBXDIS32_F));
556 state_input = (dcbxdis
557 ? CXGB4_DCB_INPUT_FW_DISABLED
558 : CXGB4_DCB_INPUT_FW_ENABLED);
688848b1
AB		 559
560 cxgb4_dcb_state_fsm(dev, state_input);
561 }
562
563 if (cmd == FW_PORT_CMD &&
564 action == FW_PORT_ACTION_L2_DCB_CFG)
565 dcb_rpl(q->adap, pcmd);
566 else
567#endif
568 if (p->type == 0)
569 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 570 } else if (opcode == CPL_L2T_WRITE_RPL) {
571 const struct cpl_l2t_write_rpl *p = (void *)rsp;
572
573 do_l2t_write_rpl(q->adap, p);
3bdb376e
KS		 574 } else if (opcode == CPL_SMT_WRITE_RPL) {
575 const struct cpl_smt_write_rpl *p = (void *)rsp;
576
577 do_smt_write_rpl(q->adap, p);
f2b7e78d
VP		 578 } else if (opcode == CPL_SET_TCB_RPL) {
579 const struct cpl_set_tcb_rpl *p = (void *)rsp;
580
581 filter_rpl(q->adap, p);
12b276fb
KS		 582 } else if (opcode == CPL_ACT_OPEN_RPL) {
583 const struct cpl_act_open_rpl *p = (void *)rsp;
584
585 hash_filter_rpl(q->adap, p);
3b0b3bee
KS		 586 } else if (opcode == CPL_ABORT_RPL_RSS) {
587 const struct cpl_abort_rpl_rss *p = (void *)rsp;
588
589 hash_del_filter_rpl(q->adap, p);
c68644ef
RR		 590 } else if (opcode == CPL_SRQ_TABLE_RPL) {
591 const struct cpl_srq_table_rpl *p = (void *)rsp;
592
593 do_srq_table_rpl(q->adap, p);
b8ff05a9
DM		 594 } else
595 dev_err(q->adap->pdev_dev,
596 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 597out:
b8ff05a9
DM		 598 return 0;
599}
600
b8ff05a9
DM		 601static void disable_msi(struct adapter *adapter)
602{
603 if (adapter->flags & USING_MSIX) {
604 pci_disable_msix(adapter->pdev);
605 adapter->flags &= ~USING_MSIX;
606 } else if (adapter->flags & USING_MSI) {
607 pci_disable_msi(adapter->pdev);
608 adapter->flags &= ~USING_MSI;
609 }
610}
611
612/*
613 * Interrupt handler for non-data events used with MSI-X.
614 */
615static irqreturn_t t4_nondata_intr(int irq, void *cookie)
616{
617 struct adapter *adap = cookie;
0d804338 618 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
b8ff05a9 619
0d804338 620 if (v & PFSW_F) {
b8ff05a9 621 adap->swintr = 1;
0d804338 622 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
b8ff05a9 623 }
c3c7b121
HS		 624 if (adap->flags & MASTER_PF)
625 t4_slow_intr_handler(adap);
b8ff05a9
DM		 626 return IRQ_HANDLED;
627}
628
629/*
630 * Name the MSI-X interrupts.
631 */
632static void name_msix_vecs(struct adapter *adap)
633{
ba27816c 634 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 635
636 /* non-data interrupts */
b1a3c2b6 637 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 638
639 /* FW events */
b1a3c2b6
DM		 640 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
641 adap->port[0]->name);
b8ff05a9
DM		 642
643 /* Ethernet queues */
644 for_each_port(adap, j) {
645 struct net_device *d = adap->port[j];
646 const struct port_info *pi = netdev_priv(d);
647
ba27816c 648 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 649 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
650 d->name, i);
b8ff05a9 651 }
b8ff05a9
DM		 652}
653
654static int request_msix_queue_irqs(struct adapter *adap)
655{
656 struct sge *s = &adap->sge;
0fbc81b3 657 int err, ethqidx;
cf38be6d 658 int msi_index = 2;
b8ff05a9
DM		 659
660 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
661 adap->msix_info[1].desc, &s->fw_evtq);
662 if (err)
663 return err;
664
665 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP		 666 err = request_irq(adap->msix_info[msi_index].vec,
667 t4_sge_intr_msix, 0,
668 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 669 &s->ethrxq[ethqidx].rspq);
670 if (err)
671 goto unwind;
404d9e3f 672 msi_index++;
b8ff05a9 673 }
b8ff05a9
DM		 674 return 0;
675
676unwind:
b8ff05a9 677 while (--ethqidx >= 0)
404d9e3f
VP		 678 free_irq(adap->msix_info[--msi_index].vec,
679 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM		 680 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
681 return err;
682}
683
684static void free_msix_queue_irqs(struct adapter *adap)
685{
404d9e3f 686 int i, msi_index = 2;
b8ff05a9
DM		 687 struct sge *s = &adap->sge;
688
689 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
690 for_each_ethrxq(s, i)
404d9e3f 691 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
b8ff05a9
DM		 692}
693
671b0060 694/**
812034f1 695 * cxgb4_write_rss - write the RSS table for a given port
671b0060
DM		 696 * @pi: the port
697 * @queues: array of queue indices for RSS
698 *
699 * Sets up the portion of the HW RSS table for the port's VI to distribute
700 * packets to the Rx queues in @queues.
c035e183 701 * Should never be called before setting up sge eth rx queues
671b0060 702 */
812034f1 703int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
671b0060
DM		 704{
705 u16 *rss;
706 int i, err;
c035e183
HS		 707 struct adapter *adapter = pi->adapter;
708 const struct sge_eth_rxq *rxq;
671b0060 709
c035e183 710 rxq = &adapter->sge.ethrxq[pi->first_qset];
671b0060
DM		 711 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
712 if (!rss)
713 return -ENOMEM;
714
715 /* map the queue indices to queue ids */
716 for (i = 0; i < pi->rss_size; i++, queues++)
c035e183 717 rss[i] = rxq[*queues].rspq.abs_id;
671b0060 718
b2612722 719 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
060e0c75 720 pi->rss_size, rss, pi->rss_size);
c035e183
HS		 721 /* If Tunnel All Lookup isn't specified in the global RSS
722 * Configuration, then we need to specify a default Ingress
723 * Queue for any ingress packets which aren't hashed. We'll
724 * use our first ingress queue ...
725 */
726 if (!err)
727 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
728 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
729 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
730 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
731 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
732 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
733 rss[0]);
671b0060
DM		 734 kfree(rss);
735 return err;
736}
737
b8ff05a9
DM		 738/**
739 * setup_rss - configure RSS
740 * @adap: the adapter
741 *
671b0060 742 * Sets up RSS for each port.
b8ff05a9
DM		 743 */
744static int setup_rss(struct adapter *adap)
745{
c035e183 746 int i, j, err;
b8ff05a9
DM		 747
748 for_each_port(adap, i) {
749 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 750
c035e183
HS		 751 /* Fill default values with equal distribution */
752 for (j = 0; j < pi->rss_size; j++)
753 pi->rss[j] = j % pi->nqsets;
754
812034f1 755 err = cxgb4_write_rss(pi, pi->rss);
b8ff05a9
DM		 756 if (err)
757 return err;
758 }
759 return 0;
760}
761
e46dab4d
DM		 762/*
763 * Return the channel of the ingress queue with the given qid.
764 */
765static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
766{
767 qid -= p->ingr_start;
768 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
769}
770
b8ff05a9
DM		 771/*
772 * Wait until all NAPI handlers are descheduled.
773 */
774static void quiesce_rx(struct adapter *adap)
775{
776 int i;
777
4b8e27a8 778 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 779 struct sge_rspq *q = adap->sge.ingr_map[i];
780
5226b791 781 if (q && q->handler)
b8ff05a9
DM		 782 napi_disable(&q->napi);
783 }
784}
785
b37987e8
HS		 786/* Disable interrupt and napi handler */
787static void disable_interrupts(struct adapter *adap)
788{
789 if (adap->flags & FULL_INIT_DONE) {
790 t4_intr_disable(adap);
791 if (adap->flags & USING_MSIX) {
792 free_msix_queue_irqs(adap);
793 free_irq(adap->msix_info[0].vec, adap);
794 } else {
795 free_irq(adap->pdev->irq, adap);
796 }
797 quiesce_rx(adap);
798 }
799}
800
b8ff05a9
DM		 801/*
802 * Enable NAPI scheduling and interrupt generation for all Rx queues.
803 */
804static void enable_rx(struct adapter *adap)
805{
806 int i;
807
4b8e27a8 808 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 809 struct sge_rspq *q = adap->sge.ingr_map[i];
810
811 if (!q)
812 continue;
5226b791 813 if (q->handler)
b8ff05a9 814 napi_enable(&q->napi);
5226b791 815
b8ff05a9 816 /* 0-increment GTS to start the timer and enable interrupts */
f612b815
HS		 817 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
818 SEINTARM_V(q->intr_params) |
819 INGRESSQID_V(q->cntxt_id));
b8ff05a9
DM		 820 }
821}
822
1c6a5b0e 823
0fbc81b3 824static int setup_fw_sge_queues(struct adapter *adap)
b8ff05a9 825{
b8ff05a9 826 struct sge *s = &adap->sge;
0fbc81b3 827 int err = 0;
b8ff05a9 828
4b8e27a8
HS		 829 bitmap_zero(s->starving_fl, s->egr_sz);
830 bitmap_zero(s->txq_maperr, s->egr_sz);
b8ff05a9
DM		 831
832 if (adap->flags & USING_MSIX)
94cdb8bb 833 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */
b8ff05a9
DM		 834 else {
835 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
2337ba42 836 NULL, NULL, NULL, -1);
b8ff05a9
DM		 837 if (err)
838 return err;
94cdb8bb 839 adap->msi_idx = -((int)s->intrq.abs_id + 1);
b8ff05a9
DM		 840 }
841
842 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
94cdb8bb 843 adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
0fbc81b3
HS		 844 return err;
845}
846
847/**
848 * setup_sge_queues - configure SGE Tx/Rx/response queues
849 * @adap: the adapter
850 *
851 * Determines how many sets of SGE queues to use and initializes them.
852 * We support multiple queue sets per port if we have MSI-X, otherwise
853 * just one queue set per port.
854 */
855static int setup_sge_queues(struct adapter *adap)
856{
857 int err, i, j;
858 struct sge *s = &adap->sge;
d427caee 859 struct sge_uld_rxq_info *rxq_info = NULL;
0fbc81b3 860 unsigned int cmplqid = 0;
b8ff05a9 861
d427caee
GG		 862 if (is_uld(adap))
863 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
864
b8ff05a9
DM		 865 for_each_port(adap, i) {
866 struct net_device *dev = adap->port[i];
867 struct port_info *pi = netdev_priv(dev);
868 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
869 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
870
871 for (j = 0; j < pi->nqsets; j++, q++) {
94cdb8bb
HS		 872 if (adap->msi_idx > 0)
873 adap->msi_idx++;
b8ff05a9 874 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
94cdb8bb 875 adap->msi_idx, &q->fl,
145ef8a5 876 t4_ethrx_handler,
2337ba42 877 NULL,
193c4c28
AV		 878 t4_get_tp_ch_map(adap,
879 pi->tx_chan));
b8ff05a9
DM		 880 if (err)
881 goto freeout;
882 q->rspq.idx = j;
883 memset(&q->stats, 0, sizeof(q->stats));
884 }
885 for (j = 0; j < pi->nqsets; j++, t++) {
886 err = t4_sge_alloc_eth_txq(adap, t, dev,
887 netdev_get_tx_queue(dev, j),
888 s->fw_evtq.cntxt_id);
889 if (err)
890 goto freeout;
891 }
892 }
893
b8ff05a9 894 for_each_port(adap, i) {
0fbc81b3 895 /* Note that cmplqid below is 0 if we don't
b8ff05a9
DM		 896 * have RDMA queues, and that's the right value.
897 */
0fbc81b3
HS		 898 if (rxq_info)
899 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
900
b8ff05a9 901 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
0fbc81b3 902 s->fw_evtq.cntxt_id, cmplqid);
b8ff05a9
DM		 903 if (err)
904 goto freeout;
905 }
906
a4569504
AG		 907 if (!is_t4(adap->params.chip)) {
908 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
909 netdev_get_tx_queue(adap->port[0], 0)
910 , s->fw_evtq.cntxt_id);
911 if (err)
912 goto freeout;
913 }
914
9bb59b96 915 t4_write_reg(adap, is_t4(adap->params.chip) ?
837e4a42
HS		 916 MPS_TRC_RSS_CONTROL_A :
917 MPS_T5_TRC_RSS_CONTROL_A,
918 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
919 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
b8ff05a9 920 return 0;
0fbc81b3
HS		 921freeout:
922 t4_free_sge_resources(adap);
923 return err;
b8ff05a9
DM		 924}
925
688848b1
AB		 926static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
927 void *accel_priv, select_queue_fallback_t fallback)
928{
929 int txq;
930
931#ifdef CONFIG_CHELSIO_T4_DCB
932 /* If a Data Center Bridging has been successfully negotiated on this
933 * link then we'll use the skb's priority to map it to a TX Queue.
934 * The skb's priority is determined via the VLAN Tag Priority Code
935 * Point field.
936 */
85eacf3f 937 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
688848b1
AB		 938 u16 vlan_tci;
939 int err;
940
941 err = vlan_get_tag(skb, &vlan_tci);
942 if (unlikely(err)) {
943 if (net_ratelimit())
944 netdev_warn(dev,
945 "TX Packet without VLAN Tag on DCB Link\n");
946 txq = 0;
947 } else {
948 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
84a200b3
VP		 949#ifdef CONFIG_CHELSIO_T4_FCOE
950 if (skb->protocol == htons(ETH_P_FCOE))
951 txq = skb->priority & 0x7;
952#endif /* CONFIG_CHELSIO_T4_FCOE */
688848b1
AB		 953 }
954 return txq;
955 }
956#endif /* CONFIG_CHELSIO_T4_DCB */
957
958 if (select_queue) {
959 txq = (skb_rx_queue_recorded(skb)
960 ? skb_get_rx_queue(skb)
961 : smp_processor_id());
962
963 while (unlikely(txq >= dev->real_num_tx_queues))
964 txq -= dev->real_num_tx_queues;
965
966 return txq;
967 }
968
969 return fallback(dev, skb) % dev->real_num_tx_queues;
970}
971
b8ff05a9
DM		 972static int closest_timer(const struct sge *s, int time)
973{
974 int i, delta, match = 0, min_delta = INT_MAX;
975
976 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
977 delta = time - s->timer_val[i];
978 if (delta < 0)
979 delta = -delta;
980 if (delta < min_delta) {
981 min_delta = delta;
982 match = i;
983 }
984 }
985 return match;
986}
987
988static int closest_thres(const struct sge *s, int thres)
989{
990 int i, delta, match = 0, min_delta = INT_MAX;
991
992 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
993 delta = thres - s->counter_val[i];
994 if (delta < 0)
995 delta = -delta;
996 if (delta < min_delta) {
997 min_delta = delta;
998 match = i;
999 }
1000 }
1001 return match;
1002}
1003
b8ff05a9 1004/**
812034f1 1005 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 1006 * @q: the Rx queue
1007 * @us: the hold-off time in us, or 0 to disable timer
1008 * @cnt: the hold-off packet count, or 0 to disable counter
1009 *
1010 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1011 * one of the two needs to be enabled for the queue to generate interrupts.
1012 */
812034f1
HS		 1013int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1014 unsigned int us, unsigned int cnt)
b8ff05a9 1015{
c887ad0e
HS		 1016 struct adapter *adap = q->adap;
1017
b8ff05a9
DM		 1018 if ((us | cnt) == 0)
1019 cnt = 1;
1020
1021 if (cnt) {
1022 int err;
1023 u32 v, new_idx;
1024
1025 new_idx = closest_thres(&adap->sge, cnt);
1026 if (q->desc && q->pktcnt_idx != new_idx) {
1027 /* the queue has already been created, update it */
5167865a
HS		 1028 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1029 FW_PARAMS_PARAM_X_V(
1030 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1031 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
b2612722
HS		 1032 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1033 &v, &new_idx);
b8ff05a9
DM		 1034 if (err)
1035 return err;
1036 }
1037 q->pktcnt_idx = new_idx;
1038 }
1039
1040 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1ecc7b7a 1041 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
b8ff05a9
DM		 1042 return 0;
1043}
1044
c8f44aff 1045static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 1046{
2ed28baa 1047 const struct port_info *pi = netdev_priv(dev);
c8f44aff 1048 netdev_features_t changed = dev->features ^ features;
19ecae2c 1049 int err;
19ecae2c 1050
f646968f 1051 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 1052 return 0;
19ecae2c 1053
b2612722 1054 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
2ed28baa 1055 -1, -1, -1,
f646968f 1056 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 1057 if (unlikely(err))
f646968f 1058 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 1059 return err;
87b6cf51
DM		 1060}
1061
91744948 1062static int setup_debugfs(struct adapter *adap)
b8ff05a9 1063{
b8ff05a9
DM		 1064 if (IS_ERR_OR_NULL(adap->debugfs_root))
1065 return -1;
1066
fd88b31a
HS		 1067#ifdef CONFIG_DEBUG_FS
1068 t4_setup_debugfs(adap);
1069#endif
b8ff05a9
DM		 1070 return 0;
1071}
1072
1073/*
1074 * upper-layer driver support
1075 */
1076
1077/*
1078 * Allocate an active-open TID and set it to the supplied value.
1079 */
1080int cxgb4_alloc_atid(struct tid_info *t, void *data)
1081{
1082 int atid = -1;
1083
1084 spin_lock_bh(&t->atid_lock);
1085 if (t->afree) {
1086 union aopen_entry *p = t->afree;
1087
f2b7e78d 1088 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 1089 t->afree = p->next;
1090 p->data = data;
1091 t->atids_in_use++;
1092 }
1093 spin_unlock_bh(&t->atid_lock);
1094 return atid;
1095}
1096EXPORT_SYMBOL(cxgb4_alloc_atid);
1097
1098/*
1099 * Release an active-open TID.
1100 */
1101void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1102{
f2b7e78d 1103 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 1104
1105 spin_lock_bh(&t->atid_lock);
1106 p->next = t->afree;
1107 t->afree = p;
1108 t->atids_in_use--;
1109 spin_unlock_bh(&t->atid_lock);
1110}
1111EXPORT_SYMBOL(cxgb4_free_atid);
1112
1113/*
1114 * Allocate a server TID and set it to the supplied value.
1115 */
1116int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1117{
1118 int stid;
1119
1120 spin_lock_bh(&t->stid_lock);
1121 if (family == PF_INET) {
1122 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1123 if (stid < t->nstids)
1124 __set_bit(stid, t->stid_bmap);
1125 else
1126 stid = -1;
1127 } else {
a99c683e 1128 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
b8ff05a9
DM		 1129 if (stid < 0)
1130 stid = -1;
1131 }
1132 if (stid >= 0) {
1133 t->stid_tab[stid].data = data;
1134 stid += t->stid_base;
15f63b74
KS		 1135 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1136 * This is equivalent to 4 TIDs. With CLIP enabled it
1137 * needs 2 TIDs.
1138 */
1dec4cec 1139 if (family == PF_INET6) {
a99c683e 1140 t->stids_in_use += 2;
1dec4cec
GG		 1141 t->v6_stids_in_use += 2;
1142 } else {
1143 t->stids_in_use++;
1144 }
b8ff05a9
DM		 1145 }
1146 spin_unlock_bh(&t->stid_lock);
1147 return stid;
1148}
1149EXPORT_SYMBOL(cxgb4_alloc_stid);
1150
dca4faeb
VP		 1151/* Allocate a server filter TID and set it to the supplied value.
1152 */
1153int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1154{
1155 int stid;
1156
1157 spin_lock_bh(&t->stid_lock);
1158 if (family == PF_INET) {
1159 stid = find_next_zero_bit(t->stid_bmap,
1160 t->nstids + t->nsftids, t->nstids);
1161 if (stid < (t->nstids + t->nsftids))
1162 __set_bit(stid, t->stid_bmap);
1163 else
1164 stid = -1;
1165 } else {
1166 stid = -1;
1167 }
1168 if (stid >= 0) {
1169 t->stid_tab[stid].data = data;
470c60c4
KS		 1170 stid -= t->nstids;
1171 stid += t->sftid_base;
2248b293 1172 t->sftids_in_use++;
dca4faeb
VP		 1173 }
1174 spin_unlock_bh(&t->stid_lock);
1175 return stid;
1176}
1177EXPORT_SYMBOL(cxgb4_alloc_sftid);
1178
1179/* Release a server TID.
b8ff05a9
DM		 1180 */
1181void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1182{
470c60c4
KS		 1183 /* Is it a server filter TID? */
1184 if (t->nsftids && (stid >= t->sftid_base)) {
1185 stid -= t->sftid_base;
1186 stid += t->nstids;
1187 } else {
1188 stid -= t->stid_base;
1189 }
1190
b8ff05a9
DM		 1191 spin_lock_bh(&t->stid_lock);
1192 if (family == PF_INET)
1193 __clear_bit(stid, t->stid_bmap);
1194 else
a99c683e 1195 bitmap_release_region(t->stid_bmap, stid, 1);
b8ff05a9 1196 t->stid_tab[stid].data = NULL;
2248b293 1197 if (stid < t->nstids) {
1dec4cec 1198 if (family == PF_INET6) {
a99c683e 1199 t->stids_in_use -= 2;
1dec4cec
GG		 1200 t->v6_stids_in_use -= 2;
1201 } else {
1202 t->stids_in_use--;
1203 }
2248b293
HS		 1204 } else {
1205 t->sftids_in_use--;
1206 }
1dec4cec 1207
b8ff05a9
DM		 1208 spin_unlock_bh(&t->stid_lock);
1209}
1210EXPORT_SYMBOL(cxgb4_free_stid);
1211
1212/*
1213 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1214 */
1215static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1216 unsigned int tid)
1217{
1218 struct cpl_tid_release *req;
1219
1220 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
4df864c1 1221 req = __skb_put(skb, sizeof(*req));
b8ff05a9
DM		 1222 INIT_TP_WR(req, tid);
1223 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1224}
1225
1226/*
1227 * Queue a TID release request and if necessary schedule a work queue to
1228 * process it.
1229 */
31b9c19b 1230static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1231 unsigned int tid)
b8ff05a9
DM		 1232{
1233 void **p = &t->tid_tab[tid];
1234 struct adapter *adap = container_of(t, struct adapter, tids);
1235
1236 spin_lock_bh(&adap->tid_release_lock);
1237 *p = adap->tid_release_head;
1238 /* Low 2 bits encode the Tx channel number */
1239 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1240 if (!adap->tid_release_task_busy) {
1241 adap->tid_release_task_busy = true;
29aaee65 1242 queue_work(adap->workq, &adap->tid_release_task);
b8ff05a9
DM		 1243 }
1244 spin_unlock_bh(&adap->tid_release_lock);
1245}
b8ff05a9
DM		 1246
1247/*
1248 * Process the list of pending TID release requests.
1249 */
1250static void process_tid_release_list(struct work_struct *work)
1251{
1252 struct sk_buff *skb;
1253 struct adapter *adap;
1254
1255 adap = container_of(work, struct adapter, tid_release_task);
1256
1257 spin_lock_bh(&adap->tid_release_lock);
1258 while (adap->tid_release_head) {
1259 void **p = adap->tid_release_head;
1260 unsigned int chan = (uintptr_t)p & 3;
1261 p = (void *)p - chan;
1262
1263 adap->tid_release_head = *p;
1264 *p = NULL;
1265 spin_unlock_bh(&adap->tid_release_lock);
1266
1267 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1268 GFP_KERNEL)))
1269 schedule_timeout_uninterruptible(1);
1270
1271 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1272 t4_ofld_send(adap, skb);
1273 spin_lock_bh(&adap->tid_release_lock);
1274 }
1275 adap->tid_release_task_busy = false;
1276 spin_unlock_bh(&adap->tid_release_lock);
1277}
1278
1279/*
1280 * Release a TID and inform HW. If we are unable to allocate the release
1281 * message we defer to a work queue.
1282 */
1dec4cec
GG		 1283void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1284 unsigned short family)
b8ff05a9 1285{
b8ff05a9
DM		 1286 struct sk_buff *skb;
1287 struct adapter *adap = container_of(t, struct adapter, tids);
1288
9a1bb9f6
HS		 1289 WARN_ON(tid >= t->ntids);
1290
1291 if (t->tid_tab[tid]) {
1292 t->tid_tab[tid] = NULL;
1dec4cec
GG		 1293 atomic_dec(&t->conns_in_use);
1294 if (t->hash_base && (tid >= t->hash_base)) {
1295 if (family == AF_INET6)
1296 atomic_sub(2, &t->hash_tids_in_use);
1297 else
1298 atomic_dec(&t->hash_tids_in_use);
1299 } else {
1300 if (family == AF_INET6)
1301 atomic_sub(2, &t->tids_in_use);
1302 else
1303 atomic_dec(&t->tids_in_use);
1304 }
9a1bb9f6
HS		 1305 }
1306
b8ff05a9
DM		 1307 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1308 if (likely(skb)) {
b8ff05a9
DM		 1309 mk_tid_release(skb, chan, tid);
1310 t4_ofld_send(adap, skb);
1311 } else
1312 cxgb4_queue_tid_release(t, chan, tid);
b8ff05a9
DM		 1313}
1314EXPORT_SYMBOL(cxgb4_remove_tid);
1315
1316/*
1317 * Allocate and initialize the TID tables. Returns 0 on success.
1318 */
1319static int tid_init(struct tid_info *t)
1320{
b6f8eaec 1321 struct adapter *adap = container_of(t, struct adapter, tids);
578b46b9
RL		 1322 unsigned int max_ftids = t->nftids + t->nsftids;
1323 unsigned int natids = t->natids;
1324 unsigned int stid_bmap_size;
1325 unsigned int ftid_bmap_size;
1326 size_t size;
b8ff05a9 1327
dca4faeb 1328 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
578b46b9 1329 ftid_bmap_size = BITS_TO_LONGS(t->nftids);
f2b7e78d
VP		 1330 size = t->ntids * sizeof(*t->tid_tab) +
1331 natids * sizeof(*t->atid_tab) +
b8ff05a9 1332 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 1333 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 1334 stid_bmap_size * sizeof(long) +
578b46b9
RL		 1335 max_ftids * sizeof(*t->ftid_tab) +
1336 ftid_bmap_size * sizeof(long);
f2b7e78d 1337
752ade68 1338 t->tid_tab = kvzalloc(size, GFP_KERNEL);
b8ff05a9
DM		 1339 if (!t->tid_tab)
1340 return -ENOMEM;
1341
1342 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1343 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 1344 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 1345 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
578b46b9 1346 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
b8ff05a9
DM		 1347 spin_lock_init(&t->stid_lock);
1348 spin_lock_init(&t->atid_lock);
578b46b9 1349 spin_lock_init(&t->ftid_lock);
b8ff05a9
DM		 1350
1351 t->stids_in_use = 0;
1dec4cec 1352 t->v6_stids_in_use = 0;
2248b293 1353 t->sftids_in_use = 0;
b8ff05a9
DM		 1354 t->afree = NULL;
1355 t->atids_in_use = 0;
1356 atomic_set(&t->tids_in_use, 0);
1dec4cec 1357 atomic_set(&t->conns_in_use, 0);
9a1bb9f6 1358 atomic_set(&t->hash_tids_in_use, 0);
b8ff05a9
DM		 1359
1360 /* Setup the free list for atid_tab and clear the stid bitmap. */
1361 if (natids) {
1362 while (--natids)
1363 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1364 t->afree = t->atid_tab;
1365 }
b6f8eaec 1366
578b46b9
RL		 1367 if (is_offload(adap)) {
1368 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1369 /* Reserve stid 0 for T4/T5 adapters */
1370 if (!t->stid_base &&
1371 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1372 __set_bit(0, t->stid_bmap);
1373 }
1374
1375 bitmap_zero(t->ftid_bmap, t->nftids);
b8ff05a9
DM		 1376 return 0;
1377}
1378
1379/**
1380 * cxgb4_create_server - create an IP server
1381 * @dev: the device
1382 * @stid: the server TID
1383 * @sip: local IP address to bind server to
1384 * @sport: the server's TCP port
1385 * @queue: queue to direct messages from this server to
1386 *
1387 * Create an IP server for the given port and address.
1388 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1389 */
1390int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 1391 __be32 sip, __be16 sport, __be16 vlan,
1392 unsigned int queue)
b8ff05a9
DM		 1393{
1394 unsigned int chan;
1395 struct sk_buff *skb;
1396 struct adapter *adap;
1397 struct cpl_pass_open_req *req;
80f40c1f 1398 int ret;
b8ff05a9
DM		 1399
1400 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1401 if (!skb)
1402 return -ENOMEM;
1403
1404 adap = netdev2adap(dev);
4df864c1 1405 req = __skb_put(skb, sizeof(*req));
b8ff05a9
DM		 1406 INIT_TP_WR(req, 0);
1407 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1408 req->local_port = sport;
1409 req->peer_port = htons(0);
1410 req->local_ip = sip;
1411 req->peer_ip = htonl(0);
e46dab4d 1412 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1413 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1414 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1415 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1416 ret = t4_mgmt_tx(adap, skb);
1417 return net_xmit_eval(ret);
b8ff05a9
DM		 1418}
1419EXPORT_SYMBOL(cxgb4_create_server);
1420
80f40c1f
VP		 1421/* cxgb4_create_server6 - create an IPv6 server
1422 * @dev: the device
1423 * @stid: the server TID
1424 * @sip: local IPv6 address to bind server to
1425 * @sport: the server's TCP port
1426 * @queue: queue to direct messages from this server to
1427 *
1428 * Create an IPv6 server for the given port and address.
1429 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1430 */
1431int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1432 const struct in6_addr *sip, __be16 sport,
1433 unsigned int queue)
1434{
1435 unsigned int chan;
1436 struct sk_buff *skb;
1437 struct adapter *adap;
1438 struct cpl_pass_open_req6 *req;
1439 int ret;
1440
1441 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1442 if (!skb)
1443 return -ENOMEM;
1444
1445 adap = netdev2adap(dev);
4df864c1 1446 req = __skb_put(skb, sizeof(*req));
80f40c1f
VP		 1447 INIT_TP_WR(req, 0);
1448 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1449 req->local_port = sport;
1450 req->peer_port = htons(0);
1451 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1452 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1453 req->peer_ip_hi = cpu_to_be64(0);
1454 req->peer_ip_lo = cpu_to_be64(0);
1455 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1456 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1457 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1458 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1459 ret = t4_mgmt_tx(adap, skb);
1460 return net_xmit_eval(ret);
1461}
1462EXPORT_SYMBOL(cxgb4_create_server6);
1463
1464int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1465 unsigned int queue, bool ipv6)
1466{
1467 struct sk_buff *skb;
1468 struct adapter *adap;
1469 struct cpl_close_listsvr_req *req;
1470 int ret;
1471
1472 adap = netdev2adap(dev);
1473
1474 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1475 if (!skb)
1476 return -ENOMEM;
1477
4df864c1 1478 req = __skb_put(skb, sizeof(*req));
80f40c1f
VP		 1479 INIT_TP_WR(req, 0);
1480 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
bdc590b9
HS		 1481 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1482 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
80f40c1f
VP		 1483 ret = t4_mgmt_tx(adap, skb);
1484 return net_xmit_eval(ret);
1485}
1486EXPORT_SYMBOL(cxgb4_remove_server);
1487
b8ff05a9
DM		 1488/**
1489 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1490 * @mtus: the HW MTU table
1491 * @mtu: the target MTU
1492 * @idx: index of selected entry in the MTU table
1493 *
1494 * Returns the index and the value in the HW MTU table that is closest to
1495 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1496 * table, in which case that smallest available value is selected.
1497 */
1498unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1499 unsigned int *idx)
1500{
1501 unsigned int i = 0;
1502
1503 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1504 ++i;
1505 if (idx)
1506 *idx = i;
1507 return mtus[i];
1508}
1509EXPORT_SYMBOL(cxgb4_best_mtu);
1510
92e7ae71
HS		 1511/**
1512 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1513 * @mtus: the HW MTU table
1514 * @header_size: Header Size
1515 * @data_size_max: maximum Data Segment Size
1516 * @data_size_align: desired Data Segment Size Alignment (2^N)
1517 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1518 *
1519 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1520 * MTU Table based solely on a Maximum MTU parameter, we break that
1521 * parameter up into a Header Size and Maximum Data Segment Size, and
1522 * provide a desired Data Segment Size Alignment. If we find an MTU in
1523 * the Hardware MTU Table which will result in a Data Segment Size with
1524 * the requested alignment _and_ that MTU isn't "too far" from the
1525 * closest MTU, then we'll return that rather than the closest MTU.
1526 */
1527unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1528 unsigned short header_size,
1529 unsigned short data_size_max,
1530 unsigned short data_size_align,
1531 unsigned int *mtu_idxp)
1532{
1533 unsigned short max_mtu = header_size + data_size_max;
1534 unsigned short data_size_align_mask = data_size_align - 1;
1535 int mtu_idx, aligned_mtu_idx;
1536
1537 /* Scan the MTU Table till we find an MTU which is larger than our
1538 * Maximum MTU or we reach the end of the table. Along the way,
1539 * record the last MTU found, if any, which will result in a Data
1540 * Segment Length matching the requested alignment.
1541 */
1542 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1543 unsigned short data_size = mtus[mtu_idx] - header_size;
1544
1545 /* If this MTU minus the Header Size would result in a
1546 * Data Segment Size of the desired alignment, remember it.
1547 */
1548 if ((data_size & data_size_align_mask) == 0)
1549 aligned_mtu_idx = mtu_idx;
1550
1551 /* If we're not at the end of the Hardware MTU Table and the
1552 * next element is larger than our Maximum MTU, drop out of
1553 * the loop.
1554 */
1555 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1556 break;
1557 }
1558
1559 /* If we fell out of the loop because we ran to the end of the table,
1560 * then we just have to use the last [largest] entry.
1561 */
1562 if (mtu_idx == NMTUS)
1563 mtu_idx--;
1564
1565 /* If we found an MTU which resulted in the requested Data Segment
1566 * Length alignment and that's "not far" from the largest MTU which is
1567 * less than or equal to the maximum MTU, then use that.
1568 */
1569 if (aligned_mtu_idx >= 0 &&
1570 mtu_idx - aligned_mtu_idx <= 1)
1571 mtu_idx = aligned_mtu_idx;
1572
1573 /* If the caller has passed in an MTU Index pointer, pass the
1574 * MTU Index back. Return the MTU value.
1575 */
1576 if (mtu_idxp)
1577 *mtu_idxp = mtu_idx;
1578 return mtus[mtu_idx];
1579}
1580EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1581
27999805
H		 1582/**
1583 * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1584 * @chip: chip type
1585 * @viid: VI id of the given port
1586 *
1587 * Return the SMT index for this VI.
1588 */
1589unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1590{
1591 /* In T4/T5, SMT contains 256 SMAC entries organized in
1592 * 128 rows of 2 entries each.
1593 * In T6, SMT contains 256 SMAC entries in 256 rows.
1594 * TODO: The below code needs to be updated when we add support
1595 * for 256 VFs.
1596 */
1597 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1598 return ((viid & 0x7f) << 1);
1599 else
1600 return (viid & 0x7f);
1601}
1602EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1603
b8ff05a9
DM		 1604/**
1605 * cxgb4_port_chan - get the HW channel of a port
1606 * @dev: the net device for the port
1607 *
1608 * Return the HW Tx channel of the given port.
1609 */
1610unsigned int cxgb4_port_chan(const struct net_device *dev)
1611{
1612 return netdev2pinfo(dev)->tx_chan;
1613}
1614EXPORT_SYMBOL(cxgb4_port_chan);
1615
881806bc
VP		 1616unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1617{
1618 struct adapter *adap = netdev2adap(dev);
2cc301d2 1619 u32 v1, v2, lp_count, hp_count;
881806bc 1620
f061de42
HS		 1621 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1622 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1623 if (is_t4(adap->params.chip)) {
f061de42
HS		 1624 lp_count = LP_COUNT_G(v1);
1625 hp_count = HP_COUNT_G(v1);
2cc301d2 1626 } else {
f061de42
HS		 1627 lp_count = LP_COUNT_T5_G(v1);
1628 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1629 }
1630 return lpfifo ? lp_count : hp_count;
881806bc
VP		 1631}
1632EXPORT_SYMBOL(cxgb4_dbfifo_count);
1633
b8ff05a9
DM		 1634/**
1635 * cxgb4_port_viid - get the VI id of a port
1636 * @dev: the net device for the port
1637 *
1638 * Return the VI id of the given port.
1639 */
1640unsigned int cxgb4_port_viid(const struct net_device *dev)
1641{
1642 return netdev2pinfo(dev)->viid;
1643}
1644EXPORT_SYMBOL(cxgb4_port_viid);
1645
1646/**
1647 * cxgb4_port_idx - get the index of a port
1648 * @dev: the net device for the port
1649 *
1650 * Return the index of the given port.
1651 */
1652unsigned int cxgb4_port_idx(const struct net_device *dev)
1653{
1654 return netdev2pinfo(dev)->port_id;
1655}
1656EXPORT_SYMBOL(cxgb4_port_idx);
1657
b8ff05a9
DM		 1658void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1659 struct tp_tcp_stats *v6)
1660{
1661 struct adapter *adap = pci_get_drvdata(pdev);
1662
1663 spin_lock(&adap->stats_lock);
5ccf9d04 1664 t4_tp_get_tcp_stats(adap, v4, v6, false);
b8ff05a9
DM		 1665 spin_unlock(&adap->stats_lock);
1666}
1667EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1668
1669void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1670 const unsigned int *pgsz_order)
1671{
1672 struct adapter *adap = netdev2adap(dev);
1673
0d804338
HS		 1674 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1675 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1676 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1677 HPZ3_V(pgsz_order[3]));
b8ff05a9
DM		 1678}
1679EXPORT_SYMBOL(cxgb4_iscsi_init);
1680
3069ee9b
VP		 1681int cxgb4_flush_eq_cache(struct net_device *dev)
1682{
1683 struct adapter *adap = netdev2adap(dev);
3069ee9b 1684
736c3b94 1685 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
3069ee9b
VP		 1686}
1687EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1688
1689static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1690{
f061de42 1691 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
3069ee9b
VP		 1692 __be64 indices;
1693 int ret;
1694
fc5ab020
HS		 1695 spin_lock(&adap->win0_lock);
1696 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1697 sizeof(indices), (__be32 *)&indices,
1698 T4_MEMORY_READ);
1699 spin_unlock(&adap->win0_lock);
3069ee9b 1700 if (!ret) {
404d9e3f
VP		 1701 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1702 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 1703 }
1704 return ret;
1705}
1706
1707int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1708 u16 size)
1709{
1710 struct adapter *adap = netdev2adap(dev);
1711 u16 hw_pidx, hw_cidx;
1712 int ret;
1713
1714 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1715 if (ret)
1716 goto out;
1717
1718 if (pidx != hw_pidx) {
1719 u16 delta;
f612b815 1720 u32 val;
3069ee9b
VP		 1721
1722 if (pidx >= hw_pidx)
1723 delta = pidx - hw_pidx;
1724 else
1725 delta = size - hw_pidx + pidx;
f612b815
HS		 1726
1727 if (is_t4(adap->params.chip))
1728 val = PIDX_V(delta);
1729 else
1730 val = PIDX_T5_V(delta);
3069ee9b 1731 wmb();
f612b815
HS		 1732 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1733 QID_V(qid) | val);
3069ee9b
VP		 1734 }
1735out:
1736 return ret;
1737}
1738EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1739
031cf476
HS		 1740int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1741{
6559a7e8 1742 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
031cf476 1743 u32 edc0_end, edc1_end, mc0_end, mc1_end;
8b4e6b3c
AV		 1744 u32 offset, memtype, memaddr;
1745 struct adapter *adap;
1746 u32 hma_size = 0;
031cf476
HS		 1747 int ret;
1748
1749 adap = netdev2adap(dev);
1750
1751 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1752
1753 /* Figure out where the offset lands in the Memory Type/Address scheme.
1754 * This code assumes that the memory is laid out starting at offset 0
1755 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1756 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
1757 * MC0, and some have both MC0 and MC1.
1758 */
6559a7e8
HS		 1759 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1760 edc0_size = EDRAM0_SIZE_G(size) << 20;
1761 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1762 edc1_size = EDRAM1_SIZE_G(size) << 20;
1763 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1764 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
031cf476 1765
8b4e6b3c
AV		 1766 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1767 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1768 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1769 }
031cf476
HS		 1770 edc0_end = edc0_size;
1771 edc1_end = edc0_end + edc1_size;
1772 mc0_end = edc1_end + mc0_size;
1773
1774 if (offset < edc0_end) {
1775 memtype = MEM_EDC0;
1776 memaddr = offset;
1777 } else if (offset < edc1_end) {
1778 memtype = MEM_EDC1;
1779 memaddr = offset - edc0_end;
1780 } else {
8b4e6b3c
AV		 1781 if (hma_size && (offset < (edc1_end + hma_size))) {
1782 memtype = MEM_HMA;
1783 memaddr = offset - edc1_end;
1784 } else if (offset < mc0_end) {
031cf476
HS		 1785 memtype = MEM_MC0;
1786 memaddr = offset - edc1_end;
3ccc6cf7 1787 } else if (is_t5(adap->params.chip)) {
6559a7e8
HS		 1788 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1789 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
031cf476
HS		 1790 mc1_end = mc0_end + mc1_size;
1791 if (offset < mc1_end) {
1792 memtype = MEM_MC1;
1793 memaddr = offset - mc0_end;
1794 } else {
1795 /* offset beyond the end of any memory */
1796 goto err;
1797 }
3ccc6cf7
HS		 1798 } else {
1799 /* T4/T6 only has a single memory channel */
1800 goto err;
031cf476
HS		 1801 }
1802 }
1803
1804 spin_lock(&adap->win0_lock);
1805 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1806 spin_unlock(&adap->win0_lock);
1807 return ret;
1808
1809err:
1810 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1811 stag, offset);
1812 return -EINVAL;
1813}
1814EXPORT_SYMBOL(cxgb4_read_tpte);
1815
7730b4c7
HS		 1816u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1817{
1818 u32 hi, lo;
1819 struct adapter *adap;
1820
1821 adap = netdev2adap(dev);
f612b815
HS		 1822 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1823 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
7730b4c7
HS		 1824
1825 return ((u64)hi << 32) | (u64)lo;
1826}
1827EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1828
df64e4d3
HS		 1829int cxgb4_bar2_sge_qregs(struct net_device *dev,
1830 unsigned int qid,
1831 enum cxgb4_bar2_qtype qtype,
66cf188e 1832 int user,
df64e4d3
HS		 1833 u64 *pbar2_qoffset,
1834 unsigned int *pbar2_qid)
1835{
b2612722 1836 return t4_bar2_sge_qregs(netdev2adap(dev),
df64e4d3
HS		 1837 qid,
1838 (qtype == CXGB4_BAR2_QTYPE_EGRESS
1839 ? T4_BAR2_QTYPE_EGRESS
1840 : T4_BAR2_QTYPE_INGRESS),
66cf188e 1841 user,
df64e4d3
HS		 1842 pbar2_qoffset,
1843 pbar2_qid);
1844}
1845EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1846
b8ff05a9
DM		 1847static struct pci_driver cxgb4_driver;
1848
1849static void check_neigh_update(struct neighbour *neigh)
1850{
1851 const struct device *parent;
1852 const struct net_device *netdev = neigh->dev;
1853
d0d7b10b 1854 if (is_vlan_dev(netdev))
b8ff05a9
DM		 1855 netdev = vlan_dev_real_dev(netdev);
1856 parent = netdev->dev.parent;
1857 if (parent && parent->driver == &cxgb4_driver.driver)
1858 t4_l2t_update(dev_get_drvdata(parent), neigh);
1859}
1860
1861static int netevent_cb(struct notifier_block *nb, unsigned long event,
1862 void *data)
1863{
1864 switch (event) {
1865 case NETEVENT_NEIGH_UPDATE:
1866 check_neigh_update(data);
1867 break;
b8ff05a9
DM		 1868 case NETEVENT_REDIRECT:
1869 default:
1870 break;
1871 }
1872 return 0;
1873}
1874
1875static bool netevent_registered;
1876static struct notifier_block cxgb4_netevent_nb = {
1877 .notifier_call = netevent_cb
1878};
1879
3069ee9b
VP		 1880static void drain_db_fifo(struct adapter *adap, int usecs)
1881{
2cc301d2 1882 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 1883
1884 do {
f061de42
HS		 1885 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1886 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1887 if (is_t4(adap->params.chip)) {
f061de42
HS		 1888 lp_count = LP_COUNT_G(v1);
1889 hp_count = HP_COUNT_G(v1);
2cc301d2 1890 } else {
f061de42
HS		 1891 lp_count = LP_COUNT_T5_G(v1);
1892 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1893 }
1894
1895 if (lp_count == 0 && hp_count == 0)
1896 break;
3069ee9b
VP		 1897 set_current_state(TASK_UNINTERRUPTIBLE);
1898 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 1899 } while (1);
1900}
1901
1902static void disable_txq_db(struct sge_txq *q)
1903{
05eb2389
SW		 1904 unsigned long flags;
1905
1906 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 1907 q->db_disabled = 1;
05eb2389 1908 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 1909}
1910
05eb2389 1911static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 1912{
1913 spin_lock_irq(&q->db_lock);
05eb2389
SW		 1914 if (q->db_pidx_inc) {
1915 /* Make sure that all writes to the TX descriptors
1916 * are committed before we tell HW about them.
1917 */
1918 wmb();
f612b815
HS		 1919 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1920 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
05eb2389
SW		 1921 q->db_pidx_inc = 0;
1922 }
3069ee9b
VP		 1923 q->db_disabled = 0;
1924 spin_unlock_irq(&q->db_lock);
1925}
1926
1927static void disable_dbs(struct adapter *adap)
1928{
1929 int i;
1930
1931 for_each_ethrxq(&adap->sge, i)
1932 disable_txq_db(&adap->sge.ethtxq[i].q);
ab677ff4
HS		 1933 if (is_offload(adap)) {
1934 struct sge_uld_txq_info *txq_info =
1935 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1936
1937 if (txq_info) {
1938 for_each_ofldtxq(&adap->sge, i) {
1939 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1940
1941 disable_txq_db(&txq->q);
1942 }
1943 }
1944 }
3069ee9b
VP		 1945 for_each_port(adap, i)
1946 disable_txq_db(&adap->sge.ctrlq[i].q);
1947}
1948
1949static void enable_dbs(struct adapter *adap)
1950{
1951 int i;
1952
1953 for_each_ethrxq(&adap->sge, i)
05eb2389 1954 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
ab677ff4
HS		 1955 if (is_offload(adap)) {
1956 struct sge_uld_txq_info *txq_info =
1957 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1958
1959 if (txq_info) {
1960 for_each_ofldtxq(&adap->sge, i) {
1961 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1962
1963 enable_txq_db(adap, &txq->q);
1964 }
1965 }
1966 }
3069ee9b 1967 for_each_port(adap, i)
05eb2389
SW		 1968 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
1969}
1970
1971static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
1972{
0fbc81b3
HS		 1973 enum cxgb4_uld type = CXGB4_ULD_RDMA;
1974
1975 if (adap->uld && adap->uld[type].handle)
1976 adap->uld[type].control(adap->uld[type].handle, cmd);
05eb2389
SW		 1977}
1978
1979static void process_db_full(struct work_struct *work)
1980{
1981 struct adapter *adap;
1982
1983 adap = container_of(work, struct adapter, db_full_task);
1984
1985 drain_db_fifo(adap, dbfifo_drain_delay);
1986 enable_dbs(adap);
1987 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7
HS		 1988 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1989 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1990 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
1991 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
1992 else
1993 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1994 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
3069ee9b
VP		 1995}
1996
1997static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
1998{
1999 u16 hw_pidx, hw_cidx;
2000 int ret;
2001
05eb2389 2002 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 2003 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2004 if (ret)
2005 goto out;
2006 if (q->db_pidx != hw_pidx) {
2007 u16 delta;
f612b815 2008 u32 val;
3069ee9b
VP		 2009
2010 if (q->db_pidx >= hw_pidx)
2011 delta = q->db_pidx - hw_pidx;
2012 else
2013 delta = q->size - hw_pidx + q->db_pidx;
f612b815
HS		 2014
2015 if (is_t4(adap->params.chip))
2016 val = PIDX_V(delta);
2017 else
2018 val = PIDX_T5_V(delta);
3069ee9b 2019 wmb();
f612b815
HS		 2020 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2021 QID_V(q->cntxt_id) | val);
3069ee9b
VP		 2022 }
2023out:
2024 q->db_disabled = 0;
05eb2389
SW		 2025 q->db_pidx_inc = 0;
2026 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 2027 if (ret)
2028 CH_WARN(adap, "DB drop recovery failed.\n");
2029}
0fbc81b3 2030
3069ee9b
VP		 2031static void recover_all_queues(struct adapter *adap)
2032{
2033 int i;
2034
2035 for_each_ethrxq(&adap->sge, i)
2036 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
ab677ff4
HS		 2037 if (is_offload(adap)) {
2038 struct sge_uld_txq_info *txq_info =
2039 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2040 if (txq_info) {
2041 for_each_ofldtxq(&adap->sge, i) {
2042 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2043
2044 sync_txq_pidx(adap, &txq->q);
2045 }
2046 }
2047 }
3069ee9b
VP		 2048 for_each_port(adap, i)
2049 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2050}
2051
881806bc
VP		 2052static void process_db_drop(struct work_struct *work)
2053{
2054 struct adapter *adap;
881806bc 2055
3069ee9b 2056 adap = container_of(work, struct adapter, db_drop_task);
881806bc 2057
d14807dd 2058 if (is_t4(adap->params.chip)) {
05eb2389 2059 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2060 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 2061 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2062 recover_all_queues(adap);
05eb2389 2063 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2064 enable_dbs(adap);
05eb2389 2065 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7 2066 } else if (is_t5(adap->params.chip)) {
2cc301d2
SR		 2067 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2068 u16 qid = (dropped_db >> 15) & 0x1ffff;
2069 u16 pidx_inc = dropped_db & 0x1fff;
df64e4d3
HS		 2070 u64 bar2_qoffset;
2071 unsigned int bar2_qid;
2072 int ret;
2cc301d2 2073
b2612722 2074 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
e0456717 2075 0, &bar2_qoffset, &bar2_qid);
df64e4d3
HS		 2076 if (ret)
2077 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2078 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2079 else
f612b815 2080 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
df64e4d3 2081 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2cc301d2
SR		 2082
2083 /* Re-enable BAR2 WC */
2084 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2085 }
2086
3ccc6cf7
HS		 2087 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2088 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
881806bc
VP		 2089}
2090
2091void t4_db_full(struct adapter *adap)
2092{
d14807dd 2093 if (is_t4(adap->params.chip)) {
05eb2389
SW		 2094 disable_dbs(adap);
2095 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
f612b815
HS		 2096 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2097 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
29aaee65 2098 queue_work(adap->workq, &adap->db_full_task);
2cc301d2 2099 }
881806bc
VP		 2100}
2101
2102void t4_db_dropped(struct adapter *adap)
2103{
05eb2389
SW		 2104 if (is_t4(adap->params.chip)) {
2105 disable_dbs(adap);
2106 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2107 }
29aaee65 2108 queue_work(adap->workq, &adap->db_drop_task);
881806bc
VP		 2109}
2110
0fbc81b3
HS		 2111void t4_register_netevent_notifier(void)
2112{
b8ff05a9
DM		 2113 if (!netevent_registered) {
2114 register_netevent_notifier(&cxgb4_netevent_nb);
2115 netevent_registered = true;
2116 }
b8ff05a9
DM		 2117}
2118
2119static void detach_ulds(struct adapter *adap)
2120{
2121 unsigned int i;
2122
2123 mutex_lock(&uld_mutex);
2124 list_del(&adap->list_node);
6a146f3a 2125
b8ff05a9 2126 for (i = 0; i < CXGB4_ULD_MAX; i++)
6a146f3a 2127 if (adap->uld && adap->uld[i].handle)
94cdb8bb
HS		 2128 adap->uld[i].state_change(adap->uld[i].handle,
2129 CXGB4_STATE_DETACH);
6a146f3a 2130
b8ff05a9
DM		 2131 if (netevent_registered && list_empty(&adapter_list)) {
2132 unregister_netevent_notifier(&cxgb4_netevent_nb);
2133 netevent_registered = false;
2134 }
2135 mutex_unlock(&uld_mutex);
2136}
2137
2138static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2139{
2140 unsigned int i;
2141
2142 mutex_lock(&uld_mutex);
2143 for (i = 0; i < CXGB4_ULD_MAX; i++)
94cdb8bb
HS		 2144 if (adap->uld && adap->uld[i].handle)
2145 adap->uld[i].state_change(adap->uld[i].handle,
2146 new_state);
b8ff05a9
DM		 2147 mutex_unlock(&uld_mutex);
2148}
2149
1bb60376 2150#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 2151static int cxgb4_inet6addr_handler(struct notifier_block *this,
2152 unsigned long event, void *data)
01bcca68 2153{
b5a02f50
AB		 2154 struct inet6_ifaddr *ifa = data;
2155 struct net_device *event_dev = ifa->idev->dev;
2156 const struct device *parent = NULL;
2157#if IS_ENABLED(CONFIG_BONDING)
01bcca68 2158 struct adapter *adap;
b5a02f50 2159#endif
d0d7b10b 2160 if (is_vlan_dev(event_dev))
b5a02f50
AB		 2161 event_dev = vlan_dev_real_dev(event_dev);
2162#if IS_ENABLED(CONFIG_BONDING)
2163 if (event_dev->flags & IFF_MASTER) {
2164 list_for_each_entry(adap, &adapter_list, list_node) {
2165 switch (event) {
2166 case NETDEV_UP:
2167 cxgb4_clip_get(adap->port[0],
2168 (const u32 *)ifa, 1);
2169 break;
2170 case NETDEV_DOWN:
2171 cxgb4_clip_release(adap->port[0],
2172 (const u32 *)ifa, 1);
2173 break;
2174 default:
2175 break;
2176 }
2177 }
2178 return NOTIFY_OK;
2179 }
2180#endif
01bcca68 2181
b5a02f50
AB		 2182 if (event_dev)
2183 parent = event_dev->dev.parent;
01bcca68 2184
b5a02f50 2185 if (parent && parent->driver == &cxgb4_driver.driver) {
01bcca68
VP		 2186 switch (event) {
2187 case NETDEV_UP:
b5a02f50 2188 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2189 break;
2190 case NETDEV_DOWN:
b5a02f50 2191 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2192 break;
2193 default:
2194 break;
2195 }
2196 }
b5a02f50 2197 return NOTIFY_OK;
01bcca68
VP		 2198}
2199
b5a02f50 2200static bool inet6addr_registered;
01bcca68
VP		 2201static struct notifier_block cxgb4_inet6addr_notifier = {
2202 .notifier_call = cxgb4_inet6addr_handler
2203};
2204
01bcca68
VP		 2205static void update_clip(const struct adapter *adap)
2206{
2207 int i;
2208 struct net_device *dev;
2209 int ret;
2210
2211 rcu_read_lock();
2212
2213 for (i = 0; i < MAX_NPORTS; i++) {
2214 dev = adap->port[i];
2215 ret = 0;
2216
2217 if (dev)
b5a02f50 2218 ret = cxgb4_update_root_dev_clip(dev);
01bcca68
VP		 2219
2220 if (ret < 0)
2221 break;
2222 }
2223 rcu_read_unlock();
2224}
1bb60376 2225#endif /* IS_ENABLED(CONFIG_IPV6) */
01bcca68 2226
b8ff05a9
DM		 2227/**
2228 * cxgb_up - enable the adapter
2229 * @adap: adapter being enabled
2230 *
2231 * Called when the first port is enabled, this function performs the
2232 * actions necessary to make an adapter operational, such as completing
2233 * the initialization of HW modules, and enabling interrupts.
2234 *
2235 * Must be called with the rtnl lock held.
2236 */
2237static int cxgb_up(struct adapter *adap)
2238{
aaefae9b 2239 int err;
b8ff05a9 2240
91060381 2241 mutex_lock(&uld_mutex);
aaefae9b
DM		 2242 err = setup_sge_queues(adap);
2243 if (err)
91060381 2244 goto rel_lock;
aaefae9b
DM		 2245 err = setup_rss(adap);
2246 if (err)
2247 goto freeq;
b8ff05a9
DM		 2248
2249 if (adap->flags & USING_MSIX) {
aaefae9b 2250 name_msix_vecs(adap);
b8ff05a9
DM		 2251 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2252 adap->msix_info[0].desc, adap);
2253 if (err)
2254 goto irq_err;
b8ff05a9
DM		 2255 err = request_msix_queue_irqs(adap);
2256 if (err) {
2257 free_irq(adap->msix_info[0].vec, adap);
2258 goto irq_err;
2259 }
2260 } else {
2261 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2262 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 2263 adap->port[0]->name, adap);
b8ff05a9
DM		 2264 if (err)
2265 goto irq_err;
2266 }
e7519f99 2267
b8ff05a9
DM		 2268 enable_rx(adap);
2269 t4_sge_start(adap);
2270 t4_intr_enable(adap);
aaefae9b 2271 adap->flags |= FULL_INIT_DONE;
e7519f99
GG		 2272 mutex_unlock(&uld_mutex);
2273
b8ff05a9 2274 notify_ulds(adap, CXGB4_STATE_UP);
1bb60376 2275#if IS_ENABLED(CONFIG_IPV6)
01bcca68 2276 update_clip(adap);
1bb60376 2277#endif
fc08a01a
HS		 2278 /* Initialize hash mac addr list*/
2279 INIT_LIST_HEAD(&adap->mac_hlist);
b8ff05a9 2280 return err;
91060381 2281
b8ff05a9
DM		 2282 irq_err:
2283 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 2284 freeq:
2285 t4_free_sge_resources(adap);
91060381
RR		 2286 rel_lock:
2287 mutex_unlock(&uld_mutex);
2288 return err;
b8ff05a9
DM		 2289}
2290
2291static void cxgb_down(struct adapter *adapter)
2292{
b8ff05a9 2293 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 2294 cancel_work_sync(&adapter->db_full_task);
2295 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 2296 adapter->tid_release_task_busy = false;
204dc3c0 2297 adapter->tid_release_head = NULL;
b8ff05a9 2298
aaefae9b
DM		 2299 t4_sge_stop(adapter);
2300 t4_free_sge_resources(adapter);
2301 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM		 2302}
2303
2304/*
2305 * net_device operations
2306 */
2307static int cxgb_open(struct net_device *dev)
2308{
2309 int err;
2310 struct port_info *pi = netdev_priv(dev);
2311 struct adapter *adapter = pi->adapter;
2312
6a3c869a
DM		 2313 netif_carrier_off(dev);
2314
aaefae9b
DM		 2315 if (!(adapter->flags & FULL_INIT_DONE)) {
2316 err = cxgb_up(adapter);
2317 if (err < 0)
2318 return err;
2319 }
b8ff05a9 2320
2061ec3f
GG		 2321 /* It's possible that the basic port information could have
2322 * changed since we first read it.
2323 */
2324 err = t4_update_port_info(pi);
2325 if (err < 0)
2326 return err;
2327
f68707b8
DM		 2328 err = link_start(dev);
2329 if (!err)
2330 netif_tx_start_all_queues(dev);
2331 return err;
b8ff05a9
DM		 2332}
2333
2334static int cxgb_close(struct net_device *dev)
2335{
b8ff05a9
DM		 2336 struct port_info *pi = netdev_priv(dev);
2337 struct adapter *adapter = pi->adapter;
ba581f77 2338 int ret;
b8ff05a9
DM		 2339
2340 netif_tx_stop_all_queues(dev);
2341 netif_carrier_off(dev);
ba581f77
GG		 2342 ret = t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2343#ifdef CONFIG_CHELSIO_T4_DCB
2344 cxgb4_dcb_reset(dev);
2345 dcb_tx_queue_prio_enable(dev, false);
2346#endif
2347 return ret;
b8ff05a9
DM		 2348}
2349
dca4faeb 2350int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 2351 __be32 sip, __be16 sport, __be16 vlan,
2352 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 2353{
2354 int ret;
2355 struct filter_entry *f;
2356 struct adapter *adap;
2357 int i;
2358 u8 *val;
2359
2360 adap = netdev2adap(dev);
2361
1cab775c 2362 /* Adjust stid to correct filter index */
470c60c4 2363 stid -= adap->tids.sftid_base;
1cab775c
VP		 2364 stid += adap->tids.nftids;
2365
dca4faeb
VP		 2366 /* Check to make sure the filter requested is writable ...
2367 */
2368 f = &adap->tids.ftid_tab[stid];
2369 ret = writable_filter(f);
2370 if (ret)
2371 return ret;
2372
2373 /* Clear out any old resources being used by the filter before
2374 * we start constructing the new filter.
2375 */
2376 if (f->valid)
2377 clear_filter(adap, f);
2378
2379 /* Clear out filter specifications */
2380 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2381 f->fs.val.lport = cpu_to_be16(sport);
2382 f->fs.mask.lport = ~0;
2383 val = (u8 *)&sip;
793dad94 2384 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 2385 for (i = 0; i < 4; i++) {
2386 f->fs.val.lip[i] = val[i];
2387 f->fs.mask.lip[i] = ~0;
2388 }
0d804338 2389 if (adap->params.tp.vlan_pri_map & PORT_F) {
793dad94
VP		 2390 f->fs.val.iport = port;
2391 f->fs.mask.iport = mask;
2392 }
2393 }
dca4faeb 2394
0d804338 2395 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
7c89e555
KS		 2396 f->fs.val.proto = IPPROTO_TCP;
2397 f->fs.mask.proto = ~0;
2398 }
2399
dca4faeb
VP		 2400 f->fs.dirsteer = 1;
2401 f->fs.iq = queue;
2402 /* Mark filter as locked */
2403 f->locked = 1;
2404 f->fs.rpttid = 1;
2405
6b254afd
GG		 2406 /* Save the actual tid. We need this to get the corresponding
2407 * filter entry structure in filter_rpl.
2408 */
2409 f->tid = stid + adap->tids.ftid_base;
dca4faeb
VP		 2410 ret = set_filter_wr(adap, stid);
2411 if (ret) {
2412 clear_filter(adap, f);
2413 return ret;
2414 }
2415
2416 return 0;
2417}
2418EXPORT_SYMBOL(cxgb4_create_server_filter);
2419
2420int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2421 unsigned int queue, bool ipv6)
2422{
dca4faeb
VP		 2423 struct filter_entry *f;
2424 struct adapter *adap;
2425
2426 adap = netdev2adap(dev);
1cab775c
VP		 2427
2428 /* Adjust stid to correct filter index */
470c60c4 2429 stid -= adap->tids.sftid_base;
1cab775c
VP		 2430 stid += adap->tids.nftids;
2431
dca4faeb
VP		 2432 f = &adap->tids.ftid_tab[stid];
2433 /* Unlock the filter */
2434 f->locked = 0;
2435
8c14846d 2436 return delete_filter(adap, stid);
dca4faeb
VP		 2437}
2438EXPORT_SYMBOL(cxgb4_remove_server_filter);
2439
bc1f4470 2440static void cxgb_get_stats(struct net_device *dev,
2441 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 2442{
2443 struct port_stats stats;
2444 struct port_info *p = netdev_priv(dev);
2445 struct adapter *adapter = p->adapter;
b8ff05a9 2446
9fe6cb58
GS		 2447 /* Block retrieving statistics during EEH error
2448 * recovery. Otherwise, the recovery might fail
2449 * and the PCI device will be removed permanently
2450 */
b8ff05a9 2451 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 2452 if (!netif_device_present(dev)) {
2453 spin_unlock(&adapter->stats_lock);
bc1f4470 2454 return;
9fe6cb58 2455 }
a4cfd929
HS		 2456 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2457 &p->stats_base);
b8ff05a9
DM		 2458 spin_unlock(&adapter->stats_lock);
2459
2460 ns->tx_bytes = stats.tx_octets;
2461 ns->tx_packets = stats.tx_frames;
2462 ns->rx_bytes = stats.rx_octets;
2463 ns->rx_packets = stats.rx_frames;
2464 ns->multicast = stats.rx_mcast_frames;
2465
2466 /* detailed rx_errors */
2467 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2468 stats.rx_runt;
2469 ns->rx_over_errors = 0;
2470 ns->rx_crc_errors = stats.rx_fcs_err;
2471 ns->rx_frame_errors = stats.rx_symbol_err;
b93f79be 2472 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 +
b8ff05a9
DM		 2473 stats.rx_ovflow2 + stats.rx_ovflow3 +
2474 stats.rx_trunc0 + stats.rx_trunc1 +
2475 stats.rx_trunc2 + stats.rx_trunc3;
2476 ns->rx_missed_errors = 0;
2477
2478 /* detailed tx_errors */
2479 ns->tx_aborted_errors = 0;
2480 ns->tx_carrier_errors = 0;
2481 ns->tx_fifo_errors = 0;
2482 ns->tx_heartbeat_errors = 0;
2483 ns->tx_window_errors = 0;
2484
2485 ns->tx_errors = stats.tx_error_frames;
2486 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2487 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
b8ff05a9
DM		 2488}
2489
2490static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2491{
060e0c75 2492 unsigned int mbox;
b8ff05a9
DM		 2493 int ret = 0, prtad, devad;
2494 struct port_info *pi = netdev_priv(dev);
a4569504 2495 struct adapter *adapter = pi->adapter;
b8ff05a9
DM		 2496 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2497
2498 switch (cmd) {
2499 case SIOCGMIIPHY:
2500 if (pi->mdio_addr < 0)
2501 return -EOPNOTSUPP;
2502 data->phy_id = pi->mdio_addr;
2503 break;
2504 case SIOCGMIIREG:
2505 case SIOCSMIIREG:
2506 if (mdio_phy_id_is_c45(data->phy_id)) {
2507 prtad = mdio_phy_id_prtad(data->phy_id);
2508 devad = mdio_phy_id_devad(data->phy_id);
2509 } else if (data->phy_id < 32) {
2510 prtad = data->phy_id;
2511 devad = 0;
2512 data->reg_num &= 0x1f;
2513 } else
2514 return -EINVAL;
2515
b2612722 2516 mbox = pi->adapter->pf;
b8ff05a9 2517 if (cmd == SIOCGMIIREG)
060e0c75 2518 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2519 data->reg_num, &data->val_out);
2520 else
060e0c75 2521 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2522 data->reg_num, data->val_in);
2523 break;
5e2a5ebc
HS		 2524 case SIOCGHWTSTAMP:
2525 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2526 sizeof(pi->tstamp_config)) ?
2527 -EFAULT : 0;
2528 case SIOCSHWTSTAMP:
2529 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2530 sizeof(pi->tstamp_config)))
2531 return -EFAULT;
2532
a4569504
AG		 2533 if (!is_t4(adapter->params.chip)) {
2534 switch (pi->tstamp_config.tx_type) {
2535 case HWTSTAMP_TX_OFF:
2536 case HWTSTAMP_TX_ON:
2537 break;
2538 default:
2539 return -ERANGE;
2540 }
2541
2542 switch (pi->tstamp_config.rx_filter) {
2543 case HWTSTAMP_FILTER_NONE:
2544 pi->rxtstamp = false;
2545 break;
2546 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2547 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2548 cxgb4_ptprx_timestamping(pi, pi->port_id,
2549 PTP_TS_L4);
2550 break;
2551 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2552 cxgb4_ptprx_timestamping(pi, pi->port_id,
2553 PTP_TS_L2_L4);
2554 break;
2555 case HWTSTAMP_FILTER_ALL:
2556 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2557 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2558 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2559 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2560 pi->rxtstamp = true;
2561 break;
2562 default:
2563 pi->tstamp_config.rx_filter =
2564 HWTSTAMP_FILTER_NONE;
2565 return -ERANGE;
2566 }
2567
2568 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2569 (pi->tstamp_config.rx_filter ==
2570 HWTSTAMP_FILTER_NONE)) {
2571 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2572 pi->ptp_enable = false;
2573 }
2574
2575 if (pi->tstamp_config.rx_filter !=
2576 HWTSTAMP_FILTER_NONE) {
2577 if (cxgb4_ptp_redirect_rx_packet(adapter,
2578 pi) >= 0)
2579 pi->ptp_enable = true;
2580 }
2581 } else {
2582 /* For T4 Adapters */
2583 switch (pi->tstamp_config.rx_filter) {
2584 case HWTSTAMP_FILTER_NONE:
5e2a5ebc
HS		 2585 pi->rxtstamp = false;
2586 break;
a4569504 2587 case HWTSTAMP_FILTER_ALL:
5e2a5ebc
HS		 2588 pi->rxtstamp = true;
2589 break;
a4569504
AG		 2590 default:
2591 pi->tstamp_config.rx_filter =
2592 HWTSTAMP_FILTER_NONE;
5e2a5ebc 2593 return -ERANGE;
a4569504 2594 }
5e2a5ebc 2595 }
5e2a5ebc
HS		 2596 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2597 sizeof(pi->tstamp_config)) ?
2598 -EFAULT : 0;
b8ff05a9
DM		 2599 default:
2600 return -EOPNOTSUPP;
2601 }
2602 return ret;
2603}
2604
2605static void cxgb_set_rxmode(struct net_device *dev)
2606{
2607 /* unfortunately we can't return errors to the stack */
2608 set_rxmode(dev, -1, false);
2609}
2610
2611static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2612{
2613 int ret;
2614 struct port_info *pi = netdev_priv(dev);
2615
b2612722 2616 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
060e0c75 2617 -1, -1, -1, true);
b8ff05a9
DM		 2618 if (!ret)
2619 dev->mtu = new_mtu;
2620 return ret;
2621}
2622
858aa65c 2623#ifdef CONFIG_PCI_IOV
baf50868 2624static int cxgb4_mgmt_open(struct net_device *dev)
e7b48a32
HS		 2625{
2626 /* Turn carrier off since we don't have to transmit anything on this
2627 * interface.
2628 */
2629 netif_carrier_off(dev);
2630 return 0;
2631}
2632
661dbeb9 2633/* Fill MAC address that will be assigned by the FW */
baf50868 2634static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
661dbeb9 2635{
661dbeb9 2636 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
baf50868
GG		 2637 unsigned int i, vf, nvfs;
2638 u16 a, b;
661dbeb9
HS		 2639 int err;
2640 u8 *na;
661dbeb9 2641
baf50868
GG		 2642 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2643 PCI_CAP_ID_VPD);
661dbeb9 2644 err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
baf50868
GG		 2645 if (err)
2646 return;
2647
2648 na = adap->params.vpd.na;
2649 for (i = 0; i < ETH_ALEN; i++)
2650 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2651 hex2val(na[2 * i + 1]));
2652
2653 a = (hw_addr[0] << 8) | hw_addr[1];
2654 b = (hw_addr[1] << 8) | hw_addr[2];
2655 a ^= b;
2656 a |= 0x0200; /* locally assigned Ethernet MAC address */
2657 a &= ~0x0100; /* not a multicast Ethernet MAC address */
2658 macaddr[0] = a >> 8;
2659 macaddr[1] = a & 0xff;
2660
2661 for (i = 2; i < 5; i++)
2662 macaddr[i] = hw_addr[i + 1];
2663
2664 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2665 vf < nvfs; vf++) {
2666 macaddr[5] = adap->pf * 16 + vf;
2667 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
661dbeb9
HS		 2668 }
2669}
2670
baf50868 2671static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
858aa65c
HS		 2672{
2673 struct port_info *pi = netdev_priv(dev);
2674 struct adapter *adap = pi->adapter;
661dbeb9 2675 int ret;
858aa65c
HS		 2676
2677 /* verify MAC addr is valid */
2678 if (!is_valid_ether_addr(mac)) {
2679 dev_err(pi->adapter->pdev_dev,
2680 "Invalid Ethernet address %pM for VF %d\n",
2681 mac, vf);
2682 return -EINVAL;
2683 }
2684
2685 dev_info(pi->adapter->pdev_dev,
2686 "Setting MAC %pM on VF %d\n", mac, vf);
661dbeb9
HS		 2687 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2688 if (!ret)
2689 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2690 return ret;
2691}
2692
baf50868
GG		 2693static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2694 int vf, struct ifla_vf_info *ivi)
661dbeb9
HS		 2695{
2696 struct port_info *pi = netdev_priv(dev);
2697 struct adapter *adap = pi->adapter;
2698
2699 if (vf >= adap->num_vfs)
2700 return -EINVAL;
2701 ivi->vf = vf;
8ea4fae9
GG		 2702 ivi->max_tx_rate = adap->vfinfo[vf].tx_rate;
2703 ivi->min_tx_rate = 0;
661dbeb9
HS		 2704 ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr);
2705 return 0;
858aa65c 2706}
96fe11f2 2707
baf50868
GG		 2708static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2709 struct netdev_phys_item_id *ppid)
96fe11f2
GG		 2710{
2711 struct port_info *pi = netdev_priv(dev);
2712 unsigned int phy_port_id;
2713
2714 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2715 ppid->id_len = sizeof(phy_port_id);
2716 memcpy(ppid->id, &phy_port_id, ppid->id_len);
2717 return 0;
2718}
2719
baf50868
GG		 2720static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2721 int min_tx_rate, int max_tx_rate)
8ea4fae9
GG		 2722{
2723 struct port_info *pi = netdev_priv(dev);
2724 struct adapter *adap = pi->adapter;
c3168cab 2725 unsigned int link_ok, speed, mtu;
8ea4fae9
GG		 2726 u32 fw_pfvf, fw_class;
2727 int class_id = vf;
c3168cab 2728 int ret;
8ea4fae9
GG		 2729 u16 pktsize;
2730
2731 if (vf >= adap->num_vfs)
2732 return -EINVAL;
2733
2734 if (min_tx_rate) {
2735 dev_err(adap->pdev_dev,
2736 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2737 min_tx_rate, vf);
2738 return -EINVAL;
2739 }
c3168cab
GG		 2740
2741 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
8ea4fae9
GG		 2742 if (ret != FW_SUCCESS) {
2743 dev_err(adap->pdev_dev,
c3168cab 2744 "Failed to get link information for VF %d\n", vf);
8ea4fae9
GG		 2745 return -EINVAL;
2746 }
c3168cab 2747
8ea4fae9
GG		 2748 if (!link_ok) {
2749 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2750 return -EINVAL;
2751 }
8ea4fae9
GG		 2752
2753 if (max_tx_rate > speed) {
2754 dev_err(adap->pdev_dev,
2755 "Max tx rate %d for VF %d can't be > link-speed %u",
2756 max_tx_rate, vf, speed);
2757 return -EINVAL;
2758 }
c3168cab
GG		 2759
2760 pktsize = mtu;
8ea4fae9
GG		 2761 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2762 pktsize = pktsize - sizeof(struct ethhdr) - 4;
2763 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2764 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2765 /* configure Traffic Class for rate-limiting */
2766 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2767 SCHED_CLASS_LEVEL_CL_RL,
2768 SCHED_CLASS_MODE_CLASS,
2769 SCHED_CLASS_RATEUNIT_BITS,
2770 SCHED_CLASS_RATEMODE_ABS,
c3168cab 2771 pi->tx_chan, class_id, 0,
8ea4fae9
GG		 2772 max_tx_rate * 1000, 0, pktsize);
2773 if (ret) {
2774 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2775 ret);
2776 return -EINVAL;
2777 }
2778 dev_info(adap->pdev_dev,
2779 "Class %d with MSS %u configured with rate %u\n",
2780 class_id, pktsize, max_tx_rate);
2781
2782 /* bind VF to configured Traffic Class */
2783 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2784 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2785 fw_class = class_id;
2786 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2787 &fw_class);
2788 if (ret) {
2789 dev_err(adap->pdev_dev,
2790 "Err %d in binding VF %d to Traffic Class %d\n",
2791 ret, vf, class_id);
2792 return -EINVAL;
2793 }
2794 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2795 adap->pf, vf, class_id);
2796 adap->vfinfo[vf].tx_rate = max_tx_rate;
2797 return 0;
2798}
2799
9d5fd927
GG		 2800static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
2801 u16 vlan, u8 qos, __be16 vlan_proto)
2802{
2803 struct port_info *pi = netdev_priv(dev);
2804 struct adapter *adap = pi->adapter;
2805 int ret;
2806
2807 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
2808 return -EINVAL;
2809
2810 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
2811 return -EPROTONOSUPPORT;
2812
2813 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
2814 if (!ret) {
2815 adap->vfinfo[vf].vlan = vlan;
2816 return 0;
2817 }
2818
2819 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
2820 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
2821 return ret;
2822}
2823#endif /* CONFIG_PCI_IOV */
858aa65c 2824
b8ff05a9
DM		 2825static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2826{
2827 int ret;
2828 struct sockaddr *addr = p;
2829 struct port_info *pi = netdev_priv(dev);
2830
2831 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 2832 return -EADDRNOTAVAIL;
b8ff05a9 2833
b2612722 2834 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
060e0c75 2835 pi->xact_addr_filt, addr->sa_data, true, true);
b8ff05a9
DM		 2836 if (ret < 0)
2837 return ret;
2838
2839 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2840 pi->xact_addr_filt = ret;
2841 return 0;
2842}
2843
b8ff05a9
DM		 2844#ifdef CONFIG_NET_POLL_CONTROLLER
2845static void cxgb_netpoll(struct net_device *dev)
2846{
2847 struct port_info *pi = netdev_priv(dev);
2848 struct adapter *adap = pi->adapter;
2849
2850 if (adap->flags & USING_MSIX) {
2851 int i;
2852 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2853
2854 for (i = pi->nqsets; i; i--, rx++)
2855 t4_sge_intr_msix(0, &rx->rspq);
2856 } else
2857 t4_intr_handler(adap)(0, adap);
2858}
2859#endif
2860
10a2604e
RL		 2861static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2862{
2863 struct port_info *pi = netdev_priv(dev);
2864 struct adapter *adap = pi->adapter;
2865 struct sched_class *e;
2866 struct ch_sched_params p;
2867 struct ch_sched_queue qe;
2868 u32 req_rate;
2869 int err = 0;
2870
2871 if (!can_sched(dev))
2872 return -ENOTSUPP;
2873
2874 if (index < 0 || index > pi->nqsets - 1)
2875 return -EINVAL;
2876
2877 if (!(adap->flags & FULL_INIT_DONE)) {
2878 dev_err(adap->pdev_dev,
2879 "Failed to rate limit on queue %d. Link Down?\n",
2880 index);
2881 return -EINVAL;
2882 }
2883
2884 /* Convert from Mbps to Kbps */
2885 req_rate = rate << 10;
2886
d185efc1 2887 /* Max rate is 100 Gbps */
10a2604e
RL		 2888 if (req_rate >= SCHED_MAX_RATE_KBPS) {
2889 dev_err(adap->pdev_dev,
d185efc1
GG		 2890 "Invalid rate %u Mbps, Max rate is %u Mbps\n",
2891 rate, SCHED_MAX_RATE_KBPS >> 10);
10a2604e
RL		 2892 return -ERANGE;
2893 }
2894
2895 /* First unbind the queue from any existing class */
2896 memset(&qe, 0, sizeof(qe));
2897 qe.queue = index;
2898 qe.class = SCHED_CLS_NONE;
2899
2900 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
2901 if (err) {
2902 dev_err(adap->pdev_dev,
2903 "Unbinding Queue %d on port %d fail. Err: %d\n",
2904 index, pi->port_id, err);
2905 return err;
2906 }
2907
2908 /* Queue already unbound */
2909 if (!req_rate)
2910 return 0;
2911
2912 /* Fetch any available unused or matching scheduling class */
2913 memset(&p, 0, sizeof(p));
2914 p.type = SCHED_CLASS_TYPE_PACKET;
2915 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL;
2916 p.u.params.mode = SCHED_CLASS_MODE_CLASS;
2917 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
2918 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
2919 p.u.params.channel = pi->tx_chan;
2920 p.u.params.class = SCHED_CLS_NONE;
2921 p.u.params.minrate = 0;
2922 p.u.params.maxrate = req_rate;
2923 p.u.params.weight = 0;
2924 p.u.params.pktsize = dev->mtu;
2925
2926 e = cxgb4_sched_class_alloc(dev, &p);
2927 if (!e)
2928 return -ENOMEM;
2929
2930 /* Bind the queue to a scheduling class */
2931 memset(&qe, 0, sizeof(qe));
2932 qe.queue = index;
2933 qe.class = e->idx;
2934
2935 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
2936 if (err)
2937 dev_err(adap->pdev_dev,
2938 "Queue rate limiting failed. Err: %d\n", err);
2939 return err;
2940}
2941
6a345b3d
KS		 2942static int cxgb_setup_tc_flower(struct net_device *dev,
2943 struct tc_cls_flower_offload *cls_flower)
2944{
6a345b3d
KS		 2945 switch (cls_flower->command) {
2946 case TC_CLSFLOWER_REPLACE:
2947 return cxgb4_tc_flower_replace(dev, cls_flower);
2948 case TC_CLSFLOWER_DESTROY:
2949 return cxgb4_tc_flower_destroy(dev, cls_flower);
2950 case TC_CLSFLOWER_STATS:
2951 return cxgb4_tc_flower_stats(dev, cls_flower);
2952 default:
2953 return -EOPNOTSUPP;
2954 }
2955}
2956
f7323043 2957static int cxgb_setup_tc_cls_u32(struct net_device *dev,
f7323043
JP		 2958 struct tc_cls_u32_offload *cls_u32)
2959{
f7323043
JP		 2960 switch (cls_u32->command) {
2961 case TC_CLSU32_NEW_KNODE:
2962 case TC_CLSU32_REPLACE_KNODE:
5fd9fc4e 2963 return cxgb4_config_knode(dev, cls_u32);
f7323043 2964 case TC_CLSU32_DELETE_KNODE:
5fd9fc4e 2965 return cxgb4_delete_knode(dev, cls_u32);
f7323043
JP		 2966 default:
2967 return -EOPNOTSUPP;
2968 }
2969}
2970
cd019e91
JP		 2971static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2972 void *cb_priv)
d8931847 2973{
cd019e91 2974 struct net_device *dev = cb_priv;
d8931847
RL		 2975 struct port_info *pi = netdev2pinfo(dev);
2976 struct adapter *adap = netdev2adap(dev);
2977
2978 if (!(adap->flags & FULL_INIT_DONE)) {
2979 dev_err(adap->pdev_dev,
2980 "Failed to setup tc on port %d. Link Down?\n",
2981 pi->port_id);
2982 return -EINVAL;
2983 }
2984
2a84bbaf 2985 if (!tc_cls_can_offload_and_chain0(dev, type_data))
44ae12a7
JP		 2986 return -EOPNOTSUPP;
2987
f7323043
JP		 2988 switch (type) {
2989 case TC_SETUP_CLSU32:
de4784ca 2990 return cxgb_setup_tc_cls_u32(dev, type_data);
6a345b3d
KS		 2991 case TC_SETUP_CLSFLOWER:
2992 return cxgb_setup_tc_flower(dev, type_data);
f7323043
JP		 2993 default:
2994 return -EOPNOTSUPP;
d8931847 2995 }
d8931847
RL		 2996}
2997
cd019e91
JP		 2998static int cxgb_setup_tc_block(struct net_device *dev,
2999 struct tc_block_offload *f)
3000{
3001 struct port_info *pi = netdev2pinfo(dev);
3002
3003 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3004 return -EOPNOTSUPP;
3005
3006 switch (f->command) {
3007 case TC_BLOCK_BIND:
3008 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb,
3009 pi, dev);
3010 case TC_BLOCK_UNBIND:
3011 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi);
3012 return 0;
3013 default:
3014 return -EOPNOTSUPP;
3015 }
3016}
3017
3018static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3019 void *type_data)
3020{
3021 switch (type) {
cd019e91
JP		 3022 case TC_SETUP_BLOCK:
3023 return cxgb_setup_tc_block(dev, type_data);
3024 default:
3025 return -EOPNOTSUPP;
3026 }
3027}
3028
846eac3f
GG		 3029static void cxgb_del_udp_tunnel(struct net_device *netdev,
3030 struct udp_tunnel_info *ti)
3031{
3032 struct port_info *pi = netdev_priv(netdev);
3033 struct adapter *adapter = pi->adapter;
3034 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3035 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3036 int ret = 0, i;
3037
3038 if (chip_ver < CHELSIO_T6)
3039 return;
3040
3041 switch (ti->type) {
3042 case UDP_TUNNEL_TYPE_VXLAN:
3043 if (!adapter->vxlan_port_cnt ||
3044 adapter->vxlan_port != ti->port)
3045 return; /* Invalid VxLAN destination port */
3046
3047 adapter->vxlan_port_cnt--;
3048 if (adapter->vxlan_port_cnt)
3049 return;
3050
3051 adapter->vxlan_port = 0;
3052 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3053 break;
c746fc0e
GG		 3054 case UDP_TUNNEL_TYPE_GENEVE:
3055 if (!adapter->geneve_port_cnt ||
3056 adapter->geneve_port != ti->port)
3057 return; /* Invalid GENEVE destination port */
3058
3059 adapter->geneve_port_cnt--;
3060 if (adapter->geneve_port_cnt)
3061 return;
3062
3063 adapter->geneve_port = 0;
3064 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
846eac3f
GG		 3065 default:
3066 return;
3067 }
3068
3069 /* Matchall mac entries can be deleted only after all tunnel ports
3070 * are brought down or removed.
3071 */
3072 if (!adapter->rawf_cnt)
3073 return;
3074 for_each_port(adapter, i) {
3075 pi = adap2pinfo(adapter, i);
3076 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3077 match_all_mac, match_all_mac,
3078 adapter->rawf_start +
3079 pi->port_id,
3080 1, pi->port_id, true);
3081 if (ret < 0) {
3082 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3083 i);
3084 return;
3085 }
3086 atomic_dec(&adapter->mps_encap[adapter->rawf_start +
3087 pi->port_id].refcnt);
3088 }
3089}
3090
3091static void cxgb_add_udp_tunnel(struct net_device *netdev,
3092 struct udp_tunnel_info *ti)
3093{
3094 struct port_info *pi = netdev_priv(netdev);
3095 struct adapter *adapter = pi->adapter;
3096 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3097 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3098 int i, ret;
3099
c746fc0e 3100 if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
846eac3f
GG		 3101 return;
3102
3103 switch (ti->type) {
3104 case UDP_TUNNEL_TYPE_VXLAN:
846eac3f
GG		 3105 /* Callback for adding vxlan port can be called with the same
3106 * port for both IPv4 and IPv6. We should not disable the
3107 * offloading when the same port for both protocols is added
3108 * and later one of them is removed.
3109 */
3110 if (adapter->vxlan_port_cnt &&
3111 adapter->vxlan_port == ti->port) {
3112 adapter->vxlan_port_cnt++;
3113 return;
3114 }
3115
3116 /* We will support only one VxLAN port */
3117 if (adapter->vxlan_port_cnt) {
3118 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3119 be16_to_cpu(adapter->vxlan_port),
3120 be16_to_cpu(ti->port));
3121 return;
3122 }
3123
3124 adapter->vxlan_port = ti->port;
3125 adapter->vxlan_port_cnt = 1;
3126
3127 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3128 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3129 break;
c746fc0e
GG		 3130 case UDP_TUNNEL_TYPE_GENEVE:
3131 if (adapter->geneve_port_cnt &&
3132 adapter->geneve_port == ti->port) {
3133 adapter->geneve_port_cnt++;
3134 return;
3135 }
3136
3137 /* We will support only one GENEVE port */
3138 if (adapter->geneve_port_cnt) {
3139 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3140 be16_to_cpu(adapter->geneve_port),
3141 be16_to_cpu(ti->port));
3142 return;
3143 }
3144
3145 adapter->geneve_port = ti->port;
3146 adapter->geneve_port_cnt = 1;
3147
3148 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3149 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
846eac3f
GG		 3150 default:
3151 return;
3152 }
3153
3154 /* Create a 'match all' mac filter entry for inner mac,
3155 * if raw mac interface is supported. Once the linux kernel provides
3156 * driver entry points for adding/deleting the inner mac addresses,
3157 * we will remove this 'match all' entry and fallback to adding
3158 * exact match filters.
3159 */
c746fc0e
GG		 3160 for_each_port(adapter, i) {
3161 pi = adap2pinfo(adapter, i);
3162
3163 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3164 match_all_mac,
3165 match_all_mac,
3166 adapter->rawf_start +
3167 pi->port_id,
3168 1, pi->port_id, true);
3169 if (ret < 0) {
3170 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3171 be16_to_cpu(ti->port));
3172 cxgb_del_udp_tunnel(netdev, ti);
3173 return;
846eac3f 3174 }
c746fc0e 3175 atomic_inc(&adapter->mps_encap[ret].refcnt);
846eac3f
GG		 3176 }
3177}
3178
4621ffd6
GG		 3179static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3180 struct net_device *dev,
3181 netdev_features_t features)
3182{
3183 struct port_info *pi = netdev_priv(dev);
3184 struct adapter *adapter = pi->adapter;
3185
3186 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3187 return features;
3188
3189 /* Check if hw supports offload for this packet */
3190 if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3191 return features;
3192
3193 /* Offload is not supported for this encapsulated packet */
3194 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3195}
3196
90592b9a
AV		 3197static netdev_features_t cxgb_fix_features(struct net_device *dev,
3198 netdev_features_t features)
3199{
3200 /* Disable GRO, if RX_CSUM is disabled */
3201 if (!(features & NETIF_F_RXCSUM))
3202 features &= ~NETIF_F_GRO;
3203
3204 return features;
3205}
3206
b8ff05a9
DM		 3207static const struct net_device_ops cxgb4_netdev_ops = {
3208 .ndo_open = cxgb_open,
3209 .ndo_stop = cxgb_close,
3210 .ndo_start_xmit = t4_eth_xmit,
688848b1 3211 .ndo_select_queue = cxgb_select_queue,
9be793bf 3212 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 3213 .ndo_set_rx_mode = cxgb_set_rxmode,
3214 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 3215 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 3216 .ndo_validate_addr = eth_validate_addr,
3217 .ndo_do_ioctl = cxgb_ioctl,
3218 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 3219#ifdef CONFIG_NET_POLL_CONTROLLER
3220 .ndo_poll_controller = cxgb_netpoll,
3221#endif
84a200b3
VP		 3222#ifdef CONFIG_CHELSIO_T4_FCOE
3223 .ndo_fcoe_enable = cxgb_fcoe_enable,
3224 .ndo_fcoe_disable = cxgb_fcoe_disable,
3225#endif /* CONFIG_CHELSIO_T4_FCOE */
10a2604e 3226 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate,
d8931847 3227 .ndo_setup_tc = cxgb_setup_tc,
846eac3f
GG		 3228 .ndo_udp_tunnel_add = cxgb_add_udp_tunnel,
3229 .ndo_udp_tunnel_del = cxgb_del_udp_tunnel,
4621ffd6 3230 .ndo_features_check = cxgb_features_check,
90592b9a 3231 .ndo_fix_features = cxgb_fix_features,
b8ff05a9
DM		 3232};
3233
858aa65c 3234#ifdef CONFIG_PCI_IOV
e7b48a32 3235static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
baf50868
GG		 3236 .ndo_open = cxgb4_mgmt_open,
3237 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac,
3238 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config,
3239 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate,
3240 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id,
9d5fd927 3241 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan,
7829451c 3242};
e7b48a32 3243#endif
7829451c 3244
baf50868
GG		 3245static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3246 struct ethtool_drvinfo *info)
7829451c
HS		 3247{
3248 struct adapter *adapter = netdev2adap(dev);
3249
3250 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3251 strlcpy(info->version, cxgb4_driver_version,
3252 sizeof(info->version));
3253 strlcpy(info->bus_info, pci_name(adapter->pdev),
3254 sizeof(info->bus_info));
3255}
3256
3257static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
baf50868 3258 .get_drvinfo = cxgb4_mgmt_get_drvinfo,
7829451c
HS		 3259};
3260
8b7372c1
GG		 3261static void notify_fatal_err(struct work_struct *work)
3262{
3263 struct adapter *adap;
3264
3265 adap = container_of(work, struct adapter, fatal_err_notify_task);
3266 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3267}
3268
b8ff05a9
DM		 3269void t4_fatal_err(struct adapter *adap)
3270{
3be0679b
HS		 3271 int port;
3272
025d0973
GP		 3273 if (pci_channel_offline(adap->pdev))
3274 return;
3275
3be0679b
HS		 3276 /* Disable the SGE since ULDs are going to free resources that
3277 * could be exposed to the adapter. RDMA MWs for example...
3278 */
3279 t4_shutdown_adapter(adap);
3280 for_each_port(adap, port) {
3281 struct net_device *dev = adap->port[port];
3282
3283 /* If we get here in very early initialization the network
3284 * devices may not have been set up yet.
3285 */
3286 if (!dev)
3287 continue;
3288
3289 netif_tx_stop_all_queues(dev);
3290 netif_carrier_off(dev);
3291 }
b8ff05a9 3292 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
8b7372c1 3293 queue_work(adap->workq, &adap->fatal_err_notify_task);
b8ff05a9
DM		 3294}
3295
3296static void setup_memwin(struct adapter *adap)
3297{
b562fc37 3298 u32 nic_win_base = t4_get_util_window(adap);
b8ff05a9 3299
b562fc37 3300 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
636f9d37
VP		 3301}
3302
3303static void setup_memwin_rdma(struct adapter *adap)
3304{
1ae970e0 3305 if (adap->vres.ocq.size) {
0abfd152
HS		 3306 u32 start;
3307 unsigned int sz_kb;
1ae970e0 3308
0abfd152
HS		 3309 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3310 start &= PCI_BASE_ADDRESS_MEM_MASK;
3311 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 3312 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3313 t4_write_reg(adap,
f061de42
HS		 3314 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3315 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
1ae970e0 3316 t4_write_reg(adap,
f061de42 3317 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
1ae970e0
DM		 3318 adap->vres.ocq.start);
3319 t4_read_reg(adap,
f061de42 3320 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
1ae970e0 3321 }
b8ff05a9
DM		 3322}
3323
8b4e6b3c
AV		 3324/* HMA Definitions */
3325
3326/* The maximum number of address that can be send in a single FW cmd */
3327#define HMA_MAX_ADDR_IN_CMD 5
3328
3329#define HMA_PAGE_SIZE PAGE_SIZE
3330
3331#define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */
3332
3333#define HMA_PAGE_ORDER \
3334 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \
3335 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3336
3337/* The minimum and maximum possible HMA sizes that can be specified in the FW
3338 * configuration(in units of MB).
3339 */
3340#define HMA_MIN_TOTAL_SIZE 1
3341#define HMA_MAX_TOTAL_SIZE \
3342 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \
3343 HMA_MAX_NO_FW_ADDRESS) >> 20)
3344
3345static void adap_free_hma_mem(struct adapter *adapter)
3346{
3347 struct scatterlist *iter;
3348 struct page *page;
3349 int i;
3350
3351 if (!adapter->hma.sgt)
3352 return;
3353
3354 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3355 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3356 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3357 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3358 }
3359
3360 for_each_sg(adapter->hma.sgt->sgl, iter,
3361 adapter->hma.sgt->orig_nents, i) {
3362 page = sg_page(iter);
3363 if (page)
3364 __free_pages(page, HMA_PAGE_ORDER);
3365 }
3366
3367 kfree(adapter->hma.phy_addr);
3368 sg_free_table(adapter->hma.sgt);
3369 kfree(adapter->hma.sgt);
3370 adapter->hma.sgt = NULL;
3371}
3372
3373static int adap_config_hma(struct adapter *adapter)
3374{
3375 struct scatterlist *sgl, *iter;
3376 struct sg_table *sgt;
3377 struct page *newpage;
3378 unsigned int i, j, k;
3379 u32 param, hma_size;
3380 unsigned int ncmds;
3381 size_t page_size;
3382 u32 page_order;
3383 int node, ret;
3384
3385 /* HMA is supported only for T6+ cards.
3386 * Avoid initializing HMA in kdump kernels.
3387 */
3388 if (is_kdump_kernel() ||
3389 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3390 return 0;
3391
3392 /* Get the HMA region size required by fw */
3393 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3394 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3395 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3396 1, &param, &hma_size);
3397 /* An error means card has its own memory or HMA is not supported by
3398 * the firmware. Return without any errors.
3399 */
3400 if (ret || !hma_size)
3401 return 0;
3402
3403 if (hma_size < HMA_MIN_TOTAL_SIZE ||
3404 hma_size > HMA_MAX_TOTAL_SIZE) {
3405 dev_err(adapter->pdev_dev,
3406 "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3407 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3408 return -EINVAL;
3409 }
3410
3411 page_size = HMA_PAGE_SIZE;
3412 page_order = HMA_PAGE_ORDER;
3413 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3414 if (unlikely(!adapter->hma.sgt)) {
3415 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3416 return -ENOMEM;
3417 }
3418 sgt = adapter->hma.sgt;
3419 /* FW returned value will be in MB's
3420 */
3421 sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3422 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3423 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3424 kfree(adapter->hma.sgt);
3425 adapter->hma.sgt = NULL;
3426 return -ENOMEM;
3427 }
3428
3429 sgl = adapter->hma.sgt->sgl;
3430 node = dev_to_node(adapter->pdev_dev);
3431 for_each_sg(sgl, iter, sgt->orig_nents, i) {
3432 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL,
3433 page_order);
3434 if (!newpage) {
3435 dev_err(adapter->pdev_dev,
3436 "Not enough memory for HMA page allocation\n");
3437 ret = -ENOMEM;
3438 goto free_hma;
3439 }
3440 sg_set_page(iter, newpage, page_size << page_order, 0);
3441 }
3442
3443 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3444 DMA_BIDIRECTIONAL);
3445 if (!sgt->nents) {
3446 dev_err(adapter->pdev_dev,
3447 "Not enough memory for HMA DMA mapping");
3448 ret = -ENOMEM;
3449 goto free_hma;
3450 }
3451 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3452
3453 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3454 GFP_KERNEL);
3455 if (unlikely(!adapter->hma.phy_addr))
3456 goto free_hma;
3457
3458 for_each_sg(sgl, iter, sgt->nents, i) {
3459 newpage = sg_page(iter);
3460 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3461 }
3462
3463 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3464 /* Pass on the addresses to firmware */
3465 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3466 struct fw_hma_cmd hma_cmd;
3467 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3468 u8 soc = 0, eoc = 0;
3469 u8 hma_mode = 1; /* Presently we support only Page table mode */
3470
3471 soc = (i == 0) ? 1 : 0;
3472 eoc = (i == ncmds - 1) ? 1 : 0;
3473
3474 /* For last cmd, set naddr corresponding to remaining
3475 * addresses
3476 */
3477 if (i == ncmds - 1) {
3478 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3479 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3480 }
3481 memset(&hma_cmd, 0, sizeof(hma_cmd));
3482 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3483 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3484 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3485
3486 hma_cmd.mode_to_pcie_params =
3487 htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3488 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3489
3490 /* HMA cmd size specified in MB's */
3491 hma_cmd.naddr_size =
3492 htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3493 FW_HMA_CMD_NADDR_V(naddr));
3494
3495 /* Total Page size specified in units of 4K */
3496 hma_cmd.addr_size_pkd =
3497 htonl(FW_HMA_CMD_ADDR_SIZE_V
3498 ((page_size << page_order) >> 12));
3499
3500 /* Fill the 5 addresses */
3501 for (j = 0; j < naddr; j++) {
3502 hma_cmd.phy_address[j] =
3503 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3504 }
3505 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3506 sizeof(hma_cmd), &hma_cmd);
3507 if (ret) {
3508 dev_err(adapter->pdev_dev,
3509 "HMA FW command failed with err %d\n", ret);
3510 goto free_hma;
3511 }
3512 }
3513
3514 if (!ret)
3515 dev_info(adapter->pdev_dev,
3516 "Reserved %uMB host memory for HMA\n", hma_size);
3517 return ret;
3518
3519free_hma:
3520 adap_free_hma_mem(adapter);
3521 return ret;
3522}
3523
02b5fb8e
DM		 3524static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3525{
3526 u32 v;
3527 int ret;
3528
3529 /* get device capabilities */
3530 memset(c, 0, sizeof(*c));
e2ac9628
HS		 3531 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3532 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3533 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
b2612722 3534 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
02b5fb8e
DM		 3535 if (ret < 0)
3536 return ret;
3537
e2ac9628
HS		 3538 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3539 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
b2612722 3540 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
02b5fb8e
DM		 3541 if (ret < 0)
3542 return ret;
3543
b2612722 3544 ret = t4_config_glbl_rss(adap, adap->pf,
02b5fb8e 3545 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
b2e1a3f0
HS		 3546 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3547 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
02b5fb8e
DM		 3548 if (ret < 0)
3549 return ret;
3550
b2612722 3551 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
4b8e27a8
HS		 3552 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3553 FW_CMD_CAP_PF);
02b5fb8e
DM		 3554 if (ret < 0)
3555 return ret;
3556
3557 t4_sge_init(adap);
3558
02b5fb8e 3559 /* tweak some settings */
837e4a42 3560 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
0d804338 3561 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
837e4a42
HS		 3562 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3563 v = t4_read_reg(adap, TP_PIO_DATA_A);
3564 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
060e0c75 3565
dca4faeb
VP		 3566 /* first 4 Tx modulation queues point to consecutive Tx channels */
3567 adap->params.tp.tx_modq_map = 0xE4;
0d804338
HS		 3568 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3569 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
dca4faeb
VP		 3570
3571 /* associate each Tx modulation queue with consecutive Tx channels */
3572 v = 0x84218421;
837e4a42 3573 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3574 &v, 1, TP_TX_SCHED_HDR_A);
837e4a42 3575 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3576 &v, 1, TP_TX_SCHED_FIFO_A);
837e4a42 3577 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3578 &v, 1, TP_TX_SCHED_PCMD_A);
dca4faeb
VP		 3579
3580#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3581 if (is_offload(adap)) {
0d804338
HS		 3582 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3583 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3584 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3585 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3586 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3587 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3588 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3589 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3590 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3591 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
dca4faeb
VP		 3592 }
3593
060e0c75 3594 /* get basic stuff going */
b2612722 3595 return t4_early_init(adap, adap->pf);
02b5fb8e
DM		 3596}
3597
b8ff05a9
DM		 3598/*
3599 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3600 */
3601#define MAX_ATIDS 8192U
3602
636f9d37
VP		 3603/*
3604 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3605 *
3606 * If the firmware we're dealing with has Configuration File support, then
3607 * we use that to perform all configuration
3608 */
3609
3610/*
3611 * Tweak configuration based on module parameters, etc. Most of these have
3612 * defaults assigned to them by Firmware Configuration Files (if we're using
3613 * them) but need to be explicitly set if we're using hard-coded
3614 * initialization. But even in the case of using Firmware Configuration
3615 * Files, we'd like to expose the ability to change these via module
3616 * parameters so these are essentially common tweaks/settings for
3617 * Configuration Files and hard-coded initialization ...
3618 */
3619static int adap_init0_tweaks(struct adapter *adapter)
3620{
3621 /*
3622 * Fix up various Host-Dependent Parameters like Page Size, Cache
3623 * Line Size, etc. The firmware default is for a 4KB Page Size and
3624 * 64B Cache Line Size ...
3625 */
3626 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3627
3628 /*
3629 * Process module parameters which affect early initialization.
3630 */
3631 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3632 dev_err(&adapter->pdev->dev,
3633 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3634 rx_dma_offset);
3635 rx_dma_offset = 2;
3636 }
f612b815
HS		 3637 t4_set_reg_field(adapter, SGE_CONTROL_A,
3638 PKTSHIFT_V(PKTSHIFT_M),
3639 PKTSHIFT_V(rx_dma_offset));
636f9d37
VP		 3640
3641 /*
3642 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3643 * adds the pseudo header itself.
3644 */
837e4a42
HS		 3645 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3646 CSUM_HAS_PSEUDO_HDR_F, 0);
636f9d37
VP		 3647
3648 return 0;
3649}
3650
01b69614
HS		 3651/* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3652 * unto themselves and they contain their own firmware to perform their
3653 * tasks ...
3654 */
3655static int phy_aq1202_version(const u8 *phy_fw_data,
3656 size_t phy_fw_size)
3657{
3658 int offset;
3659
3660 /* At offset 0x8 you're looking for the primary image's
3661 * starting offset which is 3 Bytes wide
3662 *
3663 * At offset 0xa of the primary image, you look for the offset
3664 * of the DRAM segment which is 3 Bytes wide.
3665 *
3666 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3667 * wide
3668 */
3669 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3670 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3671 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3672
3673 offset = le24(phy_fw_data + 0x8) << 12;
3674 offset = le24(phy_fw_data + offset + 0xa);
3675 return be16(phy_fw_data + offset + 0x27e);
3676
3677 #undef be16
3678 #undef le16
3679 #undef le24
3680}
3681
3682static struct info_10gbt_phy_fw {
3683 unsigned int phy_fw_id; /* PCI Device ID */
3684 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3685 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3686 int phy_flash; /* Has FLASH for PHY Firmware */
3687} phy_info_array[] = {
3688 {
3689 PHY_AQ1202_DEVICEID,
3690 PHY_AQ1202_FIRMWARE,
3691 phy_aq1202_version,
3692 1,
3693 },
3694 {
3695 PHY_BCM84834_DEVICEID,
3696 PHY_BCM84834_FIRMWARE,
3697 NULL,
3698 0,
3699 },
3700 { 0, NULL, NULL },
3701};
3702
3703static struct info_10gbt_phy_fw *find_phy_info(int devid)
3704{
3705 int i;
3706
3707 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3708 if (phy_info_array[i].phy_fw_id == devid)
3709 return &phy_info_array[i];
3710 }
3711 return NULL;
3712}
3713
3714/* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3715 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3716 * we return a negative error number. If we transfer new firmware we return 1
3717 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3718 */
3719static int adap_init0_phy(struct adapter *adap)
3720{
3721 const struct firmware *phyf;
3722 int ret;
3723 struct info_10gbt_phy_fw *phy_info;
3724
3725 /* Use the device ID to determine which PHY file to flash.
3726 */
3727 phy_info = find_phy_info(adap->pdev->device);
3728 if (!phy_info) {
3729 dev_warn(adap->pdev_dev,
3730 "No PHY Firmware file found for this PHY\n");
3731 return -EOPNOTSUPP;
3732 }
3733
3734 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3735 * use that. The adapter firmware provides us with a memory buffer
3736 * where we can load a PHY firmware file from the host if we want to
3737 * override the PHY firmware File in flash.
3738 */
3739 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3740 adap->pdev_dev);
3741 if (ret < 0) {
3742 /* For adapters without FLASH attached to PHY for their
3743 * firmware, it's obviously a fatal error if we can't get the
3744 * firmware to the adapter. For adapters with PHY firmware
3745 * FLASH storage, it's worth a warning if we can't find the
3746 * PHY Firmware but we'll neuter the error ...
3747 */
3748 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3749 "/lib/firmware/%s, error %d\n",
3750 phy_info->phy_fw_file, -ret);
3751 if (phy_info->phy_flash) {
3752 int cur_phy_fw_ver = 0;
3753
3754 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3755 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3756 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3757 ret = 0;
3758 }
3759
3760 return ret;
3761 }
3762
3763 /* Load PHY Firmware onto adapter.
3764 */
3765 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3766 phy_info->phy_fw_version,
3767 (u8 *)phyf->data, phyf->size);
3768 if (ret < 0)
3769 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3770 -ret);
3771 else if (ret > 0) {
3772 int new_phy_fw_ver = 0;
3773
3774 if (phy_info->phy_fw_version)
3775 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3776 phyf->size);
3777 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3778 "Firmware /lib/firmware/%s, version %#x\n",
3779 phy_info->phy_fw_file, new_phy_fw_ver);
3780 }
3781
3782 release_firmware(phyf);
3783
3784 return ret;
3785}
3786
636f9d37
VP		 3787/*
3788 * Attempt to initialize the adapter via a Firmware Configuration File.
3789 */
3790static int adap_init0_config(struct adapter *adapter, int reset)
3791{
3792 struct fw_caps_config_cmd caps_cmd;
3793 const struct firmware *cf;
3794 unsigned long mtype = 0, maddr = 0;
3795 u32 finiver, finicsum, cfcsum;
16e47624
HS		 3796 int ret;
3797 int config_issued = 0;
0a57a536 3798 char *fw_config_file, fw_config_file_path[256];
16e47624 3799 char *config_name = NULL;
636f9d37
VP		 3800
3801 /*
3802 * Reset device if necessary.
3803 */
3804 if (reset) {
3805 ret = t4_fw_reset(adapter, adapter->mbox,
0d804338 3806 PIORSTMODE_F | PIORST_F);
636f9d37
VP		 3807 if (ret < 0)
3808 goto bye;
3809 }
3810
01b69614
HS		 3811 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3812 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3813 * to be performed after any global adapter RESET above since some
3814 * PHYs only have local RAM copies of the PHY firmware.
3815 */
3816 if (is_10gbt_device(adapter->pdev->device)) {
3817 ret = adap_init0_phy(adapter);
3818 if (ret < 0)
3819 goto bye;
3820 }
636f9d37
VP		 3821 /*
3822 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3823 * then use that. Otherwise, use the configuration file stored
3824 * in the adapter flash ...
3825 */
d14807dd 3826 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 3827 case CHELSIO_T4:
16e47624 3828 fw_config_file = FW4_CFNAME;
0a57a536
SR		 3829 break;
3830 case CHELSIO_T5:
3831 fw_config_file = FW5_CFNAME;
3832 break;
3ccc6cf7
HS		 3833 case CHELSIO_T6:
3834 fw_config_file = FW6_CFNAME;
3835 break;
0a57a536
SR		 3836 default:
3837 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3838 adapter->pdev->device);
3839 ret = -EINVAL;
3840 goto bye;
3841 }
3842
3843 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 3844 if (ret < 0) {
16e47624 3845 config_name = "On FLASH";
636f9d37
VP		 3846 mtype = FW_MEMTYPE_CF_FLASH;
3847 maddr = t4_flash_cfg_addr(adapter);
3848 } else {
3849 u32 params[7], val[7];
3850
16e47624
HS		 3851 sprintf(fw_config_file_path,
3852 "/lib/firmware/%s", fw_config_file);
3853 config_name = fw_config_file_path;
3854
636f9d37
VP		 3855 if (cf->size >= FLASH_CFG_MAX_SIZE)
3856 ret = -ENOMEM;
3857 else {
5167865a
HS		 3858 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3859 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
636f9d37 3860 ret = t4_query_params(adapter, adapter->mbox,
b2612722 3861 adapter->pf, 0, 1, params, val);
636f9d37
VP		 3862 if (ret == 0) {
3863 /*
fc5ab020 3864 * For t4_memory_rw() below addresses and
636f9d37
VP		 3865 * sizes have to be in terms of multiples of 4
3866 * bytes. So, if the Configuration File isn't
3867 * a multiple of 4 bytes in length we'll have
3868 * to write that out separately since we can't
3869 * guarantee that the bytes following the
3870 * residual byte in the buffer returned by
3871 * request_firmware() are zeroed out ...
3872 */
3873 size_t resid = cf->size & 0x3;
3874 size_t size = cf->size & ~0x3;
3875 __be32 *data = (__be32 *)cf->data;
3876
5167865a
HS		 3877 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3878 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
636f9d37 3879
fc5ab020
HS		 3880 spin_lock(&adapter->win0_lock);
3881 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3882 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 3883 if (ret == 0 && resid != 0) {
3884 union {
3885 __be32 word;
3886 char buf[4];
3887 } last;
3888 int i;
3889
3890 last.word = data[size >> 2];
3891 for (i = resid; i < 4; i++)
3892 last.buf[i] = 0;
fc5ab020
HS		 3893 ret = t4_memory_rw(adapter, 0, mtype,
3894 maddr + size,
3895 4, &last.word,
3896 T4_MEMORY_WRITE);
636f9d37 3897 }
fc5ab020 3898 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 3899 }
3900 }
3901
3902 release_firmware(cf);
3903 if (ret)
3904 goto bye;
3905 }
3906
3907 /*
3908 * Issue a Capability Configuration command to the firmware to get it
3909 * to parse the Configuration File. We don't use t4_fw_config_file()
3910 * because we want the ability to modify various features after we've
3911 * processed the configuration file ...
3912 */
3913 memset(&caps_cmd, 0, sizeof(caps_cmd));
3914 caps_cmd.op_to_write =
e2ac9628
HS		 3915 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3916 FW_CMD_REQUEST_F |
3917 FW_CMD_READ_F);
ce91a923 3918 caps_cmd.cfvalid_to_len16 =
5167865a
HS		 3919 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3920 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3921 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
636f9d37
VP		 3922 FW_LEN16(caps_cmd));
3923 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3924 &caps_cmd);
16e47624
HS		 3925
3926 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3927 * Configuration File in FLASH), our last gasp effort is to use the
3928 * Firmware Configuration File which is embedded in the firmware. A
3929 * very few early versions of the firmware didn't have one embedded
3930 * but we can ignore those.
3931 */
3932 if (ret == -ENOENT) {
3933 memset(&caps_cmd, 0, sizeof(caps_cmd));
3934 caps_cmd.op_to_write =
e2ac9628
HS		 3935 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3936 FW_CMD_REQUEST_F |
3937 FW_CMD_READ_F);
16e47624
HS		 3938 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3939 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3940 sizeof(caps_cmd), &caps_cmd);
3941 config_name = "Firmware Default";
3942 }
3943
3944 config_issued = 1;
636f9d37
VP		 3945 if (ret < 0)
3946 goto bye;
3947
3948 finiver = ntohl(caps_cmd.finiver);
3949 finicsum = ntohl(caps_cmd.finicsum);
3950 cfcsum = ntohl(caps_cmd.cfcsum);
3951 if (finicsum != cfcsum)
3952 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3953 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3954 finicsum, cfcsum);
3955
636f9d37
VP		 3956 /*
3957 * And now tell the firmware to use the configuration we just loaded.
3958 */
3959 caps_cmd.op_to_write =
e2ac9628
HS		 3960 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3961 FW_CMD_REQUEST_F |
3962 FW_CMD_WRITE_F);
ce91a923 3963 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3964 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3965 NULL);
3966 if (ret < 0)
3967 goto bye;
3968
3969 /*
3970 * Tweak configuration based on system architecture, module
3971 * parameters, etc.
3972 */
3973 ret = adap_init0_tweaks(adapter);
3974 if (ret < 0)
3975 goto bye;
3976
8b4e6b3c
AV		 3977 /* We will proceed even if HMA init fails. */
3978 ret = adap_config_hma(adapter);
3979 if (ret)
3980 dev_err(adapter->pdev_dev,
3981 "HMA configuration failed with error %d\n", ret);
3982
636f9d37
VP		 3983 /*
3984 * And finally tell the firmware to initialize itself using the
3985 * parameters from the Configuration File.
3986 */
3987 ret = t4_fw_initialize(adapter, adapter->mbox);
3988 if (ret < 0)
3989 goto bye;
3990
06640310
HS		 3991 /* Emit Firmware Configuration File information and return
3992 * successfully.
636f9d37 3993 */
636f9d37 3994 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 3995 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3996 config_name, finiver, cfcsum);
636f9d37
VP		 3997 return 0;
3998
3999 /*
4000 * Something bad happened. Return the error ... (If the "error"
4001 * is that there's no Configuration File on the adapter we don't
4002 * want to issue a warning since this is fairly common.)
4003 */
4004bye:
16e47624
HS		 4005 if (config_issued && ret != -ENOENT)
4006 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4007 config_name, -ret);
636f9d37
VP		 4008 return ret;
4009}
4010
16e47624
HS		 4011static struct fw_info fw_info_array[] = {
4012 {
4013 .chip = CHELSIO_T4,
4014 .fs_name = FW4_CFNAME,
4015 .fw_mod_name = FW4_FNAME,
4016 .fw_hdr = {
4017 .chip = FW_HDR_CHIP_T4,
4018 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4019 .intfver_nic = FW_INTFVER(T4, NIC),
4020 .intfver_vnic = FW_INTFVER(T4, VNIC),
4021 .intfver_ri = FW_INTFVER(T4, RI),
4022 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4023 .intfver_fcoe = FW_INTFVER(T4, FCOE),
4024 },
4025 }, {
4026 .chip = CHELSIO_T5,
4027 .fs_name = FW5_CFNAME,
4028 .fw_mod_name = FW5_FNAME,
4029 .fw_hdr = {
4030 .chip = FW_HDR_CHIP_T5,
4031 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4032 .intfver_nic = FW_INTFVER(T5, NIC),
4033 .intfver_vnic = FW_INTFVER(T5, VNIC),
4034 .intfver_ri = FW_INTFVER(T5, RI),
4035 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4036 .intfver_fcoe = FW_INTFVER(T5, FCOE),
4037 },
3ccc6cf7
HS		 4038 }, {
4039 .chip = CHELSIO_T6,
4040 .fs_name = FW6_CFNAME,
4041 .fw_mod_name = FW6_FNAME,
4042 .fw_hdr = {
4043 .chip = FW_HDR_CHIP_T6,
4044 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4045 .intfver_nic = FW_INTFVER(T6, NIC),
4046 .intfver_vnic = FW_INTFVER(T6, VNIC),
4047 .intfver_ofld = FW_INTFVER(T6, OFLD),
4048 .intfver_ri = FW_INTFVER(T6, RI),
4049 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4050 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4051 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4052 .intfver_fcoe = FW_INTFVER(T6, FCOE),
4053 },
16e47624 4054 }
3ccc6cf7 4055
16e47624
HS		 4056};
4057
4058static struct fw_info *find_fw_info(int chip)
4059{
4060 int i;
4061
4062 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4063 if (fw_info_array[i].chip == chip)
4064 return &fw_info_array[i];
4065 }
4066 return NULL;
4067}
4068
b8ff05a9
DM		 4069/*
4070 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4071 */
4072static int adap_init0(struct adapter *adap)
4073{
4074 int ret;
4075 u32 v, port_vec;
4076 enum dev_state state;
4077 u32 params[7], val[7];
9a4da2cd 4078 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 4079 int reset = 1;
b8ff05a9 4080
ae469b68
HS		 4081 /* Grab Firmware Device Log parameters as early as possible so we have
4082 * access to it for debugging, etc.
4083 */
4084 ret = t4_init_devlog_params(adap);
4085 if (ret < 0)
4086 return ret;
4087
666224d4 4088 /* Contact FW, advertising Master capability */
c5a8c0f3
HS		 4089 ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4090 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
b8ff05a9
DM		 4091 if (ret < 0) {
4092 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4093 ret);
4094 return ret;
4095 }
636f9d37
VP		 4096 if (ret == adap->mbox)
4097 adap->flags |= MASTER_PF;
b8ff05a9 4098
636f9d37
VP		 4099 /*
4100 * If we're the Master PF Driver and the device is uninitialized,
4101 * then let's consider upgrading the firmware ... (We always want
4102 * to check the firmware version number in order to A. get it for
4103 * later reporting and B. to warn if the currently loaded firmware
4104 * is excessively mismatched relative to the driver.)
4105 */
0de72738 4106
760446f9 4107 t4_get_version_info(adap);
a69265e9
HS		 4108 ret = t4_check_fw_version(adap);
4109 /* If firmware is too old (not supported by driver) force an update. */
21d11bd6 4110 if (ret)
a69265e9 4111 state = DEV_STATE_UNINIT;
636f9d37 4112 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 4113 struct fw_info *fw_info;
4114 struct fw_hdr *card_fw;
4115 const struct firmware *fw;
4116 const u8 *fw_data = NULL;
4117 unsigned int fw_size = 0;
4118
4119 /* This is the firmware whose headers the driver was compiled
4120 * against
4121 */
4122 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4123 if (fw_info == NULL) {
4124 dev_err(adap->pdev_dev,
4125 "unable to get firmware info for chip %d.\n",
4126 CHELSIO_CHIP_VERSION(adap->params.chip));
4127 return -EINVAL;
636f9d37 4128 }
16e47624
HS		 4129
4130 /* allocate memory to read the header of the firmware on the
4131 * card
4132 */
752ade68 4133 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
16e47624
HS		 4134
4135 /* Get FW from from /lib/firmware/ */
4136 ret = request_firmware(&fw, fw_info->fw_mod_name,
4137 adap->pdev_dev);
4138 if (ret < 0) {
4139 dev_err(adap->pdev_dev,
4140 "unable to load firmware image %s, error %d\n",
4141 fw_info->fw_mod_name, ret);
4142 } else {
4143 fw_data = fw->data;
4144 fw_size = fw->size;
4145 }
4146
4147 /* upgrade FW logic */
4148 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4149 state, &reset);
4150
4151 /* Cleaning up */
0b5b6bee 4152 release_firmware(fw);
752ade68 4153 kvfree(card_fw);
16e47624 4154
636f9d37 4155 if (ret < 0)
16e47624 4156 goto bye;
636f9d37 4157 }
b8ff05a9 4158
636f9d37
VP		 4159 /*
4160 * Grab VPD parameters. This should be done after we establish a
4161 * connection to the firmware since some of the VPD parameters
4162 * (notably the Core Clock frequency) are retrieved via requests to
4163 * the firmware. On the other hand, we need these fairly early on
4164 * so we do this right after getting ahold of the firmware.
4165 */
098ef6c2 4166 ret = t4_get_vpd_params(adap, &adap->params.vpd);
a0881cab
DM		 4167 if (ret < 0)
4168 goto bye;
a0881cab 4169
636f9d37 4170 /*
13ee15d3
VP		 4171 * Find out what ports are available to us. Note that we need to do
4172 * this before calling adap_init0_no_config() since it needs nports
4173 * and portvec ...
636f9d37
VP		 4174 */
4175 v =
5167865a
HS		 4176 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4177 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
b2612722 4178 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
a0881cab
DM		 4179 if (ret < 0)
4180 goto bye;
4181
636f9d37
VP		 4182 adap->params.nports = hweight32(port_vec);
4183 adap->params.portvec = port_vec;
4184
06640310
HS		 4185 /* If the firmware is initialized already, emit a simply note to that
4186 * effect. Otherwise, it's time to try initializing the adapter.
636f9d37
VP		 4187 */
4188 if (state == DEV_STATE_INIT) {
8b4e6b3c
AV		 4189 ret = adap_config_hma(adap);
4190 if (ret)
4191 dev_err(adap->pdev_dev,
4192 "HMA configuration failed with error %d\n",
4193 ret);
636f9d37
VP		 4194 dev_info(adap->pdev_dev, "Coming up as %s: "\
4195 "Adapter already initialized\n",
4196 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
636f9d37
VP		 4197 } else {
4198 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4199 "Initializing adapter\n");
06640310
HS		 4200
4201 /* Find out whether we're dealing with a version of the
4202 * firmware which has configuration file support.
636f9d37 4203 */
06640310
HS		 4204 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4205 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
b2612722 4206 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
06640310 4207 params, val);
13ee15d3 4208
06640310
HS		 4209 /* If the firmware doesn't support Configuration Files,
4210 * return an error.
4211 */
4212 if (ret < 0) {
4213 dev_err(adap->pdev_dev, "firmware doesn't support "
4214 "Firmware Configuration Files\n");
4215 goto bye;
4216 }
4217
4218 /* The firmware provides us with a memory buffer where we can
4219 * load a Configuration File from the host if we want to
4220 * override the Configuration File in flash.
4221 */
4222 ret = adap_init0_config(adap, reset);
4223 if (ret == -ENOENT) {
4224 dev_err(adap->pdev_dev, "no Configuration File "
4225 "present on adapter.\n");
4226 goto bye;
636f9d37
VP		 4227 }
4228 if (ret < 0) {
06640310
HS		 4229 dev_err(adap->pdev_dev, "could not initialize "
4230 "adapter, error %d\n", -ret);
636f9d37
VP		 4231 goto bye;
4232 }
4233 }
4234
06640310
HS		 4235 /* Give the SGE code a chance to pull in anything that it needs ...
4236 * Note that this must be called after we retrieve our VPD parameters
4237 * in order to know how to convert core ticks to seconds, etc.
636f9d37 4238 */
06640310
HS		 4239 ret = t4_sge_init(adap);
4240 if (ret < 0)
4241 goto bye;
636f9d37 4242
9a4da2cd
VP		 4243 if (is_bypass_device(adap->pdev->device))
4244 adap->params.bypass = 1;
4245
636f9d37
VP		 4246 /*
4247 * Grab some of our basic fundamental operating parameters.
4248 */
4249#define FW_PARAM_DEV(param) \
5167865a
HS		 4250 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
4251 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
636f9d37 4252
b8ff05a9 4253#define FW_PARAM_PFVF(param) \
5167865a
HS		 4254 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
4255 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
4256 FW_PARAMS_PARAM_Y_V(0) | \
4257 FW_PARAMS_PARAM_Z_V(0)
b8ff05a9 4258
636f9d37 4259 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 4260 params[1] = FW_PARAM_PFVF(L2T_START);
4261 params[2] = FW_PARAM_PFVF(L2T_END);
4262 params[3] = FW_PARAM_PFVF(FILTER_START);
4263 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 4264 params[5] = FW_PARAM_PFVF(IQFLINT_START);
b2612722 4265 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
b8ff05a9
DM		 4266 if (ret < 0)
4267 goto bye;
636f9d37
VP		 4268 adap->sge.egr_start = val[0];
4269 adap->l2t_start = val[1];
4270 adap->l2t_end = val[2];
b8ff05a9
DM		 4271 adap->tids.ftid_base = val[3];
4272 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 4273 adap->sge.ingr_start = val[5];
b8ff05a9 4274
4b8e27a8
HS		 4275 /* qids (ingress/egress) returned from firmware can be anywhere
4276 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4277 * Hence driver needs to allocate memory for this range to
4278 * store the queue info. Get the highest IQFLINT/EQ index returned
4279 * in FW_EQ_*_CMD.alloc command.
4280 */
4281 params[0] = FW_PARAM_PFVF(EQ_END);
4282 params[1] = FW_PARAM_PFVF(IQFLINT_END);
b2612722 4283 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4b8e27a8
HS		 4284 if (ret < 0)
4285 goto bye;
4286 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4287 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4288
4289 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4290 sizeof(*adap->sge.egr_map), GFP_KERNEL);
4291 if (!adap->sge.egr_map) {
4292 ret = -ENOMEM;
4293 goto bye;
4294 }
4295
4296 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4297 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4298 if (!adap->sge.ingr_map) {
4299 ret = -ENOMEM;
4300 goto bye;
4301 }
4302
4303 /* Allocate the memory for the vaious egress queue bitmaps
5b377d11 4304 * ie starving_fl, txq_maperr and blocked_fl.
4b8e27a8
HS		 4305 */
4306 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4307 sizeof(long), GFP_KERNEL);
4308 if (!adap->sge.starving_fl) {
4309 ret = -ENOMEM;
4310 goto bye;
4311 }
4312
4313 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4314 sizeof(long), GFP_KERNEL);
4315 if (!adap->sge.txq_maperr) {
4316 ret = -ENOMEM;
4317 goto bye;
4318 }
4319
5b377d11
HS		 4320#ifdef CONFIG_DEBUG_FS
4321 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4322 sizeof(long), GFP_KERNEL);
4323 if (!adap->sge.blocked_fl) {
4324 ret = -ENOMEM;
4325 goto bye;
4326 }
4327#endif
4328
b5a02f50
AB		 4329 params[0] = FW_PARAM_PFVF(CLIP_START);
4330 params[1] = FW_PARAM_PFVF(CLIP_END);
b2612722 4331 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
b5a02f50
AB		 4332 if (ret < 0)
4333 goto bye;
4334 adap->clipt_start = val[0];
4335 adap->clipt_end = val[1];
4336
b72a32da
RL		 4337 /* We don't yet have a PARAMs calls to retrieve the number of Traffic
4338 * Classes supported by the hardware/firmware so we hard code it here
4339 * for now.
4340 */
4341 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4342
636f9d37
VP		 4343 /* query params related to active filter region */
4344 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4345 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
b2612722 4346 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
636f9d37
VP		 4347 /* If Active filter size is set we enable establishing
4348 * offload connection through firmware work request
4349 */
4350 if ((val[0] != val[1]) && (ret >= 0)) {
4351 adap->flags |= FW_OFLD_CONN;
4352 adap->tids.aftid_base = val[0];
4353 adap->tids.aftid_end = val[1];
4354 }
4355
b407a4a9
VP		 4356 /* If we're running on newer firmware, let it know that we're
4357 * prepared to deal with encapsulated CPL messages. Older
4358 * firmware won't understand this and we'll just get
4359 * unencapsulated messages ...
4360 */
4361 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4362 val[0] = 1;
b2612722 4363 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
b407a4a9 4364
1ac0f095
KS		 4365 /*
4366 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4367 * capability. Earlier versions of the firmware didn't have the
4368 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4369 * permission to use ULPTX MEMWRITE DSGL.
4370 */
4371 if (is_t4(adap->params.chip)) {
4372 adap->params.ulptx_memwrite_dsgl = false;
4373 } else {
4374 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
b2612722 4375 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1ac0f095
KS		 4376 1, params, val);
4377 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4378 }
4379
086de575
SW		 4380 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4381 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4382 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4383 1, params, val);
4384 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4385
0ff90994
KS		 4386 /* See if FW supports FW_FILTER2 work request */
4387 if (is_t4(adap->params.chip)) {
4388 adap->params.filter2_wr_support = 0;
4389 } else {
4390 params[0] = FW_PARAM_DEV(FILTER2_WR);
4391 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4392 1, params, val);
4393 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4394 }
4395
636f9d37
VP		 4396 /*
4397 * Get device capabilities so we can determine what resources we need
4398 * to manage.
4399 */
4400 memset(&caps_cmd, 0, sizeof(caps_cmd));
e2ac9628
HS		 4401 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4402 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 4403 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 4404 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4405 &caps_cmd);
4406 if (ret < 0)
4407 goto bye;
4408
5c31254e
KS		 4409 if (caps_cmd.ofldcaps ||
4410 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) {
b8ff05a9
DM		 4411 /* query offload-related parameters */
4412 params[0] = FW_PARAM_DEV(NTID);
4413 params[1] = FW_PARAM_PFVF(SERVER_START);
4414 params[2] = FW_PARAM_PFVF(SERVER_END);
4415 params[3] = FW_PARAM_PFVF(TDDP_START);
4416 params[4] = FW_PARAM_PFVF(TDDP_END);
4417 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
b2612722 4418 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 4419 params, val);
b8ff05a9
DM		 4420 if (ret < 0)
4421 goto bye;
4422 adap->tids.ntids = val[0];
4423 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4424 adap->tids.stid_base = val[1];
4425 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37 4426 /*
dbedd44e 4427 * Setup server filter region. Divide the available filter
636f9d37
VP		 4428 * region into two parts. Regular filters get 1/3rd and server
4429 * filters get 2/3rd part. This is only enabled if workarond
4430 * path is enabled.
4431 * 1. For regular filters.
4432 * 2. Server filter: This are special filters which are used
4433 * to redirect SYN packets to offload queue.
4434 */
4435 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
4436 adap->tids.sftid_base = adap->tids.ftid_base +
4437 DIV_ROUND_UP(adap->tids.nftids, 3);
4438 adap->tids.nsftids = adap->tids.nftids -
4439 DIV_ROUND_UP(adap->tids.nftids, 3);
4440 adap->tids.nftids = adap->tids.sftid_base -
4441 adap->tids.ftid_base;
4442 }
b8ff05a9
DM		 4443 adap->vres.ddp.start = val[3];
4444 adap->vres.ddp.size = val[4] - val[3] + 1;
4445 adap->params.ofldq_wr_cred = val[5];
636f9d37 4446
5c31254e
KS		 4447 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4448 if (init_hash_filter(adap) < 0)
4449 goto bye;
4450 } else {
4451 adap->params.offload = 1;
4452 adap->num_ofld_uld += 1;
4453 }
b8ff05a9 4454 }
636f9d37 4455 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 4456 params[0] = FW_PARAM_PFVF(STAG_START);
4457 params[1] = FW_PARAM_PFVF(STAG_END);
4458 params[2] = FW_PARAM_PFVF(RQ_START);
4459 params[3] = FW_PARAM_PFVF(RQ_END);
4460 params[4] = FW_PARAM_PFVF(PBL_START);
4461 params[5] = FW_PARAM_PFVF(PBL_END);
b2612722 4462 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 4463 params, val);
b8ff05a9
DM		 4464 if (ret < 0)
4465 goto bye;
4466 adap->vres.stag.start = val[0];
4467 adap->vres.stag.size = val[1] - val[0] + 1;
4468 adap->vres.rq.start = val[2];
4469 adap->vres.rq.size = val[3] - val[2] + 1;
4470 adap->vres.pbl.start = val[4];
4471 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab 4472
c68644ef
RR		 4473 params[0] = FW_PARAM_PFVF(SRQ_START);
4474 params[1] = FW_PARAM_PFVF(SRQ_END);
4475 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4476 params, val);
4477 if (!ret) {
4478 adap->vres.srq.start = val[0];
4479 adap->vres.srq.size = val[1] - val[0] + 1;
4480 }
4481 if (adap->vres.srq.size) {
4482 adap->srq = t4_init_srq(adap->vres.srq.size);
4483 if (!adap->srq)
4484 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4485 }
4486
a0881cab
DM		 4487 params[0] = FW_PARAM_PFVF(SQRQ_START);
4488 params[1] = FW_PARAM_PFVF(SQRQ_END);
4489 params[2] = FW_PARAM_PFVF(CQ_START);
4490 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 4491 params[4] = FW_PARAM_PFVF(OCQ_START);
4492 params[5] = FW_PARAM_PFVF(OCQ_END);
b2612722 4493 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
5c937dd3 4494 val);
a0881cab
DM		 4495 if (ret < 0)
4496 goto bye;
4497 adap->vres.qp.start = val[0];
4498 adap->vres.qp.size = val[1] - val[0] + 1;
4499 adap->vres.cq.start = val[2];
4500 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 4501 adap->vres.ocq.start = val[4];
4502 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS		 4503
4504 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4505 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
b2612722 4506 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
5c937dd3 4507 val);
4c2c5763
HS		 4508 if (ret < 0) {
4509 adap->params.max_ordird_qp = 8;
4510 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4511 ret = 0;
4512 } else {
4513 adap->params.max_ordird_qp = val[0];
4514 adap->params.max_ird_adapter = val[1];
4515 }
4516 dev_info(adap->pdev_dev,
4517 "max_ordird_qp %d max_ird_adapter %d\n",
4518 adap->params.max_ordird_qp,
4519 adap->params.max_ird_adapter);
43db9296
RR		 4520
4521 /* Enable write_with_immediate if FW supports it */
4522 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
4523 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4524 val);
4525 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
f3910c62
RR		 4526
4527 /* Enable write_cmpl if FW supports it */
4528 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
4529 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4530 val);
4531 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
0fbc81b3 4532 adap->num_ofld_uld += 2;
b8ff05a9 4533 }
636f9d37 4534 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 4535 params[0] = FW_PARAM_PFVF(ISCSI_START);
4536 params[1] = FW_PARAM_PFVF(ISCSI_END);
b2612722 4537 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
636f9d37 4538 params, val);
b8ff05a9
DM		 4539 if (ret < 0)
4540 goto bye;
4541 adap->vres.iscsi.start = val[0];
4542 adap->vres.iscsi.size = val[1] - val[0] + 1;
0fbc81b3
HS		 4543 /* LIO target and cxgb4i initiaitor */
4544 adap->num_ofld_uld += 2;
b8ff05a9 4545 }
94cdb8bb
HS		 4546 if (caps_cmd.cryptocaps) {
4547 /* Should query params here...TODO */
72a56ca9
HJ		 4548 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
4549 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4550 params, val);
4551 if (ret < 0) {
4552 if (ret != -EINVAL)
4553 goto bye;
4554 } else {
4555 adap->vres.ncrypto_fc = val[0];
4556 }
a6ec572b 4557 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
94cdb8bb
HS		 4558 adap->num_uld += 1;
4559 }
b8ff05a9
DM		 4560#undef FW_PARAM_PFVF
4561#undef FW_PARAM_DEV
4562
92e7ae71
HS		 4563 /* The MTU/MSS Table is initialized by now, so load their values. If
4564 * we're initializing the adapter, then we'll make any modifications
4565 * we want to the MTU/MSS Table and also initialize the congestion
4566 * parameters.
636f9d37 4567 */
b8ff05a9 4568 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 4569 if (state != DEV_STATE_INIT) {
4570 int i;
4571
4572 /* The default MTU Table contains values 1492 and 1500.
4573 * However, for TCP, it's better to have two values which are
4574 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4575 * This allows us to have a TCP Data Payload which is a
4576 * multiple of 8 regardless of what combination of TCP Options
4577 * are in use (always a multiple of 4 bytes) which is
4578 * important for performance reasons. For instance, if no
4579 * options are in use, then we have a 20-byte IP header and a
4580 * 20-byte TCP header. In this case, a 1500-byte MSS would
4581 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4582 * which is not a multiple of 8. So using an MSS of 1488 in
4583 * this case results in a TCP Data Payload of 1448 bytes which
4584 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4585 * Stamps have been negotiated, then an MTU of 1500 bytes
4586 * results in a TCP Data Payload of 1448 bytes which, as
4587 * above, is a multiple of 8 bytes ...
4588 */
4589 for (i = 0; i < NMTUS; i++)
4590 if (adap->params.mtus[i] == 1492) {
4591 adap->params.mtus[i] = 1488;
4592 break;
4593 }
7ee9ff94 4594
92e7ae71
HS		 4595 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4596 adap->params.b_wnd);
4597 }
df64e4d3 4598 t4_init_sge_params(adap);
636f9d37 4599 adap->flags |= FW_OK;
5ccf9d04 4600 t4_init_tp_params(adap, true);
b8ff05a9
DM		 4601 return 0;
4602
4603 /*
636f9d37
VP		 4604 * Something bad happened. If a command timed out or failed with EIO
4605 * FW does not operate within its spec or something catastrophic
4606 * happened to HW/FW, stop issuing commands.
b8ff05a9 4607 */
636f9d37 4608bye:
8b4e6b3c 4609 adap_free_hma_mem(adap);
4b8e27a8
HS		 4610 kfree(adap->sge.egr_map);
4611 kfree(adap->sge.ingr_map);
4612 kfree(adap->sge.starving_fl);
4613 kfree(adap->sge.txq_maperr);
5b377d11
HS		 4614#ifdef CONFIG_DEBUG_FS
4615 kfree(adap->sge.blocked_fl);
4616#endif
636f9d37
VP		 4617 if (ret != -ETIMEDOUT && ret != -EIO)
4618 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 4619 return ret;
4620}
4621
204dc3c0
DM		 4622/* EEH callbacks */
4623
4624static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4625 pci_channel_state_t state)
4626{
4627 int i;
4628 struct adapter *adap = pci_get_drvdata(pdev);
4629
4630 if (!adap)
4631 goto out;
4632
4633 rtnl_lock();
4634 adap->flags &= ~FW_OK;
4635 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 4636 spin_lock(&adap->stats_lock);
204dc3c0
DM		 4637 for_each_port(adap, i) {
4638 struct net_device *dev = adap->port[i];
025d0973
GP		 4639 if (dev) {
4640 netif_device_detach(dev);
4641 netif_carrier_off(dev);
4642 }
204dc3c0 4643 }
9fe6cb58 4644 spin_unlock(&adap->stats_lock);
b37987e8 4645 disable_interrupts(adap);
204dc3c0
DM		 4646 if (adap->flags & FULL_INIT_DONE)
4647 cxgb_down(adap);
4648 rtnl_unlock();
144be3d9
GS		 4649 if ((adap->flags & DEV_ENABLED)) {
4650 pci_disable_device(pdev);
4651 adap->flags &= ~DEV_ENABLED;
4652 }
204dc3c0
DM		 4653out: return state == pci_channel_io_perm_failure ?
4654 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4655}
4656
4657static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4658{
4659 int i, ret;
4660 struct fw_caps_config_cmd c;
4661 struct adapter *adap = pci_get_drvdata(pdev);
4662
4663 if (!adap) {
4664 pci_restore_state(pdev);
4665 pci_save_state(pdev);
4666 return PCI_ERS_RESULT_RECOVERED;
4667 }
4668
144be3d9
GS		 4669 if (!(adap->flags & DEV_ENABLED)) {
4670 if (pci_enable_device(pdev)) {
4671 dev_err(&pdev->dev, "Cannot reenable PCI "
4672 "device after reset\n");
4673 return PCI_ERS_RESULT_DISCONNECT;
4674 }
4675 adap->flags |= DEV_ENABLED;
204dc3c0
DM		 4676 }
4677
4678 pci_set_master(pdev);
4679 pci_restore_state(pdev);
4680 pci_save_state(pdev);
4681 pci_cleanup_aer_uncorrect_error_status(pdev);
4682
8203b509 4683 if (t4_wait_dev_ready(adap->regs) < 0)
204dc3c0 4684 return PCI_ERS_RESULT_DISCONNECT;
b2612722 4685 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
204dc3c0
DM		 4686 return PCI_ERS_RESULT_DISCONNECT;
4687 adap->flags |= FW_OK;
4688 if (adap_init1(adap, &c))
4689 return PCI_ERS_RESULT_DISCONNECT;
4690
4691 for_each_port(adap, i) {
4692 struct port_info *p = adap2pinfo(adap, i);
4693
b2612722 4694 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
060e0c75 4695 NULL, NULL);
204dc3c0
DM		 4696 if (ret < 0)
4697 return PCI_ERS_RESULT_DISCONNECT;
4698 p->viid = ret;
4699 p->xact_addr_filt = -1;
4700 }
4701
4702 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4703 adap->params.b_wnd);
1ae970e0 4704 setup_memwin(adap);
204dc3c0
DM		 4705 if (cxgb_up(adap))
4706 return PCI_ERS_RESULT_DISCONNECT;
4707 return PCI_ERS_RESULT_RECOVERED;
4708}
4709
4710static void eeh_resume(struct pci_dev *pdev)
4711{
4712 int i;
4713 struct adapter *adap = pci_get_drvdata(pdev);
4714
4715 if (!adap)
4716 return;
4717
4718 rtnl_lock();
4719 for_each_port(adap, i) {
4720 struct net_device *dev = adap->port[i];
025d0973
GP		 4721 if (dev) {
4722 if (netif_running(dev)) {
4723 link_start(dev);
4724 cxgb_set_rxmode(dev);
4725 }
4726 netif_device_attach(dev);
204dc3c0 4727 }
204dc3c0
DM		 4728 }
4729 rtnl_unlock();
4730}
4731
3646f0e5 4732static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 4733 .error_detected = eeh_err_detected,
4734 .slot_reset = eeh_slot_reset,
4735 .resume = eeh_resume,
4736};
4737
9b86a8d1
HS		 4738/* Return true if the Link Configuration supports "High Speeds" (those greater
4739 * than 1Gb/s).
4740 */
57d8b764 4741static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 4742{
9b86a8d1
HS		 4743 unsigned int speeds, high_speeds;
4744
c3168cab
GG		 4745 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
4746 high_speeds = speeds &
4747 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
9b86a8d1
HS		 4748
4749 return high_speeds != 0;
b8ff05a9
DM		 4750}
4751
b8ff05a9
DM		 4752/*
4753 * Perform default configuration of DMA queues depending on the number and type
4754 * of ports we found and the number of available CPUs. Most settings can be
4755 * modified by the admin prior to actual use.
4756 */
91744948 4757static void cfg_queues(struct adapter *adap)
b8ff05a9
DM		 4758{
4759 struct sge *s = &adap->sge;
ab677ff4 4760 int i = 0, n10g = 0, qidx = 0;
688848b1
AB		 4761#ifndef CONFIG_CHELSIO_T4_DCB
4762 int q10g = 0;
4763#endif
b8ff05a9 4764
94cdb8bb
HS		 4765 /* Reduce memory usage in kdump environment, disable all offload.
4766 */
85eacf3f 4767 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
0fbc81b3 4768 adap->params.offload = 0;
94cdb8bb
HS		 4769 adap->params.crypto = 0;
4770 }
4771
ab677ff4 4772 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
688848b1
AB		 4773#ifdef CONFIG_CHELSIO_T4_DCB
4774 /* For Data Center Bridging support we need to be able to support up
4775 * to 8 Traffic Priorities; each of which will be assigned to its
4776 * own TX Queue in order to prevent Head-Of-Line Blocking.
4777 */
4778 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4779 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4780 MAX_ETH_QSETS, adap->params.nports * 8);
4781 BUG_ON(1);
4782 }
b8ff05a9 4783
688848b1
AB		 4784 for_each_port(adap, i) {
4785 struct port_info *pi = adap2pinfo(adap, i);
4786
4787 pi->first_qset = qidx;
85eacf3f 4788 pi->nqsets = is_kdump_kernel() ? 1 : 8;
688848b1
AB		 4789 qidx += pi->nqsets;
4790 }
4791#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4792 /*
4793 * We default to 1 queue per non-10G port and up to # of cores queues
4794 * per 10G port.
4795 */
4796 if (n10g)
4797 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 4798 if (q10g > netif_get_num_default_rss_queues())
4799 q10g = netif_get_num_default_rss_queues();
b8ff05a9 4800
85eacf3f
GG		 4801 if (is_kdump_kernel())
4802 q10g = 1;
4803
b8ff05a9
DM		 4804 for_each_port(adap, i) {
4805 struct port_info *pi = adap2pinfo(adap, i);
4806
4807 pi->first_qset = qidx;
57d8b764 4808 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 4809 qidx += pi->nqsets;
4810 }
688848b1 4811#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4812
4813 s->ethqsets = qidx;
4814 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4815
0fbc81b3 4816 if (is_uld(adap)) {
b8ff05a9
DM		 4817 /*
4818 * For offload we use 1 queue/channel if all ports are up to 1G,
4819 * otherwise we divide all available queues amongst the channels
4820 * capped by the number of available cores.
4821 */
4822 if (n10g) {
a56177e1 4823 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
0fbc81b3
HS		 4824 s->ofldqsets = roundup(i, adap->params.nports);
4825 } else {
4826 s->ofldqsets = adap->params.nports;
4827 }
b8ff05a9
DM		 4828 }
4829
4830 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4831 struct sge_eth_rxq *r = &s->ethrxq[i];
4832
c887ad0e 4833 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 4834 r->fl.size = 72;
4835 }
4836
4837 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4838 s->ethtxq[i].q.size = 1024;
4839
4840 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4841 s->ctrlq[i].q.size = 512;
4842
a4569504
AG		 4843 if (!is_t4(adap->params.chip))
4844 s->ptptxq.q.size = 8;
4845
c887ad0e 4846 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
0fbc81b3 4847 init_rspq(adap, &s->intrq, 0, 1, 512, 64);
b8ff05a9
DM		 4848}
4849
4850/*
4851 * Reduce the number of Ethernet queues across all ports to at most n.
4852 * n provides at least one queue per port.
4853 */
91744948 4854static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 4855{
4856 int i;
4857 struct port_info *pi;
4858
4859 while (n < adap->sge.ethqsets)
4860 for_each_port(adap, i) {
4861 pi = adap2pinfo(adap, i);
4862 if (pi->nqsets > 1) {
4863 pi->nqsets--;
4864 adap->sge.ethqsets--;
4865 if (adap->sge.ethqsets <= n)
4866 break;
4867 }
4868 }
4869
4870 n = 0;
4871 for_each_port(adap, i) {
4872 pi = adap2pinfo(adap, i);
4873 pi->first_qset = n;
4874 n += pi->nqsets;
4875 }
4876}
4877
94cdb8bb
HS		 4878static int get_msix_info(struct adapter *adap)
4879{
4880 struct uld_msix_info *msix_info;
0fbc81b3
HS		 4881 unsigned int max_ingq = 0;
4882
4883 if (is_offload(adap))
4884 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
4885 if (is_pci_uld(adap))
4886 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
4887
4888 if (!max_ingq)
4889 goto out;
94cdb8bb
HS		 4890
4891 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
4892 if (!msix_info)
4893 return -ENOMEM;
4894
4895 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
4896 sizeof(long), GFP_KERNEL);
4897 if (!adap->msix_bmap_ulds.msix_bmap) {
4898 kfree(msix_info);
4899 return -ENOMEM;
4900 }
4901 spin_lock_init(&adap->msix_bmap_ulds.lock);
4902 adap->msix_info_ulds = msix_info;
0fbc81b3 4903out:
94cdb8bb
HS		 4904 return 0;
4905}
4906
4907static void free_msix_info(struct adapter *adap)
4908{
0fbc81b3 4909 if (!(adap->num_uld && adap->num_ofld_uld))
94cdb8bb
HS		 4910 return;
4911
4912 kfree(adap->msix_info_ulds);
4913 kfree(adap->msix_bmap_ulds.msix_bmap);
4914}
4915
b8ff05a9
DM		 4916/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4917#define EXTRA_VECS 2
4918
91744948 4919static int enable_msix(struct adapter *adap)
b8ff05a9 4920{
94cdb8bb
HS		 4921 int ofld_need = 0, uld_need = 0;
4922 int i, j, want, need, allocated;
b8ff05a9
DM		 4923 struct sge *s = &adap->sge;
4924 unsigned int nchan = adap->params.nports;
f36e58e5 4925 struct msix_entry *entries;
94cdb8bb 4926 int max_ingq = MAX_INGQ;
f36e58e5 4927
0fbc81b3
HS		 4928 if (is_pci_uld(adap))
4929 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
4930 if (is_offload(adap))
4931 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
94cdb8bb 4932 entries = kmalloc(sizeof(*entries) * (max_ingq + 1),
f36e58e5
HS		 4933 GFP_KERNEL);
4934 if (!entries)
4935 return -ENOMEM;
b8ff05a9 4936
94cdb8bb 4937 /* map for msix */
0fbc81b3
HS		 4938 if (get_msix_info(adap)) {
4939 adap->params.offload = 0;
94cdb8bb 4940 adap->params.crypto = 0;
0fbc81b3 4941 }
94cdb8bb
HS		 4942
4943 for (i = 0; i < max_ingq + 1; ++i)
b8ff05a9
DM		 4944 entries[i].entry = i;
4945
4946 want = s->max_ethqsets + EXTRA_VECS;
4947 if (is_offload(adap)) {
0fbc81b3
HS		 4948 want += adap->num_ofld_uld * s->ofldqsets;
4949 ofld_need = adap->num_ofld_uld * nchan;
b8ff05a9 4950 }
94cdb8bb 4951 if (is_pci_uld(adap)) {
0fbc81b3
HS		 4952 want += adap->num_uld * s->ofldqsets;
4953 uld_need = adap->num_uld * nchan;
94cdb8bb 4954 }
688848b1
AB		 4955#ifdef CONFIG_CHELSIO_T4_DCB
4956 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4957 * each port.
4958 */
94cdb8bb 4959 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
688848b1 4960#else
94cdb8bb 4961 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
688848b1 4962#endif
f36e58e5
HS		 4963 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4964 if (allocated < 0) {
4965 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4966 " not using MSI-X\n");
4967 kfree(entries);
4968 return allocated;
4969 }
b8ff05a9 4970
f36e58e5 4971 /* Distribute available vectors to the various queue groups.
c32ad224
AG		 4972 * Every group gets its minimum requirement and NIC gets top
4973 * priority for leftovers.
4974 */
94cdb8bb 4975 i = allocated - EXTRA_VECS - ofld_need - uld_need;
c32ad224
AG		 4976 if (i < s->max_ethqsets) {
4977 s->max_ethqsets = i;
4978 if (i < s->ethqsets)
4979 reduce_ethqs(adap, i);
4980 }
0fbc81b3 4981 if (is_uld(adap)) {
94cdb8bb
HS		 4982 if (allocated < want)
4983 s->nqs_per_uld = nchan;
4984 else
0fbc81b3 4985 s->nqs_per_uld = s->ofldqsets;
94cdb8bb
HS		 4986 }
4987
0fbc81b3 4988 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
c32ad224 4989 adap->msix_info[i].vec = entries[i].vector;
0fbc81b3
HS		 4990 if (is_uld(adap)) {
4991 for (j = 0 ; i < allocated; ++i, j++) {
94cdb8bb 4992 adap->msix_info_ulds[j].vec = entries[i].vector;
0fbc81b3
HS		 4993 adap->msix_info_ulds[j].idx = i;
4994 }
94cdb8bb
HS		 4995 adap->msix_bmap_ulds.mapsize = j;
4996 }
43eb4e82 4997 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
0fbc81b3
HS		 4998 "nic %d per uld %d\n",
4999 allocated, s->max_ethqsets, s->nqs_per_uld);
c32ad224 5000
f36e58e5 5001 kfree(entries);
c32ad224 5002 return 0;
b8ff05a9
DM		 5003}
5004
5005#undef EXTRA_VECS
5006
91744948 5007static int init_rss(struct adapter *adap)
671b0060 5008{
c035e183
HS		 5009 unsigned int i;
5010 int err;
5011
5012 err = t4_init_rss_mode(adap, adap->mbox);
5013 if (err)
5014 return err;
671b0060
DM		 5015
5016 for_each_port(adap, i) {
5017 struct port_info *pi = adap2pinfo(adap, i);
5018
5019 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5020 if (!pi->rss)
5021 return -ENOMEM;
671b0060
DM		 5022 }
5023 return 0;
5024}
5025
547fd272
HS		 5026static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,
5027 enum pci_bus_speed *speed,
5028 enum pcie_link_width *width)
5029{
5030 u32 lnkcap1, lnkcap2;
5031 int err1, err2;
5032
5033#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
5034
5035 *speed = PCI_SPEED_UNKNOWN;
5036 *width = PCIE_LNK_WIDTH_UNKNOWN;
5037
5038 err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,
5039 &lnkcap1);
5040 err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,
5041 &lnkcap2);
5042 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
5043 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5044 *speed = PCIE_SPEED_8_0GT;
5045 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
5046 *speed = PCIE_SPEED_5_0GT;
5047 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
5048 *speed = PCIE_SPEED_2_5GT;
5049 }
5050 if (!err1) {
5051 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
5052 if (!lnkcap2) { /* pre-r3.0 */
5053 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
5054 *speed = PCIE_SPEED_5_0GT;
5055 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
5056 *speed = PCIE_SPEED_2_5GT;
5057 }
5058 }
5059
5060 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5061 return err1 ? err1 : err2 ? err2 : -EINVAL;
5062 return 0;
5063}
5064
5065static void cxgb4_check_pcie_caps(struct adapter *adap)
5066{
5067 enum pcie_link_width width, width_cap;
5068 enum pci_bus_speed speed, speed_cap;
5069
5070#define PCIE_SPEED_STR(speed) \
5071 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
5072 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
5073 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
5074 "Unknown")
5075
5076 if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {
5077 dev_warn(adap->pdev_dev,
5078 "Unable to determine PCIe device BW capabilities\n");
5079 return;
5080 }
5081
5082 if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||
5083 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
5084 dev_warn(adap->pdev_dev,
5085 "Unable to determine PCI Express bandwidth.\n");
5086 return;
5087 }
5088
5089 dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",
5090 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
5091 dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",
5092 width, width_cap);
5093 if (speed < speed_cap || width < width_cap)
5094 dev_info(adap->pdev_dev,
5095 "A slot with more lanes and/or higher speed is "
5096 "suggested for optimal performance.\n");
5097}
5098
0de72738
HS		 5099/* Dump basic information about the adapter */
5100static void print_adapter_info(struct adapter *adapter)
5101{
760446f9
GG		 5102 /* Hardware/Firmware/etc. Version/Revision IDs */
5103 t4_dump_version_info(adapter);
0de72738
HS		 5104
5105 /* Software/Hardware configuration */
5106 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5107 is_offload(adapter) ? "R" : "",
5108 ((adapter->flags & USING_MSIX) ? "MSI-X" :
5109 (adapter->flags & USING_MSI) ? "MSI" : ""),
5110 is_offload(adapter) ? "Offload" : "non-Offload");
5111}
5112
91744948 5113static void print_port_info(const struct net_device *dev)
b8ff05a9 5114{
b8ff05a9 5115 char buf[80];
118969ed 5116 char *bufp = buf;
f1a051b9 5117 const char *spd = "";
118969ed
DM		 5118 const struct port_info *pi = netdev_priv(dev);
5119 const struct adapter *adap = pi->adapter;
f1a051b9
DM		 5120
5121 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
5122 spd = " 2.5 GT/s";
5123 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
5124 spd = " 5 GT/s";
d2e752db
RD		 5125 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
5126 spd = " 8 GT/s";
b8ff05a9 5127
c3168cab 5128 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5e78f7fd 5129 bufp += sprintf(bufp, "100M/");
c3168cab 5130 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5e78f7fd 5131 bufp += sprintf(bufp, "1G/");
c3168cab 5132 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
118969ed 5133 bufp += sprintf(bufp, "10G/");
c3168cab 5134 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
9b86a8d1 5135 bufp += sprintf(bufp, "25G/");
c3168cab 5136 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
72aca4bf 5137 bufp += sprintf(bufp, "40G/");
c3168cab
GG		 5138 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5139 bufp += sprintf(bufp, "50G/");
5140 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
9b86a8d1 5141 bufp += sprintf(bufp, "100G/");
c3168cab
GG		 5142 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5143 bufp += sprintf(bufp, "200G/");
5144 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5145 bufp += sprintf(bufp, "400G/");
118969ed
DM		 5146 if (bufp != buf)
5147 --bufp;
72aca4bf 5148 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed 5149
0de72738
HS		 5150 netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5151 dev->name, adap->params.vpd.id, adap->name, buf);
b8ff05a9
DM		 5152}
5153
06546391
DM		 5154/*
5155 * Free the following resources:
5156 * - memory used for tables
5157 * - MSI/MSI-X
5158 * - net devices
5159 * - resources FW is holding for us
5160 */
5161static void free_some_resources(struct adapter *adapter)
5162{
5163 unsigned int i;
5164
3bdb376e 5165 kvfree(adapter->smt);
752ade68 5166 kvfree(adapter->l2t);
c68644ef 5167 kvfree(adapter->srq);
b72a32da 5168 t4_cleanup_sched(adapter);
752ade68 5169 kvfree(adapter->tids.tid_tab);
e0f911c8 5170 cxgb4_cleanup_tc_flower(adapter);
d8931847 5171 cxgb4_cleanup_tc_u32(adapter);
4b8e27a8
HS		 5172 kfree(adapter->sge.egr_map);
5173 kfree(adapter->sge.ingr_map);
5174 kfree(adapter->sge.starving_fl);
5175 kfree(adapter->sge.txq_maperr);
5b377d11
HS		 5176#ifdef CONFIG_DEBUG_FS
5177 kfree(adapter->sge.blocked_fl);
5178#endif
06546391
DM		 5179 disable_msi(adapter);
5180
5181 for_each_port(adapter, i)
671b0060 5182 if (adapter->port[i]) {
4f3a0fcf
HS		 5183 struct port_info *pi = adap2pinfo(adapter, i);
5184
5185 if (pi->viid != 0)
5186 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5187 0, pi->viid);
671b0060 5188 kfree(adap2pinfo(adapter, i)->rss);
06546391 5189 free_netdev(adapter->port[i]);
671b0060 5190 }
06546391 5191 if (adapter->flags & FW_OK)
b2612722 5192 t4_fw_bye(adapter, adapter->pf);
06546391
DM		 5193}
5194
2ed28baa 5195#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 5196#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 5197 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 5198#define SEGMENT_SIZE 128
b8ff05a9 5199
d86bd29e
HS		 5200static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
5201{
d86bd29e
HS		 5202 u16 device_id;
5203
5204 /* Retrieve adapter's device ID */
5205 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
46cdc9be 5206
5207 switch (device_id >> 12) {
d86bd29e 5208 case CHELSIO_T4:
46cdc9be 5209 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
d86bd29e 5210 case CHELSIO_T5:
46cdc9be 5211 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
d86bd29e 5212 case CHELSIO_T6:
46cdc9be 5213 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
d86bd29e
HS		 5214 default:
5215 dev_err(&pdev->dev, "Device %d is not supported\n",
5216 device_id);
d86bd29e 5217 }
46cdc9be 5218 return -EINVAL;
d86bd29e
HS		 5219}
5220
b6244201 5221#ifdef CONFIG_PCI_IOV
baf50868 5222static void cxgb4_mgmt_setup(struct net_device *dev)
e7b48a32
HS		 5223{
5224 dev->type = ARPHRD_NONE;
5225 dev->mtu = 0;
5226 dev->hard_header_len = 0;
5227 dev->addr_len = 0;
5228 dev->tx_queue_len = 0;
5229 dev->flags |= IFF_NOARP;
5230 dev->priv_flags |= IFF_NO_QUEUE;
5231
5232 /* Initialize the device structure. */
5233 dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5234 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
e7b48a32
HS		 5235}
5236
b6244201
HS		 5237static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5238{
7829451c 5239 struct adapter *adap = pci_get_drvdata(pdev);
b6244201
HS		 5240 int err = 0;
5241 int current_vfs = pci_num_vf(pdev);
5242 u32 pcie_fw;
b6244201 5243
7829451c 5244 pcie_fw = readl(adap->regs + PCIE_FW_A);
b6244201 5245 /* Check if cxgb4 is the MASTER and fw is initialized */
c4e43e14
GG		 5246 if (num_vfs &&
5247 (!(pcie_fw & PCIE_FW_INIT_F) ||
b6244201 5248 !(pcie_fw & PCIE_FW_MASTER_VLD_F) ||
c4e43e14 5249 PCIE_FW_MASTER_G(pcie_fw) != CXGB4_UNIFIED_PF)) {
b6244201
HS		 5250 dev_warn(&pdev->dev,
5251 "cxgb4 driver needs to be MASTER to support SRIOV\n");
5252 return -EOPNOTSUPP;
5253 }
5254
5255 /* If any of the VF's is already assigned to Guest OS, then
5256 * SRIOV for the same cannot be modified
5257 */
5258 if (current_vfs && pci_vfs_assigned(pdev)) {
5259 dev_err(&pdev->dev,
5260 "Cannot modify SR-IOV while VFs are assigned\n");
baf50868 5261 return current_vfs;
b6244201 5262 }
baf50868
GG		 5263 /* Note that the upper-level code ensures that we're never called with
5264 * a non-zero "num_vfs" when we already have VFs instantiated. But
5265 * it never hurts to code defensively.
b6244201 5266 */
baf50868
GG		 5267 if (num_vfs != 0 && current_vfs != 0)
5268 return -EBUSY;
5269
5270 /* Nothing to do for no change. */
5271 if (num_vfs == current_vfs)
5272 return num_vfs;
5273
5274 /* Disable SRIOV when zero is passed. */
b6244201
HS		 5275 if (!num_vfs) {
5276 pci_disable_sriov(pdev);
baf50868
GG		 5277 /* free VF Management Interface */
5278 unregister_netdev(adap->port[0]);
5279 free_netdev(adap->port[0]);
5280 adap->port[0] = NULL;
5281
661dbeb9 5282 /* free VF resources */
baf50868 5283 adap->num_vfs = 0;
661dbeb9
HS		 5284 kfree(adap->vfinfo);
5285 adap->vfinfo = NULL;
baf50868 5286 return 0;
b6244201
HS		 5287 }
5288
baf50868
GG		 5289 if (!current_vfs) {
5290 struct fw_pfvf_cmd port_cmd, port_rpl;
5291 struct net_device *netdev;
5292 unsigned int pmask, port;
5293 struct pci_dev *pbridge;
5294 struct port_info *pi;
5295 char name[IFNAMSIZ];
5296 u32 devcap2;
5297 u16 flags;
5298 int pos;
5299
5300 /* If we want to instantiate Virtual Functions, then our
5301 * parent bridge's PCI-E needs to support Alternative Routing
5302 * ID (ARI) because our VFs will show up at function offset 8
5303 * and above.
5304 */
5305 pbridge = pdev->bus->self;
5306 pos = pci_find_capability(pbridge, PCI_CAP_ID_EXP);
5307 pci_read_config_word(pbridge, pos + PCI_EXP_FLAGS, &flags);
5308 pci_read_config_dword(pbridge, pos + PCI_EXP_DEVCAP2, &devcap2);
5309
5310 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5311 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5312 /* Our parent bridge does not support ARI so issue a
5313 * warning and skip instantiating the VFs. They
5314 * won't be reachable.
5315 */
5316 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5317 pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5318 PCI_FUNC(pbridge->devfn));
5319 return -ENOTSUPP;
5320 }
5321 memset(&port_cmd, 0, sizeof(port_cmd));
5322 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
5323 FW_CMD_REQUEST_F |
5324 FW_CMD_READ_F |
5325 FW_PFVF_CMD_PFN_V(adap->pf) |
5326 FW_PFVF_CMD_VFN_V(0));
5327 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
5328 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
5329 &port_rpl);
b6244201
HS		 5330 if (err)
5331 return err;
baf50868
GG		 5332 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
5333 port = ffs(pmask) - 1;
5334 /* Allocate VF Management Interface. */
5335 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
5336 adap->pf);
5337 netdev = alloc_netdev(sizeof(struct port_info),
5338 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
5339 if (!netdev)
5340 return -ENOMEM;
7829451c 5341
baf50868
GG		 5342 pi = netdev_priv(netdev);
5343 pi->adapter = adap;
5344 pi->lport = port;
5345 pi->tx_chan = port;
5346 SET_NETDEV_DEV(netdev, &pdev->dev);
5347
5348 adap->port[0] = netdev;
5349 pi->port_id = 0;
5350
5351 err = register_netdev(adap->port[0]);
5352 if (err) {
5353 pr_info("Unable to register VF mgmt netdev %s\n", name);
5354 free_netdev(adap->port[0]);
5355 adap->port[0] = NULL;
e7b48a32 5356 return err;
baf50868
GG		 5357 }
5358 /* Allocate and set up VF Information. */
5359 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
5360 sizeof(struct vf_info), GFP_KERNEL);
5361 if (!adap->vfinfo) {
5362 unregister_netdev(adap->port[0]);
5363 free_netdev(adap->port[0]);
5364 adap->port[0] = NULL;
5365 return -ENOMEM;
5366 }
5367 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
5368 }
5369 /* Instantiate the requested number of VFs. */
5370 err = pci_enable_sriov(pdev, num_vfs);
5371 if (err) {
5372 pr_info("Unable to instantiate %d VFs\n", num_vfs);
5373 if (!current_vfs) {
5374 unregister_netdev(adap->port[0]);
5375 free_netdev(adap->port[0]);
5376 adap->port[0] = NULL;
5377 kfree(adap->vfinfo);
5378 adap->vfinfo = NULL;
5379 }
5380 return err;
b6244201 5381 }
661dbeb9 5382
baf50868 5383 adap->num_vfs = num_vfs;
b6244201
HS		 5384 return num_vfs;
5385}
baf50868 5386#endif /* CONFIG_PCI_IOV */
b6244201 5387
1dd06ae8 5388static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 5389{
22adfe0a 5390 int func, i, err, s_qpp, qpp, num_seg;
b8ff05a9 5391 struct port_info *pi;
c8f44aff 5392 bool highdma = false;
b8ff05a9 5393 struct adapter *adapter = NULL;
7829451c 5394 struct net_device *netdev;
d6ce2628 5395 void __iomem *regs;
d86bd29e
HS		 5396 u32 whoami, pl_rev;
5397 enum chip_type chip;
7829451c 5398 static int adap_idx = 1;
b8ff05a9
DM		 5399
5400 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
5401
5402 err = pci_request_regions(pdev, KBUILD_MODNAME);
5403 if (err) {
5404 /* Just info, some other driver may have claimed the device. */
5405 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
5406 return err;
5407 }
5408
b8ff05a9
DM		 5409 err = pci_enable_device(pdev);
5410 if (err) {
5411 dev_err(&pdev->dev, "cannot enable PCI device\n");
5412 goto out_release_regions;
5413 }
5414
d6ce2628
HS		 5415 regs = pci_ioremap_bar(pdev, 0);
5416 if (!regs) {
5417 dev_err(&pdev->dev, "cannot map device registers\n");
5418 err = -ENOMEM;
5419 goto out_disable_device;
5420 }
5421
baf50868
GG		 5422 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5423 if (!adapter) {
5424 err = -ENOMEM;
5425 goto out_unmap_bar0;
5426 }
5427
5428 adapter->regs = regs;
8203b509
HS		 5429 err = t4_wait_dev_ready(regs);
5430 if (err < 0)
e729452e 5431 goto out_free_adapter;
8203b509 5432
d6ce2628 5433 /* We control everything through one PF */
d86bd29e
HS		 5434 whoami = readl(regs + PL_WHOAMI_A);
5435 pl_rev = REV_G(readl(regs + PL_REV_A));
5436 chip = get_chip_type(pdev, pl_rev);
5437 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
5438 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
baf50868
GG		 5439
5440 adapter->pdev = pdev;
5441 adapter->pdev_dev = &pdev->dev;
5442 adapter->name = pci_name(pdev);
5443 adapter->mbox = func;
5444 adapter->pf = func;
016764de
GG		 5445 adapter->params.chip = chip;
5446 adapter->adap_idx = adap_idx;
baf50868
GG		 5447 adapter->msg_enable = DFLT_MSG_ENABLE;
5448 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5449 (sizeof(struct mbox_cmd) *
5450 T4_OS_LOG_MBOX_CMDS),
5451 GFP_KERNEL);
5452 if (!adapter->mbox_log) {
5453 err = -ENOMEM;
5454 goto out_free_adapter;
5455 }
5456 spin_lock_init(&adapter->mbox_lock);
5457 INIT_LIST_HEAD(&adapter->mlist.list);
5458 pci_set_drvdata(pdev, adapter);
5459
d6ce2628 5460 if (func != ent->driver_data) {
d6ce2628
HS		 5461 pci_disable_device(pdev);
5462 pci_save_state(pdev); /* to restore SR-IOV later */
baf50868 5463 return 0;
d6ce2628
HS		 5464 }
5465
b8ff05a9 5466 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 5467 highdma = true;
b8ff05a9
DM		 5468 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
5469 if (err) {
5470 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
5471 "coherent allocations\n");
baf50868 5472 goto out_free_adapter;
b8ff05a9
DM		 5473 }
5474 } else {
5475 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5476 if (err) {
5477 dev_err(&pdev->dev, "no usable DMA configuration\n");
baf50868 5478 goto out_free_adapter;
b8ff05a9
DM		 5479 }
5480 }
5481
5482 pci_enable_pcie_error_reporting(pdev);
5483 pci_set_master(pdev);
5484 pci_save_state(pdev);
7829451c 5485 adap_idx++;
29aaee65
AB		 5486 adapter->workq = create_singlethread_workqueue("cxgb4");
5487 if (!adapter->workq) {
5488 err = -ENOMEM;
5489 goto out_free_adapter;
5490 }
5491
7f080c3f
HS		 5492 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
5493
144be3d9
GS		 5494 /* PCI device has been enabled */
5495 adapter->flags |= DEV_ENABLED;
b8ff05a9
DM		 5496 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
5497
b0ba9d5f
CL		 5498 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
5499 * Ingress Packet Data to Free List Buffers in order to allow for
5500 * chipset performance optimizations between the Root Complex and
5501 * Memory Controllers. (Messages to the associated Ingress Queue
5502 * notifying new Packet Placement in the Free Lists Buffers will be
5503 * send without the Relaxed Ordering Attribute thus guaranteeing that
5504 * all preceding PCIe Transaction Layer Packets will be processed
5505 * first.) But some Root Complexes have various issues with Upstream
5506 * Transaction Layer Packets with the Relaxed Ordering Attribute set.
5507 * The PCIe devices which under the Root Complexes will be cleared the
5508 * Relaxed Ordering bit in the configuration space, So we check our
5509 * PCIe configuration space to see if it's flagged with advice against
5510 * using Relaxed Ordering.
5511 */
5512 if (!pcie_relaxed_ordering_enabled(pdev))
5513 adapter->flags |= ROOT_NO_RELAXED_ORDERING;
5514
b8ff05a9
DM		 5515 spin_lock_init(&adapter->stats_lock);
5516 spin_lock_init(&adapter->tid_release_lock);
e327c225 5517 spin_lock_init(&adapter->win0_lock);
b8ff05a9
DM		 5518
5519 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 5520 INIT_WORK(&adapter->db_full_task, process_db_full);
5521 INIT_WORK(&adapter->db_drop_task, process_db_drop);
8b7372c1 5522 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
b8ff05a9
DM		 5523
5524 err = t4_prep_adapter(adapter);
5525 if (err)
d6ce2628
HS		 5526 goto out_free_adapter;
5527
22adfe0a 5528
d14807dd 5529 if (!is_t4(adapter->params.chip)) {
f612b815
HS		 5530 s_qpp = (QUEUESPERPAGEPF0_S +
5531 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
b2612722 5532 adapter->pf);
f612b815
HS		 5533 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
5534 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
22adfe0a
SR		 5535 num_seg = PAGE_SIZE / SEGMENT_SIZE;
5536
5537 /* Each segment size is 128B. Write coalescing is enabled only
5538 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
5539 * queue is less no of segments that can be accommodated in
5540 * a page size.
5541 */
5542 if (qpp > num_seg) {
5543 dev_err(&pdev->dev,
5544 "Incorrect number of egress queues per page\n");
5545 err = -EINVAL;
d6ce2628 5546 goto out_free_adapter;
22adfe0a
SR		 5547 }
5548 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
5549 pci_resource_len(pdev, 2));
5550 if (!adapter->bar2) {
5551 dev_err(&pdev->dev, "cannot map device bar2 region\n");
5552 err = -ENOMEM;
d6ce2628 5553 goto out_free_adapter;
22adfe0a
SR		 5554 }
5555 }
5556
636f9d37 5557 setup_memwin(adapter);
b8ff05a9 5558 err = adap_init0(adapter);
5b377d11
HS		 5559#ifdef CONFIG_DEBUG_FS
5560 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
5561#endif
636f9d37 5562 setup_memwin_rdma(adapter);
b8ff05a9
DM		 5563 if (err)
5564 goto out_unmap_bar;
5565
2a485cf7
HS		 5566 /* configure SGE_STAT_CFG_A to read WC stats */
5567 if (!is_t4(adapter->params.chip))
676d6a75
HS		 5568 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
5569 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
5570 T6_STATMODE_V(0)));
2a485cf7 5571
b8ff05a9 5572 for_each_port(adapter, i) {
b8ff05a9
DM		 5573 netdev = alloc_etherdev_mq(sizeof(struct port_info),
5574 MAX_ETH_QSETS);
5575 if (!netdev) {
5576 err = -ENOMEM;
5577 goto out_free_dev;
5578 }
5579
5580 SET_NETDEV_DEV(netdev, &pdev->dev);
5581
5582 adapter->port[i] = netdev;
5583 pi = netdev_priv(netdev);
5584 pi->adapter = adapter;
5585 pi->xact_addr_filt = -1;
b8ff05a9 5586 pi->port_id = i;
b8ff05a9
DM		 5587 netdev->irq = pdev->irq;
5588
2ed28baa
MM		 5589 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5590 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5591 NETIF_F_RXCSUM | NETIF_F_RXHASH |
d8931847
RL		 5592 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
5593 NETIF_F_HW_TC;
d0a1299c
GG		 5594
5595 if (CHELSIO_CHIP_VERSION(chip) > CHELSIO_T5)
5596 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
5597
c8f44aff
MM		 5598 if (highdma)
5599 netdev->hw_features |= NETIF_F_HIGHDMA;
5600 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 5601 netdev->vlan_features = netdev->features & VLAN_FEAT;
5602
01789349
JP		 5603 netdev->priv_flags |= IFF_UNICAST_FLT;
5604
d894be57 5605 /* MTU range: 81 - 9600 */
a047fbae 5606 netdev->min_mtu = 81; /* accommodate SACK */
d894be57
JW		 5607 netdev->max_mtu = MAX_MTU;
5608
b8ff05a9 5609 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 5610#ifdef CONFIG_CHELSIO_T4_DCB
5611 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5612 cxgb4_dcb_state_init(netdev);
5613#endif
812034f1 5614 cxgb4_set_ethtool_ops(netdev);
b8ff05a9
DM		 5615 }
5616
ad75b7d3
RL		 5617 cxgb4_init_ethtool_dump(adapter);
5618
b8ff05a9
DM		 5619 pci_set_drvdata(pdev, adapter);
5620
5621 if (adapter->flags & FW_OK) {
060e0c75 5622 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 5623 if (err)
5624 goto out_free_dev;
098ef6c2
HS		 5625 } else if (adapter->params.nports == 1) {
5626 /* If we don't have a connection to the firmware -- possibly
5627 * because of an error -- grab the raw VPD parameters so we
5628 * can set the proper MAC Address on the debug network
5629 * interface that we've created.
5630 */
5631 u8 hw_addr[ETH_ALEN];
5632 u8 *na = adapter->params.vpd.na;
5633
5634 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5635 if (!err) {
5636 for (i = 0; i < ETH_ALEN; i++)
5637 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5638 hex2val(na[2 * i + 1]));
5639 t4_set_hw_addr(adapter, 0, hw_addr);
5640 }
b8ff05a9
DM		 5641 }
5642
098ef6c2 5643 /* Configure queues and allocate tables now, they can be needed as
b8ff05a9
DM		 5644 * soon as the first register_netdev completes.
5645 */
5646 cfg_queues(adapter);
5647
3bdb376e
KS		 5648 adapter->smt = t4_init_smt();
5649 if (!adapter->smt) {
5650 /* We tolerate a lack of SMT, giving up some functionality */
5651 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
5652 }
5653
5be9ed8d 5654 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
b8ff05a9
DM		 5655 if (!adapter->l2t) {
5656 /* We tolerate a lack of L2T, giving up some functionality */
5657 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5658 adapter->params.offload = 0;
5659 }
5660
b5a02f50 5661#if IS_ENABLED(CONFIG_IPV6)
eb72f74f
HS		 5662 if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
5663 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5664 /* CLIP functionality is not present in hardware,
5665 * hence disable all offload features
b5a02f50
AB		 5666 */
5667 dev_warn(&pdev->dev,
eb72f74f 5668 "CLIP not enabled in hardware, continuing\n");
b5a02f50 5669 adapter->params.offload = 0;
eb72f74f
HS		 5670 } else {
5671 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5672 adapter->clipt_end);
5673 if (!adapter->clipt) {
5674 /* We tolerate a lack of clip_table, giving up
5675 * some functionality
5676 */
5677 dev_warn(&pdev->dev,
5678 "could not allocate Clip table, continuing\n");
5679 adapter->params.offload = 0;
5680 }
b5a02f50
AB		 5681 }
5682#endif
b72a32da
RL		 5683
5684 for_each_port(adapter, i) {
5685 pi = adap2pinfo(adapter, i);
5686 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5687 if (!pi->sched_tbl)
5688 dev_warn(&pdev->dev,
5689 "could not activate scheduling on port %d\n",
5690 i);
5691 }
5692
578b46b9 5693 if (tid_init(&adapter->tids) < 0) {
b8ff05a9
DM		 5694 dev_warn(&pdev->dev, "could not allocate TID table, "
5695 "continuing\n");
5696 adapter->params.offload = 0;
d8931847 5697 } else {
45da1ca2 5698 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
d8931847
RL		 5699 if (!adapter->tc_u32)
5700 dev_warn(&pdev->dev,
5701 "could not offload tc u32, continuing\n");
62488e4b 5702
79e6d46a
KS		 5703 if (cxgb4_init_tc_flower(adapter))
5704 dev_warn(&pdev->dev,
5705 "could not offload tc flower, continuing\n");
b8ff05a9
DM		 5706 }
5707
5c31254e 5708 if (is_offload(adapter) || is_hashfilter(adapter)) {
9a1bb9f6
HS		 5709 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5710 u32 hash_base, hash_reg;
5711
5712 if (chip <= CHELSIO_T5) {
5713 hash_reg = LE_DB_TID_HASHBASE_A;
5714 hash_base = t4_read_reg(adapter, hash_reg);
5715 adapter->tids.hash_base = hash_base / 4;
5716 } else {
5717 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5718 hash_base = t4_read_reg(adapter, hash_reg);
5719 adapter->tids.hash_base = hash_base;
5720 }
5721 }
5722 }
5723
f7cabcdd
DM		 5724 /* See what interrupts we'll be using */
5725 if (msi > 1 && enable_msix(adapter) == 0)
5726 adapter->flags |= USING_MSIX;
94cdb8bb 5727 else if (msi > 0 && pci_enable_msi(pdev) == 0) {
f7cabcdd 5728 adapter->flags |= USING_MSI;
94cdb8bb
HS		 5729 if (msi > 1)
5730 free_msix_info(adapter);
5731 }
f7cabcdd 5732
547fd272
HS		 5733 /* check for PCI Express bandwidth capabiltites */
5734 cxgb4_check_pcie_caps(adapter);
5735
671b0060
DM		 5736 err = init_rss(adapter);
5737 if (err)
5738 goto out_free_dev;
5739
843bd7db
AV		 5740 err = setup_fw_sge_queues(adapter);
5741 if (err) {
5742 dev_err(adapter->pdev_dev,
5743 "FW sge queue allocation failed, err %d", err);
5744 goto out_free_dev;
5745 }
5746
b8ff05a9
DM		 5747 /*
5748 * The card is now ready to go. If any errors occur during device
5749 * registration we do not fail the whole card but rather proceed only
5750 * with the ports we manage to register successfully. However we must
5751 * register at least one net device.
5752 */
5753 for_each_port(adapter, i) {
a57cabe0 5754 pi = adap2pinfo(adapter, i);
d2a007ab 5755 adapter->port[i]->dev_port = pi->lport;
a57cabe0
DM		 5756 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5757 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5758
b1a73af9
SM		 5759 netif_carrier_off(adapter->port[i]);
5760
b8ff05a9
DM		 5761 err = register_netdev(adapter->port[i]);
5762 if (err)
b1a3c2b6 5763 break;
b1a3c2b6
DM		 5764 adapter->chan_map[pi->tx_chan] = i;
5765 print_port_info(adapter->port[i]);
b8ff05a9 5766 }
b1a3c2b6 5767 if (i == 0) {
b8ff05a9
DM		 5768 dev_err(&pdev->dev, "could not register any net devices\n");
5769 goto out_free_dev;
5770 }
b1a3c2b6
DM		 5771 if (err) {
5772 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5773 err = 0;
6403eab1 5774 }
b8ff05a9
DM		 5775
5776 if (cxgb4_debugfs_root) {
5777 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5778 cxgb4_debugfs_root);
5779 setup_debugfs(adapter);
5780 }
5781
6482aa7c
DLR		 5782 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5783 pdev->needs_freset = 1;
5784
0fbc81b3
HS		 5785 if (is_uld(adapter)) {
5786 mutex_lock(&uld_mutex);
5787 list_add_tail(&adapter->list_node, &adapter_list);
5788 mutex_unlock(&uld_mutex);
5789 }
b8ff05a9 5790
9c33e420
AG		 5791 if (!is_t4(adapter->params.chip))
5792 cxgb4_ptp_init(adapter);
5793
0de72738 5794 print_adapter_info(adapter);
7829451c 5795 return 0;
0de72738 5796
b8ff05a9 5797 out_free_dev:
843bd7db 5798 t4_free_sge_resources(adapter);
06546391 5799 free_some_resources(adapter);
94cdb8bb
HS		 5800 if (adapter->flags & USING_MSIX)
5801 free_msix_info(adapter);
0fbc81b3
HS		 5802 if (adapter->num_uld || adapter->num_ofld_uld)
5803 t4_uld_mem_free(adapter);
b8ff05a9 5804 out_unmap_bar:
d14807dd 5805 if (!is_t4(adapter->params.chip))
22adfe0a 5806 iounmap(adapter->bar2);
b8ff05a9 5807 out_free_adapter:
29aaee65
AB		 5808 if (adapter->workq)
5809 destroy_workqueue(adapter->workq);
5810
7f080c3f 5811 kfree(adapter->mbox_log);
b8ff05a9 5812 kfree(adapter);
d6ce2628
HS		 5813 out_unmap_bar0:
5814 iounmap(regs);
b8ff05a9
DM		 5815 out_disable_device:
5816 pci_disable_pcie_error_reporting(pdev);
5817 pci_disable_device(pdev);
5818 out_release_regions:
5819 pci_release_regions(pdev);
b8ff05a9
DM		 5820 return err;
5821}
5822
91744948 5823static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 5824{
5825 struct adapter *adapter = pci_get_drvdata(pdev);
5826
7829451c
HS		 5827 if (!adapter) {
5828 pci_release_regions(pdev);
5829 return;
5830 }
636f9d37 5831
e1f6198e
GG		 5832 adapter->flags |= SHUTTING_DOWN;
5833
7829451c 5834 if (adapter->pf == 4) {
b8ff05a9
DM		 5835 int i;
5836
29aaee65
AB		 5837 /* Tear down per-adapter Work Queue first since it can contain
5838 * references to our adapter data structure.
5839 */
5840 destroy_workqueue(adapter->workq);
5841
6a146f3a 5842 if (is_uld(adapter)) {
b8ff05a9 5843 detach_ulds(adapter);
6a146f3a
GP		 5844 t4_uld_clean_up(adapter);
5845 }
b8ff05a9 5846
8b4e6b3c
AV		 5847 adap_free_hma_mem(adapter);
5848
b37987e8
HS		 5849 disable_interrupts(adapter);
5850
b8ff05a9 5851 for_each_port(adapter, i)
8f3a7676 5852 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 5853 unregister_netdev(adapter->port[i]);
5854
9f16dc2e 5855 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 5856
9c33e420
AG		 5857 if (!is_t4(adapter->params.chip))
5858 cxgb4_ptp_stop(adapter);
5859
f2b7e78d
VP		 5860 /* If we allocated filters, free up state associated with any
5861 * valid filters ...
5862 */
578b46b9 5863 clear_all_filters(adapter);
f2b7e78d 5864
aaefae9b
DM		 5865 if (adapter->flags & FULL_INIT_DONE)
5866 cxgb_down(adapter);
b8ff05a9 5867
94cdb8bb
HS		 5868 if (adapter->flags & USING_MSIX)
5869 free_msix_info(adapter);
0fbc81b3
HS		 5870 if (adapter->num_uld || adapter->num_ofld_uld)
5871 t4_uld_mem_free(adapter);
06546391 5872 free_some_resources(adapter);
b5a02f50
AB		 5873#if IS_ENABLED(CONFIG_IPV6)
5874 t4_cleanup_clip_tbl(adapter);
5875#endif
d14807dd 5876 if (!is_t4(adapter->params.chip))
22adfe0a 5877 iounmap(adapter->bar2);
7829451c
HS		 5878 }
5879#ifdef CONFIG_PCI_IOV
5880 else {
baf50868 5881 cxgb4_iov_configure(adapter->pdev, 0);
7829451c
HS		 5882 }
5883#endif
c4e43e14
GG		 5884 iounmap(adapter->regs);
5885 pci_disable_pcie_error_reporting(pdev);
5886 if ((adapter->flags & DEV_ENABLED)) {
5887 pci_disable_device(pdev);
5888 adapter->flags &= ~DEV_ENABLED;
5889 }
5890 pci_release_regions(pdev);
5891 kfree(adapter->mbox_log);
5892 synchronize_rcu();
5893 kfree(adapter);
b8ff05a9
DM		 5894}
5895
0fbc81b3
HS		 5896/* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
5897 * delivery. This is essentially a stripped down version of the PCI remove()
5898 * function where we do the minimal amount of work necessary to shutdown any
5899 * further activity.
5900 */
5901static void shutdown_one(struct pci_dev *pdev)
5902{
5903 struct adapter *adapter = pci_get_drvdata(pdev);
5904
5905 /* As with remove_one() above (see extended comment), we only want do
5906 * do cleanup on PCI Devices which went all the way through init_one()
5907 * ...
5908 */
5909 if (!adapter) {
5910 pci_release_regions(pdev);
5911 return;
5912 }
5913
e1f6198e
GG		 5914 adapter->flags |= SHUTTING_DOWN;
5915
0fbc81b3
HS		 5916 if (adapter->pf == 4) {
5917 int i;
5918
5919 for_each_port(adapter, i)
5920 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5921 cxgb_close(adapter->port[i]);
5922
6a146f3a
GP		 5923 if (is_uld(adapter)) {
5924 detach_ulds(adapter);
5925 t4_uld_clean_up(adapter);
5926 }
5927
0fbc81b3
HS		 5928 disable_interrupts(adapter);
5929 disable_msi(adapter);
5930
5931 t4_sge_stop(adapter);
5932 if (adapter->flags & FW_OK)
5933 t4_fw_bye(adapter, adapter->mbox);
5934 }
0fbc81b3
HS		 5935}
5936
b8ff05a9
DM		 5937static struct pci_driver cxgb4_driver = {
5938 .name = KBUILD_MODNAME,
5939 .id_table = cxgb4_pci_tbl,
5940 .probe = init_one,
91744948 5941 .remove = remove_one,
0fbc81b3 5942 .shutdown = shutdown_one,
b6244201
HS		 5943#ifdef CONFIG_PCI_IOV
5944 .sriov_configure = cxgb4_iov_configure,
5945#endif
204dc3c0 5946 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 5947};
5948
5949static int __init cxgb4_init_module(void)
5950{
5951 int ret;
5952
5953 /* Debugfs support is optional, just warn if this fails */
5954 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5955 if (!cxgb4_debugfs_root)
428ac43f 5956 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 5957
5958 ret = pci_register_driver(&cxgb4_driver);
29aaee65 5959 if (ret < 0)
b8ff05a9 5960 debugfs_remove(cxgb4_debugfs_root);
01bcca68 5961
1bb60376 5962#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 5963 if (!inet6addr_registered) {
5964 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5965 inet6addr_registered = true;
5966 }
1bb60376 5967#endif
01bcca68 5968
b8ff05a9
DM		 5969 return ret;
5970}
5971
5972static void __exit cxgb4_cleanup_module(void)
5973{
1bb60376 5974#if IS_ENABLED(CONFIG_IPV6)
1793c798 5975 if (inet6addr_registered) {
b5a02f50
AB		 5976 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5977 inet6addr_registered = false;
5978 }
1bb60376 5979#endif
b8ff05a9
DM		 5980 pci_unregister_driver(&cxgb4_driver);
5981 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
5982}
5983
5984module_init(cxgb4_init_module);
5985module_exit(cxgb4_cleanup_module);
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