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b8ff05a9 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
b8ff05a9 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
36 | ||
37 | #include <linux/bitmap.h> | |
38 | #include <linux/crc32.h> | |
39 | #include <linux/ctype.h> | |
40 | #include <linux/debugfs.h> | |
41 | #include <linux/err.h> | |
42 | #include <linux/etherdevice.h> | |
43 | #include <linux/firmware.h> | |
01789349 | 44 | #include <linux/if.h> |
b8ff05a9 DM |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/init.h> | |
47 | #include <linux/log2.h> | |
48 | #include <linux/mdio.h> | |
49 | #include <linux/module.h> | |
50 | #include <linux/moduleparam.h> | |
51 | #include <linux/mutex.h> | |
52 | #include <linux/netdevice.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/aer.h> | |
55 | #include <linux/rtnetlink.h> | |
56 | #include <linux/sched.h> | |
57 | #include <linux/seq_file.h> | |
58 | #include <linux/sockios.h> | |
59 | #include <linux/vmalloc.h> | |
60 | #include <linux/workqueue.h> | |
61 | #include <net/neighbour.h> | |
62 | #include <net/netevent.h> | |
01bcca68 | 63 | #include <net/addrconf.h> |
1ef8019b | 64 | #include <net/bonding.h> |
b5a02f50 | 65 | #include <net/addrconf.h> |
b8ff05a9 | 66 | #include <asm/uaccess.h> |
c5a8c0f3 | 67 | #include <linux/crash_dump.h> |
b8ff05a9 DM |
68 | |
69 | #include "cxgb4.h" | |
70 | #include "t4_regs.h" | |
f612b815 | 71 | #include "t4_values.h" |
b8ff05a9 DM |
72 | #include "t4_msg.h" |
73 | #include "t4fw_api.h" | |
cd6c2f12 | 74 | #include "t4fw_version.h" |
688848b1 | 75 | #include "cxgb4_dcb.h" |
fd88b31a | 76 | #include "cxgb4_debugfs.h" |
b5a02f50 | 77 | #include "clip_tbl.h" |
b8ff05a9 DM |
78 | #include "l2t.h" |
79 | ||
812034f1 HS |
80 | char cxgb4_driver_name[] = KBUILD_MODNAME; |
81 | ||
01bcca68 VP |
82 | #ifdef DRV_VERSION |
83 | #undef DRV_VERSION | |
84 | #endif | |
3a7f8554 | 85 | #define DRV_VERSION "2.0.0-ko" |
812034f1 | 86 | const char cxgb4_driver_version[] = DRV_VERSION; |
52a5f846 | 87 | #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" |
b8ff05a9 | 88 | |
f2b7e78d VP |
89 | /* Host shadow copy of ingress filter entry. This is in host native format |
90 | * and doesn't match the ordering or bit order, etc. of the hardware of the | |
91 | * firmware command. The use of bit-field structure elements is purely to | |
92 | * remind ourselves of the field size limitations and save memory in the case | |
93 | * where the filter table is large. | |
94 | */ | |
95 | struct filter_entry { | |
96 | /* Administrative fields for filter. | |
97 | */ | |
98 | u32 valid:1; /* filter allocated and valid */ | |
99 | u32 locked:1; /* filter is administratively locked */ | |
100 | ||
101 | u32 pending:1; /* filter action is pending firmware reply */ | |
102 | u32 smtidx:8; /* Source MAC Table index for smac */ | |
103 | struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ | |
104 | ||
105 | /* The filter itself. Most of this is a straight copy of information | |
106 | * provided by the extended ioctl(). Some fields are translated to | |
107 | * internal forms -- for instance the Ingress Queue ID passed in from | |
108 | * the ioctl() is translated into the Absolute Ingress Queue ID. | |
109 | */ | |
110 | struct ch_filter_specification fs; | |
111 | }; | |
112 | ||
b8ff05a9 DM |
113 | #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ |
114 | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ | |
115 | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) | |
116 | ||
3fedeab1 HS |
117 | /* Macros needed to support the PCI Device ID Table ... |
118 | */ | |
119 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ | |
768ffc66 | 120 | static const struct pci_device_id cxgb4_pci_tbl[] = { |
3fedeab1 | 121 | #define CH_PCI_DEVICE_ID_FUNCTION 0x4 |
b8ff05a9 | 122 | |
3fedeab1 HS |
123 | /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is |
124 | * called for both. | |
125 | */ | |
126 | #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 | |
127 | ||
128 | #define CH_PCI_ID_TABLE_ENTRY(devid) \ | |
129 | {PCI_VDEVICE(CHELSIO, (devid)), 4} | |
130 | ||
131 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ | |
132 | { 0, } \ | |
133 | } | |
134 | ||
135 | #include "t4_pci_id_tbl.h" | |
b8ff05a9 | 136 | |
16e47624 | 137 | #define FW4_FNAME "cxgb4/t4fw.bin" |
0a57a536 | 138 | #define FW5_FNAME "cxgb4/t5fw.bin" |
3ccc6cf7 | 139 | #define FW6_FNAME "cxgb4/t6fw.bin" |
16e47624 | 140 | #define FW4_CFNAME "cxgb4/t4-config.txt" |
0a57a536 | 141 | #define FW5_CFNAME "cxgb4/t5-config.txt" |
3ccc6cf7 | 142 | #define FW6_CFNAME "cxgb4/t6-config.txt" |
01b69614 HS |
143 | #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" |
144 | #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" | |
145 | #define PHY_AQ1202_DEVICEID 0x4409 | |
146 | #define PHY_BCM84834_DEVICEID 0x4486 | |
b8ff05a9 DM |
147 | |
148 | MODULE_DESCRIPTION(DRV_DESC); | |
149 | MODULE_AUTHOR("Chelsio Communications"); | |
150 | MODULE_LICENSE("Dual BSD/GPL"); | |
151 | MODULE_VERSION(DRV_VERSION); | |
152 | MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); | |
16e47624 | 153 | MODULE_FIRMWARE(FW4_FNAME); |
0a57a536 | 154 | MODULE_FIRMWARE(FW5_FNAME); |
52a5f846 | 155 | MODULE_FIRMWARE(FW6_FNAME); |
b8ff05a9 | 156 | |
636f9d37 VP |
157 | /* |
158 | * Normally we're willing to become the firmware's Master PF but will be happy | |
159 | * if another PF has already become the Master and initialized the adapter. | |
160 | * Setting "force_init" will cause this driver to forcibly establish itself as | |
161 | * the Master PF and initialize the adapter. | |
162 | */ | |
163 | static uint force_init; | |
164 | ||
165 | module_param(force_init, uint, 0644); | |
d7d3e25f HS |
166 | MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter," |
167 | "deprecated parameter"); | |
13ee15d3 | 168 | |
b8ff05a9 DM |
169 | static int dflt_msg_enable = DFLT_MSG_ENABLE; |
170 | ||
171 | module_param(dflt_msg_enable, int, 0644); | |
8a21ec4e HS |
172 | MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap, " |
173 | "deprecated parameter"); | |
b8ff05a9 DM |
174 | |
175 | /* | |
176 | * The driver uses the best interrupt scheme available on a platform in the | |
177 | * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which | |
178 | * of these schemes the driver may consider as follows: | |
179 | * | |
180 | * msi = 2: choose from among all three options | |
181 | * msi = 1: only consider MSI and INTx interrupts | |
182 | * msi = 0: force INTx interrupts | |
183 | */ | |
184 | static int msi = 2; | |
185 | ||
186 | module_param(msi, int, 0644); | |
187 | MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); | |
188 | ||
636f9d37 VP |
189 | /* |
190 | * Normally we tell the chip to deliver Ingress Packets into our DMA buffers | |
191 | * offset by 2 bytes in order to have the IP headers line up on 4-byte | |
192 | * boundaries. This is a requirement for many architectures which will throw | |
193 | * a machine check fault if an attempt is made to access one of the 4-byte IP | |
194 | * header fields on a non-4-byte boundary. And it's a major performance issue | |
195 | * even on some architectures which allow it like some implementations of the | |
196 | * x86 ISA. However, some architectures don't mind this and for some very | |
197 | * edge-case performance sensitive applications (like forwarding large volumes | |
198 | * of small packets), setting this DMA offset to 0 will decrease the number of | |
199 | * PCI-E Bus transfers enough to measurably affect performance. | |
200 | */ | |
201 | static int rx_dma_offset = 2; | |
202 | ||
b8ff05a9 | 203 | #ifdef CONFIG_PCI_IOV |
7d6727cf SR |
204 | /* Configure the number of PCI-E Virtual Function which are to be instantiated |
205 | * on SR-IOV Capable Physical Functions. | |
0a57a536 | 206 | */ |
7d6727cf | 207 | static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV]; |
b8ff05a9 DM |
208 | |
209 | module_param_array(num_vf, uint, NULL, 0644); | |
b6244201 | 210 | MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3, deprecated parameter - please use the pci sysfs interface."); |
b8ff05a9 DM |
211 | #endif |
212 | ||
688848b1 AB |
213 | /* TX Queue select used to determine what algorithm to use for selecting TX |
214 | * queue. Select between the kernel provided function (select_queue=0) or user | |
215 | * cxgb_select_queue function (select_queue=1) | |
216 | * | |
217 | * Default: select_queue=0 | |
218 | */ | |
219 | static int select_queue; | |
220 | module_param(select_queue, int, 0644); | |
221 | MODULE_PARM_DESC(select_queue, | |
222 | "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); | |
223 | ||
b8ff05a9 DM |
224 | static struct dentry *cxgb4_debugfs_root; |
225 | ||
226 | static LIST_HEAD(adapter_list); | |
227 | static DEFINE_MUTEX(uld_mutex); | |
01bcca68 VP |
228 | /* Adapter list to be accessed from atomic context */ |
229 | static LIST_HEAD(adap_rcu_list); | |
230 | static DEFINE_SPINLOCK(adap_rcu_lock); | |
b8ff05a9 | 231 | static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX]; |
f2692d16 | 232 | static const char *const uld_str[] = { "RDMA", "iSCSI", "iSCSIT" }; |
b8ff05a9 DM |
233 | |
234 | static void link_report(struct net_device *dev) | |
235 | { | |
236 | if (!netif_carrier_ok(dev)) | |
237 | netdev_info(dev, "link down\n"); | |
238 | else { | |
239 | static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; | |
240 | ||
85412255 | 241 | const char *s; |
b8ff05a9 DM |
242 | const struct port_info *p = netdev_priv(dev); |
243 | ||
244 | switch (p->link_cfg.speed) { | |
e8b39015 | 245 | case 10000: |
b8ff05a9 DM |
246 | s = "10Gbps"; |
247 | break; | |
e8b39015 | 248 | case 1000: |
b8ff05a9 DM |
249 | s = "1000Mbps"; |
250 | break; | |
e8b39015 | 251 | case 100: |
b8ff05a9 DM |
252 | s = "100Mbps"; |
253 | break; | |
e8b39015 | 254 | case 40000: |
72aca4bf KS |
255 | s = "40Gbps"; |
256 | break; | |
85412255 HS |
257 | default: |
258 | pr_info("%s: unsupported speed: %d\n", | |
259 | dev->name, p->link_cfg.speed); | |
260 | return; | |
b8ff05a9 DM |
261 | } |
262 | ||
263 | netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, | |
264 | fc[p->link_cfg.fc]); | |
265 | } | |
266 | } | |
267 | ||
688848b1 AB |
268 | #ifdef CONFIG_CHELSIO_T4_DCB |
269 | /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ | |
270 | static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) | |
271 | { | |
272 | struct port_info *pi = netdev_priv(dev); | |
273 | struct adapter *adap = pi->adapter; | |
274 | struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; | |
275 | int i; | |
276 | ||
277 | /* We use a simple mapping of Port TX Queue Index to DCB | |
278 | * Priority when we're enabling DCB. | |
279 | */ | |
280 | for (i = 0; i < pi->nqsets; i++, txq++) { | |
281 | u32 name, value; | |
282 | int err; | |
283 | ||
5167865a HS |
284 | name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
285 | FW_PARAMS_PARAM_X_V( | |
286 | FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | | |
287 | FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); | |
688848b1 AB |
288 | value = enable ? i : 0xffffffff; |
289 | ||
290 | /* Since we can be called while atomic (from "interrupt | |
291 | * level") we need to issue the Set Parameters Commannd | |
292 | * without sleeping (timeout < 0). | |
293 | */ | |
b2612722 | 294 | err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, |
01b69614 HS |
295 | &name, &value, |
296 | -FW_CMD_MAX_TIMEOUT); | |
688848b1 AB |
297 | |
298 | if (err) | |
299 | dev_err(adap->pdev_dev, | |
300 | "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", | |
301 | enable ? "set" : "unset", pi->port_id, i, -err); | |
10b00466 AB |
302 | else |
303 | txq->dcb_prio = value; | |
688848b1 AB |
304 | } |
305 | } | |
306 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
307 | ||
218d48e7 HS |
308 | int cxgb4_dcb_enabled(const struct net_device *dev) |
309 | { | |
310 | #ifdef CONFIG_CHELSIO_T4_DCB | |
311 | struct port_info *pi = netdev_priv(dev); | |
312 | ||
313 | if (!pi->dcb.enabled) | |
314 | return 0; | |
315 | ||
316 | return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || | |
317 | (pi->dcb.state == CXGB4_DCB_STATE_HOST)); | |
318 | #else | |
319 | return 0; | |
320 | #endif | |
321 | } | |
322 | EXPORT_SYMBOL(cxgb4_dcb_enabled); | |
323 | ||
b8ff05a9 DM |
324 | void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) |
325 | { | |
326 | struct net_device *dev = adapter->port[port_id]; | |
327 | ||
328 | /* Skip changes from disabled ports. */ | |
329 | if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { | |
330 | if (link_stat) | |
331 | netif_carrier_on(dev); | |
688848b1 AB |
332 | else { |
333 | #ifdef CONFIG_CHELSIO_T4_DCB | |
218d48e7 HS |
334 | if (cxgb4_dcb_enabled(dev)) { |
335 | cxgb4_dcb_state_init(dev); | |
336 | dcb_tx_queue_prio_enable(dev, false); | |
337 | } | |
688848b1 | 338 | #endif /* CONFIG_CHELSIO_T4_DCB */ |
b8ff05a9 | 339 | netif_carrier_off(dev); |
688848b1 | 340 | } |
b8ff05a9 DM |
341 | |
342 | link_report(dev); | |
343 | } | |
344 | } | |
345 | ||
346 | void t4_os_portmod_changed(const struct adapter *adap, int port_id) | |
347 | { | |
348 | static const char *mod_str[] = { | |
a0881cab | 349 | NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" |
b8ff05a9 DM |
350 | }; |
351 | ||
352 | const struct net_device *dev = adap->port[port_id]; | |
353 | const struct port_info *pi = netdev_priv(dev); | |
354 | ||
355 | if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) | |
356 | netdev_info(dev, "port module unplugged\n"); | |
a0881cab | 357 | else if (pi->mod_type < ARRAY_SIZE(mod_str)) |
b8ff05a9 | 358 | netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); |
be81a2de HS |
359 | else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) |
360 | netdev_info(dev, "%s: unsupported port module inserted\n", | |
361 | dev->name); | |
362 | else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) | |
363 | netdev_info(dev, "%s: unknown port module inserted\n", | |
364 | dev->name); | |
365 | else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) | |
366 | netdev_info(dev, "%s: transceiver module error\n", dev->name); | |
367 | else | |
368 | netdev_info(dev, "%s: unknown module type %d inserted\n", | |
369 | dev->name, pi->mod_type); | |
b8ff05a9 DM |
370 | } |
371 | ||
fc08a01a HS |
372 | int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ |
373 | module_param(dbfifo_int_thresh, int, 0644); | |
374 | MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); | |
375 | ||
b8ff05a9 | 376 | /* |
fc08a01a | 377 | * usecs to sleep while draining the dbfifo |
b8ff05a9 | 378 | */ |
fc08a01a HS |
379 | static int dbfifo_drain_delay = 1000; |
380 | module_param(dbfifo_drain_delay, int, 0644); | |
381 | MODULE_PARM_DESC(dbfifo_drain_delay, | |
382 | "usecs to sleep while draining the dbfifo"); | |
383 | ||
384 | static inline int cxgb4_set_addr_hash(struct port_info *pi) | |
b8ff05a9 | 385 | { |
fc08a01a HS |
386 | struct adapter *adap = pi->adapter; |
387 | u64 vec = 0; | |
388 | bool ucast = false; | |
389 | struct hash_mac_addr *entry; | |
390 | ||
391 | /* Calculate the hash vector for the updated list and program it */ | |
392 | list_for_each_entry(entry, &adap->mac_hlist, list) { | |
393 | ucast |= is_unicast_ether_addr(entry->addr); | |
394 | vec |= (1ULL << hash_mac_addr(entry->addr)); | |
395 | } | |
396 | return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, | |
397 | vec, false); | |
398 | } | |
399 | ||
400 | static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) | |
401 | { | |
402 | struct port_info *pi = netdev_priv(netdev); | |
403 | struct adapter *adap = pi->adapter; | |
404 | int ret; | |
b8ff05a9 DM |
405 | u64 mhash = 0; |
406 | u64 uhash = 0; | |
fc08a01a HS |
407 | bool free = false; |
408 | bool ucast = is_unicast_ether_addr(mac_addr); | |
409 | const u8 *maclist[1] = {mac_addr}; | |
410 | struct hash_mac_addr *new_entry; | |
411 | ||
412 | ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist, | |
413 | NULL, ucast ? &uhash : &mhash, false); | |
414 | if (ret < 0) | |
415 | goto out; | |
416 | /* if hash != 0, then add the addr to hash addr list | |
417 | * so on the end we will calculate the hash for the | |
418 | * list and program it | |
419 | */ | |
420 | if (uhash || mhash) { | |
421 | new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); | |
422 | if (!new_entry) | |
423 | return -ENOMEM; | |
424 | ether_addr_copy(new_entry->addr, mac_addr); | |
425 | list_add_tail(&new_entry->list, &adap->mac_hlist); | |
426 | ret = cxgb4_set_addr_hash(pi); | |
b8ff05a9 | 427 | } |
fc08a01a HS |
428 | out: |
429 | return ret < 0 ? ret : 0; | |
430 | } | |
b8ff05a9 | 431 | |
fc08a01a HS |
432 | static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) |
433 | { | |
434 | struct port_info *pi = netdev_priv(netdev); | |
435 | struct adapter *adap = pi->adapter; | |
436 | int ret; | |
437 | const u8 *maclist[1] = {mac_addr}; | |
438 | struct hash_mac_addr *entry, *tmp; | |
b8ff05a9 | 439 | |
fc08a01a HS |
440 | /* If the MAC address to be removed is in the hash addr |
441 | * list, delete it from the list and update hash vector | |
442 | */ | |
443 | list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { | |
444 | if (ether_addr_equal(entry->addr, mac_addr)) { | |
445 | list_del(&entry->list); | |
446 | kfree(entry); | |
447 | return cxgb4_set_addr_hash(pi); | |
b8ff05a9 DM |
448 | } |
449 | } | |
450 | ||
fc08a01a HS |
451 | ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false); |
452 | return ret < 0 ? -EINVAL : 0; | |
b8ff05a9 DM |
453 | } |
454 | ||
455 | /* | |
456 | * Set Rx properties of a port, such as promiscruity, address filters, and MTU. | |
457 | * If @mtu is -1 it is left unchanged. | |
458 | */ | |
459 | static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) | |
460 | { | |
b8ff05a9 | 461 | struct port_info *pi = netdev_priv(dev); |
fc08a01a | 462 | struct adapter *adapter = pi->adapter; |
b8ff05a9 | 463 | |
d01f7abc HS |
464 | __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); |
465 | __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); | |
fc08a01a HS |
466 | |
467 | return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, | |
468 | (dev->flags & IFF_PROMISC) ? 1 : 0, | |
469 | (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, | |
470 | sleep_ok); | |
b8ff05a9 DM |
471 | } |
472 | ||
473 | /** | |
474 | * link_start - enable a port | |
475 | * @dev: the port to enable | |
476 | * | |
477 | * Performs the MAC and PHY actions needed to enable a port. | |
478 | */ | |
479 | static int link_start(struct net_device *dev) | |
480 | { | |
481 | int ret; | |
482 | struct port_info *pi = netdev_priv(dev); | |
b2612722 | 483 | unsigned int mb = pi->adapter->pf; |
b8ff05a9 DM |
484 | |
485 | /* | |
486 | * We do not set address filters and promiscuity here, the stack does | |
487 | * that step explicitly. | |
488 | */ | |
060e0c75 | 489 | ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, |
f646968f | 490 | !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); |
b8ff05a9 | 491 | if (ret == 0) { |
060e0c75 | 492 | ret = t4_change_mac(pi->adapter, mb, pi->viid, |
b8ff05a9 | 493 | pi->xact_addr_filt, dev->dev_addr, true, |
b6bd29e7 | 494 | true); |
b8ff05a9 DM |
495 | if (ret >= 0) { |
496 | pi->xact_addr_filt = ret; | |
497 | ret = 0; | |
498 | } | |
499 | } | |
500 | if (ret == 0) | |
4036da90 | 501 | ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, |
060e0c75 | 502 | &pi->link_cfg); |
30f00847 AB |
503 | if (ret == 0) { |
504 | local_bh_disable(); | |
688848b1 AB |
505 | ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true, |
506 | true, CXGB4_DCB_ENABLED); | |
30f00847 AB |
507 | local_bh_enable(); |
508 | } | |
688848b1 | 509 | |
b8ff05a9 DM |
510 | return ret; |
511 | } | |
512 | ||
688848b1 AB |
513 | #ifdef CONFIG_CHELSIO_T4_DCB |
514 | /* Handle a Data Center Bridging update message from the firmware. */ | |
515 | static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) | |
516 | { | |
2b5fb1f2 | 517 | int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); |
134491fd | 518 | struct net_device *dev = adap->port[adap->chan_map[port]]; |
688848b1 AB |
519 | int old_dcb_enabled = cxgb4_dcb_enabled(dev); |
520 | int new_dcb_enabled; | |
521 | ||
522 | cxgb4_dcb_handle_fw_update(adap, pcmd); | |
523 | new_dcb_enabled = cxgb4_dcb_enabled(dev); | |
524 | ||
525 | /* If the DCB has become enabled or disabled on the port then we're | |
526 | * going to need to set up/tear down DCB Priority parameters for the | |
527 | * TX Queues associated with the port. | |
528 | */ | |
529 | if (new_dcb_enabled != old_dcb_enabled) | |
530 | dcb_tx_queue_prio_enable(dev, new_dcb_enabled); | |
531 | } | |
532 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
533 | ||
f2b7e78d VP |
534 | /* Clear a filter and release any of its resources that we own. This also |
535 | * clears the filter's "pending" status. | |
536 | */ | |
537 | static void clear_filter(struct adapter *adap, struct filter_entry *f) | |
538 | { | |
539 | /* If the new or old filter have loopback rewriteing rules then we'll | |
540 | * need to free any existing Layer Two Table (L2T) entries of the old | |
541 | * filter rule. The firmware will handle freeing up any Source MAC | |
542 | * Table (SMT) entries used for rewriting Source MAC Addresses in | |
543 | * loopback rules. | |
544 | */ | |
545 | if (f->l2t) | |
546 | cxgb4_l2t_release(f->l2t); | |
547 | ||
548 | /* The zeroing of the filter rule below clears the filter valid, | |
549 | * pending, locked flags, l2t pointer, etc. so it's all we need for | |
550 | * this operation. | |
551 | */ | |
552 | memset(f, 0, sizeof(*f)); | |
553 | } | |
554 | ||
555 | /* Handle a filter write/deletion reply. | |
556 | */ | |
557 | static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl) | |
558 | { | |
559 | unsigned int idx = GET_TID(rpl); | |
560 | unsigned int nidx = idx - adap->tids.ftid_base; | |
561 | unsigned int ret; | |
562 | struct filter_entry *f; | |
563 | ||
564 | if (idx >= adap->tids.ftid_base && nidx < | |
565 | (adap->tids.nftids + adap->tids.nsftids)) { | |
566 | idx = nidx; | |
bdc590b9 | 567 | ret = TCB_COOKIE_G(rpl->cookie); |
f2b7e78d VP |
568 | f = &adap->tids.ftid_tab[idx]; |
569 | ||
570 | if (ret == FW_FILTER_WR_FLT_DELETED) { | |
571 | /* Clear the filter when we get confirmation from the | |
572 | * hardware that the filter has been deleted. | |
573 | */ | |
574 | clear_filter(adap, f); | |
575 | } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) { | |
576 | dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n", | |
577 | idx); | |
578 | clear_filter(adap, f); | |
579 | } else if (ret == FW_FILTER_WR_FLT_ADDED) { | |
580 | f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff; | |
581 | f->pending = 0; /* asynchronous setup completed */ | |
582 | f->valid = 1; | |
583 | } else { | |
584 | /* Something went wrong. Issue a warning about the | |
585 | * problem and clear everything out. | |
586 | */ | |
587 | dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n", | |
588 | idx, ret); | |
589 | clear_filter(adap, f); | |
590 | } | |
591 | } | |
592 | } | |
593 | ||
594 | /* Response queue handler for the FW event queue. | |
b8ff05a9 DM |
595 | */ |
596 | static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, | |
597 | const struct pkt_gl *gl) | |
598 | { | |
599 | u8 opcode = ((const struct rss_header *)rsp)->opcode; | |
600 | ||
601 | rsp++; /* skip RSS header */ | |
b407a4a9 VP |
602 | |
603 | /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. | |
604 | */ | |
605 | if (unlikely(opcode == CPL_FW4_MSG && | |
606 | ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { | |
607 | rsp++; | |
608 | opcode = ((const struct rss_header *)rsp)->opcode; | |
609 | rsp++; | |
610 | if (opcode != CPL_SGE_EGR_UPDATE) { | |
611 | dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" | |
612 | , opcode); | |
613 | goto out; | |
614 | } | |
615 | } | |
616 | ||
b8ff05a9 DM |
617 | if (likely(opcode == CPL_SGE_EGR_UPDATE)) { |
618 | const struct cpl_sge_egr_update *p = (void *)rsp; | |
bdc590b9 | 619 | unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); |
e46dab4d | 620 | struct sge_txq *txq; |
b8ff05a9 | 621 | |
e46dab4d | 622 | txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; |
b8ff05a9 | 623 | txq->restarts++; |
e46dab4d | 624 | if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) { |
b8ff05a9 DM |
625 | struct sge_eth_txq *eq; |
626 | ||
627 | eq = container_of(txq, struct sge_eth_txq, q); | |
628 | netif_tx_wake_queue(eq->txq); | |
629 | } else { | |
630 | struct sge_ofld_txq *oq; | |
631 | ||
632 | oq = container_of(txq, struct sge_ofld_txq, q); | |
633 | tasklet_schedule(&oq->qresume_tsk); | |
634 | } | |
635 | } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { | |
636 | const struct cpl_fw6_msg *p = (void *)rsp; | |
637 | ||
688848b1 AB |
638 | #ifdef CONFIG_CHELSIO_T4_DCB |
639 | const struct fw_port_cmd *pcmd = (const void *)p->data; | |
e2ac9628 | 640 | unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); |
688848b1 | 641 | unsigned int action = |
2b5fb1f2 | 642 | FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); |
688848b1 AB |
643 | |
644 | if (cmd == FW_PORT_CMD && | |
645 | action == FW_PORT_ACTION_GET_PORT_INFO) { | |
2b5fb1f2 | 646 | int port = FW_PORT_CMD_PORTID_G( |
688848b1 | 647 | be32_to_cpu(pcmd->op_to_portid)); |
134491fd HS |
648 | struct net_device *dev = |
649 | q->adap->port[q->adap->chan_map[port]]; | |
688848b1 | 650 | int state_input = ((pcmd->u.info.dcbxdis_pkd & |
2b5fb1f2 | 651 | FW_PORT_CMD_DCBXDIS_F) |
688848b1 AB |
652 | ? CXGB4_DCB_INPUT_FW_DISABLED |
653 | : CXGB4_DCB_INPUT_FW_ENABLED); | |
654 | ||
655 | cxgb4_dcb_state_fsm(dev, state_input); | |
656 | } | |
657 | ||
658 | if (cmd == FW_PORT_CMD && | |
659 | action == FW_PORT_ACTION_L2_DCB_CFG) | |
660 | dcb_rpl(q->adap, pcmd); | |
661 | else | |
662 | #endif | |
663 | if (p->type == 0) | |
664 | t4_handle_fw_rpl(q->adap, p->data); | |
b8ff05a9 DM |
665 | } else if (opcode == CPL_L2T_WRITE_RPL) { |
666 | const struct cpl_l2t_write_rpl *p = (void *)rsp; | |
667 | ||
668 | do_l2t_write_rpl(q->adap, p); | |
f2b7e78d VP |
669 | } else if (opcode == CPL_SET_TCB_RPL) { |
670 | const struct cpl_set_tcb_rpl *p = (void *)rsp; | |
671 | ||
672 | filter_rpl(q->adap, p); | |
b8ff05a9 DM |
673 | } else |
674 | dev_err(q->adap->pdev_dev, | |
675 | "unexpected CPL %#x on FW event queue\n", opcode); | |
b407a4a9 | 676 | out: |
b8ff05a9 DM |
677 | return 0; |
678 | } | |
679 | ||
2337ba42 VP |
680 | /* Flush the aggregated lro sessions */ |
681 | static void uldrx_flush_handler(struct sge_rspq *q) | |
682 | { | |
683 | if (ulds[q->uld].lro_flush) | |
684 | ulds[q->uld].lro_flush(&q->lro_mgr); | |
685 | } | |
686 | ||
b8ff05a9 DM |
687 | /** |
688 | * uldrx_handler - response queue handler for ULD queues | |
689 | * @q: the response queue that received the packet | |
690 | * @rsp: the response queue descriptor holding the offload message | |
691 | * @gl: the gather list of packet fragments | |
692 | * | |
693 | * Deliver an ingress offload packet to a ULD. All processing is done by | |
694 | * the ULD, we just maintain statistics. | |
695 | */ | |
696 | static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp, | |
697 | const struct pkt_gl *gl) | |
698 | { | |
699 | struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq); | |
2337ba42 | 700 | int ret; |
b8ff05a9 | 701 | |
b407a4a9 VP |
702 | /* FW can send CPLs encapsulated in a CPL_FW4_MSG. |
703 | */ | |
704 | if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG && | |
705 | ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL) | |
706 | rsp += 2; | |
707 | ||
2337ba42 VP |
708 | if (q->flush_handler) |
709 | ret = ulds[q->uld].lro_rx_handler(q->adap->uld_handle[q->uld], | |
710 | rsp, gl, &q->lro_mgr, | |
711 | &q->napi); | |
712 | else | |
713 | ret = ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], | |
714 | rsp, gl); | |
715 | ||
716 | if (ret) { | |
b8ff05a9 DM |
717 | rxq->stats.nomem++; |
718 | return -1; | |
719 | } | |
2337ba42 | 720 | |
b8ff05a9 DM |
721 | if (gl == NULL) |
722 | rxq->stats.imm++; | |
723 | else if (gl == CXGB4_MSG_AN) | |
724 | rxq->stats.an++; | |
725 | else | |
726 | rxq->stats.pkts++; | |
727 | return 0; | |
728 | } | |
729 | ||
730 | static void disable_msi(struct adapter *adapter) | |
731 | { | |
732 | if (adapter->flags & USING_MSIX) { | |
733 | pci_disable_msix(adapter->pdev); | |
734 | adapter->flags &= ~USING_MSIX; | |
735 | } else if (adapter->flags & USING_MSI) { | |
736 | pci_disable_msi(adapter->pdev); | |
737 | adapter->flags &= ~USING_MSI; | |
738 | } | |
739 | } | |
740 | ||
741 | /* | |
742 | * Interrupt handler for non-data events used with MSI-X. | |
743 | */ | |
744 | static irqreturn_t t4_nondata_intr(int irq, void *cookie) | |
745 | { | |
746 | struct adapter *adap = cookie; | |
0d804338 | 747 | u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); |
b8ff05a9 | 748 | |
0d804338 | 749 | if (v & PFSW_F) { |
b8ff05a9 | 750 | adap->swintr = 1; |
0d804338 | 751 | t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); |
b8ff05a9 | 752 | } |
c3c7b121 HS |
753 | if (adap->flags & MASTER_PF) |
754 | t4_slow_intr_handler(adap); | |
b8ff05a9 DM |
755 | return IRQ_HANDLED; |
756 | } | |
757 | ||
758 | /* | |
759 | * Name the MSI-X interrupts. | |
760 | */ | |
761 | static void name_msix_vecs(struct adapter *adap) | |
762 | { | |
ba27816c | 763 | int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); |
b8ff05a9 DM |
764 | |
765 | /* non-data interrupts */ | |
b1a3c2b6 | 766 | snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); |
b8ff05a9 DM |
767 | |
768 | /* FW events */ | |
b1a3c2b6 DM |
769 | snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", |
770 | adap->port[0]->name); | |
b8ff05a9 DM |
771 | |
772 | /* Ethernet queues */ | |
773 | for_each_port(adap, j) { | |
774 | struct net_device *d = adap->port[j]; | |
775 | const struct port_info *pi = netdev_priv(d); | |
776 | ||
ba27816c | 777 | for (i = 0; i < pi->nqsets; i++, msi_idx++) |
b8ff05a9 DM |
778 | snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", |
779 | d->name, i); | |
b8ff05a9 DM |
780 | } |
781 | ||
782 | /* offload queues */ | |
f90ce561 HS |
783 | for_each_iscsirxq(&adap->sge, i) |
784 | snprintf(adap->msix_info[msi_idx++].desc, n, "%s-iscsi%d", | |
b1a3c2b6 | 785 | adap->port[0]->name, i); |
ba27816c | 786 | |
f2692d16 VP |
787 | for_each_iscsitrxq(&adap->sge, i) |
788 | snprintf(adap->msix_info[msi_idx++].desc, n, "%s-iSCSIT%d", | |
789 | adap->port[0]->name, i); | |
790 | ||
ba27816c DM |
791 | for_each_rdmarxq(&adap->sge, i) |
792 | snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d", | |
b1a3c2b6 | 793 | adap->port[0]->name, i); |
cf38be6d HS |
794 | |
795 | for_each_rdmaciq(&adap->sge, i) | |
796 | snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d", | |
797 | adap->port[0]->name, i); | |
b8ff05a9 DM |
798 | } |
799 | ||
800 | static int request_msix_queue_irqs(struct adapter *adap) | |
801 | { | |
802 | struct sge *s = &adap->sge; | |
f90ce561 | 803 | int err, ethqidx, iscsiqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0; |
f2692d16 | 804 | int iscsitqidx = 0; |
cf38be6d | 805 | int msi_index = 2; |
b8ff05a9 DM |
806 | |
807 | err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, | |
808 | adap->msix_info[1].desc, &s->fw_evtq); | |
809 | if (err) | |
810 | return err; | |
811 | ||
812 | for_each_ethrxq(s, ethqidx) { | |
404d9e3f VP |
813 | err = request_irq(adap->msix_info[msi_index].vec, |
814 | t4_sge_intr_msix, 0, | |
815 | adap->msix_info[msi_index].desc, | |
b8ff05a9 DM |
816 | &s->ethrxq[ethqidx].rspq); |
817 | if (err) | |
818 | goto unwind; | |
404d9e3f | 819 | msi_index++; |
b8ff05a9 | 820 | } |
f90ce561 | 821 | for_each_iscsirxq(s, iscsiqidx) { |
404d9e3f VP |
822 | err = request_irq(adap->msix_info[msi_index].vec, |
823 | t4_sge_intr_msix, 0, | |
824 | adap->msix_info[msi_index].desc, | |
f90ce561 | 825 | &s->iscsirxq[iscsiqidx].rspq); |
b8ff05a9 DM |
826 | if (err) |
827 | goto unwind; | |
404d9e3f | 828 | msi_index++; |
b8ff05a9 | 829 | } |
f2692d16 VP |
830 | for_each_iscsitrxq(s, iscsitqidx) { |
831 | err = request_irq(adap->msix_info[msi_index].vec, | |
832 | t4_sge_intr_msix, 0, | |
833 | adap->msix_info[msi_index].desc, | |
834 | &s->iscsitrxq[iscsitqidx].rspq); | |
835 | if (err) | |
836 | goto unwind; | |
837 | msi_index++; | |
838 | } | |
b8ff05a9 | 839 | for_each_rdmarxq(s, rdmaqidx) { |
404d9e3f VP |
840 | err = request_irq(adap->msix_info[msi_index].vec, |
841 | t4_sge_intr_msix, 0, | |
842 | adap->msix_info[msi_index].desc, | |
b8ff05a9 DM |
843 | &s->rdmarxq[rdmaqidx].rspq); |
844 | if (err) | |
845 | goto unwind; | |
404d9e3f | 846 | msi_index++; |
b8ff05a9 | 847 | } |
cf38be6d HS |
848 | for_each_rdmaciq(s, rdmaciqqidx) { |
849 | err = request_irq(adap->msix_info[msi_index].vec, | |
850 | t4_sge_intr_msix, 0, | |
851 | adap->msix_info[msi_index].desc, | |
852 | &s->rdmaciq[rdmaciqqidx].rspq); | |
853 | if (err) | |
854 | goto unwind; | |
855 | msi_index++; | |
856 | } | |
b8ff05a9 DM |
857 | return 0; |
858 | ||
859 | unwind: | |
cf38be6d HS |
860 | while (--rdmaciqqidx >= 0) |
861 | free_irq(adap->msix_info[--msi_index].vec, | |
862 | &s->rdmaciq[rdmaciqqidx].rspq); | |
b8ff05a9 | 863 | while (--rdmaqidx >= 0) |
404d9e3f | 864 | free_irq(adap->msix_info[--msi_index].vec, |
b8ff05a9 | 865 | &s->rdmarxq[rdmaqidx].rspq); |
f2692d16 VP |
866 | while (--iscsitqidx >= 0) |
867 | free_irq(adap->msix_info[--msi_index].vec, | |
868 | &s->iscsitrxq[iscsitqidx].rspq); | |
f90ce561 | 869 | while (--iscsiqidx >= 0) |
404d9e3f | 870 | free_irq(adap->msix_info[--msi_index].vec, |
f90ce561 | 871 | &s->iscsirxq[iscsiqidx].rspq); |
b8ff05a9 | 872 | while (--ethqidx >= 0) |
404d9e3f VP |
873 | free_irq(adap->msix_info[--msi_index].vec, |
874 | &s->ethrxq[ethqidx].rspq); | |
b8ff05a9 DM |
875 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); |
876 | return err; | |
877 | } | |
878 | ||
879 | static void free_msix_queue_irqs(struct adapter *adap) | |
880 | { | |
404d9e3f | 881 | int i, msi_index = 2; |
b8ff05a9 DM |
882 | struct sge *s = &adap->sge; |
883 | ||
884 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); | |
885 | for_each_ethrxq(s, i) | |
404d9e3f | 886 | free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); |
f90ce561 HS |
887 | for_each_iscsirxq(s, i) |
888 | free_irq(adap->msix_info[msi_index++].vec, | |
889 | &s->iscsirxq[i].rspq); | |
f2692d16 VP |
890 | for_each_iscsitrxq(s, i) |
891 | free_irq(adap->msix_info[msi_index++].vec, | |
892 | &s->iscsitrxq[i].rspq); | |
b8ff05a9 | 893 | for_each_rdmarxq(s, i) |
404d9e3f | 894 | free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq); |
cf38be6d HS |
895 | for_each_rdmaciq(s, i) |
896 | free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq); | |
b8ff05a9 DM |
897 | } |
898 | ||
671b0060 | 899 | /** |
812034f1 | 900 | * cxgb4_write_rss - write the RSS table for a given port |
671b0060 DM |
901 | * @pi: the port |
902 | * @queues: array of queue indices for RSS | |
903 | * | |
904 | * Sets up the portion of the HW RSS table for the port's VI to distribute | |
905 | * packets to the Rx queues in @queues. | |
c035e183 | 906 | * Should never be called before setting up sge eth rx queues |
671b0060 | 907 | */ |
812034f1 | 908 | int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) |
671b0060 DM |
909 | { |
910 | u16 *rss; | |
911 | int i, err; | |
c035e183 HS |
912 | struct adapter *adapter = pi->adapter; |
913 | const struct sge_eth_rxq *rxq; | |
671b0060 | 914 | |
c035e183 | 915 | rxq = &adapter->sge.ethrxq[pi->first_qset]; |
671b0060 DM |
916 | rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL); |
917 | if (!rss) | |
918 | return -ENOMEM; | |
919 | ||
920 | /* map the queue indices to queue ids */ | |
921 | for (i = 0; i < pi->rss_size; i++, queues++) | |
c035e183 | 922 | rss[i] = rxq[*queues].rspq.abs_id; |
671b0060 | 923 | |
b2612722 | 924 | err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, |
060e0c75 | 925 | pi->rss_size, rss, pi->rss_size); |
c035e183 HS |
926 | /* If Tunnel All Lookup isn't specified in the global RSS |
927 | * Configuration, then we need to specify a default Ingress | |
928 | * Queue for any ingress packets which aren't hashed. We'll | |
929 | * use our first ingress queue ... | |
930 | */ | |
931 | if (!err) | |
932 | err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, | |
933 | FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | | |
934 | FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | | |
935 | FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | | |
936 | FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | | |
937 | FW_RSS_VI_CONFIG_CMD_UDPEN_F, | |
938 | rss[0]); | |
671b0060 DM |
939 | kfree(rss); |
940 | return err; | |
941 | } | |
942 | ||
b8ff05a9 DM |
943 | /** |
944 | * setup_rss - configure RSS | |
945 | * @adap: the adapter | |
946 | * | |
671b0060 | 947 | * Sets up RSS for each port. |
b8ff05a9 DM |
948 | */ |
949 | static int setup_rss(struct adapter *adap) | |
950 | { | |
c035e183 | 951 | int i, j, err; |
b8ff05a9 DM |
952 | |
953 | for_each_port(adap, i) { | |
954 | const struct port_info *pi = adap2pinfo(adap, i); | |
b8ff05a9 | 955 | |
c035e183 HS |
956 | /* Fill default values with equal distribution */ |
957 | for (j = 0; j < pi->rss_size; j++) | |
958 | pi->rss[j] = j % pi->nqsets; | |
959 | ||
812034f1 | 960 | err = cxgb4_write_rss(pi, pi->rss); |
b8ff05a9 DM |
961 | if (err) |
962 | return err; | |
963 | } | |
964 | return 0; | |
965 | } | |
966 | ||
e46dab4d DM |
967 | /* |
968 | * Return the channel of the ingress queue with the given qid. | |
969 | */ | |
970 | static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) | |
971 | { | |
972 | qid -= p->ingr_start; | |
973 | return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; | |
974 | } | |
975 | ||
b8ff05a9 DM |
976 | /* |
977 | * Wait until all NAPI handlers are descheduled. | |
978 | */ | |
979 | static void quiesce_rx(struct adapter *adap) | |
980 | { | |
981 | int i; | |
982 | ||
4b8e27a8 | 983 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
984 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
985 | ||
3a336cb1 | 986 | if (q && q->handler) { |
b8ff05a9 | 987 | napi_disable(&q->napi); |
3a336cb1 HS |
988 | local_bh_disable(); |
989 | while (!cxgb_poll_lock_napi(q)) | |
990 | mdelay(1); | |
991 | local_bh_enable(); | |
992 | } | |
993 | ||
b8ff05a9 DM |
994 | } |
995 | } | |
996 | ||
b37987e8 HS |
997 | /* Disable interrupt and napi handler */ |
998 | static void disable_interrupts(struct adapter *adap) | |
999 | { | |
1000 | if (adap->flags & FULL_INIT_DONE) { | |
1001 | t4_intr_disable(adap); | |
1002 | if (adap->flags & USING_MSIX) { | |
1003 | free_msix_queue_irqs(adap); | |
1004 | free_irq(adap->msix_info[0].vec, adap); | |
1005 | } else { | |
1006 | free_irq(adap->pdev->irq, adap); | |
1007 | } | |
1008 | quiesce_rx(adap); | |
1009 | } | |
1010 | } | |
1011 | ||
b8ff05a9 DM |
1012 | /* |
1013 | * Enable NAPI scheduling and interrupt generation for all Rx queues. | |
1014 | */ | |
1015 | static void enable_rx(struct adapter *adap) | |
1016 | { | |
1017 | int i; | |
1018 | ||
4b8e27a8 | 1019 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
1020 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
1021 | ||
1022 | if (!q) | |
1023 | continue; | |
3a336cb1 HS |
1024 | if (q->handler) { |
1025 | cxgb_busy_poll_init_lock(q); | |
b8ff05a9 | 1026 | napi_enable(&q->napi); |
3a336cb1 | 1027 | } |
b8ff05a9 | 1028 | /* 0-increment GTS to start the timer and enable interrupts */ |
f612b815 HS |
1029 | t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), |
1030 | SEINTARM_V(q->intr_params) | | |
1031 | INGRESSQID_V(q->cntxt_id)); | |
b8ff05a9 DM |
1032 | } |
1033 | } | |
1034 | ||
1c6a5b0e HS |
1035 | static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q, |
1036 | unsigned int nq, unsigned int per_chan, int msi_idx, | |
2337ba42 | 1037 | u16 *ids, bool lro) |
1c6a5b0e HS |
1038 | { |
1039 | int i, err; | |
1040 | ||
1041 | for (i = 0; i < nq; i++, q++) { | |
1042 | if (msi_idx > 0) | |
1043 | msi_idx++; | |
1044 | err = t4_sge_alloc_rxq(adap, &q->rspq, false, | |
1045 | adap->port[i / per_chan], | |
1046 | msi_idx, q->fl.size ? &q->fl : NULL, | |
2337ba42 VP |
1047 | uldrx_handler, |
1048 | lro ? uldrx_flush_handler : NULL, | |
1049 | 0); | |
1c6a5b0e HS |
1050 | if (err) |
1051 | return err; | |
1052 | memset(&q->stats, 0, sizeof(q->stats)); | |
1053 | if (ids) | |
1054 | ids[i] = q->rspq.abs_id; | |
1055 | } | |
1056 | return 0; | |
1057 | } | |
1058 | ||
b8ff05a9 DM |
1059 | /** |
1060 | * setup_sge_queues - configure SGE Tx/Rx/response queues | |
1061 | * @adap: the adapter | |
1062 | * | |
1063 | * Determines how many sets of SGE queues to use and initializes them. | |
1064 | * We support multiple queue sets per port if we have MSI-X, otherwise | |
1065 | * just one queue set per port. | |
1066 | */ | |
1067 | static int setup_sge_queues(struct adapter *adap) | |
1068 | { | |
1069 | int err, msi_idx, i, j; | |
1070 | struct sge *s = &adap->sge; | |
1071 | ||
4b8e27a8 HS |
1072 | bitmap_zero(s->starving_fl, s->egr_sz); |
1073 | bitmap_zero(s->txq_maperr, s->egr_sz); | |
b8ff05a9 DM |
1074 | |
1075 | if (adap->flags & USING_MSIX) | |
1076 | msi_idx = 1; /* vector 0 is for non-queue interrupts */ | |
1077 | else { | |
1078 | err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, | |
2337ba42 | 1079 | NULL, NULL, NULL, -1); |
b8ff05a9 DM |
1080 | if (err) |
1081 | return err; | |
1082 | msi_idx = -((int)s->intrq.abs_id + 1); | |
1083 | } | |
1084 | ||
4b8e27a8 HS |
1085 | /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here, |
1086 | * don't forget to update the following which need to be | |
1087 | * synchronized to and changes here. | |
1088 | * | |
1089 | * 1. The calculations of MAX_INGQ in cxgb4.h. | |
1090 | * | |
1091 | * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs | |
1092 | * to accommodate any new/deleted Ingress Queues | |
1093 | * which need MSI-X Vectors. | |
1094 | * | |
1095 | * 3. Update sge_qinfo_show() to include information on the | |
1096 | * new/deleted queues. | |
1097 | */ | |
b8ff05a9 | 1098 | err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], |
2337ba42 | 1099 | msi_idx, NULL, fwevtq_handler, NULL, -1); |
b8ff05a9 DM |
1100 | if (err) { |
1101 | freeout: t4_free_sge_resources(adap); | |
1102 | return err; | |
1103 | } | |
1104 | ||
1105 | for_each_port(adap, i) { | |
1106 | struct net_device *dev = adap->port[i]; | |
1107 | struct port_info *pi = netdev_priv(dev); | |
1108 | struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; | |
1109 | struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; | |
1110 | ||
1111 | for (j = 0; j < pi->nqsets; j++, q++) { | |
1112 | if (msi_idx > 0) | |
1113 | msi_idx++; | |
1114 | err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, | |
1115 | msi_idx, &q->fl, | |
145ef8a5 | 1116 | t4_ethrx_handler, |
2337ba42 | 1117 | NULL, |
145ef8a5 HS |
1118 | t4_get_mps_bg_map(adap, |
1119 | pi->tx_chan)); | |
b8ff05a9 DM |
1120 | if (err) |
1121 | goto freeout; | |
1122 | q->rspq.idx = j; | |
1123 | memset(&q->stats, 0, sizeof(q->stats)); | |
1124 | } | |
1125 | for (j = 0; j < pi->nqsets; j++, t++) { | |
1126 | err = t4_sge_alloc_eth_txq(adap, t, dev, | |
1127 | netdev_get_tx_queue(dev, j), | |
1128 | s->fw_evtq.cntxt_id); | |
1129 | if (err) | |
1130 | goto freeout; | |
1131 | } | |
1132 | } | |
1133 | ||
f90ce561 HS |
1134 | j = s->iscsiqsets / adap->params.nports; /* iscsi queues per channel */ |
1135 | for_each_iscsirxq(s, i) { | |
1c6a5b0e HS |
1136 | err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], |
1137 | adap->port[i / j], | |
b8ff05a9 DM |
1138 | s->fw_evtq.cntxt_id); |
1139 | if (err) | |
1140 | goto freeout; | |
1141 | } | |
1142 | ||
2337ba42 VP |
1143 | #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids, lro) do { \ |
1144 | err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids, lro); \ | |
1c6a5b0e HS |
1145 | if (err) \ |
1146 | goto freeout; \ | |
1147 | if (msi_idx > 0) \ | |
1148 | msi_idx += nq; \ | |
1149 | } while (0) | |
b8ff05a9 | 1150 | |
2337ba42 VP |
1151 | ALLOC_OFLD_RXQS(s->iscsirxq, s->iscsiqsets, j, s->iscsi_rxq, false); |
1152 | ALLOC_OFLD_RXQS(s->iscsitrxq, s->niscsitq, j, s->iscsit_rxq, true); | |
1153 | ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq, false); | |
f36e58e5 | 1154 | j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */ |
2337ba42 | 1155 | ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq, false); |
b8ff05a9 | 1156 | |
1c6a5b0e | 1157 | #undef ALLOC_OFLD_RXQS |
cf38be6d | 1158 | |
b8ff05a9 DM |
1159 | for_each_port(adap, i) { |
1160 | /* | |
1161 | * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't | |
1162 | * have RDMA queues, and that's the right value. | |
1163 | */ | |
1164 | err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], | |
1165 | s->fw_evtq.cntxt_id, | |
1166 | s->rdmarxq[i].rspq.cntxt_id); | |
1167 | if (err) | |
1168 | goto freeout; | |
1169 | } | |
1170 | ||
9bb59b96 | 1171 | t4_write_reg(adap, is_t4(adap->params.chip) ? |
837e4a42 HS |
1172 | MPS_TRC_RSS_CONTROL_A : |
1173 | MPS_T5_TRC_RSS_CONTROL_A, | |
1174 | RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | | |
1175 | QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); | |
b8ff05a9 DM |
1176 | return 0; |
1177 | } | |
1178 | ||
b8ff05a9 DM |
1179 | /* |
1180 | * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc. | |
1181 | * The allocated memory is cleared. | |
1182 | */ | |
1183 | void *t4_alloc_mem(size_t size) | |
1184 | { | |
8be04b93 | 1185 | void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); |
b8ff05a9 DM |
1186 | |
1187 | if (!p) | |
89bf67f1 | 1188 | p = vzalloc(size); |
b8ff05a9 DM |
1189 | return p; |
1190 | } | |
1191 | ||
1192 | /* | |
1193 | * Free memory allocated through alloc_mem(). | |
1194 | */ | |
fd88b31a | 1195 | void t4_free_mem(void *addr) |
b8ff05a9 | 1196 | { |
d2fcb548 | 1197 | kvfree(addr); |
b8ff05a9 DM |
1198 | } |
1199 | ||
f2b7e78d VP |
1200 | /* Send a Work Request to write the filter at a specified index. We construct |
1201 | * a Firmware Filter Work Request to have the work done and put the indicated | |
1202 | * filter into "pending" mode which will prevent any further actions against | |
1203 | * it till we get a reply from the firmware on the completion status of the | |
1204 | * request. | |
1205 | */ | |
1206 | static int set_filter_wr(struct adapter *adapter, int fidx) | |
1207 | { | |
1208 | struct filter_entry *f = &adapter->tids.ftid_tab[fidx]; | |
1209 | struct sk_buff *skb; | |
1210 | struct fw_filter_wr *fwr; | |
1211 | unsigned int ftid; | |
1212 | ||
f72f116a MH |
1213 | skb = alloc_skb(sizeof(*fwr), GFP_KERNEL); |
1214 | if (!skb) | |
1215 | return -ENOMEM; | |
1216 | ||
f2b7e78d VP |
1217 | /* If the new filter requires loopback Destination MAC and/or VLAN |
1218 | * rewriting then we need to allocate a Layer 2 Table (L2T) entry for | |
1219 | * the filter. | |
1220 | */ | |
1221 | if (f->fs.newdmac || f->fs.newvlan) { | |
1222 | /* allocate L2T entry for new filter */ | |
f7502659 HS |
1223 | f->l2t = t4_l2t_alloc_switching(adapter, f->fs.vlan, |
1224 | f->fs.eport, f->fs.dmac); | |
f72f116a | 1225 | if (f->l2t == NULL) { |
f72f116a | 1226 | kfree_skb(skb); |
f2b7e78d VP |
1227 | return -ENOMEM; |
1228 | } | |
1229 | } | |
1230 | ||
1231 | ftid = adapter->tids.ftid_base + fidx; | |
1232 | ||
f2b7e78d VP |
1233 | fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr)); |
1234 | memset(fwr, 0, sizeof(*fwr)); | |
1235 | ||
1236 | /* It would be nice to put most of the following in t4_hw.c but most | |
1237 | * of the work is translating the cxgbtool ch_filter_specification | |
1238 | * into the Work Request and the definition of that structure is | |
1239 | * currently in cxgbtool.h which isn't appropriate to pull into the | |
1240 | * common code. We may eventually try to come up with a more neutral | |
1241 | * filter specification structure but for now it's easiest to simply | |
1242 | * put this fairly direct code in line ... | |
1243 | */ | |
e2ac9628 HS |
1244 | fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR)); |
1245 | fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16)); | |
f2b7e78d | 1246 | fwr->tid_to_iq = |
77a80e23 HS |
1247 | htonl(FW_FILTER_WR_TID_V(ftid) | |
1248 | FW_FILTER_WR_RQTYPE_V(f->fs.type) | | |
1249 | FW_FILTER_WR_NOREPLY_V(0) | | |
1250 | FW_FILTER_WR_IQ_V(f->fs.iq)); | |
f2b7e78d | 1251 | fwr->del_filter_to_l2tix = |
77a80e23 HS |
1252 | htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) | |
1253 | FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) | | |
1254 | FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) | | |
1255 | FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) | | |
1256 | FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) | | |
1257 | FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) | | |
1258 | FW_FILTER_WR_DMAC_V(f->fs.newdmac) | | |
1259 | FW_FILTER_WR_SMAC_V(f->fs.newsmac) | | |
1260 | FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT || | |
f2b7e78d | 1261 | f->fs.newvlan == VLAN_REWRITE) | |
77a80e23 | 1262 | FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE || |
f2b7e78d | 1263 | f->fs.newvlan == VLAN_REWRITE) | |
77a80e23 HS |
1264 | FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) | |
1265 | FW_FILTER_WR_TXCHAN_V(f->fs.eport) | | |
1266 | FW_FILTER_WR_PRIO_V(f->fs.prio) | | |
1267 | FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0)); | |
f2b7e78d VP |
1268 | fwr->ethtype = htons(f->fs.val.ethtype); |
1269 | fwr->ethtypem = htons(f->fs.mask.ethtype); | |
1270 | fwr->frag_to_ovlan_vldm = | |
77a80e23 HS |
1271 | (FW_FILTER_WR_FRAG_V(f->fs.val.frag) | |
1272 | FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) | | |
1273 | FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) | | |
1274 | FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) | | |
1275 | FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) | | |
1276 | FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld)); | |
f2b7e78d VP |
1277 | fwr->smac_sel = 0; |
1278 | fwr->rx_chan_rx_rpl_iq = | |
77a80e23 HS |
1279 | htons(FW_FILTER_WR_RX_CHAN_V(0) | |
1280 | FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id)); | |
f2b7e78d | 1281 | fwr->maci_to_matchtypem = |
77a80e23 HS |
1282 | htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) | |
1283 | FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) | | |
1284 | FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) | | |
1285 | FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) | | |
1286 | FW_FILTER_WR_PORT_V(f->fs.val.iport) | | |
1287 | FW_FILTER_WR_PORTM_V(f->fs.mask.iport) | | |
1288 | FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) | | |
1289 | FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype)); | |
f2b7e78d VP |
1290 | fwr->ptcl = f->fs.val.proto; |
1291 | fwr->ptclm = f->fs.mask.proto; | |
1292 | fwr->ttyp = f->fs.val.tos; | |
1293 | fwr->ttypm = f->fs.mask.tos; | |
1294 | fwr->ivlan = htons(f->fs.val.ivlan); | |
1295 | fwr->ivlanm = htons(f->fs.mask.ivlan); | |
1296 | fwr->ovlan = htons(f->fs.val.ovlan); | |
1297 | fwr->ovlanm = htons(f->fs.mask.ovlan); | |
1298 | memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip)); | |
1299 | memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm)); | |
1300 | memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip)); | |
1301 | memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm)); | |
1302 | fwr->lp = htons(f->fs.val.lport); | |
1303 | fwr->lpm = htons(f->fs.mask.lport); | |
1304 | fwr->fp = htons(f->fs.val.fport); | |
1305 | fwr->fpm = htons(f->fs.mask.fport); | |
1306 | if (f->fs.newsmac) | |
1307 | memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma)); | |
1308 | ||
1309 | /* Mark the filter as "pending" and ship off the Filter Work Request. | |
1310 | * When we get the Work Request Reply we'll clear the pending status. | |
1311 | */ | |
1312 | f->pending = 1; | |
1313 | set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); | |
1314 | t4_ofld_send(adapter, skb); | |
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | /* Delete the filter at a specified index. | |
1319 | */ | |
1320 | static int del_filter_wr(struct adapter *adapter, int fidx) | |
1321 | { | |
1322 | struct filter_entry *f = &adapter->tids.ftid_tab[fidx]; | |
1323 | struct sk_buff *skb; | |
1324 | struct fw_filter_wr *fwr; | |
1325 | unsigned int len, ftid; | |
1326 | ||
1327 | len = sizeof(*fwr); | |
1328 | ftid = adapter->tids.ftid_base + fidx; | |
1329 | ||
f72f116a MH |
1330 | skb = alloc_skb(len, GFP_KERNEL); |
1331 | if (!skb) | |
1332 | return -ENOMEM; | |
1333 | ||
f2b7e78d VP |
1334 | fwr = (struct fw_filter_wr *)__skb_put(skb, len); |
1335 | t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id); | |
1336 | ||
1337 | /* Mark the filter as "pending" and ship off the Filter Work Request. | |
1338 | * When we get the Work Request Reply we'll clear the pending status. | |
1339 | */ | |
1340 | f->pending = 1; | |
1341 | t4_mgmt_tx(adapter, skb); | |
1342 | return 0; | |
1343 | } | |
1344 | ||
688848b1 AB |
1345 | static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, |
1346 | void *accel_priv, select_queue_fallback_t fallback) | |
1347 | { | |
1348 | int txq; | |
1349 | ||
1350 | #ifdef CONFIG_CHELSIO_T4_DCB | |
1351 | /* If a Data Center Bridging has been successfully negotiated on this | |
1352 | * link then we'll use the skb's priority to map it to a TX Queue. | |
1353 | * The skb's priority is determined via the VLAN Tag Priority Code | |
1354 | * Point field. | |
1355 | */ | |
1356 | if (cxgb4_dcb_enabled(dev)) { | |
1357 | u16 vlan_tci; | |
1358 | int err; | |
1359 | ||
1360 | err = vlan_get_tag(skb, &vlan_tci); | |
1361 | if (unlikely(err)) { | |
1362 | if (net_ratelimit()) | |
1363 | netdev_warn(dev, | |
1364 | "TX Packet without VLAN Tag on DCB Link\n"); | |
1365 | txq = 0; | |
1366 | } else { | |
1367 | txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; | |
84a200b3 VP |
1368 | #ifdef CONFIG_CHELSIO_T4_FCOE |
1369 | if (skb->protocol == htons(ETH_P_FCOE)) | |
1370 | txq = skb->priority & 0x7; | |
1371 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
688848b1 AB |
1372 | } |
1373 | return txq; | |
1374 | } | |
1375 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
1376 | ||
1377 | if (select_queue) { | |
1378 | txq = (skb_rx_queue_recorded(skb) | |
1379 | ? skb_get_rx_queue(skb) | |
1380 | : smp_processor_id()); | |
1381 | ||
1382 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
1383 | txq -= dev->real_num_tx_queues; | |
1384 | ||
1385 | return txq; | |
1386 | } | |
1387 | ||
1388 | return fallback(dev, skb) % dev->real_num_tx_queues; | |
1389 | } | |
1390 | ||
b8ff05a9 DM |
1391 | static int closest_timer(const struct sge *s, int time) |
1392 | { | |
1393 | int i, delta, match = 0, min_delta = INT_MAX; | |
1394 | ||
1395 | for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { | |
1396 | delta = time - s->timer_val[i]; | |
1397 | if (delta < 0) | |
1398 | delta = -delta; | |
1399 | if (delta < min_delta) { | |
1400 | min_delta = delta; | |
1401 | match = i; | |
1402 | } | |
1403 | } | |
1404 | return match; | |
1405 | } | |
1406 | ||
1407 | static int closest_thres(const struct sge *s, int thres) | |
1408 | { | |
1409 | int i, delta, match = 0, min_delta = INT_MAX; | |
1410 | ||
1411 | for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { | |
1412 | delta = thres - s->counter_val[i]; | |
1413 | if (delta < 0) | |
1414 | delta = -delta; | |
1415 | if (delta < min_delta) { | |
1416 | min_delta = delta; | |
1417 | match = i; | |
1418 | } | |
1419 | } | |
1420 | return match; | |
1421 | } | |
1422 | ||
b8ff05a9 | 1423 | /** |
812034f1 | 1424 | * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters |
b8ff05a9 DM |
1425 | * @q: the Rx queue |
1426 | * @us: the hold-off time in us, or 0 to disable timer | |
1427 | * @cnt: the hold-off packet count, or 0 to disable counter | |
1428 | * | |
1429 | * Sets an Rx queue's interrupt hold-off time and packet count. At least | |
1430 | * one of the two needs to be enabled for the queue to generate interrupts. | |
1431 | */ | |
812034f1 HS |
1432 | int cxgb4_set_rspq_intr_params(struct sge_rspq *q, |
1433 | unsigned int us, unsigned int cnt) | |
b8ff05a9 | 1434 | { |
c887ad0e HS |
1435 | struct adapter *adap = q->adap; |
1436 | ||
b8ff05a9 DM |
1437 | if ((us | cnt) == 0) |
1438 | cnt = 1; | |
1439 | ||
1440 | if (cnt) { | |
1441 | int err; | |
1442 | u32 v, new_idx; | |
1443 | ||
1444 | new_idx = closest_thres(&adap->sge, cnt); | |
1445 | if (q->desc && q->pktcnt_idx != new_idx) { | |
1446 | /* the queue has already been created, update it */ | |
5167865a HS |
1447 | v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
1448 | FW_PARAMS_PARAM_X_V( | |
1449 | FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | | |
1450 | FW_PARAMS_PARAM_YZ_V(q->cntxt_id); | |
b2612722 HS |
1451 | err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, |
1452 | &v, &new_idx); | |
b8ff05a9 DM |
1453 | if (err) |
1454 | return err; | |
1455 | } | |
1456 | q->pktcnt_idx = new_idx; | |
1457 | } | |
1458 | ||
1459 | us = us == 0 ? 6 : closest_timer(&adap->sge, us); | |
1ecc7b7a | 1460 | q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); |
b8ff05a9 DM |
1461 | return 0; |
1462 | } | |
1463 | ||
c8f44aff | 1464 | static int cxgb_set_features(struct net_device *dev, netdev_features_t features) |
87b6cf51 | 1465 | { |
2ed28baa | 1466 | const struct port_info *pi = netdev_priv(dev); |
c8f44aff | 1467 | netdev_features_t changed = dev->features ^ features; |
19ecae2c | 1468 | int err; |
19ecae2c | 1469 | |
f646968f | 1470 | if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) |
2ed28baa | 1471 | return 0; |
19ecae2c | 1472 | |
b2612722 | 1473 | err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, |
2ed28baa | 1474 | -1, -1, -1, |
f646968f | 1475 | !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); |
2ed28baa | 1476 | if (unlikely(err)) |
f646968f | 1477 | dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; |
19ecae2c | 1478 | return err; |
87b6cf51 DM |
1479 | } |
1480 | ||
91744948 | 1481 | static int setup_debugfs(struct adapter *adap) |
b8ff05a9 | 1482 | { |
b8ff05a9 DM |
1483 | if (IS_ERR_OR_NULL(adap->debugfs_root)) |
1484 | return -1; | |
1485 | ||
fd88b31a HS |
1486 | #ifdef CONFIG_DEBUG_FS |
1487 | t4_setup_debugfs(adap); | |
1488 | #endif | |
b8ff05a9 DM |
1489 | return 0; |
1490 | } | |
1491 | ||
1492 | /* | |
1493 | * upper-layer driver support | |
1494 | */ | |
1495 | ||
1496 | /* | |
1497 | * Allocate an active-open TID and set it to the supplied value. | |
1498 | */ | |
1499 | int cxgb4_alloc_atid(struct tid_info *t, void *data) | |
1500 | { | |
1501 | int atid = -1; | |
1502 | ||
1503 | spin_lock_bh(&t->atid_lock); | |
1504 | if (t->afree) { | |
1505 | union aopen_entry *p = t->afree; | |
1506 | ||
f2b7e78d | 1507 | atid = (p - t->atid_tab) + t->atid_base; |
b8ff05a9 DM |
1508 | t->afree = p->next; |
1509 | p->data = data; | |
1510 | t->atids_in_use++; | |
1511 | } | |
1512 | spin_unlock_bh(&t->atid_lock); | |
1513 | return atid; | |
1514 | } | |
1515 | EXPORT_SYMBOL(cxgb4_alloc_atid); | |
1516 | ||
1517 | /* | |
1518 | * Release an active-open TID. | |
1519 | */ | |
1520 | void cxgb4_free_atid(struct tid_info *t, unsigned int atid) | |
1521 | { | |
f2b7e78d | 1522 | union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; |
b8ff05a9 DM |
1523 | |
1524 | spin_lock_bh(&t->atid_lock); | |
1525 | p->next = t->afree; | |
1526 | t->afree = p; | |
1527 | t->atids_in_use--; | |
1528 | spin_unlock_bh(&t->atid_lock); | |
1529 | } | |
1530 | EXPORT_SYMBOL(cxgb4_free_atid); | |
1531 | ||
1532 | /* | |
1533 | * Allocate a server TID and set it to the supplied value. | |
1534 | */ | |
1535 | int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) | |
1536 | { | |
1537 | int stid; | |
1538 | ||
1539 | spin_lock_bh(&t->stid_lock); | |
1540 | if (family == PF_INET) { | |
1541 | stid = find_first_zero_bit(t->stid_bmap, t->nstids); | |
1542 | if (stid < t->nstids) | |
1543 | __set_bit(stid, t->stid_bmap); | |
1544 | else | |
1545 | stid = -1; | |
1546 | } else { | |
a99c683e | 1547 | stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); |
b8ff05a9 DM |
1548 | if (stid < 0) |
1549 | stid = -1; | |
1550 | } | |
1551 | if (stid >= 0) { | |
1552 | t->stid_tab[stid].data = data; | |
1553 | stid += t->stid_base; | |
15f63b74 KS |
1554 | /* IPv6 requires max of 520 bits or 16 cells in TCAM |
1555 | * This is equivalent to 4 TIDs. With CLIP enabled it | |
1556 | * needs 2 TIDs. | |
1557 | */ | |
1558 | if (family == PF_INET) | |
1559 | t->stids_in_use++; | |
1560 | else | |
a99c683e | 1561 | t->stids_in_use += 2; |
b8ff05a9 DM |
1562 | } |
1563 | spin_unlock_bh(&t->stid_lock); | |
1564 | return stid; | |
1565 | } | |
1566 | EXPORT_SYMBOL(cxgb4_alloc_stid); | |
1567 | ||
dca4faeb VP |
1568 | /* Allocate a server filter TID and set it to the supplied value. |
1569 | */ | |
1570 | int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) | |
1571 | { | |
1572 | int stid; | |
1573 | ||
1574 | spin_lock_bh(&t->stid_lock); | |
1575 | if (family == PF_INET) { | |
1576 | stid = find_next_zero_bit(t->stid_bmap, | |
1577 | t->nstids + t->nsftids, t->nstids); | |
1578 | if (stid < (t->nstids + t->nsftids)) | |
1579 | __set_bit(stid, t->stid_bmap); | |
1580 | else | |
1581 | stid = -1; | |
1582 | } else { | |
1583 | stid = -1; | |
1584 | } | |
1585 | if (stid >= 0) { | |
1586 | t->stid_tab[stid].data = data; | |
470c60c4 KS |
1587 | stid -= t->nstids; |
1588 | stid += t->sftid_base; | |
2248b293 | 1589 | t->sftids_in_use++; |
dca4faeb VP |
1590 | } |
1591 | spin_unlock_bh(&t->stid_lock); | |
1592 | return stid; | |
1593 | } | |
1594 | EXPORT_SYMBOL(cxgb4_alloc_sftid); | |
1595 | ||
1596 | /* Release a server TID. | |
b8ff05a9 DM |
1597 | */ |
1598 | void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) | |
1599 | { | |
470c60c4 KS |
1600 | /* Is it a server filter TID? */ |
1601 | if (t->nsftids && (stid >= t->sftid_base)) { | |
1602 | stid -= t->sftid_base; | |
1603 | stid += t->nstids; | |
1604 | } else { | |
1605 | stid -= t->stid_base; | |
1606 | } | |
1607 | ||
b8ff05a9 DM |
1608 | spin_lock_bh(&t->stid_lock); |
1609 | if (family == PF_INET) | |
1610 | __clear_bit(stid, t->stid_bmap); | |
1611 | else | |
a99c683e | 1612 | bitmap_release_region(t->stid_bmap, stid, 1); |
b8ff05a9 | 1613 | t->stid_tab[stid].data = NULL; |
2248b293 HS |
1614 | if (stid < t->nstids) { |
1615 | if (family == PF_INET) | |
1616 | t->stids_in_use--; | |
1617 | else | |
a99c683e | 1618 | t->stids_in_use -= 2; |
2248b293 HS |
1619 | } else { |
1620 | t->sftids_in_use--; | |
1621 | } | |
b8ff05a9 DM |
1622 | spin_unlock_bh(&t->stid_lock); |
1623 | } | |
1624 | EXPORT_SYMBOL(cxgb4_free_stid); | |
1625 | ||
1626 | /* | |
1627 | * Populate a TID_RELEASE WR. Caller must properly size the skb. | |
1628 | */ | |
1629 | static void mk_tid_release(struct sk_buff *skb, unsigned int chan, | |
1630 | unsigned int tid) | |
1631 | { | |
1632 | struct cpl_tid_release *req; | |
1633 | ||
1634 | set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); | |
1635 | req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req)); | |
1636 | INIT_TP_WR(req, tid); | |
1637 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); | |
1638 | } | |
1639 | ||
1640 | /* | |
1641 | * Queue a TID release request and if necessary schedule a work queue to | |
1642 | * process it. | |
1643 | */ | |
31b9c19b | 1644 | static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, |
1645 | unsigned int tid) | |
b8ff05a9 DM |
1646 | { |
1647 | void **p = &t->tid_tab[tid]; | |
1648 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1649 | ||
1650 | spin_lock_bh(&adap->tid_release_lock); | |
1651 | *p = adap->tid_release_head; | |
1652 | /* Low 2 bits encode the Tx channel number */ | |
1653 | adap->tid_release_head = (void **)((uintptr_t)p | chan); | |
1654 | if (!adap->tid_release_task_busy) { | |
1655 | adap->tid_release_task_busy = true; | |
29aaee65 | 1656 | queue_work(adap->workq, &adap->tid_release_task); |
b8ff05a9 DM |
1657 | } |
1658 | spin_unlock_bh(&adap->tid_release_lock); | |
1659 | } | |
b8ff05a9 DM |
1660 | |
1661 | /* | |
1662 | * Process the list of pending TID release requests. | |
1663 | */ | |
1664 | static void process_tid_release_list(struct work_struct *work) | |
1665 | { | |
1666 | struct sk_buff *skb; | |
1667 | struct adapter *adap; | |
1668 | ||
1669 | adap = container_of(work, struct adapter, tid_release_task); | |
1670 | ||
1671 | spin_lock_bh(&adap->tid_release_lock); | |
1672 | while (adap->tid_release_head) { | |
1673 | void **p = adap->tid_release_head; | |
1674 | unsigned int chan = (uintptr_t)p & 3; | |
1675 | p = (void *)p - chan; | |
1676 | ||
1677 | adap->tid_release_head = *p; | |
1678 | *p = NULL; | |
1679 | spin_unlock_bh(&adap->tid_release_lock); | |
1680 | ||
1681 | while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), | |
1682 | GFP_KERNEL))) | |
1683 | schedule_timeout_uninterruptible(1); | |
1684 | ||
1685 | mk_tid_release(skb, chan, p - adap->tids.tid_tab); | |
1686 | t4_ofld_send(adap, skb); | |
1687 | spin_lock_bh(&adap->tid_release_lock); | |
1688 | } | |
1689 | adap->tid_release_task_busy = false; | |
1690 | spin_unlock_bh(&adap->tid_release_lock); | |
1691 | } | |
1692 | ||
1693 | /* | |
1694 | * Release a TID and inform HW. If we are unable to allocate the release | |
1695 | * message we defer to a work queue. | |
1696 | */ | |
1697 | void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid) | |
1698 | { | |
b8ff05a9 DM |
1699 | struct sk_buff *skb; |
1700 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1701 | ||
9a1bb9f6 HS |
1702 | WARN_ON(tid >= t->ntids); |
1703 | ||
1704 | if (t->tid_tab[tid]) { | |
1705 | t->tid_tab[tid] = NULL; | |
1706 | if (t->hash_base && (tid >= t->hash_base)) | |
1707 | atomic_dec(&t->hash_tids_in_use); | |
1708 | else | |
1709 | atomic_dec(&t->tids_in_use); | |
1710 | } | |
1711 | ||
b8ff05a9 DM |
1712 | skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); |
1713 | if (likely(skb)) { | |
b8ff05a9 DM |
1714 | mk_tid_release(skb, chan, tid); |
1715 | t4_ofld_send(adap, skb); | |
1716 | } else | |
1717 | cxgb4_queue_tid_release(t, chan, tid); | |
b8ff05a9 DM |
1718 | } |
1719 | EXPORT_SYMBOL(cxgb4_remove_tid); | |
1720 | ||
1721 | /* | |
1722 | * Allocate and initialize the TID tables. Returns 0 on success. | |
1723 | */ | |
1724 | static int tid_init(struct tid_info *t) | |
1725 | { | |
1726 | size_t size; | |
f2b7e78d | 1727 | unsigned int stid_bmap_size; |
b8ff05a9 | 1728 | unsigned int natids = t->natids; |
b6f8eaec | 1729 | struct adapter *adap = container_of(t, struct adapter, tids); |
b8ff05a9 | 1730 | |
dca4faeb | 1731 | stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); |
f2b7e78d VP |
1732 | size = t->ntids * sizeof(*t->tid_tab) + |
1733 | natids * sizeof(*t->atid_tab) + | |
b8ff05a9 | 1734 | t->nstids * sizeof(*t->stid_tab) + |
dca4faeb | 1735 | t->nsftids * sizeof(*t->stid_tab) + |
f2b7e78d | 1736 | stid_bmap_size * sizeof(long) + |
dca4faeb VP |
1737 | t->nftids * sizeof(*t->ftid_tab) + |
1738 | t->nsftids * sizeof(*t->ftid_tab); | |
f2b7e78d | 1739 | |
b8ff05a9 DM |
1740 | t->tid_tab = t4_alloc_mem(size); |
1741 | if (!t->tid_tab) | |
1742 | return -ENOMEM; | |
1743 | ||
1744 | t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; | |
1745 | t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; | |
dca4faeb | 1746 | t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; |
f2b7e78d | 1747 | t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; |
b8ff05a9 DM |
1748 | spin_lock_init(&t->stid_lock); |
1749 | spin_lock_init(&t->atid_lock); | |
1750 | ||
1751 | t->stids_in_use = 0; | |
2248b293 | 1752 | t->sftids_in_use = 0; |
b8ff05a9 DM |
1753 | t->afree = NULL; |
1754 | t->atids_in_use = 0; | |
1755 | atomic_set(&t->tids_in_use, 0); | |
9a1bb9f6 | 1756 | atomic_set(&t->hash_tids_in_use, 0); |
b8ff05a9 DM |
1757 | |
1758 | /* Setup the free list for atid_tab and clear the stid bitmap. */ | |
1759 | if (natids) { | |
1760 | while (--natids) | |
1761 | t->atid_tab[natids - 1].next = &t->atid_tab[natids]; | |
1762 | t->afree = t->atid_tab; | |
1763 | } | |
dca4faeb | 1764 | bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); |
b6f8eaec KS |
1765 | /* Reserve stid 0 for T4/T5 adapters */ |
1766 | if (!t->stid_base && | |
3ccc6cf7 | 1767 | (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)) |
b6f8eaec KS |
1768 | __set_bit(0, t->stid_bmap); |
1769 | ||
b8ff05a9 DM |
1770 | return 0; |
1771 | } | |
1772 | ||
1773 | /** | |
1774 | * cxgb4_create_server - create an IP server | |
1775 | * @dev: the device | |
1776 | * @stid: the server TID | |
1777 | * @sip: local IP address to bind server to | |
1778 | * @sport: the server's TCP port | |
1779 | * @queue: queue to direct messages from this server to | |
1780 | * | |
1781 | * Create an IP server for the given port and address. | |
1782 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1783 | */ | |
1784 | int cxgb4_create_server(const struct net_device *dev, unsigned int stid, | |
793dad94 VP |
1785 | __be32 sip, __be16 sport, __be16 vlan, |
1786 | unsigned int queue) | |
b8ff05a9 DM |
1787 | { |
1788 | unsigned int chan; | |
1789 | struct sk_buff *skb; | |
1790 | struct adapter *adap; | |
1791 | struct cpl_pass_open_req *req; | |
80f40c1f | 1792 | int ret; |
b8ff05a9 DM |
1793 | |
1794 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1795 | if (!skb) | |
1796 | return -ENOMEM; | |
1797 | ||
1798 | adap = netdev2adap(dev); | |
1799 | req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req)); | |
1800 | INIT_TP_WR(req, 0); | |
1801 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); | |
1802 | req->local_port = sport; | |
1803 | req->peer_port = htons(0); | |
1804 | req->local_ip = sip; | |
1805 | req->peer_ip = htonl(0); | |
e46dab4d | 1806 | chan = rxq_to_chan(&adap->sge, queue); |
d7990b0c | 1807 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1808 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1809 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1810 | ret = t4_mgmt_tx(adap, skb); |
1811 | return net_xmit_eval(ret); | |
b8ff05a9 DM |
1812 | } |
1813 | EXPORT_SYMBOL(cxgb4_create_server); | |
1814 | ||
80f40c1f VP |
1815 | /* cxgb4_create_server6 - create an IPv6 server |
1816 | * @dev: the device | |
1817 | * @stid: the server TID | |
1818 | * @sip: local IPv6 address to bind server to | |
1819 | * @sport: the server's TCP port | |
1820 | * @queue: queue to direct messages from this server to | |
1821 | * | |
1822 | * Create an IPv6 server for the given port and address. | |
1823 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1824 | */ | |
1825 | int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, | |
1826 | const struct in6_addr *sip, __be16 sport, | |
1827 | unsigned int queue) | |
1828 | { | |
1829 | unsigned int chan; | |
1830 | struct sk_buff *skb; | |
1831 | struct adapter *adap; | |
1832 | struct cpl_pass_open_req6 *req; | |
1833 | int ret; | |
1834 | ||
1835 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1836 | if (!skb) | |
1837 | return -ENOMEM; | |
1838 | ||
1839 | adap = netdev2adap(dev); | |
1840 | req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req)); | |
1841 | INIT_TP_WR(req, 0); | |
1842 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); | |
1843 | req->local_port = sport; | |
1844 | req->peer_port = htons(0); | |
1845 | req->local_ip_hi = *(__be64 *)(sip->s6_addr); | |
1846 | req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); | |
1847 | req->peer_ip_hi = cpu_to_be64(0); | |
1848 | req->peer_ip_lo = cpu_to_be64(0); | |
1849 | chan = rxq_to_chan(&adap->sge, queue); | |
d7990b0c | 1850 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1851 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1852 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1853 | ret = t4_mgmt_tx(adap, skb); |
1854 | return net_xmit_eval(ret); | |
1855 | } | |
1856 | EXPORT_SYMBOL(cxgb4_create_server6); | |
1857 | ||
1858 | int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, | |
1859 | unsigned int queue, bool ipv6) | |
1860 | { | |
1861 | struct sk_buff *skb; | |
1862 | struct adapter *adap; | |
1863 | struct cpl_close_listsvr_req *req; | |
1864 | int ret; | |
1865 | ||
1866 | adap = netdev2adap(dev); | |
1867 | ||
1868 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1869 | if (!skb) | |
1870 | return -ENOMEM; | |
1871 | ||
1872 | req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req)); | |
1873 | INIT_TP_WR(req, 0); | |
1874 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); | |
bdc590b9 HS |
1875 | req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : |
1876 | LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); | |
80f40c1f VP |
1877 | ret = t4_mgmt_tx(adap, skb); |
1878 | return net_xmit_eval(ret); | |
1879 | } | |
1880 | EXPORT_SYMBOL(cxgb4_remove_server); | |
1881 | ||
b8ff05a9 DM |
1882 | /** |
1883 | * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU | |
1884 | * @mtus: the HW MTU table | |
1885 | * @mtu: the target MTU | |
1886 | * @idx: index of selected entry in the MTU table | |
1887 | * | |
1888 | * Returns the index and the value in the HW MTU table that is closest to | |
1889 | * but does not exceed @mtu, unless @mtu is smaller than any value in the | |
1890 | * table, in which case that smallest available value is selected. | |
1891 | */ | |
1892 | unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, | |
1893 | unsigned int *idx) | |
1894 | { | |
1895 | unsigned int i = 0; | |
1896 | ||
1897 | while (i < NMTUS - 1 && mtus[i + 1] <= mtu) | |
1898 | ++i; | |
1899 | if (idx) | |
1900 | *idx = i; | |
1901 | return mtus[i]; | |
1902 | } | |
1903 | EXPORT_SYMBOL(cxgb4_best_mtu); | |
1904 | ||
92e7ae71 HS |
1905 | /** |
1906 | * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned | |
1907 | * @mtus: the HW MTU table | |
1908 | * @header_size: Header Size | |
1909 | * @data_size_max: maximum Data Segment Size | |
1910 | * @data_size_align: desired Data Segment Size Alignment (2^N) | |
1911 | * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) | |
1912 | * | |
1913 | * Similar to cxgb4_best_mtu() but instead of searching the Hardware | |
1914 | * MTU Table based solely on a Maximum MTU parameter, we break that | |
1915 | * parameter up into a Header Size and Maximum Data Segment Size, and | |
1916 | * provide a desired Data Segment Size Alignment. If we find an MTU in | |
1917 | * the Hardware MTU Table which will result in a Data Segment Size with | |
1918 | * the requested alignment _and_ that MTU isn't "too far" from the | |
1919 | * closest MTU, then we'll return that rather than the closest MTU. | |
1920 | */ | |
1921 | unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, | |
1922 | unsigned short header_size, | |
1923 | unsigned short data_size_max, | |
1924 | unsigned short data_size_align, | |
1925 | unsigned int *mtu_idxp) | |
1926 | { | |
1927 | unsigned short max_mtu = header_size + data_size_max; | |
1928 | unsigned short data_size_align_mask = data_size_align - 1; | |
1929 | int mtu_idx, aligned_mtu_idx; | |
1930 | ||
1931 | /* Scan the MTU Table till we find an MTU which is larger than our | |
1932 | * Maximum MTU or we reach the end of the table. Along the way, | |
1933 | * record the last MTU found, if any, which will result in a Data | |
1934 | * Segment Length matching the requested alignment. | |
1935 | */ | |
1936 | for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { | |
1937 | unsigned short data_size = mtus[mtu_idx] - header_size; | |
1938 | ||
1939 | /* If this MTU minus the Header Size would result in a | |
1940 | * Data Segment Size of the desired alignment, remember it. | |
1941 | */ | |
1942 | if ((data_size & data_size_align_mask) == 0) | |
1943 | aligned_mtu_idx = mtu_idx; | |
1944 | ||
1945 | /* If we're not at the end of the Hardware MTU Table and the | |
1946 | * next element is larger than our Maximum MTU, drop out of | |
1947 | * the loop. | |
1948 | */ | |
1949 | if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) | |
1950 | break; | |
1951 | } | |
1952 | ||
1953 | /* If we fell out of the loop because we ran to the end of the table, | |
1954 | * then we just have to use the last [largest] entry. | |
1955 | */ | |
1956 | if (mtu_idx == NMTUS) | |
1957 | mtu_idx--; | |
1958 | ||
1959 | /* If we found an MTU which resulted in the requested Data Segment | |
1960 | * Length alignment and that's "not far" from the largest MTU which is | |
1961 | * less than or equal to the maximum MTU, then use that. | |
1962 | */ | |
1963 | if (aligned_mtu_idx >= 0 && | |
1964 | mtu_idx - aligned_mtu_idx <= 1) | |
1965 | mtu_idx = aligned_mtu_idx; | |
1966 | ||
1967 | /* If the caller has passed in an MTU Index pointer, pass the | |
1968 | * MTU Index back. Return the MTU value. | |
1969 | */ | |
1970 | if (mtu_idxp) | |
1971 | *mtu_idxp = mtu_idx; | |
1972 | return mtus[mtu_idx]; | |
1973 | } | |
1974 | EXPORT_SYMBOL(cxgb4_best_aligned_mtu); | |
1975 | ||
27999805 H |
1976 | /** |
1977 | * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI | |
1978 | * @chip: chip type | |
1979 | * @viid: VI id of the given port | |
1980 | * | |
1981 | * Return the SMT index for this VI. | |
1982 | */ | |
1983 | unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid) | |
1984 | { | |
1985 | /* In T4/T5, SMT contains 256 SMAC entries organized in | |
1986 | * 128 rows of 2 entries each. | |
1987 | * In T6, SMT contains 256 SMAC entries in 256 rows. | |
1988 | * TODO: The below code needs to be updated when we add support | |
1989 | * for 256 VFs. | |
1990 | */ | |
1991 | if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) | |
1992 | return ((viid & 0x7f) << 1); | |
1993 | else | |
1994 | return (viid & 0x7f); | |
1995 | } | |
1996 | EXPORT_SYMBOL(cxgb4_tp_smt_idx); | |
1997 | ||
b8ff05a9 DM |
1998 | /** |
1999 | * cxgb4_port_chan - get the HW channel of a port | |
2000 | * @dev: the net device for the port | |
2001 | * | |
2002 | * Return the HW Tx channel of the given port. | |
2003 | */ | |
2004 | unsigned int cxgb4_port_chan(const struct net_device *dev) | |
2005 | { | |
2006 | return netdev2pinfo(dev)->tx_chan; | |
2007 | } | |
2008 | EXPORT_SYMBOL(cxgb4_port_chan); | |
2009 | ||
881806bc VP |
2010 | unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) |
2011 | { | |
2012 | struct adapter *adap = netdev2adap(dev); | |
2cc301d2 | 2013 | u32 v1, v2, lp_count, hp_count; |
881806bc | 2014 | |
f061de42 HS |
2015 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
2016 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 2017 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
2018 | lp_count = LP_COUNT_G(v1); |
2019 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 2020 | } else { |
f061de42 HS |
2021 | lp_count = LP_COUNT_T5_G(v1); |
2022 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
2023 | } |
2024 | return lpfifo ? lp_count : hp_count; | |
881806bc VP |
2025 | } |
2026 | EXPORT_SYMBOL(cxgb4_dbfifo_count); | |
2027 | ||
b8ff05a9 DM |
2028 | /** |
2029 | * cxgb4_port_viid - get the VI id of a port | |
2030 | * @dev: the net device for the port | |
2031 | * | |
2032 | * Return the VI id of the given port. | |
2033 | */ | |
2034 | unsigned int cxgb4_port_viid(const struct net_device *dev) | |
2035 | { | |
2036 | return netdev2pinfo(dev)->viid; | |
2037 | } | |
2038 | EXPORT_SYMBOL(cxgb4_port_viid); | |
2039 | ||
2040 | /** | |
2041 | * cxgb4_port_idx - get the index of a port | |
2042 | * @dev: the net device for the port | |
2043 | * | |
2044 | * Return the index of the given port. | |
2045 | */ | |
2046 | unsigned int cxgb4_port_idx(const struct net_device *dev) | |
2047 | { | |
2048 | return netdev2pinfo(dev)->port_id; | |
2049 | } | |
2050 | EXPORT_SYMBOL(cxgb4_port_idx); | |
2051 | ||
b8ff05a9 DM |
2052 | void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, |
2053 | struct tp_tcp_stats *v6) | |
2054 | { | |
2055 | struct adapter *adap = pci_get_drvdata(pdev); | |
2056 | ||
2057 | spin_lock(&adap->stats_lock); | |
2058 | t4_tp_get_tcp_stats(adap, v4, v6); | |
2059 | spin_unlock(&adap->stats_lock); | |
2060 | } | |
2061 | EXPORT_SYMBOL(cxgb4_get_tcp_stats); | |
2062 | ||
2063 | void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, | |
2064 | const unsigned int *pgsz_order) | |
2065 | { | |
2066 | struct adapter *adap = netdev2adap(dev); | |
2067 | ||
0d804338 HS |
2068 | t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); |
2069 | t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | | |
2070 | HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | | |
2071 | HPZ3_V(pgsz_order[3])); | |
b8ff05a9 DM |
2072 | } |
2073 | EXPORT_SYMBOL(cxgb4_iscsi_init); | |
2074 | ||
3069ee9b VP |
2075 | int cxgb4_flush_eq_cache(struct net_device *dev) |
2076 | { | |
2077 | struct adapter *adap = netdev2adap(dev); | |
3069ee9b | 2078 | |
5d700ecb | 2079 | return t4_sge_ctxt_flush(adap, adap->mbox); |
3069ee9b VP |
2080 | } |
2081 | EXPORT_SYMBOL(cxgb4_flush_eq_cache); | |
2082 | ||
2083 | static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) | |
2084 | { | |
f061de42 | 2085 | u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; |
3069ee9b VP |
2086 | __be64 indices; |
2087 | int ret; | |
2088 | ||
fc5ab020 HS |
2089 | spin_lock(&adap->win0_lock); |
2090 | ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, | |
2091 | sizeof(indices), (__be32 *)&indices, | |
2092 | T4_MEMORY_READ); | |
2093 | spin_unlock(&adap->win0_lock); | |
3069ee9b | 2094 | if (!ret) { |
404d9e3f VP |
2095 | *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; |
2096 | *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; | |
3069ee9b VP |
2097 | } |
2098 | return ret; | |
2099 | } | |
2100 | ||
2101 | int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, | |
2102 | u16 size) | |
2103 | { | |
2104 | struct adapter *adap = netdev2adap(dev); | |
2105 | u16 hw_pidx, hw_cidx; | |
2106 | int ret; | |
2107 | ||
2108 | ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); | |
2109 | if (ret) | |
2110 | goto out; | |
2111 | ||
2112 | if (pidx != hw_pidx) { | |
2113 | u16 delta; | |
f612b815 | 2114 | u32 val; |
3069ee9b VP |
2115 | |
2116 | if (pidx >= hw_pidx) | |
2117 | delta = pidx - hw_pidx; | |
2118 | else | |
2119 | delta = size - hw_pidx + pidx; | |
f612b815 HS |
2120 | |
2121 | if (is_t4(adap->params.chip)) | |
2122 | val = PIDX_V(delta); | |
2123 | else | |
2124 | val = PIDX_T5_V(delta); | |
3069ee9b | 2125 | wmb(); |
f612b815 HS |
2126 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
2127 | QID_V(qid) | val); | |
3069ee9b VP |
2128 | } |
2129 | out: | |
2130 | return ret; | |
2131 | } | |
2132 | EXPORT_SYMBOL(cxgb4_sync_txq_pidx); | |
2133 | ||
031cf476 HS |
2134 | int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) |
2135 | { | |
2136 | struct adapter *adap; | |
2137 | u32 offset, memtype, memaddr; | |
6559a7e8 | 2138 | u32 edc0_size, edc1_size, mc0_size, mc1_size, size; |
031cf476 HS |
2139 | u32 edc0_end, edc1_end, mc0_end, mc1_end; |
2140 | int ret; | |
2141 | ||
2142 | adap = netdev2adap(dev); | |
2143 | ||
2144 | offset = ((stag >> 8) * 32) + adap->vres.stag.start; | |
2145 | ||
2146 | /* Figure out where the offset lands in the Memory Type/Address scheme. | |
2147 | * This code assumes that the memory is laid out starting at offset 0 | |
2148 | * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 | |
2149 | * and EDC1. Some cards will have neither MC0 nor MC1, most cards have | |
2150 | * MC0, and some have both MC0 and MC1. | |
2151 | */ | |
6559a7e8 HS |
2152 | size = t4_read_reg(adap, MA_EDRAM0_BAR_A); |
2153 | edc0_size = EDRAM0_SIZE_G(size) << 20; | |
2154 | size = t4_read_reg(adap, MA_EDRAM1_BAR_A); | |
2155 | edc1_size = EDRAM1_SIZE_G(size) << 20; | |
2156 | size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); | |
2157 | mc0_size = EXT_MEM0_SIZE_G(size) << 20; | |
031cf476 HS |
2158 | |
2159 | edc0_end = edc0_size; | |
2160 | edc1_end = edc0_end + edc1_size; | |
2161 | mc0_end = edc1_end + mc0_size; | |
2162 | ||
2163 | if (offset < edc0_end) { | |
2164 | memtype = MEM_EDC0; | |
2165 | memaddr = offset; | |
2166 | } else if (offset < edc1_end) { | |
2167 | memtype = MEM_EDC1; | |
2168 | memaddr = offset - edc0_end; | |
2169 | } else { | |
2170 | if (offset < mc0_end) { | |
2171 | memtype = MEM_MC0; | |
2172 | memaddr = offset - edc1_end; | |
3ccc6cf7 | 2173 | } else if (is_t5(adap->params.chip)) { |
6559a7e8 HS |
2174 | size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); |
2175 | mc1_size = EXT_MEM1_SIZE_G(size) << 20; | |
031cf476 HS |
2176 | mc1_end = mc0_end + mc1_size; |
2177 | if (offset < mc1_end) { | |
2178 | memtype = MEM_MC1; | |
2179 | memaddr = offset - mc0_end; | |
2180 | } else { | |
2181 | /* offset beyond the end of any memory */ | |
2182 | goto err; | |
2183 | } | |
3ccc6cf7 HS |
2184 | } else { |
2185 | /* T4/T6 only has a single memory channel */ | |
2186 | goto err; | |
031cf476 HS |
2187 | } |
2188 | } | |
2189 | ||
2190 | spin_lock(&adap->win0_lock); | |
2191 | ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); | |
2192 | spin_unlock(&adap->win0_lock); | |
2193 | return ret; | |
2194 | ||
2195 | err: | |
2196 | dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", | |
2197 | stag, offset); | |
2198 | return -EINVAL; | |
2199 | } | |
2200 | EXPORT_SYMBOL(cxgb4_read_tpte); | |
2201 | ||
7730b4c7 HS |
2202 | u64 cxgb4_read_sge_timestamp(struct net_device *dev) |
2203 | { | |
2204 | u32 hi, lo; | |
2205 | struct adapter *adap; | |
2206 | ||
2207 | adap = netdev2adap(dev); | |
f612b815 HS |
2208 | lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); |
2209 | hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); | |
7730b4c7 HS |
2210 | |
2211 | return ((u64)hi << 32) | (u64)lo; | |
2212 | } | |
2213 | EXPORT_SYMBOL(cxgb4_read_sge_timestamp); | |
2214 | ||
df64e4d3 HS |
2215 | int cxgb4_bar2_sge_qregs(struct net_device *dev, |
2216 | unsigned int qid, | |
2217 | enum cxgb4_bar2_qtype qtype, | |
66cf188e | 2218 | int user, |
df64e4d3 HS |
2219 | u64 *pbar2_qoffset, |
2220 | unsigned int *pbar2_qid) | |
2221 | { | |
b2612722 | 2222 | return t4_bar2_sge_qregs(netdev2adap(dev), |
df64e4d3 HS |
2223 | qid, |
2224 | (qtype == CXGB4_BAR2_QTYPE_EGRESS | |
2225 | ? T4_BAR2_QTYPE_EGRESS | |
2226 | : T4_BAR2_QTYPE_INGRESS), | |
66cf188e | 2227 | user, |
df64e4d3 HS |
2228 | pbar2_qoffset, |
2229 | pbar2_qid); | |
2230 | } | |
2231 | EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); | |
2232 | ||
b8ff05a9 DM |
2233 | static struct pci_driver cxgb4_driver; |
2234 | ||
2235 | static void check_neigh_update(struct neighbour *neigh) | |
2236 | { | |
2237 | const struct device *parent; | |
2238 | const struct net_device *netdev = neigh->dev; | |
2239 | ||
2240 | if (netdev->priv_flags & IFF_802_1Q_VLAN) | |
2241 | netdev = vlan_dev_real_dev(netdev); | |
2242 | parent = netdev->dev.parent; | |
2243 | if (parent && parent->driver == &cxgb4_driver.driver) | |
2244 | t4_l2t_update(dev_get_drvdata(parent), neigh); | |
2245 | } | |
2246 | ||
2247 | static int netevent_cb(struct notifier_block *nb, unsigned long event, | |
2248 | void *data) | |
2249 | { | |
2250 | switch (event) { | |
2251 | case NETEVENT_NEIGH_UPDATE: | |
2252 | check_neigh_update(data); | |
2253 | break; | |
b8ff05a9 DM |
2254 | case NETEVENT_REDIRECT: |
2255 | default: | |
2256 | break; | |
2257 | } | |
2258 | return 0; | |
2259 | } | |
2260 | ||
2261 | static bool netevent_registered; | |
2262 | static struct notifier_block cxgb4_netevent_nb = { | |
2263 | .notifier_call = netevent_cb | |
2264 | }; | |
2265 | ||
3069ee9b VP |
2266 | static void drain_db_fifo(struct adapter *adap, int usecs) |
2267 | { | |
2cc301d2 | 2268 | u32 v1, v2, lp_count, hp_count; |
3069ee9b VP |
2269 | |
2270 | do { | |
f061de42 HS |
2271 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
2272 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 2273 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
2274 | lp_count = LP_COUNT_G(v1); |
2275 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 2276 | } else { |
f061de42 HS |
2277 | lp_count = LP_COUNT_T5_G(v1); |
2278 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
2279 | } |
2280 | ||
2281 | if (lp_count == 0 && hp_count == 0) | |
2282 | break; | |
3069ee9b VP |
2283 | set_current_state(TASK_UNINTERRUPTIBLE); |
2284 | schedule_timeout(usecs_to_jiffies(usecs)); | |
3069ee9b VP |
2285 | } while (1); |
2286 | } | |
2287 | ||
2288 | static void disable_txq_db(struct sge_txq *q) | |
2289 | { | |
05eb2389 SW |
2290 | unsigned long flags; |
2291 | ||
2292 | spin_lock_irqsave(&q->db_lock, flags); | |
3069ee9b | 2293 | q->db_disabled = 1; |
05eb2389 | 2294 | spin_unlock_irqrestore(&q->db_lock, flags); |
3069ee9b VP |
2295 | } |
2296 | ||
05eb2389 | 2297 | static void enable_txq_db(struct adapter *adap, struct sge_txq *q) |
3069ee9b VP |
2298 | { |
2299 | spin_lock_irq(&q->db_lock); | |
05eb2389 SW |
2300 | if (q->db_pidx_inc) { |
2301 | /* Make sure that all writes to the TX descriptors | |
2302 | * are committed before we tell HW about them. | |
2303 | */ | |
2304 | wmb(); | |
f612b815 HS |
2305 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
2306 | QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); | |
05eb2389 SW |
2307 | q->db_pidx_inc = 0; |
2308 | } | |
3069ee9b VP |
2309 | q->db_disabled = 0; |
2310 | spin_unlock_irq(&q->db_lock); | |
2311 | } | |
2312 | ||
2313 | static void disable_dbs(struct adapter *adap) | |
2314 | { | |
2315 | int i; | |
2316 | ||
2317 | for_each_ethrxq(&adap->sge, i) | |
2318 | disable_txq_db(&adap->sge.ethtxq[i].q); | |
f90ce561 | 2319 | for_each_iscsirxq(&adap->sge, i) |
3069ee9b VP |
2320 | disable_txq_db(&adap->sge.ofldtxq[i].q); |
2321 | for_each_port(adap, i) | |
2322 | disable_txq_db(&adap->sge.ctrlq[i].q); | |
2323 | } | |
2324 | ||
2325 | static void enable_dbs(struct adapter *adap) | |
2326 | { | |
2327 | int i; | |
2328 | ||
2329 | for_each_ethrxq(&adap->sge, i) | |
05eb2389 | 2330 | enable_txq_db(adap, &adap->sge.ethtxq[i].q); |
f90ce561 | 2331 | for_each_iscsirxq(&adap->sge, i) |
05eb2389 | 2332 | enable_txq_db(adap, &adap->sge.ofldtxq[i].q); |
3069ee9b | 2333 | for_each_port(adap, i) |
05eb2389 SW |
2334 | enable_txq_db(adap, &adap->sge.ctrlq[i].q); |
2335 | } | |
2336 | ||
2337 | static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) | |
2338 | { | |
2339 | if (adap->uld_handle[CXGB4_ULD_RDMA]) | |
2340 | ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA], | |
2341 | cmd); | |
2342 | } | |
2343 | ||
2344 | static void process_db_full(struct work_struct *work) | |
2345 | { | |
2346 | struct adapter *adap; | |
2347 | ||
2348 | adap = container_of(work, struct adapter, db_full_task); | |
2349 | ||
2350 | drain_db_fifo(adap, dbfifo_drain_delay); | |
2351 | enable_dbs(adap); | |
2352 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); | |
3ccc6cf7 HS |
2353 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
2354 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
2355 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, | |
2356 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); | |
2357 | else | |
2358 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
2359 | DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); | |
3069ee9b VP |
2360 | } |
2361 | ||
2362 | static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) | |
2363 | { | |
2364 | u16 hw_pidx, hw_cidx; | |
2365 | int ret; | |
2366 | ||
05eb2389 | 2367 | spin_lock_irq(&q->db_lock); |
3069ee9b VP |
2368 | ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); |
2369 | if (ret) | |
2370 | goto out; | |
2371 | if (q->db_pidx != hw_pidx) { | |
2372 | u16 delta; | |
f612b815 | 2373 | u32 val; |
3069ee9b VP |
2374 | |
2375 | if (q->db_pidx >= hw_pidx) | |
2376 | delta = q->db_pidx - hw_pidx; | |
2377 | else | |
2378 | delta = q->size - hw_pidx + q->db_pidx; | |
f612b815 HS |
2379 | |
2380 | if (is_t4(adap->params.chip)) | |
2381 | val = PIDX_V(delta); | |
2382 | else | |
2383 | val = PIDX_T5_V(delta); | |
3069ee9b | 2384 | wmb(); |
f612b815 HS |
2385 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
2386 | QID_V(q->cntxt_id) | val); | |
3069ee9b VP |
2387 | } |
2388 | out: | |
2389 | q->db_disabled = 0; | |
05eb2389 SW |
2390 | q->db_pidx_inc = 0; |
2391 | spin_unlock_irq(&q->db_lock); | |
3069ee9b VP |
2392 | if (ret) |
2393 | CH_WARN(adap, "DB drop recovery failed.\n"); | |
2394 | } | |
2395 | static void recover_all_queues(struct adapter *adap) | |
2396 | { | |
2397 | int i; | |
2398 | ||
2399 | for_each_ethrxq(&adap->sge, i) | |
2400 | sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); | |
f90ce561 | 2401 | for_each_iscsirxq(&adap->sge, i) |
3069ee9b VP |
2402 | sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q); |
2403 | for_each_port(adap, i) | |
2404 | sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); | |
2405 | } | |
2406 | ||
881806bc VP |
2407 | static void process_db_drop(struct work_struct *work) |
2408 | { | |
2409 | struct adapter *adap; | |
881806bc | 2410 | |
3069ee9b | 2411 | adap = container_of(work, struct adapter, db_drop_task); |
881806bc | 2412 | |
d14807dd | 2413 | if (is_t4(adap->params.chip)) { |
05eb2389 | 2414 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2415 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); |
05eb2389 | 2416 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2417 | recover_all_queues(adap); |
05eb2389 | 2418 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2419 | enable_dbs(adap); |
05eb2389 | 2420 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); |
3ccc6cf7 | 2421 | } else if (is_t5(adap->params.chip)) { |
2cc301d2 SR |
2422 | u32 dropped_db = t4_read_reg(adap, 0x010ac); |
2423 | u16 qid = (dropped_db >> 15) & 0x1ffff; | |
2424 | u16 pidx_inc = dropped_db & 0x1fff; | |
df64e4d3 HS |
2425 | u64 bar2_qoffset; |
2426 | unsigned int bar2_qid; | |
2427 | int ret; | |
2cc301d2 | 2428 | |
b2612722 | 2429 | ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, |
e0456717 | 2430 | 0, &bar2_qoffset, &bar2_qid); |
df64e4d3 HS |
2431 | if (ret) |
2432 | dev_err(adap->pdev_dev, "doorbell drop recovery: " | |
2433 | "qid=%d, pidx_inc=%d\n", qid, pidx_inc); | |
2434 | else | |
f612b815 | 2435 | writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), |
df64e4d3 | 2436 | adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); |
2cc301d2 SR |
2437 | |
2438 | /* Re-enable BAR2 WC */ | |
2439 | t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); | |
2440 | } | |
2441 | ||
3ccc6cf7 HS |
2442 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
2443 | t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); | |
881806bc VP |
2444 | } |
2445 | ||
2446 | void t4_db_full(struct adapter *adap) | |
2447 | { | |
d14807dd | 2448 | if (is_t4(adap->params.chip)) { |
05eb2389 SW |
2449 | disable_dbs(adap); |
2450 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
f612b815 HS |
2451 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, |
2452 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); | |
29aaee65 | 2453 | queue_work(adap->workq, &adap->db_full_task); |
2cc301d2 | 2454 | } |
881806bc VP |
2455 | } |
2456 | ||
2457 | void t4_db_dropped(struct adapter *adap) | |
2458 | { | |
05eb2389 SW |
2459 | if (is_t4(adap->params.chip)) { |
2460 | disable_dbs(adap); | |
2461 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
2462 | } | |
29aaee65 | 2463 | queue_work(adap->workq, &adap->db_drop_task); |
881806bc VP |
2464 | } |
2465 | ||
b8ff05a9 DM |
2466 | static void uld_attach(struct adapter *adap, unsigned int uld) |
2467 | { | |
2468 | void *handle; | |
2469 | struct cxgb4_lld_info lli; | |
dca4faeb | 2470 | unsigned short i; |
b8ff05a9 DM |
2471 | |
2472 | lli.pdev = adap->pdev; | |
b2612722 | 2473 | lli.pf = adap->pf; |
b8ff05a9 DM |
2474 | lli.l2t = adap->l2t; |
2475 | lli.tids = &adap->tids; | |
2476 | lli.ports = adap->port; | |
2477 | lli.vr = &adap->vres; | |
2478 | lli.mtus = adap->params.mtus; | |
2479 | if (uld == CXGB4_ULD_RDMA) { | |
2480 | lli.rxq_ids = adap->sge.rdma_rxq; | |
cf38be6d | 2481 | lli.ciq_ids = adap->sge.rdma_ciq; |
b8ff05a9 | 2482 | lli.nrxq = adap->sge.rdmaqs; |
cf38be6d | 2483 | lli.nciq = adap->sge.rdmaciqs; |
b8ff05a9 | 2484 | } else if (uld == CXGB4_ULD_ISCSI) { |
f90ce561 HS |
2485 | lli.rxq_ids = adap->sge.iscsi_rxq; |
2486 | lli.nrxq = adap->sge.iscsiqsets; | |
f2692d16 VP |
2487 | } else if (uld == CXGB4_ULD_ISCSIT) { |
2488 | lli.rxq_ids = adap->sge.iscsit_rxq; | |
2489 | lli.nrxq = adap->sge.niscsitq; | |
b8ff05a9 | 2490 | } |
f90ce561 | 2491 | lli.ntxq = adap->sge.iscsiqsets; |
b8ff05a9 DM |
2492 | lli.nchan = adap->params.nports; |
2493 | lli.nports = adap->params.nports; | |
2494 | lli.wr_cred = adap->params.ofldq_wr_cred; | |
d14807dd | 2495 | lli.adapter_type = adap->params.chip; |
837e4a42 | 2496 | lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A)); |
7714cb9e VP |
2497 | lli.iscsi_tagmask = t4_read_reg(adap, ULP_RX_ISCSI_TAGMASK_A); |
2498 | lli.iscsi_pgsz_order = t4_read_reg(adap, ULP_RX_ISCSI_PSZ_A); | |
2499 | lli.iscsi_llimit = t4_read_reg(adap, ULP_RX_ISCSI_LLIMIT_A); | |
2500 | lli.iscsi_ppm = &adap->iscsi_ppm; | |
7730b4c7 | 2501 | lli.cclk_ps = 1000000000 / adap->params.vpd.cclk; |
df64e4d3 HS |
2502 | lli.udb_density = 1 << adap->params.sge.eq_qpp; |
2503 | lli.ucq_density = 1 << adap->params.sge.iq_qpp; | |
dcf7b6f5 | 2504 | lli.filt_mode = adap->params.tp.vlan_pri_map; |
dca4faeb VP |
2505 | /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */ |
2506 | for (i = 0; i < NCHAN; i++) | |
2507 | lli.tx_modq[i] = i; | |
f612b815 HS |
2508 | lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A); |
2509 | lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A); | |
b8ff05a9 | 2510 | lli.fw_vers = adap->params.fw_vers; |
3069ee9b | 2511 | lli.dbfifo_int_thresh = dbfifo_int_thresh; |
04e10e21 HS |
2512 | lli.sge_ingpadboundary = adap->sge.fl_align; |
2513 | lli.sge_egrstatuspagesize = adap->sge.stat_len; | |
dca4faeb VP |
2514 | lli.sge_pktshift = adap->sge.pktshift; |
2515 | lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN; | |
4c2c5763 HS |
2516 | lli.max_ordird_qp = adap->params.max_ordird_qp; |
2517 | lli.max_ird_adapter = adap->params.max_ird_adapter; | |
1ac0f095 | 2518 | lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl; |
982b81eb | 2519 | lli.nodeid = dev_to_node(adap->pdev_dev); |
b8ff05a9 DM |
2520 | |
2521 | handle = ulds[uld].add(&lli); | |
2522 | if (IS_ERR(handle)) { | |
2523 | dev_warn(adap->pdev_dev, | |
2524 | "could not attach to the %s driver, error %ld\n", | |
2525 | uld_str[uld], PTR_ERR(handle)); | |
2526 | return; | |
2527 | } | |
2528 | ||
2529 | adap->uld_handle[uld] = handle; | |
2530 | ||
2531 | if (!netevent_registered) { | |
2532 | register_netevent_notifier(&cxgb4_netevent_nb); | |
2533 | netevent_registered = true; | |
2534 | } | |
e29f5dbc DM |
2535 | |
2536 | if (adap->flags & FULL_INIT_DONE) | |
2537 | ulds[uld].state_change(handle, CXGB4_STATE_UP); | |
b8ff05a9 DM |
2538 | } |
2539 | ||
2540 | static void attach_ulds(struct adapter *adap) | |
2541 | { | |
2542 | unsigned int i; | |
2543 | ||
01bcca68 VP |
2544 | spin_lock(&adap_rcu_lock); |
2545 | list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list); | |
2546 | spin_unlock(&adap_rcu_lock); | |
2547 | ||
b8ff05a9 DM |
2548 | mutex_lock(&uld_mutex); |
2549 | list_add_tail(&adap->list_node, &adapter_list); | |
2550 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
2551 | if (ulds[i].add) | |
2552 | uld_attach(adap, i); | |
2553 | mutex_unlock(&uld_mutex); | |
2554 | } | |
2555 | ||
2556 | static void detach_ulds(struct adapter *adap) | |
2557 | { | |
2558 | unsigned int i; | |
2559 | ||
2560 | mutex_lock(&uld_mutex); | |
2561 | list_del(&adap->list_node); | |
2562 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
2563 | if (adap->uld_handle[i]) { | |
2564 | ulds[i].state_change(adap->uld_handle[i], | |
2565 | CXGB4_STATE_DETACH); | |
2566 | adap->uld_handle[i] = NULL; | |
2567 | } | |
2568 | if (netevent_registered && list_empty(&adapter_list)) { | |
2569 | unregister_netevent_notifier(&cxgb4_netevent_nb); | |
2570 | netevent_registered = false; | |
2571 | } | |
2572 | mutex_unlock(&uld_mutex); | |
01bcca68 VP |
2573 | |
2574 | spin_lock(&adap_rcu_lock); | |
2575 | list_del_rcu(&adap->rcu_node); | |
2576 | spin_unlock(&adap_rcu_lock); | |
b8ff05a9 DM |
2577 | } |
2578 | ||
2579 | static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) | |
2580 | { | |
2581 | unsigned int i; | |
2582 | ||
2583 | mutex_lock(&uld_mutex); | |
2584 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
2585 | if (adap->uld_handle[i]) | |
2586 | ulds[i].state_change(adap->uld_handle[i], new_state); | |
2587 | mutex_unlock(&uld_mutex); | |
2588 | } | |
2589 | ||
2590 | /** | |
2591 | * cxgb4_register_uld - register an upper-layer driver | |
2592 | * @type: the ULD type | |
2593 | * @p: the ULD methods | |
2594 | * | |
2595 | * Registers an upper-layer driver with this driver and notifies the ULD | |
2596 | * about any presently available devices that support its type. Returns | |
2597 | * %-EBUSY if a ULD of the same type is already registered. | |
2598 | */ | |
2599 | int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p) | |
2600 | { | |
2601 | int ret = 0; | |
2602 | struct adapter *adap; | |
2603 | ||
2604 | if (type >= CXGB4_ULD_MAX) | |
2605 | return -EINVAL; | |
2606 | mutex_lock(&uld_mutex); | |
2607 | if (ulds[type].add) { | |
2608 | ret = -EBUSY; | |
2609 | goto out; | |
2610 | } | |
2611 | ulds[type] = *p; | |
2612 | list_for_each_entry(adap, &adapter_list, list_node) | |
2613 | uld_attach(adap, type); | |
2614 | out: mutex_unlock(&uld_mutex); | |
2615 | return ret; | |
2616 | } | |
2617 | EXPORT_SYMBOL(cxgb4_register_uld); | |
2618 | ||
2619 | /** | |
2620 | * cxgb4_unregister_uld - unregister an upper-layer driver | |
2621 | * @type: the ULD type | |
2622 | * | |
2623 | * Unregisters an existing upper-layer driver. | |
2624 | */ | |
2625 | int cxgb4_unregister_uld(enum cxgb4_uld type) | |
2626 | { | |
2627 | struct adapter *adap; | |
2628 | ||
2629 | if (type >= CXGB4_ULD_MAX) | |
2630 | return -EINVAL; | |
2631 | mutex_lock(&uld_mutex); | |
2632 | list_for_each_entry(adap, &adapter_list, list_node) | |
2633 | adap->uld_handle[type] = NULL; | |
2634 | ulds[type].add = NULL; | |
2635 | mutex_unlock(&uld_mutex); | |
2636 | return 0; | |
2637 | } | |
2638 | EXPORT_SYMBOL(cxgb4_unregister_uld); | |
2639 | ||
1bb60376 | 2640 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
2641 | static int cxgb4_inet6addr_handler(struct notifier_block *this, |
2642 | unsigned long event, void *data) | |
01bcca68 | 2643 | { |
b5a02f50 AB |
2644 | struct inet6_ifaddr *ifa = data; |
2645 | struct net_device *event_dev = ifa->idev->dev; | |
2646 | const struct device *parent = NULL; | |
2647 | #if IS_ENABLED(CONFIG_BONDING) | |
01bcca68 | 2648 | struct adapter *adap; |
b5a02f50 AB |
2649 | #endif |
2650 | if (event_dev->priv_flags & IFF_802_1Q_VLAN) | |
2651 | event_dev = vlan_dev_real_dev(event_dev); | |
2652 | #if IS_ENABLED(CONFIG_BONDING) | |
2653 | if (event_dev->flags & IFF_MASTER) { | |
2654 | list_for_each_entry(adap, &adapter_list, list_node) { | |
2655 | switch (event) { | |
2656 | case NETDEV_UP: | |
2657 | cxgb4_clip_get(adap->port[0], | |
2658 | (const u32 *)ifa, 1); | |
2659 | break; | |
2660 | case NETDEV_DOWN: | |
2661 | cxgb4_clip_release(adap->port[0], | |
2662 | (const u32 *)ifa, 1); | |
2663 | break; | |
2664 | default: | |
2665 | break; | |
2666 | } | |
2667 | } | |
2668 | return NOTIFY_OK; | |
2669 | } | |
2670 | #endif | |
01bcca68 | 2671 | |
b5a02f50 AB |
2672 | if (event_dev) |
2673 | parent = event_dev->dev.parent; | |
01bcca68 | 2674 | |
b5a02f50 | 2675 | if (parent && parent->driver == &cxgb4_driver.driver) { |
01bcca68 VP |
2676 | switch (event) { |
2677 | case NETDEV_UP: | |
b5a02f50 | 2678 | cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2679 | break; |
2680 | case NETDEV_DOWN: | |
b5a02f50 | 2681 | cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2682 | break; |
2683 | default: | |
2684 | break; | |
2685 | } | |
2686 | } | |
b5a02f50 | 2687 | return NOTIFY_OK; |
01bcca68 VP |
2688 | } |
2689 | ||
b5a02f50 | 2690 | static bool inet6addr_registered; |
01bcca68 VP |
2691 | static struct notifier_block cxgb4_inet6addr_notifier = { |
2692 | .notifier_call = cxgb4_inet6addr_handler | |
2693 | }; | |
2694 | ||
01bcca68 VP |
2695 | static void update_clip(const struct adapter *adap) |
2696 | { | |
2697 | int i; | |
2698 | struct net_device *dev; | |
2699 | int ret; | |
2700 | ||
2701 | rcu_read_lock(); | |
2702 | ||
2703 | for (i = 0; i < MAX_NPORTS; i++) { | |
2704 | dev = adap->port[i]; | |
2705 | ret = 0; | |
2706 | ||
2707 | if (dev) | |
b5a02f50 | 2708 | ret = cxgb4_update_root_dev_clip(dev); |
01bcca68 VP |
2709 | |
2710 | if (ret < 0) | |
2711 | break; | |
2712 | } | |
2713 | rcu_read_unlock(); | |
2714 | } | |
1bb60376 | 2715 | #endif /* IS_ENABLED(CONFIG_IPV6) */ |
01bcca68 | 2716 | |
b8ff05a9 DM |
2717 | /** |
2718 | * cxgb_up - enable the adapter | |
2719 | * @adap: adapter being enabled | |
2720 | * | |
2721 | * Called when the first port is enabled, this function performs the | |
2722 | * actions necessary to make an adapter operational, such as completing | |
2723 | * the initialization of HW modules, and enabling interrupts. | |
2724 | * | |
2725 | * Must be called with the rtnl lock held. | |
2726 | */ | |
2727 | static int cxgb_up(struct adapter *adap) | |
2728 | { | |
aaefae9b | 2729 | int err; |
b8ff05a9 | 2730 | |
aaefae9b DM |
2731 | err = setup_sge_queues(adap); |
2732 | if (err) | |
2733 | goto out; | |
2734 | err = setup_rss(adap); | |
2735 | if (err) | |
2736 | goto freeq; | |
b8ff05a9 DM |
2737 | |
2738 | if (adap->flags & USING_MSIX) { | |
aaefae9b | 2739 | name_msix_vecs(adap); |
b8ff05a9 DM |
2740 | err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, |
2741 | adap->msix_info[0].desc, adap); | |
2742 | if (err) | |
2743 | goto irq_err; | |
2744 | ||
2745 | err = request_msix_queue_irqs(adap); | |
2746 | if (err) { | |
2747 | free_irq(adap->msix_info[0].vec, adap); | |
2748 | goto irq_err; | |
2749 | } | |
2750 | } else { | |
2751 | err = request_irq(adap->pdev->irq, t4_intr_handler(adap), | |
2752 | (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, | |
b1a3c2b6 | 2753 | adap->port[0]->name, adap); |
b8ff05a9 DM |
2754 | if (err) |
2755 | goto irq_err; | |
2756 | } | |
2757 | enable_rx(adap); | |
2758 | t4_sge_start(adap); | |
2759 | t4_intr_enable(adap); | |
aaefae9b | 2760 | adap->flags |= FULL_INIT_DONE; |
b8ff05a9 | 2761 | notify_ulds(adap, CXGB4_STATE_UP); |
1bb60376 | 2762 | #if IS_ENABLED(CONFIG_IPV6) |
01bcca68 | 2763 | update_clip(adap); |
1bb60376 | 2764 | #endif |
fc08a01a HS |
2765 | /* Initialize hash mac addr list*/ |
2766 | INIT_LIST_HEAD(&adap->mac_hlist); | |
b8ff05a9 DM |
2767 | out: |
2768 | return err; | |
2769 | irq_err: | |
2770 | dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); | |
aaefae9b DM |
2771 | freeq: |
2772 | t4_free_sge_resources(adap); | |
b8ff05a9 DM |
2773 | goto out; |
2774 | } | |
2775 | ||
2776 | static void cxgb_down(struct adapter *adapter) | |
2777 | { | |
b8ff05a9 | 2778 | cancel_work_sync(&adapter->tid_release_task); |
881806bc VP |
2779 | cancel_work_sync(&adapter->db_full_task); |
2780 | cancel_work_sync(&adapter->db_drop_task); | |
b8ff05a9 | 2781 | adapter->tid_release_task_busy = false; |
204dc3c0 | 2782 | adapter->tid_release_head = NULL; |
b8ff05a9 | 2783 | |
aaefae9b DM |
2784 | t4_sge_stop(adapter); |
2785 | t4_free_sge_resources(adapter); | |
2786 | adapter->flags &= ~FULL_INIT_DONE; | |
b8ff05a9 DM |
2787 | } |
2788 | ||
2789 | /* | |
2790 | * net_device operations | |
2791 | */ | |
2792 | static int cxgb_open(struct net_device *dev) | |
2793 | { | |
2794 | int err; | |
2795 | struct port_info *pi = netdev_priv(dev); | |
2796 | struct adapter *adapter = pi->adapter; | |
2797 | ||
6a3c869a DM |
2798 | netif_carrier_off(dev); |
2799 | ||
aaefae9b DM |
2800 | if (!(adapter->flags & FULL_INIT_DONE)) { |
2801 | err = cxgb_up(adapter); | |
2802 | if (err < 0) | |
2803 | return err; | |
2804 | } | |
b8ff05a9 | 2805 | |
f68707b8 DM |
2806 | err = link_start(dev); |
2807 | if (!err) | |
2808 | netif_tx_start_all_queues(dev); | |
2809 | return err; | |
b8ff05a9 DM |
2810 | } |
2811 | ||
2812 | static int cxgb_close(struct net_device *dev) | |
2813 | { | |
b8ff05a9 DM |
2814 | struct port_info *pi = netdev_priv(dev); |
2815 | struct adapter *adapter = pi->adapter; | |
2816 | ||
2817 | netif_tx_stop_all_queues(dev); | |
2818 | netif_carrier_off(dev); | |
b2612722 | 2819 | return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false); |
b8ff05a9 DM |
2820 | } |
2821 | ||
f2b7e78d VP |
2822 | /* Return an error number if the indicated filter isn't writable ... |
2823 | */ | |
2824 | static int writable_filter(struct filter_entry *f) | |
2825 | { | |
2826 | if (f->locked) | |
2827 | return -EPERM; | |
2828 | if (f->pending) | |
2829 | return -EBUSY; | |
2830 | ||
2831 | return 0; | |
2832 | } | |
2833 | ||
2834 | /* Delete the filter at the specified index (if valid). The checks for all | |
2835 | * the common problems with doing this like the filter being locked, currently | |
2836 | * pending in another operation, etc. | |
2837 | */ | |
2838 | static int delete_filter(struct adapter *adapter, unsigned int fidx) | |
2839 | { | |
2840 | struct filter_entry *f; | |
2841 | int ret; | |
2842 | ||
dca4faeb | 2843 | if (fidx >= adapter->tids.nftids + adapter->tids.nsftids) |
f2b7e78d VP |
2844 | return -EINVAL; |
2845 | ||
2846 | f = &adapter->tids.ftid_tab[fidx]; | |
2847 | ret = writable_filter(f); | |
2848 | if (ret) | |
2849 | return ret; | |
2850 | if (f->valid) | |
2851 | return del_filter_wr(adapter, fidx); | |
2852 | ||
2853 | return 0; | |
2854 | } | |
2855 | ||
dca4faeb | 2856 | int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, |
793dad94 VP |
2857 | __be32 sip, __be16 sport, __be16 vlan, |
2858 | unsigned int queue, unsigned char port, unsigned char mask) | |
dca4faeb VP |
2859 | { |
2860 | int ret; | |
2861 | struct filter_entry *f; | |
2862 | struct adapter *adap; | |
2863 | int i; | |
2864 | u8 *val; | |
2865 | ||
2866 | adap = netdev2adap(dev); | |
2867 | ||
1cab775c | 2868 | /* Adjust stid to correct filter index */ |
470c60c4 | 2869 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2870 | stid += adap->tids.nftids; |
2871 | ||
dca4faeb VP |
2872 | /* Check to make sure the filter requested is writable ... |
2873 | */ | |
2874 | f = &adap->tids.ftid_tab[stid]; | |
2875 | ret = writable_filter(f); | |
2876 | if (ret) | |
2877 | return ret; | |
2878 | ||
2879 | /* Clear out any old resources being used by the filter before | |
2880 | * we start constructing the new filter. | |
2881 | */ | |
2882 | if (f->valid) | |
2883 | clear_filter(adap, f); | |
2884 | ||
2885 | /* Clear out filter specifications */ | |
2886 | memset(&f->fs, 0, sizeof(struct ch_filter_specification)); | |
2887 | f->fs.val.lport = cpu_to_be16(sport); | |
2888 | f->fs.mask.lport = ~0; | |
2889 | val = (u8 *)&sip; | |
793dad94 | 2890 | if ((val[0] | val[1] | val[2] | val[3]) != 0) { |
dca4faeb VP |
2891 | for (i = 0; i < 4; i++) { |
2892 | f->fs.val.lip[i] = val[i]; | |
2893 | f->fs.mask.lip[i] = ~0; | |
2894 | } | |
0d804338 | 2895 | if (adap->params.tp.vlan_pri_map & PORT_F) { |
793dad94 VP |
2896 | f->fs.val.iport = port; |
2897 | f->fs.mask.iport = mask; | |
2898 | } | |
2899 | } | |
dca4faeb | 2900 | |
0d804338 | 2901 | if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { |
7c89e555 KS |
2902 | f->fs.val.proto = IPPROTO_TCP; |
2903 | f->fs.mask.proto = ~0; | |
2904 | } | |
2905 | ||
dca4faeb VP |
2906 | f->fs.dirsteer = 1; |
2907 | f->fs.iq = queue; | |
2908 | /* Mark filter as locked */ | |
2909 | f->locked = 1; | |
2910 | f->fs.rpttid = 1; | |
2911 | ||
2912 | ret = set_filter_wr(adap, stid); | |
2913 | if (ret) { | |
2914 | clear_filter(adap, f); | |
2915 | return ret; | |
2916 | } | |
2917 | ||
2918 | return 0; | |
2919 | } | |
2920 | EXPORT_SYMBOL(cxgb4_create_server_filter); | |
2921 | ||
2922 | int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, | |
2923 | unsigned int queue, bool ipv6) | |
2924 | { | |
2925 | int ret; | |
2926 | struct filter_entry *f; | |
2927 | struct adapter *adap; | |
2928 | ||
2929 | adap = netdev2adap(dev); | |
1cab775c VP |
2930 | |
2931 | /* Adjust stid to correct filter index */ | |
470c60c4 | 2932 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2933 | stid += adap->tids.nftids; |
2934 | ||
dca4faeb VP |
2935 | f = &adap->tids.ftid_tab[stid]; |
2936 | /* Unlock the filter */ | |
2937 | f->locked = 0; | |
2938 | ||
2939 | ret = delete_filter(adap, stid); | |
2940 | if (ret) | |
2941 | return ret; | |
2942 | ||
2943 | return 0; | |
2944 | } | |
2945 | EXPORT_SYMBOL(cxgb4_remove_server_filter); | |
2946 | ||
f5152c90 DM |
2947 | static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev, |
2948 | struct rtnl_link_stats64 *ns) | |
b8ff05a9 DM |
2949 | { |
2950 | struct port_stats stats; | |
2951 | struct port_info *p = netdev_priv(dev); | |
2952 | struct adapter *adapter = p->adapter; | |
b8ff05a9 | 2953 | |
9fe6cb58 GS |
2954 | /* Block retrieving statistics during EEH error |
2955 | * recovery. Otherwise, the recovery might fail | |
2956 | * and the PCI device will be removed permanently | |
2957 | */ | |
b8ff05a9 | 2958 | spin_lock(&adapter->stats_lock); |
9fe6cb58 GS |
2959 | if (!netif_device_present(dev)) { |
2960 | spin_unlock(&adapter->stats_lock); | |
2961 | return ns; | |
2962 | } | |
a4cfd929 HS |
2963 | t4_get_port_stats_offset(adapter, p->tx_chan, &stats, |
2964 | &p->stats_base); | |
b8ff05a9 DM |
2965 | spin_unlock(&adapter->stats_lock); |
2966 | ||
2967 | ns->tx_bytes = stats.tx_octets; | |
2968 | ns->tx_packets = stats.tx_frames; | |
2969 | ns->rx_bytes = stats.rx_octets; | |
2970 | ns->rx_packets = stats.rx_frames; | |
2971 | ns->multicast = stats.rx_mcast_frames; | |
2972 | ||
2973 | /* detailed rx_errors */ | |
2974 | ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + | |
2975 | stats.rx_runt; | |
2976 | ns->rx_over_errors = 0; | |
2977 | ns->rx_crc_errors = stats.rx_fcs_err; | |
2978 | ns->rx_frame_errors = stats.rx_symbol_err; | |
2979 | ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 + | |
2980 | stats.rx_ovflow2 + stats.rx_ovflow3 + | |
2981 | stats.rx_trunc0 + stats.rx_trunc1 + | |
2982 | stats.rx_trunc2 + stats.rx_trunc3; | |
2983 | ns->rx_missed_errors = 0; | |
2984 | ||
2985 | /* detailed tx_errors */ | |
2986 | ns->tx_aborted_errors = 0; | |
2987 | ns->tx_carrier_errors = 0; | |
2988 | ns->tx_fifo_errors = 0; | |
2989 | ns->tx_heartbeat_errors = 0; | |
2990 | ns->tx_window_errors = 0; | |
2991 | ||
2992 | ns->tx_errors = stats.tx_error_frames; | |
2993 | ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + | |
2994 | ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; | |
2995 | return ns; | |
2996 | } | |
2997 | ||
2998 | static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
2999 | { | |
060e0c75 | 3000 | unsigned int mbox; |
b8ff05a9 DM |
3001 | int ret = 0, prtad, devad; |
3002 | struct port_info *pi = netdev_priv(dev); | |
3003 | struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; | |
3004 | ||
3005 | switch (cmd) { | |
3006 | case SIOCGMIIPHY: | |
3007 | if (pi->mdio_addr < 0) | |
3008 | return -EOPNOTSUPP; | |
3009 | data->phy_id = pi->mdio_addr; | |
3010 | break; | |
3011 | case SIOCGMIIREG: | |
3012 | case SIOCSMIIREG: | |
3013 | if (mdio_phy_id_is_c45(data->phy_id)) { | |
3014 | prtad = mdio_phy_id_prtad(data->phy_id); | |
3015 | devad = mdio_phy_id_devad(data->phy_id); | |
3016 | } else if (data->phy_id < 32) { | |
3017 | prtad = data->phy_id; | |
3018 | devad = 0; | |
3019 | data->reg_num &= 0x1f; | |
3020 | } else | |
3021 | return -EINVAL; | |
3022 | ||
b2612722 | 3023 | mbox = pi->adapter->pf; |
b8ff05a9 | 3024 | if (cmd == SIOCGMIIREG) |
060e0c75 | 3025 | ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
3026 | data->reg_num, &data->val_out); |
3027 | else | |
060e0c75 | 3028 | ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
3029 | data->reg_num, data->val_in); |
3030 | break; | |
5e2a5ebc HS |
3031 | case SIOCGHWTSTAMP: |
3032 | return copy_to_user(req->ifr_data, &pi->tstamp_config, | |
3033 | sizeof(pi->tstamp_config)) ? | |
3034 | -EFAULT : 0; | |
3035 | case SIOCSHWTSTAMP: | |
3036 | if (copy_from_user(&pi->tstamp_config, req->ifr_data, | |
3037 | sizeof(pi->tstamp_config))) | |
3038 | return -EFAULT; | |
3039 | ||
3040 | switch (pi->tstamp_config.rx_filter) { | |
3041 | case HWTSTAMP_FILTER_NONE: | |
3042 | pi->rxtstamp = false; | |
3043 | break; | |
3044 | case HWTSTAMP_FILTER_ALL: | |
3045 | pi->rxtstamp = true; | |
3046 | break; | |
3047 | default: | |
3048 | pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; | |
3049 | return -ERANGE; | |
3050 | } | |
3051 | ||
3052 | return copy_to_user(req->ifr_data, &pi->tstamp_config, | |
3053 | sizeof(pi->tstamp_config)) ? | |
3054 | -EFAULT : 0; | |
b8ff05a9 DM |
3055 | default: |
3056 | return -EOPNOTSUPP; | |
3057 | } | |
3058 | return ret; | |
3059 | } | |
3060 | ||
3061 | static void cxgb_set_rxmode(struct net_device *dev) | |
3062 | { | |
3063 | /* unfortunately we can't return errors to the stack */ | |
3064 | set_rxmode(dev, -1, false); | |
3065 | } | |
3066 | ||
3067 | static int cxgb_change_mtu(struct net_device *dev, int new_mtu) | |
3068 | { | |
3069 | int ret; | |
3070 | struct port_info *pi = netdev_priv(dev); | |
3071 | ||
3072 | if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */ | |
3073 | return -EINVAL; | |
b2612722 | 3074 | ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, |
060e0c75 | 3075 | -1, -1, -1, true); |
b8ff05a9 DM |
3076 | if (!ret) |
3077 | dev->mtu = new_mtu; | |
3078 | return ret; | |
3079 | } | |
3080 | ||
3081 | static int cxgb_set_mac_addr(struct net_device *dev, void *p) | |
3082 | { | |
3083 | int ret; | |
3084 | struct sockaddr *addr = p; | |
3085 | struct port_info *pi = netdev_priv(dev); | |
3086 | ||
3087 | if (!is_valid_ether_addr(addr->sa_data)) | |
504f9b5a | 3088 | return -EADDRNOTAVAIL; |
b8ff05a9 | 3089 | |
b2612722 | 3090 | ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, |
060e0c75 | 3091 | pi->xact_addr_filt, addr->sa_data, true, true); |
b8ff05a9 DM |
3092 | if (ret < 0) |
3093 | return ret; | |
3094 | ||
3095 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
3096 | pi->xact_addr_filt = ret; | |
3097 | return 0; | |
3098 | } | |
3099 | ||
b8ff05a9 DM |
3100 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3101 | static void cxgb_netpoll(struct net_device *dev) | |
3102 | { | |
3103 | struct port_info *pi = netdev_priv(dev); | |
3104 | struct adapter *adap = pi->adapter; | |
3105 | ||
3106 | if (adap->flags & USING_MSIX) { | |
3107 | int i; | |
3108 | struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; | |
3109 | ||
3110 | for (i = pi->nqsets; i; i--, rx++) | |
3111 | t4_sge_intr_msix(0, &rx->rspq); | |
3112 | } else | |
3113 | t4_intr_handler(adap)(0, adap); | |
3114 | } | |
3115 | #endif | |
3116 | ||
3117 | static const struct net_device_ops cxgb4_netdev_ops = { | |
3118 | .ndo_open = cxgb_open, | |
3119 | .ndo_stop = cxgb_close, | |
3120 | .ndo_start_xmit = t4_eth_xmit, | |
688848b1 | 3121 | .ndo_select_queue = cxgb_select_queue, |
9be793bf | 3122 | .ndo_get_stats64 = cxgb_get_stats, |
b8ff05a9 DM |
3123 | .ndo_set_rx_mode = cxgb_set_rxmode, |
3124 | .ndo_set_mac_address = cxgb_set_mac_addr, | |
2ed28baa | 3125 | .ndo_set_features = cxgb_set_features, |
b8ff05a9 DM |
3126 | .ndo_validate_addr = eth_validate_addr, |
3127 | .ndo_do_ioctl = cxgb_ioctl, | |
3128 | .ndo_change_mtu = cxgb_change_mtu, | |
b8ff05a9 DM |
3129 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3130 | .ndo_poll_controller = cxgb_netpoll, | |
3131 | #endif | |
84a200b3 VP |
3132 | #ifdef CONFIG_CHELSIO_T4_FCOE |
3133 | .ndo_fcoe_enable = cxgb_fcoe_enable, | |
3134 | .ndo_fcoe_disable = cxgb_fcoe_disable, | |
3135 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
3a336cb1 HS |
3136 | #ifdef CONFIG_NET_RX_BUSY_POLL |
3137 | .ndo_busy_poll = cxgb_busy_poll, | |
3138 | #endif | |
3139 | ||
b8ff05a9 DM |
3140 | }; |
3141 | ||
3142 | void t4_fatal_err(struct adapter *adap) | |
3143 | { | |
f612b815 | 3144 | t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0); |
b8ff05a9 DM |
3145 | t4_intr_disable(adap); |
3146 | dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); | |
3147 | } | |
3148 | ||
3149 | static void setup_memwin(struct adapter *adap) | |
3150 | { | |
b562fc37 | 3151 | u32 nic_win_base = t4_get_util_window(adap); |
b8ff05a9 | 3152 | |
b562fc37 | 3153 | t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); |
636f9d37 VP |
3154 | } |
3155 | ||
3156 | static void setup_memwin_rdma(struct adapter *adap) | |
3157 | { | |
1ae970e0 | 3158 | if (adap->vres.ocq.size) { |
0abfd152 HS |
3159 | u32 start; |
3160 | unsigned int sz_kb; | |
1ae970e0 | 3161 | |
0abfd152 HS |
3162 | start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); |
3163 | start &= PCI_BASE_ADDRESS_MEM_MASK; | |
3164 | start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); | |
1ae970e0 DM |
3165 | sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; |
3166 | t4_write_reg(adap, | |
f061de42 HS |
3167 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), |
3168 | start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); | |
1ae970e0 | 3169 | t4_write_reg(adap, |
f061de42 | 3170 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), |
1ae970e0 DM |
3171 | adap->vres.ocq.start); |
3172 | t4_read_reg(adap, | |
f061de42 | 3173 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); |
1ae970e0 | 3174 | } |
b8ff05a9 DM |
3175 | } |
3176 | ||
02b5fb8e DM |
3177 | static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) |
3178 | { | |
3179 | u32 v; | |
3180 | int ret; | |
3181 | ||
3182 | /* get device capabilities */ | |
3183 | memset(c, 0, sizeof(*c)); | |
e2ac9628 HS |
3184 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3185 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 3186 | c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); |
b2612722 | 3187 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); |
02b5fb8e DM |
3188 | if (ret < 0) |
3189 | return ret; | |
3190 | ||
e2ac9628 HS |
3191 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3192 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
b2612722 | 3193 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); |
02b5fb8e DM |
3194 | if (ret < 0) |
3195 | return ret; | |
3196 | ||
b2612722 | 3197 | ret = t4_config_glbl_rss(adap, adap->pf, |
02b5fb8e | 3198 | FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, |
b2e1a3f0 HS |
3199 | FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | |
3200 | FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); | |
02b5fb8e DM |
3201 | if (ret < 0) |
3202 | return ret; | |
3203 | ||
b2612722 | 3204 | ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, |
4b8e27a8 HS |
3205 | MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, |
3206 | FW_CMD_CAP_PF); | |
02b5fb8e DM |
3207 | if (ret < 0) |
3208 | return ret; | |
3209 | ||
3210 | t4_sge_init(adap); | |
3211 | ||
02b5fb8e | 3212 | /* tweak some settings */ |
837e4a42 | 3213 | t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); |
0d804338 | 3214 | t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); |
837e4a42 HS |
3215 | t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); |
3216 | v = t4_read_reg(adap, TP_PIO_DATA_A); | |
3217 | t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); | |
060e0c75 | 3218 | |
dca4faeb VP |
3219 | /* first 4 Tx modulation queues point to consecutive Tx channels */ |
3220 | adap->params.tp.tx_modq_map = 0xE4; | |
0d804338 HS |
3221 | t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, |
3222 | TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); | |
dca4faeb VP |
3223 | |
3224 | /* associate each Tx modulation queue with consecutive Tx channels */ | |
3225 | v = 0x84218421; | |
837e4a42 | 3226 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3227 | &v, 1, TP_TX_SCHED_HDR_A); |
837e4a42 | 3228 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3229 | &v, 1, TP_TX_SCHED_FIFO_A); |
837e4a42 | 3230 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 3231 | &v, 1, TP_TX_SCHED_PCMD_A); |
dca4faeb VP |
3232 | |
3233 | #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ | |
3234 | if (is_offload(adap)) { | |
0d804338 HS |
3235 | t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, |
3236 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3237 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3238 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3239 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
3240 | t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, | |
3241 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3242 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3243 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
3244 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
dca4faeb VP |
3245 | } |
3246 | ||
060e0c75 | 3247 | /* get basic stuff going */ |
b2612722 | 3248 | return t4_early_init(adap, adap->pf); |
02b5fb8e DM |
3249 | } |
3250 | ||
b8ff05a9 DM |
3251 | /* |
3252 | * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. | |
3253 | */ | |
3254 | #define MAX_ATIDS 8192U | |
3255 | ||
636f9d37 VP |
3256 | /* |
3257 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
3258 | * | |
3259 | * If the firmware we're dealing with has Configuration File support, then | |
3260 | * we use that to perform all configuration | |
3261 | */ | |
3262 | ||
3263 | /* | |
3264 | * Tweak configuration based on module parameters, etc. Most of these have | |
3265 | * defaults assigned to them by Firmware Configuration Files (if we're using | |
3266 | * them) but need to be explicitly set if we're using hard-coded | |
3267 | * initialization. But even in the case of using Firmware Configuration | |
3268 | * Files, we'd like to expose the ability to change these via module | |
3269 | * parameters so these are essentially common tweaks/settings for | |
3270 | * Configuration Files and hard-coded initialization ... | |
3271 | */ | |
3272 | static int adap_init0_tweaks(struct adapter *adapter) | |
3273 | { | |
3274 | /* | |
3275 | * Fix up various Host-Dependent Parameters like Page Size, Cache | |
3276 | * Line Size, etc. The firmware default is for a 4KB Page Size and | |
3277 | * 64B Cache Line Size ... | |
3278 | */ | |
3279 | t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); | |
3280 | ||
3281 | /* | |
3282 | * Process module parameters which affect early initialization. | |
3283 | */ | |
3284 | if (rx_dma_offset != 2 && rx_dma_offset != 0) { | |
3285 | dev_err(&adapter->pdev->dev, | |
3286 | "Ignoring illegal rx_dma_offset=%d, using 2\n", | |
3287 | rx_dma_offset); | |
3288 | rx_dma_offset = 2; | |
3289 | } | |
f612b815 HS |
3290 | t4_set_reg_field(adapter, SGE_CONTROL_A, |
3291 | PKTSHIFT_V(PKTSHIFT_M), | |
3292 | PKTSHIFT_V(rx_dma_offset)); | |
636f9d37 VP |
3293 | |
3294 | /* | |
3295 | * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux | |
3296 | * adds the pseudo header itself. | |
3297 | */ | |
837e4a42 HS |
3298 | t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, |
3299 | CSUM_HAS_PSEUDO_HDR_F, 0); | |
636f9d37 VP |
3300 | |
3301 | return 0; | |
3302 | } | |
3303 | ||
01b69614 HS |
3304 | /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips |
3305 | * unto themselves and they contain their own firmware to perform their | |
3306 | * tasks ... | |
3307 | */ | |
3308 | static int phy_aq1202_version(const u8 *phy_fw_data, | |
3309 | size_t phy_fw_size) | |
3310 | { | |
3311 | int offset; | |
3312 | ||
3313 | /* At offset 0x8 you're looking for the primary image's | |
3314 | * starting offset which is 3 Bytes wide | |
3315 | * | |
3316 | * At offset 0xa of the primary image, you look for the offset | |
3317 | * of the DRAM segment which is 3 Bytes wide. | |
3318 | * | |
3319 | * The FW version is at offset 0x27e of the DRAM and is 2 Bytes | |
3320 | * wide | |
3321 | */ | |
3322 | #define be16(__p) (((__p)[0] << 8) | (__p)[1]) | |
3323 | #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) | |
3324 | #define le24(__p) (le16(__p) | ((__p)[2] << 16)) | |
3325 | ||
3326 | offset = le24(phy_fw_data + 0x8) << 12; | |
3327 | offset = le24(phy_fw_data + offset + 0xa); | |
3328 | return be16(phy_fw_data + offset + 0x27e); | |
3329 | ||
3330 | #undef be16 | |
3331 | #undef le16 | |
3332 | #undef le24 | |
3333 | } | |
3334 | ||
3335 | static struct info_10gbt_phy_fw { | |
3336 | unsigned int phy_fw_id; /* PCI Device ID */ | |
3337 | char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ | |
3338 | int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); | |
3339 | int phy_flash; /* Has FLASH for PHY Firmware */ | |
3340 | } phy_info_array[] = { | |
3341 | { | |
3342 | PHY_AQ1202_DEVICEID, | |
3343 | PHY_AQ1202_FIRMWARE, | |
3344 | phy_aq1202_version, | |
3345 | 1, | |
3346 | }, | |
3347 | { | |
3348 | PHY_BCM84834_DEVICEID, | |
3349 | PHY_BCM84834_FIRMWARE, | |
3350 | NULL, | |
3351 | 0, | |
3352 | }, | |
3353 | { 0, NULL, NULL }, | |
3354 | }; | |
3355 | ||
3356 | static struct info_10gbt_phy_fw *find_phy_info(int devid) | |
3357 | { | |
3358 | int i; | |
3359 | ||
3360 | for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { | |
3361 | if (phy_info_array[i].phy_fw_id == devid) | |
3362 | return &phy_info_array[i]; | |
3363 | } | |
3364 | return NULL; | |
3365 | } | |
3366 | ||
3367 | /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to | |
3368 | * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error | |
3369 | * we return a negative error number. If we transfer new firmware we return 1 | |
3370 | * (from t4_load_phy_fw()). If we don't do anything we return 0. | |
3371 | */ | |
3372 | static int adap_init0_phy(struct adapter *adap) | |
3373 | { | |
3374 | const struct firmware *phyf; | |
3375 | int ret; | |
3376 | struct info_10gbt_phy_fw *phy_info; | |
3377 | ||
3378 | /* Use the device ID to determine which PHY file to flash. | |
3379 | */ | |
3380 | phy_info = find_phy_info(adap->pdev->device); | |
3381 | if (!phy_info) { | |
3382 | dev_warn(adap->pdev_dev, | |
3383 | "No PHY Firmware file found for this PHY\n"); | |
3384 | return -EOPNOTSUPP; | |
3385 | } | |
3386 | ||
3387 | /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then | |
3388 | * use that. The adapter firmware provides us with a memory buffer | |
3389 | * where we can load a PHY firmware file from the host if we want to | |
3390 | * override the PHY firmware File in flash. | |
3391 | */ | |
3392 | ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, | |
3393 | adap->pdev_dev); | |
3394 | if (ret < 0) { | |
3395 | /* For adapters without FLASH attached to PHY for their | |
3396 | * firmware, it's obviously a fatal error if we can't get the | |
3397 | * firmware to the adapter. For adapters with PHY firmware | |
3398 | * FLASH storage, it's worth a warning if we can't find the | |
3399 | * PHY Firmware but we'll neuter the error ... | |
3400 | */ | |
3401 | dev_err(adap->pdev_dev, "unable to find PHY Firmware image " | |
3402 | "/lib/firmware/%s, error %d\n", | |
3403 | phy_info->phy_fw_file, -ret); | |
3404 | if (phy_info->phy_flash) { | |
3405 | int cur_phy_fw_ver = 0; | |
3406 | ||
3407 | t4_phy_fw_ver(adap, &cur_phy_fw_ver); | |
3408 | dev_warn(adap->pdev_dev, "continuing with, on-adapter " | |
3409 | "FLASH copy, version %#x\n", cur_phy_fw_ver); | |
3410 | ret = 0; | |
3411 | } | |
3412 | ||
3413 | return ret; | |
3414 | } | |
3415 | ||
3416 | /* Load PHY Firmware onto adapter. | |
3417 | */ | |
3418 | ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, | |
3419 | phy_info->phy_fw_version, | |
3420 | (u8 *)phyf->data, phyf->size); | |
3421 | if (ret < 0) | |
3422 | dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", | |
3423 | -ret); | |
3424 | else if (ret > 0) { | |
3425 | int new_phy_fw_ver = 0; | |
3426 | ||
3427 | if (phy_info->phy_fw_version) | |
3428 | new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, | |
3429 | phyf->size); | |
3430 | dev_info(adap->pdev_dev, "Successfully transferred PHY " | |
3431 | "Firmware /lib/firmware/%s, version %#x\n", | |
3432 | phy_info->phy_fw_file, new_phy_fw_ver); | |
3433 | } | |
3434 | ||
3435 | release_firmware(phyf); | |
3436 | ||
3437 | return ret; | |
3438 | } | |
3439 | ||
636f9d37 VP |
3440 | /* |
3441 | * Attempt to initialize the adapter via a Firmware Configuration File. | |
3442 | */ | |
3443 | static int adap_init0_config(struct adapter *adapter, int reset) | |
3444 | { | |
3445 | struct fw_caps_config_cmd caps_cmd; | |
3446 | const struct firmware *cf; | |
3447 | unsigned long mtype = 0, maddr = 0; | |
3448 | u32 finiver, finicsum, cfcsum; | |
16e47624 HS |
3449 | int ret; |
3450 | int config_issued = 0; | |
0a57a536 | 3451 | char *fw_config_file, fw_config_file_path[256]; |
16e47624 | 3452 | char *config_name = NULL; |
636f9d37 VP |
3453 | |
3454 | /* | |
3455 | * Reset device if necessary. | |
3456 | */ | |
3457 | if (reset) { | |
3458 | ret = t4_fw_reset(adapter, adapter->mbox, | |
0d804338 | 3459 | PIORSTMODE_F | PIORST_F); |
636f9d37 VP |
3460 | if (ret < 0) |
3461 | goto bye; | |
3462 | } | |
3463 | ||
01b69614 HS |
3464 | /* If this is a 10Gb/s-BT adapter make sure the chip-external |
3465 | * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs | |
3466 | * to be performed after any global adapter RESET above since some | |
3467 | * PHYs only have local RAM copies of the PHY firmware. | |
3468 | */ | |
3469 | if (is_10gbt_device(adapter->pdev->device)) { | |
3470 | ret = adap_init0_phy(adapter); | |
3471 | if (ret < 0) | |
3472 | goto bye; | |
3473 | } | |
636f9d37 VP |
3474 | /* |
3475 | * If we have a T4 configuration file under /lib/firmware/cxgb4/, | |
3476 | * then use that. Otherwise, use the configuration file stored | |
3477 | * in the adapter flash ... | |
3478 | */ | |
d14807dd | 3479 | switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { |
0a57a536 | 3480 | case CHELSIO_T4: |
16e47624 | 3481 | fw_config_file = FW4_CFNAME; |
0a57a536 SR |
3482 | break; |
3483 | case CHELSIO_T5: | |
3484 | fw_config_file = FW5_CFNAME; | |
3485 | break; | |
3ccc6cf7 HS |
3486 | case CHELSIO_T6: |
3487 | fw_config_file = FW6_CFNAME; | |
3488 | break; | |
0a57a536 SR |
3489 | default: |
3490 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", | |
3491 | adapter->pdev->device); | |
3492 | ret = -EINVAL; | |
3493 | goto bye; | |
3494 | } | |
3495 | ||
3496 | ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); | |
636f9d37 | 3497 | if (ret < 0) { |
16e47624 | 3498 | config_name = "On FLASH"; |
636f9d37 VP |
3499 | mtype = FW_MEMTYPE_CF_FLASH; |
3500 | maddr = t4_flash_cfg_addr(adapter); | |
3501 | } else { | |
3502 | u32 params[7], val[7]; | |
3503 | ||
16e47624 HS |
3504 | sprintf(fw_config_file_path, |
3505 | "/lib/firmware/%s", fw_config_file); | |
3506 | config_name = fw_config_file_path; | |
3507 | ||
636f9d37 VP |
3508 | if (cf->size >= FLASH_CFG_MAX_SIZE) |
3509 | ret = -ENOMEM; | |
3510 | else { | |
5167865a HS |
3511 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3512 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
636f9d37 | 3513 | ret = t4_query_params(adapter, adapter->mbox, |
b2612722 | 3514 | adapter->pf, 0, 1, params, val); |
636f9d37 VP |
3515 | if (ret == 0) { |
3516 | /* | |
fc5ab020 | 3517 | * For t4_memory_rw() below addresses and |
636f9d37 VP |
3518 | * sizes have to be in terms of multiples of 4 |
3519 | * bytes. So, if the Configuration File isn't | |
3520 | * a multiple of 4 bytes in length we'll have | |
3521 | * to write that out separately since we can't | |
3522 | * guarantee that the bytes following the | |
3523 | * residual byte in the buffer returned by | |
3524 | * request_firmware() are zeroed out ... | |
3525 | */ | |
3526 | size_t resid = cf->size & 0x3; | |
3527 | size_t size = cf->size & ~0x3; | |
3528 | __be32 *data = (__be32 *)cf->data; | |
3529 | ||
5167865a HS |
3530 | mtype = FW_PARAMS_PARAM_Y_G(val[0]); |
3531 | maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; | |
636f9d37 | 3532 | |
fc5ab020 HS |
3533 | spin_lock(&adapter->win0_lock); |
3534 | ret = t4_memory_rw(adapter, 0, mtype, maddr, | |
3535 | size, data, T4_MEMORY_WRITE); | |
636f9d37 VP |
3536 | if (ret == 0 && resid != 0) { |
3537 | union { | |
3538 | __be32 word; | |
3539 | char buf[4]; | |
3540 | } last; | |
3541 | int i; | |
3542 | ||
3543 | last.word = data[size >> 2]; | |
3544 | for (i = resid; i < 4; i++) | |
3545 | last.buf[i] = 0; | |
fc5ab020 HS |
3546 | ret = t4_memory_rw(adapter, 0, mtype, |
3547 | maddr + size, | |
3548 | 4, &last.word, | |
3549 | T4_MEMORY_WRITE); | |
636f9d37 | 3550 | } |
fc5ab020 | 3551 | spin_unlock(&adapter->win0_lock); |
636f9d37 VP |
3552 | } |
3553 | } | |
3554 | ||
3555 | release_firmware(cf); | |
3556 | if (ret) | |
3557 | goto bye; | |
3558 | } | |
3559 | ||
3560 | /* | |
3561 | * Issue a Capability Configuration command to the firmware to get it | |
3562 | * to parse the Configuration File. We don't use t4_fw_config_file() | |
3563 | * because we want the ability to modify various features after we've | |
3564 | * processed the configuration file ... | |
3565 | */ | |
3566 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3567 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3568 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3569 | FW_CMD_REQUEST_F | | |
3570 | FW_CMD_READ_F); | |
ce91a923 | 3571 | caps_cmd.cfvalid_to_len16 = |
5167865a HS |
3572 | htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | |
3573 | FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | | |
3574 | FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | | |
636f9d37 VP |
3575 | FW_LEN16(caps_cmd)); |
3576 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), | |
3577 | &caps_cmd); | |
16e47624 HS |
3578 | |
3579 | /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware | |
3580 | * Configuration File in FLASH), our last gasp effort is to use the | |
3581 | * Firmware Configuration File which is embedded in the firmware. A | |
3582 | * very few early versions of the firmware didn't have one embedded | |
3583 | * but we can ignore those. | |
3584 | */ | |
3585 | if (ret == -ENOENT) { | |
3586 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3587 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3588 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3589 | FW_CMD_REQUEST_F | | |
3590 | FW_CMD_READ_F); | |
16e47624 HS |
3591 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
3592 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, | |
3593 | sizeof(caps_cmd), &caps_cmd); | |
3594 | config_name = "Firmware Default"; | |
3595 | } | |
3596 | ||
3597 | config_issued = 1; | |
636f9d37 VP |
3598 | if (ret < 0) |
3599 | goto bye; | |
3600 | ||
3601 | finiver = ntohl(caps_cmd.finiver); | |
3602 | finicsum = ntohl(caps_cmd.finicsum); | |
3603 | cfcsum = ntohl(caps_cmd.cfcsum); | |
3604 | if (finicsum != cfcsum) | |
3605 | dev_warn(adapter->pdev_dev, "Configuration File checksum "\ | |
3606 | "mismatch: [fini] csum=%#x, computed csum=%#x\n", | |
3607 | finicsum, cfcsum); | |
3608 | ||
636f9d37 VP |
3609 | /* |
3610 | * And now tell the firmware to use the configuration we just loaded. | |
3611 | */ | |
3612 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3613 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3614 | FW_CMD_REQUEST_F | | |
3615 | FW_CMD_WRITE_F); | |
ce91a923 | 3616 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
3617 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), |
3618 | NULL); | |
3619 | if (ret < 0) | |
3620 | goto bye; | |
3621 | ||
3622 | /* | |
3623 | * Tweak configuration based on system architecture, module | |
3624 | * parameters, etc. | |
3625 | */ | |
3626 | ret = adap_init0_tweaks(adapter); | |
3627 | if (ret < 0) | |
3628 | goto bye; | |
3629 | ||
3630 | /* | |
3631 | * And finally tell the firmware to initialize itself using the | |
3632 | * parameters from the Configuration File. | |
3633 | */ | |
3634 | ret = t4_fw_initialize(adapter, adapter->mbox); | |
3635 | if (ret < 0) | |
3636 | goto bye; | |
3637 | ||
06640310 HS |
3638 | /* Emit Firmware Configuration File information and return |
3639 | * successfully. | |
636f9d37 | 3640 | */ |
636f9d37 | 3641 | dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ |
16e47624 HS |
3642 | "Configuration File \"%s\", version %#x, computed checksum %#x\n", |
3643 | config_name, finiver, cfcsum); | |
636f9d37 VP |
3644 | return 0; |
3645 | ||
3646 | /* | |
3647 | * Something bad happened. Return the error ... (If the "error" | |
3648 | * is that there's no Configuration File on the adapter we don't | |
3649 | * want to issue a warning since this is fairly common.) | |
3650 | */ | |
3651 | bye: | |
16e47624 HS |
3652 | if (config_issued && ret != -ENOENT) |
3653 | dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", | |
3654 | config_name, -ret); | |
636f9d37 VP |
3655 | return ret; |
3656 | } | |
3657 | ||
16e47624 HS |
3658 | static struct fw_info fw_info_array[] = { |
3659 | { | |
3660 | .chip = CHELSIO_T4, | |
3661 | .fs_name = FW4_CFNAME, | |
3662 | .fw_mod_name = FW4_FNAME, | |
3663 | .fw_hdr = { | |
3664 | .chip = FW_HDR_CHIP_T4, | |
3665 | .fw_ver = __cpu_to_be32(FW_VERSION(T4)), | |
3666 | .intfver_nic = FW_INTFVER(T4, NIC), | |
3667 | .intfver_vnic = FW_INTFVER(T4, VNIC), | |
3668 | .intfver_ri = FW_INTFVER(T4, RI), | |
3669 | .intfver_iscsi = FW_INTFVER(T4, ISCSI), | |
3670 | .intfver_fcoe = FW_INTFVER(T4, FCOE), | |
3671 | }, | |
3672 | }, { | |
3673 | .chip = CHELSIO_T5, | |
3674 | .fs_name = FW5_CFNAME, | |
3675 | .fw_mod_name = FW5_FNAME, | |
3676 | .fw_hdr = { | |
3677 | .chip = FW_HDR_CHIP_T5, | |
3678 | .fw_ver = __cpu_to_be32(FW_VERSION(T5)), | |
3679 | .intfver_nic = FW_INTFVER(T5, NIC), | |
3680 | .intfver_vnic = FW_INTFVER(T5, VNIC), | |
3681 | .intfver_ri = FW_INTFVER(T5, RI), | |
3682 | .intfver_iscsi = FW_INTFVER(T5, ISCSI), | |
3683 | .intfver_fcoe = FW_INTFVER(T5, FCOE), | |
3684 | }, | |
3ccc6cf7 HS |
3685 | }, { |
3686 | .chip = CHELSIO_T6, | |
3687 | .fs_name = FW6_CFNAME, | |
3688 | .fw_mod_name = FW6_FNAME, | |
3689 | .fw_hdr = { | |
3690 | .chip = FW_HDR_CHIP_T6, | |
3691 | .fw_ver = __cpu_to_be32(FW_VERSION(T6)), | |
3692 | .intfver_nic = FW_INTFVER(T6, NIC), | |
3693 | .intfver_vnic = FW_INTFVER(T6, VNIC), | |
3694 | .intfver_ofld = FW_INTFVER(T6, OFLD), | |
3695 | .intfver_ri = FW_INTFVER(T6, RI), | |
3696 | .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), | |
3697 | .intfver_iscsi = FW_INTFVER(T6, ISCSI), | |
3698 | .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), | |
3699 | .intfver_fcoe = FW_INTFVER(T6, FCOE), | |
3700 | }, | |
16e47624 | 3701 | } |
3ccc6cf7 | 3702 | |
16e47624 HS |
3703 | }; |
3704 | ||
3705 | static struct fw_info *find_fw_info(int chip) | |
3706 | { | |
3707 | int i; | |
3708 | ||
3709 | for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { | |
3710 | if (fw_info_array[i].chip == chip) | |
3711 | return &fw_info_array[i]; | |
3712 | } | |
3713 | return NULL; | |
3714 | } | |
3715 | ||
b8ff05a9 DM |
3716 | /* |
3717 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
3718 | */ | |
3719 | static int adap_init0(struct adapter *adap) | |
3720 | { | |
3721 | int ret; | |
3722 | u32 v, port_vec; | |
3723 | enum dev_state state; | |
3724 | u32 params[7], val[7]; | |
9a4da2cd | 3725 | struct fw_caps_config_cmd caps_cmd; |
dcf7b6f5 | 3726 | int reset = 1; |
b8ff05a9 | 3727 | |
ae469b68 HS |
3728 | /* Grab Firmware Device Log parameters as early as possible so we have |
3729 | * access to it for debugging, etc. | |
3730 | */ | |
3731 | ret = t4_init_devlog_params(adap); | |
3732 | if (ret < 0) | |
3733 | return ret; | |
3734 | ||
666224d4 | 3735 | /* Contact FW, advertising Master capability */ |
c5a8c0f3 HS |
3736 | ret = t4_fw_hello(adap, adap->mbox, adap->mbox, |
3737 | is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); | |
b8ff05a9 DM |
3738 | if (ret < 0) { |
3739 | dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", | |
3740 | ret); | |
3741 | return ret; | |
3742 | } | |
636f9d37 VP |
3743 | if (ret == adap->mbox) |
3744 | adap->flags |= MASTER_PF; | |
b8ff05a9 | 3745 | |
636f9d37 VP |
3746 | /* |
3747 | * If we're the Master PF Driver and the device is uninitialized, | |
3748 | * then let's consider upgrading the firmware ... (We always want | |
3749 | * to check the firmware version number in order to A. get it for | |
3750 | * later reporting and B. to warn if the currently loaded firmware | |
3751 | * is excessively mismatched relative to the driver.) | |
3752 | */ | |
16e47624 | 3753 | t4_get_fw_version(adap, &adap->params.fw_vers); |
0de72738 | 3754 | t4_get_bs_version(adap, &adap->params.bs_vers); |
16e47624 | 3755 | t4_get_tp_version(adap, &adap->params.tp_vers); |
0de72738 HS |
3756 | t4_get_exprom_version(adap, &adap->params.er_vers); |
3757 | ||
a69265e9 HS |
3758 | ret = t4_check_fw_version(adap); |
3759 | /* If firmware is too old (not supported by driver) force an update. */ | |
21d11bd6 | 3760 | if (ret) |
a69265e9 | 3761 | state = DEV_STATE_UNINIT; |
636f9d37 | 3762 | if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { |
16e47624 HS |
3763 | struct fw_info *fw_info; |
3764 | struct fw_hdr *card_fw; | |
3765 | const struct firmware *fw; | |
3766 | const u8 *fw_data = NULL; | |
3767 | unsigned int fw_size = 0; | |
3768 | ||
3769 | /* This is the firmware whose headers the driver was compiled | |
3770 | * against | |
3771 | */ | |
3772 | fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); | |
3773 | if (fw_info == NULL) { | |
3774 | dev_err(adap->pdev_dev, | |
3775 | "unable to get firmware info for chip %d.\n", | |
3776 | CHELSIO_CHIP_VERSION(adap->params.chip)); | |
3777 | return -EINVAL; | |
636f9d37 | 3778 | } |
16e47624 HS |
3779 | |
3780 | /* allocate memory to read the header of the firmware on the | |
3781 | * card | |
3782 | */ | |
3783 | card_fw = t4_alloc_mem(sizeof(*card_fw)); | |
3784 | ||
3785 | /* Get FW from from /lib/firmware/ */ | |
3786 | ret = request_firmware(&fw, fw_info->fw_mod_name, | |
3787 | adap->pdev_dev); | |
3788 | if (ret < 0) { | |
3789 | dev_err(adap->pdev_dev, | |
3790 | "unable to load firmware image %s, error %d\n", | |
3791 | fw_info->fw_mod_name, ret); | |
3792 | } else { | |
3793 | fw_data = fw->data; | |
3794 | fw_size = fw->size; | |
3795 | } | |
3796 | ||
3797 | /* upgrade FW logic */ | |
3798 | ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, | |
3799 | state, &reset); | |
3800 | ||
3801 | /* Cleaning up */ | |
0b5b6bee | 3802 | release_firmware(fw); |
16e47624 HS |
3803 | t4_free_mem(card_fw); |
3804 | ||
636f9d37 | 3805 | if (ret < 0) |
16e47624 | 3806 | goto bye; |
636f9d37 | 3807 | } |
b8ff05a9 | 3808 | |
636f9d37 VP |
3809 | /* |
3810 | * Grab VPD parameters. This should be done after we establish a | |
3811 | * connection to the firmware since some of the VPD parameters | |
3812 | * (notably the Core Clock frequency) are retrieved via requests to | |
3813 | * the firmware. On the other hand, we need these fairly early on | |
3814 | * so we do this right after getting ahold of the firmware. | |
3815 | */ | |
098ef6c2 | 3816 | ret = t4_get_vpd_params(adap, &adap->params.vpd); |
a0881cab DM |
3817 | if (ret < 0) |
3818 | goto bye; | |
a0881cab | 3819 | |
636f9d37 | 3820 | /* |
13ee15d3 VP |
3821 | * Find out what ports are available to us. Note that we need to do |
3822 | * this before calling adap_init0_no_config() since it needs nports | |
3823 | * and portvec ... | |
636f9d37 VP |
3824 | */ |
3825 | v = | |
5167865a HS |
3826 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3827 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); | |
b2612722 | 3828 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); |
a0881cab DM |
3829 | if (ret < 0) |
3830 | goto bye; | |
3831 | ||
636f9d37 VP |
3832 | adap->params.nports = hweight32(port_vec); |
3833 | adap->params.portvec = port_vec; | |
3834 | ||
06640310 HS |
3835 | /* If the firmware is initialized already, emit a simply note to that |
3836 | * effect. Otherwise, it's time to try initializing the adapter. | |
636f9d37 VP |
3837 | */ |
3838 | if (state == DEV_STATE_INIT) { | |
3839 | dev_info(adap->pdev_dev, "Coming up as %s: "\ | |
3840 | "Adapter already initialized\n", | |
3841 | adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); | |
636f9d37 VP |
3842 | } else { |
3843 | dev_info(adap->pdev_dev, "Coming up as MASTER: "\ | |
3844 | "Initializing adapter\n"); | |
06640310 HS |
3845 | |
3846 | /* Find out whether we're dealing with a version of the | |
3847 | * firmware which has configuration file support. | |
636f9d37 | 3848 | */ |
06640310 HS |
3849 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3850 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
b2612722 | 3851 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, |
06640310 | 3852 | params, val); |
13ee15d3 | 3853 | |
06640310 HS |
3854 | /* If the firmware doesn't support Configuration Files, |
3855 | * return an error. | |
3856 | */ | |
3857 | if (ret < 0) { | |
3858 | dev_err(adap->pdev_dev, "firmware doesn't support " | |
3859 | "Firmware Configuration Files\n"); | |
3860 | goto bye; | |
3861 | } | |
3862 | ||
3863 | /* The firmware provides us with a memory buffer where we can | |
3864 | * load a Configuration File from the host if we want to | |
3865 | * override the Configuration File in flash. | |
3866 | */ | |
3867 | ret = adap_init0_config(adap, reset); | |
3868 | if (ret == -ENOENT) { | |
3869 | dev_err(adap->pdev_dev, "no Configuration File " | |
3870 | "present on adapter.\n"); | |
3871 | goto bye; | |
636f9d37 VP |
3872 | } |
3873 | if (ret < 0) { | |
06640310 HS |
3874 | dev_err(adap->pdev_dev, "could not initialize " |
3875 | "adapter, error %d\n", -ret); | |
636f9d37 VP |
3876 | goto bye; |
3877 | } | |
3878 | } | |
3879 | ||
06640310 HS |
3880 | /* Give the SGE code a chance to pull in anything that it needs ... |
3881 | * Note that this must be called after we retrieve our VPD parameters | |
3882 | * in order to know how to convert core ticks to seconds, etc. | |
636f9d37 | 3883 | */ |
06640310 HS |
3884 | ret = t4_sge_init(adap); |
3885 | if (ret < 0) | |
3886 | goto bye; | |
636f9d37 | 3887 | |
9a4da2cd VP |
3888 | if (is_bypass_device(adap->pdev->device)) |
3889 | adap->params.bypass = 1; | |
3890 | ||
636f9d37 VP |
3891 | /* |
3892 | * Grab some of our basic fundamental operating parameters. | |
3893 | */ | |
3894 | #define FW_PARAM_DEV(param) \ | |
5167865a HS |
3895 | (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ |
3896 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) | |
636f9d37 | 3897 | |
b8ff05a9 | 3898 | #define FW_PARAM_PFVF(param) \ |
5167865a HS |
3899 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ |
3900 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ | |
3901 | FW_PARAMS_PARAM_Y_V(0) | \ | |
3902 | FW_PARAMS_PARAM_Z_V(0) | |
b8ff05a9 | 3903 | |
636f9d37 | 3904 | params[0] = FW_PARAM_PFVF(EQ_START); |
b8ff05a9 DM |
3905 | params[1] = FW_PARAM_PFVF(L2T_START); |
3906 | params[2] = FW_PARAM_PFVF(L2T_END); | |
3907 | params[3] = FW_PARAM_PFVF(FILTER_START); | |
3908 | params[4] = FW_PARAM_PFVF(FILTER_END); | |
e46dab4d | 3909 | params[5] = FW_PARAM_PFVF(IQFLINT_START); |
b2612722 | 3910 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); |
b8ff05a9 DM |
3911 | if (ret < 0) |
3912 | goto bye; | |
636f9d37 VP |
3913 | adap->sge.egr_start = val[0]; |
3914 | adap->l2t_start = val[1]; | |
3915 | adap->l2t_end = val[2]; | |
b8ff05a9 DM |
3916 | adap->tids.ftid_base = val[3]; |
3917 | adap->tids.nftids = val[4] - val[3] + 1; | |
e46dab4d | 3918 | adap->sge.ingr_start = val[5]; |
b8ff05a9 | 3919 | |
4b8e27a8 HS |
3920 | /* qids (ingress/egress) returned from firmware can be anywhere |
3921 | * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. | |
3922 | * Hence driver needs to allocate memory for this range to | |
3923 | * store the queue info. Get the highest IQFLINT/EQ index returned | |
3924 | * in FW_EQ_*_CMD.alloc command. | |
3925 | */ | |
3926 | params[0] = FW_PARAM_PFVF(EQ_END); | |
3927 | params[1] = FW_PARAM_PFVF(IQFLINT_END); | |
b2612722 | 3928 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
4b8e27a8 HS |
3929 | if (ret < 0) |
3930 | goto bye; | |
3931 | adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; | |
3932 | adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; | |
3933 | ||
3934 | adap->sge.egr_map = kcalloc(adap->sge.egr_sz, | |
3935 | sizeof(*adap->sge.egr_map), GFP_KERNEL); | |
3936 | if (!adap->sge.egr_map) { | |
3937 | ret = -ENOMEM; | |
3938 | goto bye; | |
3939 | } | |
3940 | ||
3941 | adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, | |
3942 | sizeof(*adap->sge.ingr_map), GFP_KERNEL); | |
3943 | if (!adap->sge.ingr_map) { | |
3944 | ret = -ENOMEM; | |
3945 | goto bye; | |
3946 | } | |
3947 | ||
3948 | /* Allocate the memory for the vaious egress queue bitmaps | |
5b377d11 | 3949 | * ie starving_fl, txq_maperr and blocked_fl. |
4b8e27a8 HS |
3950 | */ |
3951 | adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3952 | sizeof(long), GFP_KERNEL); | |
3953 | if (!adap->sge.starving_fl) { | |
3954 | ret = -ENOMEM; | |
3955 | goto bye; | |
3956 | } | |
3957 | ||
3958 | adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3959 | sizeof(long), GFP_KERNEL); | |
3960 | if (!adap->sge.txq_maperr) { | |
3961 | ret = -ENOMEM; | |
3962 | goto bye; | |
3963 | } | |
3964 | ||
5b377d11 HS |
3965 | #ifdef CONFIG_DEBUG_FS |
3966 | adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3967 | sizeof(long), GFP_KERNEL); | |
3968 | if (!adap->sge.blocked_fl) { | |
3969 | ret = -ENOMEM; | |
3970 | goto bye; | |
3971 | } | |
3972 | #endif | |
3973 | ||
b5a02f50 AB |
3974 | params[0] = FW_PARAM_PFVF(CLIP_START); |
3975 | params[1] = FW_PARAM_PFVF(CLIP_END); | |
b2612722 | 3976 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
b5a02f50 AB |
3977 | if (ret < 0) |
3978 | goto bye; | |
3979 | adap->clipt_start = val[0]; | |
3980 | adap->clipt_end = val[1]; | |
3981 | ||
636f9d37 VP |
3982 | /* query params related to active filter region */ |
3983 | params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); | |
3984 | params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); | |
b2612722 | 3985 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
636f9d37 VP |
3986 | /* If Active filter size is set we enable establishing |
3987 | * offload connection through firmware work request | |
3988 | */ | |
3989 | if ((val[0] != val[1]) && (ret >= 0)) { | |
3990 | adap->flags |= FW_OFLD_CONN; | |
3991 | adap->tids.aftid_base = val[0]; | |
3992 | adap->tids.aftid_end = val[1]; | |
3993 | } | |
3994 | ||
b407a4a9 VP |
3995 | /* If we're running on newer firmware, let it know that we're |
3996 | * prepared to deal with encapsulated CPL messages. Older | |
3997 | * firmware won't understand this and we'll just get | |
3998 | * unencapsulated messages ... | |
3999 | */ | |
4000 | params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); | |
4001 | val[0] = 1; | |
b2612722 | 4002 | (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); |
b407a4a9 | 4003 | |
1ac0f095 KS |
4004 | /* |
4005 | * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL | |
4006 | * capability. Earlier versions of the firmware didn't have the | |
4007 | * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no | |
4008 | * permission to use ULPTX MEMWRITE DSGL. | |
4009 | */ | |
4010 | if (is_t4(adap->params.chip)) { | |
4011 | adap->params.ulptx_memwrite_dsgl = false; | |
4012 | } else { | |
4013 | params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); | |
b2612722 | 4014 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, |
1ac0f095 KS |
4015 | 1, params, val); |
4016 | adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); | |
4017 | } | |
4018 | ||
636f9d37 VP |
4019 | /* |
4020 | * Get device capabilities so we can determine what resources we need | |
4021 | * to manage. | |
4022 | */ | |
4023 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
e2ac9628 HS |
4024 | caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
4025 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 4026 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
4027 | ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), |
4028 | &caps_cmd); | |
4029 | if (ret < 0) | |
4030 | goto bye; | |
4031 | ||
13ee15d3 | 4032 | if (caps_cmd.ofldcaps) { |
b8ff05a9 DM |
4033 | /* query offload-related parameters */ |
4034 | params[0] = FW_PARAM_DEV(NTID); | |
4035 | params[1] = FW_PARAM_PFVF(SERVER_START); | |
4036 | params[2] = FW_PARAM_PFVF(SERVER_END); | |
4037 | params[3] = FW_PARAM_PFVF(TDDP_START); | |
4038 | params[4] = FW_PARAM_PFVF(TDDP_END); | |
4039 | params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); | |
b2612722 | 4040 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 4041 | params, val); |
b8ff05a9 DM |
4042 | if (ret < 0) |
4043 | goto bye; | |
4044 | adap->tids.ntids = val[0]; | |
4045 | adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); | |
4046 | adap->tids.stid_base = val[1]; | |
4047 | adap->tids.nstids = val[2] - val[1] + 1; | |
636f9d37 | 4048 | /* |
dbedd44e | 4049 | * Setup server filter region. Divide the available filter |
636f9d37 VP |
4050 | * region into two parts. Regular filters get 1/3rd and server |
4051 | * filters get 2/3rd part. This is only enabled if workarond | |
4052 | * path is enabled. | |
4053 | * 1. For regular filters. | |
4054 | * 2. Server filter: This are special filters which are used | |
4055 | * to redirect SYN packets to offload queue. | |
4056 | */ | |
4057 | if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { | |
4058 | adap->tids.sftid_base = adap->tids.ftid_base + | |
4059 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
4060 | adap->tids.nsftids = adap->tids.nftids - | |
4061 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
4062 | adap->tids.nftids = adap->tids.sftid_base - | |
4063 | adap->tids.ftid_base; | |
4064 | } | |
b8ff05a9 DM |
4065 | adap->vres.ddp.start = val[3]; |
4066 | adap->vres.ddp.size = val[4] - val[3] + 1; | |
4067 | adap->params.ofldq_wr_cred = val[5]; | |
636f9d37 | 4068 | |
b8ff05a9 DM |
4069 | adap->params.offload = 1; |
4070 | } | |
636f9d37 | 4071 | if (caps_cmd.rdmacaps) { |
b8ff05a9 DM |
4072 | params[0] = FW_PARAM_PFVF(STAG_START); |
4073 | params[1] = FW_PARAM_PFVF(STAG_END); | |
4074 | params[2] = FW_PARAM_PFVF(RQ_START); | |
4075 | params[3] = FW_PARAM_PFVF(RQ_END); | |
4076 | params[4] = FW_PARAM_PFVF(PBL_START); | |
4077 | params[5] = FW_PARAM_PFVF(PBL_END); | |
b2612722 | 4078 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 4079 | params, val); |
b8ff05a9 DM |
4080 | if (ret < 0) |
4081 | goto bye; | |
4082 | adap->vres.stag.start = val[0]; | |
4083 | adap->vres.stag.size = val[1] - val[0] + 1; | |
4084 | adap->vres.rq.start = val[2]; | |
4085 | adap->vres.rq.size = val[3] - val[2] + 1; | |
4086 | adap->vres.pbl.start = val[4]; | |
4087 | adap->vres.pbl.size = val[5] - val[4] + 1; | |
a0881cab DM |
4088 | |
4089 | params[0] = FW_PARAM_PFVF(SQRQ_START); | |
4090 | params[1] = FW_PARAM_PFVF(SQRQ_END); | |
4091 | params[2] = FW_PARAM_PFVF(CQ_START); | |
4092 | params[3] = FW_PARAM_PFVF(CQ_END); | |
1ae970e0 DM |
4093 | params[4] = FW_PARAM_PFVF(OCQ_START); |
4094 | params[5] = FW_PARAM_PFVF(OCQ_END); | |
b2612722 | 4095 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, |
5c937dd3 | 4096 | val); |
a0881cab DM |
4097 | if (ret < 0) |
4098 | goto bye; | |
4099 | adap->vres.qp.start = val[0]; | |
4100 | adap->vres.qp.size = val[1] - val[0] + 1; | |
4101 | adap->vres.cq.start = val[2]; | |
4102 | adap->vres.cq.size = val[3] - val[2] + 1; | |
1ae970e0 DM |
4103 | adap->vres.ocq.start = val[4]; |
4104 | adap->vres.ocq.size = val[5] - val[4] + 1; | |
4c2c5763 HS |
4105 | |
4106 | params[0] = FW_PARAM_DEV(MAXORDIRD_QP); | |
4107 | params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); | |
b2612722 | 4108 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, |
5c937dd3 | 4109 | val); |
4c2c5763 HS |
4110 | if (ret < 0) { |
4111 | adap->params.max_ordird_qp = 8; | |
4112 | adap->params.max_ird_adapter = 32 * adap->tids.ntids; | |
4113 | ret = 0; | |
4114 | } else { | |
4115 | adap->params.max_ordird_qp = val[0]; | |
4116 | adap->params.max_ird_adapter = val[1]; | |
4117 | } | |
4118 | dev_info(adap->pdev_dev, | |
4119 | "max_ordird_qp %d max_ird_adapter %d\n", | |
4120 | adap->params.max_ordird_qp, | |
4121 | adap->params.max_ird_adapter); | |
b8ff05a9 | 4122 | } |
636f9d37 | 4123 | if (caps_cmd.iscsicaps) { |
b8ff05a9 DM |
4124 | params[0] = FW_PARAM_PFVF(ISCSI_START); |
4125 | params[1] = FW_PARAM_PFVF(ISCSI_END); | |
b2612722 | 4126 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, |
636f9d37 | 4127 | params, val); |
b8ff05a9 DM |
4128 | if (ret < 0) |
4129 | goto bye; | |
4130 | adap->vres.iscsi.start = val[0]; | |
4131 | adap->vres.iscsi.size = val[1] - val[0] + 1; | |
4132 | } | |
4133 | #undef FW_PARAM_PFVF | |
4134 | #undef FW_PARAM_DEV | |
4135 | ||
92e7ae71 HS |
4136 | /* The MTU/MSS Table is initialized by now, so load their values. If |
4137 | * we're initializing the adapter, then we'll make any modifications | |
4138 | * we want to the MTU/MSS Table and also initialize the congestion | |
4139 | * parameters. | |
636f9d37 | 4140 | */ |
b8ff05a9 | 4141 | t4_read_mtu_tbl(adap, adap->params.mtus, NULL); |
92e7ae71 HS |
4142 | if (state != DEV_STATE_INIT) { |
4143 | int i; | |
4144 | ||
4145 | /* The default MTU Table contains values 1492 and 1500. | |
4146 | * However, for TCP, it's better to have two values which are | |
4147 | * a multiple of 8 +/- 4 bytes apart near this popular MTU. | |
4148 | * This allows us to have a TCP Data Payload which is a | |
4149 | * multiple of 8 regardless of what combination of TCP Options | |
4150 | * are in use (always a multiple of 4 bytes) which is | |
4151 | * important for performance reasons. For instance, if no | |
4152 | * options are in use, then we have a 20-byte IP header and a | |
4153 | * 20-byte TCP header. In this case, a 1500-byte MSS would | |
4154 | * result in a TCP Data Payload of 1500 - 40 == 1460 bytes | |
4155 | * which is not a multiple of 8. So using an MSS of 1488 in | |
4156 | * this case results in a TCP Data Payload of 1448 bytes which | |
4157 | * is a multiple of 8. On the other hand, if 12-byte TCP Time | |
4158 | * Stamps have been negotiated, then an MTU of 1500 bytes | |
4159 | * results in a TCP Data Payload of 1448 bytes which, as | |
4160 | * above, is a multiple of 8 bytes ... | |
4161 | */ | |
4162 | for (i = 0; i < NMTUS; i++) | |
4163 | if (adap->params.mtus[i] == 1492) { | |
4164 | adap->params.mtus[i] = 1488; | |
4165 | break; | |
4166 | } | |
7ee9ff94 | 4167 | |
92e7ae71 HS |
4168 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, |
4169 | adap->params.b_wnd); | |
4170 | } | |
df64e4d3 | 4171 | t4_init_sge_params(adap); |
636f9d37 | 4172 | adap->flags |= FW_OK; |
c1e9af0c | 4173 | t4_init_tp_params(adap); |
b8ff05a9 DM |
4174 | return 0; |
4175 | ||
4176 | /* | |
636f9d37 VP |
4177 | * Something bad happened. If a command timed out or failed with EIO |
4178 | * FW does not operate within its spec or something catastrophic | |
4179 | * happened to HW/FW, stop issuing commands. | |
b8ff05a9 | 4180 | */ |
636f9d37 | 4181 | bye: |
4b8e27a8 HS |
4182 | kfree(adap->sge.egr_map); |
4183 | kfree(adap->sge.ingr_map); | |
4184 | kfree(adap->sge.starving_fl); | |
4185 | kfree(adap->sge.txq_maperr); | |
5b377d11 HS |
4186 | #ifdef CONFIG_DEBUG_FS |
4187 | kfree(adap->sge.blocked_fl); | |
4188 | #endif | |
636f9d37 VP |
4189 | if (ret != -ETIMEDOUT && ret != -EIO) |
4190 | t4_fw_bye(adap, adap->mbox); | |
b8ff05a9 DM |
4191 | return ret; |
4192 | } | |
4193 | ||
204dc3c0 DM |
4194 | /* EEH callbacks */ |
4195 | ||
4196 | static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, | |
4197 | pci_channel_state_t state) | |
4198 | { | |
4199 | int i; | |
4200 | struct adapter *adap = pci_get_drvdata(pdev); | |
4201 | ||
4202 | if (!adap) | |
4203 | goto out; | |
4204 | ||
4205 | rtnl_lock(); | |
4206 | adap->flags &= ~FW_OK; | |
4207 | notify_ulds(adap, CXGB4_STATE_START_RECOVERY); | |
9fe6cb58 | 4208 | spin_lock(&adap->stats_lock); |
204dc3c0 DM |
4209 | for_each_port(adap, i) { |
4210 | struct net_device *dev = adap->port[i]; | |
4211 | ||
4212 | netif_device_detach(dev); | |
4213 | netif_carrier_off(dev); | |
4214 | } | |
9fe6cb58 | 4215 | spin_unlock(&adap->stats_lock); |
b37987e8 | 4216 | disable_interrupts(adap); |
204dc3c0 DM |
4217 | if (adap->flags & FULL_INIT_DONE) |
4218 | cxgb_down(adap); | |
4219 | rtnl_unlock(); | |
144be3d9 GS |
4220 | if ((adap->flags & DEV_ENABLED)) { |
4221 | pci_disable_device(pdev); | |
4222 | adap->flags &= ~DEV_ENABLED; | |
4223 | } | |
204dc3c0 DM |
4224 | out: return state == pci_channel_io_perm_failure ? |
4225 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
4226 | } | |
4227 | ||
4228 | static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) | |
4229 | { | |
4230 | int i, ret; | |
4231 | struct fw_caps_config_cmd c; | |
4232 | struct adapter *adap = pci_get_drvdata(pdev); | |
4233 | ||
4234 | if (!adap) { | |
4235 | pci_restore_state(pdev); | |
4236 | pci_save_state(pdev); | |
4237 | return PCI_ERS_RESULT_RECOVERED; | |
4238 | } | |
4239 | ||
144be3d9 GS |
4240 | if (!(adap->flags & DEV_ENABLED)) { |
4241 | if (pci_enable_device(pdev)) { | |
4242 | dev_err(&pdev->dev, "Cannot reenable PCI " | |
4243 | "device after reset\n"); | |
4244 | return PCI_ERS_RESULT_DISCONNECT; | |
4245 | } | |
4246 | adap->flags |= DEV_ENABLED; | |
204dc3c0 DM |
4247 | } |
4248 | ||
4249 | pci_set_master(pdev); | |
4250 | pci_restore_state(pdev); | |
4251 | pci_save_state(pdev); | |
4252 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
4253 | ||
8203b509 | 4254 | if (t4_wait_dev_ready(adap->regs) < 0) |
204dc3c0 | 4255 | return PCI_ERS_RESULT_DISCONNECT; |
b2612722 | 4256 | if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) |
204dc3c0 DM |
4257 | return PCI_ERS_RESULT_DISCONNECT; |
4258 | adap->flags |= FW_OK; | |
4259 | if (adap_init1(adap, &c)) | |
4260 | return PCI_ERS_RESULT_DISCONNECT; | |
4261 | ||
4262 | for_each_port(adap, i) { | |
4263 | struct port_info *p = adap2pinfo(adap, i); | |
4264 | ||
b2612722 | 4265 | ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, |
060e0c75 | 4266 | NULL, NULL); |
204dc3c0 DM |
4267 | if (ret < 0) |
4268 | return PCI_ERS_RESULT_DISCONNECT; | |
4269 | p->viid = ret; | |
4270 | p->xact_addr_filt = -1; | |
4271 | } | |
4272 | ||
4273 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, | |
4274 | adap->params.b_wnd); | |
1ae970e0 | 4275 | setup_memwin(adap); |
204dc3c0 DM |
4276 | if (cxgb_up(adap)) |
4277 | return PCI_ERS_RESULT_DISCONNECT; | |
4278 | return PCI_ERS_RESULT_RECOVERED; | |
4279 | } | |
4280 | ||
4281 | static void eeh_resume(struct pci_dev *pdev) | |
4282 | { | |
4283 | int i; | |
4284 | struct adapter *adap = pci_get_drvdata(pdev); | |
4285 | ||
4286 | if (!adap) | |
4287 | return; | |
4288 | ||
4289 | rtnl_lock(); | |
4290 | for_each_port(adap, i) { | |
4291 | struct net_device *dev = adap->port[i]; | |
4292 | ||
4293 | if (netif_running(dev)) { | |
4294 | link_start(dev); | |
4295 | cxgb_set_rxmode(dev); | |
4296 | } | |
4297 | netif_device_attach(dev); | |
4298 | } | |
4299 | rtnl_unlock(); | |
4300 | } | |
4301 | ||
3646f0e5 | 4302 | static const struct pci_error_handlers cxgb4_eeh = { |
204dc3c0 DM |
4303 | .error_detected = eeh_err_detected, |
4304 | .slot_reset = eeh_slot_reset, | |
4305 | .resume = eeh_resume, | |
4306 | }; | |
4307 | ||
57d8b764 | 4308 | static inline bool is_x_10g_port(const struct link_config *lc) |
b8ff05a9 | 4309 | { |
57d8b764 KS |
4310 | return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 || |
4311 | (lc->supported & FW_PORT_CAP_SPEED_40G) != 0; | |
b8ff05a9 DM |
4312 | } |
4313 | ||
c887ad0e HS |
4314 | static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, |
4315 | unsigned int us, unsigned int cnt, | |
b8ff05a9 DM |
4316 | unsigned int size, unsigned int iqe_size) |
4317 | { | |
c887ad0e | 4318 | q->adap = adap; |
812034f1 | 4319 | cxgb4_set_rspq_intr_params(q, us, cnt); |
b8ff05a9 DM |
4320 | q->iqe_len = iqe_size; |
4321 | q->size = size; | |
4322 | } | |
4323 | ||
4324 | /* | |
4325 | * Perform default configuration of DMA queues depending on the number and type | |
4326 | * of ports we found and the number of available CPUs. Most settings can be | |
4327 | * modified by the admin prior to actual use. | |
4328 | */ | |
91744948 | 4329 | static void cfg_queues(struct adapter *adap) |
b8ff05a9 DM |
4330 | { |
4331 | struct sge *s = &adap->sge; | |
688848b1 AB |
4332 | int i, n10g = 0, qidx = 0; |
4333 | #ifndef CONFIG_CHELSIO_T4_DCB | |
4334 | int q10g = 0; | |
4335 | #endif | |
cf38be6d | 4336 | int ciq_size; |
b8ff05a9 DM |
4337 | |
4338 | for_each_port(adap, i) | |
57d8b764 | 4339 | n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); |
688848b1 AB |
4340 | #ifdef CONFIG_CHELSIO_T4_DCB |
4341 | /* For Data Center Bridging support we need to be able to support up | |
4342 | * to 8 Traffic Priorities; each of which will be assigned to its | |
4343 | * own TX Queue in order to prevent Head-Of-Line Blocking. | |
4344 | */ | |
4345 | if (adap->params.nports * 8 > MAX_ETH_QSETS) { | |
4346 | dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n", | |
4347 | MAX_ETH_QSETS, adap->params.nports * 8); | |
4348 | BUG_ON(1); | |
4349 | } | |
b8ff05a9 | 4350 | |
688848b1 AB |
4351 | for_each_port(adap, i) { |
4352 | struct port_info *pi = adap2pinfo(adap, i); | |
4353 | ||
4354 | pi->first_qset = qidx; | |
4355 | pi->nqsets = 8; | |
4356 | qidx += pi->nqsets; | |
4357 | } | |
4358 | #else /* !CONFIG_CHELSIO_T4_DCB */ | |
b8ff05a9 DM |
4359 | /* |
4360 | * We default to 1 queue per non-10G port and up to # of cores queues | |
4361 | * per 10G port. | |
4362 | */ | |
4363 | if (n10g) | |
4364 | q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; | |
5952dde7 YM |
4365 | if (q10g > netif_get_num_default_rss_queues()) |
4366 | q10g = netif_get_num_default_rss_queues(); | |
b8ff05a9 | 4367 | |
c5a8c0f3 HS |
4368 | /* Reduce memory usage in kdump environment, disable all offload. |
4369 | */ | |
4370 | if (is_kdump_kernel()) | |
4371 | adap->params.offload = 0; | |
4372 | ||
b8ff05a9 DM |
4373 | for_each_port(adap, i) { |
4374 | struct port_info *pi = adap2pinfo(adap, i); | |
4375 | ||
4376 | pi->first_qset = qidx; | |
57d8b764 | 4377 | pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; |
b8ff05a9 DM |
4378 | qidx += pi->nqsets; |
4379 | } | |
688848b1 | 4380 | #endif /* !CONFIG_CHELSIO_T4_DCB */ |
b8ff05a9 DM |
4381 | |
4382 | s->ethqsets = qidx; | |
4383 | s->max_ethqsets = qidx; /* MSI-X may lower it later */ | |
4384 | ||
4385 | if (is_offload(adap)) { | |
4386 | /* | |
4387 | * For offload we use 1 queue/channel if all ports are up to 1G, | |
4388 | * otherwise we divide all available queues amongst the channels | |
4389 | * capped by the number of available cores. | |
4390 | */ | |
4391 | if (n10g) { | |
f90ce561 | 4392 | i = min_t(int, ARRAY_SIZE(s->iscsirxq), |
b8ff05a9 | 4393 | num_online_cpus()); |
f90ce561 | 4394 | s->iscsiqsets = roundup(i, adap->params.nports); |
b8ff05a9 | 4395 | } else |
f90ce561 | 4396 | s->iscsiqsets = adap->params.nports; |
b8ff05a9 DM |
4397 | /* For RDMA one Rx queue per channel suffices */ |
4398 | s->rdmaqs = adap->params.nports; | |
f36e58e5 HS |
4399 | /* Try and allow at least 1 CIQ per cpu rounding down |
4400 | * to the number of ports, with a minimum of 1 per port. | |
4401 | * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port. | |
4402 | * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port. | |
4403 | * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port. | |
4404 | */ | |
4405 | s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus()); | |
4406 | s->rdmaciqs = (s->rdmaciqs / adap->params.nports) * | |
4407 | adap->params.nports; | |
4408 | s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports); | |
f2692d16 VP |
4409 | |
4410 | if (!is_t4(adap->params.chip)) | |
4411 | s->niscsitq = s->iscsiqsets; | |
b8ff05a9 DM |
4412 | } |
4413 | ||
4414 | for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { | |
4415 | struct sge_eth_rxq *r = &s->ethrxq[i]; | |
4416 | ||
c887ad0e | 4417 | init_rspq(adap, &r->rspq, 5, 10, 1024, 64); |
b8ff05a9 DM |
4418 | r->fl.size = 72; |
4419 | } | |
4420 | ||
4421 | for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) | |
4422 | s->ethtxq[i].q.size = 1024; | |
4423 | ||
4424 | for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) | |
4425 | s->ctrlq[i].q.size = 512; | |
4426 | ||
4427 | for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) | |
4428 | s->ofldtxq[i].q.size = 1024; | |
4429 | ||
f90ce561 HS |
4430 | for (i = 0; i < ARRAY_SIZE(s->iscsirxq); i++) { |
4431 | struct sge_ofld_rxq *r = &s->iscsirxq[i]; | |
b8ff05a9 | 4432 | |
c887ad0e | 4433 | init_rspq(adap, &r->rspq, 5, 1, 1024, 64); |
b8ff05a9 DM |
4434 | r->rspq.uld = CXGB4_ULD_ISCSI; |
4435 | r->fl.size = 72; | |
4436 | } | |
4437 | ||
f2692d16 VP |
4438 | if (!is_t4(adap->params.chip)) { |
4439 | for (i = 0; i < ARRAY_SIZE(s->iscsitrxq); i++) { | |
4440 | struct sge_ofld_rxq *r = &s->iscsitrxq[i]; | |
4441 | ||
4442 | init_rspq(adap, &r->rspq, 5, 1, 1024, 64); | |
4443 | r->rspq.uld = CXGB4_ULD_ISCSIT; | |
4444 | r->fl.size = 72; | |
4445 | } | |
4446 | } | |
4447 | ||
b8ff05a9 DM |
4448 | for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) { |
4449 | struct sge_ofld_rxq *r = &s->rdmarxq[i]; | |
4450 | ||
c887ad0e | 4451 | init_rspq(adap, &r->rspq, 5, 1, 511, 64); |
b8ff05a9 DM |
4452 | r->rspq.uld = CXGB4_ULD_RDMA; |
4453 | r->fl.size = 72; | |
4454 | } | |
4455 | ||
cf38be6d HS |
4456 | ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids; |
4457 | if (ciq_size > SGE_MAX_IQ_SIZE) { | |
4458 | CH_WARN(adap, "CIQ size too small for available IQs\n"); | |
4459 | ciq_size = SGE_MAX_IQ_SIZE; | |
4460 | } | |
4461 | ||
4462 | for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) { | |
4463 | struct sge_ofld_rxq *r = &s->rdmaciq[i]; | |
4464 | ||
c887ad0e | 4465 | init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64); |
cf38be6d HS |
4466 | r->rspq.uld = CXGB4_ULD_RDMA; |
4467 | } | |
4468 | ||
c887ad0e HS |
4469 | init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); |
4470 | init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64); | |
b8ff05a9 DM |
4471 | } |
4472 | ||
4473 | /* | |
4474 | * Reduce the number of Ethernet queues across all ports to at most n. | |
4475 | * n provides at least one queue per port. | |
4476 | */ | |
91744948 | 4477 | static void reduce_ethqs(struct adapter *adap, int n) |
b8ff05a9 DM |
4478 | { |
4479 | int i; | |
4480 | struct port_info *pi; | |
4481 | ||
4482 | while (n < adap->sge.ethqsets) | |
4483 | for_each_port(adap, i) { | |
4484 | pi = adap2pinfo(adap, i); | |
4485 | if (pi->nqsets > 1) { | |
4486 | pi->nqsets--; | |
4487 | adap->sge.ethqsets--; | |
4488 | if (adap->sge.ethqsets <= n) | |
4489 | break; | |
4490 | } | |
4491 | } | |
4492 | ||
4493 | n = 0; | |
4494 | for_each_port(adap, i) { | |
4495 | pi = adap2pinfo(adap, i); | |
4496 | pi->first_qset = n; | |
4497 | n += pi->nqsets; | |
4498 | } | |
4499 | } | |
4500 | ||
4501 | /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ | |
4502 | #define EXTRA_VECS 2 | |
4503 | ||
91744948 | 4504 | static int enable_msix(struct adapter *adap) |
b8ff05a9 DM |
4505 | { |
4506 | int ofld_need = 0; | |
f36e58e5 | 4507 | int i, want, need, allocated; |
b8ff05a9 DM |
4508 | struct sge *s = &adap->sge; |
4509 | unsigned int nchan = adap->params.nports; | |
f36e58e5 HS |
4510 | struct msix_entry *entries; |
4511 | ||
4512 | entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1), | |
4513 | GFP_KERNEL); | |
4514 | if (!entries) | |
4515 | return -ENOMEM; | |
b8ff05a9 | 4516 | |
f36e58e5 | 4517 | for (i = 0; i < MAX_INGQ + 1; ++i) |
b8ff05a9 DM |
4518 | entries[i].entry = i; |
4519 | ||
4520 | want = s->max_ethqsets + EXTRA_VECS; | |
4521 | if (is_offload(adap)) { | |
f2692d16 VP |
4522 | want += s->rdmaqs + s->rdmaciqs + s->iscsiqsets + |
4523 | s->niscsitq; | |
b8ff05a9 | 4524 | /* need nchan for each possible ULD */ |
f2692d16 VP |
4525 | if (is_t4(adap->params.chip)) |
4526 | ofld_need = 3 * nchan; | |
4527 | else | |
4528 | ofld_need = 4 * nchan; | |
b8ff05a9 | 4529 | } |
688848b1 AB |
4530 | #ifdef CONFIG_CHELSIO_T4_DCB |
4531 | /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for | |
4532 | * each port. | |
4533 | */ | |
4534 | need = 8 * adap->params.nports + EXTRA_VECS + ofld_need; | |
4535 | #else | |
b8ff05a9 | 4536 | need = adap->params.nports + EXTRA_VECS + ofld_need; |
688848b1 | 4537 | #endif |
f36e58e5 HS |
4538 | allocated = pci_enable_msix_range(adap->pdev, entries, need, want); |
4539 | if (allocated < 0) { | |
4540 | dev_info(adap->pdev_dev, "not enough MSI-X vectors left," | |
4541 | " not using MSI-X\n"); | |
4542 | kfree(entries); | |
4543 | return allocated; | |
4544 | } | |
b8ff05a9 | 4545 | |
f36e58e5 | 4546 | /* Distribute available vectors to the various queue groups. |
c32ad224 AG |
4547 | * Every group gets its minimum requirement and NIC gets top |
4548 | * priority for leftovers. | |
4549 | */ | |
f36e58e5 | 4550 | i = allocated - EXTRA_VECS - ofld_need; |
c32ad224 AG |
4551 | if (i < s->max_ethqsets) { |
4552 | s->max_ethqsets = i; | |
4553 | if (i < s->ethqsets) | |
4554 | reduce_ethqs(adap, i); | |
4555 | } | |
4556 | if (is_offload(adap)) { | |
f36e58e5 HS |
4557 | if (allocated < want) { |
4558 | s->rdmaqs = nchan; | |
4559 | s->rdmaciqs = nchan; | |
f2692d16 VP |
4560 | |
4561 | if (!is_t4(adap->params.chip)) | |
4562 | s->niscsitq = nchan; | |
f36e58e5 HS |
4563 | } |
4564 | ||
4565 | /* leftovers go to OFLD */ | |
4566 | i = allocated - EXTRA_VECS - s->max_ethqsets - | |
f2692d16 | 4567 | s->rdmaqs - s->rdmaciqs - s->niscsitq; |
f90ce561 | 4568 | s->iscsiqsets = (i / nchan) * nchan; /* round down */ |
f2692d16 | 4569 | |
c32ad224 | 4570 | } |
f36e58e5 | 4571 | for (i = 0; i < allocated; ++i) |
c32ad224 | 4572 | adap->msix_info[i].vec = entries[i].vector; |
43eb4e82 HS |
4573 | dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " |
4574 | "nic %d iscsi %d rdma cpl %d rdma ciq %d\n", | |
f90ce561 | 4575 | allocated, s->max_ethqsets, s->iscsiqsets, s->rdmaqs, |
43eb4e82 | 4576 | s->rdmaciqs); |
c32ad224 | 4577 | |
f36e58e5 | 4578 | kfree(entries); |
c32ad224 | 4579 | return 0; |
b8ff05a9 DM |
4580 | } |
4581 | ||
4582 | #undef EXTRA_VECS | |
4583 | ||
91744948 | 4584 | static int init_rss(struct adapter *adap) |
671b0060 | 4585 | { |
c035e183 HS |
4586 | unsigned int i; |
4587 | int err; | |
4588 | ||
4589 | err = t4_init_rss_mode(adap, adap->mbox); | |
4590 | if (err) | |
4591 | return err; | |
671b0060 DM |
4592 | |
4593 | for_each_port(adap, i) { | |
4594 | struct port_info *pi = adap2pinfo(adap, i); | |
4595 | ||
4596 | pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); | |
4597 | if (!pi->rss) | |
4598 | return -ENOMEM; | |
671b0060 DM |
4599 | } |
4600 | return 0; | |
4601 | } | |
4602 | ||
547fd272 HS |
4603 | static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap, |
4604 | enum pci_bus_speed *speed, | |
4605 | enum pcie_link_width *width) | |
4606 | { | |
4607 | u32 lnkcap1, lnkcap2; | |
4608 | int err1, err2; | |
4609 | ||
4610 | #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ | |
4611 | ||
4612 | *speed = PCI_SPEED_UNKNOWN; | |
4613 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4614 | ||
4615 | err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP, | |
4616 | &lnkcap1); | |
4617 | err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2, | |
4618 | &lnkcap2); | |
4619 | if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ | |
4620 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
4621 | *speed = PCIE_SPEED_8_0GT; | |
4622 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
4623 | *speed = PCIE_SPEED_5_0GT; | |
4624 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
4625 | *speed = PCIE_SPEED_2_5GT; | |
4626 | } | |
4627 | if (!err1) { | |
4628 | *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; | |
4629 | if (!lnkcap2) { /* pre-r3.0 */ | |
4630 | if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) | |
4631 | *speed = PCIE_SPEED_5_0GT; | |
4632 | else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) | |
4633 | *speed = PCIE_SPEED_2_5GT; | |
4634 | } | |
4635 | } | |
4636 | ||
4637 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
4638 | return err1 ? err1 : err2 ? err2 : -EINVAL; | |
4639 | return 0; | |
4640 | } | |
4641 | ||
4642 | static void cxgb4_check_pcie_caps(struct adapter *adap) | |
4643 | { | |
4644 | enum pcie_link_width width, width_cap; | |
4645 | enum pci_bus_speed speed, speed_cap; | |
4646 | ||
4647 | #define PCIE_SPEED_STR(speed) \ | |
4648 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ | |
4649 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ | |
4650 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ | |
4651 | "Unknown") | |
4652 | ||
4653 | if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) { | |
4654 | dev_warn(adap->pdev_dev, | |
4655 | "Unable to determine PCIe device BW capabilities\n"); | |
4656 | return; | |
4657 | } | |
4658 | ||
4659 | if (pcie_get_minimum_link(adap->pdev, &speed, &width) || | |
4660 | speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { | |
4661 | dev_warn(adap->pdev_dev, | |
4662 | "Unable to determine PCI Express bandwidth.\n"); | |
4663 | return; | |
4664 | } | |
4665 | ||
4666 | dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n", | |
4667 | PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); | |
4668 | dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n", | |
4669 | width, width_cap); | |
4670 | if (speed < speed_cap || width < width_cap) | |
4671 | dev_info(adap->pdev_dev, | |
4672 | "A slot with more lanes and/or higher speed is " | |
4673 | "suggested for optimal performance.\n"); | |
4674 | } | |
4675 | ||
0de72738 HS |
4676 | /* Dump basic information about the adapter */ |
4677 | static void print_adapter_info(struct adapter *adapter) | |
4678 | { | |
4679 | /* Device information */ | |
4680 | dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n", | |
4681 | adapter->params.vpd.id, | |
4682 | CHELSIO_CHIP_RELEASE(adapter->params.chip)); | |
4683 | dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n", | |
4684 | adapter->params.vpd.sn, adapter->params.vpd.pn); | |
4685 | ||
4686 | /* Firmware Version */ | |
4687 | if (!adapter->params.fw_vers) | |
4688 | dev_warn(adapter->pdev_dev, "No firmware loaded\n"); | |
4689 | else | |
4690 | dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n", | |
4691 | FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers), | |
4692 | FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers), | |
4693 | FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers), | |
4694 | FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers)); | |
4695 | ||
4696 | /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap | |
4697 | * Firmware, so dev_info() is more appropriate here.) | |
4698 | */ | |
4699 | if (!adapter->params.bs_vers) | |
4700 | dev_info(adapter->pdev_dev, "No bootstrap loaded\n"); | |
4701 | else | |
4702 | dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n", | |
4703 | FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers), | |
4704 | FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers), | |
4705 | FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers), | |
4706 | FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers)); | |
4707 | ||
4708 | /* TP Microcode Version */ | |
4709 | if (!adapter->params.tp_vers) | |
4710 | dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n"); | |
4711 | else | |
4712 | dev_info(adapter->pdev_dev, | |
4713 | "TP Microcode version: %u.%u.%u.%u\n", | |
4714 | FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers), | |
4715 | FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers), | |
4716 | FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers), | |
4717 | FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers)); | |
4718 | ||
4719 | /* Expansion ROM version */ | |
4720 | if (!adapter->params.er_vers) | |
4721 | dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n"); | |
4722 | else | |
4723 | dev_info(adapter->pdev_dev, | |
4724 | "Expansion ROM version: %u.%u.%u.%u\n", | |
4725 | FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers), | |
4726 | FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers), | |
4727 | FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers), | |
4728 | FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers)); | |
4729 | ||
4730 | /* Software/Hardware configuration */ | |
4731 | dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", | |
4732 | is_offload(adapter) ? "R" : "", | |
4733 | ((adapter->flags & USING_MSIX) ? "MSI-X" : | |
4734 | (adapter->flags & USING_MSI) ? "MSI" : ""), | |
4735 | is_offload(adapter) ? "Offload" : "non-Offload"); | |
4736 | } | |
4737 | ||
91744948 | 4738 | static void print_port_info(const struct net_device *dev) |
b8ff05a9 | 4739 | { |
b8ff05a9 | 4740 | char buf[80]; |
118969ed | 4741 | char *bufp = buf; |
f1a051b9 | 4742 | const char *spd = ""; |
118969ed DM |
4743 | const struct port_info *pi = netdev_priv(dev); |
4744 | const struct adapter *adap = pi->adapter; | |
f1a051b9 DM |
4745 | |
4746 | if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) | |
4747 | spd = " 2.5 GT/s"; | |
4748 | else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) | |
4749 | spd = " 5 GT/s"; | |
d2e752db RD |
4750 | else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) |
4751 | spd = " 8 GT/s"; | |
b8ff05a9 | 4752 | |
118969ed DM |
4753 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M) |
4754 | bufp += sprintf(bufp, "100/"); | |
4755 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) | |
4756 | bufp += sprintf(bufp, "1000/"); | |
4757 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) | |
4758 | bufp += sprintf(bufp, "10G/"); | |
72aca4bf KS |
4759 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) |
4760 | bufp += sprintf(bufp, "40G/"); | |
118969ed DM |
4761 | if (bufp != buf) |
4762 | --bufp; | |
72aca4bf | 4763 | sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); |
118969ed | 4764 | |
0de72738 HS |
4765 | netdev_info(dev, "%s: Chelsio %s (%s) %s\n", |
4766 | dev->name, adap->params.vpd.id, adap->name, buf); | |
b8ff05a9 DM |
4767 | } |
4768 | ||
91744948 | 4769 | static void enable_pcie_relaxed_ordering(struct pci_dev *dev) |
ef306b50 | 4770 | { |
e5c8ae5f | 4771 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); |
ef306b50 DM |
4772 | } |
4773 | ||
06546391 DM |
4774 | /* |
4775 | * Free the following resources: | |
4776 | * - memory used for tables | |
4777 | * - MSI/MSI-X | |
4778 | * - net devices | |
4779 | * - resources FW is holding for us | |
4780 | */ | |
4781 | static void free_some_resources(struct adapter *adapter) | |
4782 | { | |
4783 | unsigned int i; | |
4784 | ||
4785 | t4_free_mem(adapter->l2t); | |
4786 | t4_free_mem(adapter->tids.tid_tab); | |
4b8e27a8 HS |
4787 | kfree(adapter->sge.egr_map); |
4788 | kfree(adapter->sge.ingr_map); | |
4789 | kfree(adapter->sge.starving_fl); | |
4790 | kfree(adapter->sge.txq_maperr); | |
5b377d11 HS |
4791 | #ifdef CONFIG_DEBUG_FS |
4792 | kfree(adapter->sge.blocked_fl); | |
4793 | #endif | |
06546391 DM |
4794 | disable_msi(adapter); |
4795 | ||
4796 | for_each_port(adapter, i) | |
671b0060 | 4797 | if (adapter->port[i]) { |
4f3a0fcf HS |
4798 | struct port_info *pi = adap2pinfo(adapter, i); |
4799 | ||
4800 | if (pi->viid != 0) | |
4801 | t4_free_vi(adapter, adapter->mbox, adapter->pf, | |
4802 | 0, pi->viid); | |
671b0060 | 4803 | kfree(adap2pinfo(adapter, i)->rss); |
06546391 | 4804 | free_netdev(adapter->port[i]); |
671b0060 | 4805 | } |
06546391 | 4806 | if (adapter->flags & FW_OK) |
b2612722 | 4807 | t4_fw_bye(adapter, adapter->pf); |
06546391 DM |
4808 | } |
4809 | ||
2ed28baa | 4810 | #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) |
35d35682 | 4811 | #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ |
b8ff05a9 | 4812 | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) |
22adfe0a | 4813 | #define SEGMENT_SIZE 128 |
b8ff05a9 | 4814 | |
d86bd29e HS |
4815 | static int get_chip_type(struct pci_dev *pdev, u32 pl_rev) |
4816 | { | |
d86bd29e HS |
4817 | u16 device_id; |
4818 | ||
4819 | /* Retrieve adapter's device ID */ | |
4820 | pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); | |
46cdc9be | 4821 | |
4822 | switch (device_id >> 12) { | |
d86bd29e | 4823 | case CHELSIO_T4: |
46cdc9be | 4824 | return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); |
d86bd29e | 4825 | case CHELSIO_T5: |
46cdc9be | 4826 | return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); |
d86bd29e | 4827 | case CHELSIO_T6: |
46cdc9be | 4828 | return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); |
d86bd29e HS |
4829 | default: |
4830 | dev_err(&pdev->dev, "Device %d is not supported\n", | |
4831 | device_id); | |
d86bd29e | 4832 | } |
46cdc9be | 4833 | return -EINVAL; |
d86bd29e HS |
4834 | } |
4835 | ||
b6244201 HS |
4836 | #ifdef CONFIG_PCI_IOV |
4837 | static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) | |
4838 | { | |
4839 | int err = 0; | |
4840 | int current_vfs = pci_num_vf(pdev); | |
4841 | u32 pcie_fw; | |
4842 | void __iomem *regs; | |
4843 | ||
4844 | regs = pci_ioremap_bar(pdev, 0); | |
4845 | if (!regs) { | |
4846 | dev_err(&pdev->dev, "cannot map device registers\n"); | |
4847 | return -ENOMEM; | |
4848 | } | |
4849 | ||
4850 | pcie_fw = readl(regs + PCIE_FW_A); | |
4851 | iounmap(regs); | |
4852 | /* Check if cxgb4 is the MASTER and fw is initialized */ | |
4853 | if (!(pcie_fw & PCIE_FW_INIT_F) || | |
4854 | !(pcie_fw & PCIE_FW_MASTER_VLD_F) || | |
4855 | PCIE_FW_MASTER_G(pcie_fw) != 4) { | |
4856 | dev_warn(&pdev->dev, | |
4857 | "cxgb4 driver needs to be MASTER to support SRIOV\n"); | |
4858 | return -EOPNOTSUPP; | |
4859 | } | |
4860 | ||
4861 | /* If any of the VF's is already assigned to Guest OS, then | |
4862 | * SRIOV for the same cannot be modified | |
4863 | */ | |
4864 | if (current_vfs && pci_vfs_assigned(pdev)) { | |
4865 | dev_err(&pdev->dev, | |
4866 | "Cannot modify SR-IOV while VFs are assigned\n"); | |
4867 | num_vfs = current_vfs; | |
4868 | return num_vfs; | |
4869 | } | |
4870 | ||
4871 | /* Disable SRIOV when zero is passed. | |
4872 | * One needs to disable SRIOV before modifying it, else | |
4873 | * stack throws the below warning: | |
4874 | * " 'n' VFs already enabled. Disable before enabling 'm' VFs." | |
4875 | */ | |
4876 | if (!num_vfs) { | |
4877 | pci_disable_sriov(pdev); | |
4878 | return num_vfs; | |
4879 | } | |
4880 | ||
4881 | if (num_vfs != current_vfs) { | |
4882 | err = pci_enable_sriov(pdev, num_vfs); | |
4883 | if (err) | |
4884 | return err; | |
4885 | } | |
4886 | return num_vfs; | |
4887 | } | |
4888 | #endif | |
4889 | ||
1dd06ae8 | 4890 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
b8ff05a9 | 4891 | { |
22adfe0a | 4892 | int func, i, err, s_qpp, qpp, num_seg; |
b8ff05a9 | 4893 | struct port_info *pi; |
c8f44aff | 4894 | bool highdma = false; |
b8ff05a9 | 4895 | struct adapter *adapter = NULL; |
d6ce2628 | 4896 | void __iomem *regs; |
d86bd29e HS |
4897 | u32 whoami, pl_rev; |
4898 | enum chip_type chip; | |
b8ff05a9 DM |
4899 | |
4900 | printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); | |
4901 | ||
4902 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
4903 | if (err) { | |
4904 | /* Just info, some other driver may have claimed the device. */ | |
4905 | dev_info(&pdev->dev, "cannot obtain PCI resources\n"); | |
4906 | return err; | |
4907 | } | |
4908 | ||
b8ff05a9 DM |
4909 | err = pci_enable_device(pdev); |
4910 | if (err) { | |
4911 | dev_err(&pdev->dev, "cannot enable PCI device\n"); | |
4912 | goto out_release_regions; | |
4913 | } | |
4914 | ||
d6ce2628 HS |
4915 | regs = pci_ioremap_bar(pdev, 0); |
4916 | if (!regs) { | |
4917 | dev_err(&pdev->dev, "cannot map device registers\n"); | |
4918 | err = -ENOMEM; | |
4919 | goto out_disable_device; | |
4920 | } | |
4921 | ||
8203b509 HS |
4922 | err = t4_wait_dev_ready(regs); |
4923 | if (err < 0) | |
4924 | goto out_unmap_bar0; | |
4925 | ||
d6ce2628 | 4926 | /* We control everything through one PF */ |
d86bd29e HS |
4927 | whoami = readl(regs + PL_WHOAMI_A); |
4928 | pl_rev = REV_G(readl(regs + PL_REV_A)); | |
4929 | chip = get_chip_type(pdev, pl_rev); | |
4930 | func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? | |
4931 | SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); | |
d6ce2628 HS |
4932 | if (func != ent->driver_data) { |
4933 | iounmap(regs); | |
4934 | pci_disable_device(pdev); | |
4935 | pci_save_state(pdev); /* to restore SR-IOV later */ | |
4936 | goto sriov; | |
4937 | } | |
4938 | ||
b8ff05a9 | 4939 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
c8f44aff | 4940 | highdma = true; |
b8ff05a9 DM |
4941 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
4942 | if (err) { | |
4943 | dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " | |
4944 | "coherent allocations\n"); | |
d6ce2628 | 4945 | goto out_unmap_bar0; |
b8ff05a9 DM |
4946 | } |
4947 | } else { | |
4948 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
4949 | if (err) { | |
4950 | dev_err(&pdev->dev, "no usable DMA configuration\n"); | |
d6ce2628 | 4951 | goto out_unmap_bar0; |
b8ff05a9 DM |
4952 | } |
4953 | } | |
4954 | ||
4955 | pci_enable_pcie_error_reporting(pdev); | |
ef306b50 | 4956 | enable_pcie_relaxed_ordering(pdev); |
b8ff05a9 DM |
4957 | pci_set_master(pdev); |
4958 | pci_save_state(pdev); | |
4959 | ||
4960 | adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); | |
4961 | if (!adapter) { | |
4962 | err = -ENOMEM; | |
d6ce2628 | 4963 | goto out_unmap_bar0; |
b8ff05a9 DM |
4964 | } |
4965 | ||
29aaee65 AB |
4966 | adapter->workq = create_singlethread_workqueue("cxgb4"); |
4967 | if (!adapter->workq) { | |
4968 | err = -ENOMEM; | |
4969 | goto out_free_adapter; | |
4970 | } | |
4971 | ||
7f080c3f HS |
4972 | adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + |
4973 | (sizeof(struct mbox_cmd) * | |
4974 | T4_OS_LOG_MBOX_CMDS), | |
4975 | GFP_KERNEL); | |
4976 | if (!adapter->mbox_log) { | |
4977 | err = -ENOMEM; | |
4978 | goto out_free_adapter; | |
4979 | } | |
4980 | adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; | |
4981 | ||
144be3d9 GS |
4982 | /* PCI device has been enabled */ |
4983 | adapter->flags |= DEV_ENABLED; | |
4984 | ||
d6ce2628 | 4985 | adapter->regs = regs; |
b8ff05a9 DM |
4986 | adapter->pdev = pdev; |
4987 | adapter->pdev_dev = &pdev->dev; | |
0de72738 | 4988 | adapter->name = pci_name(pdev); |
3069ee9b | 4989 | adapter->mbox = func; |
b2612722 | 4990 | adapter->pf = func; |
b8ff05a9 DM |
4991 | adapter->msg_enable = dflt_msg_enable; |
4992 | memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); | |
4993 | ||
4994 | spin_lock_init(&adapter->stats_lock); | |
4995 | spin_lock_init(&adapter->tid_release_lock); | |
e327c225 | 4996 | spin_lock_init(&adapter->win0_lock); |
b8ff05a9 DM |
4997 | |
4998 | INIT_WORK(&adapter->tid_release_task, process_tid_release_list); | |
881806bc VP |
4999 | INIT_WORK(&adapter->db_full_task, process_db_full); |
5000 | INIT_WORK(&adapter->db_drop_task, process_db_drop); | |
b8ff05a9 DM |
5001 | |
5002 | err = t4_prep_adapter(adapter); | |
5003 | if (err) | |
d6ce2628 HS |
5004 | goto out_free_adapter; |
5005 | ||
22adfe0a | 5006 | |
d14807dd | 5007 | if (!is_t4(adapter->params.chip)) { |
f612b815 HS |
5008 | s_qpp = (QUEUESPERPAGEPF0_S + |
5009 | (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * | |
b2612722 | 5010 | adapter->pf); |
f612b815 HS |
5011 | qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, |
5012 | SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); | |
22adfe0a SR |
5013 | num_seg = PAGE_SIZE / SEGMENT_SIZE; |
5014 | ||
5015 | /* Each segment size is 128B. Write coalescing is enabled only | |
5016 | * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the | |
5017 | * queue is less no of segments that can be accommodated in | |
5018 | * a page size. | |
5019 | */ | |
5020 | if (qpp > num_seg) { | |
5021 | dev_err(&pdev->dev, | |
5022 | "Incorrect number of egress queues per page\n"); | |
5023 | err = -EINVAL; | |
d6ce2628 | 5024 | goto out_free_adapter; |
22adfe0a SR |
5025 | } |
5026 | adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), | |
5027 | pci_resource_len(pdev, 2)); | |
5028 | if (!adapter->bar2) { | |
5029 | dev_err(&pdev->dev, "cannot map device bar2 region\n"); | |
5030 | err = -ENOMEM; | |
d6ce2628 | 5031 | goto out_free_adapter; |
22adfe0a SR |
5032 | } |
5033 | } | |
5034 | ||
636f9d37 | 5035 | setup_memwin(adapter); |
b8ff05a9 | 5036 | err = adap_init0(adapter); |
5b377d11 HS |
5037 | #ifdef CONFIG_DEBUG_FS |
5038 | bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); | |
5039 | #endif | |
636f9d37 | 5040 | setup_memwin_rdma(adapter); |
b8ff05a9 DM |
5041 | if (err) |
5042 | goto out_unmap_bar; | |
5043 | ||
2a485cf7 HS |
5044 | /* configure SGE_STAT_CFG_A to read WC stats */ |
5045 | if (!is_t4(adapter->params.chip)) | |
676d6a75 HS |
5046 | t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | |
5047 | (is_t5(adapter->params.chip) ? STATMODE_V(0) : | |
5048 | T6_STATMODE_V(0))); | |
2a485cf7 | 5049 | |
b8ff05a9 DM |
5050 | for_each_port(adapter, i) { |
5051 | struct net_device *netdev; | |
5052 | ||
5053 | netdev = alloc_etherdev_mq(sizeof(struct port_info), | |
5054 | MAX_ETH_QSETS); | |
5055 | if (!netdev) { | |
5056 | err = -ENOMEM; | |
5057 | goto out_free_dev; | |
5058 | } | |
5059 | ||
5060 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
5061 | ||
5062 | adapter->port[i] = netdev; | |
5063 | pi = netdev_priv(netdev); | |
5064 | pi->adapter = adapter; | |
5065 | pi->xact_addr_filt = -1; | |
b8ff05a9 | 5066 | pi->port_id = i; |
b8ff05a9 DM |
5067 | netdev->irq = pdev->irq; |
5068 | ||
2ed28baa MM |
5069 | netdev->hw_features = NETIF_F_SG | TSO_FLAGS | |
5070 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
5071 | NETIF_F_RXCSUM | NETIF_F_RXHASH | | |
f646968f | 5072 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
c8f44aff MM |
5073 | if (highdma) |
5074 | netdev->hw_features |= NETIF_F_HIGHDMA; | |
5075 | netdev->features |= netdev->hw_features; | |
b8ff05a9 DM |
5076 | netdev->vlan_features = netdev->features & VLAN_FEAT; |
5077 | ||
01789349 JP |
5078 | netdev->priv_flags |= IFF_UNICAST_FLT; |
5079 | ||
b8ff05a9 | 5080 | netdev->netdev_ops = &cxgb4_netdev_ops; |
688848b1 AB |
5081 | #ifdef CONFIG_CHELSIO_T4_DCB |
5082 | netdev->dcbnl_ops = &cxgb4_dcb_ops; | |
5083 | cxgb4_dcb_state_init(netdev); | |
5084 | #endif | |
812034f1 | 5085 | cxgb4_set_ethtool_ops(netdev); |
b8ff05a9 DM |
5086 | } |
5087 | ||
5088 | pci_set_drvdata(pdev, adapter); | |
5089 | ||
5090 | if (adapter->flags & FW_OK) { | |
060e0c75 | 5091 | err = t4_port_init(adapter, func, func, 0); |
b8ff05a9 DM |
5092 | if (err) |
5093 | goto out_free_dev; | |
098ef6c2 HS |
5094 | } else if (adapter->params.nports == 1) { |
5095 | /* If we don't have a connection to the firmware -- possibly | |
5096 | * because of an error -- grab the raw VPD parameters so we | |
5097 | * can set the proper MAC Address on the debug network | |
5098 | * interface that we've created. | |
5099 | */ | |
5100 | u8 hw_addr[ETH_ALEN]; | |
5101 | u8 *na = adapter->params.vpd.na; | |
5102 | ||
5103 | err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); | |
5104 | if (!err) { | |
5105 | for (i = 0; i < ETH_ALEN; i++) | |
5106 | hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + | |
5107 | hex2val(na[2 * i + 1])); | |
5108 | t4_set_hw_addr(adapter, 0, hw_addr); | |
5109 | } | |
b8ff05a9 DM |
5110 | } |
5111 | ||
098ef6c2 | 5112 | /* Configure queues and allocate tables now, they can be needed as |
b8ff05a9 DM |
5113 | * soon as the first register_netdev completes. |
5114 | */ | |
5115 | cfg_queues(adapter); | |
5116 | ||
5be9ed8d | 5117 | adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); |
b8ff05a9 DM |
5118 | if (!adapter->l2t) { |
5119 | /* We tolerate a lack of L2T, giving up some functionality */ | |
5120 | dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); | |
5121 | adapter->params.offload = 0; | |
5122 | } | |
5123 | ||
b5a02f50 | 5124 | #if IS_ENABLED(CONFIG_IPV6) |
eb72f74f HS |
5125 | if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) && |
5126 | (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { | |
5127 | /* CLIP functionality is not present in hardware, | |
5128 | * hence disable all offload features | |
b5a02f50 AB |
5129 | */ |
5130 | dev_warn(&pdev->dev, | |
eb72f74f | 5131 | "CLIP not enabled in hardware, continuing\n"); |
b5a02f50 | 5132 | adapter->params.offload = 0; |
eb72f74f HS |
5133 | } else { |
5134 | adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, | |
5135 | adapter->clipt_end); | |
5136 | if (!adapter->clipt) { | |
5137 | /* We tolerate a lack of clip_table, giving up | |
5138 | * some functionality | |
5139 | */ | |
5140 | dev_warn(&pdev->dev, | |
5141 | "could not allocate Clip table, continuing\n"); | |
5142 | adapter->params.offload = 0; | |
5143 | } | |
b5a02f50 AB |
5144 | } |
5145 | #endif | |
b8ff05a9 DM |
5146 | if (is_offload(adapter) && tid_init(&adapter->tids) < 0) { |
5147 | dev_warn(&pdev->dev, "could not allocate TID table, " | |
5148 | "continuing\n"); | |
5149 | adapter->params.offload = 0; | |
5150 | } | |
5151 | ||
9a1bb9f6 HS |
5152 | if (is_offload(adapter)) { |
5153 | if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { | |
5154 | u32 hash_base, hash_reg; | |
5155 | ||
5156 | if (chip <= CHELSIO_T5) { | |
5157 | hash_reg = LE_DB_TID_HASHBASE_A; | |
5158 | hash_base = t4_read_reg(adapter, hash_reg); | |
5159 | adapter->tids.hash_base = hash_base / 4; | |
5160 | } else { | |
5161 | hash_reg = T6_LE_DB_HASH_TID_BASE_A; | |
5162 | hash_base = t4_read_reg(adapter, hash_reg); | |
5163 | adapter->tids.hash_base = hash_base; | |
5164 | } | |
5165 | } | |
5166 | } | |
5167 | ||
f7cabcdd DM |
5168 | /* See what interrupts we'll be using */ |
5169 | if (msi > 1 && enable_msix(adapter) == 0) | |
5170 | adapter->flags |= USING_MSIX; | |
5171 | else if (msi > 0 && pci_enable_msi(pdev) == 0) | |
5172 | adapter->flags |= USING_MSI; | |
5173 | ||
547fd272 HS |
5174 | /* check for PCI Express bandwidth capabiltites */ |
5175 | cxgb4_check_pcie_caps(adapter); | |
5176 | ||
671b0060 DM |
5177 | err = init_rss(adapter); |
5178 | if (err) | |
5179 | goto out_free_dev; | |
5180 | ||
b8ff05a9 DM |
5181 | /* |
5182 | * The card is now ready to go. If any errors occur during device | |
5183 | * registration we do not fail the whole card but rather proceed only | |
5184 | * with the ports we manage to register successfully. However we must | |
5185 | * register at least one net device. | |
5186 | */ | |
5187 | for_each_port(adapter, i) { | |
a57cabe0 DM |
5188 | pi = adap2pinfo(adapter, i); |
5189 | netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); | |
5190 | netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); | |
5191 | ||
b8ff05a9 DM |
5192 | err = register_netdev(adapter->port[i]); |
5193 | if (err) | |
b1a3c2b6 | 5194 | break; |
b1a3c2b6 DM |
5195 | adapter->chan_map[pi->tx_chan] = i; |
5196 | print_port_info(adapter->port[i]); | |
b8ff05a9 | 5197 | } |
b1a3c2b6 | 5198 | if (i == 0) { |
b8ff05a9 DM |
5199 | dev_err(&pdev->dev, "could not register any net devices\n"); |
5200 | goto out_free_dev; | |
5201 | } | |
b1a3c2b6 DM |
5202 | if (err) { |
5203 | dev_warn(&pdev->dev, "only %d net devices registered\n", i); | |
5204 | err = 0; | |
6403eab1 | 5205 | } |
b8ff05a9 DM |
5206 | |
5207 | if (cxgb4_debugfs_root) { | |
5208 | adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), | |
5209 | cxgb4_debugfs_root); | |
5210 | setup_debugfs(adapter); | |
5211 | } | |
5212 | ||
6482aa7c DLR |
5213 | /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ |
5214 | pdev->needs_freset = 1; | |
5215 | ||
b8ff05a9 DM |
5216 | if (is_offload(adapter)) |
5217 | attach_ulds(adapter); | |
5218 | ||
0de72738 HS |
5219 | print_adapter_info(adapter); |
5220 | ||
8e1e6059 | 5221 | sriov: |
b8ff05a9 | 5222 | #ifdef CONFIG_PCI_IOV |
b6244201 HS |
5223 | if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0) { |
5224 | dev_warn(&pdev->dev, | |
5225 | "Enabling SR-IOV VFs using the num_vf module " | |
5226 | "parameter is deprecated - please use the pci sysfs " | |
5227 | "interface instead.\n"); | |
b8ff05a9 DM |
5228 | if (pci_enable_sriov(pdev, num_vf[func]) == 0) |
5229 | dev_info(&pdev->dev, | |
5230 | "instantiated %u virtual functions\n", | |
5231 | num_vf[func]); | |
b6244201 | 5232 | } |
b8ff05a9 DM |
5233 | #endif |
5234 | return 0; | |
5235 | ||
5236 | out_free_dev: | |
06546391 | 5237 | free_some_resources(adapter); |
b8ff05a9 | 5238 | out_unmap_bar: |
d14807dd | 5239 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5240 | iounmap(adapter->bar2); |
b8ff05a9 | 5241 | out_free_adapter: |
29aaee65 AB |
5242 | if (adapter->workq) |
5243 | destroy_workqueue(adapter->workq); | |
5244 | ||
7f080c3f | 5245 | kfree(adapter->mbox_log); |
b8ff05a9 | 5246 | kfree(adapter); |
d6ce2628 HS |
5247 | out_unmap_bar0: |
5248 | iounmap(regs); | |
b8ff05a9 DM |
5249 | out_disable_device: |
5250 | pci_disable_pcie_error_reporting(pdev); | |
5251 | pci_disable_device(pdev); | |
5252 | out_release_regions: | |
5253 | pci_release_regions(pdev); | |
b8ff05a9 DM |
5254 | return err; |
5255 | } | |
5256 | ||
91744948 | 5257 | static void remove_one(struct pci_dev *pdev) |
b8ff05a9 DM |
5258 | { |
5259 | struct adapter *adapter = pci_get_drvdata(pdev); | |
5260 | ||
636f9d37 | 5261 | #ifdef CONFIG_PCI_IOV |
b8ff05a9 DM |
5262 | pci_disable_sriov(pdev); |
5263 | ||
636f9d37 VP |
5264 | #endif |
5265 | ||
b8ff05a9 DM |
5266 | if (adapter) { |
5267 | int i; | |
5268 | ||
29aaee65 AB |
5269 | /* Tear down per-adapter Work Queue first since it can contain |
5270 | * references to our adapter data structure. | |
5271 | */ | |
5272 | destroy_workqueue(adapter->workq); | |
5273 | ||
b8ff05a9 DM |
5274 | if (is_offload(adapter)) |
5275 | detach_ulds(adapter); | |
5276 | ||
b37987e8 HS |
5277 | disable_interrupts(adapter); |
5278 | ||
b8ff05a9 | 5279 | for_each_port(adapter, i) |
8f3a7676 | 5280 | if (adapter->port[i]->reg_state == NETREG_REGISTERED) |
b8ff05a9 DM |
5281 | unregister_netdev(adapter->port[i]); |
5282 | ||
9f16dc2e | 5283 | debugfs_remove_recursive(adapter->debugfs_root); |
b8ff05a9 | 5284 | |
f2b7e78d VP |
5285 | /* If we allocated filters, free up state associated with any |
5286 | * valid filters ... | |
5287 | */ | |
5288 | if (adapter->tids.ftid_tab) { | |
5289 | struct filter_entry *f = &adapter->tids.ftid_tab[0]; | |
dca4faeb VP |
5290 | for (i = 0; i < (adapter->tids.nftids + |
5291 | adapter->tids.nsftids); i++, f++) | |
f2b7e78d VP |
5292 | if (f->valid) |
5293 | clear_filter(adapter, f); | |
5294 | } | |
5295 | ||
aaefae9b DM |
5296 | if (adapter->flags & FULL_INIT_DONE) |
5297 | cxgb_down(adapter); | |
b8ff05a9 | 5298 | |
06546391 | 5299 | free_some_resources(adapter); |
b5a02f50 AB |
5300 | #if IS_ENABLED(CONFIG_IPV6) |
5301 | t4_cleanup_clip_tbl(adapter); | |
5302 | #endif | |
b8ff05a9 | 5303 | iounmap(adapter->regs); |
d14807dd | 5304 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5305 | iounmap(adapter->bar2); |
b8ff05a9 | 5306 | pci_disable_pcie_error_reporting(pdev); |
144be3d9 GS |
5307 | if ((adapter->flags & DEV_ENABLED)) { |
5308 | pci_disable_device(pdev); | |
5309 | adapter->flags &= ~DEV_ENABLED; | |
5310 | } | |
b8ff05a9 | 5311 | pci_release_regions(pdev); |
7f080c3f | 5312 | kfree(adapter->mbox_log); |
ee9a33b2 | 5313 | synchronize_rcu(); |
8b662fe7 | 5314 | kfree(adapter); |
a069ec91 | 5315 | } else |
b8ff05a9 DM |
5316 | pci_release_regions(pdev); |
5317 | } | |
5318 | ||
5319 | static struct pci_driver cxgb4_driver = { | |
5320 | .name = KBUILD_MODNAME, | |
5321 | .id_table = cxgb4_pci_tbl, | |
5322 | .probe = init_one, | |
91744948 | 5323 | .remove = remove_one, |
687d705c | 5324 | .shutdown = remove_one, |
b6244201 HS |
5325 | #ifdef CONFIG_PCI_IOV |
5326 | .sriov_configure = cxgb4_iov_configure, | |
5327 | #endif | |
204dc3c0 | 5328 | .err_handler = &cxgb4_eeh, |
b8ff05a9 DM |
5329 | }; |
5330 | ||
5331 | static int __init cxgb4_init_module(void) | |
5332 | { | |
5333 | int ret; | |
5334 | ||
5335 | /* Debugfs support is optional, just warn if this fails */ | |
5336 | cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); | |
5337 | if (!cxgb4_debugfs_root) | |
428ac43f | 5338 | pr_warn("could not create debugfs entry, continuing\n"); |
b8ff05a9 DM |
5339 | |
5340 | ret = pci_register_driver(&cxgb4_driver); | |
29aaee65 | 5341 | if (ret < 0) |
b8ff05a9 | 5342 | debugfs_remove(cxgb4_debugfs_root); |
01bcca68 | 5343 | |
1bb60376 | 5344 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
5345 | if (!inet6addr_registered) { |
5346 | register_inet6addr_notifier(&cxgb4_inet6addr_notifier); | |
5347 | inet6addr_registered = true; | |
5348 | } | |
1bb60376 | 5349 | #endif |
01bcca68 | 5350 | |
b8ff05a9 DM |
5351 | return ret; |
5352 | } | |
5353 | ||
5354 | static void __exit cxgb4_cleanup_module(void) | |
5355 | { | |
1bb60376 | 5356 | #if IS_ENABLED(CONFIG_IPV6) |
1793c798 | 5357 | if (inet6addr_registered) { |
b5a02f50 AB |
5358 | unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); |
5359 | inet6addr_registered = false; | |
5360 | } | |
1bb60376 | 5361 | #endif |
b8ff05a9 DM |
5362 | pci_unregister_driver(&cxgb4_driver); |
5363 | debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ | |
5364 | } | |
5365 | ||
5366 | module_init(cxgb4_init_module); | |
5367 | module_exit(cxgb4_cleanup_module); |