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b8ff05a9 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
b72a32da | 4 | * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. |
b8ff05a9 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
36 | ||
37 | #include <linux/bitmap.h> | |
38 | #include <linux/crc32.h> | |
39 | #include <linux/ctype.h> | |
40 | #include <linux/debugfs.h> | |
41 | #include <linux/err.h> | |
42 | #include <linux/etherdevice.h> | |
43 | #include <linux/firmware.h> | |
01789349 | 44 | #include <linux/if.h> |
b8ff05a9 DM |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/init.h> | |
47 | #include <linux/log2.h> | |
48 | #include <linux/mdio.h> | |
49 | #include <linux/module.h> | |
50 | #include <linux/moduleparam.h> | |
51 | #include <linux/mutex.h> | |
52 | #include <linux/netdevice.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/aer.h> | |
55 | #include <linux/rtnetlink.h> | |
56 | #include <linux/sched.h> | |
57 | #include <linux/seq_file.h> | |
58 | #include <linux/sockios.h> | |
59 | #include <linux/vmalloc.h> | |
60 | #include <linux/workqueue.h> | |
61 | #include <net/neighbour.h> | |
62 | #include <net/netevent.h> | |
01bcca68 | 63 | #include <net/addrconf.h> |
1ef8019b | 64 | #include <net/bonding.h> |
b5a02f50 | 65 | #include <net/addrconf.h> |
7c0f6ba6 | 66 | #include <linux/uaccess.h> |
c5a8c0f3 | 67 | #include <linux/crash_dump.h> |
b8ff05a9 DM |
68 | |
69 | #include "cxgb4.h" | |
d57fd6ca | 70 | #include "cxgb4_filter.h" |
b8ff05a9 | 71 | #include "t4_regs.h" |
f612b815 | 72 | #include "t4_values.h" |
b8ff05a9 DM |
73 | #include "t4_msg.h" |
74 | #include "t4fw_api.h" | |
cd6c2f12 | 75 | #include "t4fw_version.h" |
688848b1 | 76 | #include "cxgb4_dcb.h" |
fd88b31a | 77 | #include "cxgb4_debugfs.h" |
b5a02f50 | 78 | #include "clip_tbl.h" |
b8ff05a9 | 79 | #include "l2t.h" |
b72a32da | 80 | #include "sched.h" |
d8931847 | 81 | #include "cxgb4_tc_u32.h" |
b8ff05a9 | 82 | |
812034f1 HS |
83 | char cxgb4_driver_name[] = KBUILD_MODNAME; |
84 | ||
01bcca68 VP |
85 | #ifdef DRV_VERSION |
86 | #undef DRV_VERSION | |
87 | #endif | |
3a7f8554 | 88 | #define DRV_VERSION "2.0.0-ko" |
812034f1 | 89 | const char cxgb4_driver_version[] = DRV_VERSION; |
52a5f846 | 90 | #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" |
b8ff05a9 | 91 | |
b8ff05a9 DM |
92 | #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ |
93 | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ | |
94 | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) | |
95 | ||
3fedeab1 HS |
96 | /* Macros needed to support the PCI Device ID Table ... |
97 | */ | |
98 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ | |
768ffc66 | 99 | static const struct pci_device_id cxgb4_pci_tbl[] = { |
3fedeab1 | 100 | #define CH_PCI_DEVICE_ID_FUNCTION 0x4 |
b8ff05a9 | 101 | |
3fedeab1 HS |
102 | /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is |
103 | * called for both. | |
104 | */ | |
105 | #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 | |
106 | ||
107 | #define CH_PCI_ID_TABLE_ENTRY(devid) \ | |
108 | {PCI_VDEVICE(CHELSIO, (devid)), 4} | |
109 | ||
110 | #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ | |
111 | { 0, } \ | |
112 | } | |
113 | ||
114 | #include "t4_pci_id_tbl.h" | |
b8ff05a9 | 115 | |
16e47624 | 116 | #define FW4_FNAME "cxgb4/t4fw.bin" |
0a57a536 | 117 | #define FW5_FNAME "cxgb4/t5fw.bin" |
3ccc6cf7 | 118 | #define FW6_FNAME "cxgb4/t6fw.bin" |
16e47624 | 119 | #define FW4_CFNAME "cxgb4/t4-config.txt" |
0a57a536 | 120 | #define FW5_CFNAME "cxgb4/t5-config.txt" |
3ccc6cf7 | 121 | #define FW6_CFNAME "cxgb4/t6-config.txt" |
01b69614 HS |
122 | #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" |
123 | #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" | |
124 | #define PHY_AQ1202_DEVICEID 0x4409 | |
125 | #define PHY_BCM84834_DEVICEID 0x4486 | |
b8ff05a9 DM |
126 | |
127 | MODULE_DESCRIPTION(DRV_DESC); | |
128 | MODULE_AUTHOR("Chelsio Communications"); | |
129 | MODULE_LICENSE("Dual BSD/GPL"); | |
130 | MODULE_VERSION(DRV_VERSION); | |
131 | MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); | |
16e47624 | 132 | MODULE_FIRMWARE(FW4_FNAME); |
0a57a536 | 133 | MODULE_FIRMWARE(FW5_FNAME); |
52a5f846 | 134 | MODULE_FIRMWARE(FW6_FNAME); |
b8ff05a9 | 135 | |
b8ff05a9 DM |
136 | /* |
137 | * The driver uses the best interrupt scheme available on a platform in the | |
138 | * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which | |
139 | * of these schemes the driver may consider as follows: | |
140 | * | |
141 | * msi = 2: choose from among all three options | |
142 | * msi = 1: only consider MSI and INTx interrupts | |
143 | * msi = 0: force INTx interrupts | |
144 | */ | |
145 | static int msi = 2; | |
146 | ||
147 | module_param(msi, int, 0644); | |
148 | MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); | |
149 | ||
636f9d37 VP |
150 | /* |
151 | * Normally we tell the chip to deliver Ingress Packets into our DMA buffers | |
152 | * offset by 2 bytes in order to have the IP headers line up on 4-byte | |
153 | * boundaries. This is a requirement for many architectures which will throw | |
154 | * a machine check fault if an attempt is made to access one of the 4-byte IP | |
155 | * header fields on a non-4-byte boundary. And it's a major performance issue | |
156 | * even on some architectures which allow it like some implementations of the | |
157 | * x86 ISA. However, some architectures don't mind this and for some very | |
158 | * edge-case performance sensitive applications (like forwarding large volumes | |
159 | * of small packets), setting this DMA offset to 0 will decrease the number of | |
160 | * PCI-E Bus transfers enough to measurably affect performance. | |
161 | */ | |
162 | static int rx_dma_offset = 2; | |
163 | ||
688848b1 AB |
164 | /* TX Queue select used to determine what algorithm to use for selecting TX |
165 | * queue. Select between the kernel provided function (select_queue=0) or user | |
166 | * cxgb_select_queue function (select_queue=1) | |
167 | * | |
168 | * Default: select_queue=0 | |
169 | */ | |
170 | static int select_queue; | |
171 | module_param(select_queue, int, 0644); | |
172 | MODULE_PARM_DESC(select_queue, | |
173 | "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); | |
174 | ||
b8ff05a9 DM |
175 | static struct dentry *cxgb4_debugfs_root; |
176 | ||
94cdb8bb HS |
177 | LIST_HEAD(adapter_list); |
178 | DEFINE_MUTEX(uld_mutex); | |
b8ff05a9 DM |
179 | |
180 | static void link_report(struct net_device *dev) | |
181 | { | |
182 | if (!netif_carrier_ok(dev)) | |
183 | netdev_info(dev, "link down\n"); | |
184 | else { | |
185 | static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; | |
186 | ||
85412255 | 187 | const char *s; |
b8ff05a9 DM |
188 | const struct port_info *p = netdev_priv(dev); |
189 | ||
190 | switch (p->link_cfg.speed) { | |
5e78f7fd GG |
191 | case 100: |
192 | s = "100Mbps"; | |
b8ff05a9 | 193 | break; |
e8b39015 | 194 | case 1000: |
5e78f7fd | 195 | s = "1Gbps"; |
b8ff05a9 | 196 | break; |
5e78f7fd GG |
197 | case 10000: |
198 | s = "10Gbps"; | |
199 | break; | |
200 | case 25000: | |
201 | s = "25Gbps"; | |
b8ff05a9 | 202 | break; |
e8b39015 | 203 | case 40000: |
72aca4bf KS |
204 | s = "40Gbps"; |
205 | break; | |
5e78f7fd GG |
206 | case 100000: |
207 | s = "100Gbps"; | |
208 | break; | |
85412255 HS |
209 | default: |
210 | pr_info("%s: unsupported speed: %d\n", | |
211 | dev->name, p->link_cfg.speed); | |
212 | return; | |
b8ff05a9 DM |
213 | } |
214 | ||
215 | netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, | |
216 | fc[p->link_cfg.fc]); | |
217 | } | |
218 | } | |
219 | ||
688848b1 AB |
220 | #ifdef CONFIG_CHELSIO_T4_DCB |
221 | /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ | |
222 | static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) | |
223 | { | |
224 | struct port_info *pi = netdev_priv(dev); | |
225 | struct adapter *adap = pi->adapter; | |
226 | struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; | |
227 | int i; | |
228 | ||
229 | /* We use a simple mapping of Port TX Queue Index to DCB | |
230 | * Priority when we're enabling DCB. | |
231 | */ | |
232 | for (i = 0; i < pi->nqsets; i++, txq++) { | |
233 | u32 name, value; | |
234 | int err; | |
235 | ||
5167865a HS |
236 | name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
237 | FW_PARAMS_PARAM_X_V( | |
238 | FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | | |
239 | FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); | |
688848b1 AB |
240 | value = enable ? i : 0xffffffff; |
241 | ||
242 | /* Since we can be called while atomic (from "interrupt | |
243 | * level") we need to issue the Set Parameters Commannd | |
244 | * without sleeping (timeout < 0). | |
245 | */ | |
b2612722 | 246 | err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, |
01b69614 HS |
247 | &name, &value, |
248 | -FW_CMD_MAX_TIMEOUT); | |
688848b1 AB |
249 | |
250 | if (err) | |
251 | dev_err(adap->pdev_dev, | |
252 | "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", | |
253 | enable ? "set" : "unset", pi->port_id, i, -err); | |
10b00466 AB |
254 | else |
255 | txq->dcb_prio = value; | |
688848b1 AB |
256 | } |
257 | } | |
688848b1 | 258 | |
50935857 | 259 | static int cxgb4_dcb_enabled(const struct net_device *dev) |
218d48e7 | 260 | { |
218d48e7 HS |
261 | struct port_info *pi = netdev_priv(dev); |
262 | ||
263 | if (!pi->dcb.enabled) | |
264 | return 0; | |
265 | ||
266 | return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || | |
267 | (pi->dcb.state == CXGB4_DCB_STATE_HOST)); | |
218d48e7 | 268 | } |
7c70c4f8 | 269 | #endif /* CONFIG_CHELSIO_T4_DCB */ |
218d48e7 | 270 | |
b8ff05a9 DM |
271 | void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) |
272 | { | |
273 | struct net_device *dev = adapter->port[port_id]; | |
274 | ||
275 | /* Skip changes from disabled ports. */ | |
276 | if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { | |
277 | if (link_stat) | |
278 | netif_carrier_on(dev); | |
688848b1 AB |
279 | else { |
280 | #ifdef CONFIG_CHELSIO_T4_DCB | |
218d48e7 HS |
281 | if (cxgb4_dcb_enabled(dev)) { |
282 | cxgb4_dcb_state_init(dev); | |
283 | dcb_tx_queue_prio_enable(dev, false); | |
284 | } | |
688848b1 | 285 | #endif /* CONFIG_CHELSIO_T4_DCB */ |
b8ff05a9 | 286 | netif_carrier_off(dev); |
688848b1 | 287 | } |
b8ff05a9 DM |
288 | |
289 | link_report(dev); | |
290 | } | |
291 | } | |
292 | ||
293 | void t4_os_portmod_changed(const struct adapter *adap, int port_id) | |
294 | { | |
295 | static const char *mod_str[] = { | |
a0881cab | 296 | NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" |
b8ff05a9 DM |
297 | }; |
298 | ||
299 | const struct net_device *dev = adap->port[port_id]; | |
300 | const struct port_info *pi = netdev_priv(dev); | |
301 | ||
302 | if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) | |
303 | netdev_info(dev, "port module unplugged\n"); | |
a0881cab | 304 | else if (pi->mod_type < ARRAY_SIZE(mod_str)) |
b8ff05a9 | 305 | netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); |
be81a2de HS |
306 | else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) |
307 | netdev_info(dev, "%s: unsupported port module inserted\n", | |
308 | dev->name); | |
309 | else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) | |
310 | netdev_info(dev, "%s: unknown port module inserted\n", | |
311 | dev->name); | |
312 | else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) | |
313 | netdev_info(dev, "%s: transceiver module error\n", dev->name); | |
314 | else | |
315 | netdev_info(dev, "%s: unknown module type %d inserted\n", | |
316 | dev->name, pi->mod_type); | |
b8ff05a9 DM |
317 | } |
318 | ||
fc08a01a HS |
319 | int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ |
320 | module_param(dbfifo_int_thresh, int, 0644); | |
321 | MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); | |
322 | ||
b8ff05a9 | 323 | /* |
fc08a01a | 324 | * usecs to sleep while draining the dbfifo |
b8ff05a9 | 325 | */ |
fc08a01a HS |
326 | static int dbfifo_drain_delay = 1000; |
327 | module_param(dbfifo_drain_delay, int, 0644); | |
328 | MODULE_PARM_DESC(dbfifo_drain_delay, | |
329 | "usecs to sleep while draining the dbfifo"); | |
330 | ||
331 | static inline int cxgb4_set_addr_hash(struct port_info *pi) | |
b8ff05a9 | 332 | { |
fc08a01a HS |
333 | struct adapter *adap = pi->adapter; |
334 | u64 vec = 0; | |
335 | bool ucast = false; | |
336 | struct hash_mac_addr *entry; | |
337 | ||
338 | /* Calculate the hash vector for the updated list and program it */ | |
339 | list_for_each_entry(entry, &adap->mac_hlist, list) { | |
340 | ucast |= is_unicast_ether_addr(entry->addr); | |
341 | vec |= (1ULL << hash_mac_addr(entry->addr)); | |
342 | } | |
343 | return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, | |
344 | vec, false); | |
345 | } | |
346 | ||
347 | static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) | |
348 | { | |
349 | struct port_info *pi = netdev_priv(netdev); | |
350 | struct adapter *adap = pi->adapter; | |
351 | int ret; | |
b8ff05a9 DM |
352 | u64 mhash = 0; |
353 | u64 uhash = 0; | |
fc08a01a HS |
354 | bool free = false; |
355 | bool ucast = is_unicast_ether_addr(mac_addr); | |
356 | const u8 *maclist[1] = {mac_addr}; | |
357 | struct hash_mac_addr *new_entry; | |
358 | ||
359 | ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist, | |
360 | NULL, ucast ? &uhash : &mhash, false); | |
361 | if (ret < 0) | |
362 | goto out; | |
363 | /* if hash != 0, then add the addr to hash addr list | |
364 | * so on the end we will calculate the hash for the | |
365 | * list and program it | |
366 | */ | |
367 | if (uhash || mhash) { | |
368 | new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); | |
369 | if (!new_entry) | |
370 | return -ENOMEM; | |
371 | ether_addr_copy(new_entry->addr, mac_addr); | |
372 | list_add_tail(&new_entry->list, &adap->mac_hlist); | |
373 | ret = cxgb4_set_addr_hash(pi); | |
b8ff05a9 | 374 | } |
fc08a01a HS |
375 | out: |
376 | return ret < 0 ? ret : 0; | |
377 | } | |
b8ff05a9 | 378 | |
fc08a01a HS |
379 | static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) |
380 | { | |
381 | struct port_info *pi = netdev_priv(netdev); | |
382 | struct adapter *adap = pi->adapter; | |
383 | int ret; | |
384 | const u8 *maclist[1] = {mac_addr}; | |
385 | struct hash_mac_addr *entry, *tmp; | |
b8ff05a9 | 386 | |
fc08a01a HS |
387 | /* If the MAC address to be removed is in the hash addr |
388 | * list, delete it from the list and update hash vector | |
389 | */ | |
390 | list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { | |
391 | if (ether_addr_equal(entry->addr, mac_addr)) { | |
392 | list_del(&entry->list); | |
393 | kfree(entry); | |
394 | return cxgb4_set_addr_hash(pi); | |
b8ff05a9 DM |
395 | } |
396 | } | |
397 | ||
fc08a01a HS |
398 | ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false); |
399 | return ret < 0 ? -EINVAL : 0; | |
b8ff05a9 DM |
400 | } |
401 | ||
402 | /* | |
403 | * Set Rx properties of a port, such as promiscruity, address filters, and MTU. | |
404 | * If @mtu is -1 it is left unchanged. | |
405 | */ | |
406 | static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) | |
407 | { | |
b8ff05a9 | 408 | struct port_info *pi = netdev_priv(dev); |
fc08a01a | 409 | struct adapter *adapter = pi->adapter; |
b8ff05a9 | 410 | |
d01f7abc HS |
411 | __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); |
412 | __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); | |
fc08a01a HS |
413 | |
414 | return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, | |
415 | (dev->flags & IFF_PROMISC) ? 1 : 0, | |
416 | (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, | |
417 | sleep_ok); | |
b8ff05a9 DM |
418 | } |
419 | ||
420 | /** | |
421 | * link_start - enable a port | |
422 | * @dev: the port to enable | |
423 | * | |
424 | * Performs the MAC and PHY actions needed to enable a port. | |
425 | */ | |
426 | static int link_start(struct net_device *dev) | |
427 | { | |
428 | int ret; | |
429 | struct port_info *pi = netdev_priv(dev); | |
b2612722 | 430 | unsigned int mb = pi->adapter->pf; |
b8ff05a9 DM |
431 | |
432 | /* | |
433 | * We do not set address filters and promiscuity here, the stack does | |
434 | * that step explicitly. | |
435 | */ | |
060e0c75 | 436 | ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, |
f646968f | 437 | !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); |
b8ff05a9 | 438 | if (ret == 0) { |
060e0c75 | 439 | ret = t4_change_mac(pi->adapter, mb, pi->viid, |
b8ff05a9 | 440 | pi->xact_addr_filt, dev->dev_addr, true, |
b6bd29e7 | 441 | true); |
b8ff05a9 DM |
442 | if (ret >= 0) { |
443 | pi->xact_addr_filt = ret; | |
444 | ret = 0; | |
445 | } | |
446 | } | |
447 | if (ret == 0) | |
4036da90 | 448 | ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, |
060e0c75 | 449 | &pi->link_cfg); |
30f00847 AB |
450 | if (ret == 0) { |
451 | local_bh_disable(); | |
688848b1 AB |
452 | ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true, |
453 | true, CXGB4_DCB_ENABLED); | |
30f00847 AB |
454 | local_bh_enable(); |
455 | } | |
688848b1 | 456 | |
b8ff05a9 DM |
457 | return ret; |
458 | } | |
459 | ||
688848b1 AB |
460 | #ifdef CONFIG_CHELSIO_T4_DCB |
461 | /* Handle a Data Center Bridging update message from the firmware. */ | |
462 | static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) | |
463 | { | |
2b5fb1f2 | 464 | int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); |
134491fd | 465 | struct net_device *dev = adap->port[adap->chan_map[port]]; |
688848b1 AB |
466 | int old_dcb_enabled = cxgb4_dcb_enabled(dev); |
467 | int new_dcb_enabled; | |
468 | ||
469 | cxgb4_dcb_handle_fw_update(adap, pcmd); | |
470 | new_dcb_enabled = cxgb4_dcb_enabled(dev); | |
471 | ||
472 | /* If the DCB has become enabled or disabled on the port then we're | |
473 | * going to need to set up/tear down DCB Priority parameters for the | |
474 | * TX Queues associated with the port. | |
475 | */ | |
476 | if (new_dcb_enabled != old_dcb_enabled) | |
477 | dcb_tx_queue_prio_enable(dev, new_dcb_enabled); | |
478 | } | |
479 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
480 | ||
f2b7e78d | 481 | /* Response queue handler for the FW event queue. |
b8ff05a9 DM |
482 | */ |
483 | static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, | |
484 | const struct pkt_gl *gl) | |
485 | { | |
486 | u8 opcode = ((const struct rss_header *)rsp)->opcode; | |
487 | ||
488 | rsp++; /* skip RSS header */ | |
b407a4a9 VP |
489 | |
490 | /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. | |
491 | */ | |
492 | if (unlikely(opcode == CPL_FW4_MSG && | |
493 | ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { | |
494 | rsp++; | |
495 | opcode = ((const struct rss_header *)rsp)->opcode; | |
496 | rsp++; | |
497 | if (opcode != CPL_SGE_EGR_UPDATE) { | |
498 | dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" | |
499 | , opcode); | |
500 | goto out; | |
501 | } | |
502 | } | |
503 | ||
b8ff05a9 DM |
504 | if (likely(opcode == CPL_SGE_EGR_UPDATE)) { |
505 | const struct cpl_sge_egr_update *p = (void *)rsp; | |
bdc590b9 | 506 | unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); |
e46dab4d | 507 | struct sge_txq *txq; |
b8ff05a9 | 508 | |
e46dab4d | 509 | txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; |
b8ff05a9 | 510 | txq->restarts++; |
ab677ff4 | 511 | if (txq->q_type == CXGB4_TXQ_ETH) { |
b8ff05a9 DM |
512 | struct sge_eth_txq *eq; |
513 | ||
514 | eq = container_of(txq, struct sge_eth_txq, q); | |
515 | netif_tx_wake_queue(eq->txq); | |
516 | } else { | |
ab677ff4 | 517 | struct sge_uld_txq *oq; |
b8ff05a9 | 518 | |
ab677ff4 | 519 | oq = container_of(txq, struct sge_uld_txq, q); |
b8ff05a9 DM |
520 | tasklet_schedule(&oq->qresume_tsk); |
521 | } | |
522 | } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { | |
523 | const struct cpl_fw6_msg *p = (void *)rsp; | |
524 | ||
688848b1 AB |
525 | #ifdef CONFIG_CHELSIO_T4_DCB |
526 | const struct fw_port_cmd *pcmd = (const void *)p->data; | |
e2ac9628 | 527 | unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); |
688848b1 | 528 | unsigned int action = |
2b5fb1f2 | 529 | FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); |
688848b1 AB |
530 | |
531 | if (cmd == FW_PORT_CMD && | |
532 | action == FW_PORT_ACTION_GET_PORT_INFO) { | |
2b5fb1f2 | 533 | int port = FW_PORT_CMD_PORTID_G( |
688848b1 | 534 | be32_to_cpu(pcmd->op_to_portid)); |
134491fd HS |
535 | struct net_device *dev = |
536 | q->adap->port[q->adap->chan_map[port]]; | |
688848b1 | 537 | int state_input = ((pcmd->u.info.dcbxdis_pkd & |
2b5fb1f2 | 538 | FW_PORT_CMD_DCBXDIS_F) |
688848b1 AB |
539 | ? CXGB4_DCB_INPUT_FW_DISABLED |
540 | : CXGB4_DCB_INPUT_FW_ENABLED); | |
541 | ||
542 | cxgb4_dcb_state_fsm(dev, state_input); | |
543 | } | |
544 | ||
545 | if (cmd == FW_PORT_CMD && | |
546 | action == FW_PORT_ACTION_L2_DCB_CFG) | |
547 | dcb_rpl(q->adap, pcmd); | |
548 | else | |
549 | #endif | |
550 | if (p->type == 0) | |
551 | t4_handle_fw_rpl(q->adap, p->data); | |
b8ff05a9 DM |
552 | } else if (opcode == CPL_L2T_WRITE_RPL) { |
553 | const struct cpl_l2t_write_rpl *p = (void *)rsp; | |
554 | ||
555 | do_l2t_write_rpl(q->adap, p); | |
f2b7e78d VP |
556 | } else if (opcode == CPL_SET_TCB_RPL) { |
557 | const struct cpl_set_tcb_rpl *p = (void *)rsp; | |
558 | ||
559 | filter_rpl(q->adap, p); | |
b8ff05a9 DM |
560 | } else |
561 | dev_err(q->adap->pdev_dev, | |
562 | "unexpected CPL %#x on FW event queue\n", opcode); | |
b407a4a9 | 563 | out: |
b8ff05a9 DM |
564 | return 0; |
565 | } | |
566 | ||
b8ff05a9 DM |
567 | static void disable_msi(struct adapter *adapter) |
568 | { | |
569 | if (adapter->flags & USING_MSIX) { | |
570 | pci_disable_msix(adapter->pdev); | |
571 | adapter->flags &= ~USING_MSIX; | |
572 | } else if (adapter->flags & USING_MSI) { | |
573 | pci_disable_msi(adapter->pdev); | |
574 | adapter->flags &= ~USING_MSI; | |
575 | } | |
576 | } | |
577 | ||
578 | /* | |
579 | * Interrupt handler for non-data events used with MSI-X. | |
580 | */ | |
581 | static irqreturn_t t4_nondata_intr(int irq, void *cookie) | |
582 | { | |
583 | struct adapter *adap = cookie; | |
0d804338 | 584 | u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); |
b8ff05a9 | 585 | |
0d804338 | 586 | if (v & PFSW_F) { |
b8ff05a9 | 587 | adap->swintr = 1; |
0d804338 | 588 | t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); |
b8ff05a9 | 589 | } |
c3c7b121 HS |
590 | if (adap->flags & MASTER_PF) |
591 | t4_slow_intr_handler(adap); | |
b8ff05a9 DM |
592 | return IRQ_HANDLED; |
593 | } | |
594 | ||
595 | /* | |
596 | * Name the MSI-X interrupts. | |
597 | */ | |
598 | static void name_msix_vecs(struct adapter *adap) | |
599 | { | |
ba27816c | 600 | int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); |
b8ff05a9 DM |
601 | |
602 | /* non-data interrupts */ | |
b1a3c2b6 | 603 | snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); |
b8ff05a9 DM |
604 | |
605 | /* FW events */ | |
b1a3c2b6 DM |
606 | snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", |
607 | adap->port[0]->name); | |
b8ff05a9 DM |
608 | |
609 | /* Ethernet queues */ | |
610 | for_each_port(adap, j) { | |
611 | struct net_device *d = adap->port[j]; | |
612 | const struct port_info *pi = netdev_priv(d); | |
613 | ||
ba27816c | 614 | for (i = 0; i < pi->nqsets; i++, msi_idx++) |
b8ff05a9 DM |
615 | snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", |
616 | d->name, i); | |
b8ff05a9 | 617 | } |
b8ff05a9 DM |
618 | } |
619 | ||
620 | static int request_msix_queue_irqs(struct adapter *adap) | |
621 | { | |
622 | struct sge *s = &adap->sge; | |
0fbc81b3 | 623 | int err, ethqidx; |
cf38be6d | 624 | int msi_index = 2; |
b8ff05a9 DM |
625 | |
626 | err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, | |
627 | adap->msix_info[1].desc, &s->fw_evtq); | |
628 | if (err) | |
629 | return err; | |
630 | ||
631 | for_each_ethrxq(s, ethqidx) { | |
404d9e3f VP |
632 | err = request_irq(adap->msix_info[msi_index].vec, |
633 | t4_sge_intr_msix, 0, | |
634 | adap->msix_info[msi_index].desc, | |
b8ff05a9 DM |
635 | &s->ethrxq[ethqidx].rspq); |
636 | if (err) | |
637 | goto unwind; | |
404d9e3f | 638 | msi_index++; |
b8ff05a9 | 639 | } |
b8ff05a9 DM |
640 | return 0; |
641 | ||
642 | unwind: | |
b8ff05a9 | 643 | while (--ethqidx >= 0) |
404d9e3f VP |
644 | free_irq(adap->msix_info[--msi_index].vec, |
645 | &s->ethrxq[ethqidx].rspq); | |
b8ff05a9 DM |
646 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); |
647 | return err; | |
648 | } | |
649 | ||
650 | static void free_msix_queue_irqs(struct adapter *adap) | |
651 | { | |
404d9e3f | 652 | int i, msi_index = 2; |
b8ff05a9 DM |
653 | struct sge *s = &adap->sge; |
654 | ||
655 | free_irq(adap->msix_info[1].vec, &s->fw_evtq); | |
656 | for_each_ethrxq(s, i) | |
404d9e3f | 657 | free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); |
b8ff05a9 DM |
658 | } |
659 | ||
671b0060 | 660 | /** |
812034f1 | 661 | * cxgb4_write_rss - write the RSS table for a given port |
671b0060 DM |
662 | * @pi: the port |
663 | * @queues: array of queue indices for RSS | |
664 | * | |
665 | * Sets up the portion of the HW RSS table for the port's VI to distribute | |
666 | * packets to the Rx queues in @queues. | |
c035e183 | 667 | * Should never be called before setting up sge eth rx queues |
671b0060 | 668 | */ |
812034f1 | 669 | int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) |
671b0060 DM |
670 | { |
671 | u16 *rss; | |
672 | int i, err; | |
c035e183 HS |
673 | struct adapter *adapter = pi->adapter; |
674 | const struct sge_eth_rxq *rxq; | |
671b0060 | 675 | |
c035e183 | 676 | rxq = &adapter->sge.ethrxq[pi->first_qset]; |
671b0060 DM |
677 | rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL); |
678 | if (!rss) | |
679 | return -ENOMEM; | |
680 | ||
681 | /* map the queue indices to queue ids */ | |
682 | for (i = 0; i < pi->rss_size; i++, queues++) | |
c035e183 | 683 | rss[i] = rxq[*queues].rspq.abs_id; |
671b0060 | 684 | |
b2612722 | 685 | err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, |
060e0c75 | 686 | pi->rss_size, rss, pi->rss_size); |
c035e183 HS |
687 | /* If Tunnel All Lookup isn't specified in the global RSS |
688 | * Configuration, then we need to specify a default Ingress | |
689 | * Queue for any ingress packets which aren't hashed. We'll | |
690 | * use our first ingress queue ... | |
691 | */ | |
692 | if (!err) | |
693 | err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, | |
694 | FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | | |
695 | FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | | |
696 | FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | | |
697 | FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | | |
698 | FW_RSS_VI_CONFIG_CMD_UDPEN_F, | |
699 | rss[0]); | |
671b0060 DM |
700 | kfree(rss); |
701 | return err; | |
702 | } | |
703 | ||
b8ff05a9 DM |
704 | /** |
705 | * setup_rss - configure RSS | |
706 | * @adap: the adapter | |
707 | * | |
671b0060 | 708 | * Sets up RSS for each port. |
b8ff05a9 DM |
709 | */ |
710 | static int setup_rss(struct adapter *adap) | |
711 | { | |
c035e183 | 712 | int i, j, err; |
b8ff05a9 DM |
713 | |
714 | for_each_port(adap, i) { | |
715 | const struct port_info *pi = adap2pinfo(adap, i); | |
b8ff05a9 | 716 | |
c035e183 HS |
717 | /* Fill default values with equal distribution */ |
718 | for (j = 0; j < pi->rss_size; j++) | |
719 | pi->rss[j] = j % pi->nqsets; | |
720 | ||
812034f1 | 721 | err = cxgb4_write_rss(pi, pi->rss); |
b8ff05a9 DM |
722 | if (err) |
723 | return err; | |
724 | } | |
725 | return 0; | |
726 | } | |
727 | ||
e46dab4d DM |
728 | /* |
729 | * Return the channel of the ingress queue with the given qid. | |
730 | */ | |
731 | static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) | |
732 | { | |
733 | qid -= p->ingr_start; | |
734 | return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; | |
735 | } | |
736 | ||
b8ff05a9 DM |
737 | /* |
738 | * Wait until all NAPI handlers are descheduled. | |
739 | */ | |
740 | static void quiesce_rx(struct adapter *adap) | |
741 | { | |
742 | int i; | |
743 | ||
4b8e27a8 | 744 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
745 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
746 | ||
5226b791 | 747 | if (q && q->handler) |
b8ff05a9 DM |
748 | napi_disable(&q->napi); |
749 | } | |
750 | } | |
751 | ||
b37987e8 HS |
752 | /* Disable interrupt and napi handler */ |
753 | static void disable_interrupts(struct adapter *adap) | |
754 | { | |
755 | if (adap->flags & FULL_INIT_DONE) { | |
756 | t4_intr_disable(adap); | |
757 | if (adap->flags & USING_MSIX) { | |
758 | free_msix_queue_irqs(adap); | |
759 | free_irq(adap->msix_info[0].vec, adap); | |
760 | } else { | |
761 | free_irq(adap->pdev->irq, adap); | |
762 | } | |
763 | quiesce_rx(adap); | |
764 | } | |
765 | } | |
766 | ||
b8ff05a9 DM |
767 | /* |
768 | * Enable NAPI scheduling and interrupt generation for all Rx queues. | |
769 | */ | |
770 | static void enable_rx(struct adapter *adap) | |
771 | { | |
772 | int i; | |
773 | ||
4b8e27a8 | 774 | for (i = 0; i < adap->sge.ingr_sz; i++) { |
b8ff05a9 DM |
775 | struct sge_rspq *q = adap->sge.ingr_map[i]; |
776 | ||
777 | if (!q) | |
778 | continue; | |
5226b791 | 779 | if (q->handler) |
b8ff05a9 | 780 | napi_enable(&q->napi); |
5226b791 | 781 | |
b8ff05a9 | 782 | /* 0-increment GTS to start the timer and enable interrupts */ |
f612b815 HS |
783 | t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), |
784 | SEINTARM_V(q->intr_params) | | |
785 | INGRESSQID_V(q->cntxt_id)); | |
b8ff05a9 DM |
786 | } |
787 | } | |
788 | ||
1c6a5b0e | 789 | |
0fbc81b3 | 790 | static int setup_fw_sge_queues(struct adapter *adap) |
b8ff05a9 | 791 | { |
b8ff05a9 | 792 | struct sge *s = &adap->sge; |
0fbc81b3 | 793 | int err = 0; |
b8ff05a9 | 794 | |
4b8e27a8 HS |
795 | bitmap_zero(s->starving_fl, s->egr_sz); |
796 | bitmap_zero(s->txq_maperr, s->egr_sz); | |
b8ff05a9 DM |
797 | |
798 | if (adap->flags & USING_MSIX) | |
94cdb8bb | 799 | adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */ |
b8ff05a9 DM |
800 | else { |
801 | err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, | |
2337ba42 | 802 | NULL, NULL, NULL, -1); |
b8ff05a9 DM |
803 | if (err) |
804 | return err; | |
94cdb8bb | 805 | adap->msi_idx = -((int)s->intrq.abs_id + 1); |
b8ff05a9 DM |
806 | } |
807 | ||
808 | err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], | |
94cdb8bb | 809 | adap->msi_idx, NULL, fwevtq_handler, NULL, -1); |
0fbc81b3 HS |
810 | if (err) |
811 | t4_free_sge_resources(adap); | |
812 | return err; | |
813 | } | |
814 | ||
815 | /** | |
816 | * setup_sge_queues - configure SGE Tx/Rx/response queues | |
817 | * @adap: the adapter | |
818 | * | |
819 | * Determines how many sets of SGE queues to use and initializes them. | |
820 | * We support multiple queue sets per port if we have MSI-X, otherwise | |
821 | * just one queue set per port. | |
822 | */ | |
823 | static int setup_sge_queues(struct adapter *adap) | |
824 | { | |
825 | int err, i, j; | |
826 | struct sge *s = &adap->sge; | |
827 | struct sge_uld_rxq_info *rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; | |
828 | unsigned int cmplqid = 0; | |
b8ff05a9 DM |
829 | |
830 | for_each_port(adap, i) { | |
831 | struct net_device *dev = adap->port[i]; | |
832 | struct port_info *pi = netdev_priv(dev); | |
833 | struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; | |
834 | struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; | |
835 | ||
836 | for (j = 0; j < pi->nqsets; j++, q++) { | |
94cdb8bb HS |
837 | if (adap->msi_idx > 0) |
838 | adap->msi_idx++; | |
b8ff05a9 | 839 | err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, |
94cdb8bb | 840 | adap->msi_idx, &q->fl, |
145ef8a5 | 841 | t4_ethrx_handler, |
2337ba42 | 842 | NULL, |
145ef8a5 HS |
843 | t4_get_mps_bg_map(adap, |
844 | pi->tx_chan)); | |
b8ff05a9 DM |
845 | if (err) |
846 | goto freeout; | |
847 | q->rspq.idx = j; | |
848 | memset(&q->stats, 0, sizeof(q->stats)); | |
849 | } | |
850 | for (j = 0; j < pi->nqsets; j++, t++) { | |
851 | err = t4_sge_alloc_eth_txq(adap, t, dev, | |
852 | netdev_get_tx_queue(dev, j), | |
853 | s->fw_evtq.cntxt_id); | |
854 | if (err) | |
855 | goto freeout; | |
856 | } | |
857 | } | |
858 | ||
b8ff05a9 | 859 | for_each_port(adap, i) { |
0fbc81b3 | 860 | /* Note that cmplqid below is 0 if we don't |
b8ff05a9 DM |
861 | * have RDMA queues, and that's the right value. |
862 | */ | |
0fbc81b3 HS |
863 | if (rxq_info) |
864 | cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id; | |
865 | ||
b8ff05a9 | 866 | err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], |
0fbc81b3 | 867 | s->fw_evtq.cntxt_id, cmplqid); |
b8ff05a9 DM |
868 | if (err) |
869 | goto freeout; | |
870 | } | |
871 | ||
9bb59b96 | 872 | t4_write_reg(adap, is_t4(adap->params.chip) ? |
837e4a42 HS |
873 | MPS_TRC_RSS_CONTROL_A : |
874 | MPS_T5_TRC_RSS_CONTROL_A, | |
875 | RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | | |
876 | QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); | |
b8ff05a9 | 877 | return 0; |
0fbc81b3 HS |
878 | freeout: |
879 | t4_free_sge_resources(adap); | |
880 | return err; | |
b8ff05a9 DM |
881 | } |
882 | ||
b8ff05a9 DM |
883 | /* |
884 | * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc. | |
885 | * The allocated memory is cleared. | |
886 | */ | |
887 | void *t4_alloc_mem(size_t size) | |
888 | { | |
8be04b93 | 889 | void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); |
b8ff05a9 DM |
890 | |
891 | if (!p) | |
89bf67f1 | 892 | p = vzalloc(size); |
b8ff05a9 DM |
893 | return p; |
894 | } | |
895 | ||
896 | /* | |
897 | * Free memory allocated through alloc_mem(). | |
898 | */ | |
fd88b31a | 899 | void t4_free_mem(void *addr) |
b8ff05a9 | 900 | { |
d2fcb548 | 901 | kvfree(addr); |
b8ff05a9 DM |
902 | } |
903 | ||
688848b1 AB |
904 | static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, |
905 | void *accel_priv, select_queue_fallback_t fallback) | |
906 | { | |
907 | int txq; | |
908 | ||
909 | #ifdef CONFIG_CHELSIO_T4_DCB | |
910 | /* If a Data Center Bridging has been successfully negotiated on this | |
911 | * link then we'll use the skb's priority to map it to a TX Queue. | |
912 | * The skb's priority is determined via the VLAN Tag Priority Code | |
913 | * Point field. | |
914 | */ | |
915 | if (cxgb4_dcb_enabled(dev)) { | |
916 | u16 vlan_tci; | |
917 | int err; | |
918 | ||
919 | err = vlan_get_tag(skb, &vlan_tci); | |
920 | if (unlikely(err)) { | |
921 | if (net_ratelimit()) | |
922 | netdev_warn(dev, | |
923 | "TX Packet without VLAN Tag on DCB Link\n"); | |
924 | txq = 0; | |
925 | } else { | |
926 | txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; | |
84a200b3 VP |
927 | #ifdef CONFIG_CHELSIO_T4_FCOE |
928 | if (skb->protocol == htons(ETH_P_FCOE)) | |
929 | txq = skb->priority & 0x7; | |
930 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
688848b1 AB |
931 | } |
932 | return txq; | |
933 | } | |
934 | #endif /* CONFIG_CHELSIO_T4_DCB */ | |
935 | ||
936 | if (select_queue) { | |
937 | txq = (skb_rx_queue_recorded(skb) | |
938 | ? skb_get_rx_queue(skb) | |
939 | : smp_processor_id()); | |
940 | ||
941 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
942 | txq -= dev->real_num_tx_queues; | |
943 | ||
944 | return txq; | |
945 | } | |
946 | ||
947 | return fallback(dev, skb) % dev->real_num_tx_queues; | |
948 | } | |
949 | ||
b8ff05a9 DM |
950 | static int closest_timer(const struct sge *s, int time) |
951 | { | |
952 | int i, delta, match = 0, min_delta = INT_MAX; | |
953 | ||
954 | for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { | |
955 | delta = time - s->timer_val[i]; | |
956 | if (delta < 0) | |
957 | delta = -delta; | |
958 | if (delta < min_delta) { | |
959 | min_delta = delta; | |
960 | match = i; | |
961 | } | |
962 | } | |
963 | return match; | |
964 | } | |
965 | ||
966 | static int closest_thres(const struct sge *s, int thres) | |
967 | { | |
968 | int i, delta, match = 0, min_delta = INT_MAX; | |
969 | ||
970 | for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { | |
971 | delta = thres - s->counter_val[i]; | |
972 | if (delta < 0) | |
973 | delta = -delta; | |
974 | if (delta < min_delta) { | |
975 | min_delta = delta; | |
976 | match = i; | |
977 | } | |
978 | } | |
979 | return match; | |
980 | } | |
981 | ||
b8ff05a9 | 982 | /** |
812034f1 | 983 | * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters |
b8ff05a9 DM |
984 | * @q: the Rx queue |
985 | * @us: the hold-off time in us, or 0 to disable timer | |
986 | * @cnt: the hold-off packet count, or 0 to disable counter | |
987 | * | |
988 | * Sets an Rx queue's interrupt hold-off time and packet count. At least | |
989 | * one of the two needs to be enabled for the queue to generate interrupts. | |
990 | */ | |
812034f1 HS |
991 | int cxgb4_set_rspq_intr_params(struct sge_rspq *q, |
992 | unsigned int us, unsigned int cnt) | |
b8ff05a9 | 993 | { |
c887ad0e HS |
994 | struct adapter *adap = q->adap; |
995 | ||
b8ff05a9 DM |
996 | if ((us | cnt) == 0) |
997 | cnt = 1; | |
998 | ||
999 | if (cnt) { | |
1000 | int err; | |
1001 | u32 v, new_idx; | |
1002 | ||
1003 | new_idx = closest_thres(&adap->sge, cnt); | |
1004 | if (q->desc && q->pktcnt_idx != new_idx) { | |
1005 | /* the queue has already been created, update it */ | |
5167865a HS |
1006 | v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | |
1007 | FW_PARAMS_PARAM_X_V( | |
1008 | FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | | |
1009 | FW_PARAMS_PARAM_YZ_V(q->cntxt_id); | |
b2612722 HS |
1010 | err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, |
1011 | &v, &new_idx); | |
b8ff05a9 DM |
1012 | if (err) |
1013 | return err; | |
1014 | } | |
1015 | q->pktcnt_idx = new_idx; | |
1016 | } | |
1017 | ||
1018 | us = us == 0 ? 6 : closest_timer(&adap->sge, us); | |
1ecc7b7a | 1019 | q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); |
b8ff05a9 DM |
1020 | return 0; |
1021 | } | |
1022 | ||
c8f44aff | 1023 | static int cxgb_set_features(struct net_device *dev, netdev_features_t features) |
87b6cf51 | 1024 | { |
2ed28baa | 1025 | const struct port_info *pi = netdev_priv(dev); |
c8f44aff | 1026 | netdev_features_t changed = dev->features ^ features; |
19ecae2c | 1027 | int err; |
19ecae2c | 1028 | |
f646968f | 1029 | if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) |
2ed28baa | 1030 | return 0; |
19ecae2c | 1031 | |
b2612722 | 1032 | err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, |
2ed28baa | 1033 | -1, -1, -1, |
f646968f | 1034 | !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); |
2ed28baa | 1035 | if (unlikely(err)) |
f646968f | 1036 | dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; |
19ecae2c | 1037 | return err; |
87b6cf51 DM |
1038 | } |
1039 | ||
91744948 | 1040 | static int setup_debugfs(struct adapter *adap) |
b8ff05a9 | 1041 | { |
b8ff05a9 DM |
1042 | if (IS_ERR_OR_NULL(adap->debugfs_root)) |
1043 | return -1; | |
1044 | ||
fd88b31a HS |
1045 | #ifdef CONFIG_DEBUG_FS |
1046 | t4_setup_debugfs(adap); | |
1047 | #endif | |
b8ff05a9 DM |
1048 | return 0; |
1049 | } | |
1050 | ||
1051 | /* | |
1052 | * upper-layer driver support | |
1053 | */ | |
1054 | ||
1055 | /* | |
1056 | * Allocate an active-open TID and set it to the supplied value. | |
1057 | */ | |
1058 | int cxgb4_alloc_atid(struct tid_info *t, void *data) | |
1059 | { | |
1060 | int atid = -1; | |
1061 | ||
1062 | spin_lock_bh(&t->atid_lock); | |
1063 | if (t->afree) { | |
1064 | union aopen_entry *p = t->afree; | |
1065 | ||
f2b7e78d | 1066 | atid = (p - t->atid_tab) + t->atid_base; |
b8ff05a9 DM |
1067 | t->afree = p->next; |
1068 | p->data = data; | |
1069 | t->atids_in_use++; | |
1070 | } | |
1071 | spin_unlock_bh(&t->atid_lock); | |
1072 | return atid; | |
1073 | } | |
1074 | EXPORT_SYMBOL(cxgb4_alloc_atid); | |
1075 | ||
1076 | /* | |
1077 | * Release an active-open TID. | |
1078 | */ | |
1079 | void cxgb4_free_atid(struct tid_info *t, unsigned int atid) | |
1080 | { | |
f2b7e78d | 1081 | union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; |
b8ff05a9 DM |
1082 | |
1083 | spin_lock_bh(&t->atid_lock); | |
1084 | p->next = t->afree; | |
1085 | t->afree = p; | |
1086 | t->atids_in_use--; | |
1087 | spin_unlock_bh(&t->atid_lock); | |
1088 | } | |
1089 | EXPORT_SYMBOL(cxgb4_free_atid); | |
1090 | ||
1091 | /* | |
1092 | * Allocate a server TID and set it to the supplied value. | |
1093 | */ | |
1094 | int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) | |
1095 | { | |
1096 | int stid; | |
1097 | ||
1098 | spin_lock_bh(&t->stid_lock); | |
1099 | if (family == PF_INET) { | |
1100 | stid = find_first_zero_bit(t->stid_bmap, t->nstids); | |
1101 | if (stid < t->nstids) | |
1102 | __set_bit(stid, t->stid_bmap); | |
1103 | else | |
1104 | stid = -1; | |
1105 | } else { | |
a99c683e | 1106 | stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); |
b8ff05a9 DM |
1107 | if (stid < 0) |
1108 | stid = -1; | |
1109 | } | |
1110 | if (stid >= 0) { | |
1111 | t->stid_tab[stid].data = data; | |
1112 | stid += t->stid_base; | |
15f63b74 KS |
1113 | /* IPv6 requires max of 520 bits or 16 cells in TCAM |
1114 | * This is equivalent to 4 TIDs. With CLIP enabled it | |
1115 | * needs 2 TIDs. | |
1116 | */ | |
1117 | if (family == PF_INET) | |
1118 | t->stids_in_use++; | |
1119 | else | |
a99c683e | 1120 | t->stids_in_use += 2; |
b8ff05a9 DM |
1121 | } |
1122 | spin_unlock_bh(&t->stid_lock); | |
1123 | return stid; | |
1124 | } | |
1125 | EXPORT_SYMBOL(cxgb4_alloc_stid); | |
1126 | ||
dca4faeb VP |
1127 | /* Allocate a server filter TID and set it to the supplied value. |
1128 | */ | |
1129 | int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) | |
1130 | { | |
1131 | int stid; | |
1132 | ||
1133 | spin_lock_bh(&t->stid_lock); | |
1134 | if (family == PF_INET) { | |
1135 | stid = find_next_zero_bit(t->stid_bmap, | |
1136 | t->nstids + t->nsftids, t->nstids); | |
1137 | if (stid < (t->nstids + t->nsftids)) | |
1138 | __set_bit(stid, t->stid_bmap); | |
1139 | else | |
1140 | stid = -1; | |
1141 | } else { | |
1142 | stid = -1; | |
1143 | } | |
1144 | if (stid >= 0) { | |
1145 | t->stid_tab[stid].data = data; | |
470c60c4 KS |
1146 | stid -= t->nstids; |
1147 | stid += t->sftid_base; | |
2248b293 | 1148 | t->sftids_in_use++; |
dca4faeb VP |
1149 | } |
1150 | spin_unlock_bh(&t->stid_lock); | |
1151 | return stid; | |
1152 | } | |
1153 | EXPORT_SYMBOL(cxgb4_alloc_sftid); | |
1154 | ||
1155 | /* Release a server TID. | |
b8ff05a9 DM |
1156 | */ |
1157 | void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) | |
1158 | { | |
470c60c4 KS |
1159 | /* Is it a server filter TID? */ |
1160 | if (t->nsftids && (stid >= t->sftid_base)) { | |
1161 | stid -= t->sftid_base; | |
1162 | stid += t->nstids; | |
1163 | } else { | |
1164 | stid -= t->stid_base; | |
1165 | } | |
1166 | ||
b8ff05a9 DM |
1167 | spin_lock_bh(&t->stid_lock); |
1168 | if (family == PF_INET) | |
1169 | __clear_bit(stid, t->stid_bmap); | |
1170 | else | |
a99c683e | 1171 | bitmap_release_region(t->stid_bmap, stid, 1); |
b8ff05a9 | 1172 | t->stid_tab[stid].data = NULL; |
2248b293 HS |
1173 | if (stid < t->nstids) { |
1174 | if (family == PF_INET) | |
1175 | t->stids_in_use--; | |
1176 | else | |
a99c683e | 1177 | t->stids_in_use -= 2; |
2248b293 HS |
1178 | } else { |
1179 | t->sftids_in_use--; | |
1180 | } | |
b8ff05a9 DM |
1181 | spin_unlock_bh(&t->stid_lock); |
1182 | } | |
1183 | EXPORT_SYMBOL(cxgb4_free_stid); | |
1184 | ||
1185 | /* | |
1186 | * Populate a TID_RELEASE WR. Caller must properly size the skb. | |
1187 | */ | |
1188 | static void mk_tid_release(struct sk_buff *skb, unsigned int chan, | |
1189 | unsigned int tid) | |
1190 | { | |
1191 | struct cpl_tid_release *req; | |
1192 | ||
1193 | set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); | |
1194 | req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req)); | |
1195 | INIT_TP_WR(req, tid); | |
1196 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); | |
1197 | } | |
1198 | ||
1199 | /* | |
1200 | * Queue a TID release request and if necessary schedule a work queue to | |
1201 | * process it. | |
1202 | */ | |
31b9c19b | 1203 | static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, |
1204 | unsigned int tid) | |
b8ff05a9 DM |
1205 | { |
1206 | void **p = &t->tid_tab[tid]; | |
1207 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1208 | ||
1209 | spin_lock_bh(&adap->tid_release_lock); | |
1210 | *p = adap->tid_release_head; | |
1211 | /* Low 2 bits encode the Tx channel number */ | |
1212 | adap->tid_release_head = (void **)((uintptr_t)p | chan); | |
1213 | if (!adap->tid_release_task_busy) { | |
1214 | adap->tid_release_task_busy = true; | |
29aaee65 | 1215 | queue_work(adap->workq, &adap->tid_release_task); |
b8ff05a9 DM |
1216 | } |
1217 | spin_unlock_bh(&adap->tid_release_lock); | |
1218 | } | |
b8ff05a9 DM |
1219 | |
1220 | /* | |
1221 | * Process the list of pending TID release requests. | |
1222 | */ | |
1223 | static void process_tid_release_list(struct work_struct *work) | |
1224 | { | |
1225 | struct sk_buff *skb; | |
1226 | struct adapter *adap; | |
1227 | ||
1228 | adap = container_of(work, struct adapter, tid_release_task); | |
1229 | ||
1230 | spin_lock_bh(&adap->tid_release_lock); | |
1231 | while (adap->tid_release_head) { | |
1232 | void **p = adap->tid_release_head; | |
1233 | unsigned int chan = (uintptr_t)p & 3; | |
1234 | p = (void *)p - chan; | |
1235 | ||
1236 | adap->tid_release_head = *p; | |
1237 | *p = NULL; | |
1238 | spin_unlock_bh(&adap->tid_release_lock); | |
1239 | ||
1240 | while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), | |
1241 | GFP_KERNEL))) | |
1242 | schedule_timeout_uninterruptible(1); | |
1243 | ||
1244 | mk_tid_release(skb, chan, p - adap->tids.tid_tab); | |
1245 | t4_ofld_send(adap, skb); | |
1246 | spin_lock_bh(&adap->tid_release_lock); | |
1247 | } | |
1248 | adap->tid_release_task_busy = false; | |
1249 | spin_unlock_bh(&adap->tid_release_lock); | |
1250 | } | |
1251 | ||
1252 | /* | |
1253 | * Release a TID and inform HW. If we are unable to allocate the release | |
1254 | * message we defer to a work queue. | |
1255 | */ | |
1256 | void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid) | |
1257 | { | |
b8ff05a9 DM |
1258 | struct sk_buff *skb; |
1259 | struct adapter *adap = container_of(t, struct adapter, tids); | |
1260 | ||
9a1bb9f6 HS |
1261 | WARN_ON(tid >= t->ntids); |
1262 | ||
1263 | if (t->tid_tab[tid]) { | |
1264 | t->tid_tab[tid] = NULL; | |
1265 | if (t->hash_base && (tid >= t->hash_base)) | |
1266 | atomic_dec(&t->hash_tids_in_use); | |
1267 | else | |
1268 | atomic_dec(&t->tids_in_use); | |
1269 | } | |
1270 | ||
b8ff05a9 DM |
1271 | skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); |
1272 | if (likely(skb)) { | |
b8ff05a9 DM |
1273 | mk_tid_release(skb, chan, tid); |
1274 | t4_ofld_send(adap, skb); | |
1275 | } else | |
1276 | cxgb4_queue_tid_release(t, chan, tid); | |
b8ff05a9 DM |
1277 | } |
1278 | EXPORT_SYMBOL(cxgb4_remove_tid); | |
1279 | ||
1280 | /* | |
1281 | * Allocate and initialize the TID tables. Returns 0 on success. | |
1282 | */ | |
1283 | static int tid_init(struct tid_info *t) | |
1284 | { | |
b6f8eaec | 1285 | struct adapter *adap = container_of(t, struct adapter, tids); |
578b46b9 RL |
1286 | unsigned int max_ftids = t->nftids + t->nsftids; |
1287 | unsigned int natids = t->natids; | |
1288 | unsigned int stid_bmap_size; | |
1289 | unsigned int ftid_bmap_size; | |
1290 | size_t size; | |
b8ff05a9 | 1291 | |
dca4faeb | 1292 | stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); |
578b46b9 | 1293 | ftid_bmap_size = BITS_TO_LONGS(t->nftids); |
f2b7e78d VP |
1294 | size = t->ntids * sizeof(*t->tid_tab) + |
1295 | natids * sizeof(*t->atid_tab) + | |
b8ff05a9 | 1296 | t->nstids * sizeof(*t->stid_tab) + |
dca4faeb | 1297 | t->nsftids * sizeof(*t->stid_tab) + |
f2b7e78d | 1298 | stid_bmap_size * sizeof(long) + |
578b46b9 RL |
1299 | max_ftids * sizeof(*t->ftid_tab) + |
1300 | ftid_bmap_size * sizeof(long); | |
f2b7e78d | 1301 | |
b8ff05a9 DM |
1302 | t->tid_tab = t4_alloc_mem(size); |
1303 | if (!t->tid_tab) | |
1304 | return -ENOMEM; | |
1305 | ||
1306 | t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; | |
1307 | t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; | |
dca4faeb | 1308 | t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; |
f2b7e78d | 1309 | t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; |
578b46b9 | 1310 | t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids]; |
b8ff05a9 DM |
1311 | spin_lock_init(&t->stid_lock); |
1312 | spin_lock_init(&t->atid_lock); | |
578b46b9 | 1313 | spin_lock_init(&t->ftid_lock); |
b8ff05a9 DM |
1314 | |
1315 | t->stids_in_use = 0; | |
2248b293 | 1316 | t->sftids_in_use = 0; |
b8ff05a9 DM |
1317 | t->afree = NULL; |
1318 | t->atids_in_use = 0; | |
1319 | atomic_set(&t->tids_in_use, 0); | |
9a1bb9f6 | 1320 | atomic_set(&t->hash_tids_in_use, 0); |
b8ff05a9 DM |
1321 | |
1322 | /* Setup the free list for atid_tab and clear the stid bitmap. */ | |
1323 | if (natids) { | |
1324 | while (--natids) | |
1325 | t->atid_tab[natids - 1].next = &t->atid_tab[natids]; | |
1326 | t->afree = t->atid_tab; | |
1327 | } | |
b6f8eaec | 1328 | |
578b46b9 RL |
1329 | if (is_offload(adap)) { |
1330 | bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); | |
1331 | /* Reserve stid 0 for T4/T5 adapters */ | |
1332 | if (!t->stid_base && | |
1333 | CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) | |
1334 | __set_bit(0, t->stid_bmap); | |
1335 | } | |
1336 | ||
1337 | bitmap_zero(t->ftid_bmap, t->nftids); | |
b8ff05a9 DM |
1338 | return 0; |
1339 | } | |
1340 | ||
1341 | /** | |
1342 | * cxgb4_create_server - create an IP server | |
1343 | * @dev: the device | |
1344 | * @stid: the server TID | |
1345 | * @sip: local IP address to bind server to | |
1346 | * @sport: the server's TCP port | |
1347 | * @queue: queue to direct messages from this server to | |
1348 | * | |
1349 | * Create an IP server for the given port and address. | |
1350 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1351 | */ | |
1352 | int cxgb4_create_server(const struct net_device *dev, unsigned int stid, | |
793dad94 VP |
1353 | __be32 sip, __be16 sport, __be16 vlan, |
1354 | unsigned int queue) | |
b8ff05a9 DM |
1355 | { |
1356 | unsigned int chan; | |
1357 | struct sk_buff *skb; | |
1358 | struct adapter *adap; | |
1359 | struct cpl_pass_open_req *req; | |
80f40c1f | 1360 | int ret; |
b8ff05a9 DM |
1361 | |
1362 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1363 | if (!skb) | |
1364 | return -ENOMEM; | |
1365 | ||
1366 | adap = netdev2adap(dev); | |
1367 | req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req)); | |
1368 | INIT_TP_WR(req, 0); | |
1369 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); | |
1370 | req->local_port = sport; | |
1371 | req->peer_port = htons(0); | |
1372 | req->local_ip = sip; | |
1373 | req->peer_ip = htonl(0); | |
e46dab4d | 1374 | chan = rxq_to_chan(&adap->sge, queue); |
d7990b0c | 1375 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1376 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1377 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1378 | ret = t4_mgmt_tx(adap, skb); |
1379 | return net_xmit_eval(ret); | |
b8ff05a9 DM |
1380 | } |
1381 | EXPORT_SYMBOL(cxgb4_create_server); | |
1382 | ||
80f40c1f VP |
1383 | /* cxgb4_create_server6 - create an IPv6 server |
1384 | * @dev: the device | |
1385 | * @stid: the server TID | |
1386 | * @sip: local IPv6 address to bind server to | |
1387 | * @sport: the server's TCP port | |
1388 | * @queue: queue to direct messages from this server to | |
1389 | * | |
1390 | * Create an IPv6 server for the given port and address. | |
1391 | * Returns <0 on error and one of the %NET_XMIT_* values on success. | |
1392 | */ | |
1393 | int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, | |
1394 | const struct in6_addr *sip, __be16 sport, | |
1395 | unsigned int queue) | |
1396 | { | |
1397 | unsigned int chan; | |
1398 | struct sk_buff *skb; | |
1399 | struct adapter *adap; | |
1400 | struct cpl_pass_open_req6 *req; | |
1401 | int ret; | |
1402 | ||
1403 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1404 | if (!skb) | |
1405 | return -ENOMEM; | |
1406 | ||
1407 | adap = netdev2adap(dev); | |
1408 | req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req)); | |
1409 | INIT_TP_WR(req, 0); | |
1410 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); | |
1411 | req->local_port = sport; | |
1412 | req->peer_port = htons(0); | |
1413 | req->local_ip_hi = *(__be64 *)(sip->s6_addr); | |
1414 | req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); | |
1415 | req->peer_ip_hi = cpu_to_be64(0); | |
1416 | req->peer_ip_lo = cpu_to_be64(0); | |
1417 | chan = rxq_to_chan(&adap->sge, queue); | |
d7990b0c | 1418 | req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); |
6c53e938 HS |
1419 | req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | |
1420 | SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); | |
80f40c1f VP |
1421 | ret = t4_mgmt_tx(adap, skb); |
1422 | return net_xmit_eval(ret); | |
1423 | } | |
1424 | EXPORT_SYMBOL(cxgb4_create_server6); | |
1425 | ||
1426 | int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, | |
1427 | unsigned int queue, bool ipv6) | |
1428 | { | |
1429 | struct sk_buff *skb; | |
1430 | struct adapter *adap; | |
1431 | struct cpl_close_listsvr_req *req; | |
1432 | int ret; | |
1433 | ||
1434 | adap = netdev2adap(dev); | |
1435 | ||
1436 | skb = alloc_skb(sizeof(*req), GFP_KERNEL); | |
1437 | if (!skb) | |
1438 | return -ENOMEM; | |
1439 | ||
1440 | req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req)); | |
1441 | INIT_TP_WR(req, 0); | |
1442 | OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); | |
bdc590b9 HS |
1443 | req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : |
1444 | LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); | |
80f40c1f VP |
1445 | ret = t4_mgmt_tx(adap, skb); |
1446 | return net_xmit_eval(ret); | |
1447 | } | |
1448 | EXPORT_SYMBOL(cxgb4_remove_server); | |
1449 | ||
b8ff05a9 DM |
1450 | /** |
1451 | * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU | |
1452 | * @mtus: the HW MTU table | |
1453 | * @mtu: the target MTU | |
1454 | * @idx: index of selected entry in the MTU table | |
1455 | * | |
1456 | * Returns the index and the value in the HW MTU table that is closest to | |
1457 | * but does not exceed @mtu, unless @mtu is smaller than any value in the | |
1458 | * table, in which case that smallest available value is selected. | |
1459 | */ | |
1460 | unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, | |
1461 | unsigned int *idx) | |
1462 | { | |
1463 | unsigned int i = 0; | |
1464 | ||
1465 | while (i < NMTUS - 1 && mtus[i + 1] <= mtu) | |
1466 | ++i; | |
1467 | if (idx) | |
1468 | *idx = i; | |
1469 | return mtus[i]; | |
1470 | } | |
1471 | EXPORT_SYMBOL(cxgb4_best_mtu); | |
1472 | ||
92e7ae71 HS |
1473 | /** |
1474 | * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned | |
1475 | * @mtus: the HW MTU table | |
1476 | * @header_size: Header Size | |
1477 | * @data_size_max: maximum Data Segment Size | |
1478 | * @data_size_align: desired Data Segment Size Alignment (2^N) | |
1479 | * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) | |
1480 | * | |
1481 | * Similar to cxgb4_best_mtu() but instead of searching the Hardware | |
1482 | * MTU Table based solely on a Maximum MTU parameter, we break that | |
1483 | * parameter up into a Header Size and Maximum Data Segment Size, and | |
1484 | * provide a desired Data Segment Size Alignment. If we find an MTU in | |
1485 | * the Hardware MTU Table which will result in a Data Segment Size with | |
1486 | * the requested alignment _and_ that MTU isn't "too far" from the | |
1487 | * closest MTU, then we'll return that rather than the closest MTU. | |
1488 | */ | |
1489 | unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, | |
1490 | unsigned short header_size, | |
1491 | unsigned short data_size_max, | |
1492 | unsigned short data_size_align, | |
1493 | unsigned int *mtu_idxp) | |
1494 | { | |
1495 | unsigned short max_mtu = header_size + data_size_max; | |
1496 | unsigned short data_size_align_mask = data_size_align - 1; | |
1497 | int mtu_idx, aligned_mtu_idx; | |
1498 | ||
1499 | /* Scan the MTU Table till we find an MTU which is larger than our | |
1500 | * Maximum MTU or we reach the end of the table. Along the way, | |
1501 | * record the last MTU found, if any, which will result in a Data | |
1502 | * Segment Length matching the requested alignment. | |
1503 | */ | |
1504 | for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { | |
1505 | unsigned short data_size = mtus[mtu_idx] - header_size; | |
1506 | ||
1507 | /* If this MTU minus the Header Size would result in a | |
1508 | * Data Segment Size of the desired alignment, remember it. | |
1509 | */ | |
1510 | if ((data_size & data_size_align_mask) == 0) | |
1511 | aligned_mtu_idx = mtu_idx; | |
1512 | ||
1513 | /* If we're not at the end of the Hardware MTU Table and the | |
1514 | * next element is larger than our Maximum MTU, drop out of | |
1515 | * the loop. | |
1516 | */ | |
1517 | if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) | |
1518 | break; | |
1519 | } | |
1520 | ||
1521 | /* If we fell out of the loop because we ran to the end of the table, | |
1522 | * then we just have to use the last [largest] entry. | |
1523 | */ | |
1524 | if (mtu_idx == NMTUS) | |
1525 | mtu_idx--; | |
1526 | ||
1527 | /* If we found an MTU which resulted in the requested Data Segment | |
1528 | * Length alignment and that's "not far" from the largest MTU which is | |
1529 | * less than or equal to the maximum MTU, then use that. | |
1530 | */ | |
1531 | if (aligned_mtu_idx >= 0 && | |
1532 | mtu_idx - aligned_mtu_idx <= 1) | |
1533 | mtu_idx = aligned_mtu_idx; | |
1534 | ||
1535 | /* If the caller has passed in an MTU Index pointer, pass the | |
1536 | * MTU Index back. Return the MTU value. | |
1537 | */ | |
1538 | if (mtu_idxp) | |
1539 | *mtu_idxp = mtu_idx; | |
1540 | return mtus[mtu_idx]; | |
1541 | } | |
1542 | EXPORT_SYMBOL(cxgb4_best_aligned_mtu); | |
1543 | ||
27999805 H |
1544 | /** |
1545 | * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI | |
1546 | * @chip: chip type | |
1547 | * @viid: VI id of the given port | |
1548 | * | |
1549 | * Return the SMT index for this VI. | |
1550 | */ | |
1551 | unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid) | |
1552 | { | |
1553 | /* In T4/T5, SMT contains 256 SMAC entries organized in | |
1554 | * 128 rows of 2 entries each. | |
1555 | * In T6, SMT contains 256 SMAC entries in 256 rows. | |
1556 | * TODO: The below code needs to be updated when we add support | |
1557 | * for 256 VFs. | |
1558 | */ | |
1559 | if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) | |
1560 | return ((viid & 0x7f) << 1); | |
1561 | else | |
1562 | return (viid & 0x7f); | |
1563 | } | |
1564 | EXPORT_SYMBOL(cxgb4_tp_smt_idx); | |
1565 | ||
b8ff05a9 DM |
1566 | /** |
1567 | * cxgb4_port_chan - get the HW channel of a port | |
1568 | * @dev: the net device for the port | |
1569 | * | |
1570 | * Return the HW Tx channel of the given port. | |
1571 | */ | |
1572 | unsigned int cxgb4_port_chan(const struct net_device *dev) | |
1573 | { | |
1574 | return netdev2pinfo(dev)->tx_chan; | |
1575 | } | |
1576 | EXPORT_SYMBOL(cxgb4_port_chan); | |
1577 | ||
881806bc VP |
1578 | unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) |
1579 | { | |
1580 | struct adapter *adap = netdev2adap(dev); | |
2cc301d2 | 1581 | u32 v1, v2, lp_count, hp_count; |
881806bc | 1582 | |
f061de42 HS |
1583 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
1584 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 1585 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
1586 | lp_count = LP_COUNT_G(v1); |
1587 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 1588 | } else { |
f061de42 HS |
1589 | lp_count = LP_COUNT_T5_G(v1); |
1590 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
1591 | } |
1592 | return lpfifo ? lp_count : hp_count; | |
881806bc VP |
1593 | } |
1594 | EXPORT_SYMBOL(cxgb4_dbfifo_count); | |
1595 | ||
b8ff05a9 DM |
1596 | /** |
1597 | * cxgb4_port_viid - get the VI id of a port | |
1598 | * @dev: the net device for the port | |
1599 | * | |
1600 | * Return the VI id of the given port. | |
1601 | */ | |
1602 | unsigned int cxgb4_port_viid(const struct net_device *dev) | |
1603 | { | |
1604 | return netdev2pinfo(dev)->viid; | |
1605 | } | |
1606 | EXPORT_SYMBOL(cxgb4_port_viid); | |
1607 | ||
1608 | /** | |
1609 | * cxgb4_port_idx - get the index of a port | |
1610 | * @dev: the net device for the port | |
1611 | * | |
1612 | * Return the index of the given port. | |
1613 | */ | |
1614 | unsigned int cxgb4_port_idx(const struct net_device *dev) | |
1615 | { | |
1616 | return netdev2pinfo(dev)->port_id; | |
1617 | } | |
1618 | EXPORT_SYMBOL(cxgb4_port_idx); | |
1619 | ||
b8ff05a9 DM |
1620 | void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, |
1621 | struct tp_tcp_stats *v6) | |
1622 | { | |
1623 | struct adapter *adap = pci_get_drvdata(pdev); | |
1624 | ||
1625 | spin_lock(&adap->stats_lock); | |
1626 | t4_tp_get_tcp_stats(adap, v4, v6); | |
1627 | spin_unlock(&adap->stats_lock); | |
1628 | } | |
1629 | EXPORT_SYMBOL(cxgb4_get_tcp_stats); | |
1630 | ||
1631 | void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, | |
1632 | const unsigned int *pgsz_order) | |
1633 | { | |
1634 | struct adapter *adap = netdev2adap(dev); | |
1635 | ||
0d804338 HS |
1636 | t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); |
1637 | t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | | |
1638 | HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | | |
1639 | HPZ3_V(pgsz_order[3])); | |
b8ff05a9 DM |
1640 | } |
1641 | EXPORT_SYMBOL(cxgb4_iscsi_init); | |
1642 | ||
3069ee9b VP |
1643 | int cxgb4_flush_eq_cache(struct net_device *dev) |
1644 | { | |
1645 | struct adapter *adap = netdev2adap(dev); | |
3069ee9b | 1646 | |
5d700ecb | 1647 | return t4_sge_ctxt_flush(adap, adap->mbox); |
3069ee9b VP |
1648 | } |
1649 | EXPORT_SYMBOL(cxgb4_flush_eq_cache); | |
1650 | ||
1651 | static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) | |
1652 | { | |
f061de42 | 1653 | u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; |
3069ee9b VP |
1654 | __be64 indices; |
1655 | int ret; | |
1656 | ||
fc5ab020 HS |
1657 | spin_lock(&adap->win0_lock); |
1658 | ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, | |
1659 | sizeof(indices), (__be32 *)&indices, | |
1660 | T4_MEMORY_READ); | |
1661 | spin_unlock(&adap->win0_lock); | |
3069ee9b | 1662 | if (!ret) { |
404d9e3f VP |
1663 | *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; |
1664 | *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; | |
3069ee9b VP |
1665 | } |
1666 | return ret; | |
1667 | } | |
1668 | ||
1669 | int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, | |
1670 | u16 size) | |
1671 | { | |
1672 | struct adapter *adap = netdev2adap(dev); | |
1673 | u16 hw_pidx, hw_cidx; | |
1674 | int ret; | |
1675 | ||
1676 | ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); | |
1677 | if (ret) | |
1678 | goto out; | |
1679 | ||
1680 | if (pidx != hw_pidx) { | |
1681 | u16 delta; | |
f612b815 | 1682 | u32 val; |
3069ee9b VP |
1683 | |
1684 | if (pidx >= hw_pidx) | |
1685 | delta = pidx - hw_pidx; | |
1686 | else | |
1687 | delta = size - hw_pidx + pidx; | |
f612b815 HS |
1688 | |
1689 | if (is_t4(adap->params.chip)) | |
1690 | val = PIDX_V(delta); | |
1691 | else | |
1692 | val = PIDX_T5_V(delta); | |
3069ee9b | 1693 | wmb(); |
f612b815 HS |
1694 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
1695 | QID_V(qid) | val); | |
3069ee9b VP |
1696 | } |
1697 | out: | |
1698 | return ret; | |
1699 | } | |
1700 | EXPORT_SYMBOL(cxgb4_sync_txq_pidx); | |
1701 | ||
031cf476 HS |
1702 | int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) |
1703 | { | |
1704 | struct adapter *adap; | |
1705 | u32 offset, memtype, memaddr; | |
6559a7e8 | 1706 | u32 edc0_size, edc1_size, mc0_size, mc1_size, size; |
031cf476 HS |
1707 | u32 edc0_end, edc1_end, mc0_end, mc1_end; |
1708 | int ret; | |
1709 | ||
1710 | adap = netdev2adap(dev); | |
1711 | ||
1712 | offset = ((stag >> 8) * 32) + adap->vres.stag.start; | |
1713 | ||
1714 | /* Figure out where the offset lands in the Memory Type/Address scheme. | |
1715 | * This code assumes that the memory is laid out starting at offset 0 | |
1716 | * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 | |
1717 | * and EDC1. Some cards will have neither MC0 nor MC1, most cards have | |
1718 | * MC0, and some have both MC0 and MC1. | |
1719 | */ | |
6559a7e8 HS |
1720 | size = t4_read_reg(adap, MA_EDRAM0_BAR_A); |
1721 | edc0_size = EDRAM0_SIZE_G(size) << 20; | |
1722 | size = t4_read_reg(adap, MA_EDRAM1_BAR_A); | |
1723 | edc1_size = EDRAM1_SIZE_G(size) << 20; | |
1724 | size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); | |
1725 | mc0_size = EXT_MEM0_SIZE_G(size) << 20; | |
031cf476 HS |
1726 | |
1727 | edc0_end = edc0_size; | |
1728 | edc1_end = edc0_end + edc1_size; | |
1729 | mc0_end = edc1_end + mc0_size; | |
1730 | ||
1731 | if (offset < edc0_end) { | |
1732 | memtype = MEM_EDC0; | |
1733 | memaddr = offset; | |
1734 | } else if (offset < edc1_end) { | |
1735 | memtype = MEM_EDC1; | |
1736 | memaddr = offset - edc0_end; | |
1737 | } else { | |
1738 | if (offset < mc0_end) { | |
1739 | memtype = MEM_MC0; | |
1740 | memaddr = offset - edc1_end; | |
3ccc6cf7 | 1741 | } else if (is_t5(adap->params.chip)) { |
6559a7e8 HS |
1742 | size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); |
1743 | mc1_size = EXT_MEM1_SIZE_G(size) << 20; | |
031cf476 HS |
1744 | mc1_end = mc0_end + mc1_size; |
1745 | if (offset < mc1_end) { | |
1746 | memtype = MEM_MC1; | |
1747 | memaddr = offset - mc0_end; | |
1748 | } else { | |
1749 | /* offset beyond the end of any memory */ | |
1750 | goto err; | |
1751 | } | |
3ccc6cf7 HS |
1752 | } else { |
1753 | /* T4/T6 only has a single memory channel */ | |
1754 | goto err; | |
031cf476 HS |
1755 | } |
1756 | } | |
1757 | ||
1758 | spin_lock(&adap->win0_lock); | |
1759 | ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); | |
1760 | spin_unlock(&adap->win0_lock); | |
1761 | return ret; | |
1762 | ||
1763 | err: | |
1764 | dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", | |
1765 | stag, offset); | |
1766 | return -EINVAL; | |
1767 | } | |
1768 | EXPORT_SYMBOL(cxgb4_read_tpte); | |
1769 | ||
7730b4c7 HS |
1770 | u64 cxgb4_read_sge_timestamp(struct net_device *dev) |
1771 | { | |
1772 | u32 hi, lo; | |
1773 | struct adapter *adap; | |
1774 | ||
1775 | adap = netdev2adap(dev); | |
f612b815 HS |
1776 | lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); |
1777 | hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); | |
7730b4c7 HS |
1778 | |
1779 | return ((u64)hi << 32) | (u64)lo; | |
1780 | } | |
1781 | EXPORT_SYMBOL(cxgb4_read_sge_timestamp); | |
1782 | ||
df64e4d3 HS |
1783 | int cxgb4_bar2_sge_qregs(struct net_device *dev, |
1784 | unsigned int qid, | |
1785 | enum cxgb4_bar2_qtype qtype, | |
66cf188e | 1786 | int user, |
df64e4d3 HS |
1787 | u64 *pbar2_qoffset, |
1788 | unsigned int *pbar2_qid) | |
1789 | { | |
b2612722 | 1790 | return t4_bar2_sge_qregs(netdev2adap(dev), |
df64e4d3 HS |
1791 | qid, |
1792 | (qtype == CXGB4_BAR2_QTYPE_EGRESS | |
1793 | ? T4_BAR2_QTYPE_EGRESS | |
1794 | : T4_BAR2_QTYPE_INGRESS), | |
66cf188e | 1795 | user, |
df64e4d3 HS |
1796 | pbar2_qoffset, |
1797 | pbar2_qid); | |
1798 | } | |
1799 | EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); | |
1800 | ||
b8ff05a9 DM |
1801 | static struct pci_driver cxgb4_driver; |
1802 | ||
1803 | static void check_neigh_update(struct neighbour *neigh) | |
1804 | { | |
1805 | const struct device *parent; | |
1806 | const struct net_device *netdev = neigh->dev; | |
1807 | ||
d0d7b10b | 1808 | if (is_vlan_dev(netdev)) |
b8ff05a9 DM |
1809 | netdev = vlan_dev_real_dev(netdev); |
1810 | parent = netdev->dev.parent; | |
1811 | if (parent && parent->driver == &cxgb4_driver.driver) | |
1812 | t4_l2t_update(dev_get_drvdata(parent), neigh); | |
1813 | } | |
1814 | ||
1815 | static int netevent_cb(struct notifier_block *nb, unsigned long event, | |
1816 | void *data) | |
1817 | { | |
1818 | switch (event) { | |
1819 | case NETEVENT_NEIGH_UPDATE: | |
1820 | check_neigh_update(data); | |
1821 | break; | |
b8ff05a9 DM |
1822 | case NETEVENT_REDIRECT: |
1823 | default: | |
1824 | break; | |
1825 | } | |
1826 | return 0; | |
1827 | } | |
1828 | ||
1829 | static bool netevent_registered; | |
1830 | static struct notifier_block cxgb4_netevent_nb = { | |
1831 | .notifier_call = netevent_cb | |
1832 | }; | |
1833 | ||
3069ee9b VP |
1834 | static void drain_db_fifo(struct adapter *adap, int usecs) |
1835 | { | |
2cc301d2 | 1836 | u32 v1, v2, lp_count, hp_count; |
3069ee9b VP |
1837 | |
1838 | do { | |
f061de42 HS |
1839 | v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); |
1840 | v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); | |
d14807dd | 1841 | if (is_t4(adap->params.chip)) { |
f061de42 HS |
1842 | lp_count = LP_COUNT_G(v1); |
1843 | hp_count = HP_COUNT_G(v1); | |
2cc301d2 | 1844 | } else { |
f061de42 HS |
1845 | lp_count = LP_COUNT_T5_G(v1); |
1846 | hp_count = HP_COUNT_T5_G(v2); | |
2cc301d2 SR |
1847 | } |
1848 | ||
1849 | if (lp_count == 0 && hp_count == 0) | |
1850 | break; | |
3069ee9b VP |
1851 | set_current_state(TASK_UNINTERRUPTIBLE); |
1852 | schedule_timeout(usecs_to_jiffies(usecs)); | |
3069ee9b VP |
1853 | } while (1); |
1854 | } | |
1855 | ||
1856 | static void disable_txq_db(struct sge_txq *q) | |
1857 | { | |
05eb2389 SW |
1858 | unsigned long flags; |
1859 | ||
1860 | spin_lock_irqsave(&q->db_lock, flags); | |
3069ee9b | 1861 | q->db_disabled = 1; |
05eb2389 | 1862 | spin_unlock_irqrestore(&q->db_lock, flags); |
3069ee9b VP |
1863 | } |
1864 | ||
05eb2389 | 1865 | static void enable_txq_db(struct adapter *adap, struct sge_txq *q) |
3069ee9b VP |
1866 | { |
1867 | spin_lock_irq(&q->db_lock); | |
05eb2389 SW |
1868 | if (q->db_pidx_inc) { |
1869 | /* Make sure that all writes to the TX descriptors | |
1870 | * are committed before we tell HW about them. | |
1871 | */ | |
1872 | wmb(); | |
f612b815 HS |
1873 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
1874 | QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); | |
05eb2389 SW |
1875 | q->db_pidx_inc = 0; |
1876 | } | |
3069ee9b VP |
1877 | q->db_disabled = 0; |
1878 | spin_unlock_irq(&q->db_lock); | |
1879 | } | |
1880 | ||
1881 | static void disable_dbs(struct adapter *adap) | |
1882 | { | |
1883 | int i; | |
1884 | ||
1885 | for_each_ethrxq(&adap->sge, i) | |
1886 | disable_txq_db(&adap->sge.ethtxq[i].q); | |
ab677ff4 HS |
1887 | if (is_offload(adap)) { |
1888 | struct sge_uld_txq_info *txq_info = | |
1889 | adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
1890 | ||
1891 | if (txq_info) { | |
1892 | for_each_ofldtxq(&adap->sge, i) { | |
1893 | struct sge_uld_txq *txq = &txq_info->uldtxq[i]; | |
1894 | ||
1895 | disable_txq_db(&txq->q); | |
1896 | } | |
1897 | } | |
1898 | } | |
3069ee9b VP |
1899 | for_each_port(adap, i) |
1900 | disable_txq_db(&adap->sge.ctrlq[i].q); | |
1901 | } | |
1902 | ||
1903 | static void enable_dbs(struct adapter *adap) | |
1904 | { | |
1905 | int i; | |
1906 | ||
1907 | for_each_ethrxq(&adap->sge, i) | |
05eb2389 | 1908 | enable_txq_db(adap, &adap->sge.ethtxq[i].q); |
ab677ff4 HS |
1909 | if (is_offload(adap)) { |
1910 | struct sge_uld_txq_info *txq_info = | |
1911 | adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
1912 | ||
1913 | if (txq_info) { | |
1914 | for_each_ofldtxq(&adap->sge, i) { | |
1915 | struct sge_uld_txq *txq = &txq_info->uldtxq[i]; | |
1916 | ||
1917 | enable_txq_db(adap, &txq->q); | |
1918 | } | |
1919 | } | |
1920 | } | |
3069ee9b | 1921 | for_each_port(adap, i) |
05eb2389 SW |
1922 | enable_txq_db(adap, &adap->sge.ctrlq[i].q); |
1923 | } | |
1924 | ||
1925 | static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) | |
1926 | { | |
0fbc81b3 HS |
1927 | enum cxgb4_uld type = CXGB4_ULD_RDMA; |
1928 | ||
1929 | if (adap->uld && adap->uld[type].handle) | |
1930 | adap->uld[type].control(adap->uld[type].handle, cmd); | |
05eb2389 SW |
1931 | } |
1932 | ||
1933 | static void process_db_full(struct work_struct *work) | |
1934 | { | |
1935 | struct adapter *adap; | |
1936 | ||
1937 | adap = container_of(work, struct adapter, db_full_task); | |
1938 | ||
1939 | drain_db_fifo(adap, dbfifo_drain_delay); | |
1940 | enable_dbs(adap); | |
1941 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); | |
3ccc6cf7 HS |
1942 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
1943 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
1944 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, | |
1945 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); | |
1946 | else | |
1947 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, | |
1948 | DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); | |
3069ee9b VP |
1949 | } |
1950 | ||
1951 | static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) | |
1952 | { | |
1953 | u16 hw_pidx, hw_cidx; | |
1954 | int ret; | |
1955 | ||
05eb2389 | 1956 | spin_lock_irq(&q->db_lock); |
3069ee9b VP |
1957 | ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); |
1958 | if (ret) | |
1959 | goto out; | |
1960 | if (q->db_pidx != hw_pidx) { | |
1961 | u16 delta; | |
f612b815 | 1962 | u32 val; |
3069ee9b VP |
1963 | |
1964 | if (q->db_pidx >= hw_pidx) | |
1965 | delta = q->db_pidx - hw_pidx; | |
1966 | else | |
1967 | delta = q->size - hw_pidx + q->db_pidx; | |
f612b815 HS |
1968 | |
1969 | if (is_t4(adap->params.chip)) | |
1970 | val = PIDX_V(delta); | |
1971 | else | |
1972 | val = PIDX_T5_V(delta); | |
3069ee9b | 1973 | wmb(); |
f612b815 HS |
1974 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
1975 | QID_V(q->cntxt_id) | val); | |
3069ee9b VP |
1976 | } |
1977 | out: | |
1978 | q->db_disabled = 0; | |
05eb2389 SW |
1979 | q->db_pidx_inc = 0; |
1980 | spin_unlock_irq(&q->db_lock); | |
3069ee9b VP |
1981 | if (ret) |
1982 | CH_WARN(adap, "DB drop recovery failed.\n"); | |
1983 | } | |
0fbc81b3 | 1984 | |
3069ee9b VP |
1985 | static void recover_all_queues(struct adapter *adap) |
1986 | { | |
1987 | int i; | |
1988 | ||
1989 | for_each_ethrxq(&adap->sge, i) | |
1990 | sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); | |
ab677ff4 HS |
1991 | if (is_offload(adap)) { |
1992 | struct sge_uld_txq_info *txq_info = | |
1993 | adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
1994 | if (txq_info) { | |
1995 | for_each_ofldtxq(&adap->sge, i) { | |
1996 | struct sge_uld_txq *txq = &txq_info->uldtxq[i]; | |
1997 | ||
1998 | sync_txq_pidx(adap, &txq->q); | |
1999 | } | |
2000 | } | |
2001 | } | |
3069ee9b VP |
2002 | for_each_port(adap, i) |
2003 | sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); | |
2004 | } | |
2005 | ||
881806bc VP |
2006 | static void process_db_drop(struct work_struct *work) |
2007 | { | |
2008 | struct adapter *adap; | |
881806bc | 2009 | |
3069ee9b | 2010 | adap = container_of(work, struct adapter, db_drop_task); |
881806bc | 2011 | |
d14807dd | 2012 | if (is_t4(adap->params.chip)) { |
05eb2389 | 2013 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2014 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); |
05eb2389 | 2015 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2016 | recover_all_queues(adap); |
05eb2389 | 2017 | drain_db_fifo(adap, dbfifo_drain_delay); |
2cc301d2 | 2018 | enable_dbs(adap); |
05eb2389 | 2019 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); |
3ccc6cf7 | 2020 | } else if (is_t5(adap->params.chip)) { |
2cc301d2 SR |
2021 | u32 dropped_db = t4_read_reg(adap, 0x010ac); |
2022 | u16 qid = (dropped_db >> 15) & 0x1ffff; | |
2023 | u16 pidx_inc = dropped_db & 0x1fff; | |
df64e4d3 HS |
2024 | u64 bar2_qoffset; |
2025 | unsigned int bar2_qid; | |
2026 | int ret; | |
2cc301d2 | 2027 | |
b2612722 | 2028 | ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, |
e0456717 | 2029 | 0, &bar2_qoffset, &bar2_qid); |
df64e4d3 HS |
2030 | if (ret) |
2031 | dev_err(adap->pdev_dev, "doorbell drop recovery: " | |
2032 | "qid=%d, pidx_inc=%d\n", qid, pidx_inc); | |
2033 | else | |
f612b815 | 2034 | writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), |
df64e4d3 | 2035 | adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); |
2cc301d2 SR |
2036 | |
2037 | /* Re-enable BAR2 WC */ | |
2038 | t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); | |
2039 | } | |
2040 | ||
3ccc6cf7 HS |
2041 | if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
2042 | t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); | |
881806bc VP |
2043 | } |
2044 | ||
2045 | void t4_db_full(struct adapter *adap) | |
2046 | { | |
d14807dd | 2047 | if (is_t4(adap->params.chip)) { |
05eb2389 SW |
2048 | disable_dbs(adap); |
2049 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
f612b815 HS |
2050 | t4_set_reg_field(adap, SGE_INT_ENABLE3_A, |
2051 | DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); | |
29aaee65 | 2052 | queue_work(adap->workq, &adap->db_full_task); |
2cc301d2 | 2053 | } |
881806bc VP |
2054 | } |
2055 | ||
2056 | void t4_db_dropped(struct adapter *adap) | |
2057 | { | |
05eb2389 SW |
2058 | if (is_t4(adap->params.chip)) { |
2059 | disable_dbs(adap); | |
2060 | notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); | |
2061 | } | |
29aaee65 | 2062 | queue_work(adap->workq, &adap->db_drop_task); |
881806bc VP |
2063 | } |
2064 | ||
0fbc81b3 HS |
2065 | void t4_register_netevent_notifier(void) |
2066 | { | |
b8ff05a9 DM |
2067 | if (!netevent_registered) { |
2068 | register_netevent_notifier(&cxgb4_netevent_nb); | |
2069 | netevent_registered = true; | |
2070 | } | |
b8ff05a9 DM |
2071 | } |
2072 | ||
2073 | static void detach_ulds(struct adapter *adap) | |
2074 | { | |
2075 | unsigned int i; | |
2076 | ||
2077 | mutex_lock(&uld_mutex); | |
2078 | list_del(&adap->list_node); | |
2079 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
94cdb8bb HS |
2080 | if (adap->uld && adap->uld[i].handle) { |
2081 | adap->uld[i].state_change(adap->uld[i].handle, | |
2082 | CXGB4_STATE_DETACH); | |
2083 | adap->uld[i].handle = NULL; | |
2084 | } | |
b8ff05a9 DM |
2085 | if (netevent_registered && list_empty(&adapter_list)) { |
2086 | unregister_netevent_notifier(&cxgb4_netevent_nb); | |
2087 | netevent_registered = false; | |
2088 | } | |
2089 | mutex_unlock(&uld_mutex); | |
2090 | } | |
2091 | ||
2092 | static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) | |
2093 | { | |
2094 | unsigned int i; | |
2095 | ||
2096 | mutex_lock(&uld_mutex); | |
2097 | for (i = 0; i < CXGB4_ULD_MAX; i++) | |
94cdb8bb HS |
2098 | if (adap->uld && adap->uld[i].handle) |
2099 | adap->uld[i].state_change(adap->uld[i].handle, | |
2100 | new_state); | |
b8ff05a9 DM |
2101 | mutex_unlock(&uld_mutex); |
2102 | } | |
2103 | ||
1bb60376 | 2104 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
2105 | static int cxgb4_inet6addr_handler(struct notifier_block *this, |
2106 | unsigned long event, void *data) | |
01bcca68 | 2107 | { |
b5a02f50 AB |
2108 | struct inet6_ifaddr *ifa = data; |
2109 | struct net_device *event_dev = ifa->idev->dev; | |
2110 | const struct device *parent = NULL; | |
2111 | #if IS_ENABLED(CONFIG_BONDING) | |
01bcca68 | 2112 | struct adapter *adap; |
b5a02f50 | 2113 | #endif |
d0d7b10b | 2114 | if (is_vlan_dev(event_dev)) |
b5a02f50 AB |
2115 | event_dev = vlan_dev_real_dev(event_dev); |
2116 | #if IS_ENABLED(CONFIG_BONDING) | |
2117 | if (event_dev->flags & IFF_MASTER) { | |
2118 | list_for_each_entry(adap, &adapter_list, list_node) { | |
2119 | switch (event) { | |
2120 | case NETDEV_UP: | |
2121 | cxgb4_clip_get(adap->port[0], | |
2122 | (const u32 *)ifa, 1); | |
2123 | break; | |
2124 | case NETDEV_DOWN: | |
2125 | cxgb4_clip_release(adap->port[0], | |
2126 | (const u32 *)ifa, 1); | |
2127 | break; | |
2128 | default: | |
2129 | break; | |
2130 | } | |
2131 | } | |
2132 | return NOTIFY_OK; | |
2133 | } | |
2134 | #endif | |
01bcca68 | 2135 | |
b5a02f50 AB |
2136 | if (event_dev) |
2137 | parent = event_dev->dev.parent; | |
01bcca68 | 2138 | |
b5a02f50 | 2139 | if (parent && parent->driver == &cxgb4_driver.driver) { |
01bcca68 VP |
2140 | switch (event) { |
2141 | case NETDEV_UP: | |
b5a02f50 | 2142 | cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2143 | break; |
2144 | case NETDEV_DOWN: | |
b5a02f50 | 2145 | cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); |
01bcca68 VP |
2146 | break; |
2147 | default: | |
2148 | break; | |
2149 | } | |
2150 | } | |
b5a02f50 | 2151 | return NOTIFY_OK; |
01bcca68 VP |
2152 | } |
2153 | ||
b5a02f50 | 2154 | static bool inet6addr_registered; |
01bcca68 VP |
2155 | static struct notifier_block cxgb4_inet6addr_notifier = { |
2156 | .notifier_call = cxgb4_inet6addr_handler | |
2157 | }; | |
2158 | ||
01bcca68 VP |
2159 | static void update_clip(const struct adapter *adap) |
2160 | { | |
2161 | int i; | |
2162 | struct net_device *dev; | |
2163 | int ret; | |
2164 | ||
2165 | rcu_read_lock(); | |
2166 | ||
2167 | for (i = 0; i < MAX_NPORTS; i++) { | |
2168 | dev = adap->port[i]; | |
2169 | ret = 0; | |
2170 | ||
2171 | if (dev) | |
b5a02f50 | 2172 | ret = cxgb4_update_root_dev_clip(dev); |
01bcca68 VP |
2173 | |
2174 | if (ret < 0) | |
2175 | break; | |
2176 | } | |
2177 | rcu_read_unlock(); | |
2178 | } | |
1bb60376 | 2179 | #endif /* IS_ENABLED(CONFIG_IPV6) */ |
01bcca68 | 2180 | |
b8ff05a9 DM |
2181 | /** |
2182 | * cxgb_up - enable the adapter | |
2183 | * @adap: adapter being enabled | |
2184 | * | |
2185 | * Called when the first port is enabled, this function performs the | |
2186 | * actions necessary to make an adapter operational, such as completing | |
2187 | * the initialization of HW modules, and enabling interrupts. | |
2188 | * | |
2189 | * Must be called with the rtnl lock held. | |
2190 | */ | |
2191 | static int cxgb_up(struct adapter *adap) | |
2192 | { | |
aaefae9b | 2193 | int err; |
b8ff05a9 | 2194 | |
aaefae9b DM |
2195 | err = setup_sge_queues(adap); |
2196 | if (err) | |
2197 | goto out; | |
2198 | err = setup_rss(adap); | |
2199 | if (err) | |
2200 | goto freeq; | |
b8ff05a9 DM |
2201 | |
2202 | if (adap->flags & USING_MSIX) { | |
aaefae9b | 2203 | name_msix_vecs(adap); |
b8ff05a9 DM |
2204 | err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, |
2205 | adap->msix_info[0].desc, adap); | |
2206 | if (err) | |
2207 | goto irq_err; | |
b8ff05a9 DM |
2208 | err = request_msix_queue_irqs(adap); |
2209 | if (err) { | |
2210 | free_irq(adap->msix_info[0].vec, adap); | |
2211 | goto irq_err; | |
2212 | } | |
2213 | } else { | |
2214 | err = request_irq(adap->pdev->irq, t4_intr_handler(adap), | |
2215 | (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, | |
b1a3c2b6 | 2216 | adap->port[0]->name, adap); |
b8ff05a9 DM |
2217 | if (err) |
2218 | goto irq_err; | |
2219 | } | |
2220 | enable_rx(adap); | |
2221 | t4_sge_start(adap); | |
2222 | t4_intr_enable(adap); | |
aaefae9b | 2223 | adap->flags |= FULL_INIT_DONE; |
b8ff05a9 | 2224 | notify_ulds(adap, CXGB4_STATE_UP); |
1bb60376 | 2225 | #if IS_ENABLED(CONFIG_IPV6) |
01bcca68 | 2226 | update_clip(adap); |
1bb60376 | 2227 | #endif |
fc08a01a HS |
2228 | /* Initialize hash mac addr list*/ |
2229 | INIT_LIST_HEAD(&adap->mac_hlist); | |
b8ff05a9 DM |
2230 | out: |
2231 | return err; | |
2232 | irq_err: | |
2233 | dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); | |
aaefae9b DM |
2234 | freeq: |
2235 | t4_free_sge_resources(adap); | |
b8ff05a9 DM |
2236 | goto out; |
2237 | } | |
2238 | ||
2239 | static void cxgb_down(struct adapter *adapter) | |
2240 | { | |
b8ff05a9 | 2241 | cancel_work_sync(&adapter->tid_release_task); |
881806bc VP |
2242 | cancel_work_sync(&adapter->db_full_task); |
2243 | cancel_work_sync(&adapter->db_drop_task); | |
b8ff05a9 | 2244 | adapter->tid_release_task_busy = false; |
204dc3c0 | 2245 | adapter->tid_release_head = NULL; |
b8ff05a9 | 2246 | |
aaefae9b DM |
2247 | t4_sge_stop(adapter); |
2248 | t4_free_sge_resources(adapter); | |
2249 | adapter->flags &= ~FULL_INIT_DONE; | |
b8ff05a9 DM |
2250 | } |
2251 | ||
2252 | /* | |
2253 | * net_device operations | |
2254 | */ | |
2255 | static int cxgb_open(struct net_device *dev) | |
2256 | { | |
2257 | int err; | |
2258 | struct port_info *pi = netdev_priv(dev); | |
2259 | struct adapter *adapter = pi->adapter; | |
2260 | ||
6a3c869a DM |
2261 | netif_carrier_off(dev); |
2262 | ||
aaefae9b DM |
2263 | if (!(adapter->flags & FULL_INIT_DONE)) { |
2264 | err = cxgb_up(adapter); | |
2265 | if (err < 0) | |
2266 | return err; | |
2267 | } | |
b8ff05a9 | 2268 | |
f68707b8 DM |
2269 | err = link_start(dev); |
2270 | if (!err) | |
2271 | netif_tx_start_all_queues(dev); | |
2272 | return err; | |
b8ff05a9 DM |
2273 | } |
2274 | ||
2275 | static int cxgb_close(struct net_device *dev) | |
2276 | { | |
b8ff05a9 DM |
2277 | struct port_info *pi = netdev_priv(dev); |
2278 | struct adapter *adapter = pi->adapter; | |
2279 | ||
2280 | netif_tx_stop_all_queues(dev); | |
2281 | netif_carrier_off(dev); | |
b2612722 | 2282 | return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false); |
b8ff05a9 DM |
2283 | } |
2284 | ||
dca4faeb | 2285 | int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, |
793dad94 VP |
2286 | __be32 sip, __be16 sport, __be16 vlan, |
2287 | unsigned int queue, unsigned char port, unsigned char mask) | |
dca4faeb VP |
2288 | { |
2289 | int ret; | |
2290 | struct filter_entry *f; | |
2291 | struct adapter *adap; | |
2292 | int i; | |
2293 | u8 *val; | |
2294 | ||
2295 | adap = netdev2adap(dev); | |
2296 | ||
1cab775c | 2297 | /* Adjust stid to correct filter index */ |
470c60c4 | 2298 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2299 | stid += adap->tids.nftids; |
2300 | ||
dca4faeb VP |
2301 | /* Check to make sure the filter requested is writable ... |
2302 | */ | |
2303 | f = &adap->tids.ftid_tab[stid]; | |
2304 | ret = writable_filter(f); | |
2305 | if (ret) | |
2306 | return ret; | |
2307 | ||
2308 | /* Clear out any old resources being used by the filter before | |
2309 | * we start constructing the new filter. | |
2310 | */ | |
2311 | if (f->valid) | |
2312 | clear_filter(adap, f); | |
2313 | ||
2314 | /* Clear out filter specifications */ | |
2315 | memset(&f->fs, 0, sizeof(struct ch_filter_specification)); | |
2316 | f->fs.val.lport = cpu_to_be16(sport); | |
2317 | f->fs.mask.lport = ~0; | |
2318 | val = (u8 *)&sip; | |
793dad94 | 2319 | if ((val[0] | val[1] | val[2] | val[3]) != 0) { |
dca4faeb VP |
2320 | for (i = 0; i < 4; i++) { |
2321 | f->fs.val.lip[i] = val[i]; | |
2322 | f->fs.mask.lip[i] = ~0; | |
2323 | } | |
0d804338 | 2324 | if (adap->params.tp.vlan_pri_map & PORT_F) { |
793dad94 VP |
2325 | f->fs.val.iport = port; |
2326 | f->fs.mask.iport = mask; | |
2327 | } | |
2328 | } | |
dca4faeb | 2329 | |
0d804338 | 2330 | if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { |
7c89e555 KS |
2331 | f->fs.val.proto = IPPROTO_TCP; |
2332 | f->fs.mask.proto = ~0; | |
2333 | } | |
2334 | ||
dca4faeb VP |
2335 | f->fs.dirsteer = 1; |
2336 | f->fs.iq = queue; | |
2337 | /* Mark filter as locked */ | |
2338 | f->locked = 1; | |
2339 | f->fs.rpttid = 1; | |
2340 | ||
2341 | ret = set_filter_wr(adap, stid); | |
2342 | if (ret) { | |
2343 | clear_filter(adap, f); | |
2344 | return ret; | |
2345 | } | |
2346 | ||
2347 | return 0; | |
2348 | } | |
2349 | EXPORT_SYMBOL(cxgb4_create_server_filter); | |
2350 | ||
2351 | int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, | |
2352 | unsigned int queue, bool ipv6) | |
2353 | { | |
dca4faeb VP |
2354 | struct filter_entry *f; |
2355 | struct adapter *adap; | |
2356 | ||
2357 | adap = netdev2adap(dev); | |
1cab775c VP |
2358 | |
2359 | /* Adjust stid to correct filter index */ | |
470c60c4 | 2360 | stid -= adap->tids.sftid_base; |
1cab775c VP |
2361 | stid += adap->tids.nftids; |
2362 | ||
dca4faeb VP |
2363 | f = &adap->tids.ftid_tab[stid]; |
2364 | /* Unlock the filter */ | |
2365 | f->locked = 0; | |
2366 | ||
8c14846d | 2367 | return delete_filter(adap, stid); |
dca4faeb VP |
2368 | } |
2369 | EXPORT_SYMBOL(cxgb4_remove_server_filter); | |
2370 | ||
bc1f4470 | 2371 | static void cxgb_get_stats(struct net_device *dev, |
2372 | struct rtnl_link_stats64 *ns) | |
b8ff05a9 DM |
2373 | { |
2374 | struct port_stats stats; | |
2375 | struct port_info *p = netdev_priv(dev); | |
2376 | struct adapter *adapter = p->adapter; | |
b8ff05a9 | 2377 | |
9fe6cb58 GS |
2378 | /* Block retrieving statistics during EEH error |
2379 | * recovery. Otherwise, the recovery might fail | |
2380 | * and the PCI device will be removed permanently | |
2381 | */ | |
b8ff05a9 | 2382 | spin_lock(&adapter->stats_lock); |
9fe6cb58 GS |
2383 | if (!netif_device_present(dev)) { |
2384 | spin_unlock(&adapter->stats_lock); | |
bc1f4470 | 2385 | return; |
9fe6cb58 | 2386 | } |
a4cfd929 HS |
2387 | t4_get_port_stats_offset(adapter, p->tx_chan, &stats, |
2388 | &p->stats_base); | |
b8ff05a9 DM |
2389 | spin_unlock(&adapter->stats_lock); |
2390 | ||
2391 | ns->tx_bytes = stats.tx_octets; | |
2392 | ns->tx_packets = stats.tx_frames; | |
2393 | ns->rx_bytes = stats.rx_octets; | |
2394 | ns->rx_packets = stats.rx_frames; | |
2395 | ns->multicast = stats.rx_mcast_frames; | |
2396 | ||
2397 | /* detailed rx_errors */ | |
2398 | ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + | |
2399 | stats.rx_runt; | |
2400 | ns->rx_over_errors = 0; | |
2401 | ns->rx_crc_errors = stats.rx_fcs_err; | |
2402 | ns->rx_frame_errors = stats.rx_symbol_err; | |
b93f79be | 2403 | ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 + |
b8ff05a9 DM |
2404 | stats.rx_ovflow2 + stats.rx_ovflow3 + |
2405 | stats.rx_trunc0 + stats.rx_trunc1 + | |
2406 | stats.rx_trunc2 + stats.rx_trunc3; | |
2407 | ns->rx_missed_errors = 0; | |
2408 | ||
2409 | /* detailed tx_errors */ | |
2410 | ns->tx_aborted_errors = 0; | |
2411 | ns->tx_carrier_errors = 0; | |
2412 | ns->tx_fifo_errors = 0; | |
2413 | ns->tx_heartbeat_errors = 0; | |
2414 | ns->tx_window_errors = 0; | |
2415 | ||
2416 | ns->tx_errors = stats.tx_error_frames; | |
2417 | ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + | |
2418 | ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; | |
b8ff05a9 DM |
2419 | } |
2420 | ||
2421 | static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
2422 | { | |
060e0c75 | 2423 | unsigned int mbox; |
b8ff05a9 DM |
2424 | int ret = 0, prtad, devad; |
2425 | struct port_info *pi = netdev_priv(dev); | |
2426 | struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; | |
2427 | ||
2428 | switch (cmd) { | |
2429 | case SIOCGMIIPHY: | |
2430 | if (pi->mdio_addr < 0) | |
2431 | return -EOPNOTSUPP; | |
2432 | data->phy_id = pi->mdio_addr; | |
2433 | break; | |
2434 | case SIOCGMIIREG: | |
2435 | case SIOCSMIIREG: | |
2436 | if (mdio_phy_id_is_c45(data->phy_id)) { | |
2437 | prtad = mdio_phy_id_prtad(data->phy_id); | |
2438 | devad = mdio_phy_id_devad(data->phy_id); | |
2439 | } else if (data->phy_id < 32) { | |
2440 | prtad = data->phy_id; | |
2441 | devad = 0; | |
2442 | data->reg_num &= 0x1f; | |
2443 | } else | |
2444 | return -EINVAL; | |
2445 | ||
b2612722 | 2446 | mbox = pi->adapter->pf; |
b8ff05a9 | 2447 | if (cmd == SIOCGMIIREG) |
060e0c75 | 2448 | ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
2449 | data->reg_num, &data->val_out); |
2450 | else | |
060e0c75 | 2451 | ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, |
b8ff05a9 DM |
2452 | data->reg_num, data->val_in); |
2453 | break; | |
5e2a5ebc HS |
2454 | case SIOCGHWTSTAMP: |
2455 | return copy_to_user(req->ifr_data, &pi->tstamp_config, | |
2456 | sizeof(pi->tstamp_config)) ? | |
2457 | -EFAULT : 0; | |
2458 | case SIOCSHWTSTAMP: | |
2459 | if (copy_from_user(&pi->tstamp_config, req->ifr_data, | |
2460 | sizeof(pi->tstamp_config))) | |
2461 | return -EFAULT; | |
2462 | ||
2463 | switch (pi->tstamp_config.rx_filter) { | |
2464 | case HWTSTAMP_FILTER_NONE: | |
2465 | pi->rxtstamp = false; | |
2466 | break; | |
2467 | case HWTSTAMP_FILTER_ALL: | |
2468 | pi->rxtstamp = true; | |
2469 | break; | |
2470 | default: | |
2471 | pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; | |
2472 | return -ERANGE; | |
2473 | } | |
2474 | ||
2475 | return copy_to_user(req->ifr_data, &pi->tstamp_config, | |
2476 | sizeof(pi->tstamp_config)) ? | |
2477 | -EFAULT : 0; | |
b8ff05a9 DM |
2478 | default: |
2479 | return -EOPNOTSUPP; | |
2480 | } | |
2481 | return ret; | |
2482 | } | |
2483 | ||
2484 | static void cxgb_set_rxmode(struct net_device *dev) | |
2485 | { | |
2486 | /* unfortunately we can't return errors to the stack */ | |
2487 | set_rxmode(dev, -1, false); | |
2488 | } | |
2489 | ||
2490 | static int cxgb_change_mtu(struct net_device *dev, int new_mtu) | |
2491 | { | |
2492 | int ret; | |
2493 | struct port_info *pi = netdev_priv(dev); | |
2494 | ||
b2612722 | 2495 | ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, |
060e0c75 | 2496 | -1, -1, -1, true); |
b8ff05a9 DM |
2497 | if (!ret) |
2498 | dev->mtu = new_mtu; | |
2499 | return ret; | |
2500 | } | |
2501 | ||
858aa65c | 2502 | #ifdef CONFIG_PCI_IOV |
e7b48a32 HS |
2503 | static int dummy_open(struct net_device *dev) |
2504 | { | |
2505 | /* Turn carrier off since we don't have to transmit anything on this | |
2506 | * interface. | |
2507 | */ | |
2508 | netif_carrier_off(dev); | |
2509 | return 0; | |
2510 | } | |
2511 | ||
661dbeb9 HS |
2512 | /* Fill MAC address that will be assigned by the FW */ |
2513 | static void fill_vf_station_mac_addr(struct adapter *adap) | |
2514 | { | |
2515 | unsigned int i; | |
2516 | u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN]; | |
2517 | int err; | |
2518 | u8 *na; | |
2519 | u16 a, b; | |
2520 | ||
2521 | err = t4_get_raw_vpd_params(adap, &adap->params.vpd); | |
2522 | if (!err) { | |
2523 | na = adap->params.vpd.na; | |
2524 | for (i = 0; i < ETH_ALEN; i++) | |
2525 | hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + | |
2526 | hex2val(na[2 * i + 1])); | |
2527 | a = (hw_addr[0] << 8) | hw_addr[1]; | |
2528 | b = (hw_addr[1] << 8) | hw_addr[2]; | |
2529 | a ^= b; | |
2530 | a |= 0x0200; /* locally assigned Ethernet MAC address */ | |
2531 | a &= ~0x0100; /* not a multicast Ethernet MAC address */ | |
2532 | macaddr[0] = a >> 8; | |
2533 | macaddr[1] = a & 0xff; | |
2534 | ||
2535 | for (i = 2; i < 5; i++) | |
2536 | macaddr[i] = hw_addr[i + 1]; | |
2537 | ||
2538 | for (i = 0; i < adap->num_vfs; i++) { | |
2539 | macaddr[5] = adap->pf * 16 + i; | |
2540 | ether_addr_copy(adap->vfinfo[i].vf_mac_addr, macaddr); | |
2541 | } | |
2542 | } | |
2543 | } | |
2544 | ||
858aa65c HS |
2545 | static int cxgb_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
2546 | { | |
2547 | struct port_info *pi = netdev_priv(dev); | |
2548 | struct adapter *adap = pi->adapter; | |
661dbeb9 | 2549 | int ret; |
858aa65c HS |
2550 | |
2551 | /* verify MAC addr is valid */ | |
2552 | if (!is_valid_ether_addr(mac)) { | |
2553 | dev_err(pi->adapter->pdev_dev, | |
2554 | "Invalid Ethernet address %pM for VF %d\n", | |
2555 | mac, vf); | |
2556 | return -EINVAL; | |
2557 | } | |
2558 | ||
2559 | dev_info(pi->adapter->pdev_dev, | |
2560 | "Setting MAC %pM on VF %d\n", mac, vf); | |
661dbeb9 HS |
2561 | ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac); |
2562 | if (!ret) | |
2563 | ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac); | |
2564 | return ret; | |
2565 | } | |
2566 | ||
2567 | static int cxgb_get_vf_config(struct net_device *dev, | |
2568 | int vf, struct ifla_vf_info *ivi) | |
2569 | { | |
2570 | struct port_info *pi = netdev_priv(dev); | |
2571 | struct adapter *adap = pi->adapter; | |
2572 | ||
2573 | if (vf >= adap->num_vfs) | |
2574 | return -EINVAL; | |
2575 | ivi->vf = vf; | |
2576 | ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr); | |
2577 | return 0; | |
858aa65c | 2578 | } |
96fe11f2 GG |
2579 | |
2580 | static int cxgb_get_phys_port_id(struct net_device *dev, | |
2581 | struct netdev_phys_item_id *ppid) | |
2582 | { | |
2583 | struct port_info *pi = netdev_priv(dev); | |
2584 | unsigned int phy_port_id; | |
2585 | ||
2586 | phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id; | |
2587 | ppid->id_len = sizeof(phy_port_id); | |
2588 | memcpy(ppid->id, &phy_port_id, ppid->id_len); | |
2589 | return 0; | |
2590 | } | |
2591 | ||
858aa65c HS |
2592 | #endif |
2593 | ||
b8ff05a9 DM |
2594 | static int cxgb_set_mac_addr(struct net_device *dev, void *p) |
2595 | { | |
2596 | int ret; | |
2597 | struct sockaddr *addr = p; | |
2598 | struct port_info *pi = netdev_priv(dev); | |
2599 | ||
2600 | if (!is_valid_ether_addr(addr->sa_data)) | |
504f9b5a | 2601 | return -EADDRNOTAVAIL; |
b8ff05a9 | 2602 | |
b2612722 | 2603 | ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, |
060e0c75 | 2604 | pi->xact_addr_filt, addr->sa_data, true, true); |
b8ff05a9 DM |
2605 | if (ret < 0) |
2606 | return ret; | |
2607 | ||
2608 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
2609 | pi->xact_addr_filt = ret; | |
2610 | return 0; | |
2611 | } | |
2612 | ||
b8ff05a9 DM |
2613 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2614 | static void cxgb_netpoll(struct net_device *dev) | |
2615 | { | |
2616 | struct port_info *pi = netdev_priv(dev); | |
2617 | struct adapter *adap = pi->adapter; | |
2618 | ||
2619 | if (adap->flags & USING_MSIX) { | |
2620 | int i; | |
2621 | struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; | |
2622 | ||
2623 | for (i = pi->nqsets; i; i--, rx++) | |
2624 | t4_sge_intr_msix(0, &rx->rspq); | |
2625 | } else | |
2626 | t4_intr_handler(adap)(0, adap); | |
2627 | } | |
2628 | #endif | |
2629 | ||
10a2604e RL |
2630 | static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate) |
2631 | { | |
2632 | struct port_info *pi = netdev_priv(dev); | |
2633 | struct adapter *adap = pi->adapter; | |
2634 | struct sched_class *e; | |
2635 | struct ch_sched_params p; | |
2636 | struct ch_sched_queue qe; | |
2637 | u32 req_rate; | |
2638 | int err = 0; | |
2639 | ||
2640 | if (!can_sched(dev)) | |
2641 | return -ENOTSUPP; | |
2642 | ||
2643 | if (index < 0 || index > pi->nqsets - 1) | |
2644 | return -EINVAL; | |
2645 | ||
2646 | if (!(adap->flags & FULL_INIT_DONE)) { | |
2647 | dev_err(adap->pdev_dev, | |
2648 | "Failed to rate limit on queue %d. Link Down?\n", | |
2649 | index); | |
2650 | return -EINVAL; | |
2651 | } | |
2652 | ||
2653 | /* Convert from Mbps to Kbps */ | |
2654 | req_rate = rate << 10; | |
2655 | ||
2656 | /* Max rate is 10 Gbps */ | |
2657 | if (req_rate >= SCHED_MAX_RATE_KBPS) { | |
2658 | dev_err(adap->pdev_dev, | |
2659 | "Invalid rate %u Mbps, Max rate is %u Gbps\n", | |
2660 | rate, SCHED_MAX_RATE_KBPS); | |
2661 | return -ERANGE; | |
2662 | } | |
2663 | ||
2664 | /* First unbind the queue from any existing class */ | |
2665 | memset(&qe, 0, sizeof(qe)); | |
2666 | qe.queue = index; | |
2667 | qe.class = SCHED_CLS_NONE; | |
2668 | ||
2669 | err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE); | |
2670 | if (err) { | |
2671 | dev_err(adap->pdev_dev, | |
2672 | "Unbinding Queue %d on port %d fail. Err: %d\n", | |
2673 | index, pi->port_id, err); | |
2674 | return err; | |
2675 | } | |
2676 | ||
2677 | /* Queue already unbound */ | |
2678 | if (!req_rate) | |
2679 | return 0; | |
2680 | ||
2681 | /* Fetch any available unused or matching scheduling class */ | |
2682 | memset(&p, 0, sizeof(p)); | |
2683 | p.type = SCHED_CLASS_TYPE_PACKET; | |
2684 | p.u.params.level = SCHED_CLASS_LEVEL_CL_RL; | |
2685 | p.u.params.mode = SCHED_CLASS_MODE_CLASS; | |
2686 | p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS; | |
2687 | p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS; | |
2688 | p.u.params.channel = pi->tx_chan; | |
2689 | p.u.params.class = SCHED_CLS_NONE; | |
2690 | p.u.params.minrate = 0; | |
2691 | p.u.params.maxrate = req_rate; | |
2692 | p.u.params.weight = 0; | |
2693 | p.u.params.pktsize = dev->mtu; | |
2694 | ||
2695 | e = cxgb4_sched_class_alloc(dev, &p); | |
2696 | if (!e) | |
2697 | return -ENOMEM; | |
2698 | ||
2699 | /* Bind the queue to a scheduling class */ | |
2700 | memset(&qe, 0, sizeof(qe)); | |
2701 | qe.queue = index; | |
2702 | qe.class = e->idx; | |
2703 | ||
2704 | err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE); | |
2705 | if (err) | |
2706 | dev_err(adap->pdev_dev, | |
2707 | "Queue rate limiting failed. Err: %d\n", err); | |
2708 | return err; | |
2709 | } | |
2710 | ||
8efebd6e BX |
2711 | static int cxgb_setup_tc(struct net_device *dev, u32 handle, __be16 proto, |
2712 | struct tc_to_netdev *tc) | |
d8931847 RL |
2713 | { |
2714 | struct port_info *pi = netdev2pinfo(dev); | |
2715 | struct adapter *adap = netdev2adap(dev); | |
2716 | ||
2717 | if (!(adap->flags & FULL_INIT_DONE)) { | |
2718 | dev_err(adap->pdev_dev, | |
2719 | "Failed to setup tc on port %d. Link Down?\n", | |
2720 | pi->port_id); | |
2721 | return -EINVAL; | |
2722 | } | |
2723 | ||
2724 | if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) && | |
2725 | tc->type == TC_SETUP_CLSU32) { | |
2726 | switch (tc->cls_u32->command) { | |
2727 | case TC_CLSU32_NEW_KNODE: | |
2728 | case TC_CLSU32_REPLACE_KNODE: | |
2729 | return cxgb4_config_knode(dev, proto, tc->cls_u32); | |
2730 | case TC_CLSU32_DELETE_KNODE: | |
2731 | return cxgb4_delete_knode(dev, proto, tc->cls_u32); | |
2732 | default: | |
2733 | return -EOPNOTSUPP; | |
2734 | } | |
2735 | } | |
2736 | ||
2737 | return -EOPNOTSUPP; | |
2738 | } | |
2739 | ||
b8ff05a9 DM |
2740 | static const struct net_device_ops cxgb4_netdev_ops = { |
2741 | .ndo_open = cxgb_open, | |
2742 | .ndo_stop = cxgb_close, | |
2743 | .ndo_start_xmit = t4_eth_xmit, | |
688848b1 | 2744 | .ndo_select_queue = cxgb_select_queue, |
9be793bf | 2745 | .ndo_get_stats64 = cxgb_get_stats, |
b8ff05a9 DM |
2746 | .ndo_set_rx_mode = cxgb_set_rxmode, |
2747 | .ndo_set_mac_address = cxgb_set_mac_addr, | |
2ed28baa | 2748 | .ndo_set_features = cxgb_set_features, |
b8ff05a9 DM |
2749 | .ndo_validate_addr = eth_validate_addr, |
2750 | .ndo_do_ioctl = cxgb_ioctl, | |
2751 | .ndo_change_mtu = cxgb_change_mtu, | |
b8ff05a9 DM |
2752 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2753 | .ndo_poll_controller = cxgb_netpoll, | |
2754 | #endif | |
84a200b3 VP |
2755 | #ifdef CONFIG_CHELSIO_T4_FCOE |
2756 | .ndo_fcoe_enable = cxgb_fcoe_enable, | |
2757 | .ndo_fcoe_disable = cxgb_fcoe_disable, | |
2758 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
10a2604e | 2759 | .ndo_set_tx_maxrate = cxgb_set_tx_maxrate, |
d8931847 | 2760 | .ndo_setup_tc = cxgb_setup_tc, |
b8ff05a9 DM |
2761 | }; |
2762 | ||
858aa65c | 2763 | #ifdef CONFIG_PCI_IOV |
e7b48a32 HS |
2764 | static const struct net_device_ops cxgb4_mgmt_netdev_ops = { |
2765 | .ndo_open = dummy_open, | |
858aa65c | 2766 | .ndo_set_vf_mac = cxgb_set_vf_mac, |
661dbeb9 | 2767 | .ndo_get_vf_config = cxgb_get_vf_config, |
96fe11f2 | 2768 | .ndo_get_phys_port_id = cxgb_get_phys_port_id, |
7829451c | 2769 | }; |
e7b48a32 | 2770 | #endif |
7829451c HS |
2771 | |
2772 | static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
2773 | { | |
2774 | struct adapter *adapter = netdev2adap(dev); | |
2775 | ||
2776 | strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver)); | |
2777 | strlcpy(info->version, cxgb4_driver_version, | |
2778 | sizeof(info->version)); | |
2779 | strlcpy(info->bus_info, pci_name(adapter->pdev), | |
2780 | sizeof(info->bus_info)); | |
2781 | } | |
2782 | ||
2783 | static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = { | |
2784 | .get_drvinfo = get_drvinfo, | |
2785 | }; | |
2786 | ||
b8ff05a9 DM |
2787 | void t4_fatal_err(struct adapter *adap) |
2788 | { | |
3be0679b HS |
2789 | int port; |
2790 | ||
2791 | /* Disable the SGE since ULDs are going to free resources that | |
2792 | * could be exposed to the adapter. RDMA MWs for example... | |
2793 | */ | |
2794 | t4_shutdown_adapter(adap); | |
2795 | for_each_port(adap, port) { | |
2796 | struct net_device *dev = adap->port[port]; | |
2797 | ||
2798 | /* If we get here in very early initialization the network | |
2799 | * devices may not have been set up yet. | |
2800 | */ | |
2801 | if (!dev) | |
2802 | continue; | |
2803 | ||
2804 | netif_tx_stop_all_queues(dev); | |
2805 | netif_carrier_off(dev); | |
2806 | } | |
b8ff05a9 DM |
2807 | dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); |
2808 | } | |
2809 | ||
2810 | static void setup_memwin(struct adapter *adap) | |
2811 | { | |
b562fc37 | 2812 | u32 nic_win_base = t4_get_util_window(adap); |
b8ff05a9 | 2813 | |
b562fc37 | 2814 | t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); |
636f9d37 VP |
2815 | } |
2816 | ||
2817 | static void setup_memwin_rdma(struct adapter *adap) | |
2818 | { | |
1ae970e0 | 2819 | if (adap->vres.ocq.size) { |
0abfd152 HS |
2820 | u32 start; |
2821 | unsigned int sz_kb; | |
1ae970e0 | 2822 | |
0abfd152 HS |
2823 | start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); |
2824 | start &= PCI_BASE_ADDRESS_MEM_MASK; | |
2825 | start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); | |
1ae970e0 DM |
2826 | sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; |
2827 | t4_write_reg(adap, | |
f061de42 HS |
2828 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), |
2829 | start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); | |
1ae970e0 | 2830 | t4_write_reg(adap, |
f061de42 | 2831 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), |
1ae970e0 DM |
2832 | adap->vres.ocq.start); |
2833 | t4_read_reg(adap, | |
f061de42 | 2834 | PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); |
1ae970e0 | 2835 | } |
b8ff05a9 DM |
2836 | } |
2837 | ||
02b5fb8e DM |
2838 | static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) |
2839 | { | |
2840 | u32 v; | |
2841 | int ret; | |
2842 | ||
2843 | /* get device capabilities */ | |
2844 | memset(c, 0, sizeof(*c)); | |
e2ac9628 HS |
2845 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
2846 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 2847 | c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); |
b2612722 | 2848 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); |
02b5fb8e DM |
2849 | if (ret < 0) |
2850 | return ret; | |
2851 | ||
e2ac9628 HS |
2852 | c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
2853 | FW_CMD_REQUEST_F | FW_CMD_WRITE_F); | |
b2612722 | 2854 | ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); |
02b5fb8e DM |
2855 | if (ret < 0) |
2856 | return ret; | |
2857 | ||
b2612722 | 2858 | ret = t4_config_glbl_rss(adap, adap->pf, |
02b5fb8e | 2859 | FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, |
b2e1a3f0 HS |
2860 | FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | |
2861 | FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); | |
02b5fb8e DM |
2862 | if (ret < 0) |
2863 | return ret; | |
2864 | ||
b2612722 | 2865 | ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, |
4b8e27a8 HS |
2866 | MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, |
2867 | FW_CMD_CAP_PF); | |
02b5fb8e DM |
2868 | if (ret < 0) |
2869 | return ret; | |
2870 | ||
2871 | t4_sge_init(adap); | |
2872 | ||
02b5fb8e | 2873 | /* tweak some settings */ |
837e4a42 | 2874 | t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); |
0d804338 | 2875 | t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); |
837e4a42 HS |
2876 | t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); |
2877 | v = t4_read_reg(adap, TP_PIO_DATA_A); | |
2878 | t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); | |
060e0c75 | 2879 | |
dca4faeb VP |
2880 | /* first 4 Tx modulation queues point to consecutive Tx channels */ |
2881 | adap->params.tp.tx_modq_map = 0xE4; | |
0d804338 HS |
2882 | t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, |
2883 | TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); | |
dca4faeb VP |
2884 | |
2885 | /* associate each Tx modulation queue with consecutive Tx channels */ | |
2886 | v = 0x84218421; | |
837e4a42 | 2887 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 2888 | &v, 1, TP_TX_SCHED_HDR_A); |
837e4a42 | 2889 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 2890 | &v, 1, TP_TX_SCHED_FIFO_A); |
837e4a42 | 2891 | t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, |
0d804338 | 2892 | &v, 1, TP_TX_SCHED_PCMD_A); |
dca4faeb VP |
2893 | |
2894 | #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ | |
2895 | if (is_offload(adap)) { | |
0d804338 HS |
2896 | t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, |
2897 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
2898 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
2899 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
2900 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
2901 | t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, | |
2902 | TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
2903 | TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
2904 | TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | | |
2905 | TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); | |
dca4faeb VP |
2906 | } |
2907 | ||
060e0c75 | 2908 | /* get basic stuff going */ |
b2612722 | 2909 | return t4_early_init(adap, adap->pf); |
02b5fb8e DM |
2910 | } |
2911 | ||
b8ff05a9 DM |
2912 | /* |
2913 | * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. | |
2914 | */ | |
2915 | #define MAX_ATIDS 8192U | |
2916 | ||
636f9d37 VP |
2917 | /* |
2918 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
2919 | * | |
2920 | * If the firmware we're dealing with has Configuration File support, then | |
2921 | * we use that to perform all configuration | |
2922 | */ | |
2923 | ||
2924 | /* | |
2925 | * Tweak configuration based on module parameters, etc. Most of these have | |
2926 | * defaults assigned to them by Firmware Configuration Files (if we're using | |
2927 | * them) but need to be explicitly set if we're using hard-coded | |
2928 | * initialization. But even in the case of using Firmware Configuration | |
2929 | * Files, we'd like to expose the ability to change these via module | |
2930 | * parameters so these are essentially common tweaks/settings for | |
2931 | * Configuration Files and hard-coded initialization ... | |
2932 | */ | |
2933 | static int adap_init0_tweaks(struct adapter *adapter) | |
2934 | { | |
2935 | /* | |
2936 | * Fix up various Host-Dependent Parameters like Page Size, Cache | |
2937 | * Line Size, etc. The firmware default is for a 4KB Page Size and | |
2938 | * 64B Cache Line Size ... | |
2939 | */ | |
2940 | t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); | |
2941 | ||
2942 | /* | |
2943 | * Process module parameters which affect early initialization. | |
2944 | */ | |
2945 | if (rx_dma_offset != 2 && rx_dma_offset != 0) { | |
2946 | dev_err(&adapter->pdev->dev, | |
2947 | "Ignoring illegal rx_dma_offset=%d, using 2\n", | |
2948 | rx_dma_offset); | |
2949 | rx_dma_offset = 2; | |
2950 | } | |
f612b815 HS |
2951 | t4_set_reg_field(adapter, SGE_CONTROL_A, |
2952 | PKTSHIFT_V(PKTSHIFT_M), | |
2953 | PKTSHIFT_V(rx_dma_offset)); | |
636f9d37 VP |
2954 | |
2955 | /* | |
2956 | * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux | |
2957 | * adds the pseudo header itself. | |
2958 | */ | |
837e4a42 HS |
2959 | t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, |
2960 | CSUM_HAS_PSEUDO_HDR_F, 0); | |
636f9d37 VP |
2961 | |
2962 | return 0; | |
2963 | } | |
2964 | ||
01b69614 HS |
2965 | /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips |
2966 | * unto themselves and they contain their own firmware to perform their | |
2967 | * tasks ... | |
2968 | */ | |
2969 | static int phy_aq1202_version(const u8 *phy_fw_data, | |
2970 | size_t phy_fw_size) | |
2971 | { | |
2972 | int offset; | |
2973 | ||
2974 | /* At offset 0x8 you're looking for the primary image's | |
2975 | * starting offset which is 3 Bytes wide | |
2976 | * | |
2977 | * At offset 0xa of the primary image, you look for the offset | |
2978 | * of the DRAM segment which is 3 Bytes wide. | |
2979 | * | |
2980 | * The FW version is at offset 0x27e of the DRAM and is 2 Bytes | |
2981 | * wide | |
2982 | */ | |
2983 | #define be16(__p) (((__p)[0] << 8) | (__p)[1]) | |
2984 | #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) | |
2985 | #define le24(__p) (le16(__p) | ((__p)[2] << 16)) | |
2986 | ||
2987 | offset = le24(phy_fw_data + 0x8) << 12; | |
2988 | offset = le24(phy_fw_data + offset + 0xa); | |
2989 | return be16(phy_fw_data + offset + 0x27e); | |
2990 | ||
2991 | #undef be16 | |
2992 | #undef le16 | |
2993 | #undef le24 | |
2994 | } | |
2995 | ||
2996 | static struct info_10gbt_phy_fw { | |
2997 | unsigned int phy_fw_id; /* PCI Device ID */ | |
2998 | char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ | |
2999 | int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); | |
3000 | int phy_flash; /* Has FLASH for PHY Firmware */ | |
3001 | } phy_info_array[] = { | |
3002 | { | |
3003 | PHY_AQ1202_DEVICEID, | |
3004 | PHY_AQ1202_FIRMWARE, | |
3005 | phy_aq1202_version, | |
3006 | 1, | |
3007 | }, | |
3008 | { | |
3009 | PHY_BCM84834_DEVICEID, | |
3010 | PHY_BCM84834_FIRMWARE, | |
3011 | NULL, | |
3012 | 0, | |
3013 | }, | |
3014 | { 0, NULL, NULL }, | |
3015 | }; | |
3016 | ||
3017 | static struct info_10gbt_phy_fw *find_phy_info(int devid) | |
3018 | { | |
3019 | int i; | |
3020 | ||
3021 | for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { | |
3022 | if (phy_info_array[i].phy_fw_id == devid) | |
3023 | return &phy_info_array[i]; | |
3024 | } | |
3025 | return NULL; | |
3026 | } | |
3027 | ||
3028 | /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to | |
3029 | * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error | |
3030 | * we return a negative error number. If we transfer new firmware we return 1 | |
3031 | * (from t4_load_phy_fw()). If we don't do anything we return 0. | |
3032 | */ | |
3033 | static int adap_init0_phy(struct adapter *adap) | |
3034 | { | |
3035 | const struct firmware *phyf; | |
3036 | int ret; | |
3037 | struct info_10gbt_phy_fw *phy_info; | |
3038 | ||
3039 | /* Use the device ID to determine which PHY file to flash. | |
3040 | */ | |
3041 | phy_info = find_phy_info(adap->pdev->device); | |
3042 | if (!phy_info) { | |
3043 | dev_warn(adap->pdev_dev, | |
3044 | "No PHY Firmware file found for this PHY\n"); | |
3045 | return -EOPNOTSUPP; | |
3046 | } | |
3047 | ||
3048 | /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then | |
3049 | * use that. The adapter firmware provides us with a memory buffer | |
3050 | * where we can load a PHY firmware file from the host if we want to | |
3051 | * override the PHY firmware File in flash. | |
3052 | */ | |
3053 | ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, | |
3054 | adap->pdev_dev); | |
3055 | if (ret < 0) { | |
3056 | /* For adapters without FLASH attached to PHY for their | |
3057 | * firmware, it's obviously a fatal error if we can't get the | |
3058 | * firmware to the adapter. For adapters with PHY firmware | |
3059 | * FLASH storage, it's worth a warning if we can't find the | |
3060 | * PHY Firmware but we'll neuter the error ... | |
3061 | */ | |
3062 | dev_err(adap->pdev_dev, "unable to find PHY Firmware image " | |
3063 | "/lib/firmware/%s, error %d\n", | |
3064 | phy_info->phy_fw_file, -ret); | |
3065 | if (phy_info->phy_flash) { | |
3066 | int cur_phy_fw_ver = 0; | |
3067 | ||
3068 | t4_phy_fw_ver(adap, &cur_phy_fw_ver); | |
3069 | dev_warn(adap->pdev_dev, "continuing with, on-adapter " | |
3070 | "FLASH copy, version %#x\n", cur_phy_fw_ver); | |
3071 | ret = 0; | |
3072 | } | |
3073 | ||
3074 | return ret; | |
3075 | } | |
3076 | ||
3077 | /* Load PHY Firmware onto adapter. | |
3078 | */ | |
3079 | ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, | |
3080 | phy_info->phy_fw_version, | |
3081 | (u8 *)phyf->data, phyf->size); | |
3082 | if (ret < 0) | |
3083 | dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", | |
3084 | -ret); | |
3085 | else if (ret > 0) { | |
3086 | int new_phy_fw_ver = 0; | |
3087 | ||
3088 | if (phy_info->phy_fw_version) | |
3089 | new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, | |
3090 | phyf->size); | |
3091 | dev_info(adap->pdev_dev, "Successfully transferred PHY " | |
3092 | "Firmware /lib/firmware/%s, version %#x\n", | |
3093 | phy_info->phy_fw_file, new_phy_fw_ver); | |
3094 | } | |
3095 | ||
3096 | release_firmware(phyf); | |
3097 | ||
3098 | return ret; | |
3099 | } | |
3100 | ||
636f9d37 VP |
3101 | /* |
3102 | * Attempt to initialize the adapter via a Firmware Configuration File. | |
3103 | */ | |
3104 | static int adap_init0_config(struct adapter *adapter, int reset) | |
3105 | { | |
3106 | struct fw_caps_config_cmd caps_cmd; | |
3107 | const struct firmware *cf; | |
3108 | unsigned long mtype = 0, maddr = 0; | |
3109 | u32 finiver, finicsum, cfcsum; | |
16e47624 HS |
3110 | int ret; |
3111 | int config_issued = 0; | |
0a57a536 | 3112 | char *fw_config_file, fw_config_file_path[256]; |
16e47624 | 3113 | char *config_name = NULL; |
636f9d37 VP |
3114 | |
3115 | /* | |
3116 | * Reset device if necessary. | |
3117 | */ | |
3118 | if (reset) { | |
3119 | ret = t4_fw_reset(adapter, adapter->mbox, | |
0d804338 | 3120 | PIORSTMODE_F | PIORST_F); |
636f9d37 VP |
3121 | if (ret < 0) |
3122 | goto bye; | |
3123 | } | |
3124 | ||
01b69614 HS |
3125 | /* If this is a 10Gb/s-BT adapter make sure the chip-external |
3126 | * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs | |
3127 | * to be performed after any global adapter RESET above since some | |
3128 | * PHYs only have local RAM copies of the PHY firmware. | |
3129 | */ | |
3130 | if (is_10gbt_device(adapter->pdev->device)) { | |
3131 | ret = adap_init0_phy(adapter); | |
3132 | if (ret < 0) | |
3133 | goto bye; | |
3134 | } | |
636f9d37 VP |
3135 | /* |
3136 | * If we have a T4 configuration file under /lib/firmware/cxgb4/, | |
3137 | * then use that. Otherwise, use the configuration file stored | |
3138 | * in the adapter flash ... | |
3139 | */ | |
d14807dd | 3140 | switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { |
0a57a536 | 3141 | case CHELSIO_T4: |
16e47624 | 3142 | fw_config_file = FW4_CFNAME; |
0a57a536 SR |
3143 | break; |
3144 | case CHELSIO_T5: | |
3145 | fw_config_file = FW5_CFNAME; | |
3146 | break; | |
3ccc6cf7 HS |
3147 | case CHELSIO_T6: |
3148 | fw_config_file = FW6_CFNAME; | |
3149 | break; | |
0a57a536 SR |
3150 | default: |
3151 | dev_err(adapter->pdev_dev, "Device %d is not supported\n", | |
3152 | adapter->pdev->device); | |
3153 | ret = -EINVAL; | |
3154 | goto bye; | |
3155 | } | |
3156 | ||
3157 | ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); | |
636f9d37 | 3158 | if (ret < 0) { |
16e47624 | 3159 | config_name = "On FLASH"; |
636f9d37 VP |
3160 | mtype = FW_MEMTYPE_CF_FLASH; |
3161 | maddr = t4_flash_cfg_addr(adapter); | |
3162 | } else { | |
3163 | u32 params[7], val[7]; | |
3164 | ||
16e47624 HS |
3165 | sprintf(fw_config_file_path, |
3166 | "/lib/firmware/%s", fw_config_file); | |
3167 | config_name = fw_config_file_path; | |
3168 | ||
636f9d37 VP |
3169 | if (cf->size >= FLASH_CFG_MAX_SIZE) |
3170 | ret = -ENOMEM; | |
3171 | else { | |
5167865a HS |
3172 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3173 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
636f9d37 | 3174 | ret = t4_query_params(adapter, adapter->mbox, |
b2612722 | 3175 | adapter->pf, 0, 1, params, val); |
636f9d37 VP |
3176 | if (ret == 0) { |
3177 | /* | |
fc5ab020 | 3178 | * For t4_memory_rw() below addresses and |
636f9d37 VP |
3179 | * sizes have to be in terms of multiples of 4 |
3180 | * bytes. So, if the Configuration File isn't | |
3181 | * a multiple of 4 bytes in length we'll have | |
3182 | * to write that out separately since we can't | |
3183 | * guarantee that the bytes following the | |
3184 | * residual byte in the buffer returned by | |
3185 | * request_firmware() are zeroed out ... | |
3186 | */ | |
3187 | size_t resid = cf->size & 0x3; | |
3188 | size_t size = cf->size & ~0x3; | |
3189 | __be32 *data = (__be32 *)cf->data; | |
3190 | ||
5167865a HS |
3191 | mtype = FW_PARAMS_PARAM_Y_G(val[0]); |
3192 | maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; | |
636f9d37 | 3193 | |
fc5ab020 HS |
3194 | spin_lock(&adapter->win0_lock); |
3195 | ret = t4_memory_rw(adapter, 0, mtype, maddr, | |
3196 | size, data, T4_MEMORY_WRITE); | |
636f9d37 VP |
3197 | if (ret == 0 && resid != 0) { |
3198 | union { | |
3199 | __be32 word; | |
3200 | char buf[4]; | |
3201 | } last; | |
3202 | int i; | |
3203 | ||
3204 | last.word = data[size >> 2]; | |
3205 | for (i = resid; i < 4; i++) | |
3206 | last.buf[i] = 0; | |
fc5ab020 HS |
3207 | ret = t4_memory_rw(adapter, 0, mtype, |
3208 | maddr + size, | |
3209 | 4, &last.word, | |
3210 | T4_MEMORY_WRITE); | |
636f9d37 | 3211 | } |
fc5ab020 | 3212 | spin_unlock(&adapter->win0_lock); |
636f9d37 VP |
3213 | } |
3214 | } | |
3215 | ||
3216 | release_firmware(cf); | |
3217 | if (ret) | |
3218 | goto bye; | |
3219 | } | |
3220 | ||
3221 | /* | |
3222 | * Issue a Capability Configuration command to the firmware to get it | |
3223 | * to parse the Configuration File. We don't use t4_fw_config_file() | |
3224 | * because we want the ability to modify various features after we've | |
3225 | * processed the configuration file ... | |
3226 | */ | |
3227 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3228 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3229 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3230 | FW_CMD_REQUEST_F | | |
3231 | FW_CMD_READ_F); | |
ce91a923 | 3232 | caps_cmd.cfvalid_to_len16 = |
5167865a HS |
3233 | htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | |
3234 | FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | | |
3235 | FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | | |
636f9d37 VP |
3236 | FW_LEN16(caps_cmd)); |
3237 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), | |
3238 | &caps_cmd); | |
16e47624 HS |
3239 | |
3240 | /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware | |
3241 | * Configuration File in FLASH), our last gasp effort is to use the | |
3242 | * Firmware Configuration File which is embedded in the firmware. A | |
3243 | * very few early versions of the firmware didn't have one embedded | |
3244 | * but we can ignore those. | |
3245 | */ | |
3246 | if (ret == -ENOENT) { | |
3247 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
3248 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3249 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3250 | FW_CMD_REQUEST_F | | |
3251 | FW_CMD_READ_F); | |
16e47624 HS |
3252 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
3253 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, | |
3254 | sizeof(caps_cmd), &caps_cmd); | |
3255 | config_name = "Firmware Default"; | |
3256 | } | |
3257 | ||
3258 | config_issued = 1; | |
636f9d37 VP |
3259 | if (ret < 0) |
3260 | goto bye; | |
3261 | ||
3262 | finiver = ntohl(caps_cmd.finiver); | |
3263 | finicsum = ntohl(caps_cmd.finicsum); | |
3264 | cfcsum = ntohl(caps_cmd.cfcsum); | |
3265 | if (finicsum != cfcsum) | |
3266 | dev_warn(adapter->pdev_dev, "Configuration File checksum "\ | |
3267 | "mismatch: [fini] csum=%#x, computed csum=%#x\n", | |
3268 | finicsum, cfcsum); | |
3269 | ||
636f9d37 VP |
3270 | /* |
3271 | * And now tell the firmware to use the configuration we just loaded. | |
3272 | */ | |
3273 | caps_cmd.op_to_write = | |
e2ac9628 HS |
3274 | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3275 | FW_CMD_REQUEST_F | | |
3276 | FW_CMD_WRITE_F); | |
ce91a923 | 3277 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
3278 | ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), |
3279 | NULL); | |
3280 | if (ret < 0) | |
3281 | goto bye; | |
3282 | ||
3283 | /* | |
3284 | * Tweak configuration based on system architecture, module | |
3285 | * parameters, etc. | |
3286 | */ | |
3287 | ret = adap_init0_tweaks(adapter); | |
3288 | if (ret < 0) | |
3289 | goto bye; | |
3290 | ||
3291 | /* | |
3292 | * And finally tell the firmware to initialize itself using the | |
3293 | * parameters from the Configuration File. | |
3294 | */ | |
3295 | ret = t4_fw_initialize(adapter, adapter->mbox); | |
3296 | if (ret < 0) | |
3297 | goto bye; | |
3298 | ||
06640310 HS |
3299 | /* Emit Firmware Configuration File information and return |
3300 | * successfully. | |
636f9d37 | 3301 | */ |
636f9d37 | 3302 | dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ |
16e47624 HS |
3303 | "Configuration File \"%s\", version %#x, computed checksum %#x\n", |
3304 | config_name, finiver, cfcsum); | |
636f9d37 VP |
3305 | return 0; |
3306 | ||
3307 | /* | |
3308 | * Something bad happened. Return the error ... (If the "error" | |
3309 | * is that there's no Configuration File on the adapter we don't | |
3310 | * want to issue a warning since this is fairly common.) | |
3311 | */ | |
3312 | bye: | |
16e47624 HS |
3313 | if (config_issued && ret != -ENOENT) |
3314 | dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", | |
3315 | config_name, -ret); | |
636f9d37 VP |
3316 | return ret; |
3317 | } | |
3318 | ||
16e47624 HS |
3319 | static struct fw_info fw_info_array[] = { |
3320 | { | |
3321 | .chip = CHELSIO_T4, | |
3322 | .fs_name = FW4_CFNAME, | |
3323 | .fw_mod_name = FW4_FNAME, | |
3324 | .fw_hdr = { | |
3325 | .chip = FW_HDR_CHIP_T4, | |
3326 | .fw_ver = __cpu_to_be32(FW_VERSION(T4)), | |
3327 | .intfver_nic = FW_INTFVER(T4, NIC), | |
3328 | .intfver_vnic = FW_INTFVER(T4, VNIC), | |
3329 | .intfver_ri = FW_INTFVER(T4, RI), | |
3330 | .intfver_iscsi = FW_INTFVER(T4, ISCSI), | |
3331 | .intfver_fcoe = FW_INTFVER(T4, FCOE), | |
3332 | }, | |
3333 | }, { | |
3334 | .chip = CHELSIO_T5, | |
3335 | .fs_name = FW5_CFNAME, | |
3336 | .fw_mod_name = FW5_FNAME, | |
3337 | .fw_hdr = { | |
3338 | .chip = FW_HDR_CHIP_T5, | |
3339 | .fw_ver = __cpu_to_be32(FW_VERSION(T5)), | |
3340 | .intfver_nic = FW_INTFVER(T5, NIC), | |
3341 | .intfver_vnic = FW_INTFVER(T5, VNIC), | |
3342 | .intfver_ri = FW_INTFVER(T5, RI), | |
3343 | .intfver_iscsi = FW_INTFVER(T5, ISCSI), | |
3344 | .intfver_fcoe = FW_INTFVER(T5, FCOE), | |
3345 | }, | |
3ccc6cf7 HS |
3346 | }, { |
3347 | .chip = CHELSIO_T6, | |
3348 | .fs_name = FW6_CFNAME, | |
3349 | .fw_mod_name = FW6_FNAME, | |
3350 | .fw_hdr = { | |
3351 | .chip = FW_HDR_CHIP_T6, | |
3352 | .fw_ver = __cpu_to_be32(FW_VERSION(T6)), | |
3353 | .intfver_nic = FW_INTFVER(T6, NIC), | |
3354 | .intfver_vnic = FW_INTFVER(T6, VNIC), | |
3355 | .intfver_ofld = FW_INTFVER(T6, OFLD), | |
3356 | .intfver_ri = FW_INTFVER(T6, RI), | |
3357 | .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), | |
3358 | .intfver_iscsi = FW_INTFVER(T6, ISCSI), | |
3359 | .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), | |
3360 | .intfver_fcoe = FW_INTFVER(T6, FCOE), | |
3361 | }, | |
16e47624 | 3362 | } |
3ccc6cf7 | 3363 | |
16e47624 HS |
3364 | }; |
3365 | ||
3366 | static struct fw_info *find_fw_info(int chip) | |
3367 | { | |
3368 | int i; | |
3369 | ||
3370 | for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { | |
3371 | if (fw_info_array[i].chip == chip) | |
3372 | return &fw_info_array[i]; | |
3373 | } | |
3374 | return NULL; | |
3375 | } | |
3376 | ||
b8ff05a9 DM |
3377 | /* |
3378 | * Phase 0 of initialization: contact FW, obtain config, perform basic init. | |
3379 | */ | |
3380 | static int adap_init0(struct adapter *adap) | |
3381 | { | |
3382 | int ret; | |
3383 | u32 v, port_vec; | |
3384 | enum dev_state state; | |
3385 | u32 params[7], val[7]; | |
9a4da2cd | 3386 | struct fw_caps_config_cmd caps_cmd; |
dcf7b6f5 | 3387 | int reset = 1; |
b8ff05a9 | 3388 | |
ae469b68 HS |
3389 | /* Grab Firmware Device Log parameters as early as possible so we have |
3390 | * access to it for debugging, etc. | |
3391 | */ | |
3392 | ret = t4_init_devlog_params(adap); | |
3393 | if (ret < 0) | |
3394 | return ret; | |
3395 | ||
666224d4 | 3396 | /* Contact FW, advertising Master capability */ |
c5a8c0f3 HS |
3397 | ret = t4_fw_hello(adap, adap->mbox, adap->mbox, |
3398 | is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); | |
b8ff05a9 DM |
3399 | if (ret < 0) { |
3400 | dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", | |
3401 | ret); | |
3402 | return ret; | |
3403 | } | |
636f9d37 VP |
3404 | if (ret == adap->mbox) |
3405 | adap->flags |= MASTER_PF; | |
b8ff05a9 | 3406 | |
636f9d37 VP |
3407 | /* |
3408 | * If we're the Master PF Driver and the device is uninitialized, | |
3409 | * then let's consider upgrading the firmware ... (We always want | |
3410 | * to check the firmware version number in order to A. get it for | |
3411 | * later reporting and B. to warn if the currently loaded firmware | |
3412 | * is excessively mismatched relative to the driver.) | |
3413 | */ | |
16e47624 | 3414 | t4_get_fw_version(adap, &adap->params.fw_vers); |
0de72738 | 3415 | t4_get_bs_version(adap, &adap->params.bs_vers); |
16e47624 | 3416 | t4_get_tp_version(adap, &adap->params.tp_vers); |
0de72738 HS |
3417 | t4_get_exprom_version(adap, &adap->params.er_vers); |
3418 | ||
a69265e9 HS |
3419 | ret = t4_check_fw_version(adap); |
3420 | /* If firmware is too old (not supported by driver) force an update. */ | |
21d11bd6 | 3421 | if (ret) |
a69265e9 | 3422 | state = DEV_STATE_UNINIT; |
636f9d37 | 3423 | if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { |
16e47624 HS |
3424 | struct fw_info *fw_info; |
3425 | struct fw_hdr *card_fw; | |
3426 | const struct firmware *fw; | |
3427 | const u8 *fw_data = NULL; | |
3428 | unsigned int fw_size = 0; | |
3429 | ||
3430 | /* This is the firmware whose headers the driver was compiled | |
3431 | * against | |
3432 | */ | |
3433 | fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); | |
3434 | if (fw_info == NULL) { | |
3435 | dev_err(adap->pdev_dev, | |
3436 | "unable to get firmware info for chip %d.\n", | |
3437 | CHELSIO_CHIP_VERSION(adap->params.chip)); | |
3438 | return -EINVAL; | |
636f9d37 | 3439 | } |
16e47624 HS |
3440 | |
3441 | /* allocate memory to read the header of the firmware on the | |
3442 | * card | |
3443 | */ | |
3444 | card_fw = t4_alloc_mem(sizeof(*card_fw)); | |
3445 | ||
3446 | /* Get FW from from /lib/firmware/ */ | |
3447 | ret = request_firmware(&fw, fw_info->fw_mod_name, | |
3448 | adap->pdev_dev); | |
3449 | if (ret < 0) { | |
3450 | dev_err(adap->pdev_dev, | |
3451 | "unable to load firmware image %s, error %d\n", | |
3452 | fw_info->fw_mod_name, ret); | |
3453 | } else { | |
3454 | fw_data = fw->data; | |
3455 | fw_size = fw->size; | |
3456 | } | |
3457 | ||
3458 | /* upgrade FW logic */ | |
3459 | ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, | |
3460 | state, &reset); | |
3461 | ||
3462 | /* Cleaning up */ | |
0b5b6bee | 3463 | release_firmware(fw); |
16e47624 HS |
3464 | t4_free_mem(card_fw); |
3465 | ||
636f9d37 | 3466 | if (ret < 0) |
16e47624 | 3467 | goto bye; |
636f9d37 | 3468 | } |
b8ff05a9 | 3469 | |
636f9d37 VP |
3470 | /* |
3471 | * Grab VPD parameters. This should be done after we establish a | |
3472 | * connection to the firmware since some of the VPD parameters | |
3473 | * (notably the Core Clock frequency) are retrieved via requests to | |
3474 | * the firmware. On the other hand, we need these fairly early on | |
3475 | * so we do this right after getting ahold of the firmware. | |
3476 | */ | |
098ef6c2 | 3477 | ret = t4_get_vpd_params(adap, &adap->params.vpd); |
a0881cab DM |
3478 | if (ret < 0) |
3479 | goto bye; | |
a0881cab | 3480 | |
636f9d37 | 3481 | /* |
13ee15d3 VP |
3482 | * Find out what ports are available to us. Note that we need to do |
3483 | * this before calling adap_init0_no_config() since it needs nports | |
3484 | * and portvec ... | |
636f9d37 VP |
3485 | */ |
3486 | v = | |
5167865a HS |
3487 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3488 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); | |
b2612722 | 3489 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); |
a0881cab DM |
3490 | if (ret < 0) |
3491 | goto bye; | |
3492 | ||
636f9d37 VP |
3493 | adap->params.nports = hweight32(port_vec); |
3494 | adap->params.portvec = port_vec; | |
3495 | ||
06640310 HS |
3496 | /* If the firmware is initialized already, emit a simply note to that |
3497 | * effect. Otherwise, it's time to try initializing the adapter. | |
636f9d37 VP |
3498 | */ |
3499 | if (state == DEV_STATE_INIT) { | |
3500 | dev_info(adap->pdev_dev, "Coming up as %s: "\ | |
3501 | "Adapter already initialized\n", | |
3502 | adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); | |
636f9d37 VP |
3503 | } else { |
3504 | dev_info(adap->pdev_dev, "Coming up as MASTER: "\ | |
3505 | "Initializing adapter\n"); | |
06640310 HS |
3506 | |
3507 | /* Find out whether we're dealing with a version of the | |
3508 | * firmware which has configuration file support. | |
636f9d37 | 3509 | */ |
06640310 HS |
3510 | params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | |
3511 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); | |
b2612722 | 3512 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, |
06640310 | 3513 | params, val); |
13ee15d3 | 3514 | |
06640310 HS |
3515 | /* If the firmware doesn't support Configuration Files, |
3516 | * return an error. | |
3517 | */ | |
3518 | if (ret < 0) { | |
3519 | dev_err(adap->pdev_dev, "firmware doesn't support " | |
3520 | "Firmware Configuration Files\n"); | |
3521 | goto bye; | |
3522 | } | |
3523 | ||
3524 | /* The firmware provides us with a memory buffer where we can | |
3525 | * load a Configuration File from the host if we want to | |
3526 | * override the Configuration File in flash. | |
3527 | */ | |
3528 | ret = adap_init0_config(adap, reset); | |
3529 | if (ret == -ENOENT) { | |
3530 | dev_err(adap->pdev_dev, "no Configuration File " | |
3531 | "present on adapter.\n"); | |
3532 | goto bye; | |
636f9d37 VP |
3533 | } |
3534 | if (ret < 0) { | |
06640310 HS |
3535 | dev_err(adap->pdev_dev, "could not initialize " |
3536 | "adapter, error %d\n", -ret); | |
636f9d37 VP |
3537 | goto bye; |
3538 | } | |
3539 | } | |
3540 | ||
06640310 HS |
3541 | /* Give the SGE code a chance to pull in anything that it needs ... |
3542 | * Note that this must be called after we retrieve our VPD parameters | |
3543 | * in order to know how to convert core ticks to seconds, etc. | |
636f9d37 | 3544 | */ |
06640310 HS |
3545 | ret = t4_sge_init(adap); |
3546 | if (ret < 0) | |
3547 | goto bye; | |
636f9d37 | 3548 | |
9a4da2cd VP |
3549 | if (is_bypass_device(adap->pdev->device)) |
3550 | adap->params.bypass = 1; | |
3551 | ||
636f9d37 VP |
3552 | /* |
3553 | * Grab some of our basic fundamental operating parameters. | |
3554 | */ | |
3555 | #define FW_PARAM_DEV(param) \ | |
5167865a HS |
3556 | (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ |
3557 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) | |
636f9d37 | 3558 | |
b8ff05a9 | 3559 | #define FW_PARAM_PFVF(param) \ |
5167865a HS |
3560 | FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ |
3561 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ | |
3562 | FW_PARAMS_PARAM_Y_V(0) | \ | |
3563 | FW_PARAMS_PARAM_Z_V(0) | |
b8ff05a9 | 3564 | |
636f9d37 | 3565 | params[0] = FW_PARAM_PFVF(EQ_START); |
b8ff05a9 DM |
3566 | params[1] = FW_PARAM_PFVF(L2T_START); |
3567 | params[2] = FW_PARAM_PFVF(L2T_END); | |
3568 | params[3] = FW_PARAM_PFVF(FILTER_START); | |
3569 | params[4] = FW_PARAM_PFVF(FILTER_END); | |
e46dab4d | 3570 | params[5] = FW_PARAM_PFVF(IQFLINT_START); |
b2612722 | 3571 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); |
b8ff05a9 DM |
3572 | if (ret < 0) |
3573 | goto bye; | |
636f9d37 VP |
3574 | adap->sge.egr_start = val[0]; |
3575 | adap->l2t_start = val[1]; | |
3576 | adap->l2t_end = val[2]; | |
b8ff05a9 DM |
3577 | adap->tids.ftid_base = val[3]; |
3578 | adap->tids.nftids = val[4] - val[3] + 1; | |
e46dab4d | 3579 | adap->sge.ingr_start = val[5]; |
b8ff05a9 | 3580 | |
4b8e27a8 HS |
3581 | /* qids (ingress/egress) returned from firmware can be anywhere |
3582 | * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. | |
3583 | * Hence driver needs to allocate memory for this range to | |
3584 | * store the queue info. Get the highest IQFLINT/EQ index returned | |
3585 | * in FW_EQ_*_CMD.alloc command. | |
3586 | */ | |
3587 | params[0] = FW_PARAM_PFVF(EQ_END); | |
3588 | params[1] = FW_PARAM_PFVF(IQFLINT_END); | |
b2612722 | 3589 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
4b8e27a8 HS |
3590 | if (ret < 0) |
3591 | goto bye; | |
3592 | adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; | |
3593 | adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; | |
3594 | ||
3595 | adap->sge.egr_map = kcalloc(adap->sge.egr_sz, | |
3596 | sizeof(*adap->sge.egr_map), GFP_KERNEL); | |
3597 | if (!adap->sge.egr_map) { | |
3598 | ret = -ENOMEM; | |
3599 | goto bye; | |
3600 | } | |
3601 | ||
3602 | adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, | |
3603 | sizeof(*adap->sge.ingr_map), GFP_KERNEL); | |
3604 | if (!adap->sge.ingr_map) { | |
3605 | ret = -ENOMEM; | |
3606 | goto bye; | |
3607 | } | |
3608 | ||
3609 | /* Allocate the memory for the vaious egress queue bitmaps | |
5b377d11 | 3610 | * ie starving_fl, txq_maperr and blocked_fl. |
4b8e27a8 HS |
3611 | */ |
3612 | adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3613 | sizeof(long), GFP_KERNEL); | |
3614 | if (!adap->sge.starving_fl) { | |
3615 | ret = -ENOMEM; | |
3616 | goto bye; | |
3617 | } | |
3618 | ||
3619 | adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3620 | sizeof(long), GFP_KERNEL); | |
3621 | if (!adap->sge.txq_maperr) { | |
3622 | ret = -ENOMEM; | |
3623 | goto bye; | |
3624 | } | |
3625 | ||
5b377d11 HS |
3626 | #ifdef CONFIG_DEBUG_FS |
3627 | adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), | |
3628 | sizeof(long), GFP_KERNEL); | |
3629 | if (!adap->sge.blocked_fl) { | |
3630 | ret = -ENOMEM; | |
3631 | goto bye; | |
3632 | } | |
3633 | #endif | |
3634 | ||
b5a02f50 AB |
3635 | params[0] = FW_PARAM_PFVF(CLIP_START); |
3636 | params[1] = FW_PARAM_PFVF(CLIP_END); | |
b2612722 | 3637 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
b5a02f50 AB |
3638 | if (ret < 0) |
3639 | goto bye; | |
3640 | adap->clipt_start = val[0]; | |
3641 | adap->clipt_end = val[1]; | |
3642 | ||
b72a32da RL |
3643 | /* We don't yet have a PARAMs calls to retrieve the number of Traffic |
3644 | * Classes supported by the hardware/firmware so we hard code it here | |
3645 | * for now. | |
3646 | */ | |
3647 | adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16; | |
3648 | ||
636f9d37 VP |
3649 | /* query params related to active filter region */ |
3650 | params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); | |
3651 | params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); | |
b2612722 | 3652 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); |
636f9d37 VP |
3653 | /* If Active filter size is set we enable establishing |
3654 | * offload connection through firmware work request | |
3655 | */ | |
3656 | if ((val[0] != val[1]) && (ret >= 0)) { | |
3657 | adap->flags |= FW_OFLD_CONN; | |
3658 | adap->tids.aftid_base = val[0]; | |
3659 | adap->tids.aftid_end = val[1]; | |
3660 | } | |
3661 | ||
b407a4a9 VP |
3662 | /* If we're running on newer firmware, let it know that we're |
3663 | * prepared to deal with encapsulated CPL messages. Older | |
3664 | * firmware won't understand this and we'll just get | |
3665 | * unencapsulated messages ... | |
3666 | */ | |
3667 | params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); | |
3668 | val[0] = 1; | |
b2612722 | 3669 | (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); |
b407a4a9 | 3670 | |
1ac0f095 KS |
3671 | /* |
3672 | * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL | |
3673 | * capability. Earlier versions of the firmware didn't have the | |
3674 | * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no | |
3675 | * permission to use ULPTX MEMWRITE DSGL. | |
3676 | */ | |
3677 | if (is_t4(adap->params.chip)) { | |
3678 | adap->params.ulptx_memwrite_dsgl = false; | |
3679 | } else { | |
3680 | params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); | |
b2612722 | 3681 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, |
1ac0f095 KS |
3682 | 1, params, val); |
3683 | adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); | |
3684 | } | |
3685 | ||
086de575 SW |
3686 | /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */ |
3687 | params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); | |
3688 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, | |
3689 | 1, params, val); | |
3690 | adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); | |
3691 | ||
636f9d37 VP |
3692 | /* |
3693 | * Get device capabilities so we can determine what resources we need | |
3694 | * to manage. | |
3695 | */ | |
3696 | memset(&caps_cmd, 0, sizeof(caps_cmd)); | |
e2ac9628 HS |
3697 | caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | |
3698 | FW_CMD_REQUEST_F | FW_CMD_READ_F); | |
ce91a923 | 3699 | caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); |
636f9d37 VP |
3700 | ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), |
3701 | &caps_cmd); | |
3702 | if (ret < 0) | |
3703 | goto bye; | |
3704 | ||
13ee15d3 | 3705 | if (caps_cmd.ofldcaps) { |
b8ff05a9 DM |
3706 | /* query offload-related parameters */ |
3707 | params[0] = FW_PARAM_DEV(NTID); | |
3708 | params[1] = FW_PARAM_PFVF(SERVER_START); | |
3709 | params[2] = FW_PARAM_PFVF(SERVER_END); | |
3710 | params[3] = FW_PARAM_PFVF(TDDP_START); | |
3711 | params[4] = FW_PARAM_PFVF(TDDP_END); | |
3712 | params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); | |
b2612722 | 3713 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 3714 | params, val); |
b8ff05a9 DM |
3715 | if (ret < 0) |
3716 | goto bye; | |
3717 | adap->tids.ntids = val[0]; | |
3718 | adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); | |
3719 | adap->tids.stid_base = val[1]; | |
3720 | adap->tids.nstids = val[2] - val[1] + 1; | |
636f9d37 | 3721 | /* |
dbedd44e | 3722 | * Setup server filter region. Divide the available filter |
636f9d37 VP |
3723 | * region into two parts. Regular filters get 1/3rd and server |
3724 | * filters get 2/3rd part. This is only enabled if workarond | |
3725 | * path is enabled. | |
3726 | * 1. For regular filters. | |
3727 | * 2. Server filter: This are special filters which are used | |
3728 | * to redirect SYN packets to offload queue. | |
3729 | */ | |
3730 | if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { | |
3731 | adap->tids.sftid_base = adap->tids.ftid_base + | |
3732 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
3733 | adap->tids.nsftids = adap->tids.nftids - | |
3734 | DIV_ROUND_UP(adap->tids.nftids, 3); | |
3735 | adap->tids.nftids = adap->tids.sftid_base - | |
3736 | adap->tids.ftid_base; | |
3737 | } | |
b8ff05a9 DM |
3738 | adap->vres.ddp.start = val[3]; |
3739 | adap->vres.ddp.size = val[4] - val[3] + 1; | |
3740 | adap->params.ofldq_wr_cred = val[5]; | |
636f9d37 | 3741 | |
b8ff05a9 | 3742 | adap->params.offload = 1; |
0fbc81b3 | 3743 | adap->num_ofld_uld += 1; |
b8ff05a9 | 3744 | } |
636f9d37 | 3745 | if (caps_cmd.rdmacaps) { |
b8ff05a9 DM |
3746 | params[0] = FW_PARAM_PFVF(STAG_START); |
3747 | params[1] = FW_PARAM_PFVF(STAG_END); | |
3748 | params[2] = FW_PARAM_PFVF(RQ_START); | |
3749 | params[3] = FW_PARAM_PFVF(RQ_END); | |
3750 | params[4] = FW_PARAM_PFVF(PBL_START); | |
3751 | params[5] = FW_PARAM_PFVF(PBL_END); | |
b2612722 | 3752 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, |
636f9d37 | 3753 | params, val); |
b8ff05a9 DM |
3754 | if (ret < 0) |
3755 | goto bye; | |
3756 | adap->vres.stag.start = val[0]; | |
3757 | adap->vres.stag.size = val[1] - val[0] + 1; | |
3758 | adap->vres.rq.start = val[2]; | |
3759 | adap->vres.rq.size = val[3] - val[2] + 1; | |
3760 | adap->vres.pbl.start = val[4]; | |
3761 | adap->vres.pbl.size = val[5] - val[4] + 1; | |
a0881cab DM |
3762 | |
3763 | params[0] = FW_PARAM_PFVF(SQRQ_START); | |
3764 | params[1] = FW_PARAM_PFVF(SQRQ_END); | |
3765 | params[2] = FW_PARAM_PFVF(CQ_START); | |
3766 | params[3] = FW_PARAM_PFVF(CQ_END); | |
1ae970e0 DM |
3767 | params[4] = FW_PARAM_PFVF(OCQ_START); |
3768 | params[5] = FW_PARAM_PFVF(OCQ_END); | |
b2612722 | 3769 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, |
5c937dd3 | 3770 | val); |
a0881cab DM |
3771 | if (ret < 0) |
3772 | goto bye; | |
3773 | adap->vres.qp.start = val[0]; | |
3774 | adap->vres.qp.size = val[1] - val[0] + 1; | |
3775 | adap->vres.cq.start = val[2]; | |
3776 | adap->vres.cq.size = val[3] - val[2] + 1; | |
1ae970e0 DM |
3777 | adap->vres.ocq.start = val[4]; |
3778 | adap->vres.ocq.size = val[5] - val[4] + 1; | |
4c2c5763 HS |
3779 | |
3780 | params[0] = FW_PARAM_DEV(MAXORDIRD_QP); | |
3781 | params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); | |
b2612722 | 3782 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, |
5c937dd3 | 3783 | val); |
4c2c5763 HS |
3784 | if (ret < 0) { |
3785 | adap->params.max_ordird_qp = 8; | |
3786 | adap->params.max_ird_adapter = 32 * adap->tids.ntids; | |
3787 | ret = 0; | |
3788 | } else { | |
3789 | adap->params.max_ordird_qp = val[0]; | |
3790 | adap->params.max_ird_adapter = val[1]; | |
3791 | } | |
3792 | dev_info(adap->pdev_dev, | |
3793 | "max_ordird_qp %d max_ird_adapter %d\n", | |
3794 | adap->params.max_ordird_qp, | |
3795 | adap->params.max_ird_adapter); | |
0fbc81b3 | 3796 | adap->num_ofld_uld += 2; |
b8ff05a9 | 3797 | } |
636f9d37 | 3798 | if (caps_cmd.iscsicaps) { |
b8ff05a9 DM |
3799 | params[0] = FW_PARAM_PFVF(ISCSI_START); |
3800 | params[1] = FW_PARAM_PFVF(ISCSI_END); | |
b2612722 | 3801 | ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, |
636f9d37 | 3802 | params, val); |
b8ff05a9 DM |
3803 | if (ret < 0) |
3804 | goto bye; | |
3805 | adap->vres.iscsi.start = val[0]; | |
3806 | adap->vres.iscsi.size = val[1] - val[0] + 1; | |
0fbc81b3 HS |
3807 | /* LIO target and cxgb4i initiaitor */ |
3808 | adap->num_ofld_uld += 2; | |
b8ff05a9 | 3809 | } |
94cdb8bb HS |
3810 | if (caps_cmd.cryptocaps) { |
3811 | /* Should query params here...TODO */ | |
3812 | adap->params.crypto |= ULP_CRYPTO_LOOKASIDE; | |
3813 | adap->num_uld += 1; | |
3814 | } | |
b8ff05a9 DM |
3815 | #undef FW_PARAM_PFVF |
3816 | #undef FW_PARAM_DEV | |
3817 | ||
92e7ae71 HS |
3818 | /* The MTU/MSS Table is initialized by now, so load their values. If |
3819 | * we're initializing the adapter, then we'll make any modifications | |
3820 | * we want to the MTU/MSS Table and also initialize the congestion | |
3821 | * parameters. | |
636f9d37 | 3822 | */ |
b8ff05a9 | 3823 | t4_read_mtu_tbl(adap, adap->params.mtus, NULL); |
92e7ae71 HS |
3824 | if (state != DEV_STATE_INIT) { |
3825 | int i; | |
3826 | ||
3827 | /* The default MTU Table contains values 1492 and 1500. | |
3828 | * However, for TCP, it's better to have two values which are | |
3829 | * a multiple of 8 +/- 4 bytes apart near this popular MTU. | |
3830 | * This allows us to have a TCP Data Payload which is a | |
3831 | * multiple of 8 regardless of what combination of TCP Options | |
3832 | * are in use (always a multiple of 4 bytes) which is | |
3833 | * important for performance reasons. For instance, if no | |
3834 | * options are in use, then we have a 20-byte IP header and a | |
3835 | * 20-byte TCP header. In this case, a 1500-byte MSS would | |
3836 | * result in a TCP Data Payload of 1500 - 40 == 1460 bytes | |
3837 | * which is not a multiple of 8. So using an MSS of 1488 in | |
3838 | * this case results in a TCP Data Payload of 1448 bytes which | |
3839 | * is a multiple of 8. On the other hand, if 12-byte TCP Time | |
3840 | * Stamps have been negotiated, then an MTU of 1500 bytes | |
3841 | * results in a TCP Data Payload of 1448 bytes which, as | |
3842 | * above, is a multiple of 8 bytes ... | |
3843 | */ | |
3844 | for (i = 0; i < NMTUS; i++) | |
3845 | if (adap->params.mtus[i] == 1492) { | |
3846 | adap->params.mtus[i] = 1488; | |
3847 | break; | |
3848 | } | |
7ee9ff94 | 3849 | |
92e7ae71 HS |
3850 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, |
3851 | adap->params.b_wnd); | |
3852 | } | |
df64e4d3 | 3853 | t4_init_sge_params(adap); |
636f9d37 | 3854 | adap->flags |= FW_OK; |
c1e9af0c | 3855 | t4_init_tp_params(adap); |
b8ff05a9 DM |
3856 | return 0; |
3857 | ||
3858 | /* | |
636f9d37 VP |
3859 | * Something bad happened. If a command timed out or failed with EIO |
3860 | * FW does not operate within its spec or something catastrophic | |
3861 | * happened to HW/FW, stop issuing commands. | |
b8ff05a9 | 3862 | */ |
636f9d37 | 3863 | bye: |
4b8e27a8 HS |
3864 | kfree(adap->sge.egr_map); |
3865 | kfree(adap->sge.ingr_map); | |
3866 | kfree(adap->sge.starving_fl); | |
3867 | kfree(adap->sge.txq_maperr); | |
5b377d11 HS |
3868 | #ifdef CONFIG_DEBUG_FS |
3869 | kfree(adap->sge.blocked_fl); | |
3870 | #endif | |
636f9d37 VP |
3871 | if (ret != -ETIMEDOUT && ret != -EIO) |
3872 | t4_fw_bye(adap, adap->mbox); | |
b8ff05a9 DM |
3873 | return ret; |
3874 | } | |
3875 | ||
204dc3c0 DM |
3876 | /* EEH callbacks */ |
3877 | ||
3878 | static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, | |
3879 | pci_channel_state_t state) | |
3880 | { | |
3881 | int i; | |
3882 | struct adapter *adap = pci_get_drvdata(pdev); | |
3883 | ||
3884 | if (!adap) | |
3885 | goto out; | |
3886 | ||
3887 | rtnl_lock(); | |
3888 | adap->flags &= ~FW_OK; | |
3889 | notify_ulds(adap, CXGB4_STATE_START_RECOVERY); | |
9fe6cb58 | 3890 | spin_lock(&adap->stats_lock); |
204dc3c0 DM |
3891 | for_each_port(adap, i) { |
3892 | struct net_device *dev = adap->port[i]; | |
3893 | ||
3894 | netif_device_detach(dev); | |
3895 | netif_carrier_off(dev); | |
3896 | } | |
9fe6cb58 | 3897 | spin_unlock(&adap->stats_lock); |
b37987e8 | 3898 | disable_interrupts(adap); |
204dc3c0 DM |
3899 | if (adap->flags & FULL_INIT_DONE) |
3900 | cxgb_down(adap); | |
3901 | rtnl_unlock(); | |
144be3d9 GS |
3902 | if ((adap->flags & DEV_ENABLED)) { |
3903 | pci_disable_device(pdev); | |
3904 | adap->flags &= ~DEV_ENABLED; | |
3905 | } | |
204dc3c0 DM |
3906 | out: return state == pci_channel_io_perm_failure ? |
3907 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
3908 | } | |
3909 | ||
3910 | static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) | |
3911 | { | |
3912 | int i, ret; | |
3913 | struct fw_caps_config_cmd c; | |
3914 | struct adapter *adap = pci_get_drvdata(pdev); | |
3915 | ||
3916 | if (!adap) { | |
3917 | pci_restore_state(pdev); | |
3918 | pci_save_state(pdev); | |
3919 | return PCI_ERS_RESULT_RECOVERED; | |
3920 | } | |
3921 | ||
144be3d9 GS |
3922 | if (!(adap->flags & DEV_ENABLED)) { |
3923 | if (pci_enable_device(pdev)) { | |
3924 | dev_err(&pdev->dev, "Cannot reenable PCI " | |
3925 | "device after reset\n"); | |
3926 | return PCI_ERS_RESULT_DISCONNECT; | |
3927 | } | |
3928 | adap->flags |= DEV_ENABLED; | |
204dc3c0 DM |
3929 | } |
3930 | ||
3931 | pci_set_master(pdev); | |
3932 | pci_restore_state(pdev); | |
3933 | pci_save_state(pdev); | |
3934 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
3935 | ||
8203b509 | 3936 | if (t4_wait_dev_ready(adap->regs) < 0) |
204dc3c0 | 3937 | return PCI_ERS_RESULT_DISCONNECT; |
b2612722 | 3938 | if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) |
204dc3c0 DM |
3939 | return PCI_ERS_RESULT_DISCONNECT; |
3940 | adap->flags |= FW_OK; | |
3941 | if (adap_init1(adap, &c)) | |
3942 | return PCI_ERS_RESULT_DISCONNECT; | |
3943 | ||
3944 | for_each_port(adap, i) { | |
3945 | struct port_info *p = adap2pinfo(adap, i); | |
3946 | ||
b2612722 | 3947 | ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, |
060e0c75 | 3948 | NULL, NULL); |
204dc3c0 DM |
3949 | if (ret < 0) |
3950 | return PCI_ERS_RESULT_DISCONNECT; | |
3951 | p->viid = ret; | |
3952 | p->xact_addr_filt = -1; | |
3953 | } | |
3954 | ||
3955 | t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, | |
3956 | adap->params.b_wnd); | |
1ae970e0 | 3957 | setup_memwin(adap); |
204dc3c0 DM |
3958 | if (cxgb_up(adap)) |
3959 | return PCI_ERS_RESULT_DISCONNECT; | |
3960 | return PCI_ERS_RESULT_RECOVERED; | |
3961 | } | |
3962 | ||
3963 | static void eeh_resume(struct pci_dev *pdev) | |
3964 | { | |
3965 | int i; | |
3966 | struct adapter *adap = pci_get_drvdata(pdev); | |
3967 | ||
3968 | if (!adap) | |
3969 | return; | |
3970 | ||
3971 | rtnl_lock(); | |
3972 | for_each_port(adap, i) { | |
3973 | struct net_device *dev = adap->port[i]; | |
3974 | ||
3975 | if (netif_running(dev)) { | |
3976 | link_start(dev); | |
3977 | cxgb_set_rxmode(dev); | |
3978 | } | |
3979 | netif_device_attach(dev); | |
3980 | } | |
3981 | rtnl_unlock(); | |
3982 | } | |
3983 | ||
3646f0e5 | 3984 | static const struct pci_error_handlers cxgb4_eeh = { |
204dc3c0 DM |
3985 | .error_detected = eeh_err_detected, |
3986 | .slot_reset = eeh_slot_reset, | |
3987 | .resume = eeh_resume, | |
3988 | }; | |
3989 | ||
9b86a8d1 HS |
3990 | /* Return true if the Link Configuration supports "High Speeds" (those greater |
3991 | * than 1Gb/s). | |
3992 | */ | |
57d8b764 | 3993 | static inline bool is_x_10g_port(const struct link_config *lc) |
b8ff05a9 | 3994 | { |
9b86a8d1 HS |
3995 | unsigned int speeds, high_speeds; |
3996 | ||
3997 | speeds = FW_PORT_CAP_SPEED_V(FW_PORT_CAP_SPEED_G(lc->supported)); | |
3998 | high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G); | |
3999 | ||
4000 | return high_speeds != 0; | |
b8ff05a9 DM |
4001 | } |
4002 | ||
b8ff05a9 DM |
4003 | /* |
4004 | * Perform default configuration of DMA queues depending on the number and type | |
4005 | * of ports we found and the number of available CPUs. Most settings can be | |
4006 | * modified by the admin prior to actual use. | |
4007 | */ | |
91744948 | 4008 | static void cfg_queues(struct adapter *adap) |
b8ff05a9 DM |
4009 | { |
4010 | struct sge *s = &adap->sge; | |
ab677ff4 | 4011 | int i = 0, n10g = 0, qidx = 0; |
688848b1 AB |
4012 | #ifndef CONFIG_CHELSIO_T4_DCB |
4013 | int q10g = 0; | |
4014 | #endif | |
b8ff05a9 | 4015 | |
94cdb8bb HS |
4016 | /* Reduce memory usage in kdump environment, disable all offload. |
4017 | */ | |
4018 | if (is_kdump_kernel()) { | |
4019 | adap->params.offload = 0; | |
4020 | adap->params.crypto = 0; | |
0fbc81b3 HS |
4021 | } else if (is_uld(adap) && t4_uld_mem_alloc(adap)) { |
4022 | adap->params.offload = 0; | |
94cdb8bb HS |
4023 | adap->params.crypto = 0; |
4024 | } | |
4025 | ||
ab677ff4 | 4026 | n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); |
688848b1 AB |
4027 | #ifdef CONFIG_CHELSIO_T4_DCB |
4028 | /* For Data Center Bridging support we need to be able to support up | |
4029 | * to 8 Traffic Priorities; each of which will be assigned to its | |
4030 | * own TX Queue in order to prevent Head-Of-Line Blocking. | |
4031 | */ | |
4032 | if (adap->params.nports * 8 > MAX_ETH_QSETS) { | |
4033 | dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n", | |
4034 | MAX_ETH_QSETS, adap->params.nports * 8); | |
4035 | BUG_ON(1); | |
4036 | } | |
b8ff05a9 | 4037 | |
688848b1 AB |
4038 | for_each_port(adap, i) { |
4039 | struct port_info *pi = adap2pinfo(adap, i); | |
4040 | ||
4041 | pi->first_qset = qidx; | |
4042 | pi->nqsets = 8; | |
4043 | qidx += pi->nqsets; | |
4044 | } | |
4045 | #else /* !CONFIG_CHELSIO_T4_DCB */ | |
b8ff05a9 DM |
4046 | /* |
4047 | * We default to 1 queue per non-10G port and up to # of cores queues | |
4048 | * per 10G port. | |
4049 | */ | |
4050 | if (n10g) | |
4051 | q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; | |
5952dde7 YM |
4052 | if (q10g > netif_get_num_default_rss_queues()) |
4053 | q10g = netif_get_num_default_rss_queues(); | |
b8ff05a9 DM |
4054 | |
4055 | for_each_port(adap, i) { | |
4056 | struct port_info *pi = adap2pinfo(adap, i); | |
4057 | ||
4058 | pi->first_qset = qidx; | |
57d8b764 | 4059 | pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; |
b8ff05a9 DM |
4060 | qidx += pi->nqsets; |
4061 | } | |
688848b1 | 4062 | #endif /* !CONFIG_CHELSIO_T4_DCB */ |
b8ff05a9 DM |
4063 | |
4064 | s->ethqsets = qidx; | |
4065 | s->max_ethqsets = qidx; /* MSI-X may lower it later */ | |
4066 | ||
0fbc81b3 | 4067 | if (is_uld(adap)) { |
b8ff05a9 DM |
4068 | /* |
4069 | * For offload we use 1 queue/channel if all ports are up to 1G, | |
4070 | * otherwise we divide all available queues amongst the channels | |
4071 | * capped by the number of available cores. | |
4072 | */ | |
4073 | if (n10g) { | |
a56177e1 | 4074 | i = min_t(int, MAX_OFLD_QSETS, num_online_cpus()); |
0fbc81b3 HS |
4075 | s->ofldqsets = roundup(i, adap->params.nports); |
4076 | } else { | |
4077 | s->ofldqsets = adap->params.nports; | |
4078 | } | |
b8ff05a9 DM |
4079 | } |
4080 | ||
4081 | for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { | |
4082 | struct sge_eth_rxq *r = &s->ethrxq[i]; | |
4083 | ||
c887ad0e | 4084 | init_rspq(adap, &r->rspq, 5, 10, 1024, 64); |
b8ff05a9 DM |
4085 | r->fl.size = 72; |
4086 | } | |
4087 | ||
4088 | for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) | |
4089 | s->ethtxq[i].q.size = 1024; | |
4090 | ||
4091 | for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) | |
4092 | s->ctrlq[i].q.size = 512; | |
4093 | ||
c887ad0e | 4094 | init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); |
0fbc81b3 | 4095 | init_rspq(adap, &s->intrq, 0, 1, 512, 64); |
b8ff05a9 DM |
4096 | } |
4097 | ||
4098 | /* | |
4099 | * Reduce the number of Ethernet queues across all ports to at most n. | |
4100 | * n provides at least one queue per port. | |
4101 | */ | |
91744948 | 4102 | static void reduce_ethqs(struct adapter *adap, int n) |
b8ff05a9 DM |
4103 | { |
4104 | int i; | |
4105 | struct port_info *pi; | |
4106 | ||
4107 | while (n < adap->sge.ethqsets) | |
4108 | for_each_port(adap, i) { | |
4109 | pi = adap2pinfo(adap, i); | |
4110 | if (pi->nqsets > 1) { | |
4111 | pi->nqsets--; | |
4112 | adap->sge.ethqsets--; | |
4113 | if (adap->sge.ethqsets <= n) | |
4114 | break; | |
4115 | } | |
4116 | } | |
4117 | ||
4118 | n = 0; | |
4119 | for_each_port(adap, i) { | |
4120 | pi = adap2pinfo(adap, i); | |
4121 | pi->first_qset = n; | |
4122 | n += pi->nqsets; | |
4123 | } | |
4124 | } | |
4125 | ||
94cdb8bb HS |
4126 | static int get_msix_info(struct adapter *adap) |
4127 | { | |
4128 | struct uld_msix_info *msix_info; | |
0fbc81b3 HS |
4129 | unsigned int max_ingq = 0; |
4130 | ||
4131 | if (is_offload(adap)) | |
4132 | max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld; | |
4133 | if (is_pci_uld(adap)) | |
4134 | max_ingq += MAX_OFLD_QSETS * adap->num_uld; | |
4135 | ||
4136 | if (!max_ingq) | |
4137 | goto out; | |
94cdb8bb HS |
4138 | |
4139 | msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL); | |
4140 | if (!msix_info) | |
4141 | return -ENOMEM; | |
4142 | ||
4143 | adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq), | |
4144 | sizeof(long), GFP_KERNEL); | |
4145 | if (!adap->msix_bmap_ulds.msix_bmap) { | |
4146 | kfree(msix_info); | |
4147 | return -ENOMEM; | |
4148 | } | |
4149 | spin_lock_init(&adap->msix_bmap_ulds.lock); | |
4150 | adap->msix_info_ulds = msix_info; | |
0fbc81b3 | 4151 | out: |
94cdb8bb HS |
4152 | return 0; |
4153 | } | |
4154 | ||
4155 | static void free_msix_info(struct adapter *adap) | |
4156 | { | |
0fbc81b3 | 4157 | if (!(adap->num_uld && adap->num_ofld_uld)) |
94cdb8bb HS |
4158 | return; |
4159 | ||
4160 | kfree(adap->msix_info_ulds); | |
4161 | kfree(adap->msix_bmap_ulds.msix_bmap); | |
4162 | } | |
4163 | ||
b8ff05a9 DM |
4164 | /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ |
4165 | #define EXTRA_VECS 2 | |
4166 | ||
91744948 | 4167 | static int enable_msix(struct adapter *adap) |
b8ff05a9 | 4168 | { |
94cdb8bb HS |
4169 | int ofld_need = 0, uld_need = 0; |
4170 | int i, j, want, need, allocated; | |
b8ff05a9 DM |
4171 | struct sge *s = &adap->sge; |
4172 | unsigned int nchan = adap->params.nports; | |
f36e58e5 | 4173 | struct msix_entry *entries; |
94cdb8bb | 4174 | int max_ingq = MAX_INGQ; |
f36e58e5 | 4175 | |
0fbc81b3 HS |
4176 | if (is_pci_uld(adap)) |
4177 | max_ingq += (MAX_OFLD_QSETS * adap->num_uld); | |
4178 | if (is_offload(adap)) | |
4179 | max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld); | |
94cdb8bb | 4180 | entries = kmalloc(sizeof(*entries) * (max_ingq + 1), |
f36e58e5 HS |
4181 | GFP_KERNEL); |
4182 | if (!entries) | |
4183 | return -ENOMEM; | |
b8ff05a9 | 4184 | |
94cdb8bb | 4185 | /* map for msix */ |
0fbc81b3 HS |
4186 | if (get_msix_info(adap)) { |
4187 | adap->params.offload = 0; | |
94cdb8bb | 4188 | adap->params.crypto = 0; |
0fbc81b3 | 4189 | } |
94cdb8bb HS |
4190 | |
4191 | for (i = 0; i < max_ingq + 1; ++i) | |
b8ff05a9 DM |
4192 | entries[i].entry = i; |
4193 | ||
4194 | want = s->max_ethqsets + EXTRA_VECS; | |
4195 | if (is_offload(adap)) { | |
0fbc81b3 HS |
4196 | want += adap->num_ofld_uld * s->ofldqsets; |
4197 | ofld_need = adap->num_ofld_uld * nchan; | |
b8ff05a9 | 4198 | } |
94cdb8bb | 4199 | if (is_pci_uld(adap)) { |
0fbc81b3 HS |
4200 | want += adap->num_uld * s->ofldqsets; |
4201 | uld_need = adap->num_uld * nchan; | |
94cdb8bb | 4202 | } |
688848b1 AB |
4203 | #ifdef CONFIG_CHELSIO_T4_DCB |
4204 | /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for | |
4205 | * each port. | |
4206 | */ | |
94cdb8bb | 4207 | need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need; |
688848b1 | 4208 | #else |
94cdb8bb | 4209 | need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need; |
688848b1 | 4210 | #endif |
f36e58e5 HS |
4211 | allocated = pci_enable_msix_range(adap->pdev, entries, need, want); |
4212 | if (allocated < 0) { | |
4213 | dev_info(adap->pdev_dev, "not enough MSI-X vectors left," | |
4214 | " not using MSI-X\n"); | |
4215 | kfree(entries); | |
4216 | return allocated; | |
4217 | } | |
b8ff05a9 | 4218 | |
f36e58e5 | 4219 | /* Distribute available vectors to the various queue groups. |
c32ad224 AG |
4220 | * Every group gets its minimum requirement and NIC gets top |
4221 | * priority for leftovers. | |
4222 | */ | |
94cdb8bb | 4223 | i = allocated - EXTRA_VECS - ofld_need - uld_need; |
c32ad224 AG |
4224 | if (i < s->max_ethqsets) { |
4225 | s->max_ethqsets = i; | |
4226 | if (i < s->ethqsets) | |
4227 | reduce_ethqs(adap, i); | |
4228 | } | |
0fbc81b3 | 4229 | if (is_uld(adap)) { |
94cdb8bb HS |
4230 | if (allocated < want) |
4231 | s->nqs_per_uld = nchan; | |
4232 | else | |
0fbc81b3 | 4233 | s->nqs_per_uld = s->ofldqsets; |
94cdb8bb HS |
4234 | } |
4235 | ||
0fbc81b3 | 4236 | for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i) |
c32ad224 | 4237 | adap->msix_info[i].vec = entries[i].vector; |
0fbc81b3 HS |
4238 | if (is_uld(adap)) { |
4239 | for (j = 0 ; i < allocated; ++i, j++) { | |
94cdb8bb | 4240 | adap->msix_info_ulds[j].vec = entries[i].vector; |
0fbc81b3 HS |
4241 | adap->msix_info_ulds[j].idx = i; |
4242 | } | |
94cdb8bb HS |
4243 | adap->msix_bmap_ulds.mapsize = j; |
4244 | } | |
43eb4e82 | 4245 | dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " |
0fbc81b3 HS |
4246 | "nic %d per uld %d\n", |
4247 | allocated, s->max_ethqsets, s->nqs_per_uld); | |
c32ad224 | 4248 | |
f36e58e5 | 4249 | kfree(entries); |
c32ad224 | 4250 | return 0; |
b8ff05a9 DM |
4251 | } |
4252 | ||
4253 | #undef EXTRA_VECS | |
4254 | ||
91744948 | 4255 | static int init_rss(struct adapter *adap) |
671b0060 | 4256 | { |
c035e183 HS |
4257 | unsigned int i; |
4258 | int err; | |
4259 | ||
4260 | err = t4_init_rss_mode(adap, adap->mbox); | |
4261 | if (err) | |
4262 | return err; | |
671b0060 DM |
4263 | |
4264 | for_each_port(adap, i) { | |
4265 | struct port_info *pi = adap2pinfo(adap, i); | |
4266 | ||
4267 | pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); | |
4268 | if (!pi->rss) | |
4269 | return -ENOMEM; | |
671b0060 DM |
4270 | } |
4271 | return 0; | |
4272 | } | |
4273 | ||
547fd272 HS |
4274 | static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap, |
4275 | enum pci_bus_speed *speed, | |
4276 | enum pcie_link_width *width) | |
4277 | { | |
4278 | u32 lnkcap1, lnkcap2; | |
4279 | int err1, err2; | |
4280 | ||
4281 | #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ | |
4282 | ||
4283 | *speed = PCI_SPEED_UNKNOWN; | |
4284 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4285 | ||
4286 | err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP, | |
4287 | &lnkcap1); | |
4288 | err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2, | |
4289 | &lnkcap2); | |
4290 | if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ | |
4291 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
4292 | *speed = PCIE_SPEED_8_0GT; | |
4293 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
4294 | *speed = PCIE_SPEED_5_0GT; | |
4295 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
4296 | *speed = PCIE_SPEED_2_5GT; | |
4297 | } | |
4298 | if (!err1) { | |
4299 | *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; | |
4300 | if (!lnkcap2) { /* pre-r3.0 */ | |
4301 | if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) | |
4302 | *speed = PCIE_SPEED_5_0GT; | |
4303 | else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) | |
4304 | *speed = PCIE_SPEED_2_5GT; | |
4305 | } | |
4306 | } | |
4307 | ||
4308 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
4309 | return err1 ? err1 : err2 ? err2 : -EINVAL; | |
4310 | return 0; | |
4311 | } | |
4312 | ||
4313 | static void cxgb4_check_pcie_caps(struct adapter *adap) | |
4314 | { | |
4315 | enum pcie_link_width width, width_cap; | |
4316 | enum pci_bus_speed speed, speed_cap; | |
4317 | ||
4318 | #define PCIE_SPEED_STR(speed) \ | |
4319 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ | |
4320 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ | |
4321 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ | |
4322 | "Unknown") | |
4323 | ||
4324 | if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) { | |
4325 | dev_warn(adap->pdev_dev, | |
4326 | "Unable to determine PCIe device BW capabilities\n"); | |
4327 | return; | |
4328 | } | |
4329 | ||
4330 | if (pcie_get_minimum_link(adap->pdev, &speed, &width) || | |
4331 | speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { | |
4332 | dev_warn(adap->pdev_dev, | |
4333 | "Unable to determine PCI Express bandwidth.\n"); | |
4334 | return; | |
4335 | } | |
4336 | ||
4337 | dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n", | |
4338 | PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); | |
4339 | dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n", | |
4340 | width, width_cap); | |
4341 | if (speed < speed_cap || width < width_cap) | |
4342 | dev_info(adap->pdev_dev, | |
4343 | "A slot with more lanes and/or higher speed is " | |
4344 | "suggested for optimal performance.\n"); | |
4345 | } | |
4346 | ||
0de72738 HS |
4347 | /* Dump basic information about the adapter */ |
4348 | static void print_adapter_info(struct adapter *adapter) | |
4349 | { | |
4350 | /* Device information */ | |
4351 | dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n", | |
4352 | adapter->params.vpd.id, | |
4353 | CHELSIO_CHIP_RELEASE(adapter->params.chip)); | |
4354 | dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n", | |
4355 | adapter->params.vpd.sn, adapter->params.vpd.pn); | |
4356 | ||
4357 | /* Firmware Version */ | |
4358 | if (!adapter->params.fw_vers) | |
4359 | dev_warn(adapter->pdev_dev, "No firmware loaded\n"); | |
4360 | else | |
4361 | dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n", | |
4362 | FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers), | |
4363 | FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers), | |
4364 | FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers), | |
4365 | FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers)); | |
4366 | ||
4367 | /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap | |
4368 | * Firmware, so dev_info() is more appropriate here.) | |
4369 | */ | |
4370 | if (!adapter->params.bs_vers) | |
4371 | dev_info(adapter->pdev_dev, "No bootstrap loaded\n"); | |
4372 | else | |
4373 | dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n", | |
4374 | FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers), | |
4375 | FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers), | |
4376 | FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers), | |
4377 | FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers)); | |
4378 | ||
4379 | /* TP Microcode Version */ | |
4380 | if (!adapter->params.tp_vers) | |
4381 | dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n"); | |
4382 | else | |
4383 | dev_info(adapter->pdev_dev, | |
4384 | "TP Microcode version: %u.%u.%u.%u\n", | |
4385 | FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers), | |
4386 | FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers), | |
4387 | FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers), | |
4388 | FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers)); | |
4389 | ||
4390 | /* Expansion ROM version */ | |
4391 | if (!adapter->params.er_vers) | |
4392 | dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n"); | |
4393 | else | |
4394 | dev_info(adapter->pdev_dev, | |
4395 | "Expansion ROM version: %u.%u.%u.%u\n", | |
4396 | FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers), | |
4397 | FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers), | |
4398 | FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers), | |
4399 | FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers)); | |
4400 | ||
4401 | /* Software/Hardware configuration */ | |
4402 | dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", | |
4403 | is_offload(adapter) ? "R" : "", | |
4404 | ((adapter->flags & USING_MSIX) ? "MSI-X" : | |
4405 | (adapter->flags & USING_MSI) ? "MSI" : ""), | |
4406 | is_offload(adapter) ? "Offload" : "non-Offload"); | |
4407 | } | |
4408 | ||
91744948 | 4409 | static void print_port_info(const struct net_device *dev) |
b8ff05a9 | 4410 | { |
b8ff05a9 | 4411 | char buf[80]; |
118969ed | 4412 | char *bufp = buf; |
f1a051b9 | 4413 | const char *spd = ""; |
118969ed DM |
4414 | const struct port_info *pi = netdev_priv(dev); |
4415 | const struct adapter *adap = pi->adapter; | |
f1a051b9 DM |
4416 | |
4417 | if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) | |
4418 | spd = " 2.5 GT/s"; | |
4419 | else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) | |
4420 | spd = " 5 GT/s"; | |
d2e752db RD |
4421 | else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) |
4422 | spd = " 8 GT/s"; | |
b8ff05a9 | 4423 | |
118969ed | 4424 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M) |
5e78f7fd | 4425 | bufp += sprintf(bufp, "100M/"); |
118969ed | 4426 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) |
5e78f7fd | 4427 | bufp += sprintf(bufp, "1G/"); |
118969ed DM |
4428 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) |
4429 | bufp += sprintf(bufp, "10G/"); | |
9b86a8d1 HS |
4430 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) |
4431 | bufp += sprintf(bufp, "25G/"); | |
72aca4bf KS |
4432 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) |
4433 | bufp += sprintf(bufp, "40G/"); | |
9b86a8d1 HS |
4434 | if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) |
4435 | bufp += sprintf(bufp, "100G/"); | |
118969ed DM |
4436 | if (bufp != buf) |
4437 | --bufp; | |
72aca4bf | 4438 | sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); |
118969ed | 4439 | |
0de72738 HS |
4440 | netdev_info(dev, "%s: Chelsio %s (%s) %s\n", |
4441 | dev->name, adap->params.vpd.id, adap->name, buf); | |
b8ff05a9 DM |
4442 | } |
4443 | ||
91744948 | 4444 | static void enable_pcie_relaxed_ordering(struct pci_dev *dev) |
ef306b50 | 4445 | { |
e5c8ae5f | 4446 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); |
ef306b50 DM |
4447 | } |
4448 | ||
06546391 DM |
4449 | /* |
4450 | * Free the following resources: | |
4451 | * - memory used for tables | |
4452 | * - MSI/MSI-X | |
4453 | * - net devices | |
4454 | * - resources FW is holding for us | |
4455 | */ | |
4456 | static void free_some_resources(struct adapter *adapter) | |
4457 | { | |
4458 | unsigned int i; | |
4459 | ||
4460 | t4_free_mem(adapter->l2t); | |
b72a32da | 4461 | t4_cleanup_sched(adapter); |
06546391 | 4462 | t4_free_mem(adapter->tids.tid_tab); |
d8931847 | 4463 | cxgb4_cleanup_tc_u32(adapter); |
4b8e27a8 HS |
4464 | kfree(adapter->sge.egr_map); |
4465 | kfree(adapter->sge.ingr_map); | |
4466 | kfree(adapter->sge.starving_fl); | |
4467 | kfree(adapter->sge.txq_maperr); | |
5b377d11 HS |
4468 | #ifdef CONFIG_DEBUG_FS |
4469 | kfree(adapter->sge.blocked_fl); | |
4470 | #endif | |
06546391 DM |
4471 | disable_msi(adapter); |
4472 | ||
4473 | for_each_port(adapter, i) | |
671b0060 | 4474 | if (adapter->port[i]) { |
4f3a0fcf HS |
4475 | struct port_info *pi = adap2pinfo(adapter, i); |
4476 | ||
4477 | if (pi->viid != 0) | |
4478 | t4_free_vi(adapter, adapter->mbox, adapter->pf, | |
4479 | 0, pi->viid); | |
671b0060 | 4480 | kfree(adap2pinfo(adapter, i)->rss); |
06546391 | 4481 | free_netdev(adapter->port[i]); |
671b0060 | 4482 | } |
06546391 | 4483 | if (adapter->flags & FW_OK) |
b2612722 | 4484 | t4_fw_bye(adapter, adapter->pf); |
06546391 DM |
4485 | } |
4486 | ||
2ed28baa | 4487 | #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) |
35d35682 | 4488 | #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ |
b8ff05a9 | 4489 | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) |
22adfe0a | 4490 | #define SEGMENT_SIZE 128 |
b8ff05a9 | 4491 | |
d86bd29e HS |
4492 | static int get_chip_type(struct pci_dev *pdev, u32 pl_rev) |
4493 | { | |
d86bd29e HS |
4494 | u16 device_id; |
4495 | ||
4496 | /* Retrieve adapter's device ID */ | |
4497 | pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); | |
46cdc9be | 4498 | |
4499 | switch (device_id >> 12) { | |
d86bd29e | 4500 | case CHELSIO_T4: |
46cdc9be | 4501 | return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); |
d86bd29e | 4502 | case CHELSIO_T5: |
46cdc9be | 4503 | return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); |
d86bd29e | 4504 | case CHELSIO_T6: |
46cdc9be | 4505 | return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); |
d86bd29e HS |
4506 | default: |
4507 | dev_err(&pdev->dev, "Device %d is not supported\n", | |
4508 | device_id); | |
d86bd29e | 4509 | } |
46cdc9be | 4510 | return -EINVAL; |
d86bd29e HS |
4511 | } |
4512 | ||
b6244201 | 4513 | #ifdef CONFIG_PCI_IOV |
e7b48a32 HS |
4514 | static void dummy_setup(struct net_device *dev) |
4515 | { | |
4516 | dev->type = ARPHRD_NONE; | |
4517 | dev->mtu = 0; | |
4518 | dev->hard_header_len = 0; | |
4519 | dev->addr_len = 0; | |
4520 | dev->tx_queue_len = 0; | |
4521 | dev->flags |= IFF_NOARP; | |
4522 | dev->priv_flags |= IFF_NO_QUEUE; | |
4523 | ||
4524 | /* Initialize the device structure. */ | |
4525 | dev->netdev_ops = &cxgb4_mgmt_netdev_ops; | |
4526 | dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops; | |
4527 | dev->destructor = free_netdev; | |
4528 | } | |
4529 | ||
4530 | static int config_mgmt_dev(struct pci_dev *pdev) | |
4531 | { | |
4532 | struct adapter *adap = pci_get_drvdata(pdev); | |
4533 | struct net_device *netdev; | |
4534 | struct port_info *pi; | |
4535 | char name[IFNAMSIZ]; | |
4536 | int err; | |
4537 | ||
4538 | snprintf(name, IFNAMSIZ, "mgmtpf%d%d", adap->adap_idx, adap->pf); | |
038c35a8 GG |
4539 | netdev = alloc_netdev(sizeof(struct port_info), name, NET_NAME_UNKNOWN, |
4540 | dummy_setup); | |
e7b48a32 HS |
4541 | if (!netdev) |
4542 | return -ENOMEM; | |
4543 | ||
4544 | pi = netdev_priv(netdev); | |
4545 | pi->adapter = adap; | |
96fe11f2 | 4546 | pi->port_id = adap->pf % adap->params.nports; |
e7b48a32 HS |
4547 | SET_NETDEV_DEV(netdev, &pdev->dev); |
4548 | ||
4549 | adap->port[0] = netdev; | |
4550 | ||
4551 | err = register_netdev(adap->port[0]); | |
4552 | if (err) { | |
4553 | pr_info("Unable to register VF mgmt netdev %s\n", name); | |
4554 | free_netdev(adap->port[0]); | |
4555 | adap->port[0] = NULL; | |
4556 | return err; | |
4557 | } | |
4558 | return 0; | |
4559 | } | |
4560 | ||
b6244201 HS |
4561 | static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) |
4562 | { | |
7829451c | 4563 | struct adapter *adap = pci_get_drvdata(pdev); |
b6244201 HS |
4564 | int err = 0; |
4565 | int current_vfs = pci_num_vf(pdev); | |
4566 | u32 pcie_fw; | |
b6244201 | 4567 | |
7829451c | 4568 | pcie_fw = readl(adap->regs + PCIE_FW_A); |
b6244201 HS |
4569 | /* Check if cxgb4 is the MASTER and fw is initialized */ |
4570 | if (!(pcie_fw & PCIE_FW_INIT_F) || | |
4571 | !(pcie_fw & PCIE_FW_MASTER_VLD_F) || | |
4572 | PCIE_FW_MASTER_G(pcie_fw) != 4) { | |
4573 | dev_warn(&pdev->dev, | |
4574 | "cxgb4 driver needs to be MASTER to support SRIOV\n"); | |
4575 | return -EOPNOTSUPP; | |
4576 | } | |
4577 | ||
4578 | /* If any of the VF's is already assigned to Guest OS, then | |
4579 | * SRIOV for the same cannot be modified | |
4580 | */ | |
4581 | if (current_vfs && pci_vfs_assigned(pdev)) { | |
4582 | dev_err(&pdev->dev, | |
4583 | "Cannot modify SR-IOV while VFs are assigned\n"); | |
4584 | num_vfs = current_vfs; | |
4585 | return num_vfs; | |
4586 | } | |
4587 | ||
4588 | /* Disable SRIOV when zero is passed. | |
4589 | * One needs to disable SRIOV before modifying it, else | |
4590 | * stack throws the below warning: | |
4591 | * " 'n' VFs already enabled. Disable before enabling 'm' VFs." | |
4592 | */ | |
4593 | if (!num_vfs) { | |
4594 | pci_disable_sriov(pdev); | |
e7b48a32 | 4595 | if (adap->port[0]) { |
7829451c | 4596 | unregister_netdev(adap->port[0]); |
e7b48a32 HS |
4597 | adap->port[0] = NULL; |
4598 | } | |
661dbeb9 HS |
4599 | /* free VF resources */ |
4600 | kfree(adap->vfinfo); | |
4601 | adap->vfinfo = NULL; | |
4602 | adap->num_vfs = 0; | |
b6244201 HS |
4603 | return num_vfs; |
4604 | } | |
4605 | ||
4606 | if (num_vfs != current_vfs) { | |
4607 | err = pci_enable_sriov(pdev, num_vfs); | |
4608 | if (err) | |
4609 | return err; | |
7829451c | 4610 | |
661dbeb9 | 4611 | adap->num_vfs = num_vfs; |
e7b48a32 HS |
4612 | err = config_mgmt_dev(pdev); |
4613 | if (err) | |
4614 | return err; | |
b6244201 | 4615 | } |
661dbeb9 HS |
4616 | |
4617 | adap->vfinfo = kcalloc(adap->num_vfs, | |
4618 | sizeof(struct vf_info), GFP_KERNEL); | |
4619 | if (adap->vfinfo) | |
4620 | fill_vf_station_mac_addr(adap); | |
b6244201 HS |
4621 | return num_vfs; |
4622 | } | |
4623 | #endif | |
4624 | ||
1dd06ae8 | 4625 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
b8ff05a9 | 4626 | { |
22adfe0a | 4627 | int func, i, err, s_qpp, qpp, num_seg; |
b8ff05a9 | 4628 | struct port_info *pi; |
c8f44aff | 4629 | bool highdma = false; |
b8ff05a9 | 4630 | struct adapter *adapter = NULL; |
7829451c | 4631 | struct net_device *netdev; |
d6ce2628 | 4632 | void __iomem *regs; |
d86bd29e HS |
4633 | u32 whoami, pl_rev; |
4634 | enum chip_type chip; | |
7829451c | 4635 | static int adap_idx = 1; |
0a327889 | 4636 | #ifdef CONFIG_PCI_IOV |
96fe11f2 | 4637 | u32 v, port_vec; |
0a327889 | 4638 | #endif |
b8ff05a9 DM |
4639 | |
4640 | printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); | |
4641 | ||
4642 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
4643 | if (err) { | |
4644 | /* Just info, some other driver may have claimed the device. */ | |
4645 | dev_info(&pdev->dev, "cannot obtain PCI resources\n"); | |
4646 | return err; | |
4647 | } | |
4648 | ||
b8ff05a9 DM |
4649 | err = pci_enable_device(pdev); |
4650 | if (err) { | |
4651 | dev_err(&pdev->dev, "cannot enable PCI device\n"); | |
4652 | goto out_release_regions; | |
4653 | } | |
4654 | ||
d6ce2628 HS |
4655 | regs = pci_ioremap_bar(pdev, 0); |
4656 | if (!regs) { | |
4657 | dev_err(&pdev->dev, "cannot map device registers\n"); | |
4658 | err = -ENOMEM; | |
4659 | goto out_disable_device; | |
4660 | } | |
4661 | ||
8203b509 HS |
4662 | err = t4_wait_dev_ready(regs); |
4663 | if (err < 0) | |
4664 | goto out_unmap_bar0; | |
4665 | ||
d6ce2628 | 4666 | /* We control everything through one PF */ |
d86bd29e HS |
4667 | whoami = readl(regs + PL_WHOAMI_A); |
4668 | pl_rev = REV_G(readl(regs + PL_REV_A)); | |
4669 | chip = get_chip_type(pdev, pl_rev); | |
4670 | func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? | |
4671 | SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); | |
d6ce2628 | 4672 | if (func != ent->driver_data) { |
7829451c | 4673 | #ifndef CONFIG_PCI_IOV |
d6ce2628 | 4674 | iounmap(regs); |
7829451c | 4675 | #endif |
d6ce2628 HS |
4676 | pci_disable_device(pdev); |
4677 | pci_save_state(pdev); /* to restore SR-IOV later */ | |
4678 | goto sriov; | |
4679 | } | |
4680 | ||
b8ff05a9 | 4681 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
c8f44aff | 4682 | highdma = true; |
b8ff05a9 DM |
4683 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
4684 | if (err) { | |
4685 | dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " | |
4686 | "coherent allocations\n"); | |
d6ce2628 | 4687 | goto out_unmap_bar0; |
b8ff05a9 DM |
4688 | } |
4689 | } else { | |
4690 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
4691 | if (err) { | |
4692 | dev_err(&pdev->dev, "no usable DMA configuration\n"); | |
d6ce2628 | 4693 | goto out_unmap_bar0; |
b8ff05a9 DM |
4694 | } |
4695 | } | |
4696 | ||
4697 | pci_enable_pcie_error_reporting(pdev); | |
ef306b50 | 4698 | enable_pcie_relaxed_ordering(pdev); |
b8ff05a9 DM |
4699 | pci_set_master(pdev); |
4700 | pci_save_state(pdev); | |
4701 | ||
4702 | adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); | |
4703 | if (!adapter) { | |
4704 | err = -ENOMEM; | |
d6ce2628 | 4705 | goto out_unmap_bar0; |
b8ff05a9 | 4706 | } |
7829451c | 4707 | adap_idx++; |
b8ff05a9 | 4708 | |
29aaee65 AB |
4709 | adapter->workq = create_singlethread_workqueue("cxgb4"); |
4710 | if (!adapter->workq) { | |
4711 | err = -ENOMEM; | |
4712 | goto out_free_adapter; | |
4713 | } | |
4714 | ||
7f080c3f HS |
4715 | adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + |
4716 | (sizeof(struct mbox_cmd) * | |
4717 | T4_OS_LOG_MBOX_CMDS), | |
4718 | GFP_KERNEL); | |
4719 | if (!adapter->mbox_log) { | |
4720 | err = -ENOMEM; | |
4721 | goto out_free_adapter; | |
4722 | } | |
4723 | adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; | |
4724 | ||
144be3d9 GS |
4725 | /* PCI device has been enabled */ |
4726 | adapter->flags |= DEV_ENABLED; | |
4727 | ||
d6ce2628 | 4728 | adapter->regs = regs; |
b8ff05a9 DM |
4729 | adapter->pdev = pdev; |
4730 | adapter->pdev_dev = &pdev->dev; | |
0de72738 | 4731 | adapter->name = pci_name(pdev); |
3069ee9b | 4732 | adapter->mbox = func; |
b2612722 | 4733 | adapter->pf = func; |
ea1e76f7 | 4734 | adapter->msg_enable = DFLT_MSG_ENABLE; |
b8ff05a9 DM |
4735 | memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); |
4736 | ||
4737 | spin_lock_init(&adapter->stats_lock); | |
4738 | spin_lock_init(&adapter->tid_release_lock); | |
e327c225 | 4739 | spin_lock_init(&adapter->win0_lock); |
4055ae5e HS |
4740 | spin_lock_init(&adapter->mbox_lock); |
4741 | ||
4742 | INIT_LIST_HEAD(&adapter->mlist.list); | |
b8ff05a9 DM |
4743 | |
4744 | INIT_WORK(&adapter->tid_release_task, process_tid_release_list); | |
881806bc VP |
4745 | INIT_WORK(&adapter->db_full_task, process_db_full); |
4746 | INIT_WORK(&adapter->db_drop_task, process_db_drop); | |
b8ff05a9 DM |
4747 | |
4748 | err = t4_prep_adapter(adapter); | |
4749 | if (err) | |
d6ce2628 HS |
4750 | goto out_free_adapter; |
4751 | ||
22adfe0a | 4752 | |
d14807dd | 4753 | if (!is_t4(adapter->params.chip)) { |
f612b815 HS |
4754 | s_qpp = (QUEUESPERPAGEPF0_S + |
4755 | (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * | |
b2612722 | 4756 | adapter->pf); |
f612b815 HS |
4757 | qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, |
4758 | SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); | |
22adfe0a SR |
4759 | num_seg = PAGE_SIZE / SEGMENT_SIZE; |
4760 | ||
4761 | /* Each segment size is 128B. Write coalescing is enabled only | |
4762 | * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the | |
4763 | * queue is less no of segments that can be accommodated in | |
4764 | * a page size. | |
4765 | */ | |
4766 | if (qpp > num_seg) { | |
4767 | dev_err(&pdev->dev, | |
4768 | "Incorrect number of egress queues per page\n"); | |
4769 | err = -EINVAL; | |
d6ce2628 | 4770 | goto out_free_adapter; |
22adfe0a SR |
4771 | } |
4772 | adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), | |
4773 | pci_resource_len(pdev, 2)); | |
4774 | if (!adapter->bar2) { | |
4775 | dev_err(&pdev->dev, "cannot map device bar2 region\n"); | |
4776 | err = -ENOMEM; | |
d6ce2628 | 4777 | goto out_free_adapter; |
22adfe0a SR |
4778 | } |
4779 | } | |
4780 | ||
636f9d37 | 4781 | setup_memwin(adapter); |
b8ff05a9 | 4782 | err = adap_init0(adapter); |
5b377d11 HS |
4783 | #ifdef CONFIG_DEBUG_FS |
4784 | bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); | |
4785 | #endif | |
636f9d37 | 4786 | setup_memwin_rdma(adapter); |
b8ff05a9 DM |
4787 | if (err) |
4788 | goto out_unmap_bar; | |
4789 | ||
2a485cf7 HS |
4790 | /* configure SGE_STAT_CFG_A to read WC stats */ |
4791 | if (!is_t4(adapter->params.chip)) | |
676d6a75 HS |
4792 | t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | |
4793 | (is_t5(adapter->params.chip) ? STATMODE_V(0) : | |
4794 | T6_STATMODE_V(0))); | |
2a485cf7 | 4795 | |
b8ff05a9 | 4796 | for_each_port(adapter, i) { |
b8ff05a9 DM |
4797 | netdev = alloc_etherdev_mq(sizeof(struct port_info), |
4798 | MAX_ETH_QSETS); | |
4799 | if (!netdev) { | |
4800 | err = -ENOMEM; | |
4801 | goto out_free_dev; | |
4802 | } | |
4803 | ||
4804 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
4805 | ||
4806 | adapter->port[i] = netdev; | |
4807 | pi = netdev_priv(netdev); | |
4808 | pi->adapter = adapter; | |
4809 | pi->xact_addr_filt = -1; | |
b8ff05a9 | 4810 | pi->port_id = i; |
b8ff05a9 DM |
4811 | netdev->irq = pdev->irq; |
4812 | ||
2ed28baa MM |
4813 | netdev->hw_features = NETIF_F_SG | TSO_FLAGS | |
4814 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
4815 | NETIF_F_RXCSUM | NETIF_F_RXHASH | | |
d8931847 RL |
4816 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | |
4817 | NETIF_F_HW_TC; | |
c8f44aff MM |
4818 | if (highdma) |
4819 | netdev->hw_features |= NETIF_F_HIGHDMA; | |
4820 | netdev->features |= netdev->hw_features; | |
b8ff05a9 DM |
4821 | netdev->vlan_features = netdev->features & VLAN_FEAT; |
4822 | ||
01789349 JP |
4823 | netdev->priv_flags |= IFF_UNICAST_FLT; |
4824 | ||
d894be57 JW |
4825 | /* MTU range: 81 - 9600 */ |
4826 | netdev->min_mtu = 81; | |
4827 | netdev->max_mtu = MAX_MTU; | |
4828 | ||
b8ff05a9 | 4829 | netdev->netdev_ops = &cxgb4_netdev_ops; |
688848b1 AB |
4830 | #ifdef CONFIG_CHELSIO_T4_DCB |
4831 | netdev->dcbnl_ops = &cxgb4_dcb_ops; | |
4832 | cxgb4_dcb_state_init(netdev); | |
4833 | #endif | |
812034f1 | 4834 | cxgb4_set_ethtool_ops(netdev); |
b8ff05a9 DM |
4835 | } |
4836 | ||
4837 | pci_set_drvdata(pdev, adapter); | |
4838 | ||
4839 | if (adapter->flags & FW_OK) { | |
060e0c75 | 4840 | err = t4_port_init(adapter, func, func, 0); |
b8ff05a9 DM |
4841 | if (err) |
4842 | goto out_free_dev; | |
098ef6c2 HS |
4843 | } else if (adapter->params.nports == 1) { |
4844 | /* If we don't have a connection to the firmware -- possibly | |
4845 | * because of an error -- grab the raw VPD parameters so we | |
4846 | * can set the proper MAC Address on the debug network | |
4847 | * interface that we've created. | |
4848 | */ | |
4849 | u8 hw_addr[ETH_ALEN]; | |
4850 | u8 *na = adapter->params.vpd.na; | |
4851 | ||
4852 | err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); | |
4853 | if (!err) { | |
4854 | for (i = 0; i < ETH_ALEN; i++) | |
4855 | hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + | |
4856 | hex2val(na[2 * i + 1])); | |
4857 | t4_set_hw_addr(adapter, 0, hw_addr); | |
4858 | } | |
b8ff05a9 DM |
4859 | } |
4860 | ||
098ef6c2 | 4861 | /* Configure queues and allocate tables now, they can be needed as |
b8ff05a9 DM |
4862 | * soon as the first register_netdev completes. |
4863 | */ | |
4864 | cfg_queues(adapter); | |
4865 | ||
5be9ed8d | 4866 | adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); |
b8ff05a9 DM |
4867 | if (!adapter->l2t) { |
4868 | /* We tolerate a lack of L2T, giving up some functionality */ | |
4869 | dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); | |
4870 | adapter->params.offload = 0; | |
4871 | } | |
4872 | ||
b5a02f50 | 4873 | #if IS_ENABLED(CONFIG_IPV6) |
eb72f74f HS |
4874 | if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) && |
4875 | (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { | |
4876 | /* CLIP functionality is not present in hardware, | |
4877 | * hence disable all offload features | |
b5a02f50 AB |
4878 | */ |
4879 | dev_warn(&pdev->dev, | |
eb72f74f | 4880 | "CLIP not enabled in hardware, continuing\n"); |
b5a02f50 | 4881 | adapter->params.offload = 0; |
eb72f74f HS |
4882 | } else { |
4883 | adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, | |
4884 | adapter->clipt_end); | |
4885 | if (!adapter->clipt) { | |
4886 | /* We tolerate a lack of clip_table, giving up | |
4887 | * some functionality | |
4888 | */ | |
4889 | dev_warn(&pdev->dev, | |
4890 | "could not allocate Clip table, continuing\n"); | |
4891 | adapter->params.offload = 0; | |
4892 | } | |
b5a02f50 AB |
4893 | } |
4894 | #endif | |
b72a32da RL |
4895 | |
4896 | for_each_port(adapter, i) { | |
4897 | pi = adap2pinfo(adapter, i); | |
4898 | pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls); | |
4899 | if (!pi->sched_tbl) | |
4900 | dev_warn(&pdev->dev, | |
4901 | "could not activate scheduling on port %d\n", | |
4902 | i); | |
4903 | } | |
4904 | ||
578b46b9 | 4905 | if (tid_init(&adapter->tids) < 0) { |
b8ff05a9 DM |
4906 | dev_warn(&pdev->dev, "could not allocate TID table, " |
4907 | "continuing\n"); | |
4908 | adapter->params.offload = 0; | |
d8931847 RL |
4909 | } else { |
4910 | adapter->tc_u32 = cxgb4_init_tc_u32(adapter, | |
4911 | CXGB4_MAX_LINK_HANDLE); | |
4912 | if (!adapter->tc_u32) | |
4913 | dev_warn(&pdev->dev, | |
4914 | "could not offload tc u32, continuing\n"); | |
b8ff05a9 DM |
4915 | } |
4916 | ||
9a1bb9f6 HS |
4917 | if (is_offload(adapter)) { |
4918 | if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { | |
4919 | u32 hash_base, hash_reg; | |
4920 | ||
4921 | if (chip <= CHELSIO_T5) { | |
4922 | hash_reg = LE_DB_TID_HASHBASE_A; | |
4923 | hash_base = t4_read_reg(adapter, hash_reg); | |
4924 | adapter->tids.hash_base = hash_base / 4; | |
4925 | } else { | |
4926 | hash_reg = T6_LE_DB_HASH_TID_BASE_A; | |
4927 | hash_base = t4_read_reg(adapter, hash_reg); | |
4928 | adapter->tids.hash_base = hash_base; | |
4929 | } | |
4930 | } | |
4931 | } | |
4932 | ||
f7cabcdd DM |
4933 | /* See what interrupts we'll be using */ |
4934 | if (msi > 1 && enable_msix(adapter) == 0) | |
4935 | adapter->flags |= USING_MSIX; | |
94cdb8bb | 4936 | else if (msi > 0 && pci_enable_msi(pdev) == 0) { |
f7cabcdd | 4937 | adapter->flags |= USING_MSI; |
94cdb8bb HS |
4938 | if (msi > 1) |
4939 | free_msix_info(adapter); | |
4940 | } | |
f7cabcdd | 4941 | |
547fd272 HS |
4942 | /* check for PCI Express bandwidth capabiltites */ |
4943 | cxgb4_check_pcie_caps(adapter); | |
4944 | ||
671b0060 DM |
4945 | err = init_rss(adapter); |
4946 | if (err) | |
4947 | goto out_free_dev; | |
4948 | ||
b8ff05a9 DM |
4949 | /* |
4950 | * The card is now ready to go. If any errors occur during device | |
4951 | * registration we do not fail the whole card but rather proceed only | |
4952 | * with the ports we manage to register successfully. However we must | |
4953 | * register at least one net device. | |
4954 | */ | |
4955 | for_each_port(adapter, i) { | |
a57cabe0 | 4956 | pi = adap2pinfo(adapter, i); |
d2a007ab | 4957 | adapter->port[i]->dev_port = pi->lport; |
a57cabe0 DM |
4958 | netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); |
4959 | netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); | |
4960 | ||
b8ff05a9 DM |
4961 | err = register_netdev(adapter->port[i]); |
4962 | if (err) | |
b1a3c2b6 | 4963 | break; |
b1a3c2b6 DM |
4964 | adapter->chan_map[pi->tx_chan] = i; |
4965 | print_port_info(adapter->port[i]); | |
b8ff05a9 | 4966 | } |
b1a3c2b6 | 4967 | if (i == 0) { |
b8ff05a9 DM |
4968 | dev_err(&pdev->dev, "could not register any net devices\n"); |
4969 | goto out_free_dev; | |
4970 | } | |
b1a3c2b6 DM |
4971 | if (err) { |
4972 | dev_warn(&pdev->dev, "only %d net devices registered\n", i); | |
4973 | err = 0; | |
6403eab1 | 4974 | } |
b8ff05a9 DM |
4975 | |
4976 | if (cxgb4_debugfs_root) { | |
4977 | adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), | |
4978 | cxgb4_debugfs_root); | |
4979 | setup_debugfs(adapter); | |
4980 | } | |
4981 | ||
6482aa7c DLR |
4982 | /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ |
4983 | pdev->needs_freset = 1; | |
4984 | ||
0fbc81b3 HS |
4985 | if (is_uld(adapter)) { |
4986 | mutex_lock(&uld_mutex); | |
4987 | list_add_tail(&adapter->list_node, &adapter_list); | |
4988 | mutex_unlock(&uld_mutex); | |
4989 | } | |
b8ff05a9 | 4990 | |
0de72738 | 4991 | print_adapter_info(adapter); |
0fbc81b3 | 4992 | setup_fw_sge_queues(adapter); |
7829451c | 4993 | return 0; |
0de72738 | 4994 | |
8e1e6059 | 4995 | sriov: |
b8ff05a9 | 4996 | #ifdef CONFIG_PCI_IOV |
7829451c HS |
4997 | adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); |
4998 | if (!adapter) { | |
4999 | err = -ENOMEM; | |
5000 | goto free_pci_region; | |
5001 | } | |
5002 | ||
7829451c HS |
5003 | adapter->pdev = pdev; |
5004 | adapter->pdev_dev = &pdev->dev; | |
5005 | adapter->name = pci_name(pdev); | |
5006 | adapter->mbox = func; | |
5007 | adapter->pf = func; | |
5008 | adapter->regs = regs; | |
e7b48a32 | 5009 | adapter->adap_idx = adap_idx; |
7829451c HS |
5010 | adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + |
5011 | (sizeof(struct mbox_cmd) * | |
5012 | T4_OS_LOG_MBOX_CMDS), | |
5013 | GFP_KERNEL); | |
5014 | if (!adapter->mbox_log) { | |
5015 | err = -ENOMEM; | |
e7b48a32 | 5016 | goto free_adapter; |
7829451c | 5017 | } |
038c35a8 GG |
5018 | spin_lock_init(&adapter->mbox_lock); |
5019 | INIT_LIST_HEAD(&adapter->mlist.list); | |
96fe11f2 GG |
5020 | |
5021 | v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | | |
5022 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); | |
5023 | err = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 1, | |
5024 | &v, &port_vec); | |
5025 | if (err < 0) { | |
5026 | dev_err(adapter->pdev_dev, "Could not fetch port params\n"); | |
5027 | goto free_adapter; | |
5028 | } | |
5029 | ||
5030 | adapter->params.nports = hweight32(port_vec); | |
7829451c | 5031 | pci_set_drvdata(pdev, adapter); |
7829451c HS |
5032 | return 0; |
5033 | ||
7829451c HS |
5034 | free_adapter: |
5035 | kfree(adapter); | |
5036 | free_pci_region: | |
5037 | iounmap(regs); | |
5038 | pci_disable_sriov(pdev); | |
5039 | pci_release_regions(pdev); | |
5040 | return err; | |
5041 | #else | |
b8ff05a9 | 5042 | return 0; |
7829451c | 5043 | #endif |
b8ff05a9 DM |
5044 | |
5045 | out_free_dev: | |
06546391 | 5046 | free_some_resources(adapter); |
94cdb8bb HS |
5047 | if (adapter->flags & USING_MSIX) |
5048 | free_msix_info(adapter); | |
0fbc81b3 HS |
5049 | if (adapter->num_uld || adapter->num_ofld_uld) |
5050 | t4_uld_mem_free(adapter); | |
b8ff05a9 | 5051 | out_unmap_bar: |
d14807dd | 5052 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5053 | iounmap(adapter->bar2); |
b8ff05a9 | 5054 | out_free_adapter: |
29aaee65 AB |
5055 | if (adapter->workq) |
5056 | destroy_workqueue(adapter->workq); | |
5057 | ||
7f080c3f | 5058 | kfree(adapter->mbox_log); |
b8ff05a9 | 5059 | kfree(adapter); |
d6ce2628 HS |
5060 | out_unmap_bar0: |
5061 | iounmap(regs); | |
b8ff05a9 DM |
5062 | out_disable_device: |
5063 | pci_disable_pcie_error_reporting(pdev); | |
5064 | pci_disable_device(pdev); | |
5065 | out_release_regions: | |
5066 | pci_release_regions(pdev); | |
b8ff05a9 DM |
5067 | return err; |
5068 | } | |
5069 | ||
91744948 | 5070 | static void remove_one(struct pci_dev *pdev) |
b8ff05a9 DM |
5071 | { |
5072 | struct adapter *adapter = pci_get_drvdata(pdev); | |
5073 | ||
7829451c HS |
5074 | if (!adapter) { |
5075 | pci_release_regions(pdev); | |
5076 | return; | |
5077 | } | |
636f9d37 | 5078 | |
7829451c | 5079 | if (adapter->pf == 4) { |
b8ff05a9 DM |
5080 | int i; |
5081 | ||
29aaee65 AB |
5082 | /* Tear down per-adapter Work Queue first since it can contain |
5083 | * references to our adapter data structure. | |
5084 | */ | |
5085 | destroy_workqueue(adapter->workq); | |
5086 | ||
0fbc81b3 | 5087 | if (is_uld(adapter)) |
b8ff05a9 DM |
5088 | detach_ulds(adapter); |
5089 | ||
b37987e8 HS |
5090 | disable_interrupts(adapter); |
5091 | ||
b8ff05a9 | 5092 | for_each_port(adapter, i) |
8f3a7676 | 5093 | if (adapter->port[i]->reg_state == NETREG_REGISTERED) |
b8ff05a9 DM |
5094 | unregister_netdev(adapter->port[i]); |
5095 | ||
9f16dc2e | 5096 | debugfs_remove_recursive(adapter->debugfs_root); |
b8ff05a9 | 5097 | |
f2b7e78d VP |
5098 | /* If we allocated filters, free up state associated with any |
5099 | * valid filters ... | |
5100 | */ | |
578b46b9 | 5101 | clear_all_filters(adapter); |
f2b7e78d | 5102 | |
aaefae9b DM |
5103 | if (adapter->flags & FULL_INIT_DONE) |
5104 | cxgb_down(adapter); | |
b8ff05a9 | 5105 | |
94cdb8bb HS |
5106 | if (adapter->flags & USING_MSIX) |
5107 | free_msix_info(adapter); | |
0fbc81b3 HS |
5108 | if (adapter->num_uld || adapter->num_ofld_uld) |
5109 | t4_uld_mem_free(adapter); | |
06546391 | 5110 | free_some_resources(adapter); |
b5a02f50 AB |
5111 | #if IS_ENABLED(CONFIG_IPV6) |
5112 | t4_cleanup_clip_tbl(adapter); | |
5113 | #endif | |
b8ff05a9 | 5114 | iounmap(adapter->regs); |
d14807dd | 5115 | if (!is_t4(adapter->params.chip)) |
22adfe0a | 5116 | iounmap(adapter->bar2); |
b8ff05a9 | 5117 | pci_disable_pcie_error_reporting(pdev); |
144be3d9 GS |
5118 | if ((adapter->flags & DEV_ENABLED)) { |
5119 | pci_disable_device(pdev); | |
5120 | adapter->flags &= ~DEV_ENABLED; | |
5121 | } | |
b8ff05a9 | 5122 | pci_release_regions(pdev); |
7f080c3f | 5123 | kfree(adapter->mbox_log); |
ee9a33b2 | 5124 | synchronize_rcu(); |
8b662fe7 | 5125 | kfree(adapter); |
7829451c HS |
5126 | } |
5127 | #ifdef CONFIG_PCI_IOV | |
5128 | else { | |
e7b48a32 | 5129 | if (adapter->port[0]) |
7829451c | 5130 | unregister_netdev(adapter->port[0]); |
7829451c | 5131 | iounmap(adapter->regs); |
661dbeb9 | 5132 | kfree(adapter->vfinfo); |
7829451c HS |
5133 | kfree(adapter); |
5134 | pci_disable_sriov(pdev); | |
b8ff05a9 | 5135 | pci_release_regions(pdev); |
7829451c HS |
5136 | } |
5137 | #endif | |
b8ff05a9 DM |
5138 | } |
5139 | ||
0fbc81b3 HS |
5140 | /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt |
5141 | * delivery. This is essentially a stripped down version of the PCI remove() | |
5142 | * function where we do the minimal amount of work necessary to shutdown any | |
5143 | * further activity. | |
5144 | */ | |
5145 | static void shutdown_one(struct pci_dev *pdev) | |
5146 | { | |
5147 | struct adapter *adapter = pci_get_drvdata(pdev); | |
5148 | ||
5149 | /* As with remove_one() above (see extended comment), we only want do | |
5150 | * do cleanup on PCI Devices which went all the way through init_one() | |
5151 | * ... | |
5152 | */ | |
5153 | if (!adapter) { | |
5154 | pci_release_regions(pdev); | |
5155 | return; | |
5156 | } | |
5157 | ||
5158 | if (adapter->pf == 4) { | |
5159 | int i; | |
5160 | ||
5161 | for_each_port(adapter, i) | |
5162 | if (adapter->port[i]->reg_state == NETREG_REGISTERED) | |
5163 | cxgb_close(adapter->port[i]); | |
5164 | ||
5165 | t4_uld_clean_up(adapter); | |
5166 | disable_interrupts(adapter); | |
5167 | disable_msi(adapter); | |
5168 | ||
5169 | t4_sge_stop(adapter); | |
5170 | if (adapter->flags & FW_OK) | |
5171 | t4_fw_bye(adapter, adapter->mbox); | |
5172 | } | |
5173 | #ifdef CONFIG_PCI_IOV | |
5174 | else { | |
5175 | if (adapter->port[0]) | |
5176 | unregister_netdev(adapter->port[0]); | |
5177 | iounmap(adapter->regs); | |
5178 | kfree(adapter->vfinfo); | |
5179 | kfree(adapter); | |
5180 | pci_disable_sriov(pdev); | |
5181 | pci_release_regions(pdev); | |
5182 | } | |
5183 | #endif | |
5184 | } | |
5185 | ||
b8ff05a9 DM |
5186 | static struct pci_driver cxgb4_driver = { |
5187 | .name = KBUILD_MODNAME, | |
5188 | .id_table = cxgb4_pci_tbl, | |
5189 | .probe = init_one, | |
91744948 | 5190 | .remove = remove_one, |
0fbc81b3 | 5191 | .shutdown = shutdown_one, |
b6244201 HS |
5192 | #ifdef CONFIG_PCI_IOV |
5193 | .sriov_configure = cxgb4_iov_configure, | |
5194 | #endif | |
204dc3c0 | 5195 | .err_handler = &cxgb4_eeh, |
b8ff05a9 DM |
5196 | }; |
5197 | ||
5198 | static int __init cxgb4_init_module(void) | |
5199 | { | |
5200 | int ret; | |
5201 | ||
5202 | /* Debugfs support is optional, just warn if this fails */ | |
5203 | cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); | |
5204 | if (!cxgb4_debugfs_root) | |
428ac43f | 5205 | pr_warn("could not create debugfs entry, continuing\n"); |
b8ff05a9 DM |
5206 | |
5207 | ret = pci_register_driver(&cxgb4_driver); | |
29aaee65 | 5208 | if (ret < 0) |
b8ff05a9 | 5209 | debugfs_remove(cxgb4_debugfs_root); |
01bcca68 | 5210 | |
1bb60376 | 5211 | #if IS_ENABLED(CONFIG_IPV6) |
b5a02f50 AB |
5212 | if (!inet6addr_registered) { |
5213 | register_inet6addr_notifier(&cxgb4_inet6addr_notifier); | |
5214 | inet6addr_registered = true; | |
5215 | } | |
1bb60376 | 5216 | #endif |
01bcca68 | 5217 | |
b8ff05a9 DM |
5218 | return ret; |
5219 | } | |
5220 | ||
5221 | static void __exit cxgb4_cleanup_module(void) | |
5222 | { | |
1bb60376 | 5223 | #if IS_ENABLED(CONFIG_IPV6) |
1793c798 | 5224 | if (inet6addr_registered) { |
b5a02f50 AB |
5225 | unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); |
5226 | inet6addr_registered = false; | |
5227 | } | |
1bb60376 | 5228 | #endif |
b8ff05a9 DM |
5229 | pci_unregister_driver(&cxgb4_driver); |
5230 | debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ | |
5231 | } | |
5232 | ||
5233 | module_init(cxgb4_init_module); | |
5234 | module_exit(cxgb4_cleanup_module); |