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Merge branch 'liquidio-fw-loading'
[thirdparty/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4_main.c
CommitLineData
b8ff05a9
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
b72a32da 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
b8ff05a9
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
01789349 44#include <linux/if.h>
b8ff05a9
DM		 45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
01bcca68 63#include <net/addrconf.h>
1ef8019b 64#include <net/bonding.h>
b5a02f50 65#include <net/addrconf.h>
7c0f6ba6 66#include <linux/uaccess.h>
c5a8c0f3 67#include <linux/crash_dump.h>
b8ff05a9
DM		 68
69#include "cxgb4.h"
d57fd6ca 70#include "cxgb4_filter.h"
b8ff05a9 71#include "t4_regs.h"
f612b815 72#include "t4_values.h"
b8ff05a9
DM		 73#include "t4_msg.h"
74#include "t4fw_api.h"
cd6c2f12 75#include "t4fw_version.h"
688848b1 76#include "cxgb4_dcb.h"
fd88b31a 77#include "cxgb4_debugfs.h"
b5a02f50 78#include "clip_tbl.h"
b8ff05a9 79#include "l2t.h"
b72a32da 80#include "sched.h"
d8931847 81#include "cxgb4_tc_u32.h"
6a345b3d 82#include "cxgb4_tc_flower.h"
a4569504 83#include "cxgb4_ptp.h"
b8ff05a9 84
812034f1
HS		 85char cxgb4_driver_name[] = KBUILD_MODNAME;
86
01bcca68
VP		 87#ifdef DRV_VERSION
88#undef DRV_VERSION
89#endif
3a7f8554 90#define DRV_VERSION "2.0.0-ko"
812034f1 91const char cxgb4_driver_version[] = DRV_VERSION;
52a5f846 92#define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
b8ff05a9 93
b8ff05a9
DM		 94#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
95 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
96 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
97
3fedeab1
HS		 98/* Macros needed to support the PCI Device ID Table ...
99 */
100#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
768ffc66 101 static const struct pci_device_id cxgb4_pci_tbl[] = {
3fedeab1 102#define CH_PCI_DEVICE_ID_FUNCTION 0x4
b8ff05a9 103
3fedeab1
HS		 104/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
105 * called for both.
106 */
107#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
108
109#define CH_PCI_ID_TABLE_ENTRY(devid) \
110 {PCI_VDEVICE(CHELSIO, (devid)), 4}
111
112#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
113 { 0, } \
114 }
115
116#include "t4_pci_id_tbl.h"
b8ff05a9 117
16e47624 118#define FW4_FNAME "cxgb4/t4fw.bin"
0a57a536 119#define FW5_FNAME "cxgb4/t5fw.bin"
3ccc6cf7 120#define FW6_FNAME "cxgb4/t6fw.bin"
16e47624 121#define FW4_CFNAME "cxgb4/t4-config.txt"
0a57a536 122#define FW5_CFNAME "cxgb4/t5-config.txt"
3ccc6cf7 123#define FW6_CFNAME "cxgb4/t6-config.txt"
01b69614
HS		 124#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
125#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
126#define PHY_AQ1202_DEVICEID 0x4409
127#define PHY_BCM84834_DEVICEID 0x4486
b8ff05a9
DM		 128
129MODULE_DESCRIPTION(DRV_DESC);
130MODULE_AUTHOR("Chelsio Communications");
131MODULE_LICENSE("Dual BSD/GPL");
132MODULE_VERSION(DRV_VERSION);
133MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
16e47624 134MODULE_FIRMWARE(FW4_FNAME);
0a57a536 135MODULE_FIRMWARE(FW5_FNAME);
52a5f846 136MODULE_FIRMWARE(FW6_FNAME);
b8ff05a9 137
b8ff05a9
DM		 138/*
139 * The driver uses the best interrupt scheme available on a platform in the
140 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
141 * of these schemes the driver may consider as follows:
142 *
143 * msi = 2: choose from among all three options
144 * msi = 1: only consider MSI and INTx interrupts
145 * msi = 0: force INTx interrupts
146 */
147static int msi = 2;
148
149module_param(msi, int, 0644);
150MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
151
636f9d37
VP		 152/*
153 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
154 * offset by 2 bytes in order to have the IP headers line up on 4-byte
155 * boundaries. This is a requirement for many architectures which will throw
156 * a machine check fault if an attempt is made to access one of the 4-byte IP
157 * header fields on a non-4-byte boundary. And it's a major performance issue
158 * even on some architectures which allow it like some implementations of the
159 * x86 ISA. However, some architectures don't mind this and for some very
160 * edge-case performance sensitive applications (like forwarding large volumes
161 * of small packets), setting this DMA offset to 0 will decrease the number of
162 * PCI-E Bus transfers enough to measurably affect performance.
163 */
164static int rx_dma_offset = 2;
165
688848b1
AB		 166/* TX Queue select used to determine what algorithm to use for selecting TX
167 * queue. Select between the kernel provided function (select_queue=0) or user
168 * cxgb_select_queue function (select_queue=1)
169 *
170 * Default: select_queue=0
171 */
172static int select_queue;
173module_param(select_queue, int, 0644);
174MODULE_PARM_DESC(select_queue,
175 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
176
b8ff05a9
DM		 177static struct dentry *cxgb4_debugfs_root;
178
94cdb8bb
HS		 179LIST_HEAD(adapter_list);
180DEFINE_MUTEX(uld_mutex);
b8ff05a9
DM		 181
182static void link_report(struct net_device *dev)
183{
184 if (!netif_carrier_ok(dev))
185 netdev_info(dev, "link down\n");
186 else {
187 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
188
85412255 189 const char *s;
b8ff05a9
DM		 190 const struct port_info *p = netdev_priv(dev);
191
192 switch (p->link_cfg.speed) {
5e78f7fd
GG		 193 case 100:
194 s = "100Mbps";
b8ff05a9 195 break;
e8b39015 196 case 1000:
5e78f7fd 197 s = "1Gbps";
b8ff05a9 198 break;
5e78f7fd
GG		 199 case 10000:
200 s = "10Gbps";
201 break;
202 case 25000:
203 s = "25Gbps";
b8ff05a9 204 break;
e8b39015 205 case 40000:
72aca4bf
KS		 206 s = "40Gbps";
207 break;
5e78f7fd
GG		 208 case 100000:
209 s = "100Gbps";
210 break;
85412255
HS		 211 default:
212 pr_info("%s: unsupported speed: %d\n",
213 dev->name, p->link_cfg.speed);
214 return;
b8ff05a9
DM		 215 }
216
217 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
218 fc[p->link_cfg.fc]);
219 }
220}
221
688848b1
AB		 222#ifdef CONFIG_CHELSIO_T4_DCB
223/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
224static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
225{
226 struct port_info *pi = netdev_priv(dev);
227 struct adapter *adap = pi->adapter;
228 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
229 int i;
230
231 /* We use a simple mapping of Port TX Queue Index to DCB
232 * Priority when we're enabling DCB.
233 */
234 for (i = 0; i < pi->nqsets; i++, txq++) {
235 u32 name, value;
236 int err;
237
5167865a
HS		 238 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
239 FW_PARAMS_PARAM_X_V(
240 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
241 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
688848b1
AB		 242 value = enable ? i : 0xffffffff;
243
244 /* Since we can be called while atomic (from "interrupt
245 * level") we need to issue the Set Parameters Commannd
246 * without sleeping (timeout < 0).
247 */
b2612722 248 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
01b69614
HS		 249 &name, &value,
250 -FW_CMD_MAX_TIMEOUT);
688848b1
AB		 251
252 if (err)
253 dev_err(adap->pdev_dev,
254 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
255 enable ? "set" : "unset", pi->port_id, i, -err);
10b00466
AB		 256 else
257 txq->dcb_prio = value;
688848b1
AB		 258 }
259}
688848b1 260
50935857 261static int cxgb4_dcb_enabled(const struct net_device *dev)
218d48e7 262{
218d48e7
HS		 263 struct port_info *pi = netdev_priv(dev);
264
265 if (!pi->dcb.enabled)
266 return 0;
267
268 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
269 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
218d48e7 270}
7c70c4f8 271#endif /* CONFIG_CHELSIO_T4_DCB */
218d48e7 272
b8ff05a9
DM		 273void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
274{
275 struct net_device *dev = adapter->port[port_id];
276
277 /* Skip changes from disabled ports. */
278 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
279 if (link_stat)
280 netif_carrier_on(dev);
688848b1
AB		 281 else {
282#ifdef CONFIG_CHELSIO_T4_DCB
218d48e7
HS		 283 if (cxgb4_dcb_enabled(dev)) {
284 cxgb4_dcb_state_init(dev);
285 dcb_tx_queue_prio_enable(dev, false);
286 }
688848b1 287#endif /* CONFIG_CHELSIO_T4_DCB */
b8ff05a9 288 netif_carrier_off(dev);
688848b1 289 }
b8ff05a9
DM		 290
291 link_report(dev);
292 }
293}
294
295void t4_os_portmod_changed(const struct adapter *adap, int port_id)
296{
297 static const char *mod_str[] = {
a0881cab 298 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
b8ff05a9
DM		 299 };
300
301 const struct net_device *dev = adap->port[port_id];
302 const struct port_info *pi = netdev_priv(dev);
303
304 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
305 netdev_info(dev, "port module unplugged\n");
a0881cab 306 else if (pi->mod_type < ARRAY_SIZE(mod_str))
b8ff05a9 307 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
be81a2de
HS		 308 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
309 netdev_info(dev, "%s: unsupported port module inserted\n",
310 dev->name);
311 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
312 netdev_info(dev, "%s: unknown port module inserted\n",
313 dev->name);
314 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
315 netdev_info(dev, "%s: transceiver module error\n", dev->name);
316 else
317 netdev_info(dev, "%s: unknown module type %d inserted\n",
318 dev->name, pi->mod_type);
b8ff05a9
DM		 319}
320
fc08a01a
HS		 321int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
322module_param(dbfifo_int_thresh, int, 0644);
323MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
324
b8ff05a9 325/*
fc08a01a 326 * usecs to sleep while draining the dbfifo
b8ff05a9 327 */
fc08a01a
HS		 328static int dbfifo_drain_delay = 1000;
329module_param(dbfifo_drain_delay, int, 0644);
330MODULE_PARM_DESC(dbfifo_drain_delay,
331 "usecs to sleep while draining the dbfifo");
332
333static inline int cxgb4_set_addr_hash(struct port_info *pi)
b8ff05a9 334{
fc08a01a
HS		 335 struct adapter *adap = pi->adapter;
336 u64 vec = 0;
337 bool ucast = false;
338 struct hash_mac_addr *entry;
339
340 /* Calculate the hash vector for the updated list and program it */
341 list_for_each_entry(entry, &adap->mac_hlist, list) {
342 ucast |= is_unicast_ether_addr(entry->addr);
343 vec |= (1ULL << hash_mac_addr(entry->addr));
344 }
345 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
346 vec, false);
347}
348
349static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
350{
351 struct port_info *pi = netdev_priv(netdev);
352 struct adapter *adap = pi->adapter;
353 int ret;
b8ff05a9
DM		 354 u64 mhash = 0;
355 u64 uhash = 0;
fc08a01a
HS		 356 bool free = false;
357 bool ucast = is_unicast_ether_addr(mac_addr);
358 const u8 *maclist[1] = {mac_addr};
359 struct hash_mac_addr *new_entry;
360
361 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
362 NULL, ucast ? &uhash : &mhash, false);
363 if (ret < 0)
364 goto out;
365 /* if hash != 0, then add the addr to hash addr list
366 * so on the end we will calculate the hash for the
367 * list and program it
368 */
369 if (uhash || mhash) {
370 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
371 if (!new_entry)
372 return -ENOMEM;
373 ether_addr_copy(new_entry->addr, mac_addr);
374 list_add_tail(&new_entry->list, &adap->mac_hlist);
375 ret = cxgb4_set_addr_hash(pi);
b8ff05a9 376 }
fc08a01a
HS		 377out:
378 return ret < 0 ? ret : 0;
379}
b8ff05a9 380
fc08a01a
HS		 381static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
382{
383 struct port_info *pi = netdev_priv(netdev);
384 struct adapter *adap = pi->adapter;
385 int ret;
386 const u8 *maclist[1] = {mac_addr};
387 struct hash_mac_addr *entry, *tmp;
b8ff05a9 388
fc08a01a
HS		 389 /* If the MAC address to be removed is in the hash addr
390 * list, delete it from the list and update hash vector
391 */
392 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
393 if (ether_addr_equal(entry->addr, mac_addr)) {
394 list_del(&entry->list);
395 kfree(entry);
396 return cxgb4_set_addr_hash(pi);
b8ff05a9
DM		 397 }
398 }
399
fc08a01a
HS		 400 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
401 return ret < 0 ? -EINVAL : 0;
b8ff05a9
DM		 402}
403
404/*
405 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
406 * If @mtu is -1 it is left unchanged.
407 */
408static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
409{
b8ff05a9 410 struct port_info *pi = netdev_priv(dev);
fc08a01a 411 struct adapter *adapter = pi->adapter;
b8ff05a9 412
d01f7abc
HS		 413 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
414 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
fc08a01a
HS		 415
416 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
417 (dev->flags & IFF_PROMISC) ? 1 : 0,
418 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
419 sleep_ok);
b8ff05a9
DM		 420}
421
422/**
423 * link_start - enable a port
424 * @dev: the port to enable
425 *
426 * Performs the MAC and PHY actions needed to enable a port.
427 */
428static int link_start(struct net_device *dev)
429{
430 int ret;
431 struct port_info *pi = netdev_priv(dev);
b2612722 432 unsigned int mb = pi->adapter->pf;
b8ff05a9
DM		 433
434 /*
435 * We do not set address filters and promiscuity here, the stack does
436 * that step explicitly.
437 */
060e0c75 438 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
f646968f 439 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
b8ff05a9 440 if (ret == 0) {
060e0c75 441 ret = t4_change_mac(pi->adapter, mb, pi->viid,
b8ff05a9 442 pi->xact_addr_filt, dev->dev_addr, true,
b6bd29e7 443 true);
b8ff05a9
DM		 444 if (ret >= 0) {
445 pi->xact_addr_filt = ret;
446 ret = 0;
447 }
448 }
449 if (ret == 0)
4036da90 450 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
060e0c75 451 &pi->link_cfg);
30f00847
AB		 452 if (ret == 0) {
453 local_bh_disable();
688848b1
AB		 454 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
455 true, CXGB4_DCB_ENABLED);
30f00847
AB		 456 local_bh_enable();
457 }
688848b1 458
b8ff05a9
DM		 459 return ret;
460}
461
688848b1
AB		 462#ifdef CONFIG_CHELSIO_T4_DCB
463/* Handle a Data Center Bridging update message from the firmware. */
464static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
465{
2b5fb1f2 466 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
134491fd 467 struct net_device *dev = adap->port[adap->chan_map[port]];
688848b1
AB		 468 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
469 int new_dcb_enabled;
470
471 cxgb4_dcb_handle_fw_update(adap, pcmd);
472 new_dcb_enabled = cxgb4_dcb_enabled(dev);
473
474 /* If the DCB has become enabled or disabled on the port then we're
475 * going to need to set up/tear down DCB Priority parameters for the
476 * TX Queues associated with the port.
477 */
478 if (new_dcb_enabled != old_dcb_enabled)
479 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
480}
481#endif /* CONFIG_CHELSIO_T4_DCB */
482
f2b7e78d 483/* Response queue handler for the FW event queue.
b8ff05a9
DM		 484 */
485static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
486 const struct pkt_gl *gl)
487{
488 u8 opcode = ((const struct rss_header *)rsp)->opcode;
489
490 rsp++; /* skip RSS header */
b407a4a9
VP		 491
492 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
493 */
494 if (unlikely(opcode == CPL_FW4_MSG &&
495 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
496 rsp++;
497 opcode = ((const struct rss_header *)rsp)->opcode;
498 rsp++;
499 if (opcode != CPL_SGE_EGR_UPDATE) {
500 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
501 , opcode);
502 goto out;
503 }
504 }
505
b8ff05a9
DM		 506 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
507 const struct cpl_sge_egr_update *p = (void *)rsp;
bdc590b9 508 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
e46dab4d 509 struct sge_txq *txq;
b8ff05a9 510
e46dab4d 511 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
b8ff05a9 512 txq->restarts++;
ab677ff4 513 if (txq->q_type == CXGB4_TXQ_ETH) {
b8ff05a9
DM		 514 struct sge_eth_txq *eq;
515
516 eq = container_of(txq, struct sge_eth_txq, q);
517 netif_tx_wake_queue(eq->txq);
518 } else {
ab677ff4 519 struct sge_uld_txq *oq;
b8ff05a9 520
ab677ff4 521 oq = container_of(txq, struct sge_uld_txq, q);
b8ff05a9
DM		 522 tasklet_schedule(&oq->qresume_tsk);
523 }
524 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
525 const struct cpl_fw6_msg *p = (void *)rsp;
526
688848b1
AB		 527#ifdef CONFIG_CHELSIO_T4_DCB
528 const struct fw_port_cmd *pcmd = (const void *)p->data;
e2ac9628 529 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
688848b1 530 unsigned int action =
2b5fb1f2 531 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
688848b1
AB		 532
533 if (cmd == FW_PORT_CMD &&
c3168cab
GG		 534 (action == FW_PORT_ACTION_GET_PORT_INFO ||
535 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
2b5fb1f2 536 int port = FW_PORT_CMD_PORTID_G(
688848b1 537 be32_to_cpu(pcmd->op_to_portid));
c3168cab
GG		 538 struct net_device *dev;
539 int dcbxdis, state_input;
540
541 dev = q->adap->port[q->adap->chan_map[port]];
542 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
543 ? !!(pcmd->u.info.dcbxdis_pkd &
544 FW_PORT_CMD_DCBXDIS_F)
545 : !!(pcmd->u.info32.lstatus32_to_cbllen32 &
546 FW_PORT_CMD_DCBXDIS32_F));
547 state_input = (dcbxdis
548 ? CXGB4_DCB_INPUT_FW_DISABLED
549 : CXGB4_DCB_INPUT_FW_ENABLED);
688848b1
AB		 550
551 cxgb4_dcb_state_fsm(dev, state_input);
552 }
553
554 if (cmd == FW_PORT_CMD &&
555 action == FW_PORT_ACTION_L2_DCB_CFG)
556 dcb_rpl(q->adap, pcmd);
557 else
558#endif
559 if (p->type == 0)
560 t4_handle_fw_rpl(q->adap, p->data);
b8ff05a9
DM		 561 } else if (opcode == CPL_L2T_WRITE_RPL) {
562 const struct cpl_l2t_write_rpl *p = (void *)rsp;
563
564 do_l2t_write_rpl(q->adap, p);
f2b7e78d
VP		 565 } else if (opcode == CPL_SET_TCB_RPL) {
566 const struct cpl_set_tcb_rpl *p = (void *)rsp;
567
568 filter_rpl(q->adap, p);
b8ff05a9
DM		 569 } else
570 dev_err(q->adap->pdev_dev,
571 "unexpected CPL %#x on FW event queue\n", opcode);
b407a4a9 572out:
b8ff05a9
DM		 573 return 0;
574}
575
b8ff05a9
DM		 576static void disable_msi(struct adapter *adapter)
577{
578 if (adapter->flags & USING_MSIX) {
579 pci_disable_msix(adapter->pdev);
580 adapter->flags &= ~USING_MSIX;
581 } else if (adapter->flags & USING_MSI) {
582 pci_disable_msi(adapter->pdev);
583 adapter->flags &= ~USING_MSI;
584 }
585}
586
587/*
588 * Interrupt handler for non-data events used with MSI-X.
589 */
590static irqreturn_t t4_nondata_intr(int irq, void *cookie)
591{
592 struct adapter *adap = cookie;
0d804338 593 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
b8ff05a9 594
0d804338 595 if (v & PFSW_F) {
b8ff05a9 596 adap->swintr = 1;
0d804338 597 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
b8ff05a9 598 }
c3c7b121
HS		 599 if (adap->flags & MASTER_PF)
600 t4_slow_intr_handler(adap);
b8ff05a9
DM		 601 return IRQ_HANDLED;
602}
603
604/*
605 * Name the MSI-X interrupts.
606 */
607static void name_msix_vecs(struct adapter *adap)
608{
ba27816c 609 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
b8ff05a9
DM		 610
611 /* non-data interrupts */
b1a3c2b6 612 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
b8ff05a9
DM		 613
614 /* FW events */
b1a3c2b6
DM		 615 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
616 adap->port[0]->name);
b8ff05a9
DM		 617
618 /* Ethernet queues */
619 for_each_port(adap, j) {
620 struct net_device *d = adap->port[j];
621 const struct port_info *pi = netdev_priv(d);
622
ba27816c 623 for (i = 0; i < pi->nqsets; i++, msi_idx++)
b8ff05a9
DM		 624 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
625 d->name, i);
b8ff05a9 626 }
b8ff05a9
DM		 627}
628
629static int request_msix_queue_irqs(struct adapter *adap)
630{
631 struct sge *s = &adap->sge;
0fbc81b3 632 int err, ethqidx;
cf38be6d 633 int msi_index = 2;
b8ff05a9
DM		 634
635 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
636 adap->msix_info[1].desc, &s->fw_evtq);
637 if (err)
638 return err;
639
640 for_each_ethrxq(s, ethqidx) {
404d9e3f
VP		 641 err = request_irq(adap->msix_info[msi_index].vec,
642 t4_sge_intr_msix, 0,
643 adap->msix_info[msi_index].desc,
b8ff05a9
DM		 644 &s->ethrxq[ethqidx].rspq);
645 if (err)
646 goto unwind;
404d9e3f 647 msi_index++;
b8ff05a9 648 }
b8ff05a9
DM		 649 return 0;
650
651unwind:
b8ff05a9 652 while (--ethqidx >= 0)
404d9e3f
VP		 653 free_irq(adap->msix_info[--msi_index].vec,
654 &s->ethrxq[ethqidx].rspq);
b8ff05a9
DM		 655 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
656 return err;
657}
658
659static void free_msix_queue_irqs(struct adapter *adap)
660{
404d9e3f 661 int i, msi_index = 2;
b8ff05a9
DM		 662 struct sge *s = &adap->sge;
663
664 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
665 for_each_ethrxq(s, i)
404d9e3f 666 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
b8ff05a9
DM		 667}
668
671b0060 669/**
812034f1 670 * cxgb4_write_rss - write the RSS table for a given port
671b0060
DM		 671 * @pi: the port
672 * @queues: array of queue indices for RSS
673 *
674 * Sets up the portion of the HW RSS table for the port's VI to distribute
675 * packets to the Rx queues in @queues.
c035e183 676 * Should never be called before setting up sge eth rx queues
671b0060 677 */
812034f1 678int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
671b0060
DM		 679{
680 u16 *rss;
681 int i, err;
c035e183
HS		 682 struct adapter *adapter = pi->adapter;
683 const struct sge_eth_rxq *rxq;
671b0060 684
c035e183 685 rxq = &adapter->sge.ethrxq[pi->first_qset];
671b0060
DM		 686 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
687 if (!rss)
688 return -ENOMEM;
689
690 /* map the queue indices to queue ids */
691 for (i = 0; i < pi->rss_size; i++, queues++)
c035e183 692 rss[i] = rxq[*queues].rspq.abs_id;
671b0060 693
b2612722 694 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
060e0c75 695 pi->rss_size, rss, pi->rss_size);
c035e183
HS		 696 /* If Tunnel All Lookup isn't specified in the global RSS
697 * Configuration, then we need to specify a default Ingress
698 * Queue for any ingress packets which aren't hashed. We'll
699 * use our first ingress queue ...
700 */
701 if (!err)
702 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
703 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
704 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
705 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
706 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
707 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
708 rss[0]);
671b0060
DM		 709 kfree(rss);
710 return err;
711}
712
b8ff05a9
DM		 713/**
714 * setup_rss - configure RSS
715 * @adap: the adapter
716 *
671b0060 717 * Sets up RSS for each port.
b8ff05a9
DM		 718 */
719static int setup_rss(struct adapter *adap)
720{
c035e183 721 int i, j, err;
b8ff05a9
DM		 722
723 for_each_port(adap, i) {
724 const struct port_info *pi = adap2pinfo(adap, i);
b8ff05a9 725
c035e183
HS		 726 /* Fill default values with equal distribution */
727 for (j = 0; j < pi->rss_size; j++)
728 pi->rss[j] = j % pi->nqsets;
729
812034f1 730 err = cxgb4_write_rss(pi, pi->rss);
b8ff05a9
DM		 731 if (err)
732 return err;
733 }
734 return 0;
735}
736
e46dab4d
DM		 737/*
738 * Return the channel of the ingress queue with the given qid.
739 */
740static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
741{
742 qid -= p->ingr_start;
743 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
744}
745
b8ff05a9
DM		 746/*
747 * Wait until all NAPI handlers are descheduled.
748 */
749static void quiesce_rx(struct adapter *adap)
750{
751 int i;
752
4b8e27a8 753 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 754 struct sge_rspq *q = adap->sge.ingr_map[i];
755
5226b791 756 if (q && q->handler)
b8ff05a9
DM		 757 napi_disable(&q->napi);
758 }
759}
760
b37987e8
HS		 761/* Disable interrupt and napi handler */
762static void disable_interrupts(struct adapter *adap)
763{
764 if (adap->flags & FULL_INIT_DONE) {
765 t4_intr_disable(adap);
766 if (adap->flags & USING_MSIX) {
767 free_msix_queue_irqs(adap);
768 free_irq(adap->msix_info[0].vec, adap);
769 } else {
770 free_irq(adap->pdev->irq, adap);
771 }
772 quiesce_rx(adap);
773 }
774}
775
b8ff05a9
DM		 776/*
777 * Enable NAPI scheduling and interrupt generation for all Rx queues.
778 */
779static void enable_rx(struct adapter *adap)
780{
781 int i;
782
4b8e27a8 783 for (i = 0; i < adap->sge.ingr_sz; i++) {
b8ff05a9
DM		 784 struct sge_rspq *q = adap->sge.ingr_map[i];
785
786 if (!q)
787 continue;
5226b791 788 if (q->handler)
b8ff05a9 789 napi_enable(&q->napi);
5226b791 790
b8ff05a9 791 /* 0-increment GTS to start the timer and enable interrupts */
f612b815
HS		 792 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
793 SEINTARM_V(q->intr_params) |
794 INGRESSQID_V(q->cntxt_id));
b8ff05a9
DM		 795 }
796}
797
1c6a5b0e 798
0fbc81b3 799static int setup_fw_sge_queues(struct adapter *adap)
b8ff05a9 800{
b8ff05a9 801 struct sge *s = &adap->sge;
0fbc81b3 802 int err = 0;
b8ff05a9 803
4b8e27a8
HS		 804 bitmap_zero(s->starving_fl, s->egr_sz);
805 bitmap_zero(s->txq_maperr, s->egr_sz);
b8ff05a9
DM		 806
807 if (adap->flags & USING_MSIX)
94cdb8bb 808 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */
b8ff05a9
DM		 809 else {
810 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
2337ba42 811 NULL, NULL, NULL, -1);
b8ff05a9
DM		 812 if (err)
813 return err;
94cdb8bb 814 adap->msi_idx = -((int)s->intrq.abs_id + 1);
b8ff05a9
DM		 815 }
816
817 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
94cdb8bb 818 adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
0fbc81b3
HS		 819 if (err)
820 t4_free_sge_resources(adap);
821 return err;
822}
823
824/**
825 * setup_sge_queues - configure SGE Tx/Rx/response queues
826 * @adap: the adapter
827 *
828 * Determines how many sets of SGE queues to use and initializes them.
829 * We support multiple queue sets per port if we have MSI-X, otherwise
830 * just one queue set per port.
831 */
832static int setup_sge_queues(struct adapter *adap)
833{
834 int err, i, j;
835 struct sge *s = &adap->sge;
d427caee 836 struct sge_uld_rxq_info *rxq_info = NULL;
0fbc81b3 837 unsigned int cmplqid = 0;
b8ff05a9 838
d427caee
GG		 839 if (is_uld(adap))
840 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
841
b8ff05a9
DM		 842 for_each_port(adap, i) {
843 struct net_device *dev = adap->port[i];
844 struct port_info *pi = netdev_priv(dev);
845 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
846 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
847
848 for (j = 0; j < pi->nqsets; j++, q++) {
94cdb8bb
HS		 849 if (adap->msi_idx > 0)
850 adap->msi_idx++;
b8ff05a9 851 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
94cdb8bb 852 adap->msi_idx, &q->fl,
145ef8a5 853 t4_ethrx_handler,
2337ba42 854 NULL,
193c4c28
AV		 855 t4_get_tp_ch_map(adap,
856 pi->tx_chan));
b8ff05a9
DM		 857 if (err)
858 goto freeout;
859 q->rspq.idx = j;
860 memset(&q->stats, 0, sizeof(q->stats));
861 }
862 for (j = 0; j < pi->nqsets; j++, t++) {
863 err = t4_sge_alloc_eth_txq(adap, t, dev,
864 netdev_get_tx_queue(dev, j),
865 s->fw_evtq.cntxt_id);
866 if (err)
867 goto freeout;
868 }
869 }
870
b8ff05a9 871 for_each_port(adap, i) {
0fbc81b3 872 /* Note that cmplqid below is 0 if we don't
b8ff05a9
DM		 873 * have RDMA queues, and that's the right value.
874 */
0fbc81b3
HS		 875 if (rxq_info)
876 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
877
b8ff05a9 878 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
0fbc81b3 879 s->fw_evtq.cntxt_id, cmplqid);
b8ff05a9
DM		 880 if (err)
881 goto freeout;
882 }
883
a4569504
AG		 884 if (!is_t4(adap->params.chip)) {
885 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
886 netdev_get_tx_queue(adap->port[0], 0)
887 , s->fw_evtq.cntxt_id);
888 if (err)
889 goto freeout;
890 }
891
9bb59b96 892 t4_write_reg(adap, is_t4(adap->params.chip) ?
837e4a42
HS		 893 MPS_TRC_RSS_CONTROL_A :
894 MPS_T5_TRC_RSS_CONTROL_A,
895 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
896 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
b8ff05a9 897 return 0;
0fbc81b3
HS		 898freeout:
899 t4_free_sge_resources(adap);
900 return err;
b8ff05a9
DM		 901}
902
688848b1
AB		 903static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
904 void *accel_priv, select_queue_fallback_t fallback)
905{
906 int txq;
907
908#ifdef CONFIG_CHELSIO_T4_DCB
909 /* If a Data Center Bridging has been successfully negotiated on this
910 * link then we'll use the skb's priority to map it to a TX Queue.
911 * The skb's priority is determined via the VLAN Tag Priority Code
912 * Point field.
913 */
85eacf3f 914 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
688848b1
AB		 915 u16 vlan_tci;
916 int err;
917
918 err = vlan_get_tag(skb, &vlan_tci);
919 if (unlikely(err)) {
920 if (net_ratelimit())
921 netdev_warn(dev,
922 "TX Packet without VLAN Tag on DCB Link\n");
923 txq = 0;
924 } else {
925 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
84a200b3
VP		 926#ifdef CONFIG_CHELSIO_T4_FCOE
927 if (skb->protocol == htons(ETH_P_FCOE))
928 txq = skb->priority & 0x7;
929#endif /* CONFIG_CHELSIO_T4_FCOE */
688848b1
AB		 930 }
931 return txq;
932 }
933#endif /* CONFIG_CHELSIO_T4_DCB */
934
935 if (select_queue) {
936 txq = (skb_rx_queue_recorded(skb)
937 ? skb_get_rx_queue(skb)
938 : smp_processor_id());
939
940 while (unlikely(txq >= dev->real_num_tx_queues))
941 txq -= dev->real_num_tx_queues;
942
943 return txq;
944 }
945
946 return fallback(dev, skb) % dev->real_num_tx_queues;
947}
948
b8ff05a9
DM		 949static int closest_timer(const struct sge *s, int time)
950{
951 int i, delta, match = 0, min_delta = INT_MAX;
952
953 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
954 delta = time - s->timer_val[i];
955 if (delta < 0)
956 delta = -delta;
957 if (delta < min_delta) {
958 min_delta = delta;
959 match = i;
960 }
961 }
962 return match;
963}
964
965static int closest_thres(const struct sge *s, int thres)
966{
967 int i, delta, match = 0, min_delta = INT_MAX;
968
969 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
970 delta = thres - s->counter_val[i];
971 if (delta < 0)
972 delta = -delta;
973 if (delta < min_delta) {
974 min_delta = delta;
975 match = i;
976 }
977 }
978 return match;
979}
980
b8ff05a9 981/**
812034f1 982 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
b8ff05a9
DM		 983 * @q: the Rx queue
984 * @us: the hold-off time in us, or 0 to disable timer
985 * @cnt: the hold-off packet count, or 0 to disable counter
986 *
987 * Sets an Rx queue's interrupt hold-off time and packet count. At least
988 * one of the two needs to be enabled for the queue to generate interrupts.
989 */
812034f1
HS		 990int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
991 unsigned int us, unsigned int cnt)
b8ff05a9 992{
c887ad0e
HS		 993 struct adapter *adap = q->adap;
994
b8ff05a9
DM		 995 if ((us | cnt) == 0)
996 cnt = 1;
997
998 if (cnt) {
999 int err;
1000 u32 v, new_idx;
1001
1002 new_idx = closest_thres(&adap->sge, cnt);
1003 if (q->desc && q->pktcnt_idx != new_idx) {
1004 /* the queue has already been created, update it */
5167865a
HS		 1005 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1006 FW_PARAMS_PARAM_X_V(
1007 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1008 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
b2612722
HS		 1009 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1010 &v, &new_idx);
b8ff05a9
DM		 1011 if (err)
1012 return err;
1013 }
1014 q->pktcnt_idx = new_idx;
1015 }
1016
1017 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1ecc7b7a 1018 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
b8ff05a9
DM		 1019 return 0;
1020}
1021
c8f44aff 1022static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
87b6cf51 1023{
2ed28baa 1024 const struct port_info *pi = netdev_priv(dev);
c8f44aff 1025 netdev_features_t changed = dev->features ^ features;
19ecae2c 1026 int err;
19ecae2c 1027
f646968f 1028 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2ed28baa 1029 return 0;
19ecae2c 1030
b2612722 1031 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
2ed28baa 1032 -1, -1, -1,
f646968f 1033 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2ed28baa 1034 if (unlikely(err))
f646968f 1035 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
19ecae2c 1036 return err;
87b6cf51
DM		 1037}
1038
91744948 1039static int setup_debugfs(struct adapter *adap)
b8ff05a9 1040{
b8ff05a9
DM		 1041 if (IS_ERR_OR_NULL(adap->debugfs_root))
1042 return -1;
1043
fd88b31a
HS		 1044#ifdef CONFIG_DEBUG_FS
1045 t4_setup_debugfs(adap);
1046#endif
b8ff05a9
DM		 1047 return 0;
1048}
1049
1050/*
1051 * upper-layer driver support
1052 */
1053
1054/*
1055 * Allocate an active-open TID and set it to the supplied value.
1056 */
1057int cxgb4_alloc_atid(struct tid_info *t, void *data)
1058{
1059 int atid = -1;
1060
1061 spin_lock_bh(&t->atid_lock);
1062 if (t->afree) {
1063 union aopen_entry *p = t->afree;
1064
f2b7e78d 1065 atid = (p - t->atid_tab) + t->atid_base;
b8ff05a9
DM		 1066 t->afree = p->next;
1067 p->data = data;
1068 t->atids_in_use++;
1069 }
1070 spin_unlock_bh(&t->atid_lock);
1071 return atid;
1072}
1073EXPORT_SYMBOL(cxgb4_alloc_atid);
1074
1075/*
1076 * Release an active-open TID.
1077 */
1078void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1079{
f2b7e78d 1080 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
b8ff05a9
DM		 1081
1082 spin_lock_bh(&t->atid_lock);
1083 p->next = t->afree;
1084 t->afree = p;
1085 t->atids_in_use--;
1086 spin_unlock_bh(&t->atid_lock);
1087}
1088EXPORT_SYMBOL(cxgb4_free_atid);
1089
1090/*
1091 * Allocate a server TID and set it to the supplied value.
1092 */
1093int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1094{
1095 int stid;
1096
1097 spin_lock_bh(&t->stid_lock);
1098 if (family == PF_INET) {
1099 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1100 if (stid < t->nstids)
1101 __set_bit(stid, t->stid_bmap);
1102 else
1103 stid = -1;
1104 } else {
a99c683e 1105 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
b8ff05a9
DM		 1106 if (stid < 0)
1107 stid = -1;
1108 }
1109 if (stid >= 0) {
1110 t->stid_tab[stid].data = data;
1111 stid += t->stid_base;
15f63b74
KS		 1112 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1113 * This is equivalent to 4 TIDs. With CLIP enabled it
1114 * needs 2 TIDs.
1115 */
1dec4cec 1116 if (family == PF_INET6) {
a99c683e 1117 t->stids_in_use += 2;
1dec4cec
GG		 1118 t->v6_stids_in_use += 2;
1119 } else {
1120 t->stids_in_use++;
1121 }
b8ff05a9
DM		 1122 }
1123 spin_unlock_bh(&t->stid_lock);
1124 return stid;
1125}
1126EXPORT_SYMBOL(cxgb4_alloc_stid);
1127
dca4faeb
VP		 1128/* Allocate a server filter TID and set it to the supplied value.
1129 */
1130int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1131{
1132 int stid;
1133
1134 spin_lock_bh(&t->stid_lock);
1135 if (family == PF_INET) {
1136 stid = find_next_zero_bit(t->stid_bmap,
1137 t->nstids + t->nsftids, t->nstids);
1138 if (stid < (t->nstids + t->nsftids))
1139 __set_bit(stid, t->stid_bmap);
1140 else
1141 stid = -1;
1142 } else {
1143 stid = -1;
1144 }
1145 if (stid >= 0) {
1146 t->stid_tab[stid].data = data;
470c60c4
KS		 1147 stid -= t->nstids;
1148 stid += t->sftid_base;
2248b293 1149 t->sftids_in_use++;
dca4faeb
VP		 1150 }
1151 spin_unlock_bh(&t->stid_lock);
1152 return stid;
1153}
1154EXPORT_SYMBOL(cxgb4_alloc_sftid);
1155
1156/* Release a server TID.
b8ff05a9
DM		 1157 */
1158void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1159{
470c60c4
KS		 1160 /* Is it a server filter TID? */
1161 if (t->nsftids && (stid >= t->sftid_base)) {
1162 stid -= t->sftid_base;
1163 stid += t->nstids;
1164 } else {
1165 stid -= t->stid_base;
1166 }
1167
b8ff05a9
DM		 1168 spin_lock_bh(&t->stid_lock);
1169 if (family == PF_INET)
1170 __clear_bit(stid, t->stid_bmap);
1171 else
a99c683e 1172 bitmap_release_region(t->stid_bmap, stid, 1);
b8ff05a9 1173 t->stid_tab[stid].data = NULL;
2248b293 1174 if (stid < t->nstids) {
1dec4cec 1175 if (family == PF_INET6) {
a99c683e 1176 t->stids_in_use -= 2;
1dec4cec
GG		 1177 t->v6_stids_in_use -= 2;
1178 } else {
1179 t->stids_in_use--;
1180 }
2248b293
HS		 1181 } else {
1182 t->sftids_in_use--;
1183 }
1dec4cec 1184
b8ff05a9
DM		 1185 spin_unlock_bh(&t->stid_lock);
1186}
1187EXPORT_SYMBOL(cxgb4_free_stid);
1188
1189/*
1190 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1191 */
1192static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1193 unsigned int tid)
1194{
1195 struct cpl_tid_release *req;
1196
1197 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
4df864c1 1198 req = __skb_put(skb, sizeof(*req));
b8ff05a9
DM		 1199 INIT_TP_WR(req, tid);
1200 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1201}
1202
1203/*
1204 * Queue a TID release request and if necessary schedule a work queue to
1205 * process it.
1206 */
31b9c19b 1207static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1208 unsigned int tid)
b8ff05a9
DM		 1209{
1210 void **p = &t->tid_tab[tid];
1211 struct adapter *adap = container_of(t, struct adapter, tids);
1212
1213 spin_lock_bh(&adap->tid_release_lock);
1214 *p = adap->tid_release_head;
1215 /* Low 2 bits encode the Tx channel number */
1216 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1217 if (!adap->tid_release_task_busy) {
1218 adap->tid_release_task_busy = true;
29aaee65 1219 queue_work(adap->workq, &adap->tid_release_task);
b8ff05a9
DM		 1220 }
1221 spin_unlock_bh(&adap->tid_release_lock);
1222}
b8ff05a9
DM		 1223
1224/*
1225 * Process the list of pending TID release requests.
1226 */
1227static void process_tid_release_list(struct work_struct *work)
1228{
1229 struct sk_buff *skb;
1230 struct adapter *adap;
1231
1232 adap = container_of(work, struct adapter, tid_release_task);
1233
1234 spin_lock_bh(&adap->tid_release_lock);
1235 while (adap->tid_release_head) {
1236 void **p = adap->tid_release_head;
1237 unsigned int chan = (uintptr_t)p & 3;
1238 p = (void *)p - chan;
1239
1240 adap->tid_release_head = *p;
1241 *p = NULL;
1242 spin_unlock_bh(&adap->tid_release_lock);
1243
1244 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1245 GFP_KERNEL)))
1246 schedule_timeout_uninterruptible(1);
1247
1248 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1249 t4_ofld_send(adap, skb);
1250 spin_lock_bh(&adap->tid_release_lock);
1251 }
1252 adap->tid_release_task_busy = false;
1253 spin_unlock_bh(&adap->tid_release_lock);
1254}
1255
1256/*
1257 * Release a TID and inform HW. If we are unable to allocate the release
1258 * message we defer to a work queue.
1259 */
1dec4cec
GG		 1260void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1261 unsigned short family)
b8ff05a9 1262{
b8ff05a9
DM		 1263 struct sk_buff *skb;
1264 struct adapter *adap = container_of(t, struct adapter, tids);
1265
9a1bb9f6
HS		 1266 WARN_ON(tid >= t->ntids);
1267
1268 if (t->tid_tab[tid]) {
1269 t->tid_tab[tid] = NULL;
1dec4cec
GG		 1270 atomic_dec(&t->conns_in_use);
1271 if (t->hash_base && (tid >= t->hash_base)) {
1272 if (family == AF_INET6)
1273 atomic_sub(2, &t->hash_tids_in_use);
1274 else
1275 atomic_dec(&t->hash_tids_in_use);
1276 } else {
1277 if (family == AF_INET6)
1278 atomic_sub(2, &t->tids_in_use);
1279 else
1280 atomic_dec(&t->tids_in_use);
1281 }
9a1bb9f6
HS		 1282 }
1283
b8ff05a9
DM		 1284 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1285 if (likely(skb)) {
b8ff05a9
DM		 1286 mk_tid_release(skb, chan, tid);
1287 t4_ofld_send(adap, skb);
1288 } else
1289 cxgb4_queue_tid_release(t, chan, tid);
b8ff05a9
DM		 1290}
1291EXPORT_SYMBOL(cxgb4_remove_tid);
1292
1293/*
1294 * Allocate and initialize the TID tables. Returns 0 on success.
1295 */
1296static int tid_init(struct tid_info *t)
1297{
b6f8eaec 1298 struct adapter *adap = container_of(t, struct adapter, tids);
578b46b9
RL		 1299 unsigned int max_ftids = t->nftids + t->nsftids;
1300 unsigned int natids = t->natids;
1301 unsigned int stid_bmap_size;
1302 unsigned int ftid_bmap_size;
1303 size_t size;
b8ff05a9 1304
dca4faeb 1305 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
578b46b9 1306 ftid_bmap_size = BITS_TO_LONGS(t->nftids);
f2b7e78d
VP		 1307 size = t->ntids * sizeof(*t->tid_tab) +
1308 natids * sizeof(*t->atid_tab) +
b8ff05a9 1309 t->nstids * sizeof(*t->stid_tab) +
dca4faeb 1310 t->nsftids * sizeof(*t->stid_tab) +
f2b7e78d 1311 stid_bmap_size * sizeof(long) +
578b46b9
RL		 1312 max_ftids * sizeof(*t->ftid_tab) +
1313 ftid_bmap_size * sizeof(long);
f2b7e78d 1314
752ade68 1315 t->tid_tab = kvzalloc(size, GFP_KERNEL);
b8ff05a9
DM		 1316 if (!t->tid_tab)
1317 return -ENOMEM;
1318
1319 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1320 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
dca4faeb 1321 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
f2b7e78d 1322 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
578b46b9 1323 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
b8ff05a9
DM		 1324 spin_lock_init(&t->stid_lock);
1325 spin_lock_init(&t->atid_lock);
578b46b9 1326 spin_lock_init(&t->ftid_lock);
b8ff05a9
DM		 1327
1328 t->stids_in_use = 0;
1dec4cec 1329 t->v6_stids_in_use = 0;
2248b293 1330 t->sftids_in_use = 0;
b8ff05a9
DM		 1331 t->afree = NULL;
1332 t->atids_in_use = 0;
1333 atomic_set(&t->tids_in_use, 0);
1dec4cec 1334 atomic_set(&t->conns_in_use, 0);
9a1bb9f6 1335 atomic_set(&t->hash_tids_in_use, 0);
b8ff05a9
DM		 1336
1337 /* Setup the free list for atid_tab and clear the stid bitmap. */
1338 if (natids) {
1339 while (--natids)
1340 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1341 t->afree = t->atid_tab;
1342 }
b6f8eaec 1343
578b46b9
RL		 1344 if (is_offload(adap)) {
1345 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1346 /* Reserve stid 0 for T4/T5 adapters */
1347 if (!t->stid_base &&
1348 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1349 __set_bit(0, t->stid_bmap);
1350 }
1351
1352 bitmap_zero(t->ftid_bmap, t->nftids);
b8ff05a9
DM		 1353 return 0;
1354}
1355
1356/**
1357 * cxgb4_create_server - create an IP server
1358 * @dev: the device
1359 * @stid: the server TID
1360 * @sip: local IP address to bind server to
1361 * @sport: the server's TCP port
1362 * @queue: queue to direct messages from this server to
1363 *
1364 * Create an IP server for the given port and address.
1365 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1366 */
1367int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
793dad94
VP		 1368 __be32 sip, __be16 sport, __be16 vlan,
1369 unsigned int queue)
b8ff05a9
DM		 1370{
1371 unsigned int chan;
1372 struct sk_buff *skb;
1373 struct adapter *adap;
1374 struct cpl_pass_open_req *req;
80f40c1f 1375 int ret;
b8ff05a9
DM		 1376
1377 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1378 if (!skb)
1379 return -ENOMEM;
1380
1381 adap = netdev2adap(dev);
4df864c1 1382 req = __skb_put(skb, sizeof(*req));
b8ff05a9
DM		 1383 INIT_TP_WR(req, 0);
1384 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1385 req->local_port = sport;
1386 req->peer_port = htons(0);
1387 req->local_ip = sip;
1388 req->peer_ip = htonl(0);
e46dab4d 1389 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1390 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1391 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1392 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1393 ret = t4_mgmt_tx(adap, skb);
1394 return net_xmit_eval(ret);
b8ff05a9
DM		 1395}
1396EXPORT_SYMBOL(cxgb4_create_server);
1397
80f40c1f
VP		 1398/* cxgb4_create_server6 - create an IPv6 server
1399 * @dev: the device
1400 * @stid: the server TID
1401 * @sip: local IPv6 address to bind server to
1402 * @sport: the server's TCP port
1403 * @queue: queue to direct messages from this server to
1404 *
1405 * Create an IPv6 server for the given port and address.
1406 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1407 */
1408int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1409 const struct in6_addr *sip, __be16 sport,
1410 unsigned int queue)
1411{
1412 unsigned int chan;
1413 struct sk_buff *skb;
1414 struct adapter *adap;
1415 struct cpl_pass_open_req6 *req;
1416 int ret;
1417
1418 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1419 if (!skb)
1420 return -ENOMEM;
1421
1422 adap = netdev2adap(dev);
4df864c1 1423 req = __skb_put(skb, sizeof(*req));
80f40c1f
VP		 1424 INIT_TP_WR(req, 0);
1425 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1426 req->local_port = sport;
1427 req->peer_port = htons(0);
1428 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1429 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1430 req->peer_ip_hi = cpu_to_be64(0);
1431 req->peer_ip_lo = cpu_to_be64(0);
1432 chan = rxq_to_chan(&adap->sge, queue);
d7990b0c 1433 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
6c53e938
HS		 1434 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1435 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
80f40c1f
VP		 1436 ret = t4_mgmt_tx(adap, skb);
1437 return net_xmit_eval(ret);
1438}
1439EXPORT_SYMBOL(cxgb4_create_server6);
1440
1441int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1442 unsigned int queue, bool ipv6)
1443{
1444 struct sk_buff *skb;
1445 struct adapter *adap;
1446 struct cpl_close_listsvr_req *req;
1447 int ret;
1448
1449 adap = netdev2adap(dev);
1450
1451 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1452 if (!skb)
1453 return -ENOMEM;
1454
4df864c1 1455 req = __skb_put(skb, sizeof(*req));
80f40c1f
VP		 1456 INIT_TP_WR(req, 0);
1457 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
bdc590b9
HS		 1458 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1459 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
80f40c1f
VP		 1460 ret = t4_mgmt_tx(adap, skb);
1461 return net_xmit_eval(ret);
1462}
1463EXPORT_SYMBOL(cxgb4_remove_server);
1464
b8ff05a9
DM		 1465/**
1466 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1467 * @mtus: the HW MTU table
1468 * @mtu: the target MTU
1469 * @idx: index of selected entry in the MTU table
1470 *
1471 * Returns the index and the value in the HW MTU table that is closest to
1472 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1473 * table, in which case that smallest available value is selected.
1474 */
1475unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1476 unsigned int *idx)
1477{
1478 unsigned int i = 0;
1479
1480 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1481 ++i;
1482 if (idx)
1483 *idx = i;
1484 return mtus[i];
1485}
1486EXPORT_SYMBOL(cxgb4_best_mtu);
1487
92e7ae71
HS		 1488/**
1489 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1490 * @mtus: the HW MTU table
1491 * @header_size: Header Size
1492 * @data_size_max: maximum Data Segment Size
1493 * @data_size_align: desired Data Segment Size Alignment (2^N)
1494 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1495 *
1496 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1497 * MTU Table based solely on a Maximum MTU parameter, we break that
1498 * parameter up into a Header Size and Maximum Data Segment Size, and
1499 * provide a desired Data Segment Size Alignment. If we find an MTU in
1500 * the Hardware MTU Table which will result in a Data Segment Size with
1501 * the requested alignment _and_ that MTU isn't "too far" from the
1502 * closest MTU, then we'll return that rather than the closest MTU.
1503 */
1504unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1505 unsigned short header_size,
1506 unsigned short data_size_max,
1507 unsigned short data_size_align,
1508 unsigned int *mtu_idxp)
1509{
1510 unsigned short max_mtu = header_size + data_size_max;
1511 unsigned short data_size_align_mask = data_size_align - 1;
1512 int mtu_idx, aligned_mtu_idx;
1513
1514 /* Scan the MTU Table till we find an MTU which is larger than our
1515 * Maximum MTU or we reach the end of the table. Along the way,
1516 * record the last MTU found, if any, which will result in a Data
1517 * Segment Length matching the requested alignment.
1518 */
1519 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1520 unsigned short data_size = mtus[mtu_idx] - header_size;
1521
1522 /* If this MTU minus the Header Size would result in a
1523 * Data Segment Size of the desired alignment, remember it.
1524 */
1525 if ((data_size & data_size_align_mask) == 0)
1526 aligned_mtu_idx = mtu_idx;
1527
1528 /* If we're not at the end of the Hardware MTU Table and the
1529 * next element is larger than our Maximum MTU, drop out of
1530 * the loop.
1531 */
1532 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1533 break;
1534 }
1535
1536 /* If we fell out of the loop because we ran to the end of the table,
1537 * then we just have to use the last [largest] entry.
1538 */
1539 if (mtu_idx == NMTUS)
1540 mtu_idx--;
1541
1542 /* If we found an MTU which resulted in the requested Data Segment
1543 * Length alignment and that's "not far" from the largest MTU which is
1544 * less than or equal to the maximum MTU, then use that.
1545 */
1546 if (aligned_mtu_idx >= 0 &&
1547 mtu_idx - aligned_mtu_idx <= 1)
1548 mtu_idx = aligned_mtu_idx;
1549
1550 /* If the caller has passed in an MTU Index pointer, pass the
1551 * MTU Index back. Return the MTU value.
1552 */
1553 if (mtu_idxp)
1554 *mtu_idxp = mtu_idx;
1555 return mtus[mtu_idx];
1556}
1557EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1558
27999805
H		 1559/**
1560 * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1561 * @chip: chip type
1562 * @viid: VI id of the given port
1563 *
1564 * Return the SMT index for this VI.
1565 */
1566unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1567{
1568 /* In T4/T5, SMT contains 256 SMAC entries organized in
1569 * 128 rows of 2 entries each.
1570 * In T6, SMT contains 256 SMAC entries in 256 rows.
1571 * TODO: The below code needs to be updated when we add support
1572 * for 256 VFs.
1573 */
1574 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1575 return ((viid & 0x7f) << 1);
1576 else
1577 return (viid & 0x7f);
1578}
1579EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1580
b8ff05a9
DM		 1581/**
1582 * cxgb4_port_chan - get the HW channel of a port
1583 * @dev: the net device for the port
1584 *
1585 * Return the HW Tx channel of the given port.
1586 */
1587unsigned int cxgb4_port_chan(const struct net_device *dev)
1588{
1589 return netdev2pinfo(dev)->tx_chan;
1590}
1591EXPORT_SYMBOL(cxgb4_port_chan);
1592
881806bc
VP		 1593unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1594{
1595 struct adapter *adap = netdev2adap(dev);
2cc301d2 1596 u32 v1, v2, lp_count, hp_count;
881806bc 1597
f061de42
HS		 1598 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1599 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1600 if (is_t4(adap->params.chip)) {
f061de42
HS		 1601 lp_count = LP_COUNT_G(v1);
1602 hp_count = HP_COUNT_G(v1);
2cc301d2 1603 } else {
f061de42
HS		 1604 lp_count = LP_COUNT_T5_G(v1);
1605 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1606 }
1607 return lpfifo ? lp_count : hp_count;
881806bc
VP		 1608}
1609EXPORT_SYMBOL(cxgb4_dbfifo_count);
1610
b8ff05a9
DM		 1611/**
1612 * cxgb4_port_viid - get the VI id of a port
1613 * @dev: the net device for the port
1614 *
1615 * Return the VI id of the given port.
1616 */
1617unsigned int cxgb4_port_viid(const struct net_device *dev)
1618{
1619 return netdev2pinfo(dev)->viid;
1620}
1621EXPORT_SYMBOL(cxgb4_port_viid);
1622
1623/**
1624 * cxgb4_port_idx - get the index of a port
1625 * @dev: the net device for the port
1626 *
1627 * Return the index of the given port.
1628 */
1629unsigned int cxgb4_port_idx(const struct net_device *dev)
1630{
1631 return netdev2pinfo(dev)->port_id;
1632}
1633EXPORT_SYMBOL(cxgb4_port_idx);
1634
b8ff05a9
DM		 1635void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1636 struct tp_tcp_stats *v6)
1637{
1638 struct adapter *adap = pci_get_drvdata(pdev);
1639
1640 spin_lock(&adap->stats_lock);
1641 t4_tp_get_tcp_stats(adap, v4, v6);
1642 spin_unlock(&adap->stats_lock);
1643}
1644EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1645
1646void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1647 const unsigned int *pgsz_order)
1648{
1649 struct adapter *adap = netdev2adap(dev);
1650
0d804338
HS		 1651 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1652 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1653 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1654 HPZ3_V(pgsz_order[3]));
b8ff05a9
DM		 1655}
1656EXPORT_SYMBOL(cxgb4_iscsi_init);
1657
3069ee9b
VP		 1658int cxgb4_flush_eq_cache(struct net_device *dev)
1659{
1660 struct adapter *adap = netdev2adap(dev);
3069ee9b 1661
5d700ecb 1662 return t4_sge_ctxt_flush(adap, adap->mbox);
3069ee9b
VP		 1663}
1664EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1665
1666static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1667{
f061de42 1668 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
3069ee9b
VP		 1669 __be64 indices;
1670 int ret;
1671
fc5ab020
HS		 1672 spin_lock(&adap->win0_lock);
1673 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1674 sizeof(indices), (__be32 *)&indices,
1675 T4_MEMORY_READ);
1676 spin_unlock(&adap->win0_lock);
3069ee9b 1677 if (!ret) {
404d9e3f
VP		 1678 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1679 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3069ee9b
VP		 1680 }
1681 return ret;
1682}
1683
1684int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1685 u16 size)
1686{
1687 struct adapter *adap = netdev2adap(dev);
1688 u16 hw_pidx, hw_cidx;
1689 int ret;
1690
1691 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1692 if (ret)
1693 goto out;
1694
1695 if (pidx != hw_pidx) {
1696 u16 delta;
f612b815 1697 u32 val;
3069ee9b
VP		 1698
1699 if (pidx >= hw_pidx)
1700 delta = pidx - hw_pidx;
1701 else
1702 delta = size - hw_pidx + pidx;
f612b815
HS		 1703
1704 if (is_t4(adap->params.chip))
1705 val = PIDX_V(delta);
1706 else
1707 val = PIDX_T5_V(delta);
3069ee9b 1708 wmb();
f612b815
HS		 1709 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1710 QID_V(qid) | val);
3069ee9b
VP		 1711 }
1712out:
1713 return ret;
1714}
1715EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1716
031cf476
HS		 1717int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1718{
1719 struct adapter *adap;
1720 u32 offset, memtype, memaddr;
6559a7e8 1721 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
031cf476
HS		 1722 u32 edc0_end, edc1_end, mc0_end, mc1_end;
1723 int ret;
1724
1725 adap = netdev2adap(dev);
1726
1727 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1728
1729 /* Figure out where the offset lands in the Memory Type/Address scheme.
1730 * This code assumes that the memory is laid out starting at offset 0
1731 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1732 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
1733 * MC0, and some have both MC0 and MC1.
1734 */
6559a7e8
HS		 1735 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1736 edc0_size = EDRAM0_SIZE_G(size) << 20;
1737 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1738 edc1_size = EDRAM1_SIZE_G(size) << 20;
1739 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1740 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
031cf476
HS		 1741
1742 edc0_end = edc0_size;
1743 edc1_end = edc0_end + edc1_size;
1744 mc0_end = edc1_end + mc0_size;
1745
1746 if (offset < edc0_end) {
1747 memtype = MEM_EDC0;
1748 memaddr = offset;
1749 } else if (offset < edc1_end) {
1750 memtype = MEM_EDC1;
1751 memaddr = offset - edc0_end;
1752 } else {
1753 if (offset < mc0_end) {
1754 memtype = MEM_MC0;
1755 memaddr = offset - edc1_end;
3ccc6cf7 1756 } else if (is_t5(adap->params.chip)) {
6559a7e8
HS		 1757 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1758 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
031cf476
HS		 1759 mc1_end = mc0_end + mc1_size;
1760 if (offset < mc1_end) {
1761 memtype = MEM_MC1;
1762 memaddr = offset - mc0_end;
1763 } else {
1764 /* offset beyond the end of any memory */
1765 goto err;
1766 }
3ccc6cf7
HS		 1767 } else {
1768 /* T4/T6 only has a single memory channel */
1769 goto err;
031cf476
HS		 1770 }
1771 }
1772
1773 spin_lock(&adap->win0_lock);
1774 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1775 spin_unlock(&adap->win0_lock);
1776 return ret;
1777
1778err:
1779 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1780 stag, offset);
1781 return -EINVAL;
1782}
1783EXPORT_SYMBOL(cxgb4_read_tpte);
1784
7730b4c7
HS		 1785u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1786{
1787 u32 hi, lo;
1788 struct adapter *adap;
1789
1790 adap = netdev2adap(dev);
f612b815
HS		 1791 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1792 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
7730b4c7
HS		 1793
1794 return ((u64)hi << 32) | (u64)lo;
1795}
1796EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1797
df64e4d3
HS		 1798int cxgb4_bar2_sge_qregs(struct net_device *dev,
1799 unsigned int qid,
1800 enum cxgb4_bar2_qtype qtype,
66cf188e 1801 int user,
df64e4d3
HS		 1802 u64 *pbar2_qoffset,
1803 unsigned int *pbar2_qid)
1804{
b2612722 1805 return t4_bar2_sge_qregs(netdev2adap(dev),
df64e4d3
HS		 1806 qid,
1807 (qtype == CXGB4_BAR2_QTYPE_EGRESS
1808 ? T4_BAR2_QTYPE_EGRESS
1809 : T4_BAR2_QTYPE_INGRESS),
66cf188e 1810 user,
df64e4d3
HS		 1811 pbar2_qoffset,
1812 pbar2_qid);
1813}
1814EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1815
b8ff05a9
DM		 1816static struct pci_driver cxgb4_driver;
1817
1818static void check_neigh_update(struct neighbour *neigh)
1819{
1820 const struct device *parent;
1821 const struct net_device *netdev = neigh->dev;
1822
d0d7b10b 1823 if (is_vlan_dev(netdev))
b8ff05a9
DM		 1824 netdev = vlan_dev_real_dev(netdev);
1825 parent = netdev->dev.parent;
1826 if (parent && parent->driver == &cxgb4_driver.driver)
1827 t4_l2t_update(dev_get_drvdata(parent), neigh);
1828}
1829
1830static int netevent_cb(struct notifier_block *nb, unsigned long event,
1831 void *data)
1832{
1833 switch (event) {
1834 case NETEVENT_NEIGH_UPDATE:
1835 check_neigh_update(data);
1836 break;
b8ff05a9
DM		 1837 case NETEVENT_REDIRECT:
1838 default:
1839 break;
1840 }
1841 return 0;
1842}
1843
1844static bool netevent_registered;
1845static struct notifier_block cxgb4_netevent_nb = {
1846 .notifier_call = netevent_cb
1847};
1848
3069ee9b
VP		 1849static void drain_db_fifo(struct adapter *adap, int usecs)
1850{
2cc301d2 1851 u32 v1, v2, lp_count, hp_count;
3069ee9b
VP		 1852
1853 do {
f061de42
HS		 1854 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1855 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
d14807dd 1856 if (is_t4(adap->params.chip)) {
f061de42
HS		 1857 lp_count = LP_COUNT_G(v1);
1858 hp_count = HP_COUNT_G(v1);
2cc301d2 1859 } else {
f061de42
HS		 1860 lp_count = LP_COUNT_T5_G(v1);
1861 hp_count = HP_COUNT_T5_G(v2);
2cc301d2
SR		 1862 }
1863
1864 if (lp_count == 0 && hp_count == 0)
1865 break;
3069ee9b
VP		 1866 set_current_state(TASK_UNINTERRUPTIBLE);
1867 schedule_timeout(usecs_to_jiffies(usecs));
3069ee9b
VP		 1868 } while (1);
1869}
1870
1871static void disable_txq_db(struct sge_txq *q)
1872{
05eb2389
SW		 1873 unsigned long flags;
1874
1875 spin_lock_irqsave(&q->db_lock, flags);
3069ee9b 1876 q->db_disabled = 1;
05eb2389 1877 spin_unlock_irqrestore(&q->db_lock, flags);
3069ee9b
VP		 1878}
1879
05eb2389 1880static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3069ee9b
VP		 1881{
1882 spin_lock_irq(&q->db_lock);
05eb2389
SW		 1883 if (q->db_pidx_inc) {
1884 /* Make sure that all writes to the TX descriptors
1885 * are committed before we tell HW about them.
1886 */
1887 wmb();
f612b815
HS		 1888 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1889 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
05eb2389
SW		 1890 q->db_pidx_inc = 0;
1891 }
3069ee9b
VP		 1892 q->db_disabled = 0;
1893 spin_unlock_irq(&q->db_lock);
1894}
1895
1896static void disable_dbs(struct adapter *adap)
1897{
1898 int i;
1899
1900 for_each_ethrxq(&adap->sge, i)
1901 disable_txq_db(&adap->sge.ethtxq[i].q);
ab677ff4
HS		 1902 if (is_offload(adap)) {
1903 struct sge_uld_txq_info *txq_info =
1904 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1905
1906 if (txq_info) {
1907 for_each_ofldtxq(&adap->sge, i) {
1908 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1909
1910 disable_txq_db(&txq->q);
1911 }
1912 }
1913 }
3069ee9b
VP		 1914 for_each_port(adap, i)
1915 disable_txq_db(&adap->sge.ctrlq[i].q);
1916}
1917
1918static void enable_dbs(struct adapter *adap)
1919{
1920 int i;
1921
1922 for_each_ethrxq(&adap->sge, i)
05eb2389 1923 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
ab677ff4
HS		 1924 if (is_offload(adap)) {
1925 struct sge_uld_txq_info *txq_info =
1926 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1927
1928 if (txq_info) {
1929 for_each_ofldtxq(&adap->sge, i) {
1930 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1931
1932 enable_txq_db(adap, &txq->q);
1933 }
1934 }
1935 }
3069ee9b 1936 for_each_port(adap, i)
05eb2389
SW		 1937 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
1938}
1939
1940static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
1941{
0fbc81b3
HS		 1942 enum cxgb4_uld type = CXGB4_ULD_RDMA;
1943
1944 if (adap->uld && adap->uld[type].handle)
1945 adap->uld[type].control(adap->uld[type].handle, cmd);
05eb2389
SW		 1946}
1947
1948static void process_db_full(struct work_struct *work)
1949{
1950 struct adapter *adap;
1951
1952 adap = container_of(work, struct adapter, db_full_task);
1953
1954 drain_db_fifo(adap, dbfifo_drain_delay);
1955 enable_dbs(adap);
1956 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7
HS		 1957 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1958 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1959 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
1960 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
1961 else
1962 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
1963 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
3069ee9b
VP		 1964}
1965
1966static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
1967{
1968 u16 hw_pidx, hw_cidx;
1969 int ret;
1970
05eb2389 1971 spin_lock_irq(&q->db_lock);
3069ee9b
VP		 1972 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
1973 if (ret)
1974 goto out;
1975 if (q->db_pidx != hw_pidx) {
1976 u16 delta;
f612b815 1977 u32 val;
3069ee9b
VP		 1978
1979 if (q->db_pidx >= hw_pidx)
1980 delta = q->db_pidx - hw_pidx;
1981 else
1982 delta = q->size - hw_pidx + q->db_pidx;
f612b815
HS		 1983
1984 if (is_t4(adap->params.chip))
1985 val = PIDX_V(delta);
1986 else
1987 val = PIDX_T5_V(delta);
3069ee9b 1988 wmb();
f612b815
HS		 1989 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1990 QID_V(q->cntxt_id) | val);
3069ee9b
VP		 1991 }
1992out:
1993 q->db_disabled = 0;
05eb2389
SW		 1994 q->db_pidx_inc = 0;
1995 spin_unlock_irq(&q->db_lock);
3069ee9b
VP		 1996 if (ret)
1997 CH_WARN(adap, "DB drop recovery failed.\n");
1998}
0fbc81b3 1999
3069ee9b
VP		 2000static void recover_all_queues(struct adapter *adap)
2001{
2002 int i;
2003
2004 for_each_ethrxq(&adap->sge, i)
2005 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
ab677ff4
HS		 2006 if (is_offload(adap)) {
2007 struct sge_uld_txq_info *txq_info =
2008 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2009 if (txq_info) {
2010 for_each_ofldtxq(&adap->sge, i) {
2011 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2012
2013 sync_txq_pidx(adap, &txq->q);
2014 }
2015 }
2016 }
3069ee9b
VP		 2017 for_each_port(adap, i)
2018 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2019}
2020
881806bc
VP		 2021static void process_db_drop(struct work_struct *work)
2022{
2023 struct adapter *adap;
881806bc 2024
3069ee9b 2025 adap = container_of(work, struct adapter, db_drop_task);
881806bc 2026
d14807dd 2027 if (is_t4(adap->params.chip)) {
05eb2389 2028 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2029 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
05eb2389 2030 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2031 recover_all_queues(adap);
05eb2389 2032 drain_db_fifo(adap, dbfifo_drain_delay);
2cc301d2 2033 enable_dbs(adap);
05eb2389 2034 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3ccc6cf7 2035 } else if (is_t5(adap->params.chip)) {
2cc301d2
SR		 2036 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2037 u16 qid = (dropped_db >> 15) & 0x1ffff;
2038 u16 pidx_inc = dropped_db & 0x1fff;
df64e4d3
HS		 2039 u64 bar2_qoffset;
2040 unsigned int bar2_qid;
2041 int ret;
2cc301d2 2042
b2612722 2043 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
e0456717 2044 0, &bar2_qoffset, &bar2_qid);
df64e4d3
HS		 2045 if (ret)
2046 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2047 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2048 else
f612b815 2049 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
df64e4d3 2050 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2cc301d2
SR		 2051
2052 /* Re-enable BAR2 WC */
2053 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2054 }
2055
3ccc6cf7
HS		 2056 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2057 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
881806bc
VP		 2058}
2059
2060void t4_db_full(struct adapter *adap)
2061{
d14807dd 2062 if (is_t4(adap->params.chip)) {
05eb2389
SW		 2063 disable_dbs(adap);
2064 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
f612b815
HS		 2065 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2066 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
29aaee65 2067 queue_work(adap->workq, &adap->db_full_task);
2cc301d2 2068 }
881806bc
VP		 2069}
2070
2071void t4_db_dropped(struct adapter *adap)
2072{
05eb2389
SW		 2073 if (is_t4(adap->params.chip)) {
2074 disable_dbs(adap);
2075 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2076 }
29aaee65 2077 queue_work(adap->workq, &adap->db_drop_task);
881806bc
VP		 2078}
2079
0fbc81b3
HS		 2080void t4_register_netevent_notifier(void)
2081{
b8ff05a9
DM		 2082 if (!netevent_registered) {
2083 register_netevent_notifier(&cxgb4_netevent_nb);
2084 netevent_registered = true;
2085 }
b8ff05a9
DM		 2086}
2087
2088static void detach_ulds(struct adapter *adap)
2089{
2090 unsigned int i;
2091
2092 mutex_lock(&uld_mutex);
2093 list_del(&adap->list_node);
6a146f3a 2094
b8ff05a9 2095 for (i = 0; i < CXGB4_ULD_MAX; i++)
6a146f3a 2096 if (adap->uld && adap->uld[i].handle)
94cdb8bb
HS		 2097 adap->uld[i].state_change(adap->uld[i].handle,
2098 CXGB4_STATE_DETACH);
6a146f3a 2099
b8ff05a9
DM		 2100 if (netevent_registered && list_empty(&adapter_list)) {
2101 unregister_netevent_notifier(&cxgb4_netevent_nb);
2102 netevent_registered = false;
2103 }
2104 mutex_unlock(&uld_mutex);
2105}
2106
2107static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2108{
2109 unsigned int i;
2110
2111 mutex_lock(&uld_mutex);
2112 for (i = 0; i < CXGB4_ULD_MAX; i++)
94cdb8bb
HS		 2113 if (adap->uld && adap->uld[i].handle)
2114 adap->uld[i].state_change(adap->uld[i].handle,
2115 new_state);
b8ff05a9
DM		 2116 mutex_unlock(&uld_mutex);
2117}
2118
1bb60376 2119#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 2120static int cxgb4_inet6addr_handler(struct notifier_block *this,
2121 unsigned long event, void *data)
01bcca68 2122{
b5a02f50
AB		 2123 struct inet6_ifaddr *ifa = data;
2124 struct net_device *event_dev = ifa->idev->dev;
2125 const struct device *parent = NULL;
2126#if IS_ENABLED(CONFIG_BONDING)
01bcca68 2127 struct adapter *adap;
b5a02f50 2128#endif
d0d7b10b 2129 if (is_vlan_dev(event_dev))
b5a02f50
AB		 2130 event_dev = vlan_dev_real_dev(event_dev);
2131#if IS_ENABLED(CONFIG_BONDING)
2132 if (event_dev->flags & IFF_MASTER) {
2133 list_for_each_entry(adap, &adapter_list, list_node) {
2134 switch (event) {
2135 case NETDEV_UP:
2136 cxgb4_clip_get(adap->port[0],
2137 (const u32 *)ifa, 1);
2138 break;
2139 case NETDEV_DOWN:
2140 cxgb4_clip_release(adap->port[0],
2141 (const u32 *)ifa, 1);
2142 break;
2143 default:
2144 break;
2145 }
2146 }
2147 return NOTIFY_OK;
2148 }
2149#endif
01bcca68 2150
b5a02f50
AB		 2151 if (event_dev)
2152 parent = event_dev->dev.parent;
01bcca68 2153
b5a02f50 2154 if (parent && parent->driver == &cxgb4_driver.driver) {
01bcca68
VP		 2155 switch (event) {
2156 case NETDEV_UP:
b5a02f50 2157 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2158 break;
2159 case NETDEV_DOWN:
b5a02f50 2160 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
01bcca68
VP		 2161 break;
2162 default:
2163 break;
2164 }
2165 }
b5a02f50 2166 return NOTIFY_OK;
01bcca68
VP		 2167}
2168
b5a02f50 2169static bool inet6addr_registered;
01bcca68
VP		 2170static struct notifier_block cxgb4_inet6addr_notifier = {
2171 .notifier_call = cxgb4_inet6addr_handler
2172};
2173
01bcca68
VP		 2174static void update_clip(const struct adapter *adap)
2175{
2176 int i;
2177 struct net_device *dev;
2178 int ret;
2179
2180 rcu_read_lock();
2181
2182 for (i = 0; i < MAX_NPORTS; i++) {
2183 dev = adap->port[i];
2184 ret = 0;
2185
2186 if (dev)
b5a02f50 2187 ret = cxgb4_update_root_dev_clip(dev);
01bcca68
VP		 2188
2189 if (ret < 0)
2190 break;
2191 }
2192 rcu_read_unlock();
2193}
1bb60376 2194#endif /* IS_ENABLED(CONFIG_IPV6) */
01bcca68 2195
b8ff05a9
DM		 2196/**
2197 * cxgb_up - enable the adapter
2198 * @adap: adapter being enabled
2199 *
2200 * Called when the first port is enabled, this function performs the
2201 * actions necessary to make an adapter operational, such as completing
2202 * the initialization of HW modules, and enabling interrupts.
2203 *
2204 * Must be called with the rtnl lock held.
2205 */
2206static int cxgb_up(struct adapter *adap)
2207{
aaefae9b 2208 int err;
b8ff05a9 2209
91060381 2210 mutex_lock(&uld_mutex);
aaefae9b
DM		 2211 err = setup_sge_queues(adap);
2212 if (err)
91060381 2213 goto rel_lock;
aaefae9b
DM		 2214 err = setup_rss(adap);
2215 if (err)
2216 goto freeq;
b8ff05a9
DM		 2217
2218 if (adap->flags & USING_MSIX) {
aaefae9b 2219 name_msix_vecs(adap);
b8ff05a9
DM		 2220 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2221 adap->msix_info[0].desc, adap);
2222 if (err)
2223 goto irq_err;
b8ff05a9
DM		 2224 err = request_msix_queue_irqs(adap);
2225 if (err) {
2226 free_irq(adap->msix_info[0].vec, adap);
2227 goto irq_err;
2228 }
2229 } else {
2230 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2231 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
b1a3c2b6 2232 adap->port[0]->name, adap);
b8ff05a9
DM		 2233 if (err)
2234 goto irq_err;
2235 }
e7519f99 2236
b8ff05a9
DM		 2237 enable_rx(adap);
2238 t4_sge_start(adap);
2239 t4_intr_enable(adap);
aaefae9b 2240 adap->flags |= FULL_INIT_DONE;
e7519f99
GG		 2241 mutex_unlock(&uld_mutex);
2242
b8ff05a9 2243 notify_ulds(adap, CXGB4_STATE_UP);
1bb60376 2244#if IS_ENABLED(CONFIG_IPV6)
01bcca68 2245 update_clip(adap);
1bb60376 2246#endif
fc08a01a
HS		 2247 /* Initialize hash mac addr list*/
2248 INIT_LIST_HEAD(&adap->mac_hlist);
b8ff05a9 2249 return err;
91060381 2250
b8ff05a9
DM		 2251 irq_err:
2252 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
aaefae9b
DM		 2253 freeq:
2254 t4_free_sge_resources(adap);
91060381
RR		 2255 rel_lock:
2256 mutex_unlock(&uld_mutex);
2257 return err;
b8ff05a9
DM		 2258}
2259
2260static void cxgb_down(struct adapter *adapter)
2261{
b8ff05a9 2262 cancel_work_sync(&adapter->tid_release_task);
881806bc
VP		 2263 cancel_work_sync(&adapter->db_full_task);
2264 cancel_work_sync(&adapter->db_drop_task);
b8ff05a9 2265 adapter->tid_release_task_busy = false;
204dc3c0 2266 adapter->tid_release_head = NULL;
b8ff05a9 2267
aaefae9b
DM		 2268 t4_sge_stop(adapter);
2269 t4_free_sge_resources(adapter);
2270 adapter->flags &= ~FULL_INIT_DONE;
b8ff05a9
DM		 2271}
2272
2273/*
2274 * net_device operations
2275 */
2276static int cxgb_open(struct net_device *dev)
2277{
2278 int err;
2279 struct port_info *pi = netdev_priv(dev);
2280 struct adapter *adapter = pi->adapter;
2281
6a3c869a
DM		 2282 netif_carrier_off(dev);
2283
aaefae9b
DM		 2284 if (!(adapter->flags & FULL_INIT_DONE)) {
2285 err = cxgb_up(adapter);
2286 if (err < 0)
2287 return err;
2288 }
b8ff05a9 2289
2061ec3f
GG		 2290 /* It's possible that the basic port information could have
2291 * changed since we first read it.
2292 */
2293 err = t4_update_port_info(pi);
2294 if (err < 0)
2295 return err;
2296
f68707b8
DM		 2297 err = link_start(dev);
2298 if (!err)
2299 netif_tx_start_all_queues(dev);
2300 return err;
b8ff05a9
DM		 2301}
2302
2303static int cxgb_close(struct net_device *dev)
2304{
b8ff05a9
DM		 2305 struct port_info *pi = netdev_priv(dev);
2306 struct adapter *adapter = pi->adapter;
2307
2308 netif_tx_stop_all_queues(dev);
2309 netif_carrier_off(dev);
b2612722 2310 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
b8ff05a9
DM		 2311}
2312
dca4faeb 2313int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
793dad94
VP		 2314 __be32 sip, __be16 sport, __be16 vlan,
2315 unsigned int queue, unsigned char port, unsigned char mask)
dca4faeb
VP		 2316{
2317 int ret;
2318 struct filter_entry *f;
2319 struct adapter *adap;
2320 int i;
2321 u8 *val;
2322
2323 adap = netdev2adap(dev);
2324
1cab775c 2325 /* Adjust stid to correct filter index */
470c60c4 2326 stid -= adap->tids.sftid_base;
1cab775c
VP		 2327 stid += adap->tids.nftids;
2328
dca4faeb
VP		 2329 /* Check to make sure the filter requested is writable ...
2330 */
2331 f = &adap->tids.ftid_tab[stid];
2332 ret = writable_filter(f);
2333 if (ret)
2334 return ret;
2335
2336 /* Clear out any old resources being used by the filter before
2337 * we start constructing the new filter.
2338 */
2339 if (f->valid)
2340 clear_filter(adap, f);
2341
2342 /* Clear out filter specifications */
2343 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2344 f->fs.val.lport = cpu_to_be16(sport);
2345 f->fs.mask.lport = ~0;
2346 val = (u8 *)&sip;
793dad94 2347 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
dca4faeb
VP		 2348 for (i = 0; i < 4; i++) {
2349 f->fs.val.lip[i] = val[i];
2350 f->fs.mask.lip[i] = ~0;
2351 }
0d804338 2352 if (adap->params.tp.vlan_pri_map & PORT_F) {
793dad94
VP		 2353 f->fs.val.iport = port;
2354 f->fs.mask.iport = mask;
2355 }
2356 }
dca4faeb 2357
0d804338 2358 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
7c89e555
KS		 2359 f->fs.val.proto = IPPROTO_TCP;
2360 f->fs.mask.proto = ~0;
2361 }
2362
dca4faeb
VP		 2363 f->fs.dirsteer = 1;
2364 f->fs.iq = queue;
2365 /* Mark filter as locked */
2366 f->locked = 1;
2367 f->fs.rpttid = 1;
2368
6b254afd
GG		 2369 /* Save the actual tid. We need this to get the corresponding
2370 * filter entry structure in filter_rpl.
2371 */
2372 f->tid = stid + adap->tids.ftid_base;
dca4faeb
VP		 2373 ret = set_filter_wr(adap, stid);
2374 if (ret) {
2375 clear_filter(adap, f);
2376 return ret;
2377 }
2378
2379 return 0;
2380}
2381EXPORT_SYMBOL(cxgb4_create_server_filter);
2382
2383int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2384 unsigned int queue, bool ipv6)
2385{
dca4faeb
VP		 2386 struct filter_entry *f;
2387 struct adapter *adap;
2388
2389 adap = netdev2adap(dev);
1cab775c
VP		 2390
2391 /* Adjust stid to correct filter index */
470c60c4 2392 stid -= adap->tids.sftid_base;
1cab775c
VP		 2393 stid += adap->tids.nftids;
2394
dca4faeb
VP		 2395 f = &adap->tids.ftid_tab[stid];
2396 /* Unlock the filter */
2397 f->locked = 0;
2398
8c14846d 2399 return delete_filter(adap, stid);
dca4faeb
VP		 2400}
2401EXPORT_SYMBOL(cxgb4_remove_server_filter);
2402
bc1f4470 2403static void cxgb_get_stats(struct net_device *dev,
2404 struct rtnl_link_stats64 *ns)
b8ff05a9
DM		 2405{
2406 struct port_stats stats;
2407 struct port_info *p = netdev_priv(dev);
2408 struct adapter *adapter = p->adapter;
b8ff05a9 2409
9fe6cb58
GS		 2410 /* Block retrieving statistics during EEH error
2411 * recovery. Otherwise, the recovery might fail
2412 * and the PCI device will be removed permanently
2413 */
b8ff05a9 2414 spin_lock(&adapter->stats_lock);
9fe6cb58
GS		 2415 if (!netif_device_present(dev)) {
2416 spin_unlock(&adapter->stats_lock);
bc1f4470 2417 return;
9fe6cb58 2418 }
a4cfd929
HS		 2419 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2420 &p->stats_base);
b8ff05a9
DM		 2421 spin_unlock(&adapter->stats_lock);
2422
2423 ns->tx_bytes = stats.tx_octets;
2424 ns->tx_packets = stats.tx_frames;
2425 ns->rx_bytes = stats.rx_octets;
2426 ns->rx_packets = stats.rx_frames;
2427 ns->multicast = stats.rx_mcast_frames;
2428
2429 /* detailed rx_errors */
2430 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2431 stats.rx_runt;
2432 ns->rx_over_errors = 0;
2433 ns->rx_crc_errors = stats.rx_fcs_err;
2434 ns->rx_frame_errors = stats.rx_symbol_err;
b93f79be 2435 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 +
b8ff05a9
DM		 2436 stats.rx_ovflow2 + stats.rx_ovflow3 +
2437 stats.rx_trunc0 + stats.rx_trunc1 +
2438 stats.rx_trunc2 + stats.rx_trunc3;
2439 ns->rx_missed_errors = 0;
2440
2441 /* detailed tx_errors */
2442 ns->tx_aborted_errors = 0;
2443 ns->tx_carrier_errors = 0;
2444 ns->tx_fifo_errors = 0;
2445 ns->tx_heartbeat_errors = 0;
2446 ns->tx_window_errors = 0;
2447
2448 ns->tx_errors = stats.tx_error_frames;
2449 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2450 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
b8ff05a9
DM		 2451}
2452
2453static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2454{
060e0c75 2455 unsigned int mbox;
b8ff05a9
DM		 2456 int ret = 0, prtad, devad;
2457 struct port_info *pi = netdev_priv(dev);
a4569504 2458 struct adapter *adapter = pi->adapter;
b8ff05a9
DM		 2459 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2460
2461 switch (cmd) {
2462 case SIOCGMIIPHY:
2463 if (pi->mdio_addr < 0)
2464 return -EOPNOTSUPP;
2465 data->phy_id = pi->mdio_addr;
2466 break;
2467 case SIOCGMIIREG:
2468 case SIOCSMIIREG:
2469 if (mdio_phy_id_is_c45(data->phy_id)) {
2470 prtad = mdio_phy_id_prtad(data->phy_id);
2471 devad = mdio_phy_id_devad(data->phy_id);
2472 } else if (data->phy_id < 32) {
2473 prtad = data->phy_id;
2474 devad = 0;
2475 data->reg_num &= 0x1f;
2476 } else
2477 return -EINVAL;
2478
b2612722 2479 mbox = pi->adapter->pf;
b8ff05a9 2480 if (cmd == SIOCGMIIREG)
060e0c75 2481 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2482 data->reg_num, &data->val_out);
2483 else
060e0c75 2484 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
b8ff05a9
DM		 2485 data->reg_num, data->val_in);
2486 break;
5e2a5ebc
HS		 2487 case SIOCGHWTSTAMP:
2488 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2489 sizeof(pi->tstamp_config)) ?
2490 -EFAULT : 0;
2491 case SIOCSHWTSTAMP:
2492 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2493 sizeof(pi->tstamp_config)))
2494 return -EFAULT;
2495
a4569504
AG		 2496 if (!is_t4(adapter->params.chip)) {
2497 switch (pi->tstamp_config.tx_type) {
2498 case HWTSTAMP_TX_OFF:
2499 case HWTSTAMP_TX_ON:
2500 break;
2501 default:
2502 return -ERANGE;
2503 }
2504
2505 switch (pi->tstamp_config.rx_filter) {
2506 case HWTSTAMP_FILTER_NONE:
2507 pi->rxtstamp = false;
2508 break;
2509 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2510 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2511 cxgb4_ptprx_timestamping(pi, pi->port_id,
2512 PTP_TS_L4);
2513 break;
2514 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2515 cxgb4_ptprx_timestamping(pi, pi->port_id,
2516 PTP_TS_L2_L4);
2517 break;
2518 case HWTSTAMP_FILTER_ALL:
2519 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2520 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2521 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2522 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2523 pi->rxtstamp = true;
2524 break;
2525 default:
2526 pi->tstamp_config.rx_filter =
2527 HWTSTAMP_FILTER_NONE;
2528 return -ERANGE;
2529 }
2530
2531 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2532 (pi->tstamp_config.rx_filter ==
2533 HWTSTAMP_FILTER_NONE)) {
2534 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2535 pi->ptp_enable = false;
2536 }
2537
2538 if (pi->tstamp_config.rx_filter !=
2539 HWTSTAMP_FILTER_NONE) {
2540 if (cxgb4_ptp_redirect_rx_packet(adapter,
2541 pi) >= 0)
2542 pi->ptp_enable = true;
2543 }
2544 } else {
2545 /* For T4 Adapters */
2546 switch (pi->tstamp_config.rx_filter) {
2547 case HWTSTAMP_FILTER_NONE:
5e2a5ebc
HS		 2548 pi->rxtstamp = false;
2549 break;
a4569504 2550 case HWTSTAMP_FILTER_ALL:
5e2a5ebc
HS		 2551 pi->rxtstamp = true;
2552 break;
a4569504
AG		 2553 default:
2554 pi->tstamp_config.rx_filter =
2555 HWTSTAMP_FILTER_NONE;
5e2a5ebc 2556 return -ERANGE;
a4569504 2557 }
5e2a5ebc 2558 }
5e2a5ebc
HS		 2559 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2560 sizeof(pi->tstamp_config)) ?
2561 -EFAULT : 0;
b8ff05a9
DM		 2562 default:
2563 return -EOPNOTSUPP;
2564 }
2565 return ret;
2566}
2567
2568static void cxgb_set_rxmode(struct net_device *dev)
2569{
2570 /* unfortunately we can't return errors to the stack */
2571 set_rxmode(dev, -1, false);
2572}
2573
2574static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2575{
2576 int ret;
2577 struct port_info *pi = netdev_priv(dev);
2578
b2612722 2579 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
060e0c75 2580 -1, -1, -1, true);
b8ff05a9
DM		 2581 if (!ret)
2582 dev->mtu = new_mtu;
2583 return ret;
2584}
2585
858aa65c 2586#ifdef CONFIG_PCI_IOV
e7b48a32
HS		 2587static int dummy_open(struct net_device *dev)
2588{
2589 /* Turn carrier off since we don't have to transmit anything on this
2590 * interface.
2591 */
2592 netif_carrier_off(dev);
2593 return 0;
2594}
2595
661dbeb9
HS		 2596/* Fill MAC address that will be assigned by the FW */
2597static void fill_vf_station_mac_addr(struct adapter *adap)
2598{
2599 unsigned int i;
2600 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2601 int err;
2602 u8 *na;
2603 u16 a, b;
2604
2605 err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2606 if (!err) {
2607 na = adap->params.vpd.na;
2608 for (i = 0; i < ETH_ALEN; i++)
2609 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2610 hex2val(na[2 * i + 1]));
2611 a = (hw_addr[0] << 8) | hw_addr[1];
2612 b = (hw_addr[1] << 8) | hw_addr[2];
2613 a ^= b;
2614 a |= 0x0200; /* locally assigned Ethernet MAC address */
2615 a &= ~0x0100; /* not a multicast Ethernet MAC address */
2616 macaddr[0] = a >> 8;
2617 macaddr[1] = a & 0xff;
2618
2619 for (i = 2; i < 5; i++)
2620 macaddr[i] = hw_addr[i + 1];
2621
2622 for (i = 0; i < adap->num_vfs; i++) {
2623 macaddr[5] = adap->pf * 16 + i;
2624 ether_addr_copy(adap->vfinfo[i].vf_mac_addr, macaddr);
2625 }
2626 }
2627}
2628
858aa65c
HS		 2629static int cxgb_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2630{
2631 struct port_info *pi = netdev_priv(dev);
2632 struct adapter *adap = pi->adapter;
661dbeb9 2633 int ret;
858aa65c
HS		 2634
2635 /* verify MAC addr is valid */
2636 if (!is_valid_ether_addr(mac)) {
2637 dev_err(pi->adapter->pdev_dev,
2638 "Invalid Ethernet address %pM for VF %d\n",
2639 mac, vf);
2640 return -EINVAL;
2641 }
2642
2643 dev_info(pi->adapter->pdev_dev,
2644 "Setting MAC %pM on VF %d\n", mac, vf);
661dbeb9
HS		 2645 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2646 if (!ret)
2647 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2648 return ret;
2649}
2650
2651static int cxgb_get_vf_config(struct net_device *dev,
2652 int vf, struct ifla_vf_info *ivi)
2653{
2654 struct port_info *pi = netdev_priv(dev);
2655 struct adapter *adap = pi->adapter;
2656
2657 if (vf >= adap->num_vfs)
2658 return -EINVAL;
2659 ivi->vf = vf;
8ea4fae9
GG		 2660 ivi->max_tx_rate = adap->vfinfo[vf].tx_rate;
2661 ivi->min_tx_rate = 0;
661dbeb9
HS		 2662 ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr);
2663 return 0;
858aa65c 2664}
96fe11f2
GG		 2665
2666static int cxgb_get_phys_port_id(struct net_device *dev,
2667 struct netdev_phys_item_id *ppid)
2668{
2669 struct port_info *pi = netdev_priv(dev);
2670 unsigned int phy_port_id;
2671
2672 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2673 ppid->id_len = sizeof(phy_port_id);
2674 memcpy(ppid->id, &phy_port_id, ppid->id_len);
2675 return 0;
2676}
2677
8ea4fae9
GG		 2678static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2679 int max_tx_rate)
2680{
2681 struct port_info *pi = netdev_priv(dev);
2682 struct adapter *adap = pi->adapter;
c3168cab 2683 unsigned int link_ok, speed, mtu;
8ea4fae9
GG		 2684 u32 fw_pfvf, fw_class;
2685 int class_id = vf;
c3168cab 2686 int ret;
8ea4fae9
GG		 2687 u16 pktsize;
2688
2689 if (vf >= adap->num_vfs)
2690 return -EINVAL;
2691
2692 if (min_tx_rate) {
2693 dev_err(adap->pdev_dev,
2694 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2695 min_tx_rate, vf);
2696 return -EINVAL;
2697 }
c3168cab
GG		 2698
2699 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
8ea4fae9
GG		 2700 if (ret != FW_SUCCESS) {
2701 dev_err(adap->pdev_dev,
c3168cab 2702 "Failed to get link information for VF %d\n", vf);
8ea4fae9
GG		 2703 return -EINVAL;
2704 }
c3168cab 2705
8ea4fae9
GG		 2706 if (!link_ok) {
2707 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2708 return -EINVAL;
2709 }
8ea4fae9
GG		 2710
2711 if (max_tx_rate > speed) {
2712 dev_err(adap->pdev_dev,
2713 "Max tx rate %d for VF %d can't be > link-speed %u",
2714 max_tx_rate, vf, speed);
2715 return -EINVAL;
2716 }
c3168cab
GG		 2717
2718 pktsize = mtu;
8ea4fae9
GG		 2719 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2720 pktsize = pktsize - sizeof(struct ethhdr) - 4;
2721 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2722 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2723 /* configure Traffic Class for rate-limiting */
2724 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2725 SCHED_CLASS_LEVEL_CL_RL,
2726 SCHED_CLASS_MODE_CLASS,
2727 SCHED_CLASS_RATEUNIT_BITS,
2728 SCHED_CLASS_RATEMODE_ABS,
c3168cab 2729 pi->tx_chan, class_id, 0,
8ea4fae9
GG		 2730 max_tx_rate * 1000, 0, pktsize);
2731 if (ret) {
2732 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2733 ret);
2734 return -EINVAL;
2735 }
2736 dev_info(adap->pdev_dev,
2737 "Class %d with MSS %u configured with rate %u\n",
2738 class_id, pktsize, max_tx_rate);
2739
2740 /* bind VF to configured Traffic Class */
2741 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2742 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2743 fw_class = class_id;
2744 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2745 &fw_class);
2746 if (ret) {
2747 dev_err(adap->pdev_dev,
2748 "Err %d in binding VF %d to Traffic Class %d\n",
2749 ret, vf, class_id);
2750 return -EINVAL;
2751 }
2752 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2753 adap->pf, vf, class_id);
2754 adap->vfinfo[vf].tx_rate = max_tx_rate;
2755 return 0;
2756}
2757
858aa65c
HS		 2758#endif
2759
b8ff05a9
DM		 2760static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2761{
2762 int ret;
2763 struct sockaddr *addr = p;
2764 struct port_info *pi = netdev_priv(dev);
2765
2766 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 2767 return -EADDRNOTAVAIL;
b8ff05a9 2768
b2612722 2769 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
060e0c75 2770 pi->xact_addr_filt, addr->sa_data, true, true);
b8ff05a9
DM		 2771 if (ret < 0)
2772 return ret;
2773
2774 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2775 pi->xact_addr_filt = ret;
2776 return 0;
2777}
2778
b8ff05a9
DM		 2779#ifdef CONFIG_NET_POLL_CONTROLLER
2780static void cxgb_netpoll(struct net_device *dev)
2781{
2782 struct port_info *pi = netdev_priv(dev);
2783 struct adapter *adap = pi->adapter;
2784
2785 if (adap->flags & USING_MSIX) {
2786 int i;
2787 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2788
2789 for (i = pi->nqsets; i; i--, rx++)
2790 t4_sge_intr_msix(0, &rx->rspq);
2791 } else
2792 t4_intr_handler(adap)(0, adap);
2793}
2794#endif
2795
10a2604e
RL		 2796static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2797{
2798 struct port_info *pi = netdev_priv(dev);
2799 struct adapter *adap = pi->adapter;
2800 struct sched_class *e;
2801 struct ch_sched_params p;
2802 struct ch_sched_queue qe;
2803 u32 req_rate;
2804 int err = 0;
2805
2806 if (!can_sched(dev))
2807 return -ENOTSUPP;
2808
2809 if (index < 0 || index > pi->nqsets - 1)
2810 return -EINVAL;
2811
2812 if (!(adap->flags & FULL_INIT_DONE)) {
2813 dev_err(adap->pdev_dev,
2814 "Failed to rate limit on queue %d. Link Down?\n",
2815 index);
2816 return -EINVAL;
2817 }
2818
2819 /* Convert from Mbps to Kbps */
2820 req_rate = rate << 10;
2821
2822 /* Max rate is 10 Gbps */
2823 if (req_rate >= SCHED_MAX_RATE_KBPS) {
2824 dev_err(adap->pdev_dev,
2825 "Invalid rate %u Mbps, Max rate is %u Gbps\n",
2826 rate, SCHED_MAX_RATE_KBPS);
2827 return -ERANGE;
2828 }
2829
2830 /* First unbind the queue from any existing class */
2831 memset(&qe, 0, sizeof(qe));
2832 qe.queue = index;
2833 qe.class = SCHED_CLS_NONE;
2834
2835 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
2836 if (err) {
2837 dev_err(adap->pdev_dev,
2838 "Unbinding Queue %d on port %d fail. Err: %d\n",
2839 index, pi->port_id, err);
2840 return err;
2841 }
2842
2843 /* Queue already unbound */
2844 if (!req_rate)
2845 return 0;
2846
2847 /* Fetch any available unused or matching scheduling class */
2848 memset(&p, 0, sizeof(p));
2849 p.type = SCHED_CLASS_TYPE_PACKET;
2850 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL;
2851 p.u.params.mode = SCHED_CLASS_MODE_CLASS;
2852 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
2853 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
2854 p.u.params.channel = pi->tx_chan;
2855 p.u.params.class = SCHED_CLS_NONE;
2856 p.u.params.minrate = 0;
2857 p.u.params.maxrate = req_rate;
2858 p.u.params.weight = 0;
2859 p.u.params.pktsize = dev->mtu;
2860
2861 e = cxgb4_sched_class_alloc(dev, &p);
2862 if (!e)
2863 return -ENOMEM;
2864
2865 /* Bind the queue to a scheduling class */
2866 memset(&qe, 0, sizeof(qe));
2867 qe.queue = index;
2868 qe.class = e->idx;
2869
2870 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
2871 if (err)
2872 dev_err(adap->pdev_dev,
2873 "Queue rate limiting failed. Err: %d\n", err);
2874 return err;
2875}
2876
6a345b3d
KS		 2877static int cxgb_setup_tc_flower(struct net_device *dev,
2878 struct tc_cls_flower_offload *cls_flower)
2879{
2880 if (!is_classid_clsact_ingress(cls_flower->common.classid) ||
2881 cls_flower->common.chain_index)
2882 return -EOPNOTSUPP;
2883
2884 switch (cls_flower->command) {
2885 case TC_CLSFLOWER_REPLACE:
2886 return cxgb4_tc_flower_replace(dev, cls_flower);
2887 case TC_CLSFLOWER_DESTROY:
2888 return cxgb4_tc_flower_destroy(dev, cls_flower);
2889 case TC_CLSFLOWER_STATS:
2890 return cxgb4_tc_flower_stats(dev, cls_flower);
2891 default:
2892 return -EOPNOTSUPP;
2893 }
2894}
2895
f7323043 2896static int cxgb_setup_tc_cls_u32(struct net_device *dev,
f7323043
JP		 2897 struct tc_cls_u32_offload *cls_u32)
2898{
7f3b39da 2899 if (!is_classid_clsact_ingress(cls_u32->common.classid) ||
5fd9fc4e 2900 cls_u32->common.chain_index)
f7323043
JP		 2901 return -EOPNOTSUPP;
2902
2903 switch (cls_u32->command) {
2904 case TC_CLSU32_NEW_KNODE:
2905 case TC_CLSU32_REPLACE_KNODE:
5fd9fc4e 2906 return cxgb4_config_knode(dev, cls_u32);
f7323043 2907 case TC_CLSU32_DELETE_KNODE:
5fd9fc4e 2908 return cxgb4_delete_knode(dev, cls_u32);
f7323043
JP		 2909 default:
2910 return -EOPNOTSUPP;
2911 }
2912}
2913
2572ac53 2914static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 2915 void *type_data)
d8931847
RL		 2916{
2917 struct port_info *pi = netdev2pinfo(dev);
2918 struct adapter *adap = netdev2adap(dev);
2919
2920 if (!(adap->flags & FULL_INIT_DONE)) {
2921 dev_err(adap->pdev_dev,
2922 "Failed to setup tc on port %d. Link Down?\n",
2923 pi->port_id);
2924 return -EINVAL;
2925 }
2926
f7323043
JP		 2927 switch (type) {
2928 case TC_SETUP_CLSU32:
de4784ca 2929 return cxgb_setup_tc_cls_u32(dev, type_data);
6a345b3d
KS		 2930 case TC_SETUP_CLSFLOWER:
2931 return cxgb_setup_tc_flower(dev, type_data);
f7323043
JP		 2932 default:
2933 return -EOPNOTSUPP;
d8931847 2934 }
d8931847
RL		 2935}
2936
90592b9a
AV		 2937static netdev_features_t cxgb_fix_features(struct net_device *dev,
2938 netdev_features_t features)
2939{
2940 /* Disable GRO, if RX_CSUM is disabled */
2941 if (!(features & NETIF_F_RXCSUM))
2942 features &= ~NETIF_F_GRO;
2943
2944 return features;
2945}
2946
b8ff05a9
DM		 2947static const struct net_device_ops cxgb4_netdev_ops = {
2948 .ndo_open = cxgb_open,
2949 .ndo_stop = cxgb_close,
2950 .ndo_start_xmit = t4_eth_xmit,
688848b1 2951 .ndo_select_queue = cxgb_select_queue,
9be793bf 2952 .ndo_get_stats64 = cxgb_get_stats,
b8ff05a9
DM		 2953 .ndo_set_rx_mode = cxgb_set_rxmode,
2954 .ndo_set_mac_address = cxgb_set_mac_addr,
2ed28baa 2955 .ndo_set_features = cxgb_set_features,
b8ff05a9
DM		 2956 .ndo_validate_addr = eth_validate_addr,
2957 .ndo_do_ioctl = cxgb_ioctl,
2958 .ndo_change_mtu = cxgb_change_mtu,
b8ff05a9
DM		 2959#ifdef CONFIG_NET_POLL_CONTROLLER
2960 .ndo_poll_controller = cxgb_netpoll,
2961#endif
84a200b3
VP		 2962#ifdef CONFIG_CHELSIO_T4_FCOE
2963 .ndo_fcoe_enable = cxgb_fcoe_enable,
2964 .ndo_fcoe_disable = cxgb_fcoe_disable,
2965#endif /* CONFIG_CHELSIO_T4_FCOE */
10a2604e 2966 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate,
d8931847 2967 .ndo_setup_tc = cxgb_setup_tc,
90592b9a 2968 .ndo_fix_features = cxgb_fix_features,
b8ff05a9
DM		 2969};
2970
858aa65c 2971#ifdef CONFIG_PCI_IOV
e7b48a32
HS		 2972static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
2973 .ndo_open = dummy_open,
858aa65c 2974 .ndo_set_vf_mac = cxgb_set_vf_mac,
661dbeb9 2975 .ndo_get_vf_config = cxgb_get_vf_config,
8ea4fae9 2976 .ndo_set_vf_rate = cxgb_set_vf_rate,
96fe11f2 2977 .ndo_get_phys_port_id = cxgb_get_phys_port_id,
7829451c 2978};
e7b48a32 2979#endif
7829451c
HS		 2980
2981static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2982{
2983 struct adapter *adapter = netdev2adap(dev);
2984
2985 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
2986 strlcpy(info->version, cxgb4_driver_version,
2987 sizeof(info->version));
2988 strlcpy(info->bus_info, pci_name(adapter->pdev),
2989 sizeof(info->bus_info));
2990}
2991
2992static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
2993 .get_drvinfo = get_drvinfo,
2994};
2995
b8ff05a9
DM		 2996void t4_fatal_err(struct adapter *adap)
2997{
3be0679b
HS		 2998 int port;
2999
025d0973
GP		 3000 if (pci_channel_offline(adap->pdev))
3001 return;
3002
3be0679b
HS		 3003 /* Disable the SGE since ULDs are going to free resources that
3004 * could be exposed to the adapter. RDMA MWs for example...
3005 */
3006 t4_shutdown_adapter(adap);
3007 for_each_port(adap, port) {
3008 struct net_device *dev = adap->port[port];
3009
3010 /* If we get here in very early initialization the network
3011 * devices may not have been set up yet.
3012 */
3013 if (!dev)
3014 continue;
3015
3016 netif_tx_stop_all_queues(dev);
3017 netif_carrier_off(dev);
3018 }
b8ff05a9
DM		 3019 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3020}
3021
3022static void setup_memwin(struct adapter *adap)
3023{
b562fc37 3024 u32 nic_win_base = t4_get_util_window(adap);
b8ff05a9 3025
b562fc37 3026 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
636f9d37
VP		 3027}
3028
3029static void setup_memwin_rdma(struct adapter *adap)
3030{
1ae970e0 3031 if (adap->vres.ocq.size) {
0abfd152
HS		 3032 u32 start;
3033 unsigned int sz_kb;
1ae970e0 3034
0abfd152
HS		 3035 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3036 start &= PCI_BASE_ADDRESS_MEM_MASK;
3037 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
1ae970e0
DM		 3038 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3039 t4_write_reg(adap,
f061de42
HS		 3040 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3041 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
1ae970e0 3042 t4_write_reg(adap,
f061de42 3043 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
1ae970e0
DM		 3044 adap->vres.ocq.start);
3045 t4_read_reg(adap,
f061de42 3046 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
1ae970e0 3047 }
b8ff05a9
DM		 3048}
3049
02b5fb8e
DM		 3050static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3051{
3052 u32 v;
3053 int ret;
3054
3055 /* get device capabilities */
3056 memset(c, 0, sizeof(*c));
e2ac9628
HS		 3057 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3058 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3059 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
b2612722 3060 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
02b5fb8e
DM		 3061 if (ret < 0)
3062 return ret;
3063
e2ac9628
HS		 3064 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3065 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
b2612722 3066 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
02b5fb8e
DM		 3067 if (ret < 0)
3068 return ret;
3069
b2612722 3070 ret = t4_config_glbl_rss(adap, adap->pf,
02b5fb8e 3071 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
b2e1a3f0
HS		 3072 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3073 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
02b5fb8e
DM		 3074 if (ret < 0)
3075 return ret;
3076
b2612722 3077 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
4b8e27a8
HS		 3078 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3079 FW_CMD_CAP_PF);
02b5fb8e
DM		 3080 if (ret < 0)
3081 return ret;
3082
3083 t4_sge_init(adap);
3084
02b5fb8e 3085 /* tweak some settings */
837e4a42 3086 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
0d804338 3087 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
837e4a42
HS		 3088 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3089 v = t4_read_reg(adap, TP_PIO_DATA_A);
3090 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
060e0c75 3091
dca4faeb
VP		 3092 /* first 4 Tx modulation queues point to consecutive Tx channels */
3093 adap->params.tp.tx_modq_map = 0xE4;
0d804338
HS		 3094 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3095 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
dca4faeb
VP		 3096
3097 /* associate each Tx modulation queue with consecutive Tx channels */
3098 v = 0x84218421;
837e4a42 3099 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3100 &v, 1, TP_TX_SCHED_HDR_A);
837e4a42 3101 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3102 &v, 1, TP_TX_SCHED_FIFO_A);
837e4a42 3103 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
0d804338 3104 &v, 1, TP_TX_SCHED_PCMD_A);
dca4faeb
VP		 3105
3106#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3107 if (is_offload(adap)) {
0d804338
HS		 3108 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3109 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3110 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3111 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3112 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3113 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3114 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3115 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3116 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3117 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
dca4faeb
VP		 3118 }
3119
060e0c75 3120 /* get basic stuff going */
b2612722 3121 return t4_early_init(adap, adap->pf);
02b5fb8e
DM		 3122}
3123
b8ff05a9
DM		 3124/*
3125 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3126 */
3127#define MAX_ATIDS 8192U
3128
636f9d37
VP		 3129/*
3130 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3131 *
3132 * If the firmware we're dealing with has Configuration File support, then
3133 * we use that to perform all configuration
3134 */
3135
3136/*
3137 * Tweak configuration based on module parameters, etc. Most of these have
3138 * defaults assigned to them by Firmware Configuration Files (if we're using
3139 * them) but need to be explicitly set if we're using hard-coded
3140 * initialization. But even in the case of using Firmware Configuration
3141 * Files, we'd like to expose the ability to change these via module
3142 * parameters so these are essentially common tweaks/settings for
3143 * Configuration Files and hard-coded initialization ...
3144 */
3145static int adap_init0_tweaks(struct adapter *adapter)
3146{
3147 /*
3148 * Fix up various Host-Dependent Parameters like Page Size, Cache
3149 * Line Size, etc. The firmware default is for a 4KB Page Size and
3150 * 64B Cache Line Size ...
3151 */
3152 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3153
3154 /*
3155 * Process module parameters which affect early initialization.
3156 */
3157 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3158 dev_err(&adapter->pdev->dev,
3159 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3160 rx_dma_offset);
3161 rx_dma_offset = 2;
3162 }
f612b815
HS		 3163 t4_set_reg_field(adapter, SGE_CONTROL_A,
3164 PKTSHIFT_V(PKTSHIFT_M),
3165 PKTSHIFT_V(rx_dma_offset));
636f9d37
VP		 3166
3167 /*
3168 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3169 * adds the pseudo header itself.
3170 */
837e4a42
HS		 3171 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3172 CSUM_HAS_PSEUDO_HDR_F, 0);
636f9d37
VP		 3173
3174 return 0;
3175}
3176
01b69614
HS		 3177/* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3178 * unto themselves and they contain their own firmware to perform their
3179 * tasks ...
3180 */
3181static int phy_aq1202_version(const u8 *phy_fw_data,
3182 size_t phy_fw_size)
3183{
3184 int offset;
3185
3186 /* At offset 0x8 you're looking for the primary image's
3187 * starting offset which is 3 Bytes wide
3188 *
3189 * At offset 0xa of the primary image, you look for the offset
3190 * of the DRAM segment which is 3 Bytes wide.
3191 *
3192 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3193 * wide
3194 */
3195 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3196 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3197 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3198
3199 offset = le24(phy_fw_data + 0x8) << 12;
3200 offset = le24(phy_fw_data + offset + 0xa);
3201 return be16(phy_fw_data + offset + 0x27e);
3202
3203 #undef be16
3204 #undef le16
3205 #undef le24
3206}
3207
3208static struct info_10gbt_phy_fw {
3209 unsigned int phy_fw_id; /* PCI Device ID */
3210 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3211 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3212 int phy_flash; /* Has FLASH for PHY Firmware */
3213} phy_info_array[] = {
3214 {
3215 PHY_AQ1202_DEVICEID,
3216 PHY_AQ1202_FIRMWARE,
3217 phy_aq1202_version,
3218 1,
3219 },
3220 {
3221 PHY_BCM84834_DEVICEID,
3222 PHY_BCM84834_FIRMWARE,
3223 NULL,
3224 0,
3225 },
3226 { 0, NULL, NULL },
3227};
3228
3229static struct info_10gbt_phy_fw *find_phy_info(int devid)
3230{
3231 int i;
3232
3233 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3234 if (phy_info_array[i].phy_fw_id == devid)
3235 return &phy_info_array[i];
3236 }
3237 return NULL;
3238}
3239
3240/* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3241 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3242 * we return a negative error number. If we transfer new firmware we return 1
3243 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3244 */
3245static int adap_init0_phy(struct adapter *adap)
3246{
3247 const struct firmware *phyf;
3248 int ret;
3249 struct info_10gbt_phy_fw *phy_info;
3250
3251 /* Use the device ID to determine which PHY file to flash.
3252 */
3253 phy_info = find_phy_info(adap->pdev->device);
3254 if (!phy_info) {
3255 dev_warn(adap->pdev_dev,
3256 "No PHY Firmware file found for this PHY\n");
3257 return -EOPNOTSUPP;
3258 }
3259
3260 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3261 * use that. The adapter firmware provides us with a memory buffer
3262 * where we can load a PHY firmware file from the host if we want to
3263 * override the PHY firmware File in flash.
3264 */
3265 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3266 adap->pdev_dev);
3267 if (ret < 0) {
3268 /* For adapters without FLASH attached to PHY for their
3269 * firmware, it's obviously a fatal error if we can't get the
3270 * firmware to the adapter. For adapters with PHY firmware
3271 * FLASH storage, it's worth a warning if we can't find the
3272 * PHY Firmware but we'll neuter the error ...
3273 */
3274 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3275 "/lib/firmware/%s, error %d\n",
3276 phy_info->phy_fw_file, -ret);
3277 if (phy_info->phy_flash) {
3278 int cur_phy_fw_ver = 0;
3279
3280 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3281 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3282 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3283 ret = 0;
3284 }
3285
3286 return ret;
3287 }
3288
3289 /* Load PHY Firmware onto adapter.
3290 */
3291 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3292 phy_info->phy_fw_version,
3293 (u8 *)phyf->data, phyf->size);
3294 if (ret < 0)
3295 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3296 -ret);
3297 else if (ret > 0) {
3298 int new_phy_fw_ver = 0;
3299
3300 if (phy_info->phy_fw_version)
3301 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3302 phyf->size);
3303 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3304 "Firmware /lib/firmware/%s, version %#x\n",
3305 phy_info->phy_fw_file, new_phy_fw_ver);
3306 }
3307
3308 release_firmware(phyf);
3309
3310 return ret;
3311}
3312
636f9d37
VP		 3313/*
3314 * Attempt to initialize the adapter via a Firmware Configuration File.
3315 */
3316static int adap_init0_config(struct adapter *adapter, int reset)
3317{
3318 struct fw_caps_config_cmd caps_cmd;
3319 const struct firmware *cf;
3320 unsigned long mtype = 0, maddr = 0;
3321 u32 finiver, finicsum, cfcsum;
16e47624
HS		 3322 int ret;
3323 int config_issued = 0;
0a57a536 3324 char *fw_config_file, fw_config_file_path[256];
16e47624 3325 char *config_name = NULL;
636f9d37
VP		 3326
3327 /*
3328 * Reset device if necessary.
3329 */
3330 if (reset) {
3331 ret = t4_fw_reset(adapter, adapter->mbox,
0d804338 3332 PIORSTMODE_F | PIORST_F);
636f9d37
VP		 3333 if (ret < 0)
3334 goto bye;
3335 }
3336
01b69614
HS		 3337 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3338 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3339 * to be performed after any global adapter RESET above since some
3340 * PHYs only have local RAM copies of the PHY firmware.
3341 */
3342 if (is_10gbt_device(adapter->pdev->device)) {
3343 ret = adap_init0_phy(adapter);
3344 if (ret < 0)
3345 goto bye;
3346 }
636f9d37
VP		 3347 /*
3348 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3349 * then use that. Otherwise, use the configuration file stored
3350 * in the adapter flash ...
3351 */
d14807dd 3352 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
0a57a536 3353 case CHELSIO_T4:
16e47624 3354 fw_config_file = FW4_CFNAME;
0a57a536
SR		 3355 break;
3356 case CHELSIO_T5:
3357 fw_config_file = FW5_CFNAME;
3358 break;
3ccc6cf7
HS		 3359 case CHELSIO_T6:
3360 fw_config_file = FW6_CFNAME;
3361 break;
0a57a536
SR		 3362 default:
3363 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3364 adapter->pdev->device);
3365 ret = -EINVAL;
3366 goto bye;
3367 }
3368
3369 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
636f9d37 3370 if (ret < 0) {
16e47624 3371 config_name = "On FLASH";
636f9d37
VP		 3372 mtype = FW_MEMTYPE_CF_FLASH;
3373 maddr = t4_flash_cfg_addr(adapter);
3374 } else {
3375 u32 params[7], val[7];
3376
16e47624
HS		 3377 sprintf(fw_config_file_path,
3378 "/lib/firmware/%s", fw_config_file);
3379 config_name = fw_config_file_path;
3380
636f9d37
VP		 3381 if (cf->size >= FLASH_CFG_MAX_SIZE)
3382 ret = -ENOMEM;
3383 else {
5167865a
HS		 3384 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3385 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
636f9d37 3386 ret = t4_query_params(adapter, adapter->mbox,
b2612722 3387 adapter->pf, 0, 1, params, val);
636f9d37
VP		 3388 if (ret == 0) {
3389 /*
fc5ab020 3390 * For t4_memory_rw() below addresses and
636f9d37
VP		 3391 * sizes have to be in terms of multiples of 4
3392 * bytes. So, if the Configuration File isn't
3393 * a multiple of 4 bytes in length we'll have
3394 * to write that out separately since we can't
3395 * guarantee that the bytes following the
3396 * residual byte in the buffer returned by
3397 * request_firmware() are zeroed out ...
3398 */
3399 size_t resid = cf->size & 0x3;
3400 size_t size = cf->size & ~0x3;
3401 __be32 *data = (__be32 *)cf->data;
3402
5167865a
HS		 3403 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3404 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
636f9d37 3405
fc5ab020
HS		 3406 spin_lock(&adapter->win0_lock);
3407 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3408 size, data, T4_MEMORY_WRITE);
636f9d37
VP		 3409 if (ret == 0 && resid != 0) {
3410 union {
3411 __be32 word;
3412 char buf[4];
3413 } last;
3414 int i;
3415
3416 last.word = data[size >> 2];
3417 for (i = resid; i < 4; i++)
3418 last.buf[i] = 0;
fc5ab020
HS		 3419 ret = t4_memory_rw(adapter, 0, mtype,
3420 maddr + size,
3421 4, &last.word,
3422 T4_MEMORY_WRITE);
636f9d37 3423 }
fc5ab020 3424 spin_unlock(&adapter->win0_lock);
636f9d37
VP		 3425 }
3426 }
3427
3428 release_firmware(cf);
3429 if (ret)
3430 goto bye;
3431 }
3432
3433 /*
3434 * Issue a Capability Configuration command to the firmware to get it
3435 * to parse the Configuration File. We don't use t4_fw_config_file()
3436 * because we want the ability to modify various features after we've
3437 * processed the configuration file ...
3438 */
3439 memset(&caps_cmd, 0, sizeof(caps_cmd));
3440 caps_cmd.op_to_write =
e2ac9628
HS		 3441 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3442 FW_CMD_REQUEST_F |
3443 FW_CMD_READ_F);
ce91a923 3444 caps_cmd.cfvalid_to_len16 =
5167865a
HS		 3445 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3446 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3447 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
636f9d37
VP		 3448 FW_LEN16(caps_cmd));
3449 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3450 &caps_cmd);
16e47624
HS		 3451
3452 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3453 * Configuration File in FLASH), our last gasp effort is to use the
3454 * Firmware Configuration File which is embedded in the firmware. A
3455 * very few early versions of the firmware didn't have one embedded
3456 * but we can ignore those.
3457 */
3458 if (ret == -ENOENT) {
3459 memset(&caps_cmd, 0, sizeof(caps_cmd));
3460 caps_cmd.op_to_write =
e2ac9628
HS		 3461 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3462 FW_CMD_REQUEST_F |
3463 FW_CMD_READ_F);
16e47624
HS		 3464 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3465 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3466 sizeof(caps_cmd), &caps_cmd);
3467 config_name = "Firmware Default";
3468 }
3469
3470 config_issued = 1;
636f9d37
VP		 3471 if (ret < 0)
3472 goto bye;
3473
3474 finiver = ntohl(caps_cmd.finiver);
3475 finicsum = ntohl(caps_cmd.finicsum);
3476 cfcsum = ntohl(caps_cmd.cfcsum);
3477 if (finicsum != cfcsum)
3478 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3479 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3480 finicsum, cfcsum);
3481
636f9d37
VP		 3482 /*
3483 * And now tell the firmware to use the configuration we just loaded.
3484 */
3485 caps_cmd.op_to_write =
e2ac9628
HS		 3486 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3487 FW_CMD_REQUEST_F |
3488 FW_CMD_WRITE_F);
ce91a923 3489 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3490 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3491 NULL);
3492 if (ret < 0)
3493 goto bye;
3494
3495 /*
3496 * Tweak configuration based on system architecture, module
3497 * parameters, etc.
3498 */
3499 ret = adap_init0_tweaks(adapter);
3500 if (ret < 0)
3501 goto bye;
3502
3503 /*
3504 * And finally tell the firmware to initialize itself using the
3505 * parameters from the Configuration File.
3506 */
3507 ret = t4_fw_initialize(adapter, adapter->mbox);
3508 if (ret < 0)
3509 goto bye;
3510
06640310
HS		 3511 /* Emit Firmware Configuration File information and return
3512 * successfully.
636f9d37 3513 */
636f9d37 3514 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
16e47624
HS		 3515 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3516 config_name, finiver, cfcsum);
636f9d37
VP		 3517 return 0;
3518
3519 /*
3520 * Something bad happened. Return the error ... (If the "error"
3521 * is that there's no Configuration File on the adapter we don't
3522 * want to issue a warning since this is fairly common.)
3523 */
3524bye:
16e47624
HS		 3525 if (config_issued && ret != -ENOENT)
3526 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3527 config_name, -ret);
636f9d37
VP		 3528 return ret;
3529}
3530
16e47624
HS		 3531static struct fw_info fw_info_array[] = {
3532 {
3533 .chip = CHELSIO_T4,
3534 .fs_name = FW4_CFNAME,
3535 .fw_mod_name = FW4_FNAME,
3536 .fw_hdr = {
3537 .chip = FW_HDR_CHIP_T4,
3538 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3539 .intfver_nic = FW_INTFVER(T4, NIC),
3540 .intfver_vnic = FW_INTFVER(T4, VNIC),
3541 .intfver_ri = FW_INTFVER(T4, RI),
3542 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3543 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3544 },
3545 }, {
3546 .chip = CHELSIO_T5,
3547 .fs_name = FW5_CFNAME,
3548 .fw_mod_name = FW5_FNAME,
3549 .fw_hdr = {
3550 .chip = FW_HDR_CHIP_T5,
3551 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3552 .intfver_nic = FW_INTFVER(T5, NIC),
3553 .intfver_vnic = FW_INTFVER(T5, VNIC),
3554 .intfver_ri = FW_INTFVER(T5, RI),
3555 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3556 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3557 },
3ccc6cf7
HS		 3558 }, {
3559 .chip = CHELSIO_T6,
3560 .fs_name = FW6_CFNAME,
3561 .fw_mod_name = FW6_FNAME,
3562 .fw_hdr = {
3563 .chip = FW_HDR_CHIP_T6,
3564 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3565 .intfver_nic = FW_INTFVER(T6, NIC),
3566 .intfver_vnic = FW_INTFVER(T6, VNIC),
3567 .intfver_ofld = FW_INTFVER(T6, OFLD),
3568 .intfver_ri = FW_INTFVER(T6, RI),
3569 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3570 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3571 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3572 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3573 },
16e47624 3574 }
3ccc6cf7 3575
16e47624
HS		 3576};
3577
3578static struct fw_info *find_fw_info(int chip)
3579{
3580 int i;
3581
3582 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3583 if (fw_info_array[i].chip == chip)
3584 return &fw_info_array[i];
3585 }
3586 return NULL;
3587}
3588
b8ff05a9
DM		 3589/*
3590 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3591 */
3592static int adap_init0(struct adapter *adap)
3593{
3594 int ret;
3595 u32 v, port_vec;
3596 enum dev_state state;
3597 u32 params[7], val[7];
9a4da2cd 3598 struct fw_caps_config_cmd caps_cmd;
dcf7b6f5 3599 int reset = 1;
b8ff05a9 3600
ae469b68
HS		 3601 /* Grab Firmware Device Log parameters as early as possible so we have
3602 * access to it for debugging, etc.
3603 */
3604 ret = t4_init_devlog_params(adap);
3605 if (ret < 0)
3606 return ret;
3607
666224d4 3608 /* Contact FW, advertising Master capability */
c5a8c0f3
HS		 3609 ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
3610 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
b8ff05a9
DM		 3611 if (ret < 0) {
3612 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3613 ret);
3614 return ret;
3615 }
636f9d37
VP		 3616 if (ret == adap->mbox)
3617 adap->flags |= MASTER_PF;
b8ff05a9 3618
636f9d37
VP		 3619 /*
3620 * If we're the Master PF Driver and the device is uninitialized,
3621 * then let's consider upgrading the firmware ... (We always want
3622 * to check the firmware version number in order to A. get it for
3623 * later reporting and B. to warn if the currently loaded firmware
3624 * is excessively mismatched relative to the driver.)
3625 */
0de72738 3626
760446f9 3627 t4_get_version_info(adap);
a69265e9
HS		 3628 ret = t4_check_fw_version(adap);
3629 /* If firmware is too old (not supported by driver) force an update. */
21d11bd6 3630 if (ret)
a69265e9 3631 state = DEV_STATE_UNINIT;
636f9d37 3632 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
16e47624
HS		 3633 struct fw_info *fw_info;
3634 struct fw_hdr *card_fw;
3635 const struct firmware *fw;
3636 const u8 *fw_data = NULL;
3637 unsigned int fw_size = 0;
3638
3639 /* This is the firmware whose headers the driver was compiled
3640 * against
3641 */
3642 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3643 if (fw_info == NULL) {
3644 dev_err(adap->pdev_dev,
3645 "unable to get firmware info for chip %d.\n",
3646 CHELSIO_CHIP_VERSION(adap->params.chip));
3647 return -EINVAL;
636f9d37 3648 }
16e47624
HS		 3649
3650 /* allocate memory to read the header of the firmware on the
3651 * card
3652 */
752ade68 3653 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
16e47624
HS		 3654
3655 /* Get FW from from /lib/firmware/ */
3656 ret = request_firmware(&fw, fw_info->fw_mod_name,
3657 adap->pdev_dev);
3658 if (ret < 0) {
3659 dev_err(adap->pdev_dev,
3660 "unable to load firmware image %s, error %d\n",
3661 fw_info->fw_mod_name, ret);
3662 } else {
3663 fw_data = fw->data;
3664 fw_size = fw->size;
3665 }
3666
3667 /* upgrade FW logic */
3668 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3669 state, &reset);
3670
3671 /* Cleaning up */
0b5b6bee 3672 release_firmware(fw);
752ade68 3673 kvfree(card_fw);
16e47624 3674
636f9d37 3675 if (ret < 0)
16e47624 3676 goto bye;
636f9d37 3677 }
b8ff05a9 3678
636f9d37
VP		 3679 /*
3680 * Grab VPD parameters. This should be done after we establish a
3681 * connection to the firmware since some of the VPD parameters
3682 * (notably the Core Clock frequency) are retrieved via requests to
3683 * the firmware. On the other hand, we need these fairly early on
3684 * so we do this right after getting ahold of the firmware.
3685 */
098ef6c2 3686 ret = t4_get_vpd_params(adap, &adap->params.vpd);
a0881cab
DM		 3687 if (ret < 0)
3688 goto bye;
a0881cab 3689
636f9d37 3690 /*
13ee15d3
VP		 3691 * Find out what ports are available to us. Note that we need to do
3692 * this before calling adap_init0_no_config() since it needs nports
3693 * and portvec ...
636f9d37
VP		 3694 */
3695 v =
5167865a
HS		 3696 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3697 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
b2612722 3698 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
a0881cab
DM		 3699 if (ret < 0)
3700 goto bye;
3701
636f9d37
VP		 3702 adap->params.nports = hweight32(port_vec);
3703 adap->params.portvec = port_vec;
3704
06640310
HS		 3705 /* If the firmware is initialized already, emit a simply note to that
3706 * effect. Otherwise, it's time to try initializing the adapter.
636f9d37
VP		 3707 */
3708 if (state == DEV_STATE_INIT) {
3709 dev_info(adap->pdev_dev, "Coming up as %s: "\
3710 "Adapter already initialized\n",
3711 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
636f9d37
VP		 3712 } else {
3713 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3714 "Initializing adapter\n");
06640310
HS		 3715
3716 /* Find out whether we're dealing with a version of the
3717 * firmware which has configuration file support.
636f9d37 3718 */
06640310
HS		 3719 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3720 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
b2612722 3721 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
06640310 3722 params, val);
13ee15d3 3723
06640310
HS		 3724 /* If the firmware doesn't support Configuration Files,
3725 * return an error.
3726 */
3727 if (ret < 0) {
3728 dev_err(adap->pdev_dev, "firmware doesn't support "
3729 "Firmware Configuration Files\n");
3730 goto bye;
3731 }
3732
3733 /* The firmware provides us with a memory buffer where we can
3734 * load a Configuration File from the host if we want to
3735 * override the Configuration File in flash.
3736 */
3737 ret = adap_init0_config(adap, reset);
3738 if (ret == -ENOENT) {
3739 dev_err(adap->pdev_dev, "no Configuration File "
3740 "present on adapter.\n");
3741 goto bye;
636f9d37
VP		 3742 }
3743 if (ret < 0) {
06640310
HS		 3744 dev_err(adap->pdev_dev, "could not initialize "
3745 "adapter, error %d\n", -ret);
636f9d37
VP		 3746 goto bye;
3747 }
3748 }
3749
06640310
HS		 3750 /* Give the SGE code a chance to pull in anything that it needs ...
3751 * Note that this must be called after we retrieve our VPD parameters
3752 * in order to know how to convert core ticks to seconds, etc.
636f9d37 3753 */
06640310
HS		 3754 ret = t4_sge_init(adap);
3755 if (ret < 0)
3756 goto bye;
636f9d37 3757
9a4da2cd
VP		 3758 if (is_bypass_device(adap->pdev->device))
3759 adap->params.bypass = 1;
3760
636f9d37
VP		 3761 /*
3762 * Grab some of our basic fundamental operating parameters.
3763 */
3764#define FW_PARAM_DEV(param) \
5167865a
HS		 3765 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3766 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
636f9d37 3767
b8ff05a9 3768#define FW_PARAM_PFVF(param) \
5167865a
HS		 3769 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3770 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3771 FW_PARAMS_PARAM_Y_V(0) | \
3772 FW_PARAMS_PARAM_Z_V(0)
b8ff05a9 3773
636f9d37 3774 params[0] = FW_PARAM_PFVF(EQ_START);
b8ff05a9
DM		 3775 params[1] = FW_PARAM_PFVF(L2T_START);
3776 params[2] = FW_PARAM_PFVF(L2T_END);
3777 params[3] = FW_PARAM_PFVF(FILTER_START);
3778 params[4] = FW_PARAM_PFVF(FILTER_END);
e46dab4d 3779 params[5] = FW_PARAM_PFVF(IQFLINT_START);
b2612722 3780 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
b8ff05a9
DM		 3781 if (ret < 0)
3782 goto bye;
636f9d37
VP		 3783 adap->sge.egr_start = val[0];
3784 adap->l2t_start = val[1];
3785 adap->l2t_end = val[2];
b8ff05a9
DM		 3786 adap->tids.ftid_base = val[3];
3787 adap->tids.nftids = val[4] - val[3] + 1;
e46dab4d 3788 adap->sge.ingr_start = val[5];
b8ff05a9 3789
4b8e27a8
HS		 3790 /* qids (ingress/egress) returned from firmware can be anywhere
3791 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3792 * Hence driver needs to allocate memory for this range to
3793 * store the queue info. Get the highest IQFLINT/EQ index returned
3794 * in FW_EQ_*_CMD.alloc command.
3795 */
3796 params[0] = FW_PARAM_PFVF(EQ_END);
3797 params[1] = FW_PARAM_PFVF(IQFLINT_END);
b2612722 3798 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4b8e27a8
HS		 3799 if (ret < 0)
3800 goto bye;
3801 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3802 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3803
3804 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3805 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3806 if (!adap->sge.egr_map) {
3807 ret = -ENOMEM;
3808 goto bye;
3809 }
3810
3811 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3812 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3813 if (!adap->sge.ingr_map) {
3814 ret = -ENOMEM;
3815 goto bye;
3816 }
3817
3818 /* Allocate the memory for the vaious egress queue bitmaps
5b377d11 3819 * ie starving_fl, txq_maperr and blocked_fl.
4b8e27a8
HS		 3820 */
3821 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3822 sizeof(long), GFP_KERNEL);
3823 if (!adap->sge.starving_fl) {
3824 ret = -ENOMEM;
3825 goto bye;
3826 }
3827
3828 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3829 sizeof(long), GFP_KERNEL);
3830 if (!adap->sge.txq_maperr) {
3831 ret = -ENOMEM;
3832 goto bye;
3833 }
3834
5b377d11
HS		 3835#ifdef CONFIG_DEBUG_FS
3836 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3837 sizeof(long), GFP_KERNEL);
3838 if (!adap->sge.blocked_fl) {
3839 ret = -ENOMEM;
3840 goto bye;
3841 }
3842#endif
3843
b5a02f50
AB		 3844 params[0] = FW_PARAM_PFVF(CLIP_START);
3845 params[1] = FW_PARAM_PFVF(CLIP_END);
b2612722 3846 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
b5a02f50
AB		 3847 if (ret < 0)
3848 goto bye;
3849 adap->clipt_start = val[0];
3850 adap->clipt_end = val[1];
3851
b72a32da
RL		 3852 /* We don't yet have a PARAMs calls to retrieve the number of Traffic
3853 * Classes supported by the hardware/firmware so we hard code it here
3854 * for now.
3855 */
3856 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
3857
636f9d37
VP		 3858 /* query params related to active filter region */
3859 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3860 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
b2612722 3861 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
636f9d37
VP		 3862 /* If Active filter size is set we enable establishing
3863 * offload connection through firmware work request
3864 */
3865 if ((val[0] != val[1]) && (ret >= 0)) {
3866 adap->flags |= FW_OFLD_CONN;
3867 adap->tids.aftid_base = val[0];
3868 adap->tids.aftid_end = val[1];
3869 }
3870
b407a4a9
VP		 3871 /* If we're running on newer firmware, let it know that we're
3872 * prepared to deal with encapsulated CPL messages. Older
3873 * firmware won't understand this and we'll just get
3874 * unencapsulated messages ...
3875 */
3876 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3877 val[0] = 1;
b2612722 3878 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
b407a4a9 3879
1ac0f095
KS		 3880 /*
3881 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3882 * capability. Earlier versions of the firmware didn't have the
3883 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3884 * permission to use ULPTX MEMWRITE DSGL.
3885 */
3886 if (is_t4(adap->params.chip)) {
3887 adap->params.ulptx_memwrite_dsgl = false;
3888 } else {
3889 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
b2612722 3890 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1ac0f095
KS		 3891 1, params, val);
3892 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3893 }
3894
086de575
SW		 3895 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
3896 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
3897 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3898 1, params, val);
3899 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
3900
636f9d37
VP		 3901 /*
3902 * Get device capabilities so we can determine what resources we need
3903 * to manage.
3904 */
3905 memset(&caps_cmd, 0, sizeof(caps_cmd));
e2ac9628
HS		 3906 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3907 FW_CMD_REQUEST_F | FW_CMD_READ_F);
ce91a923 3908 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
636f9d37
VP		 3909 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3910 &caps_cmd);
3911 if (ret < 0)
3912 goto bye;
3913
13ee15d3 3914 if (caps_cmd.ofldcaps) {
b8ff05a9
DM		 3915 /* query offload-related parameters */
3916 params[0] = FW_PARAM_DEV(NTID);
3917 params[1] = FW_PARAM_PFVF(SERVER_START);
3918 params[2] = FW_PARAM_PFVF(SERVER_END);
3919 params[3] = FW_PARAM_PFVF(TDDP_START);
3920 params[4] = FW_PARAM_PFVF(TDDP_END);
3921 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
b2612722 3922 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 3923 params, val);
b8ff05a9
DM		 3924 if (ret < 0)
3925 goto bye;
3926 adap->tids.ntids = val[0];
3927 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3928 adap->tids.stid_base = val[1];
3929 adap->tids.nstids = val[2] - val[1] + 1;
636f9d37 3930 /*
dbedd44e 3931 * Setup server filter region. Divide the available filter
636f9d37
VP		 3932 * region into two parts. Regular filters get 1/3rd and server
3933 * filters get 2/3rd part. This is only enabled if workarond
3934 * path is enabled.
3935 * 1. For regular filters.
3936 * 2. Server filter: This are special filters which are used
3937 * to redirect SYN packets to offload queue.
3938 */
3939 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3940 adap->tids.sftid_base = adap->tids.ftid_base +
3941 DIV_ROUND_UP(adap->tids.nftids, 3);
3942 adap->tids.nsftids = adap->tids.nftids -
3943 DIV_ROUND_UP(adap->tids.nftids, 3);
3944 adap->tids.nftids = adap->tids.sftid_base -
3945 adap->tids.ftid_base;
3946 }
b8ff05a9
DM		 3947 adap->vres.ddp.start = val[3];
3948 adap->vres.ddp.size = val[4] - val[3] + 1;
3949 adap->params.ofldq_wr_cred = val[5];
636f9d37 3950
b8ff05a9 3951 adap->params.offload = 1;
0fbc81b3 3952 adap->num_ofld_uld += 1;
b8ff05a9 3953 }
636f9d37 3954 if (caps_cmd.rdmacaps) {
b8ff05a9
DM		 3955 params[0] = FW_PARAM_PFVF(STAG_START);
3956 params[1] = FW_PARAM_PFVF(STAG_END);
3957 params[2] = FW_PARAM_PFVF(RQ_START);
3958 params[3] = FW_PARAM_PFVF(RQ_END);
3959 params[4] = FW_PARAM_PFVF(PBL_START);
3960 params[5] = FW_PARAM_PFVF(PBL_END);
b2612722 3961 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
636f9d37 3962 params, val);
b8ff05a9
DM		 3963 if (ret < 0)
3964 goto bye;
3965 adap->vres.stag.start = val[0];
3966 adap->vres.stag.size = val[1] - val[0] + 1;
3967 adap->vres.rq.start = val[2];
3968 adap->vres.rq.size = val[3] - val[2] + 1;
3969 adap->vres.pbl.start = val[4];
3970 adap->vres.pbl.size = val[5] - val[4] + 1;
a0881cab
DM		 3971
3972 params[0] = FW_PARAM_PFVF(SQRQ_START);
3973 params[1] = FW_PARAM_PFVF(SQRQ_END);
3974 params[2] = FW_PARAM_PFVF(CQ_START);
3975 params[3] = FW_PARAM_PFVF(CQ_END);
1ae970e0
DM		 3976 params[4] = FW_PARAM_PFVF(OCQ_START);
3977 params[5] = FW_PARAM_PFVF(OCQ_END);
b2612722 3978 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
5c937dd3 3979 val);
a0881cab
DM		 3980 if (ret < 0)
3981 goto bye;
3982 adap->vres.qp.start = val[0];
3983 adap->vres.qp.size = val[1] - val[0] + 1;
3984 adap->vres.cq.start = val[2];
3985 adap->vres.cq.size = val[3] - val[2] + 1;
1ae970e0
DM		 3986 adap->vres.ocq.start = val[4];
3987 adap->vres.ocq.size = val[5] - val[4] + 1;
4c2c5763
HS		 3988
3989 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
3990 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
b2612722 3991 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
5c937dd3 3992 val);
4c2c5763
HS		 3993 if (ret < 0) {
3994 adap->params.max_ordird_qp = 8;
3995 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
3996 ret = 0;
3997 } else {
3998 adap->params.max_ordird_qp = val[0];
3999 adap->params.max_ird_adapter = val[1];
4000 }
4001 dev_info(adap->pdev_dev,
4002 "max_ordird_qp %d max_ird_adapter %d\n",
4003 adap->params.max_ordird_qp,
4004 adap->params.max_ird_adapter);
0fbc81b3 4005 adap->num_ofld_uld += 2;
b8ff05a9 4006 }
636f9d37 4007 if (caps_cmd.iscsicaps) {
b8ff05a9
DM		 4008 params[0] = FW_PARAM_PFVF(ISCSI_START);
4009 params[1] = FW_PARAM_PFVF(ISCSI_END);
b2612722 4010 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
636f9d37 4011 params, val);
b8ff05a9
DM		 4012 if (ret < 0)
4013 goto bye;
4014 adap->vres.iscsi.start = val[0];
4015 adap->vres.iscsi.size = val[1] - val[0] + 1;
0fbc81b3
HS		 4016 /* LIO target and cxgb4i initiaitor */
4017 adap->num_ofld_uld += 2;
b8ff05a9 4018 }
94cdb8bb
HS		 4019 if (caps_cmd.cryptocaps) {
4020 /* Should query params here...TODO */
72a56ca9
HJ		 4021 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
4022 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4023 params, val);
4024 if (ret < 0) {
4025 if (ret != -EINVAL)
4026 goto bye;
4027 } else {
4028 adap->vres.ncrypto_fc = val[0];
4029 }
94cdb8bb
HS		 4030 adap->params.crypto |= ULP_CRYPTO_LOOKASIDE;
4031 adap->num_uld += 1;
4032 }
b8ff05a9
DM		 4033#undef FW_PARAM_PFVF
4034#undef FW_PARAM_DEV
4035
92e7ae71
HS		 4036 /* The MTU/MSS Table is initialized by now, so load their values. If
4037 * we're initializing the adapter, then we'll make any modifications
4038 * we want to the MTU/MSS Table and also initialize the congestion
4039 * parameters.
636f9d37 4040 */
b8ff05a9 4041 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
92e7ae71
HS		 4042 if (state != DEV_STATE_INIT) {
4043 int i;
4044
4045 /* The default MTU Table contains values 1492 and 1500.
4046 * However, for TCP, it's better to have two values which are
4047 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4048 * This allows us to have a TCP Data Payload which is a
4049 * multiple of 8 regardless of what combination of TCP Options
4050 * are in use (always a multiple of 4 bytes) which is
4051 * important for performance reasons. For instance, if no
4052 * options are in use, then we have a 20-byte IP header and a
4053 * 20-byte TCP header. In this case, a 1500-byte MSS would
4054 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4055 * which is not a multiple of 8. So using an MSS of 1488 in
4056 * this case results in a TCP Data Payload of 1448 bytes which
4057 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4058 * Stamps have been negotiated, then an MTU of 1500 bytes
4059 * results in a TCP Data Payload of 1448 bytes which, as
4060 * above, is a multiple of 8 bytes ...
4061 */
4062 for (i = 0; i < NMTUS; i++)
4063 if (adap->params.mtus[i] == 1492) {
4064 adap->params.mtus[i] = 1488;
4065 break;
4066 }
7ee9ff94 4067
92e7ae71
HS		 4068 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4069 adap->params.b_wnd);
4070 }
df64e4d3 4071 t4_init_sge_params(adap);
636f9d37 4072 adap->flags |= FW_OK;
c1e9af0c 4073 t4_init_tp_params(adap);
b8ff05a9
DM		 4074 return 0;
4075
4076 /*
636f9d37
VP		 4077 * Something bad happened. If a command timed out or failed with EIO
4078 * FW does not operate within its spec or something catastrophic
4079 * happened to HW/FW, stop issuing commands.
b8ff05a9 4080 */
636f9d37 4081bye:
4b8e27a8
HS		 4082 kfree(adap->sge.egr_map);
4083 kfree(adap->sge.ingr_map);
4084 kfree(adap->sge.starving_fl);
4085 kfree(adap->sge.txq_maperr);
5b377d11
HS		 4086#ifdef CONFIG_DEBUG_FS
4087 kfree(adap->sge.blocked_fl);
4088#endif
636f9d37
VP		 4089 if (ret != -ETIMEDOUT && ret != -EIO)
4090 t4_fw_bye(adap, adap->mbox);
b8ff05a9
DM		 4091 return ret;
4092}
4093
204dc3c0
DM		 4094/* EEH callbacks */
4095
4096static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4097 pci_channel_state_t state)
4098{
4099 int i;
4100 struct adapter *adap = pci_get_drvdata(pdev);
4101
4102 if (!adap)
4103 goto out;
4104
4105 rtnl_lock();
4106 adap->flags &= ~FW_OK;
4107 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
9fe6cb58 4108 spin_lock(&adap->stats_lock);
204dc3c0
DM		 4109 for_each_port(adap, i) {
4110 struct net_device *dev = adap->port[i];
025d0973
GP		 4111 if (dev) {
4112 netif_device_detach(dev);
4113 netif_carrier_off(dev);
4114 }
204dc3c0 4115 }
9fe6cb58 4116 spin_unlock(&adap->stats_lock);
b37987e8 4117 disable_interrupts(adap);
204dc3c0
DM		 4118 if (adap->flags & FULL_INIT_DONE)
4119 cxgb_down(adap);
4120 rtnl_unlock();
144be3d9
GS		 4121 if ((adap->flags & DEV_ENABLED)) {
4122 pci_disable_device(pdev);
4123 adap->flags &= ~DEV_ENABLED;
4124 }
204dc3c0
DM		 4125out: return state == pci_channel_io_perm_failure ?
4126 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4127}
4128
4129static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4130{
4131 int i, ret;
4132 struct fw_caps_config_cmd c;
4133 struct adapter *adap = pci_get_drvdata(pdev);
4134
4135 if (!adap) {
4136 pci_restore_state(pdev);
4137 pci_save_state(pdev);
4138 return PCI_ERS_RESULT_RECOVERED;
4139 }
4140
144be3d9
GS		 4141 if (!(adap->flags & DEV_ENABLED)) {
4142 if (pci_enable_device(pdev)) {
4143 dev_err(&pdev->dev, "Cannot reenable PCI "
4144 "device after reset\n");
4145 return PCI_ERS_RESULT_DISCONNECT;
4146 }
4147 adap->flags |= DEV_ENABLED;
204dc3c0
DM		 4148 }
4149
4150 pci_set_master(pdev);
4151 pci_restore_state(pdev);
4152 pci_save_state(pdev);
4153 pci_cleanup_aer_uncorrect_error_status(pdev);
4154
8203b509 4155 if (t4_wait_dev_ready(adap->regs) < 0)
204dc3c0 4156 return PCI_ERS_RESULT_DISCONNECT;
b2612722 4157 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
204dc3c0
DM		 4158 return PCI_ERS_RESULT_DISCONNECT;
4159 adap->flags |= FW_OK;
4160 if (adap_init1(adap, &c))
4161 return PCI_ERS_RESULT_DISCONNECT;
4162
4163 for_each_port(adap, i) {
4164 struct port_info *p = adap2pinfo(adap, i);
4165
b2612722 4166 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
060e0c75 4167 NULL, NULL);
204dc3c0
DM		 4168 if (ret < 0)
4169 return PCI_ERS_RESULT_DISCONNECT;
4170 p->viid = ret;
4171 p->xact_addr_filt = -1;
4172 }
4173
4174 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4175 adap->params.b_wnd);
1ae970e0 4176 setup_memwin(adap);
204dc3c0
DM		 4177 if (cxgb_up(adap))
4178 return PCI_ERS_RESULT_DISCONNECT;
4179 return PCI_ERS_RESULT_RECOVERED;
4180}
4181
4182static void eeh_resume(struct pci_dev *pdev)
4183{
4184 int i;
4185 struct adapter *adap = pci_get_drvdata(pdev);
4186
4187 if (!adap)
4188 return;
4189
4190 rtnl_lock();
4191 for_each_port(adap, i) {
4192 struct net_device *dev = adap->port[i];
025d0973
GP		 4193 if (dev) {
4194 if (netif_running(dev)) {
4195 link_start(dev);
4196 cxgb_set_rxmode(dev);
4197 }
4198 netif_device_attach(dev);
204dc3c0 4199 }
204dc3c0
DM		 4200 }
4201 rtnl_unlock();
4202}
4203
3646f0e5 4204static const struct pci_error_handlers cxgb4_eeh = {
204dc3c0
DM		 4205 .error_detected = eeh_err_detected,
4206 .slot_reset = eeh_slot_reset,
4207 .resume = eeh_resume,
4208};
4209
9b86a8d1
HS		 4210/* Return true if the Link Configuration supports "High Speeds" (those greater
4211 * than 1Gb/s).
4212 */
57d8b764 4213static inline bool is_x_10g_port(const struct link_config *lc)
b8ff05a9 4214{
9b86a8d1
HS		 4215 unsigned int speeds, high_speeds;
4216
c3168cab
GG		 4217 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
4218 high_speeds = speeds &
4219 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
9b86a8d1
HS		 4220
4221 return high_speeds != 0;
b8ff05a9
DM		 4222}
4223
b8ff05a9
DM		 4224/*
4225 * Perform default configuration of DMA queues depending on the number and type
4226 * of ports we found and the number of available CPUs. Most settings can be
4227 * modified by the admin prior to actual use.
4228 */
91744948 4229static void cfg_queues(struct adapter *adap)
b8ff05a9
DM		 4230{
4231 struct sge *s = &adap->sge;
ab677ff4 4232 int i = 0, n10g = 0, qidx = 0;
688848b1
AB		 4233#ifndef CONFIG_CHELSIO_T4_DCB
4234 int q10g = 0;
4235#endif
b8ff05a9 4236
94cdb8bb
HS		 4237 /* Reduce memory usage in kdump environment, disable all offload.
4238 */
85eacf3f 4239 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
0fbc81b3 4240 adap->params.offload = 0;
94cdb8bb
HS		 4241 adap->params.crypto = 0;
4242 }
4243
ab677ff4 4244 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
688848b1
AB		 4245#ifdef CONFIG_CHELSIO_T4_DCB
4246 /* For Data Center Bridging support we need to be able to support up
4247 * to 8 Traffic Priorities; each of which will be assigned to its
4248 * own TX Queue in order to prevent Head-Of-Line Blocking.
4249 */
4250 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4251 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4252 MAX_ETH_QSETS, adap->params.nports * 8);
4253 BUG_ON(1);
4254 }
b8ff05a9 4255
688848b1
AB		 4256 for_each_port(adap, i) {
4257 struct port_info *pi = adap2pinfo(adap, i);
4258
4259 pi->first_qset = qidx;
85eacf3f 4260 pi->nqsets = is_kdump_kernel() ? 1 : 8;
688848b1
AB		 4261 qidx += pi->nqsets;
4262 }
4263#else /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4264 /*
4265 * We default to 1 queue per non-10G port and up to # of cores queues
4266 * per 10G port.
4267 */
4268 if (n10g)
4269 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
5952dde7
YM		 4270 if (q10g > netif_get_num_default_rss_queues())
4271 q10g = netif_get_num_default_rss_queues();
b8ff05a9 4272
85eacf3f
GG		 4273 if (is_kdump_kernel())
4274 q10g = 1;
4275
b8ff05a9
DM		 4276 for_each_port(adap, i) {
4277 struct port_info *pi = adap2pinfo(adap, i);
4278
4279 pi->first_qset = qidx;
57d8b764 4280 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
b8ff05a9
DM		 4281 qidx += pi->nqsets;
4282 }
688848b1 4283#endif /* !CONFIG_CHELSIO_T4_DCB */
b8ff05a9
DM		 4284
4285 s->ethqsets = qidx;
4286 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4287
0fbc81b3 4288 if (is_uld(adap)) {
b8ff05a9
DM		 4289 /*
4290 * For offload we use 1 queue/channel if all ports are up to 1G,
4291 * otherwise we divide all available queues amongst the channels
4292 * capped by the number of available cores.
4293 */
4294 if (n10g) {
a56177e1 4295 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
0fbc81b3
HS		 4296 s->ofldqsets = roundup(i, adap->params.nports);
4297 } else {
4298 s->ofldqsets = adap->params.nports;
4299 }
b8ff05a9
DM		 4300 }
4301
4302 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4303 struct sge_eth_rxq *r = &s->ethrxq[i];
4304
c887ad0e 4305 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
b8ff05a9
DM		 4306 r->fl.size = 72;
4307 }
4308
4309 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4310 s->ethtxq[i].q.size = 1024;
4311
4312 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4313 s->ctrlq[i].q.size = 512;
4314
a4569504
AG		 4315 if (!is_t4(adap->params.chip))
4316 s->ptptxq.q.size = 8;
4317
c887ad0e 4318 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
0fbc81b3 4319 init_rspq(adap, &s->intrq, 0, 1, 512, 64);
b8ff05a9
DM		 4320}
4321
4322/*
4323 * Reduce the number of Ethernet queues across all ports to at most n.
4324 * n provides at least one queue per port.
4325 */
91744948 4326static void reduce_ethqs(struct adapter *adap, int n)
b8ff05a9
DM		 4327{
4328 int i;
4329 struct port_info *pi;
4330
4331 while (n < adap->sge.ethqsets)
4332 for_each_port(adap, i) {
4333 pi = adap2pinfo(adap, i);
4334 if (pi->nqsets > 1) {
4335 pi->nqsets--;
4336 adap->sge.ethqsets--;
4337 if (adap->sge.ethqsets <= n)
4338 break;
4339 }
4340 }
4341
4342 n = 0;
4343 for_each_port(adap, i) {
4344 pi = adap2pinfo(adap, i);
4345 pi->first_qset = n;
4346 n += pi->nqsets;
4347 }
4348}
4349
94cdb8bb
HS		 4350static int get_msix_info(struct adapter *adap)
4351{
4352 struct uld_msix_info *msix_info;
0fbc81b3
HS		 4353 unsigned int max_ingq = 0;
4354
4355 if (is_offload(adap))
4356 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
4357 if (is_pci_uld(adap))
4358 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
4359
4360 if (!max_ingq)
4361 goto out;
94cdb8bb
HS		 4362
4363 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
4364 if (!msix_info)
4365 return -ENOMEM;
4366
4367 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
4368 sizeof(long), GFP_KERNEL);
4369 if (!adap->msix_bmap_ulds.msix_bmap) {
4370 kfree(msix_info);
4371 return -ENOMEM;
4372 }
4373 spin_lock_init(&adap->msix_bmap_ulds.lock);
4374 adap->msix_info_ulds = msix_info;
0fbc81b3 4375out:
94cdb8bb
HS		 4376 return 0;
4377}
4378
4379static void free_msix_info(struct adapter *adap)
4380{
0fbc81b3 4381 if (!(adap->num_uld && adap->num_ofld_uld))
94cdb8bb
HS		 4382 return;
4383
4384 kfree(adap->msix_info_ulds);
4385 kfree(adap->msix_bmap_ulds.msix_bmap);
4386}
4387
b8ff05a9
DM		 4388/* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4389#define EXTRA_VECS 2
4390
91744948 4391static int enable_msix(struct adapter *adap)
b8ff05a9 4392{
94cdb8bb
HS		 4393 int ofld_need = 0, uld_need = 0;
4394 int i, j, want, need, allocated;
b8ff05a9
DM		 4395 struct sge *s = &adap->sge;
4396 unsigned int nchan = adap->params.nports;
f36e58e5 4397 struct msix_entry *entries;
94cdb8bb 4398 int max_ingq = MAX_INGQ;
f36e58e5 4399
0fbc81b3
HS		 4400 if (is_pci_uld(adap))
4401 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
4402 if (is_offload(adap))
4403 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
94cdb8bb 4404 entries = kmalloc(sizeof(*entries) * (max_ingq + 1),
f36e58e5
HS		 4405 GFP_KERNEL);
4406 if (!entries)
4407 return -ENOMEM;
b8ff05a9 4408
94cdb8bb 4409 /* map for msix */
0fbc81b3
HS		 4410 if (get_msix_info(adap)) {
4411 adap->params.offload = 0;
94cdb8bb 4412 adap->params.crypto = 0;
0fbc81b3 4413 }
94cdb8bb
HS		 4414
4415 for (i = 0; i < max_ingq + 1; ++i)
b8ff05a9
DM		 4416 entries[i].entry = i;
4417
4418 want = s->max_ethqsets + EXTRA_VECS;
4419 if (is_offload(adap)) {
0fbc81b3
HS		 4420 want += adap->num_ofld_uld * s->ofldqsets;
4421 ofld_need = adap->num_ofld_uld * nchan;
b8ff05a9 4422 }
94cdb8bb 4423 if (is_pci_uld(adap)) {
0fbc81b3
HS		 4424 want += adap->num_uld * s->ofldqsets;
4425 uld_need = adap->num_uld * nchan;
94cdb8bb 4426 }
688848b1
AB		 4427#ifdef CONFIG_CHELSIO_T4_DCB
4428 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4429 * each port.
4430 */
94cdb8bb 4431 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
688848b1 4432#else
94cdb8bb 4433 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
688848b1 4434#endif
f36e58e5
HS		 4435 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4436 if (allocated < 0) {
4437 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4438 " not using MSI-X\n");
4439 kfree(entries);
4440 return allocated;
4441 }
b8ff05a9 4442
f36e58e5 4443 /* Distribute available vectors to the various queue groups.
c32ad224
AG		 4444 * Every group gets its minimum requirement and NIC gets top
4445 * priority for leftovers.
4446 */
94cdb8bb 4447 i = allocated - EXTRA_VECS - ofld_need - uld_need;
c32ad224
AG		 4448 if (i < s->max_ethqsets) {
4449 s->max_ethqsets = i;
4450 if (i < s->ethqsets)
4451 reduce_ethqs(adap, i);
4452 }
0fbc81b3 4453 if (is_uld(adap)) {
94cdb8bb
HS		 4454 if (allocated < want)
4455 s->nqs_per_uld = nchan;
4456 else
0fbc81b3 4457 s->nqs_per_uld = s->ofldqsets;
94cdb8bb
HS		 4458 }
4459
0fbc81b3 4460 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
c32ad224 4461 adap->msix_info[i].vec = entries[i].vector;
0fbc81b3
HS		 4462 if (is_uld(adap)) {
4463 for (j = 0 ; i < allocated; ++i, j++) {
94cdb8bb 4464 adap->msix_info_ulds[j].vec = entries[i].vector;
0fbc81b3
HS		 4465 adap->msix_info_ulds[j].idx = i;
4466 }
94cdb8bb
HS		 4467 adap->msix_bmap_ulds.mapsize = j;
4468 }
43eb4e82 4469 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
0fbc81b3
HS		 4470 "nic %d per uld %d\n",
4471 allocated, s->max_ethqsets, s->nqs_per_uld);
c32ad224 4472
f36e58e5 4473 kfree(entries);
c32ad224 4474 return 0;
b8ff05a9
DM		 4475}
4476
4477#undef EXTRA_VECS
4478
91744948 4479static int init_rss(struct adapter *adap)
671b0060 4480{
c035e183
HS		 4481 unsigned int i;
4482 int err;
4483
4484 err = t4_init_rss_mode(adap, adap->mbox);
4485 if (err)
4486 return err;
671b0060
DM		 4487
4488 for_each_port(adap, i) {
4489 struct port_info *pi = adap2pinfo(adap, i);
4490
4491 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4492 if (!pi->rss)
4493 return -ENOMEM;
671b0060
DM		 4494 }
4495 return 0;
4496}
4497
547fd272
HS		 4498static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,
4499 enum pci_bus_speed *speed,
4500 enum pcie_link_width *width)
4501{
4502 u32 lnkcap1, lnkcap2;
4503 int err1, err2;
4504
4505#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
4506
4507 *speed = PCI_SPEED_UNKNOWN;
4508 *width = PCIE_LNK_WIDTH_UNKNOWN;
4509
4510 err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,
4511 &lnkcap1);
4512 err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,
4513 &lnkcap2);
4514 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
4515 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
4516 *speed = PCIE_SPEED_8_0GT;
4517 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
4518 *speed = PCIE_SPEED_5_0GT;
4519 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
4520 *speed = PCIE_SPEED_2_5GT;
4521 }
4522 if (!err1) {
4523 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
4524 if (!lnkcap2) { /* pre-r3.0 */
4525 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
4526 *speed = PCIE_SPEED_5_0GT;
4527 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
4528 *speed = PCIE_SPEED_2_5GT;
4529 }
4530 }
4531
4532 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
4533 return err1 ? err1 : err2 ? err2 : -EINVAL;
4534 return 0;
4535}
4536
4537static void cxgb4_check_pcie_caps(struct adapter *adap)
4538{
4539 enum pcie_link_width width, width_cap;
4540 enum pci_bus_speed speed, speed_cap;
4541
4542#define PCIE_SPEED_STR(speed) \
4543 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
4544 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
4545 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
4546 "Unknown")
4547
4548 if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {
4549 dev_warn(adap->pdev_dev,
4550 "Unable to determine PCIe device BW capabilities\n");
4551 return;
4552 }
4553
4554 if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||
4555 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
4556 dev_warn(adap->pdev_dev,
4557 "Unable to determine PCI Express bandwidth.\n");
4558 return;
4559 }
4560
4561 dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",
4562 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
4563 dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",
4564 width, width_cap);
4565 if (speed < speed_cap || width < width_cap)
4566 dev_info(adap->pdev_dev,
4567 "A slot with more lanes and/or higher speed is "
4568 "suggested for optimal performance.\n");
4569}
4570
0de72738
HS		 4571/* Dump basic information about the adapter */
4572static void print_adapter_info(struct adapter *adapter)
4573{
760446f9
GG		 4574 /* Hardware/Firmware/etc. Version/Revision IDs */
4575 t4_dump_version_info(adapter);
0de72738
HS		 4576
4577 /* Software/Hardware configuration */
4578 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
4579 is_offload(adapter) ? "R" : "",
4580 ((adapter->flags & USING_MSIX) ? "MSI-X" :
4581 (adapter->flags & USING_MSI) ? "MSI" : ""),
4582 is_offload(adapter) ? "Offload" : "non-Offload");
4583}
4584
91744948 4585static void print_port_info(const struct net_device *dev)
b8ff05a9 4586{
b8ff05a9 4587 char buf[80];
118969ed 4588 char *bufp = buf;
f1a051b9 4589 const char *spd = "";
118969ed
DM		 4590 const struct port_info *pi = netdev_priv(dev);
4591 const struct adapter *adap = pi->adapter;
f1a051b9
DM		 4592
4593 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4594 spd = " 2.5 GT/s";
4595 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4596 spd = " 5 GT/s";
d2e752db
RD		 4597 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4598 spd = " 8 GT/s";
b8ff05a9 4599
c3168cab 4600 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5e78f7fd 4601 bufp += sprintf(bufp, "100M/");
c3168cab 4602 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5e78f7fd 4603 bufp += sprintf(bufp, "1G/");
c3168cab 4604 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
118969ed 4605 bufp += sprintf(bufp, "10G/");
c3168cab 4606 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
9b86a8d1 4607 bufp += sprintf(bufp, "25G/");
c3168cab 4608 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
72aca4bf 4609 bufp += sprintf(bufp, "40G/");
c3168cab
GG		 4610 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
4611 bufp += sprintf(bufp, "50G/");
4612 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
9b86a8d1 4613 bufp += sprintf(bufp, "100G/");
c3168cab
GG		 4614 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
4615 bufp += sprintf(bufp, "200G/");
4616 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
4617 bufp += sprintf(bufp, "400G/");
118969ed
DM		 4618 if (bufp != buf)
4619 --bufp;
72aca4bf 4620 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
118969ed 4621
0de72738
HS		 4622 netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
4623 dev->name, adap->params.vpd.id, adap->name, buf);
b8ff05a9
DM		 4624}
4625
06546391
DM		 4626/*
4627 * Free the following resources:
4628 * - memory used for tables
4629 * - MSI/MSI-X
4630 * - net devices
4631 * - resources FW is holding for us
4632 */
4633static void free_some_resources(struct adapter *adapter)
4634{
4635 unsigned int i;
4636
752ade68 4637 kvfree(adapter->l2t);
b72a32da 4638 t4_cleanup_sched(adapter);
752ade68 4639 kvfree(adapter->tids.tid_tab);
e0f911c8 4640 cxgb4_cleanup_tc_flower(adapter);
d8931847 4641 cxgb4_cleanup_tc_u32(adapter);
4b8e27a8
HS		 4642 kfree(adapter->sge.egr_map);
4643 kfree(adapter->sge.ingr_map);
4644 kfree(adapter->sge.starving_fl);
4645 kfree(adapter->sge.txq_maperr);
5b377d11
HS		 4646#ifdef CONFIG_DEBUG_FS
4647 kfree(adapter->sge.blocked_fl);
4648#endif
06546391
DM		 4649 disable_msi(adapter);
4650
4651 for_each_port(adapter, i)
671b0060 4652 if (adapter->port[i]) {
4f3a0fcf
HS		 4653 struct port_info *pi = adap2pinfo(adapter, i);
4654
4655 if (pi->viid != 0)
4656 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4657 0, pi->viid);
671b0060 4658 kfree(adap2pinfo(adapter, i)->rss);
06546391 4659 free_netdev(adapter->port[i]);
671b0060 4660 }
06546391 4661 if (adapter->flags & FW_OK)
b2612722 4662 t4_fw_bye(adapter, adapter->pf);
06546391
DM		 4663}
4664
2ed28baa 4665#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
35d35682 4666#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
b8ff05a9 4667 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
22adfe0a 4668#define SEGMENT_SIZE 128
b8ff05a9 4669
d86bd29e
HS		 4670static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4671{
d86bd29e
HS		 4672 u16 device_id;
4673
4674 /* Retrieve adapter's device ID */
4675 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
46cdc9be 4676
4677 switch (device_id >> 12) {
d86bd29e 4678 case CHELSIO_T4:
46cdc9be 4679 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
d86bd29e 4680 case CHELSIO_T5:
46cdc9be 4681 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
d86bd29e 4682 case CHELSIO_T6:
46cdc9be 4683 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
d86bd29e
HS		 4684 default:
4685 dev_err(&pdev->dev, "Device %d is not supported\n",
4686 device_id);
d86bd29e 4687 }
46cdc9be 4688 return -EINVAL;
d86bd29e
HS		 4689}
4690
b6244201 4691#ifdef CONFIG_PCI_IOV
e7b48a32
HS		 4692static void dummy_setup(struct net_device *dev)
4693{
4694 dev->type = ARPHRD_NONE;
4695 dev->mtu = 0;
4696 dev->hard_header_len = 0;
4697 dev->addr_len = 0;
4698 dev->tx_queue_len = 0;
4699 dev->flags |= IFF_NOARP;
4700 dev->priv_flags |= IFF_NO_QUEUE;
4701
4702 /* Initialize the device structure. */
4703 dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
4704 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
cf124db5 4705 dev->needs_free_netdev = true;
e7b48a32
HS		 4706}
4707
4708static int config_mgmt_dev(struct pci_dev *pdev)
4709{
4710 struct adapter *adap = pci_get_drvdata(pdev);
4711 struct net_device *netdev;
4712 struct port_info *pi;
4713 char name[IFNAMSIZ];
4714 int err;
4715
4716 snprintf(name, IFNAMSIZ, "mgmtpf%d%d", adap->adap_idx, adap->pf);
038c35a8
GG		 4717 netdev = alloc_netdev(sizeof(struct port_info), name, NET_NAME_UNKNOWN,
4718 dummy_setup);
e7b48a32
HS		 4719 if (!netdev)
4720 return -ENOMEM;
4721
4722 pi = netdev_priv(netdev);
4723 pi->adapter = adap;
c3168cab 4724 pi->tx_chan = adap->pf % adap->params.nports;
e7b48a32
HS		 4725 SET_NETDEV_DEV(netdev, &pdev->dev);
4726
4727 adap->port[0] = netdev;
c3168cab 4728 pi->port_id = 0;
e7b48a32
HS		 4729
4730 err = register_netdev(adap->port[0]);
4731 if (err) {
4732 pr_info("Unable to register VF mgmt netdev %s\n", name);
4733 free_netdev(adap->port[0]);
4734 adap->port[0] = NULL;
4735 return err;
4736 }
4737 return 0;
4738}
4739
b6244201
HS		 4740static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
4741{
7829451c 4742 struct adapter *adap = pci_get_drvdata(pdev);
b6244201
HS		 4743 int err = 0;
4744 int current_vfs = pci_num_vf(pdev);
4745 u32 pcie_fw;
b6244201 4746
7829451c 4747 pcie_fw = readl(adap->regs + PCIE_FW_A);
b6244201
HS		 4748 /* Check if cxgb4 is the MASTER and fw is initialized */
4749 if (!(pcie_fw & PCIE_FW_INIT_F) ||
4750 !(pcie_fw & PCIE_FW_MASTER_VLD_F) ||
4751 PCIE_FW_MASTER_G(pcie_fw) != 4) {
4752 dev_warn(&pdev->dev,
4753 "cxgb4 driver needs to be MASTER to support SRIOV\n");
4754 return -EOPNOTSUPP;
4755 }
4756
4757 /* If any of the VF's is already assigned to Guest OS, then
4758 * SRIOV for the same cannot be modified
4759 */
4760 if (current_vfs && pci_vfs_assigned(pdev)) {
4761 dev_err(&pdev->dev,
4762 "Cannot modify SR-IOV while VFs are assigned\n");
4763 num_vfs = current_vfs;
4764 return num_vfs;
4765 }
4766
4767 /* Disable SRIOV when zero is passed.
4768 * One needs to disable SRIOV before modifying it, else
4769 * stack throws the below warning:
4770 * " 'n' VFs already enabled. Disable before enabling 'm' VFs."
4771 */
4772 if (!num_vfs) {
4773 pci_disable_sriov(pdev);
e7b48a32 4774 if (adap->port[0]) {
7829451c 4775 unregister_netdev(adap->port[0]);
e7b48a32
HS		 4776 adap->port[0] = NULL;
4777 }
661dbeb9
HS		 4778 /* free VF resources */
4779 kfree(adap->vfinfo);
4780 adap->vfinfo = NULL;
4781 adap->num_vfs = 0;
b6244201
HS		 4782 return num_vfs;
4783 }
4784
4785 if (num_vfs != current_vfs) {
4786 err = pci_enable_sriov(pdev, num_vfs);
4787 if (err)
4788 return err;
7829451c 4789
661dbeb9 4790 adap->num_vfs = num_vfs;
e7b48a32
HS		 4791 err = config_mgmt_dev(pdev);
4792 if (err)
4793 return err;
b6244201 4794 }
661dbeb9
HS		 4795
4796 adap->vfinfo = kcalloc(adap->num_vfs,
4797 sizeof(struct vf_info), GFP_KERNEL);
4798 if (adap->vfinfo)
4799 fill_vf_station_mac_addr(adap);
b6244201
HS		 4800 return num_vfs;
4801}
4802#endif
4803
1dd06ae8 4804static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
b8ff05a9 4805{
22adfe0a 4806 int func, i, err, s_qpp, qpp, num_seg;
b8ff05a9 4807 struct port_info *pi;
c8f44aff 4808 bool highdma = false;
b8ff05a9 4809 struct adapter *adapter = NULL;
7829451c 4810 struct net_device *netdev;
d6ce2628 4811 void __iomem *regs;
d86bd29e
HS		 4812 u32 whoami, pl_rev;
4813 enum chip_type chip;
7829451c 4814 static int adap_idx = 1;
0a327889 4815#ifdef CONFIG_PCI_IOV
96fe11f2 4816 u32 v, port_vec;
0a327889 4817#endif
b8ff05a9
DM		 4818
4819 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4820
4821 err = pci_request_regions(pdev, KBUILD_MODNAME);
4822 if (err) {
4823 /* Just info, some other driver may have claimed the device. */
4824 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4825 return err;
4826 }
4827
b8ff05a9
DM		 4828 err = pci_enable_device(pdev);
4829 if (err) {
4830 dev_err(&pdev->dev, "cannot enable PCI device\n");
4831 goto out_release_regions;
4832 }
4833
d6ce2628
HS		 4834 regs = pci_ioremap_bar(pdev, 0);
4835 if (!regs) {
4836 dev_err(&pdev->dev, "cannot map device registers\n");
4837 err = -ENOMEM;
4838 goto out_disable_device;
4839 }
4840
8203b509
HS		 4841 err = t4_wait_dev_ready(regs);
4842 if (err < 0)
4843 goto out_unmap_bar0;
4844
d6ce2628 4845 /* We control everything through one PF */
d86bd29e
HS		 4846 whoami = readl(regs + PL_WHOAMI_A);
4847 pl_rev = REV_G(readl(regs + PL_REV_A));
4848 chip = get_chip_type(pdev, pl_rev);
4849 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4850 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
d6ce2628 4851 if (func != ent->driver_data) {
7829451c 4852#ifndef CONFIG_PCI_IOV
d6ce2628 4853 iounmap(regs);
7829451c 4854#endif
d6ce2628
HS		 4855 pci_disable_device(pdev);
4856 pci_save_state(pdev); /* to restore SR-IOV later */
4857 goto sriov;
4858 }
4859
b8ff05a9 4860 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
c8f44aff 4861 highdma = true;
b8ff05a9
DM		 4862 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4863 if (err) {
4864 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4865 "coherent allocations\n");
d6ce2628 4866 goto out_unmap_bar0;
b8ff05a9
DM		 4867 }
4868 } else {
4869 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4870 if (err) {
4871 dev_err(&pdev->dev, "no usable DMA configuration\n");
d6ce2628 4872 goto out_unmap_bar0;
b8ff05a9
DM		 4873 }
4874 }
4875
4876 pci_enable_pcie_error_reporting(pdev);
4877 pci_set_master(pdev);
4878 pci_save_state(pdev);
4879
4880 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4881 if (!adapter) {
4882 err = -ENOMEM;
d6ce2628 4883 goto out_unmap_bar0;
b8ff05a9 4884 }
7829451c 4885 adap_idx++;
b8ff05a9 4886
29aaee65
AB		 4887 adapter->workq = create_singlethread_workqueue("cxgb4");
4888 if (!adapter->workq) {
4889 err = -ENOMEM;
4890 goto out_free_adapter;
4891 }
4892
7f080c3f
HS		 4893 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
4894 (sizeof(struct mbox_cmd) *
4895 T4_OS_LOG_MBOX_CMDS),
4896 GFP_KERNEL);
4897 if (!adapter->mbox_log) {
4898 err = -ENOMEM;
4899 goto out_free_adapter;
4900 }
4901 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
4902
144be3d9
GS		 4903 /* PCI device has been enabled */
4904 adapter->flags |= DEV_ENABLED;
4905
d6ce2628 4906 adapter->regs = regs;
b8ff05a9
DM		 4907 adapter->pdev = pdev;
4908 adapter->pdev_dev = &pdev->dev;
0de72738 4909 adapter->name = pci_name(pdev);
3069ee9b 4910 adapter->mbox = func;
b2612722 4911 adapter->pf = func;
ea1e76f7 4912 adapter->msg_enable = DFLT_MSG_ENABLE;
b8ff05a9
DM		 4913 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4914
b0ba9d5f
CL		 4915 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
4916 * Ingress Packet Data to Free List Buffers in order to allow for
4917 * chipset performance optimizations between the Root Complex and
4918 * Memory Controllers. (Messages to the associated Ingress Queue
4919 * notifying new Packet Placement in the Free Lists Buffers will be
4920 * send without the Relaxed Ordering Attribute thus guaranteeing that
4921 * all preceding PCIe Transaction Layer Packets will be processed
4922 * first.) But some Root Complexes have various issues with Upstream
4923 * Transaction Layer Packets with the Relaxed Ordering Attribute set.
4924 * The PCIe devices which under the Root Complexes will be cleared the
4925 * Relaxed Ordering bit in the configuration space, So we check our
4926 * PCIe configuration space to see if it's flagged with advice against
4927 * using Relaxed Ordering.
4928 */
4929 if (!pcie_relaxed_ordering_enabled(pdev))
4930 adapter->flags |= ROOT_NO_RELAXED_ORDERING;
4931
b8ff05a9
DM		 4932 spin_lock_init(&adapter->stats_lock);
4933 spin_lock_init(&adapter->tid_release_lock);
e327c225 4934 spin_lock_init(&adapter->win0_lock);
4055ae5e
HS		 4935 spin_lock_init(&adapter->mbox_lock);
4936
4937 INIT_LIST_HEAD(&adapter->mlist.list);
b8ff05a9
DM		 4938
4939 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
881806bc
VP		 4940 INIT_WORK(&adapter->db_full_task, process_db_full);
4941 INIT_WORK(&adapter->db_drop_task, process_db_drop);
b8ff05a9
DM		 4942
4943 err = t4_prep_adapter(adapter);
4944 if (err)
d6ce2628
HS		 4945 goto out_free_adapter;
4946
22adfe0a 4947
d14807dd 4948 if (!is_t4(adapter->params.chip)) {
f612b815
HS		 4949 s_qpp = (QUEUESPERPAGEPF0_S +
4950 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
b2612722 4951 adapter->pf);
f612b815
HS		 4952 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4953 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
22adfe0a
SR		 4954 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4955
4956 /* Each segment size is 128B. Write coalescing is enabled only
4957 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4958 * queue is less no of segments that can be accommodated in
4959 * a page size.
4960 */
4961 if (qpp > num_seg) {
4962 dev_err(&pdev->dev,
4963 "Incorrect number of egress queues per page\n");
4964 err = -EINVAL;
d6ce2628 4965 goto out_free_adapter;
22adfe0a
SR		 4966 }
4967 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4968 pci_resource_len(pdev, 2));
4969 if (!adapter->bar2) {
4970 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4971 err = -ENOMEM;
d6ce2628 4972 goto out_free_adapter;
22adfe0a
SR		 4973 }
4974 }
4975
636f9d37 4976 setup_memwin(adapter);
b8ff05a9 4977 err = adap_init0(adapter);
5b377d11
HS		 4978#ifdef CONFIG_DEBUG_FS
4979 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4980#endif
636f9d37 4981 setup_memwin_rdma(adapter);
b8ff05a9
DM		 4982 if (err)
4983 goto out_unmap_bar;
4984
2a485cf7
HS		 4985 /* configure SGE_STAT_CFG_A to read WC stats */
4986 if (!is_t4(adapter->params.chip))
676d6a75
HS		 4987 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
4988 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
4989 T6_STATMODE_V(0)));
2a485cf7 4990
b8ff05a9 4991 for_each_port(adapter, i) {
b8ff05a9
DM		 4992 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4993 MAX_ETH_QSETS);
4994 if (!netdev) {
4995 err = -ENOMEM;
4996 goto out_free_dev;
4997 }
4998
4999 SET_NETDEV_DEV(netdev, &pdev->dev);
5000
5001 adapter->port[i] = netdev;
5002 pi = netdev_priv(netdev);
5003 pi->adapter = adapter;
5004 pi->xact_addr_filt = -1;
b8ff05a9 5005 pi->port_id = i;
b8ff05a9
DM		 5006 netdev->irq = pdev->irq;
5007
2ed28baa
MM		 5008 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5009 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5010 NETIF_F_RXCSUM | NETIF_F_RXHASH |
d8931847
RL		 5011 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
5012 NETIF_F_HW_TC;
c8f44aff
MM		 5013 if (highdma)
5014 netdev->hw_features |= NETIF_F_HIGHDMA;
5015 netdev->features |= netdev->hw_features;
b8ff05a9
DM		 5016 netdev->vlan_features = netdev->features & VLAN_FEAT;
5017
01789349
JP		 5018 netdev->priv_flags |= IFF_UNICAST_FLT;
5019
d894be57
JW		 5020 /* MTU range: 81 - 9600 */
5021 netdev->min_mtu = 81;
5022 netdev->max_mtu = MAX_MTU;
5023
b8ff05a9 5024 netdev->netdev_ops = &cxgb4_netdev_ops;
688848b1
AB		 5025#ifdef CONFIG_CHELSIO_T4_DCB
5026 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5027 cxgb4_dcb_state_init(netdev);
5028#endif
812034f1 5029 cxgb4_set_ethtool_ops(netdev);
b8ff05a9
DM		 5030 }
5031
5032 pci_set_drvdata(pdev, adapter);
5033
5034 if (adapter->flags & FW_OK) {
060e0c75 5035 err = t4_port_init(adapter, func, func, 0);
b8ff05a9
DM		 5036 if (err)
5037 goto out_free_dev;
098ef6c2
HS		 5038 } else if (adapter->params.nports == 1) {
5039 /* If we don't have a connection to the firmware -- possibly
5040 * because of an error -- grab the raw VPD parameters so we
5041 * can set the proper MAC Address on the debug network
5042 * interface that we've created.
5043 */
5044 u8 hw_addr[ETH_ALEN];
5045 u8 *na = adapter->params.vpd.na;
5046
5047 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5048 if (!err) {
5049 for (i = 0; i < ETH_ALEN; i++)
5050 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5051 hex2val(na[2 * i + 1]));
5052 t4_set_hw_addr(adapter, 0, hw_addr);
5053 }
b8ff05a9
DM		 5054 }
5055
098ef6c2 5056 /* Configure queues and allocate tables now, they can be needed as
b8ff05a9
DM		 5057 * soon as the first register_netdev completes.
5058 */
5059 cfg_queues(adapter);
5060
5be9ed8d 5061 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
b8ff05a9
DM		 5062 if (!adapter->l2t) {
5063 /* We tolerate a lack of L2T, giving up some functionality */
5064 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5065 adapter->params.offload = 0;
5066 }
5067
b5a02f50 5068#if IS_ENABLED(CONFIG_IPV6)
eb72f74f
HS		 5069 if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
5070 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5071 /* CLIP functionality is not present in hardware,
5072 * hence disable all offload features
b5a02f50
AB		 5073 */
5074 dev_warn(&pdev->dev,
eb72f74f 5075 "CLIP not enabled in hardware, continuing\n");
b5a02f50 5076 adapter->params.offload = 0;
eb72f74f
HS		 5077 } else {
5078 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5079 adapter->clipt_end);
5080 if (!adapter->clipt) {
5081 /* We tolerate a lack of clip_table, giving up
5082 * some functionality
5083 */
5084 dev_warn(&pdev->dev,
5085 "could not allocate Clip table, continuing\n");
5086 adapter->params.offload = 0;
5087 }
b5a02f50
AB		 5088 }
5089#endif
b72a32da
RL		 5090
5091 for_each_port(adapter, i) {
5092 pi = adap2pinfo(adapter, i);
5093 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5094 if (!pi->sched_tbl)
5095 dev_warn(&pdev->dev,
5096 "could not activate scheduling on port %d\n",
5097 i);
5098 }
5099
578b46b9 5100 if (tid_init(&adapter->tids) < 0) {
b8ff05a9
DM		 5101 dev_warn(&pdev->dev, "could not allocate TID table, "
5102 "continuing\n");
5103 adapter->params.offload = 0;
d8931847 5104 } else {
45da1ca2 5105 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
d8931847
RL		 5106 if (!adapter->tc_u32)
5107 dev_warn(&pdev->dev,
5108 "could not offload tc u32, continuing\n");
62488e4b
KS		 5109
5110 cxgb4_init_tc_flower(adapter);
b8ff05a9
DM		 5111 }
5112
9a1bb9f6
HS		 5113 if (is_offload(adapter)) {
5114 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5115 u32 hash_base, hash_reg;
5116
5117 if (chip <= CHELSIO_T5) {
5118 hash_reg = LE_DB_TID_HASHBASE_A;
5119 hash_base = t4_read_reg(adapter, hash_reg);
5120 adapter->tids.hash_base = hash_base / 4;
5121 } else {
5122 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5123 hash_base = t4_read_reg(adapter, hash_reg);
5124 adapter->tids.hash_base = hash_base;
5125 }
5126 }
5127 }
5128
f7cabcdd
DM		 5129 /* See what interrupts we'll be using */
5130 if (msi > 1 && enable_msix(adapter) == 0)
5131 adapter->flags |= USING_MSIX;
94cdb8bb 5132 else if (msi > 0 && pci_enable_msi(pdev) == 0) {
f7cabcdd 5133 adapter->flags |= USING_MSI;
94cdb8bb
HS		 5134 if (msi > 1)
5135 free_msix_info(adapter);
5136 }
f7cabcdd 5137
547fd272
HS		 5138 /* check for PCI Express bandwidth capabiltites */
5139 cxgb4_check_pcie_caps(adapter);
5140
671b0060
DM		 5141 err = init_rss(adapter);
5142 if (err)
5143 goto out_free_dev;
5144
b8ff05a9
DM		 5145 /*
5146 * The card is now ready to go. If any errors occur during device
5147 * registration we do not fail the whole card but rather proceed only
5148 * with the ports we manage to register successfully. However we must
5149 * register at least one net device.
5150 */
5151 for_each_port(adapter, i) {
a57cabe0 5152 pi = adap2pinfo(adapter, i);
d2a007ab 5153 adapter->port[i]->dev_port = pi->lport;
a57cabe0
DM		 5154 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5155 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5156
b1a73af9
SM		 5157 netif_carrier_off(adapter->port[i]);
5158
b8ff05a9
DM		 5159 err = register_netdev(adapter->port[i]);
5160 if (err)
b1a3c2b6 5161 break;
b1a3c2b6
DM		 5162 adapter->chan_map[pi->tx_chan] = i;
5163 print_port_info(adapter->port[i]);
b8ff05a9 5164 }
b1a3c2b6 5165 if (i == 0) {
b8ff05a9
DM		 5166 dev_err(&pdev->dev, "could not register any net devices\n");
5167 goto out_free_dev;
5168 }
b1a3c2b6
DM		 5169 if (err) {
5170 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5171 err = 0;
6403eab1 5172 }
b8ff05a9
DM		 5173
5174 if (cxgb4_debugfs_root) {
5175 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5176 cxgb4_debugfs_root);
5177 setup_debugfs(adapter);
5178 }
5179
6482aa7c
DLR		 5180 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5181 pdev->needs_freset = 1;
5182
0fbc81b3
HS		 5183 if (is_uld(adapter)) {
5184 mutex_lock(&uld_mutex);
5185 list_add_tail(&adapter->list_node, &adapter_list);
5186 mutex_unlock(&uld_mutex);
5187 }
b8ff05a9 5188
9c33e420
AG		 5189 if (!is_t4(adapter->params.chip))
5190 cxgb4_ptp_init(adapter);
5191
0de72738 5192 print_adapter_info(adapter);
0fbc81b3 5193 setup_fw_sge_queues(adapter);
7829451c 5194 return 0;
0de72738 5195
8e1e6059 5196sriov:
b8ff05a9 5197#ifdef CONFIG_PCI_IOV
7829451c
HS		 5198 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5199 if (!adapter) {
5200 err = -ENOMEM;
5201 goto free_pci_region;
5202 }
5203
7829451c
HS		 5204 adapter->pdev = pdev;
5205 adapter->pdev_dev = &pdev->dev;
5206 adapter->name = pci_name(pdev);
5207 adapter->mbox = func;
5208 adapter->pf = func;
5209 adapter->regs = regs;
e7b48a32 5210 adapter->adap_idx = adap_idx;
7829451c
HS		 5211 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5212 (sizeof(struct mbox_cmd) *
5213 T4_OS_LOG_MBOX_CMDS),
5214 GFP_KERNEL);
5215 if (!adapter->mbox_log) {
5216 err = -ENOMEM;
e7b48a32 5217 goto free_adapter;
7829451c 5218 }
038c35a8
GG		 5219 spin_lock_init(&adapter->mbox_lock);
5220 INIT_LIST_HEAD(&adapter->mlist.list);
96fe11f2
GG		 5221
5222 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5223 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
5224 err = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 1,
5225 &v, &port_vec);
5226 if (err < 0) {
5227 dev_err(adapter->pdev_dev, "Could not fetch port params\n");
d0417849 5228 goto free_mbox_log;
96fe11f2
GG		 5229 }
5230
5231 adapter->params.nports = hweight32(port_vec);
7829451c 5232 pci_set_drvdata(pdev, adapter);
7829451c
HS		 5233 return 0;
5234
d0417849
GG		 5235free_mbox_log:
5236 kfree(adapter->mbox_log);
7829451c
HS		 5237 free_adapter:
5238 kfree(adapter);
5239 free_pci_region:
5240 iounmap(regs);
5241 pci_disable_sriov(pdev);
5242 pci_release_regions(pdev);
5243 return err;
5244#else
b8ff05a9 5245 return 0;
7829451c 5246#endif
b8ff05a9
DM		 5247
5248 out_free_dev:
06546391 5249 free_some_resources(adapter);
94cdb8bb
HS		 5250 if (adapter->flags & USING_MSIX)
5251 free_msix_info(adapter);
0fbc81b3
HS		 5252 if (adapter->num_uld || adapter->num_ofld_uld)
5253 t4_uld_mem_free(adapter);
b8ff05a9 5254 out_unmap_bar:
d14807dd 5255 if (!is_t4(adapter->params.chip))
22adfe0a 5256 iounmap(adapter->bar2);
b8ff05a9 5257 out_free_adapter:
29aaee65
AB		 5258 if (adapter->workq)
5259 destroy_workqueue(adapter->workq);
5260
7f080c3f 5261 kfree(adapter->mbox_log);
b8ff05a9 5262 kfree(adapter);
d6ce2628
HS		 5263 out_unmap_bar0:
5264 iounmap(regs);
b8ff05a9
DM		 5265 out_disable_device:
5266 pci_disable_pcie_error_reporting(pdev);
5267 pci_disable_device(pdev);
5268 out_release_regions:
5269 pci_release_regions(pdev);
b8ff05a9
DM		 5270 return err;
5271}
5272
91744948 5273static void remove_one(struct pci_dev *pdev)
b8ff05a9
DM		 5274{
5275 struct adapter *adapter = pci_get_drvdata(pdev);
5276
7829451c
HS		 5277 if (!adapter) {
5278 pci_release_regions(pdev);
5279 return;
5280 }
636f9d37 5281
e1f6198e
GG		 5282 adapter->flags |= SHUTTING_DOWN;
5283
7829451c 5284 if (adapter->pf == 4) {
b8ff05a9
DM		 5285 int i;
5286
29aaee65
AB		 5287 /* Tear down per-adapter Work Queue first since it can contain
5288 * references to our adapter data structure.
5289 */
5290 destroy_workqueue(adapter->workq);
5291
6a146f3a 5292 if (is_uld(adapter)) {
b8ff05a9 5293 detach_ulds(adapter);
6a146f3a
GP		 5294 t4_uld_clean_up(adapter);
5295 }
b8ff05a9 5296
b37987e8
HS		 5297 disable_interrupts(adapter);
5298
b8ff05a9 5299 for_each_port(adapter, i)
8f3a7676 5300 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
b8ff05a9
DM		 5301 unregister_netdev(adapter->port[i]);
5302
9f16dc2e 5303 debugfs_remove_recursive(adapter->debugfs_root);
b8ff05a9 5304
9c33e420
AG		 5305 if (!is_t4(adapter->params.chip))
5306 cxgb4_ptp_stop(adapter);
5307
f2b7e78d
VP		 5308 /* If we allocated filters, free up state associated with any
5309 * valid filters ...
5310 */
578b46b9 5311 clear_all_filters(adapter);
f2b7e78d 5312
aaefae9b
DM		 5313 if (adapter->flags & FULL_INIT_DONE)
5314 cxgb_down(adapter);
b8ff05a9 5315
94cdb8bb
HS		 5316 if (adapter->flags & USING_MSIX)
5317 free_msix_info(adapter);
0fbc81b3
HS		 5318 if (adapter->num_uld || adapter->num_ofld_uld)
5319 t4_uld_mem_free(adapter);
06546391 5320 free_some_resources(adapter);
b5a02f50
AB		 5321#if IS_ENABLED(CONFIG_IPV6)
5322 t4_cleanup_clip_tbl(adapter);
5323#endif
b8ff05a9 5324 iounmap(adapter->regs);
d14807dd 5325 if (!is_t4(adapter->params.chip))
22adfe0a 5326 iounmap(adapter->bar2);
b8ff05a9 5327 pci_disable_pcie_error_reporting(pdev);
144be3d9
GS		 5328 if ((adapter->flags & DEV_ENABLED)) {
5329 pci_disable_device(pdev);
5330 adapter->flags &= ~DEV_ENABLED;
5331 }
b8ff05a9 5332 pci_release_regions(pdev);
7f080c3f 5333 kfree(adapter->mbox_log);
ee9a33b2 5334 synchronize_rcu();
8b662fe7 5335 kfree(adapter);
7829451c
HS		 5336 }
5337#ifdef CONFIG_PCI_IOV
5338 else {
e7b48a32 5339 if (adapter->port[0])
7829451c 5340 unregister_netdev(adapter->port[0]);
7829451c 5341 iounmap(adapter->regs);
661dbeb9 5342 kfree(adapter->vfinfo);
d0417849 5343 kfree(adapter->mbox_log);
7829451c
HS		 5344 kfree(adapter);
5345 pci_disable_sriov(pdev);
b8ff05a9 5346 pci_release_regions(pdev);
7829451c
HS		 5347 }
5348#endif
b8ff05a9
DM		 5349}
5350
0fbc81b3
HS		 5351/* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
5352 * delivery. This is essentially a stripped down version of the PCI remove()
5353 * function where we do the minimal amount of work necessary to shutdown any
5354 * further activity.
5355 */
5356static void shutdown_one(struct pci_dev *pdev)
5357{
5358 struct adapter *adapter = pci_get_drvdata(pdev);
5359
5360 /* As with remove_one() above (see extended comment), we only want do
5361 * do cleanup on PCI Devices which went all the way through init_one()
5362 * ...
5363 */
5364 if (!adapter) {
5365 pci_release_regions(pdev);
5366 return;
5367 }
5368
e1f6198e
GG		 5369 adapter->flags |= SHUTTING_DOWN;
5370
0fbc81b3
HS		 5371 if (adapter->pf == 4) {
5372 int i;
5373
5374 for_each_port(adapter, i)
5375 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5376 cxgb_close(adapter->port[i]);
5377
6a146f3a
GP		 5378 if (is_uld(adapter)) {
5379 detach_ulds(adapter);
5380 t4_uld_clean_up(adapter);
5381 }
5382
0fbc81b3
HS		 5383 disable_interrupts(adapter);
5384 disable_msi(adapter);
5385
5386 t4_sge_stop(adapter);
5387 if (adapter->flags & FW_OK)
5388 t4_fw_bye(adapter, adapter->mbox);
5389 }
5390#ifdef CONFIG_PCI_IOV
5391 else {
5392 if (adapter->port[0])
5393 unregister_netdev(adapter->port[0]);
5394 iounmap(adapter->regs);
5395 kfree(adapter->vfinfo);
d0417849 5396 kfree(adapter->mbox_log);
0fbc81b3
HS		 5397 kfree(adapter);
5398 pci_disable_sriov(pdev);
5399 pci_release_regions(pdev);
5400 }
5401#endif
5402}
5403
b8ff05a9
DM		 5404static struct pci_driver cxgb4_driver = {
5405 .name = KBUILD_MODNAME,
5406 .id_table = cxgb4_pci_tbl,
5407 .probe = init_one,
91744948 5408 .remove = remove_one,
0fbc81b3 5409 .shutdown = shutdown_one,
b6244201
HS		 5410#ifdef CONFIG_PCI_IOV
5411 .sriov_configure = cxgb4_iov_configure,
5412#endif
204dc3c0 5413 .err_handler = &cxgb4_eeh,
b8ff05a9
DM		 5414};
5415
5416static int __init cxgb4_init_module(void)
5417{
5418 int ret;
5419
5420 /* Debugfs support is optional, just warn if this fails */
5421 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5422 if (!cxgb4_debugfs_root)
428ac43f 5423 pr_warn("could not create debugfs entry, continuing\n");
b8ff05a9
DM		 5424
5425 ret = pci_register_driver(&cxgb4_driver);
29aaee65 5426 if (ret < 0)
b8ff05a9 5427 debugfs_remove(cxgb4_debugfs_root);
01bcca68 5428
1bb60376 5429#if IS_ENABLED(CONFIG_IPV6)
b5a02f50
AB		 5430 if (!inet6addr_registered) {
5431 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5432 inet6addr_registered = true;
5433 }
1bb60376 5434#endif
01bcca68 5435
b8ff05a9
DM		 5436 return ret;
5437}
5438
5439static void __exit cxgb4_cleanup_module(void)
5440{
1bb60376 5441#if IS_ENABLED(CONFIG_IPV6)
1793c798 5442 if (inet6addr_registered) {
b5a02f50
AB		 5443 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5444 inet6addr_registered = false;
5445 }
1bb60376 5446#endif
b8ff05a9
DM		 5447 pci_unregister_driver(&cxgb4_driver);
5448 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
5449}
5450
5451module_init(cxgb4_init_module);
5452module_exit(cxgb4_cleanup_module);
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