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fd3a4790 DM |
1 | /* |
2 | * This file is part of the Chelsio T4 Ethernet driver for Linux. | |
3 | * | |
ce100b8b | 4 | * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. |
fd3a4790 DM |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/skbuff.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/etherdevice.h> | |
38 | #include <linux/if_vlan.h> | |
39 | #include <linux/ip.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/jiffies.h> | |
70c71606 | 42 | #include <linux/prefetch.h> |
ee40fa06 | 43 | #include <linux/export.h> |
a6ec572b | 44 | #include <net/xfrm.h> |
fd3a4790 DM |
45 | #include <net/ipv6.h> |
46 | #include <net/tcp.h> | |
3a336cb1 | 47 | #include <net/busy_poll.h> |
84a200b3 VP |
48 | #ifdef CONFIG_CHELSIO_T4_FCOE |
49 | #include <scsi/fc/fc_fcoe.h> | |
50 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
fd3a4790 DM |
51 | #include "cxgb4.h" |
52 | #include "t4_regs.h" | |
f612b815 | 53 | #include "t4_values.h" |
fd3a4790 DM |
54 | #include "t4_msg.h" |
55 | #include "t4fw_api.h" | |
a4569504 | 56 | #include "cxgb4_ptp.h" |
a6ec572b | 57 | #include "cxgb4_uld.h" |
4846d533 | 58 | #include "cxgb4_tc_mqprio.h" |
0e395b3c | 59 | #include "sched.h" |
fd3a4790 DM |
60 | |
61 | /* | |
62 | * Rx buffer size. We use largish buffers if possible but settle for single | |
63 | * pages under memory shortage. | |
64 | */ | |
65 | #if PAGE_SHIFT >= 16 | |
66 | # define FL_PG_ORDER 0 | |
67 | #else | |
68 | # define FL_PG_ORDER (16 - PAGE_SHIFT) | |
69 | #endif | |
70 | ||
71 | /* RX_PULL_LEN should be <= RX_COPY_THRES */ | |
72 | #define RX_COPY_THRES 256 | |
73 | #define RX_PULL_LEN 128 | |
74 | ||
75 | /* | |
76 | * Main body length for sk_buffs used for Rx Ethernet packets with fragments. | |
77 | * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room. | |
78 | */ | |
79 | #define RX_PKT_SKB_LEN 512 | |
80 | ||
fd3a4790 DM |
81 | /* |
82 | * Max number of Tx descriptors we clean up at a time. Should be modest as | |
83 | * freeing skbs isn't cheap and it happens while holding locks. We just need | |
84 | * to free packets faster than they arrive, we eventually catch up and keep | |
d429005f VK |
85 | * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES. It should |
86 | * also match the CIDX Flush Threshold. | |
fd3a4790 | 87 | */ |
d429005f | 88 | #define MAX_TX_RECLAIM 32 |
fd3a4790 DM |
89 | |
90 | /* | |
91 | * Max number of Rx buffers we replenish at a time. Again keep this modest, | |
92 | * allocating buffers isn't cheap either. | |
93 | */ | |
94 | #define MAX_RX_REFILL 16U | |
95 | ||
96 | /* | |
97 | * Period of the Rx queue check timer. This timer is infrequent as it has | |
98 | * something to do only when the system experiences severe memory shortage. | |
99 | */ | |
100 | #define RX_QCHECK_PERIOD (HZ / 2) | |
101 | ||
102 | /* | |
103 | * Period of the Tx queue check timer. | |
104 | */ | |
105 | #define TX_QCHECK_PERIOD (HZ / 2) | |
106 | ||
107 | /* | |
108 | * Max number of Tx descriptors to be reclaimed by the Tx timer. | |
109 | */ | |
110 | #define MAX_TIMER_TX_RECLAIM 100 | |
111 | ||
112 | /* | |
113 | * Timer index used when backing off due to memory shortage. | |
114 | */ | |
115 | #define NOMEM_TMR_IDX (SGE_NTIMERS - 1) | |
116 | ||
fd3a4790 DM |
117 | /* |
118 | * Suspension threshold for non-Ethernet Tx queues. We require enough room | |
119 | * for a full sized WR. | |
120 | */ | |
121 | #define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc)) | |
122 | ||
123 | /* | |
124 | * Max Tx descriptor space we allow for an Ethernet packet to be inlined | |
125 | * into a WR. | |
126 | */ | |
21dcfad6 | 127 | #define MAX_IMM_TX_PKT_LEN 256 |
fd3a4790 DM |
128 | |
129 | /* | |
130 | * Max size of a WR sent through a control Tx queue. | |
131 | */ | |
132 | #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN | |
133 | ||
fd3a4790 DM |
134 | struct rx_sw_desc { /* SW state per Rx descriptor */ |
135 | struct page *page; | |
136 | dma_addr_t dma_addr; | |
137 | }; | |
138 | ||
139 | /* | |
52367a76 VP |
140 | * Rx buffer sizes for "useskbs" Free List buffers (one ingress packet pe skb |
141 | * buffer). We currently only support two sizes for 1500- and 9000-byte MTUs. | |
142 | * We could easily support more but there doesn't seem to be much need for | |
143 | * that ... | |
144 | */ | |
145 | #define FL_MTU_SMALL 1500 | |
146 | #define FL_MTU_LARGE 9000 | |
147 | ||
148 | static inline unsigned int fl_mtu_bufsize(struct adapter *adapter, | |
149 | unsigned int mtu) | |
150 | { | |
151 | struct sge *s = &adapter->sge; | |
152 | ||
153 | return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align); | |
154 | } | |
155 | ||
156 | #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL) | |
157 | #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE) | |
158 | ||
159 | /* | |
160 | * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses | |
161 | * these to specify the buffer size as an index into the SGE Free List Buffer | |
162 | * Size register array. We also use bit 4, when the buffer has been unmapped | |
163 | * for DMA, but this is of course never sent to the hardware and is only used | |
164 | * to prevent double unmappings. All of the above requires that the Free List | |
165 | * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are | |
166 | * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal | |
167 | * Free List Buffer alignment is 32 bytes, this works out for us ... | |
fd3a4790 DM |
168 | */ |
169 | enum { | |
52367a76 VP |
170 | RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */ |
171 | RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */ | |
172 | RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */ | |
173 | ||
174 | /* | |
175 | * XXX We shouldn't depend on being able to use these indices. | |
176 | * XXX Especially when some other Master PF has initialized the | |
177 | * XXX adapter or we use the Firmware Configuration File. We | |
178 | * XXX should really search through the Host Buffer Size register | |
179 | * XXX array for the appropriately sized buffer indices. | |
180 | */ | |
181 | RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */ | |
182 | RX_LARGE_PG_BUF = 0x1, /* buffer large (FL_PG_ORDER) page buffer */ | |
183 | ||
184 | RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */ | |
185 | RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */ | |
fd3a4790 DM |
186 | }; |
187 | ||
e553ec3f HS |
188 | static int timer_pkt_quota[] = {1, 1, 2, 3, 4, 5}; |
189 | #define MIN_NAPI_WORK 1 | |
190 | ||
fd3a4790 DM |
191 | static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d) |
192 | { | |
52367a76 | 193 | return d->dma_addr & ~(dma_addr_t)RX_BUF_FLAGS; |
fd3a4790 DM |
194 | } |
195 | ||
196 | static inline bool is_buf_mapped(const struct rx_sw_desc *d) | |
197 | { | |
198 | return !(d->dma_addr & RX_UNMAPPED_BUF); | |
199 | } | |
200 | ||
201 | /** | |
202 | * txq_avail - return the number of available slots in a Tx queue | |
203 | * @q: the Tx queue | |
204 | * | |
205 | * Returns the number of descriptors in a Tx queue available to write new | |
206 | * packets. | |
207 | */ | |
208 | static inline unsigned int txq_avail(const struct sge_txq *q) | |
209 | { | |
210 | return q->size - 1 - q->in_use; | |
211 | } | |
212 | ||
213 | /** | |
214 | * fl_cap - return the capacity of a free-buffer list | |
215 | * @fl: the FL | |
216 | * | |
217 | * Returns the capacity of a free-buffer list. The capacity is less than | |
218 | * the size because one descriptor needs to be left unpopulated, otherwise | |
219 | * HW will think the FL is empty. | |
220 | */ | |
221 | static inline unsigned int fl_cap(const struct sge_fl *fl) | |
222 | { | |
223 | return fl->size - 8; /* 1 descriptor = 8 buffers */ | |
224 | } | |
225 | ||
c098b026 HS |
226 | /** |
227 | * fl_starving - return whether a Free List is starving. | |
228 | * @adapter: pointer to the adapter | |
229 | * @fl: the Free List | |
230 | * | |
231 | * Tests specified Free List to see whether the number of buffers | |
232 | * available to the hardware has falled below our "starvation" | |
233 | * threshold. | |
234 | */ | |
235 | static inline bool fl_starving(const struct adapter *adapter, | |
236 | const struct sge_fl *fl) | |
fd3a4790 | 237 | { |
c098b026 HS |
238 | const struct sge *s = &adapter->sge; |
239 | ||
240 | return fl->avail - fl->pend_cred <= s->fl_starve_thres; | |
fd3a4790 DM |
241 | } |
242 | ||
a6ec572b AG |
243 | int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb, |
244 | dma_addr_t *addr) | |
fd3a4790 DM |
245 | { |
246 | const skb_frag_t *fp, *end; | |
247 | const struct skb_shared_info *si; | |
248 | ||
249 | *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); | |
250 | if (dma_mapping_error(dev, *addr)) | |
251 | goto out_err; | |
252 | ||
253 | si = skb_shinfo(skb); | |
254 | end = &si->frags[si->nr_frags]; | |
255 | ||
256 | for (fp = si->frags; fp < end; fp++) { | |
e91b0f24 IC |
257 | *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp), |
258 | DMA_TO_DEVICE); | |
fd3a4790 DM |
259 | if (dma_mapping_error(dev, *addr)) |
260 | goto unwind; | |
261 | } | |
262 | return 0; | |
263 | ||
264 | unwind: | |
265 | while (fp-- > si->frags) | |
9e903e08 | 266 | dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE); |
fd3a4790 DM |
267 | |
268 | dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE); | |
269 | out_err: | |
270 | return -ENOMEM; | |
271 | } | |
a6ec572b | 272 | EXPORT_SYMBOL(cxgb4_map_skb); |
fd3a4790 | 273 | |
fd3a4790 DM |
274 | static void unmap_skb(struct device *dev, const struct sk_buff *skb, |
275 | const dma_addr_t *addr) | |
276 | { | |
277 | const skb_frag_t *fp, *end; | |
278 | const struct skb_shared_info *si; | |
279 | ||
280 | dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE); | |
281 | ||
282 | si = skb_shinfo(skb); | |
283 | end = &si->frags[si->nr_frags]; | |
284 | for (fp = si->frags; fp < end; fp++) | |
9e903e08 | 285 | dma_unmap_page(dev, *addr++, skb_frag_size(fp), DMA_TO_DEVICE); |
fd3a4790 DM |
286 | } |
287 | ||
b1396c2b | 288 | #ifdef CONFIG_NEED_DMA_MAP_STATE |
fd3a4790 DM |
289 | /** |
290 | * deferred_unmap_destructor - unmap a packet when it is freed | |
291 | * @skb: the packet | |
292 | * | |
293 | * This is the packet destructor used for Tx packets that need to remain | |
294 | * mapped until they are freed rather than until their Tx descriptors are | |
295 | * freed. | |
296 | */ | |
297 | static void deferred_unmap_destructor(struct sk_buff *skb) | |
298 | { | |
299 | unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head); | |
300 | } | |
301 | #endif | |
302 | ||
fd3a4790 DM |
303 | /** |
304 | * free_tx_desc - reclaims Tx descriptors and their buffers | |
305 | * @adapter: the adapter | |
306 | * @q: the Tx queue to reclaim descriptors from | |
307 | * @n: the number of descriptors to reclaim | |
308 | * @unmap: whether the buffers should be unmapped for DMA | |
309 | * | |
310 | * Reclaims Tx descriptors from an SGE Tx queue and frees the associated | |
311 | * Tx buffers. Called with the Tx queue lock held. | |
312 | */ | |
ab677ff4 HS |
313 | void free_tx_desc(struct adapter *adap, struct sge_txq *q, |
314 | unsigned int n, bool unmap) | |
fd3a4790 | 315 | { |
fd3a4790 | 316 | unsigned int cidx = q->cidx; |
0ed96b46 | 317 | struct tx_sw_desc *d; |
fd3a4790 DM |
318 | |
319 | d = &q->sdesc[cidx]; | |
320 | while (n--) { | |
321 | if (d->skb) { /* an SGL is present */ | |
0ed96b46 RL |
322 | if (unmap && d->addr[0]) { |
323 | unmap_skb(adap->pdev_dev, d->skb, d->addr); | |
324 | memset(d->addr, 0, sizeof(d->addr)); | |
325 | } | |
a7525198 | 326 | dev_consume_skb_any(d->skb); |
fd3a4790 DM |
327 | d->skb = NULL; |
328 | } | |
329 | ++d; | |
330 | if (++cidx == q->size) { | |
331 | cidx = 0; | |
332 | d = q->sdesc; | |
333 | } | |
334 | } | |
335 | q->cidx = cidx; | |
336 | } | |
337 | ||
338 | /* | |
339 | * Return the number of reclaimable descriptors in a Tx queue. | |
340 | */ | |
341 | static inline int reclaimable(const struct sge_txq *q) | |
342 | { | |
6aa7de05 | 343 | int hw_cidx = ntohs(READ_ONCE(q->stat->cidx)); |
fd3a4790 DM |
344 | hw_cidx -= q->cidx; |
345 | return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx; | |
346 | } | |
347 | ||
348 | /** | |
d429005f | 349 | * reclaim_completed_tx - reclaims completed TX Descriptors |
fd3a4790 DM |
350 | * @adap: the adapter |
351 | * @q: the Tx queue to reclaim completed descriptors from | |
d429005f | 352 | * @maxreclaim: the maximum number of TX Descriptors to reclaim or -1 |
fd3a4790 DM |
353 | * @unmap: whether the buffers should be unmapped for DMA |
354 | * | |
d429005f VK |
355 | * Reclaims Tx Descriptors that the SGE has indicated it has processed, |
356 | * and frees the associated buffers if possible. If @max == -1, then | |
357 | * we'll use a defaiult maximum. Called with the TX Queue locked. | |
fd3a4790 | 358 | */ |
d429005f VK |
359 | static inline int reclaim_completed_tx(struct adapter *adap, struct sge_txq *q, |
360 | int maxreclaim, bool unmap) | |
fd3a4790 | 361 | { |
d429005f | 362 | int reclaim = reclaimable(q); |
fd3a4790 | 363 | |
d429005f | 364 | if (reclaim) { |
fd3a4790 DM |
365 | /* |
366 | * Limit the amount of clean up work we do at a time to keep | |
367 | * the Tx lock hold time O(1). | |
368 | */ | |
d429005f VK |
369 | if (maxreclaim < 0) |
370 | maxreclaim = MAX_TX_RECLAIM; | |
371 | if (reclaim > maxreclaim) | |
372 | reclaim = maxreclaim; | |
fd3a4790 | 373 | |
d429005f VK |
374 | free_tx_desc(adap, q, reclaim, unmap); |
375 | q->in_use -= reclaim; | |
fd3a4790 | 376 | } |
d429005f VK |
377 | |
378 | return reclaim; | |
379 | } | |
380 | ||
381 | /** | |
382 | * cxgb4_reclaim_completed_tx - reclaims completed Tx descriptors | |
383 | * @adap: the adapter | |
384 | * @q: the Tx queue to reclaim completed descriptors from | |
385 | * @unmap: whether the buffers should be unmapped for DMA | |
386 | * | |
387 | * Reclaims Tx descriptors that the SGE has indicated it has processed, | |
388 | * and frees the associated buffers if possible. Called with the Tx | |
389 | * queue locked. | |
390 | */ | |
391 | void cxgb4_reclaim_completed_tx(struct adapter *adap, struct sge_txq *q, | |
392 | bool unmap) | |
393 | { | |
394 | (void)reclaim_completed_tx(adap, q, -1, unmap); | |
fd3a4790 | 395 | } |
a6ec572b | 396 | EXPORT_SYMBOL(cxgb4_reclaim_completed_tx); |
fd3a4790 | 397 | |
52367a76 VP |
398 | static inline int get_buf_size(struct adapter *adapter, |
399 | const struct rx_sw_desc *d) | |
fd3a4790 | 400 | { |
52367a76 VP |
401 | struct sge *s = &adapter->sge; |
402 | unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE; | |
403 | int buf_size; | |
404 | ||
405 | switch (rx_buf_size_idx) { | |
406 | case RX_SMALL_PG_BUF: | |
407 | buf_size = PAGE_SIZE; | |
408 | break; | |
409 | ||
410 | case RX_LARGE_PG_BUF: | |
411 | buf_size = PAGE_SIZE << s->fl_pg_order; | |
412 | break; | |
413 | ||
414 | case RX_SMALL_MTU_BUF: | |
415 | buf_size = FL_MTU_SMALL_BUFSIZE(adapter); | |
416 | break; | |
417 | ||
418 | case RX_LARGE_MTU_BUF: | |
419 | buf_size = FL_MTU_LARGE_BUFSIZE(adapter); | |
420 | break; | |
421 | ||
422 | default: | |
047a013f | 423 | BUG(); |
52367a76 VP |
424 | } |
425 | ||
426 | return buf_size; | |
fd3a4790 DM |
427 | } |
428 | ||
429 | /** | |
430 | * free_rx_bufs - free the Rx buffers on an SGE free list | |
431 | * @adap: the adapter | |
432 | * @q: the SGE free list to free buffers from | |
433 | * @n: how many buffers to free | |
434 | * | |
435 | * Release the next @n buffers on an SGE free-buffer Rx queue. The | |
436 | * buffers must be made inaccessible to HW before calling this function. | |
437 | */ | |
438 | static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n) | |
439 | { | |
440 | while (n--) { | |
441 | struct rx_sw_desc *d = &q->sdesc[q->cidx]; | |
442 | ||
443 | if (is_buf_mapped(d)) | |
444 | dma_unmap_page(adap->pdev_dev, get_buf_addr(d), | |
52367a76 VP |
445 | get_buf_size(adap, d), |
446 | PCI_DMA_FROMDEVICE); | |
fd3a4790 DM |
447 | put_page(d->page); |
448 | d->page = NULL; | |
449 | if (++q->cidx == q->size) | |
450 | q->cidx = 0; | |
451 | q->avail--; | |
452 | } | |
453 | } | |
454 | ||
455 | /** | |
456 | * unmap_rx_buf - unmap the current Rx buffer on an SGE free list | |
457 | * @adap: the adapter | |
458 | * @q: the SGE free list | |
459 | * | |
460 | * Unmap the current buffer on an SGE free-buffer Rx queue. The | |
461 | * buffer must be made inaccessible to HW before calling this function. | |
462 | * | |
463 | * This is similar to @free_rx_bufs above but does not free the buffer. | |
464 | * Do note that the FL still loses any further access to the buffer. | |
465 | */ | |
466 | static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q) | |
467 | { | |
468 | struct rx_sw_desc *d = &q->sdesc[q->cidx]; | |
469 | ||
470 | if (is_buf_mapped(d)) | |
471 | dma_unmap_page(adap->pdev_dev, get_buf_addr(d), | |
52367a76 | 472 | get_buf_size(adap, d), PCI_DMA_FROMDEVICE); |
fd3a4790 DM |
473 | d->page = NULL; |
474 | if (++q->cidx == q->size) | |
475 | q->cidx = 0; | |
476 | q->avail--; | |
477 | } | |
478 | ||
479 | static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) | |
480 | { | |
481 | if (q->pend_cred >= 8) { | |
3ccc6cf7 HS |
482 | u32 val = adap->params.arch.sge_fl_db; |
483 | ||
f612b815 | 484 | if (is_t4(adap->params.chip)) |
3ccc6cf7 | 485 | val |= PIDX_V(q->pend_cred / 8); |
f612b815 | 486 | else |
3ccc6cf7 | 487 | val |= PIDX_T5_V(q->pend_cred / 8); |
1ecc7b7a HS |
488 | |
489 | /* Make sure all memory writes to the Free List queue are | |
490 | * committed before we tell the hardware about them. | |
491 | */ | |
fd3a4790 | 492 | wmb(); |
d63a6dcf | 493 | |
df64e4d3 HS |
494 | /* If we don't have access to the new User Doorbell (T5+), use |
495 | * the old doorbell mechanism; otherwise use the new BAR2 | |
496 | * mechanism. | |
d63a6dcf | 497 | */ |
df64e4d3 | 498 | if (unlikely(q->bar2_addr == NULL)) { |
f612b815 HS |
499 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
500 | val | QID_V(q->cntxt_id)); | |
d63a6dcf | 501 | } else { |
f612b815 | 502 | writel(val | QID_V(q->bar2_qid), |
df64e4d3 | 503 | q->bar2_addr + SGE_UDB_KDOORBELL); |
d63a6dcf HS |
504 | |
505 | /* This Write memory Barrier will force the write to | |
506 | * the User Doorbell area to be flushed. | |
507 | */ | |
508 | wmb(); | |
509 | } | |
fd3a4790 DM |
510 | q->pend_cred &= 7; |
511 | } | |
512 | } | |
513 | ||
514 | static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg, | |
515 | dma_addr_t mapping) | |
516 | { | |
517 | sd->page = pg; | |
518 | sd->dma_addr = mapping; /* includes size low bits */ | |
519 | } | |
520 | ||
521 | /** | |
522 | * refill_fl - refill an SGE Rx buffer ring | |
523 | * @adap: the adapter | |
524 | * @q: the ring to refill | |
525 | * @n: the number of new buffers to allocate | |
526 | * @gfp: the gfp flags for the allocations | |
527 | * | |
528 | * (Re)populate an SGE free-buffer queue with up to @n new packet buffers, | |
529 | * allocated with the supplied gfp flags. The caller must assure that | |
530 | * @n does not exceed the queue's capacity. If afterwards the queue is | |
531 | * found critically low mark it as starving in the bitmap of starving FLs. | |
532 | * | |
533 | * Returns the number of buffers allocated. | |
534 | */ | |
535 | static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n, | |
536 | gfp_t gfp) | |
537 | { | |
52367a76 | 538 | struct sge *s = &adap->sge; |
fd3a4790 DM |
539 | struct page *pg; |
540 | dma_addr_t mapping; | |
541 | unsigned int cred = q->avail; | |
542 | __be64 *d = &q->desc[q->pidx]; | |
543 | struct rx_sw_desc *sd = &q->sdesc[q->pidx]; | |
d52ce920 | 544 | int node; |
fd3a4790 | 545 | |
5b377d11 HS |
546 | #ifdef CONFIG_DEBUG_FS |
547 | if (test_bit(q->cntxt_id - adap->sge.egr_start, adap->sge.blocked_fl)) | |
548 | goto out; | |
549 | #endif | |
550 | ||
aa9cd31c | 551 | gfp |= __GFP_NOWARN; |
d52ce920 | 552 | node = dev_to_node(adap->pdev_dev); |
fd3a4790 | 553 | |
52367a76 VP |
554 | if (s->fl_pg_order == 0) |
555 | goto alloc_small_pages; | |
556 | ||
fd3a4790 DM |
557 | /* |
558 | * Prefer large buffers | |
559 | */ | |
560 | while (n) { | |
d52ce920 | 561 | pg = alloc_pages_node(node, gfp | __GFP_COMP, s->fl_pg_order); |
fd3a4790 DM |
562 | if (unlikely(!pg)) { |
563 | q->large_alloc_failed++; | |
564 | break; /* fall back to single pages */ | |
565 | } | |
566 | ||
567 | mapping = dma_map_page(adap->pdev_dev, pg, 0, | |
52367a76 | 568 | PAGE_SIZE << s->fl_pg_order, |
fd3a4790 DM |
569 | PCI_DMA_FROMDEVICE); |
570 | if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { | |
52367a76 | 571 | __free_pages(pg, s->fl_pg_order); |
70055dd0 | 572 | q->mapping_err++; |
fd3a4790 DM |
573 | goto out; /* do not try small pages for this error */ |
574 | } | |
52367a76 | 575 | mapping |= RX_LARGE_PG_BUF; |
fd3a4790 DM |
576 | *d++ = cpu_to_be64(mapping); |
577 | ||
578 | set_rx_sw_desc(sd, pg, mapping); | |
579 | sd++; | |
580 | ||
581 | q->avail++; | |
582 | if (++q->pidx == q->size) { | |
583 | q->pidx = 0; | |
584 | sd = q->sdesc; | |
585 | d = q->desc; | |
586 | } | |
587 | n--; | |
588 | } | |
fd3a4790 | 589 | |
52367a76 | 590 | alloc_small_pages: |
fd3a4790 | 591 | while (n--) { |
d52ce920 | 592 | pg = alloc_pages_node(node, gfp, 0); |
fd3a4790 DM |
593 | if (unlikely(!pg)) { |
594 | q->alloc_failed++; | |
595 | break; | |
596 | } | |
597 | ||
598 | mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE, | |
599 | PCI_DMA_FROMDEVICE); | |
600 | if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) { | |
1f2149c1 | 601 | put_page(pg); |
70055dd0 | 602 | q->mapping_err++; |
fd3a4790 DM |
603 | goto out; |
604 | } | |
605 | *d++ = cpu_to_be64(mapping); | |
606 | ||
607 | set_rx_sw_desc(sd, pg, mapping); | |
608 | sd++; | |
609 | ||
610 | q->avail++; | |
611 | if (++q->pidx == q->size) { | |
612 | q->pidx = 0; | |
613 | sd = q->sdesc; | |
614 | d = q->desc; | |
615 | } | |
616 | } | |
617 | ||
618 | out: cred = q->avail - cred; | |
619 | q->pend_cred += cred; | |
620 | ring_fl_db(adap, q); | |
621 | ||
c098b026 | 622 | if (unlikely(fl_starving(adap, q))) { |
fd3a4790 | 623 | smp_wmb(); |
70055dd0 | 624 | q->low++; |
e46dab4d DM |
625 | set_bit(q->cntxt_id - adap->sge.egr_start, |
626 | adap->sge.starving_fl); | |
fd3a4790 DM |
627 | } |
628 | ||
629 | return cred; | |
630 | } | |
631 | ||
632 | static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl) | |
633 | { | |
634 | refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail), | |
635 | GFP_ATOMIC); | |
636 | } | |
637 | ||
638 | /** | |
639 | * alloc_ring - allocate resources for an SGE descriptor ring | |
640 | * @dev: the PCI device's core device | |
641 | * @nelem: the number of descriptors | |
642 | * @elem_size: the size of each descriptor | |
643 | * @sw_size: the size of the SW state associated with each ring element | |
644 | * @phys: the physical address of the allocated ring | |
645 | * @metadata: address of the array holding the SW state for the ring | |
646 | * @stat_size: extra space in HW ring for status information | |
ad6bad3e | 647 | * @node: preferred node for memory allocations |
fd3a4790 DM |
648 | * |
649 | * Allocates resources for an SGE descriptor ring, such as Tx queues, | |
650 | * free buffer lists, or response queues. Each SGE ring requires | |
651 | * space for its HW descriptors plus, optionally, space for the SW state | |
652 | * associated with each HW entry (the metadata). The function returns | |
653 | * three values: the virtual address for the HW ring (the return value | |
654 | * of the function), the bus address of the HW ring, and the address | |
655 | * of the SW ring. | |
656 | */ | |
657 | static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size, | |
658 | size_t sw_size, dma_addr_t *phys, void *metadata, | |
ad6bad3e | 659 | size_t stat_size, int node) |
fd3a4790 DM |
660 | { |
661 | size_t len = nelem * elem_size + stat_size; | |
662 | void *s = NULL; | |
750afb08 | 663 | void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL); |
fd3a4790 DM |
664 | |
665 | if (!p) | |
666 | return NULL; | |
667 | if (sw_size) { | |
590b5b7d | 668 | s = kcalloc_node(sw_size, nelem, GFP_KERNEL, node); |
fd3a4790 DM |
669 | |
670 | if (!s) { | |
671 | dma_free_coherent(dev, len, p, *phys); | |
672 | return NULL; | |
673 | } | |
674 | } | |
675 | if (metadata) | |
676 | *(void **)metadata = s; | |
fd3a4790 DM |
677 | return p; |
678 | } | |
679 | ||
680 | /** | |
681 | * sgl_len - calculates the size of an SGL of the given capacity | |
682 | * @n: the number of SGL entries | |
683 | * | |
684 | * Calculates the number of flits needed for a scatter/gather list that | |
685 | * can hold the given number of entries. | |
686 | */ | |
687 | static inline unsigned int sgl_len(unsigned int n) | |
688 | { | |
0aac3f56 HS |
689 | /* A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA |
690 | * addresses. The DSGL Work Request starts off with a 32-bit DSGL | |
691 | * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N, | |
692 | * repeated sequences of { Length[i], Length[i+1], Address[i], | |
693 | * Address[i+1] } (this ensures that all addresses are on 64-bit | |
694 | * boundaries). If N is even, then Length[N+1] should be set to 0 and | |
695 | * Address[N+1] is omitted. | |
696 | * | |
697 | * The following calculation incorporates all of the above. It's | |
698 | * somewhat hard to follow but, briefly: the "+2" accounts for the | |
699 | * first two flits which include the DSGL header, Length0 and | |
700 | * Address0; the "(3*(n-1))/2" covers the main body of list entries (3 | |
701 | * flits for every pair of the remaining N) +1 if (n-1) is odd; and | |
702 | * finally the "+((n-1)&1)" adds the one remaining flit needed if | |
703 | * (n-1) is odd ... | |
704 | */ | |
fd3a4790 DM |
705 | n--; |
706 | return (3 * n) / 2 + (n & 1) + 2; | |
707 | } | |
708 | ||
709 | /** | |
710 | * flits_to_desc - returns the num of Tx descriptors for the given flits | |
711 | * @n: the number of flits | |
712 | * | |
713 | * Returns the number of Tx descriptors needed for the supplied number | |
714 | * of flits. | |
715 | */ | |
716 | static inline unsigned int flits_to_desc(unsigned int n) | |
717 | { | |
718 | BUG_ON(n > SGE_MAX_WR_LEN / 8); | |
719 | return DIV_ROUND_UP(n, 8); | |
720 | } | |
721 | ||
722 | /** | |
723 | * is_eth_imm - can an Ethernet packet be sent as immediate data? | |
724 | * @skb: the packet | |
725 | * | |
726 | * Returns whether an Ethernet packet is small enough to fit as | |
0034b298 | 727 | * immediate data. Return value corresponds to headroom required. |
fd3a4790 | 728 | */ |
d0a1299c | 729 | static inline int is_eth_imm(const struct sk_buff *skb, unsigned int chip_ver) |
fd3a4790 | 730 | { |
d0a1299c | 731 | int hdrlen = 0; |
0034b298 | 732 | |
d0a1299c GG |
733 | if (skb->encapsulation && skb_shinfo(skb)->gso_size && |
734 | chip_ver > CHELSIO_T5) { | |
735 | hdrlen = sizeof(struct cpl_tx_tnl_lso); | |
736 | hdrlen += sizeof(struct cpl_tx_pkt_core); | |
1a2a14fb RL |
737 | } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { |
738 | return 0; | |
d0a1299c GG |
739 | } else { |
740 | hdrlen = skb_shinfo(skb)->gso_size ? | |
741 | sizeof(struct cpl_tx_pkt_lso_core) : 0; | |
742 | hdrlen += sizeof(struct cpl_tx_pkt); | |
743 | } | |
0034b298 KS |
744 | if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen) |
745 | return hdrlen; | |
746 | return 0; | |
fd3a4790 DM |
747 | } |
748 | ||
749 | /** | |
750 | * calc_tx_flits - calculate the number of flits for a packet Tx WR | |
751 | * @skb: the packet | |
752 | * | |
753 | * Returns the number of flits needed for a Tx WR for the given Ethernet | |
754 | * packet, including the needed WR and CPL headers. | |
755 | */ | |
d0a1299c GG |
756 | static inline unsigned int calc_tx_flits(const struct sk_buff *skb, |
757 | unsigned int chip_ver) | |
fd3a4790 DM |
758 | { |
759 | unsigned int flits; | |
d0a1299c | 760 | int hdrlen = is_eth_imm(skb, chip_ver); |
fd3a4790 | 761 | |
0aac3f56 HS |
762 | /* If the skb is small enough, we can pump it out as a work request |
763 | * with only immediate data. In that case we just have to have the | |
764 | * TX Packet header plus the skb data in the Work Request. | |
765 | */ | |
766 | ||
0034b298 KS |
767 | if (hdrlen) |
768 | return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64)); | |
fd3a4790 | 769 | |
0aac3f56 HS |
770 | /* Otherwise, we're going to have to construct a Scatter gather list |
771 | * of the skb body and fragments. We also include the flits necessary | |
772 | * for the TX Packet Work Request and CPL. We always have a firmware | |
773 | * Write Header (incorporated as part of the cpl_tx_pkt_lso and | |
774 | * cpl_tx_pkt structures), followed by either a TX Packet Write CPL | |
775 | * message or, if we're doing a Large Send Offload, an LSO CPL message | |
776 | * with an embedded TX Packet Write CPL message. | |
777 | */ | |
fd1754fb | 778 | flits = sgl_len(skb_shinfo(skb)->nr_frags + 1); |
d0a1299c | 779 | if (skb_shinfo(skb)->gso_size) { |
1a2a14fb | 780 | if (skb->encapsulation && chip_ver > CHELSIO_T5) { |
d0a1299c GG |
781 | hdrlen = sizeof(struct fw_eth_tx_pkt_wr) + |
782 | sizeof(struct cpl_tx_tnl_lso); | |
1a2a14fb RL |
783 | } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { |
784 | u32 pkt_hdrlen; | |
785 | ||
786 | pkt_hdrlen = eth_get_headlen(skb->dev, skb->data, | |
787 | skb_headlen(skb)); | |
788 | hdrlen = sizeof(struct fw_eth_tx_eo_wr) + | |
789 | round_up(pkt_hdrlen, 16); | |
790 | } else { | |
d0a1299c GG |
791 | hdrlen = sizeof(struct fw_eth_tx_pkt_wr) + |
792 | sizeof(struct cpl_tx_pkt_lso_core); | |
1a2a14fb | 793 | } |
d0a1299c GG |
794 | |
795 | hdrlen += sizeof(struct cpl_tx_pkt_core); | |
796 | flits += (hdrlen / sizeof(__be64)); | |
797 | } else { | |
0aac3f56 HS |
798 | flits += (sizeof(struct fw_eth_tx_pkt_wr) + |
799 | sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64); | |
d0a1299c | 800 | } |
fd3a4790 DM |
801 | return flits; |
802 | } | |
803 | ||
804 | /** | |
805 | * calc_tx_descs - calculate the number of Tx descriptors for a packet | |
806 | * @skb: the packet | |
807 | * | |
808 | * Returns the number of Tx descriptors needed for the given Ethernet | |
809 | * packet, including the needed WR and CPL headers. | |
810 | */ | |
d0a1299c GG |
811 | static inline unsigned int calc_tx_descs(const struct sk_buff *skb, |
812 | unsigned int chip_ver) | |
fd3a4790 | 813 | { |
d0a1299c | 814 | return flits_to_desc(calc_tx_flits(skb, chip_ver)); |
fd3a4790 DM |
815 | } |
816 | ||
817 | /** | |
a6ec572b | 818 | * cxgb4_write_sgl - populate a scatter/gather list for a packet |
fd3a4790 DM |
819 | * @skb: the packet |
820 | * @q: the Tx queue we are writing into | |
821 | * @sgl: starting location for writing the SGL | |
822 | * @end: points right after the end of the SGL | |
823 | * @start: start offset into skb main-body data to include in the SGL | |
824 | * @addr: the list of bus addresses for the SGL elements | |
825 | * | |
826 | * Generates a gather list for the buffers that make up a packet. | |
827 | * The caller must provide adequate space for the SGL that will be written. | |
828 | * The SGL includes all of the packet's page fragments and the data in its | |
829 | * main body except for the first @start bytes. @sgl must be 16-byte | |
830 | * aligned and within a Tx descriptor with available space. @end points | |
831 | * right after the end of the SGL but does not account for any potential | |
832 | * wrap around, i.e., @end > @sgl. | |
833 | */ | |
a6ec572b AG |
834 | void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q, |
835 | struct ulptx_sgl *sgl, u64 *end, unsigned int start, | |
836 | const dma_addr_t *addr) | |
fd3a4790 DM |
837 | { |
838 | unsigned int i, len; | |
839 | struct ulptx_sge_pair *to; | |
840 | const struct skb_shared_info *si = skb_shinfo(skb); | |
841 | unsigned int nfrags = si->nr_frags; | |
842 | struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1]; | |
843 | ||
844 | len = skb_headlen(skb) - start; | |
845 | if (likely(len)) { | |
846 | sgl->len0 = htonl(len); | |
847 | sgl->addr0 = cpu_to_be64(addr[0] + start); | |
848 | nfrags++; | |
849 | } else { | |
9e903e08 | 850 | sgl->len0 = htonl(skb_frag_size(&si->frags[0])); |
fd3a4790 DM |
851 | sgl->addr0 = cpu_to_be64(addr[1]); |
852 | } | |
853 | ||
bdc590b9 HS |
854 | sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) | |
855 | ULPTX_NSGE_V(nfrags)); | |
fd3a4790 DM |
856 | if (likely(--nfrags == 0)) |
857 | return; | |
858 | /* | |
859 | * Most of the complexity below deals with the possibility we hit the | |
860 | * end of the queue in the middle of writing the SGL. For this case | |
861 | * only we create the SGL in a temporary buffer and then copy it. | |
862 | */ | |
863 | to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge; | |
864 | ||
865 | for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) { | |
9e903e08 ED |
866 | to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); |
867 | to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i])); | |
fd3a4790 DM |
868 | to->addr[0] = cpu_to_be64(addr[i]); |
869 | to->addr[1] = cpu_to_be64(addr[++i]); | |
870 | } | |
871 | if (nfrags) { | |
9e903e08 | 872 | to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i])); |
fd3a4790 DM |
873 | to->len[1] = cpu_to_be32(0); |
874 | to->addr[0] = cpu_to_be64(addr[i + 1]); | |
875 | } | |
876 | if (unlikely((u8 *)end > (u8 *)q->stat)) { | |
877 | unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1; | |
878 | ||
879 | if (likely(part0)) | |
880 | memcpy(sgl->sge, buf, part0); | |
881 | part1 = (u8 *)end - (u8 *)q->stat; | |
882 | memcpy(q->desc, (u8 *)buf + part0, part1); | |
883 | end = (void *)q->desc + part1; | |
884 | } | |
885 | if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */ | |
64699336 | 886 | *end = 0; |
fd3a4790 | 887 | } |
a6ec572b | 888 | EXPORT_SYMBOL(cxgb4_write_sgl); |
fd3a4790 | 889 | |
df64e4d3 HS |
890 | /* This function copies 64 byte coalesced work request to |
891 | * memory mapped BAR2 space. For coalesced WR SGE fetches | |
892 | * data from the FIFO instead of from Host. | |
22adfe0a | 893 | */ |
df64e4d3 | 894 | static void cxgb_pio_copy(u64 __iomem *dst, u64 *src) |
22adfe0a | 895 | { |
df64e4d3 | 896 | int count = 8; |
22adfe0a SR |
897 | |
898 | while (count) { | |
899 | writeq(*src, dst); | |
900 | src++; | |
901 | dst++; | |
902 | count--; | |
903 | } | |
904 | } | |
905 | ||
fd3a4790 | 906 | /** |
a6ec572b | 907 | * cxgb4_ring_tx_db - check and potentially ring a Tx queue's doorbell |
fd3a4790 DM |
908 | * @adap: the adapter |
909 | * @q: the Tx queue | |
910 | * @n: number of new descriptors to give to HW | |
911 | * | |
912 | * Ring the doorbel for a Tx queue. | |
913 | */ | |
a6ec572b | 914 | inline void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) |
fd3a4790 | 915 | { |
1ecc7b7a HS |
916 | /* Make sure that all writes to the TX Descriptors are committed |
917 | * before we tell the hardware about them. | |
918 | */ | |
919 | wmb(); | |
d63a6dcf | 920 | |
df64e4d3 HS |
921 | /* If we don't have access to the new User Doorbell (T5+), use the old |
922 | * doorbell mechanism; otherwise use the new BAR2 mechanism. | |
923 | */ | |
924 | if (unlikely(q->bar2_addr == NULL)) { | |
f612b815 | 925 | u32 val = PIDX_V(n); |
d63a6dcf HS |
926 | unsigned long flags; |
927 | ||
928 | /* For T4 we need to participate in the Doorbell Recovery | |
929 | * mechanism. | |
930 | */ | |
931 | spin_lock_irqsave(&q->db_lock, flags); | |
932 | if (!q->db_disabled) | |
f612b815 HS |
933 | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), |
934 | QID_V(q->cntxt_id) | val); | |
d63a6dcf HS |
935 | else |
936 | q->db_pidx_inc += n; | |
937 | q->db_pidx = q->pidx; | |
938 | spin_unlock_irqrestore(&q->db_lock, flags); | |
939 | } else { | |
f612b815 | 940 | u32 val = PIDX_T5_V(n); |
d63a6dcf HS |
941 | |
942 | /* T4 and later chips share the same PIDX field offset within | |
943 | * the doorbell, but T5 and later shrank the field in order to | |
944 | * gain a bit for Doorbell Priority. The field was absurdly | |
945 | * large in the first place (14 bits) so we just use the T5 | |
946 | * and later limits and warn if a Queue ID is too large. | |
947 | */ | |
f612b815 | 948 | WARN_ON(val & DBPRIO_F); |
d63a6dcf | 949 | |
df64e4d3 HS |
950 | /* If we're only writing a single TX Descriptor and we can use |
951 | * Inferred QID registers, we can use the Write Combining | |
952 | * Gather Buffer; otherwise we use the simple doorbell. | |
d63a6dcf | 953 | */ |
df64e4d3 | 954 | if (n == 1 && q->bar2_qid == 0) { |
d63a6dcf HS |
955 | int index = (q->pidx |
956 | ? (q->pidx - 1) | |
957 | : (q->size - 1)); | |
df64e4d3 | 958 | u64 *wr = (u64 *)&q->desc[index]; |
d63a6dcf | 959 | |
df64e4d3 HS |
960 | cxgb_pio_copy((u64 __iomem *) |
961 | (q->bar2_addr + SGE_UDB_WCDOORBELL), | |
962 | wr); | |
22adfe0a | 963 | } else { |
f612b815 | 964 | writel(val | QID_V(q->bar2_qid), |
df64e4d3 | 965 | q->bar2_addr + SGE_UDB_KDOORBELL); |
22adfe0a | 966 | } |
d63a6dcf HS |
967 | |
968 | /* This Write Memory Barrier will force the write to the User | |
969 | * Doorbell area to be flushed. This is needed to prevent | |
970 | * writes on different CPUs for the same queue from hitting | |
971 | * the adapter out of order. This is required when some Work | |
972 | * Requests take the Write Combine Gather Buffer path (user | |
973 | * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some | |
974 | * take the traditional path where we simply increment the | |
975 | * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the | |
976 | * hardware DMA read the actual Work Request. | |
977 | */ | |
978 | wmb(); | |
979 | } | |
fd3a4790 | 980 | } |
a6ec572b | 981 | EXPORT_SYMBOL(cxgb4_ring_tx_db); |
fd3a4790 DM |
982 | |
983 | /** | |
a6ec572b | 984 | * cxgb4_inline_tx_skb - inline a packet's data into Tx descriptors |
fd3a4790 DM |
985 | * @skb: the packet |
986 | * @q: the Tx queue where the packet will be inlined | |
987 | * @pos: starting position in the Tx queue where to inline the packet | |
988 | * | |
989 | * Inline a packet's contents directly into Tx descriptors, starting at | |
990 | * the given position within the Tx DMA ring. | |
991 | * Most of the complexity of this operation is dealing with wrap arounds | |
992 | * in the middle of the packet we want to inline. | |
993 | */ | |
a6ec572b AG |
994 | void cxgb4_inline_tx_skb(const struct sk_buff *skb, |
995 | const struct sge_txq *q, void *pos) | |
fd3a4790 | 996 | { |
fd3a4790 | 997 | int left = (void *)q->stat - pos; |
e383f248 | 998 | u64 *p; |
fd3a4790 DM |
999 | |
1000 | if (likely(skb->len <= left)) { | |
1001 | if (likely(!skb->data_len)) | |
1002 | skb_copy_from_linear_data(skb, pos, skb->len); | |
1003 | else | |
1004 | skb_copy_bits(skb, 0, pos, skb->len); | |
1005 | pos += skb->len; | |
1006 | } else { | |
1007 | skb_copy_bits(skb, 0, pos, left); | |
1008 | skb_copy_bits(skb, left, q->desc, skb->len - left); | |
1009 | pos = (void *)q->desc + (skb->len - left); | |
1010 | } | |
1011 | ||
1012 | /* 0-pad to multiple of 16 */ | |
1013 | p = PTR_ALIGN(pos, 8); | |
1014 | if ((uintptr_t)p & 8) | |
1015 | *p = 0; | |
1016 | } | |
a6ec572b | 1017 | EXPORT_SYMBOL(cxgb4_inline_tx_skb); |
fd3a4790 | 1018 | |
8d0557d2 HS |
1019 | static void *inline_tx_skb_header(const struct sk_buff *skb, |
1020 | const struct sge_txq *q, void *pos, | |
1021 | int length) | |
1022 | { | |
1023 | u64 *p; | |
1024 | int left = (void *)q->stat - pos; | |
1025 | ||
1026 | if (likely(length <= left)) { | |
1027 | memcpy(pos, skb->data, length); | |
1028 | pos += length; | |
1029 | } else { | |
1030 | memcpy(pos, skb->data, left); | |
1031 | memcpy(q->desc, skb->data + left, length - left); | |
1032 | pos = (void *)q->desc + (length - left); | |
1033 | } | |
1034 | /* 0-pad to multiple of 16 */ | |
1035 | p = PTR_ALIGN(pos, 8); | |
1036 | if ((uintptr_t)p & 8) { | |
1037 | *p = 0; | |
1038 | return p + 1; | |
1039 | } | |
1040 | return p; | |
1041 | } | |
1042 | ||
fd3a4790 DM |
1043 | /* |
1044 | * Figure out what HW csum a packet wants and return the appropriate control | |
1045 | * bits. | |
1046 | */ | |
3ccc6cf7 | 1047 | static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb) |
fd3a4790 DM |
1048 | { |
1049 | int csum_type; | |
c50ae55e GG |
1050 | bool inner_hdr_csum = false; |
1051 | u16 proto, ver; | |
fd3a4790 | 1052 | |
c50ae55e GG |
1053 | if (skb->encapsulation && |
1054 | (CHELSIO_CHIP_VERSION(chip) > CHELSIO_T5)) | |
1055 | inner_hdr_csum = true; | |
1056 | ||
1057 | if (inner_hdr_csum) { | |
1058 | ver = inner_ip_hdr(skb)->version; | |
1059 | proto = (ver == 4) ? inner_ip_hdr(skb)->protocol : | |
1060 | inner_ipv6_hdr(skb)->nexthdr; | |
1061 | } else { | |
1062 | ver = ip_hdr(skb)->version; | |
1063 | proto = (ver == 4) ? ip_hdr(skb)->protocol : | |
1064 | ipv6_hdr(skb)->nexthdr; | |
1065 | } | |
1066 | ||
1067 | if (ver == 4) { | |
1068 | if (proto == IPPROTO_TCP) | |
fd3a4790 | 1069 | csum_type = TX_CSUM_TCPIP; |
c50ae55e | 1070 | else if (proto == IPPROTO_UDP) |
fd3a4790 DM |
1071 | csum_type = TX_CSUM_UDPIP; |
1072 | else { | |
1073 | nocsum: /* | |
1074 | * unknown protocol, disable HW csum | |
1075 | * and hope a bad packet is detected | |
1076 | */ | |
1ecc7b7a | 1077 | return TXPKT_L4CSUM_DIS_F; |
fd3a4790 DM |
1078 | } |
1079 | } else { | |
1080 | /* | |
1081 | * this doesn't work with extension headers | |
1082 | */ | |
c50ae55e | 1083 | if (proto == IPPROTO_TCP) |
fd3a4790 | 1084 | csum_type = TX_CSUM_TCPIP6; |
c50ae55e | 1085 | else if (proto == IPPROTO_UDP) |
fd3a4790 DM |
1086 | csum_type = TX_CSUM_UDPIP6; |
1087 | else | |
1088 | goto nocsum; | |
1089 | } | |
1090 | ||
3ccc6cf7 | 1091 | if (likely(csum_type >= TX_CSUM_TCPIP)) { |
c50ae55e GG |
1092 | int eth_hdr_len, l4_len; |
1093 | u64 hdr_len; | |
1094 | ||
1095 | if (inner_hdr_csum) { | |
1096 | /* This allows checksum offload for all encapsulated | |
1097 | * packets like GRE etc.. | |
1098 | */ | |
1099 | l4_len = skb_inner_network_header_len(skb); | |
1100 | eth_hdr_len = skb_inner_network_offset(skb) - ETH_HLEN; | |
1101 | } else { | |
1102 | l4_len = skb_network_header_len(skb); | |
1103 | eth_hdr_len = skb_network_offset(skb) - ETH_HLEN; | |
1104 | } | |
1105 | hdr_len = TXPKT_IPHDR_LEN_V(l4_len); | |
3ccc6cf7 HS |
1106 | |
1107 | if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) | |
1108 | hdr_len |= TXPKT_ETHHDR_LEN_V(eth_hdr_len); | |
1109 | else | |
1110 | hdr_len |= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len); | |
1111 | return TXPKT_CSUM_TYPE_V(csum_type) | hdr_len; | |
1112 | } else { | |
fd3a4790 DM |
1113 | int start = skb_transport_offset(skb); |
1114 | ||
1ecc7b7a HS |
1115 | return TXPKT_CSUM_TYPE_V(csum_type) | |
1116 | TXPKT_CSUM_START_V(start) | | |
1117 | TXPKT_CSUM_LOC_V(start + skb->csum_offset); | |
fd3a4790 DM |
1118 | } |
1119 | } | |
1120 | ||
1121 | static void eth_txq_stop(struct sge_eth_txq *q) | |
1122 | { | |
1123 | netif_tx_stop_queue(q->txq); | |
1124 | q->q.stops++; | |
1125 | } | |
1126 | ||
1127 | static inline void txq_advance(struct sge_txq *q, unsigned int n) | |
1128 | { | |
1129 | q->in_use += n; | |
1130 | q->pidx += n; | |
1131 | if (q->pidx >= q->size) | |
1132 | q->pidx -= q->size; | |
1133 | } | |
1134 | ||
84a200b3 VP |
1135 | #ifdef CONFIG_CHELSIO_T4_FCOE |
1136 | static inline int | |
1137 | cxgb_fcoe_offload(struct sk_buff *skb, struct adapter *adap, | |
1138 | const struct port_info *pi, u64 *cntrl) | |
1139 | { | |
1140 | const struct cxgb_fcoe *fcoe = &pi->fcoe; | |
1141 | ||
1142 | if (!(fcoe->flags & CXGB_FCOE_ENABLED)) | |
1143 | return 0; | |
1144 | ||
1145 | if (skb->protocol != htons(ETH_P_FCOE)) | |
1146 | return 0; | |
1147 | ||
1148 | skb_reset_mac_header(skb); | |
1149 | skb->mac_len = sizeof(struct ethhdr); | |
1150 | ||
1151 | skb_set_network_header(skb, skb->mac_len); | |
1152 | skb_set_transport_header(skb, skb->mac_len + sizeof(struct fcoe_hdr)); | |
1153 | ||
1154 | if (!cxgb_fcoe_sof_eof_supported(adap, skb)) | |
1155 | return -ENOTSUPP; | |
1156 | ||
1157 | /* FC CRC offload */ | |
1ecc7b7a HS |
1158 | *cntrl = TXPKT_CSUM_TYPE_V(TX_CSUM_FCOE) | |
1159 | TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F | | |
1160 | TXPKT_CSUM_START_V(CXGB_FCOE_TXPKT_CSUM_START) | | |
1161 | TXPKT_CSUM_END_V(CXGB_FCOE_TXPKT_CSUM_END) | | |
1162 | TXPKT_CSUM_LOC_V(CXGB_FCOE_TXPKT_CSUM_END); | |
84a200b3 VP |
1163 | return 0; |
1164 | } | |
1165 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
1166 | ||
d0a1299c GG |
1167 | /* Returns tunnel type if hardware supports offloading of the same. |
1168 | * It is called only for T5 and onwards. | |
1169 | */ | |
1170 | enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb) | |
1171 | { | |
1172 | u8 l4_hdr = 0; | |
1173 | enum cpl_tx_tnl_lso_type tnl_type = TX_TNL_TYPE_OPAQUE; | |
1174 | struct port_info *pi = netdev_priv(skb->dev); | |
1175 | struct adapter *adapter = pi->adapter; | |
1176 | ||
1177 | if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || | |
1178 | skb->inner_protocol != htons(ETH_P_TEB)) | |
1179 | return tnl_type; | |
1180 | ||
1181 | switch (vlan_get_protocol(skb)) { | |
1182 | case htons(ETH_P_IP): | |
1183 | l4_hdr = ip_hdr(skb)->protocol; | |
1184 | break; | |
1185 | case htons(ETH_P_IPV6): | |
1186 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
1187 | break; | |
1188 | default: | |
1189 | return tnl_type; | |
1190 | } | |
1191 | ||
1192 | switch (l4_hdr) { | |
1193 | case IPPROTO_UDP: | |
1194 | if (adapter->vxlan_port == udp_hdr(skb)->dest) | |
1195 | tnl_type = TX_TNL_TYPE_VXLAN; | |
c746fc0e GG |
1196 | else if (adapter->geneve_port == udp_hdr(skb)->dest) |
1197 | tnl_type = TX_TNL_TYPE_GENEVE; | |
d0a1299c GG |
1198 | break; |
1199 | default: | |
1200 | return tnl_type; | |
1201 | } | |
1202 | ||
1203 | return tnl_type; | |
1204 | } | |
1205 | ||
1206 | static inline void t6_fill_tnl_lso(struct sk_buff *skb, | |
1207 | struct cpl_tx_tnl_lso *tnl_lso, | |
1208 | enum cpl_tx_tnl_lso_type tnl_type) | |
1209 | { | |
1210 | u32 val; | |
1211 | int in_eth_xtra_len; | |
1212 | int l3hdr_len = skb_network_header_len(skb); | |
1213 | int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN; | |
1214 | const struct skb_shared_info *ssi = skb_shinfo(skb); | |
1215 | bool v6 = (ip_hdr(skb)->version == 6); | |
1216 | ||
1217 | val = CPL_TX_TNL_LSO_OPCODE_V(CPL_TX_TNL_LSO) | | |
1218 | CPL_TX_TNL_LSO_FIRST_F | | |
1219 | CPL_TX_TNL_LSO_LAST_F | | |
1220 | (v6 ? CPL_TX_TNL_LSO_IPV6OUT_F : 0) | | |
1221 | CPL_TX_TNL_LSO_ETHHDRLENOUT_V(eth_xtra_len / 4) | | |
1222 | CPL_TX_TNL_LSO_IPHDRLENOUT_V(l3hdr_len / 4) | | |
1223 | (v6 ? 0 : CPL_TX_TNL_LSO_IPHDRCHKOUT_F) | | |
1224 | CPL_TX_TNL_LSO_IPLENSETOUT_F | | |
1225 | (v6 ? 0 : CPL_TX_TNL_LSO_IPIDINCOUT_F); | |
1226 | tnl_lso->op_to_IpIdSplitOut = htonl(val); | |
1227 | ||
1228 | tnl_lso->IpIdOffsetOut = 0; | |
1229 | ||
1230 | /* Get the tunnel header length */ | |
1231 | val = skb_inner_mac_header(skb) - skb_mac_header(skb); | |
1232 | in_eth_xtra_len = skb_inner_network_header(skb) - | |
1233 | skb_inner_mac_header(skb) - ETH_HLEN; | |
1234 | ||
1235 | switch (tnl_type) { | |
1236 | case TX_TNL_TYPE_VXLAN: | |
c746fc0e | 1237 | case TX_TNL_TYPE_GENEVE: |
d0a1299c GG |
1238 | tnl_lso->UdpLenSetOut_to_TnlHdrLen = |
1239 | htons(CPL_TX_TNL_LSO_UDPCHKCLROUT_F | | |
1240 | CPL_TX_TNL_LSO_UDPLENSETOUT_F); | |
1241 | break; | |
1242 | default: | |
1243 | tnl_lso->UdpLenSetOut_to_TnlHdrLen = 0; | |
1244 | break; | |
1245 | } | |
1246 | ||
1247 | tnl_lso->UdpLenSetOut_to_TnlHdrLen |= | |
1248 | htons(CPL_TX_TNL_LSO_TNLHDRLEN_V(val) | | |
1249 | CPL_TX_TNL_LSO_TNLTYPE_V(tnl_type)); | |
1250 | ||
1251 | tnl_lso->r1 = 0; | |
1252 | ||
1253 | val = CPL_TX_TNL_LSO_ETHHDRLEN_V(in_eth_xtra_len / 4) | | |
1254 | CPL_TX_TNL_LSO_IPV6_V(inner_ip_hdr(skb)->version == 6) | | |
1255 | CPL_TX_TNL_LSO_IPHDRLEN_V(skb_inner_network_header_len(skb) / 4) | | |
1256 | CPL_TX_TNL_LSO_TCPHDRLEN_V(inner_tcp_hdrlen(skb) / 4); | |
1257 | tnl_lso->Flow_to_TcpHdrLen = htonl(val); | |
1258 | ||
1259 | tnl_lso->IpIdOffset = htons(0); | |
1260 | ||
1261 | tnl_lso->IpIdSplit_to_Mss = htons(CPL_TX_TNL_LSO_MSS_V(ssi->gso_size)); | |
1262 | tnl_lso->TCPSeqOffset = htonl(0); | |
1263 | tnl_lso->EthLenOffset_Size = htonl(CPL_TX_TNL_LSO_SIZE_V(skb->len)); | |
1264 | } | |
1265 | ||
4846d533 RL |
1266 | static inline void *write_tso_wr(struct adapter *adap, struct sk_buff *skb, |
1267 | struct cpl_tx_pkt_lso_core *lso) | |
1268 | { | |
1269 | int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN; | |
1270 | int l3hdr_len = skb_network_header_len(skb); | |
1271 | const struct skb_shared_info *ssi; | |
1272 | bool ipv6 = false; | |
1273 | ||
1274 | ssi = skb_shinfo(skb); | |
1275 | if (ssi->gso_type & SKB_GSO_TCPV6) | |
1276 | ipv6 = true; | |
1277 | ||
1278 | lso->lso_ctrl = htonl(LSO_OPCODE_V(CPL_TX_PKT_LSO) | | |
1279 | LSO_FIRST_SLICE_F | LSO_LAST_SLICE_F | | |
1280 | LSO_IPV6_V(ipv6) | | |
1281 | LSO_ETHHDR_LEN_V(eth_xtra_len / 4) | | |
1282 | LSO_IPHDR_LEN_V(l3hdr_len / 4) | | |
1283 | LSO_TCPHDR_LEN_V(tcp_hdr(skb)->doff)); | |
1284 | lso->ipid_ofst = htons(0); | |
1285 | lso->mss = htons(ssi->gso_size); | |
1286 | lso->seqno_offset = htonl(0); | |
1287 | if (is_t4(adap->params.chip)) | |
1288 | lso->len = htonl(skb->len); | |
1289 | else | |
1290 | lso->len = htonl(LSO_T5_XFER_SIZE_V(skb->len)); | |
1291 | ||
1292 | return (void *)(lso + 1); | |
1293 | } | |
1294 | ||
d429005f VK |
1295 | /** |
1296 | * t4_sge_eth_txq_egress_update - handle Ethernet TX Queue update | |
1297 | * @adap: the adapter | |
1298 | * @eq: the Ethernet TX Queue | |
1299 | * @maxreclaim: the maximum number of TX Descriptors to reclaim or -1 | |
1300 | * | |
1301 | * We're typically called here to update the state of an Ethernet TX | |
1302 | * Queue with respect to the hardware's progress in consuming the TX | |
1303 | * Work Requests that we've put on that Egress Queue. This happens | |
1304 | * when we get Egress Queue Update messages and also prophylactically | |
1305 | * in regular timer-based Ethernet TX Queue maintenance. | |
1306 | */ | |
1307 | int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *eq, | |
1308 | int maxreclaim) | |
1309 | { | |
f1f20a86 | 1310 | unsigned int reclaimed, hw_cidx; |
d429005f | 1311 | struct sge_txq *q = &eq->q; |
f1f20a86 | 1312 | int hw_in_use; |
d429005f VK |
1313 | |
1314 | if (!q->in_use || !__netif_tx_trylock(eq->txq)) | |
1315 | return 0; | |
1316 | ||
1317 | /* Reclaim pending completed TX Descriptors. */ | |
1318 | reclaimed = reclaim_completed_tx(adap, &eq->q, maxreclaim, true); | |
1319 | ||
f1f20a86 RL |
1320 | hw_cidx = ntohs(READ_ONCE(q->stat->cidx)); |
1321 | hw_in_use = q->pidx - hw_cidx; | |
1322 | if (hw_in_use < 0) | |
1323 | hw_in_use += q->size; | |
1324 | ||
d429005f VK |
1325 | /* If the TX Queue is currently stopped and there's now more than half |
1326 | * the queue available, restart it. Otherwise bail out since the rest | |
1327 | * of what we want do here is with the possibility of shipping any | |
1328 | * currently buffered Coalesced TX Work Request. | |
1329 | */ | |
f1f20a86 | 1330 | if (netif_tx_queue_stopped(eq->txq) && hw_in_use < (q->size / 2)) { |
d429005f VK |
1331 | netif_tx_wake_queue(eq->txq); |
1332 | eq->q.restarts++; | |
1333 | } | |
1334 | ||
1335 | __netif_tx_unlock(eq->txq); | |
1336 | return reclaimed; | |
1337 | } | |
1338 | ||
b1396c2b RL |
1339 | static inline int cxgb4_validate_skb(struct sk_buff *skb, |
1340 | struct net_device *dev, | |
1341 | u32 min_pkt_len) | |
1342 | { | |
1343 | u32 max_pkt_len; | |
1344 | ||
1345 | /* The chip min packet length is 10 octets but some firmware | |
1346 | * commands have a minimum packet length requirement. So, play | |
1347 | * safe and reject anything shorter than @min_pkt_len. | |
1348 | */ | |
1349 | if (unlikely(skb->len < min_pkt_len)) | |
1350 | return -EINVAL; | |
1351 | ||
1352 | /* Discard the packet if the length is greater than mtu */ | |
1353 | max_pkt_len = ETH_HLEN + dev->mtu; | |
1354 | ||
1355 | if (skb_vlan_tagged(skb)) | |
1356 | max_pkt_len += VLAN_HLEN; | |
1357 | ||
1358 | if (!skb_shinfo(skb)->gso_size && (unlikely(skb->len > max_pkt_len))) | |
1359 | return -EINVAL; | |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
1a2a14fb RL |
1364 | static void *write_eo_udp_wr(struct sk_buff *skb, struct fw_eth_tx_eo_wr *wr, |
1365 | u32 hdr_len) | |
1366 | { | |
1367 | wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG; | |
1368 | wr->u.udpseg.ethlen = skb_network_offset(skb); | |
1369 | wr->u.udpseg.iplen = cpu_to_be16(skb_network_header_len(skb)); | |
1370 | wr->u.udpseg.udplen = sizeof(struct udphdr); | |
1371 | wr->u.udpseg.rtplen = 0; | |
1372 | wr->u.udpseg.r4 = 0; | |
1373 | if (skb_shinfo(skb)->gso_size) | |
1374 | wr->u.udpseg.mss = cpu_to_be16(skb_shinfo(skb)->gso_size); | |
1375 | else | |
1376 | wr->u.udpseg.mss = cpu_to_be16(skb->len - hdr_len); | |
1377 | wr->u.udpseg.schedpktsize = wr->u.udpseg.mss; | |
1378 | wr->u.udpseg.plen = cpu_to_be32(skb->len - hdr_len); | |
1379 | ||
1380 | return (void *)(wr + 1); | |
1381 | } | |
1382 | ||
fd3a4790 | 1383 | /** |
d5fbda61 | 1384 | * cxgb4_eth_xmit - add a packet to an Ethernet Tx queue |
fd3a4790 DM |
1385 | * @skb: the packet |
1386 | * @dev: the egress net device | |
1387 | * | |
1388 | * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled. | |
1389 | */ | |
d5fbda61 | 1390 | static netdev_tx_t cxgb4_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
fd3a4790 | 1391 | { |
b1396c2b RL |
1392 | enum cpl_tx_tnl_lso_type tnl_type = TX_TNL_TYPE_OPAQUE; |
1393 | bool ptp_enabled = is_ptp_enabled(skb, dev); | |
0ed96b46 | 1394 | unsigned int last_desc, flits, ndesc; |
1a2a14fb | 1395 | u32 wr_mid, ctrl0, op, sgl_off = 0; |
b1396c2b | 1396 | const struct skb_shared_info *ssi; |
1a2a14fb | 1397 | int len, qidx, credits, ret, left; |
0ed96b46 | 1398 | struct tx_sw_desc *sgl_sdesc; |
1a2a14fb | 1399 | struct fw_eth_tx_eo_wr *eowr; |
fd3a4790 DM |
1400 | struct fw_eth_tx_pkt_wr *wr; |
1401 | struct cpl_tx_pkt_core *cpl; | |
b1396c2b | 1402 | const struct port_info *pi; |
0034b298 | 1403 | bool immediate = false; |
b1396c2b RL |
1404 | u64 cntrl, *end, *sgl; |
1405 | struct sge_eth_txq *q; | |
d0a1299c | 1406 | unsigned int chip_ver; |
b1396c2b | 1407 | struct adapter *adap; |
fd3a4790 | 1408 | |
b1396c2b RL |
1409 | ret = cxgb4_validate_skb(skb, dev, ETH_HLEN); |
1410 | if (ret) | |
637d3e99 HS |
1411 | goto out_free; |
1412 | ||
fd3a4790 DM |
1413 | pi = netdev_priv(dev); |
1414 | adap = pi->adapter; | |
a6ec572b AG |
1415 | ssi = skb_shinfo(skb); |
1416 | #ifdef CONFIG_CHELSIO_IPSEC_INLINE | |
1417 | if (xfrm_offload(skb) && !ssi->gso_size) | |
1418 | return adap->uld[CXGB4_ULD_CRYPTO].tx_handler(skb, dev); | |
1419 | #endif /* CHELSIO_IPSEC_INLINE */ | |
1420 | ||
5a4b9fe7 RM |
1421 | #ifdef CONFIG_CHELSIO_TLS_DEVICE |
1422 | if (skb->decrypted) | |
1423 | return adap->uld[CXGB4_ULD_CRYPTO].tx_handler(skb, dev); | |
1424 | #endif /* CHELSIO_TLS_DEVICE */ | |
1425 | ||
fd3a4790 | 1426 | qidx = skb_get_queue_mapping(skb); |
a4569504 AG |
1427 | if (ptp_enabled) { |
1428 | spin_lock(&adap->ptp_lock); | |
1429 | if (!(adap->ptp_tx_skb)) { | |
1430 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
1431 | adap->ptp_tx_skb = skb_get(skb); | |
1432 | } else { | |
1433 | spin_unlock(&adap->ptp_lock); | |
1434 | goto out_free; | |
1435 | } | |
1436 | q = &adap->sge.ptptxq; | |
1437 | } else { | |
1438 | q = &adap->sge.ethtxq[qidx + pi->first_qset]; | |
1439 | } | |
1440 | skb_tx_timestamp(skb); | |
fd3a4790 | 1441 | |
d429005f | 1442 | reclaim_completed_tx(adap, &q->q, -1, true); |
1ecc7b7a | 1443 | cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F; |
84a200b3 VP |
1444 | |
1445 | #ifdef CONFIG_CHELSIO_T4_FCOE | |
b1396c2b RL |
1446 | ret = cxgb_fcoe_offload(skb, adap, pi, &cntrl); |
1447 | if (unlikely(ret == -ENOTSUPP)) { | |
a4569504 AG |
1448 | if (ptp_enabled) |
1449 | spin_unlock(&adap->ptp_lock); | |
84a200b3 | 1450 | goto out_free; |
a4569504 | 1451 | } |
84a200b3 | 1452 | #endif /* CONFIG_CHELSIO_T4_FCOE */ |
fd3a4790 | 1453 | |
d0a1299c GG |
1454 | chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); |
1455 | flits = calc_tx_flits(skb, chip_ver); | |
fd3a4790 DM |
1456 | ndesc = flits_to_desc(flits); |
1457 | credits = txq_avail(&q->q) - ndesc; | |
1458 | ||
1459 | if (unlikely(credits < 0)) { | |
1460 | eth_txq_stop(q); | |
1461 | dev_err(adap->pdev_dev, | |
1462 | "%s: Tx ring %u full while queue awake!\n", | |
1463 | dev->name, qidx); | |
a4569504 AG |
1464 | if (ptp_enabled) |
1465 | spin_unlock(&adap->ptp_lock); | |
fd3a4790 DM |
1466 | return NETDEV_TX_BUSY; |
1467 | } | |
1468 | ||
d0a1299c | 1469 | if (is_eth_imm(skb, chip_ver)) |
0034b298 KS |
1470 | immediate = true; |
1471 | ||
d0a1299c GG |
1472 | if (skb->encapsulation && chip_ver > CHELSIO_T5) |
1473 | tnl_type = cxgb_encap_offload_supported(skb); | |
1474 | ||
0ed96b46 RL |
1475 | last_desc = q->q.pidx + ndesc - 1; |
1476 | if (last_desc >= q->q.size) | |
1477 | last_desc -= q->q.size; | |
1478 | sgl_sdesc = &q->q.sdesc[last_desc]; | |
1479 | ||
0034b298 | 1480 | if (!immediate && |
0ed96b46 RL |
1481 | unlikely(cxgb4_map_skb(adap->pdev_dev, skb, sgl_sdesc->addr) < 0)) { |
1482 | memset(sgl_sdesc->addr, 0, sizeof(sgl_sdesc->addr)); | |
fd3a4790 | 1483 | q->mapping_err++; |
a4569504 AG |
1484 | if (ptp_enabled) |
1485 | spin_unlock(&adap->ptp_lock); | |
fd3a4790 DM |
1486 | goto out_free; |
1487 | } | |
1488 | ||
e2ac9628 | 1489 | wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2)); |
fd3a4790 | 1490 | if (unlikely(credits < ETHTXQ_STOP_THRES)) { |
d429005f VK |
1491 | /* After we're done injecting the Work Request for this |
1492 | * packet, we'll be below our "stop threshold" so stop the TX | |
1493 | * Queue now and schedule a request for an SGE Egress Queue | |
1494 | * Update message. The queue will get started later on when | |
1495 | * the firmware processes this Work Request and sends us an | |
1496 | * Egress Queue Status Update message indicating that space | |
1497 | * has opened up. | |
1498 | */ | |
fd3a4790 | 1499 | eth_txq_stop(q); |
7affd808 | 1500 | wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F; |
fd3a4790 DM |
1501 | } |
1502 | ||
1503 | wr = (void *)&q->q.desc[q->q.pidx]; | |
1a2a14fb | 1504 | eowr = (void *)&q->q.desc[q->q.pidx]; |
fd3a4790 DM |
1505 | wr->equiq_to_len16 = htonl(wr_mid); |
1506 | wr->r3 = cpu_to_be64(0); | |
1a2a14fb RL |
1507 | if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) |
1508 | end = (u64 *)eowr + flits; | |
1509 | else | |
1510 | end = (u64 *)wr + flits; | |
fd3a4790 | 1511 | |
0034b298 | 1512 | len = immediate ? skb->len : 0; |
a6076fcd | 1513 | len += sizeof(*cpl); |
1a2a14fb | 1514 | if (ssi->gso_size && !(ssi->gso_type & SKB_GSO_UDP_L4)) { |
a6076fcd | 1515 | struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); |
d0a1299c | 1516 | struct cpl_tx_tnl_lso *tnl_lso = (void *)(wr + 1); |
fd3a4790 | 1517 | |
d0a1299c GG |
1518 | if (tnl_type) |
1519 | len += sizeof(*tnl_lso); | |
7207c0d1 | 1520 | else |
d0a1299c | 1521 | len += sizeof(*lso); |
3ccc6cf7 | 1522 | |
d0a1299c GG |
1523 | wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) | |
1524 | FW_WR_IMMDLEN_V(len)); | |
1525 | if (tnl_type) { | |
1526 | struct iphdr *iph = ip_hdr(skb); | |
3ccc6cf7 | 1527 | |
d0a1299c GG |
1528 | t6_fill_tnl_lso(skb, tnl_lso, tnl_type); |
1529 | cpl = (void *)(tnl_lso + 1); | |
1530 | /* Driver is expected to compute partial checksum that | |
1531 | * does not include the IP Total Length. | |
1532 | */ | |
1533 | if (iph->version == 4) { | |
1534 | iph->check = 0; | |
1535 | iph->tot_len = 0; | |
1536 | iph->check = (u16)(~ip_fast_csum((u8 *)iph, | |
1537 | iph->ihl)); | |
1538 | } | |
1539 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
1540 | cntrl = hwcsum(adap->params.chip, skb); | |
1541 | } else { | |
4846d533 RL |
1542 | cpl = write_tso_wr(adap, skb, lso); |
1543 | cntrl = hwcsum(adap->params.chip, skb); | |
d0a1299c | 1544 | } |
c50ae55e | 1545 | sgl = (u64 *)(cpl + 1); /* sgl start here */ |
fd3a4790 DM |
1546 | q->tso++; |
1547 | q->tx_cso += ssi->gso_segs; | |
1a2a14fb RL |
1548 | } else if (ssi->gso_size) { |
1549 | u64 *start; | |
1550 | u32 hdrlen; | |
1551 | ||
1552 | hdrlen = eth_get_headlen(dev, skb->data, skb_headlen(skb)); | |
1553 | len += hdrlen; | |
1554 | wr->op_immdlen = cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_EO_WR) | | |
1555 | FW_ETH_TX_EO_WR_IMMDLEN_V(len)); | |
1556 | cpl = write_eo_udp_wr(skb, eowr, hdrlen); | |
1557 | cntrl = hwcsum(adap->params.chip, skb); | |
1558 | ||
1559 | start = (u64 *)(cpl + 1); | |
1560 | sgl = (u64 *)inline_tx_skb_header(skb, &q->q, (void *)start, | |
1561 | hdrlen); | |
1562 | if (unlikely(start > sgl)) { | |
1563 | left = (u8 *)end - (u8 *)q->q.stat; | |
1564 | end = (void *)q->q.desc + left; | |
1565 | } | |
1566 | sgl_off = hdrlen; | |
1567 | q->uso++; | |
1568 | q->tx_cso += ssi->gso_segs; | |
fd3a4790 | 1569 | } else { |
a4569504 AG |
1570 | if (ptp_enabled) |
1571 | op = FW_PTP_TX_PKT_WR; | |
1572 | else | |
1573 | op = FW_ETH_TX_PKT_WR; | |
1574 | wr->op_immdlen = htonl(FW_WR_OP_V(op) | | |
e2ac9628 | 1575 | FW_WR_IMMDLEN_V(len)); |
fd3a4790 | 1576 | cpl = (void *)(wr + 1); |
c50ae55e | 1577 | sgl = (u64 *)(cpl + 1); |
fd3a4790 | 1578 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
3ccc6cf7 HS |
1579 | cntrl = hwcsum(adap->params.chip, skb) | |
1580 | TXPKT_IPCSUM_DIS_F; | |
fd3a4790 | 1581 | q->tx_cso++; |
84a200b3 | 1582 | } |
fd3a4790 DM |
1583 | } |
1584 | ||
1a2a14fb RL |
1585 | if (unlikely((u8 *)sgl >= (u8 *)q->q.stat)) { |
1586 | /* If current position is already at the end of the | |
1587 | * txq, reset the current to point to start of the queue | |
1588 | * and update the end ptr as well. | |
1589 | */ | |
1590 | left = (u8 *)end - (u8 *)q->q.stat; | |
1591 | end = (void *)q->q.desc + left; | |
1592 | sgl = (void *)q->q.desc; | |
1593 | } | |
1594 | ||
df8a39de | 1595 | if (skb_vlan_tag_present(skb)) { |
fd3a4790 | 1596 | q->vlan_ins++; |
1ecc7b7a | 1597 | cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb)); |
84a200b3 VP |
1598 | #ifdef CONFIG_CHELSIO_T4_FCOE |
1599 | if (skb->protocol == htons(ETH_P_FCOE)) | |
1ecc7b7a | 1600 | cntrl |= TXPKT_VLAN_V( |
84a200b3 VP |
1601 | ((skb->priority & 0x7) << VLAN_PRIO_SHIFT)); |
1602 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
fd3a4790 DM |
1603 | } |
1604 | ||
397665da AB |
1605 | ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) | |
1606 | TXPKT_PF_V(adap->pf); | |
a4569504 AG |
1607 | if (ptp_enabled) |
1608 | ctrl0 |= TXPKT_TSTAMP_F; | |
397665da AB |
1609 | #ifdef CONFIG_CHELSIO_T4_DCB |
1610 | if (is_t4(adap->params.chip)) | |
1611 | ctrl0 |= TXPKT_OVLAN_IDX_V(q->dcb_prio); | |
1612 | else | |
1613 | ctrl0 |= TXPKT_T5_OVLAN_IDX_V(q->dcb_prio); | |
1614 | #endif | |
1615 | cpl->ctrl0 = htonl(ctrl0); | |
fd3a4790 DM |
1616 | cpl->pack = htons(0); |
1617 | cpl->len = htons(skb->len); | |
1618 | cpl->ctrl1 = cpu_to_be64(cntrl); | |
1619 | ||
0034b298 | 1620 | if (immediate) { |
c50ae55e | 1621 | cxgb4_inline_tx_skb(skb, &q->q, sgl); |
a7525198 | 1622 | dev_consume_skb_any(skb); |
fd3a4790 | 1623 | } else { |
1a2a14fb | 1624 | cxgb4_write_sgl(skb, &q->q, (void *)sgl, end, sgl_off, |
0ed96b46 | 1625 | sgl_sdesc->addr); |
fd3a4790 | 1626 | skb_orphan(skb); |
0ed96b46 | 1627 | sgl_sdesc->skb = skb; |
fd3a4790 DM |
1628 | } |
1629 | ||
1630 | txq_advance(&q->q, ndesc); | |
1631 | ||
a6ec572b | 1632 | cxgb4_ring_tx_db(adap, &q->q, ndesc); |
a4569504 AG |
1633 | if (ptp_enabled) |
1634 | spin_unlock(&adap->ptp_lock); | |
fd3a4790 | 1635 | return NETDEV_TX_OK; |
b1396c2b RL |
1636 | |
1637 | out_free: | |
1638 | dev_kfree_skb_any(skb); | |
1639 | return NETDEV_TX_OK; | |
fd3a4790 DM |
1640 | } |
1641 | ||
d5fbda61 AV |
1642 | /* Constants ... */ |
1643 | enum { | |
1644 | /* Egress Queue sizes, producer and consumer indices are all in units | |
1645 | * of Egress Context Units bytes. Note that as far as the hardware is | |
1646 | * concerned, the free list is an Egress Queue (the host produces free | |
1647 | * buffers which the hardware consumes) and free list entries are | |
1648 | * 64-bit PCI DMA addresses. | |
1649 | */ | |
1650 | EQ_UNIT = SGE_EQ_IDXSIZE, | |
1651 | FL_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64), | |
1652 | TXD_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64), | |
1653 | ||
1654 | T4VF_ETHTXQ_MAX_HDR = (sizeof(struct fw_eth_tx_pkt_vm_wr) + | |
1655 | sizeof(struct cpl_tx_pkt_lso_core) + | |
1656 | sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64), | |
1657 | }; | |
1658 | ||
1659 | /** | |
1660 | * t4vf_is_eth_imm - can an Ethernet packet be sent as immediate data? | |
1661 | * @skb: the packet | |
1662 | * | |
1663 | * Returns whether an Ethernet packet is small enough to fit completely as | |
1664 | * immediate data. | |
1665 | */ | |
1666 | static inline int t4vf_is_eth_imm(const struct sk_buff *skb) | |
1667 | { | |
1668 | /* The VF Driver uses the FW_ETH_TX_PKT_VM_WR firmware Work Request | |
1669 | * which does not accommodate immediate data. We could dike out all | |
1670 | * of the support code for immediate data but that would tie our hands | |
1671 | * too much if we ever want to enhace the firmware. It would also | |
1672 | * create more differences between the PF and VF Drivers. | |
1673 | */ | |
1674 | return false; | |
1675 | } | |
1676 | ||
1677 | /** | |
1678 | * t4vf_calc_tx_flits - calculate the number of flits for a packet TX WR | |
1679 | * @skb: the packet | |
1680 | * | |
1681 | * Returns the number of flits needed for a TX Work Request for the | |
1682 | * given Ethernet packet, including the needed WR and CPL headers. | |
1683 | */ | |
1684 | static inline unsigned int t4vf_calc_tx_flits(const struct sk_buff *skb) | |
1685 | { | |
1686 | unsigned int flits; | |
1687 | ||
1688 | /* If the skb is small enough, we can pump it out as a work request | |
1689 | * with only immediate data. In that case we just have to have the | |
1690 | * TX Packet header plus the skb data in the Work Request. | |
1691 | */ | |
1692 | if (t4vf_is_eth_imm(skb)) | |
1693 | return DIV_ROUND_UP(skb->len + sizeof(struct cpl_tx_pkt), | |
1694 | sizeof(__be64)); | |
1695 | ||
1696 | /* Otherwise, we're going to have to construct a Scatter gather list | |
1697 | * of the skb body and fragments. We also include the flits necessary | |
1698 | * for the TX Packet Work Request and CPL. We always have a firmware | |
1699 | * Write Header (incorporated as part of the cpl_tx_pkt_lso and | |
1700 | * cpl_tx_pkt structures), followed by either a TX Packet Write CPL | |
1701 | * message or, if we're doing a Large Send Offload, an LSO CPL message | |
1702 | * with an embedded TX Packet Write CPL message. | |
1703 | */ | |
1704 | flits = sgl_len(skb_shinfo(skb)->nr_frags + 1); | |
1705 | if (skb_shinfo(skb)->gso_size) | |
1706 | flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) + | |
1707 | sizeof(struct cpl_tx_pkt_lso_core) + | |
1708 | sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64); | |
1709 | else | |
1710 | flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) + | |
1711 | sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64); | |
1712 | return flits; | |
1713 | } | |
1714 | ||
1715 | /** | |
1716 | * cxgb4_vf_eth_xmit - add a packet to an Ethernet TX queue | |
1717 | * @skb: the packet | |
1718 | * @dev: the egress net device | |
1719 | * | |
1720 | * Add a packet to an SGE Ethernet TX queue. Runs with softirqs disabled. | |
1721 | */ | |
1722 | static netdev_tx_t cxgb4_vf_eth_xmit(struct sk_buff *skb, | |
1723 | struct net_device *dev) | |
1724 | { | |
0ed96b46 | 1725 | unsigned int last_desc, flits, ndesc; |
d5fbda61 AV |
1726 | const struct skb_shared_info *ssi; |
1727 | struct fw_eth_tx_pkt_vm_wr *wr; | |
0ed96b46 | 1728 | struct tx_sw_desc *sgl_sdesc; |
d5fbda61 AV |
1729 | struct cpl_tx_pkt_core *cpl; |
1730 | const struct port_info *pi; | |
d5fbda61 AV |
1731 | struct sge_eth_txq *txq; |
1732 | struct adapter *adapter; | |
b1396c2b RL |
1733 | int qidx, credits, ret; |
1734 | size_t fw_hdr_copy_len; | |
d5fbda61 AV |
1735 | u64 cntrl, *end; |
1736 | u32 wr_mid; | |
d5fbda61 AV |
1737 | |
1738 | /* The chip minimum packet length is 10 octets but the firmware | |
1739 | * command that we are using requires that we copy the Ethernet header | |
1740 | * (including the VLAN tag) into the header so we reject anything | |
1741 | * smaller than that ... | |
1742 | */ | |
b1396c2b RL |
1743 | fw_hdr_copy_len = sizeof(wr->ethmacdst) + sizeof(wr->ethmacsrc) + |
1744 | sizeof(wr->ethtype) + sizeof(wr->vlantci); | |
1745 | ret = cxgb4_validate_skb(skb, dev, fw_hdr_copy_len); | |
1746 | if (ret) | |
d5fbda61 AV |
1747 | goto out_free; |
1748 | ||
1749 | /* Figure out which TX Queue we're going to use. */ | |
1750 | pi = netdev_priv(dev); | |
1751 | adapter = pi->adapter; | |
1752 | qidx = skb_get_queue_mapping(skb); | |
1753 | WARN_ON(qidx >= pi->nqsets); | |
1754 | txq = &adapter->sge.ethtxq[pi->first_qset + qidx]; | |
1755 | ||
1756 | /* Take this opportunity to reclaim any TX Descriptors whose DMA | |
1757 | * transfers have completed. | |
1758 | */ | |
d429005f | 1759 | reclaim_completed_tx(adapter, &txq->q, -1, true); |
d5fbda61 AV |
1760 | |
1761 | /* Calculate the number of flits and TX Descriptors we're going to | |
1762 | * need along with how many TX Descriptors will be left over after | |
1763 | * we inject our Work Request. | |
1764 | */ | |
1765 | flits = t4vf_calc_tx_flits(skb); | |
1766 | ndesc = flits_to_desc(flits); | |
1767 | credits = txq_avail(&txq->q) - ndesc; | |
1768 | ||
1769 | if (unlikely(credits < 0)) { | |
1770 | /* Not enough room for this packet's Work Request. Stop the | |
1771 | * TX Queue and return a "busy" condition. The queue will get | |
1772 | * started later on when the firmware informs us that space | |
1773 | * has opened up. | |
1774 | */ | |
1775 | eth_txq_stop(txq); | |
1776 | dev_err(adapter->pdev_dev, | |
1777 | "%s: TX ring %u full while queue awake!\n", | |
1778 | dev->name, qidx); | |
1779 | return NETDEV_TX_BUSY; | |
1780 | } | |
1781 | ||
0ed96b46 RL |
1782 | last_desc = txq->q.pidx + ndesc - 1; |
1783 | if (last_desc >= txq->q.size) | |
1784 | last_desc -= txq->q.size; | |
1785 | sgl_sdesc = &txq->q.sdesc[last_desc]; | |
1786 | ||
d5fbda61 | 1787 | if (!t4vf_is_eth_imm(skb) && |
0ed96b46 RL |
1788 | unlikely(cxgb4_map_skb(adapter->pdev_dev, skb, |
1789 | sgl_sdesc->addr) < 0)) { | |
d5fbda61 AV |
1790 | /* We need to map the skb into PCI DMA space (because it can't |
1791 | * be in-lined directly into the Work Request) and the mapping | |
1792 | * operation failed. Record the error and drop the packet. | |
1793 | */ | |
0ed96b46 | 1794 | memset(sgl_sdesc->addr, 0, sizeof(sgl_sdesc->addr)); |
d5fbda61 AV |
1795 | txq->mapping_err++; |
1796 | goto out_free; | |
1797 | } | |
1798 | ||
1799 | wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2)); | |
1800 | if (unlikely(credits < ETHTXQ_STOP_THRES)) { | |
1801 | /* After we're done injecting the Work Request for this | |
1802 | * packet, we'll be below our "stop threshold" so stop the TX | |
1803 | * Queue now and schedule a request for an SGE Egress Queue | |
1804 | * Update message. The queue will get started later on when | |
1805 | * the firmware processes this Work Request and sends us an | |
1806 | * Egress Queue Status Update message indicating that space | |
1807 | * has opened up. | |
1808 | */ | |
1809 | eth_txq_stop(txq); | |
7affd808 | 1810 | wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F; |
d5fbda61 AV |
1811 | } |
1812 | ||
1813 | /* Start filling in our Work Request. Note that we do _not_ handle | |
1814 | * the WR Header wrapping around the TX Descriptor Ring. If our | |
1815 | * maximum header size ever exceeds one TX Descriptor, we'll need to | |
1816 | * do something else here. | |
1817 | */ | |
1818 | WARN_ON(DIV_ROUND_UP(T4VF_ETHTXQ_MAX_HDR, TXD_PER_EQ_UNIT) > 1); | |
1819 | wr = (void *)&txq->q.desc[txq->q.pidx]; | |
1820 | wr->equiq_to_len16 = cpu_to_be32(wr_mid); | |
1821 | wr->r3[0] = cpu_to_be32(0); | |
1822 | wr->r3[1] = cpu_to_be32(0); | |
1823 | skb_copy_from_linear_data(skb, (void *)wr->ethmacdst, fw_hdr_copy_len); | |
1824 | end = (u64 *)wr + flits; | |
1825 | ||
1826 | /* If this is a Large Send Offload packet we'll put in an LSO CPL | |
1827 | * message with an encapsulated TX Packet CPL message. Otherwise we | |
1828 | * just use a TX Packet CPL message. | |
1829 | */ | |
1830 | ssi = skb_shinfo(skb); | |
1831 | if (ssi->gso_size) { | |
1832 | struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); | |
1833 | bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0; | |
1834 | int l3hdr_len = skb_network_header_len(skb); | |
1835 | int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN; | |
1836 | ||
1837 | wr->op_immdlen = | |
1838 | cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_PKT_VM_WR) | | |
1839 | FW_WR_IMMDLEN_V(sizeof(*lso) + | |
1840 | sizeof(*cpl))); | |
1841 | /* Fill in the LSO CPL message. */ | |
1842 | lso->lso_ctrl = | |
1843 | cpu_to_be32(LSO_OPCODE_V(CPL_TX_PKT_LSO) | | |
1844 | LSO_FIRST_SLICE_F | | |
1845 | LSO_LAST_SLICE_F | | |
1846 | LSO_IPV6_V(v6) | | |
1847 | LSO_ETHHDR_LEN_V(eth_xtra_len / 4) | | |
1848 | LSO_IPHDR_LEN_V(l3hdr_len / 4) | | |
1849 | LSO_TCPHDR_LEN_V(tcp_hdr(skb)->doff)); | |
1850 | lso->ipid_ofst = cpu_to_be16(0); | |
1851 | lso->mss = cpu_to_be16(ssi->gso_size); | |
1852 | lso->seqno_offset = cpu_to_be32(0); | |
1853 | if (is_t4(adapter->params.chip)) | |
1854 | lso->len = cpu_to_be32(skb->len); | |
1855 | else | |
1856 | lso->len = cpu_to_be32(LSO_T5_XFER_SIZE_V(skb->len)); | |
1857 | ||
1858 | /* Set up TX Packet CPL pointer, control word and perform | |
1859 | * accounting. | |
1860 | */ | |
1861 | cpl = (void *)(lso + 1); | |
1862 | ||
1863 | if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) | |
1864 | cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len); | |
1865 | else | |
1866 | cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len); | |
1867 | ||
1868 | cntrl |= TXPKT_CSUM_TYPE_V(v6 ? | |
1869 | TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) | | |
1870 | TXPKT_IPHDR_LEN_V(l3hdr_len); | |
1871 | txq->tso++; | |
1872 | txq->tx_cso += ssi->gso_segs; | |
1873 | } else { | |
1874 | int len; | |
1875 | ||
1876 | len = (t4vf_is_eth_imm(skb) | |
1877 | ? skb->len + sizeof(*cpl) | |
1878 | : sizeof(*cpl)); | |
1879 | wr->op_immdlen = | |
1880 | cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_PKT_VM_WR) | | |
1881 | FW_WR_IMMDLEN_V(len)); | |
1882 | ||
1883 | /* Set up TX Packet CPL pointer, control word and perform | |
1884 | * accounting. | |
1885 | */ | |
1886 | cpl = (void *)(wr + 1); | |
1887 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1888 | cntrl = hwcsum(adapter->params.chip, skb) | | |
1889 | TXPKT_IPCSUM_DIS_F; | |
1890 | txq->tx_cso++; | |
1891 | } else { | |
1892 | cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F; | |
1893 | } | |
1894 | } | |
1895 | ||
1896 | /* If there's a VLAN tag present, add that to the list of things to | |
1897 | * do in this Work Request. | |
1898 | */ | |
1899 | if (skb_vlan_tag_present(skb)) { | |
1900 | txq->vlan_ins++; | |
1901 | cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb)); | |
1902 | } | |
1903 | ||
1904 | /* Fill in the TX Packet CPL message header. */ | |
1905 | cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) | | |
1906 | TXPKT_INTF_V(pi->port_id) | | |
1907 | TXPKT_PF_V(0)); | |
1908 | cpl->pack = cpu_to_be16(0); | |
1909 | cpl->len = cpu_to_be16(skb->len); | |
1910 | cpl->ctrl1 = cpu_to_be64(cntrl); | |
1911 | ||
1912 | /* Fill in the body of the TX Packet CPL message with either in-lined | |
1913 | * data or a Scatter/Gather List. | |
1914 | */ | |
1915 | if (t4vf_is_eth_imm(skb)) { | |
1916 | /* In-line the packet's data and free the skb since we don't | |
1917 | * need it any longer. | |
1918 | */ | |
1919 | cxgb4_inline_tx_skb(skb, &txq->q, cpl + 1); | |
1920 | dev_consume_skb_any(skb); | |
1921 | } else { | |
1922 | /* Write the skb's Scatter/Gather list into the TX Packet CPL | |
1923 | * message and retain a pointer to the skb so we can free it | |
1924 | * later when its DMA completes. (We store the skb pointer | |
1925 | * in the Software Descriptor corresponding to the last TX | |
1926 | * Descriptor used by the Work Request.) | |
1927 | * | |
1928 | * The retained skb will be freed when the corresponding TX | |
1929 | * Descriptors are reclaimed after their DMAs complete. | |
1930 | * However, this could take quite a while since, in general, | |
1931 | * the hardware is set up to be lazy about sending DMA | |
1932 | * completion notifications to us and we mostly perform TX | |
1933 | * reclaims in the transmit routine. | |
1934 | * | |
1935 | * This is good for performamce but means that we rely on new | |
1936 | * TX packets arriving to run the destructors of completed | |
1937 | * packets, which open up space in their sockets' send queues. | |
1938 | * Sometimes we do not get such new packets causing TX to | |
1939 | * stall. A single UDP transmitter is a good example of this | |
1940 | * situation. We have a clean up timer that periodically | |
1941 | * reclaims completed packets but it doesn't run often enough | |
1942 | * (nor do we want it to) to prevent lengthy stalls. A | |
1943 | * solution to this problem is to run the destructor early, | |
1944 | * after the packet is queued but before it's DMAd. A con is | |
1945 | * that we lie to socket memory accounting, but the amount of | |
1946 | * extra memory is reasonable (limited by the number of TX | |
1947 | * descriptors), the packets do actually get freed quickly by | |
1948 | * new packets almost always, and for protocols like TCP that | |
1949 | * wait for acks to really free up the data the extra memory | |
1950 | * is even less. On the positive side we run the destructors | |
1951 | * on the sending CPU rather than on a potentially different | |
1952 | * completing CPU, usually a good thing. | |
1953 | * | |
1954 | * Run the destructor before telling the DMA engine about the | |
1955 | * packet to make sure it doesn't complete and get freed | |
1956 | * prematurely. | |
1957 | */ | |
1958 | struct ulptx_sgl *sgl = (struct ulptx_sgl *)(cpl + 1); | |
1959 | struct sge_txq *tq = &txq->q; | |
d5fbda61 AV |
1960 | |
1961 | /* If the Work Request header was an exact multiple of our TX | |
1962 | * Descriptor length, then it's possible that the starting SGL | |
1963 | * pointer lines up exactly with the end of our TX Descriptor | |
1964 | * ring. If that's the case, wrap around to the beginning | |
1965 | * here ... | |
1966 | */ | |
1967 | if (unlikely((void *)sgl == (void *)tq->stat)) { | |
1968 | sgl = (void *)tq->desc; | |
1969 | end = (void *)((void *)tq->desc + | |
1970 | ((void *)end - (void *)tq->stat)); | |
1971 | } | |
1972 | ||
0ed96b46 | 1973 | cxgb4_write_sgl(skb, tq, sgl, end, 0, sgl_sdesc->addr); |
d5fbda61 | 1974 | skb_orphan(skb); |
0ed96b46 | 1975 | sgl_sdesc->skb = skb; |
d5fbda61 AV |
1976 | } |
1977 | ||
1978 | /* Advance our internal TX Queue state, tell the hardware about | |
1979 | * the new TX descriptors and return success. | |
1980 | */ | |
1981 | txq_advance(&txq->q, ndesc); | |
1982 | ||
1983 | cxgb4_ring_tx_db(adapter, &txq->q, ndesc); | |
1984 | return NETDEV_TX_OK; | |
1985 | ||
1986 | out_free: | |
1987 | /* An error of some sort happened. Free the TX skb and tell the | |
1988 | * OS that we've "dealt" with the packet ... | |
1989 | */ | |
1990 | dev_kfree_skb_any(skb); | |
1991 | return NETDEV_TX_OK; | |
1992 | } | |
1993 | ||
4846d533 RL |
1994 | /** |
1995 | * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs | |
1996 | * @q: the SGE control Tx queue | |
1997 | * | |
1998 | * This is a variant of cxgb4_reclaim_completed_tx() that is used | |
1999 | * for Tx queues that send only immediate data (presently just | |
2000 | * the control queues) and thus do not have any sk_buffs to release. | |
2001 | */ | |
2002 | static inline void reclaim_completed_tx_imm(struct sge_txq *q) | |
2003 | { | |
2004 | int hw_cidx = ntohs(READ_ONCE(q->stat->cidx)); | |
2005 | int reclaim = hw_cidx - q->cidx; | |
2006 | ||
2007 | if (reclaim < 0) | |
2008 | reclaim += q->size; | |
2009 | ||
2010 | q->in_use -= reclaim; | |
2011 | q->cidx = hw_cidx; | |
2012 | } | |
2013 | ||
b1396c2b RL |
2014 | static inline void eosw_txq_advance_index(u32 *idx, u32 n, u32 max) |
2015 | { | |
2016 | u32 val = *idx + n; | |
2017 | ||
2018 | if (val >= max) | |
2019 | val -= max; | |
2020 | ||
2021 | *idx = val; | |
2022 | } | |
2023 | ||
2024 | void cxgb4_eosw_txq_free_desc(struct adapter *adap, | |
2025 | struct sge_eosw_txq *eosw_txq, u32 ndesc) | |
2026 | { | |
0ed96b46 | 2027 | struct tx_sw_desc *d; |
b1396c2b RL |
2028 | |
2029 | d = &eosw_txq->desc[eosw_txq->last_cidx]; | |
2030 | while (ndesc--) { | |
2031 | if (d->skb) { | |
2032 | if (d->addr[0]) { | |
2033 | unmap_skb(adap->pdev_dev, d->skb, d->addr); | |
2034 | memset(d->addr, 0, sizeof(d->addr)); | |
2035 | } | |
2036 | dev_consume_skb_any(d->skb); | |
2037 | d->skb = NULL; | |
2038 | } | |
2039 | eosw_txq_advance_index(&eosw_txq->last_cidx, 1, | |
2040 | eosw_txq->ndesc); | |
2041 | d = &eosw_txq->desc[eosw_txq->last_cidx]; | |
2042 | } | |
2043 | } | |
2044 | ||
4846d533 RL |
2045 | static inline void eosw_txq_advance(struct sge_eosw_txq *eosw_txq, u32 n) |
2046 | { | |
2047 | eosw_txq_advance_index(&eosw_txq->pidx, n, eosw_txq->ndesc); | |
2048 | eosw_txq->inuse += n; | |
2049 | } | |
2050 | ||
2051 | static inline int eosw_txq_enqueue(struct sge_eosw_txq *eosw_txq, | |
2052 | struct sk_buff *skb) | |
2053 | { | |
2054 | if (eosw_txq->inuse == eosw_txq->ndesc) | |
2055 | return -ENOMEM; | |
2056 | ||
2057 | eosw_txq->desc[eosw_txq->pidx].skb = skb; | |
2058 | return 0; | |
2059 | } | |
2060 | ||
2061 | static inline struct sk_buff *eosw_txq_peek(struct sge_eosw_txq *eosw_txq) | |
2062 | { | |
2063 | return eosw_txq->desc[eosw_txq->last_pidx].skb; | |
2064 | } | |
2065 | ||
2066 | static inline u8 ethofld_calc_tx_flits(struct adapter *adap, | |
2067 | struct sk_buff *skb, u32 hdr_len) | |
2068 | { | |
2069 | u8 flits, nsgl = 0; | |
2070 | u32 wrlen; | |
2071 | ||
2072 | wrlen = sizeof(struct fw_eth_tx_eo_wr) + sizeof(struct cpl_tx_pkt_core); | |
1a2a14fb RL |
2073 | if (skb_shinfo(skb)->gso_size && |
2074 | !(skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)) | |
4846d533 RL |
2075 | wrlen += sizeof(struct cpl_tx_pkt_lso_core); |
2076 | ||
2077 | wrlen += roundup(hdr_len, 16); | |
2078 | ||
2079 | /* Packet headers + WR + CPLs */ | |
2080 | flits = DIV_ROUND_UP(wrlen, 8); | |
2081 | ||
1a2a14fb RL |
2082 | if (skb_shinfo(skb)->nr_frags > 0) { |
2083 | if (skb_headlen(skb) - hdr_len) | |
2084 | nsgl = sgl_len(skb_shinfo(skb)->nr_frags + 1); | |
2085 | else | |
2086 | nsgl = sgl_len(skb_shinfo(skb)->nr_frags); | |
2087 | } else if (skb->len - hdr_len) { | |
4846d533 | 2088 | nsgl = sgl_len(1); |
1a2a14fb | 2089 | } |
4846d533 RL |
2090 | |
2091 | return flits + nsgl; | |
2092 | } | |
2093 | ||
2094 | static inline void *write_eo_wr(struct adapter *adap, | |
2095 | struct sge_eosw_txq *eosw_txq, | |
2096 | struct sk_buff *skb, struct fw_eth_tx_eo_wr *wr, | |
2097 | u32 hdr_len, u32 wrlen) | |
2098 | { | |
2099 | const struct skb_shared_info *ssi = skb_shinfo(skb); | |
2100 | struct cpl_tx_pkt_core *cpl; | |
2101 | u32 immd_len, wrlen16; | |
2102 | bool compl = false; | |
1a2a14fb RL |
2103 | u8 ver, proto; |
2104 | ||
2105 | ver = ip_hdr(skb)->version; | |
2106 | proto = (ver == 6) ? ipv6_hdr(skb)->nexthdr : ip_hdr(skb)->protocol; | |
4846d533 RL |
2107 | |
2108 | wrlen16 = DIV_ROUND_UP(wrlen, 16); | |
2109 | immd_len = sizeof(struct cpl_tx_pkt_core); | |
1a2a14fb RL |
2110 | if (skb_shinfo(skb)->gso_size && |
2111 | !(skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)) | |
2112 | immd_len += sizeof(struct cpl_tx_pkt_lso_core); | |
4846d533 RL |
2113 | immd_len += hdr_len; |
2114 | ||
2115 | if (!eosw_txq->ncompl || | |
2116 | eosw_txq->last_compl >= adap->params.ofldq_wr_cred / 2) { | |
2117 | compl = true; | |
2118 | eosw_txq->ncompl++; | |
2119 | eosw_txq->last_compl = 0; | |
2120 | } | |
2121 | ||
2122 | wr->op_immdlen = cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_EO_WR) | | |
2123 | FW_ETH_TX_EO_WR_IMMDLEN_V(immd_len) | | |
2124 | FW_WR_COMPL_V(compl)); | |
2125 | wr->equiq_to_len16 = cpu_to_be32(FW_WR_LEN16_V(wrlen16) | | |
2126 | FW_WR_FLOWID_V(eosw_txq->hwtid)); | |
2127 | wr->r3 = 0; | |
1a2a14fb RL |
2128 | if (proto == IPPROTO_UDP) { |
2129 | cpl = write_eo_udp_wr(skb, wr, hdr_len); | |
4846d533 | 2130 | } else { |
1a2a14fb RL |
2131 | wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG; |
2132 | wr->u.tcpseg.ethlen = skb_network_offset(skb); | |
2133 | wr->u.tcpseg.iplen = cpu_to_be16(skb_network_header_len(skb)); | |
2134 | wr->u.tcpseg.tcplen = tcp_hdrlen(skb); | |
2135 | wr->u.tcpseg.tsclk_tsoff = 0; | |
2136 | wr->u.tcpseg.r4 = 0; | |
2137 | wr->u.tcpseg.r5 = 0; | |
2138 | wr->u.tcpseg.plen = cpu_to_be32(skb->len - hdr_len); | |
2139 | ||
2140 | if (ssi->gso_size) { | |
2141 | struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); | |
2142 | ||
2143 | wr->u.tcpseg.mss = cpu_to_be16(ssi->gso_size); | |
2144 | cpl = write_tso_wr(adap, skb, lso); | |
2145 | } else { | |
2146 | wr->u.tcpseg.mss = cpu_to_be16(0xffff); | |
2147 | cpl = (void *)(wr + 1); | |
2148 | } | |
4846d533 RL |
2149 | } |
2150 | ||
2151 | eosw_txq->cred -= wrlen16; | |
2152 | eosw_txq->last_compl += wrlen16; | |
2153 | return cpl; | |
2154 | } | |
2155 | ||
2156 | static void ethofld_hard_xmit(struct net_device *dev, | |
2157 | struct sge_eosw_txq *eosw_txq) | |
2158 | { | |
2159 | struct port_info *pi = netdev2pinfo(dev); | |
2160 | struct adapter *adap = netdev2adap(dev); | |
2161 | u32 wrlen, wrlen16, hdr_len, data_len; | |
0e395b3c | 2162 | enum sge_eosw_state next_state; |
4846d533 RL |
2163 | u64 cntrl, *start, *end, *sgl; |
2164 | struct sge_eohw_txq *eohw_txq; | |
2165 | struct cpl_tx_pkt_core *cpl; | |
2166 | struct fw_eth_tx_eo_wr *wr; | |
0e395b3c | 2167 | bool skip_eotx_wr = false; |
0ed96b46 | 2168 | struct tx_sw_desc *d; |
4846d533 RL |
2169 | struct sk_buff *skb; |
2170 | u8 flits, ndesc; | |
2171 | int left; | |
2172 | ||
2173 | eohw_txq = &adap->sge.eohw_txq[eosw_txq->hwqid]; | |
2174 | spin_lock(&eohw_txq->lock); | |
2175 | reclaim_completed_tx_imm(&eohw_txq->q); | |
2176 | ||
2177 | d = &eosw_txq->desc[eosw_txq->last_pidx]; | |
2178 | skb = d->skb; | |
2179 | skb_tx_timestamp(skb); | |
2180 | ||
2181 | wr = (struct fw_eth_tx_eo_wr *)&eohw_txq->q.desc[eohw_txq->q.pidx]; | |
0e395b3c RL |
2182 | if (unlikely(eosw_txq->state != CXGB4_EO_STATE_ACTIVE && |
2183 | eosw_txq->last_pidx == eosw_txq->flowc_idx)) { | |
2184 | hdr_len = skb->len; | |
2185 | data_len = 0; | |
2186 | flits = DIV_ROUND_UP(hdr_len, 8); | |
2187 | if (eosw_txq->state == CXGB4_EO_STATE_FLOWC_OPEN_SEND) | |
2188 | next_state = CXGB4_EO_STATE_FLOWC_OPEN_REPLY; | |
2189 | else | |
2190 | next_state = CXGB4_EO_STATE_FLOWC_CLOSE_REPLY; | |
2191 | skip_eotx_wr = true; | |
2192 | } else { | |
2193 | hdr_len = eth_get_headlen(dev, skb->data, skb_headlen(skb)); | |
2194 | data_len = skb->len - hdr_len; | |
2195 | flits = ethofld_calc_tx_flits(adap, skb, hdr_len); | |
2196 | } | |
4846d533 RL |
2197 | ndesc = flits_to_desc(flits); |
2198 | wrlen = flits * 8; | |
2199 | wrlen16 = DIV_ROUND_UP(wrlen, 16); | |
2200 | ||
2201 | /* If there are no CPL credits, then wait for credits | |
2202 | * to come back and retry again | |
2203 | */ | |
2204 | if (unlikely(wrlen16 > eosw_txq->cred)) | |
2205 | goto out_unlock; | |
2206 | ||
0e395b3c RL |
2207 | if (unlikely(skip_eotx_wr)) { |
2208 | start = (u64 *)wr; | |
2209 | eosw_txq->state = next_state; | |
69422a7e RL |
2210 | eosw_txq->cred -= wrlen16; |
2211 | eosw_txq->ncompl++; | |
2212 | eosw_txq->last_compl = 0; | |
0e395b3c RL |
2213 | goto write_wr_headers; |
2214 | } | |
2215 | ||
4846d533 RL |
2216 | cpl = write_eo_wr(adap, eosw_txq, skb, wr, hdr_len, wrlen); |
2217 | cntrl = hwcsum(adap->params.chip, skb); | |
2218 | if (skb_vlan_tag_present(skb)) | |
2219 | cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb)); | |
2220 | ||
2221 | cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) | | |
2222 | TXPKT_INTF_V(pi->tx_chan) | | |
2223 | TXPKT_PF_V(adap->pf)); | |
2224 | cpl->pack = 0; | |
2225 | cpl->len = cpu_to_be16(skb->len); | |
2226 | cpl->ctrl1 = cpu_to_be64(cntrl); | |
2227 | ||
2228 | start = (u64 *)(cpl + 1); | |
2229 | ||
0e395b3c | 2230 | write_wr_headers: |
4846d533 RL |
2231 | sgl = (u64 *)inline_tx_skb_header(skb, &eohw_txq->q, (void *)start, |
2232 | hdr_len); | |
2233 | if (data_len) { | |
2234 | if (unlikely(cxgb4_map_skb(adap->pdev_dev, skb, d->addr))) { | |
2235 | memset(d->addr, 0, sizeof(d->addr)); | |
2236 | eohw_txq->mapping_err++; | |
2237 | goto out_unlock; | |
2238 | } | |
2239 | ||
2240 | end = (u64 *)wr + flits; | |
2241 | if (unlikely(start > sgl)) { | |
2242 | left = (u8 *)end - (u8 *)eohw_txq->q.stat; | |
2243 | end = (void *)eohw_txq->q.desc + left; | |
2244 | } | |
2245 | ||
2246 | if (unlikely((u8 *)sgl >= (u8 *)eohw_txq->q.stat)) { | |
2247 | /* If current position is already at the end of the | |
2248 | * txq, reset the current to point to start of the queue | |
2249 | * and update the end ptr as well. | |
2250 | */ | |
2251 | left = (u8 *)end - (u8 *)eohw_txq->q.stat; | |
2252 | ||
2253 | end = (void *)eohw_txq->q.desc + left; | |
2254 | sgl = (void *)eohw_txq->q.desc; | |
2255 | } | |
2256 | ||
2257 | cxgb4_write_sgl(skb, &eohw_txq->q, (void *)sgl, end, hdr_len, | |
2258 | d->addr); | |
2259 | } | |
2260 | ||
8311f0be RL |
2261 | if (skb_shinfo(skb)->gso_size) { |
2262 | if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) | |
2263 | eohw_txq->uso++; | |
2264 | else | |
2265 | eohw_txq->tso++; | |
2266 | eohw_txq->tx_cso += skb_shinfo(skb)->gso_segs; | |
2267 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
2268 | eohw_txq->tx_cso++; | |
2269 | } | |
2270 | ||
2271 | if (skb_vlan_tag_present(skb)) | |
2272 | eohw_txq->vlan_ins++; | |
2273 | ||
4846d533 RL |
2274 | txq_advance(&eohw_txq->q, ndesc); |
2275 | cxgb4_ring_tx_db(adap, &eohw_txq->q, ndesc); | |
2276 | eosw_txq_advance_index(&eosw_txq->last_pidx, 1, eosw_txq->ndesc); | |
2277 | ||
2278 | out_unlock: | |
2279 | spin_unlock(&eohw_txq->lock); | |
2280 | } | |
2281 | ||
2282 | static void ethofld_xmit(struct net_device *dev, struct sge_eosw_txq *eosw_txq) | |
2283 | { | |
2284 | struct sk_buff *skb; | |
2285 | int pktcount; | |
2286 | ||
2287 | switch (eosw_txq->state) { | |
2288 | case CXGB4_EO_STATE_ACTIVE: | |
0e395b3c RL |
2289 | case CXGB4_EO_STATE_FLOWC_OPEN_SEND: |
2290 | case CXGB4_EO_STATE_FLOWC_CLOSE_SEND: | |
4846d533 RL |
2291 | pktcount = eosw_txq->pidx - eosw_txq->last_pidx; |
2292 | if (pktcount < 0) | |
2293 | pktcount += eosw_txq->ndesc; | |
2294 | break; | |
0e395b3c RL |
2295 | case CXGB4_EO_STATE_FLOWC_OPEN_REPLY: |
2296 | case CXGB4_EO_STATE_FLOWC_CLOSE_REPLY: | |
4846d533 RL |
2297 | case CXGB4_EO_STATE_CLOSED: |
2298 | default: | |
2299 | return; | |
272630fe | 2300 | } |
4846d533 RL |
2301 | |
2302 | while (pktcount--) { | |
2303 | skb = eosw_txq_peek(eosw_txq); | |
2304 | if (!skb) { | |
2305 | eosw_txq_advance_index(&eosw_txq->last_pidx, 1, | |
2306 | eosw_txq->ndesc); | |
2307 | continue; | |
2308 | } | |
2309 | ||
2310 | ethofld_hard_xmit(dev, eosw_txq); | |
2311 | } | |
2312 | } | |
2313 | ||
b1396c2b RL |
2314 | static netdev_tx_t cxgb4_ethofld_xmit(struct sk_buff *skb, |
2315 | struct net_device *dev) | |
2316 | { | |
4846d533 RL |
2317 | struct cxgb4_tc_port_mqprio *tc_port_mqprio; |
2318 | struct port_info *pi = netdev2pinfo(dev); | |
2319 | struct adapter *adap = netdev2adap(dev); | |
2320 | struct sge_eosw_txq *eosw_txq; | |
2321 | u32 qid; | |
b1396c2b RL |
2322 | int ret; |
2323 | ||
2324 | ret = cxgb4_validate_skb(skb, dev, ETH_HLEN); | |
2325 | if (ret) | |
2326 | goto out_free; | |
2327 | ||
4846d533 RL |
2328 | tc_port_mqprio = &adap->tc_mqprio->port_mqprio[pi->port_id]; |
2329 | qid = skb_get_queue_mapping(skb) - pi->nqsets; | |
2330 | eosw_txq = &tc_port_mqprio->eosw_txq[qid]; | |
2331 | spin_lock_bh(&eosw_txq->lock); | |
2332 | if (eosw_txq->state != CXGB4_EO_STATE_ACTIVE) | |
2333 | goto out_unlock; | |
2334 | ||
2335 | ret = eosw_txq_enqueue(eosw_txq, skb); | |
2336 | if (ret) | |
2337 | goto out_unlock; | |
2338 | ||
2339 | /* SKB is queued for processing until credits are available. | |
2340 | * So, call the destructor now and we'll free the skb later | |
2341 | * after it has been successfully transmitted. | |
2342 | */ | |
2343 | skb_orphan(skb); | |
2344 | ||
2345 | eosw_txq_advance(eosw_txq, 1); | |
2346 | ethofld_xmit(dev, eosw_txq); | |
2347 | spin_unlock_bh(&eosw_txq->lock); | |
2348 | return NETDEV_TX_OK; | |
2349 | ||
2350 | out_unlock: | |
2351 | spin_unlock_bh(&eosw_txq->lock); | |
b1396c2b RL |
2352 | out_free: |
2353 | dev_kfree_skb_any(skb); | |
2354 | return NETDEV_TX_OK; | |
2355 | } | |
2356 | ||
d5fbda61 AV |
2357 | netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2358 | { | |
2359 | struct port_info *pi = netdev_priv(dev); | |
b1396c2b | 2360 | u16 qid = skb_get_queue_mapping(skb); |
d5fbda61 AV |
2361 | |
2362 | if (unlikely(pi->eth_flags & PRIV_FLAG_PORT_TX_VM)) | |
2363 | return cxgb4_vf_eth_xmit(skb, dev); | |
2364 | ||
b1396c2b RL |
2365 | if (unlikely(qid >= pi->nqsets)) |
2366 | return cxgb4_ethofld_xmit(skb, dev); | |
2367 | ||
d5fbda61 AV |
2368 | return cxgb4_eth_xmit(skb, dev); |
2369 | } | |
2370 | ||
69422a7e RL |
2371 | static void eosw_txq_flush_pending_skbs(struct sge_eosw_txq *eosw_txq) |
2372 | { | |
2373 | int pktcount = eosw_txq->pidx - eosw_txq->last_pidx; | |
2374 | int pidx = eosw_txq->pidx; | |
2375 | struct sk_buff *skb; | |
2376 | ||
2377 | if (!pktcount) | |
2378 | return; | |
2379 | ||
2380 | if (pktcount < 0) | |
2381 | pktcount += eosw_txq->ndesc; | |
2382 | ||
2383 | while (pktcount--) { | |
2384 | pidx--; | |
2385 | if (pidx < 0) | |
2386 | pidx += eosw_txq->ndesc; | |
2387 | ||
2388 | skb = eosw_txq->desc[pidx].skb; | |
2389 | if (skb) { | |
2390 | dev_consume_skb_any(skb); | |
2391 | eosw_txq->desc[pidx].skb = NULL; | |
2392 | eosw_txq->inuse--; | |
2393 | } | |
2394 | } | |
2395 | ||
2396 | eosw_txq->pidx = eosw_txq->last_pidx + 1; | |
2397 | } | |
2398 | ||
0e395b3c RL |
2399 | /** |
2400 | * cxgb4_ethofld_send_flowc - Send ETHOFLD flowc request to bind eotid to tc. | |
2401 | * @dev - netdevice | |
2402 | * @eotid - ETHOFLD tid to bind/unbind | |
2403 | * @tc - traffic class. If set to FW_SCHED_CLS_NONE, then unbinds the @eotid | |
2404 | * | |
2405 | * Send a FLOWC work request to bind an ETHOFLD TID to a traffic class. | |
2406 | * If @tc is set to FW_SCHED_CLS_NONE, then the @eotid is unbound from | |
2407 | * a traffic class. | |
2408 | */ | |
2409 | int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc) | |
2410 | { | |
2411 | struct port_info *pi = netdev2pinfo(dev); | |
2412 | struct adapter *adap = netdev2adap(dev); | |
2413 | enum sge_eosw_state next_state; | |
2414 | struct sge_eosw_txq *eosw_txq; | |
2415 | u32 len, len16, nparams = 6; | |
2416 | struct fw_flowc_wr *flowc; | |
2417 | struct eotid_entry *entry; | |
2418 | struct sge_ofld_rxq *rxq; | |
2419 | struct sk_buff *skb; | |
2420 | int ret = 0; | |
2421 | ||
2422 | len = sizeof(*flowc) + sizeof(struct fw_flowc_mnemval) * nparams; | |
2423 | len16 = DIV_ROUND_UP(len, 16); | |
2424 | ||
2425 | entry = cxgb4_lookup_eotid(&adap->tids, eotid); | |
2426 | if (!entry) | |
2427 | return -ENOMEM; | |
2428 | ||
2429 | eosw_txq = (struct sge_eosw_txq *)entry->data; | |
2430 | if (!eosw_txq) | |
2431 | return -ENOMEM; | |
2432 | ||
2433 | skb = alloc_skb(len, GFP_KERNEL); | |
2434 | if (!skb) | |
2435 | return -ENOMEM; | |
2436 | ||
2437 | spin_lock_bh(&eosw_txq->lock); | |
2438 | if (tc != FW_SCHED_CLS_NONE) { | |
2439 | if (eosw_txq->state != CXGB4_EO_STATE_CLOSED) | |
2440 | goto out_unlock; | |
2441 | ||
2442 | next_state = CXGB4_EO_STATE_FLOWC_OPEN_SEND; | |
2443 | } else { | |
2444 | if (eosw_txq->state != CXGB4_EO_STATE_ACTIVE) | |
2445 | goto out_unlock; | |
2446 | ||
2447 | next_state = CXGB4_EO_STATE_FLOWC_CLOSE_SEND; | |
2448 | } | |
2449 | ||
2450 | flowc = __skb_put(skb, len); | |
2451 | memset(flowc, 0, len); | |
2452 | ||
2453 | rxq = &adap->sge.eohw_rxq[eosw_txq->hwqid]; | |
2454 | flowc->flowid_len16 = cpu_to_be32(FW_WR_LEN16_V(len16) | | |
2455 | FW_WR_FLOWID_V(eosw_txq->hwtid)); | |
2456 | flowc->op_to_nparams = cpu_to_be32(FW_WR_OP_V(FW_FLOWC_WR) | | |
2457 | FW_FLOWC_WR_NPARAMS_V(nparams) | | |
2458 | FW_WR_COMPL_V(1)); | |
2459 | flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; | |
2460 | flowc->mnemval[0].val = cpu_to_be32(FW_PFVF_CMD_PFN_V(adap->pf)); | |
2461 | flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; | |
2462 | flowc->mnemval[1].val = cpu_to_be32(pi->tx_chan); | |
2463 | flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; | |
2464 | flowc->mnemval[2].val = cpu_to_be32(pi->tx_chan); | |
2465 | flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID; | |
2466 | flowc->mnemval[3].val = cpu_to_be32(rxq->rspq.abs_id); | |
2467 | flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS; | |
2468 | flowc->mnemval[4].val = cpu_to_be32(tc); | |
2469 | flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_EOSTATE; | |
2470 | flowc->mnemval[5].val = cpu_to_be32(tc == FW_SCHED_CLS_NONE ? | |
2471 | FW_FLOWC_MNEM_EOSTATE_CLOSING : | |
2472 | FW_FLOWC_MNEM_EOSTATE_ESTABLISHED); | |
2473 | ||
69422a7e RL |
2474 | /* Free up any pending skbs to ensure there's room for |
2475 | * termination FLOWC. | |
2476 | */ | |
2477 | if (tc == FW_SCHED_CLS_NONE) | |
2478 | eosw_txq_flush_pending_skbs(eosw_txq); | |
0e395b3c RL |
2479 | |
2480 | ret = eosw_txq_enqueue(eosw_txq, skb); | |
2481 | if (ret) { | |
2482 | dev_consume_skb_any(skb); | |
2483 | goto out_unlock; | |
2484 | } | |
2485 | ||
2486 | eosw_txq->state = next_state; | |
2487 | eosw_txq->flowc_idx = eosw_txq->pidx; | |
2488 | eosw_txq_advance(eosw_txq, 1); | |
2489 | ethofld_xmit(dev, eosw_txq); | |
2490 | ||
2491 | out_unlock: | |
2492 | spin_unlock_bh(&eosw_txq->lock); | |
2493 | return ret; | |
2494 | } | |
2495 | ||
fd3a4790 DM |
2496 | /** |
2497 | * is_imm - check whether a packet can be sent as immediate data | |
2498 | * @skb: the packet | |
2499 | * | |
2500 | * Returns true if a packet can be sent as a WR with immediate data. | |
2501 | */ | |
2502 | static inline int is_imm(const struct sk_buff *skb) | |
2503 | { | |
2504 | return skb->len <= MAX_CTRL_WR_LEN; | |
2505 | } | |
2506 | ||
2507 | /** | |
2508 | * ctrlq_check_stop - check if a control queue is full and should stop | |
2509 | * @q: the queue | |
2510 | * @wr: most recent WR written to the queue | |
2511 | * | |
2512 | * Check if a control queue has become full and should be stopped. | |
2513 | * We clean up control queue descriptors very lazily, only when we are out. | |
2514 | * If the queue is still full after reclaiming any completed descriptors | |
2515 | * we suspend it and have the last WR wake it up. | |
2516 | */ | |
2517 | static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr) | |
2518 | { | |
2519 | reclaim_completed_tx_imm(&q->q); | |
2520 | if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { | |
e2ac9628 | 2521 | wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F); |
fd3a4790 DM |
2522 | q->q.stops++; |
2523 | q->full = 1; | |
2524 | } | |
2525 | } | |
2526 | ||
2527 | /** | |
2528 | * ctrl_xmit - send a packet through an SGE control Tx queue | |
2529 | * @q: the control queue | |
2530 | * @skb: the packet | |
2531 | * | |
2532 | * Send a packet through an SGE control Tx queue. Packets sent through | |
2533 | * a control queue must fit entirely as immediate data. | |
2534 | */ | |
2535 | static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb) | |
2536 | { | |
2537 | unsigned int ndesc; | |
2538 | struct fw_wr_hdr *wr; | |
2539 | ||
2540 | if (unlikely(!is_imm(skb))) { | |
2541 | WARN_ON(1); | |
2542 | dev_kfree_skb(skb); | |
2543 | return NET_XMIT_DROP; | |
2544 | } | |
2545 | ||
2546 | ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc)); | |
2547 | spin_lock(&q->sendq.lock); | |
2548 | ||
2549 | if (unlikely(q->full)) { | |
2550 | skb->priority = ndesc; /* save for restart */ | |
2551 | __skb_queue_tail(&q->sendq, skb); | |
2552 | spin_unlock(&q->sendq.lock); | |
2553 | return NET_XMIT_CN; | |
2554 | } | |
2555 | ||
2556 | wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; | |
a6ec572b | 2557 | cxgb4_inline_tx_skb(skb, &q->q, wr); |
fd3a4790 DM |
2558 | |
2559 | txq_advance(&q->q, ndesc); | |
2560 | if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) | |
2561 | ctrlq_check_stop(q, wr); | |
2562 | ||
a6ec572b | 2563 | cxgb4_ring_tx_db(q->adap, &q->q, ndesc); |
fd3a4790 DM |
2564 | spin_unlock(&q->sendq.lock); |
2565 | ||
2566 | kfree_skb(skb); | |
2567 | return NET_XMIT_SUCCESS; | |
2568 | } | |
2569 | ||
2570 | /** | |
2571 | * restart_ctrlq - restart a suspended control queue | |
2572 | * @data: the control queue to restart | |
2573 | * | |
2574 | * Resumes transmission on a suspended Tx control queue. | |
2575 | */ | |
2576 | static void restart_ctrlq(unsigned long data) | |
2577 | { | |
2578 | struct sk_buff *skb; | |
2579 | unsigned int written = 0; | |
2580 | struct sge_ctrl_txq *q = (struct sge_ctrl_txq *)data; | |
2581 | ||
2582 | spin_lock(&q->sendq.lock); | |
2583 | reclaim_completed_tx_imm(&q->q); | |
2584 | BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */ | |
2585 | ||
2586 | while ((skb = __skb_dequeue(&q->sendq)) != NULL) { | |
2587 | struct fw_wr_hdr *wr; | |
2588 | unsigned int ndesc = skb->priority; /* previously saved */ | |
2589 | ||
a4011fd4 HS |
2590 | written += ndesc; |
2591 | /* Write descriptors and free skbs outside the lock to limit | |
fd3a4790 DM |
2592 | * wait times. q->full is still set so new skbs will be queued. |
2593 | */ | |
a4011fd4 HS |
2594 | wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx]; |
2595 | txq_advance(&q->q, ndesc); | |
fd3a4790 DM |
2596 | spin_unlock(&q->sendq.lock); |
2597 | ||
a6ec572b | 2598 | cxgb4_inline_tx_skb(skb, &q->q, wr); |
fd3a4790 DM |
2599 | kfree_skb(skb); |
2600 | ||
fd3a4790 DM |
2601 | if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { |
2602 | unsigned long old = q->q.stops; | |
2603 | ||
2604 | ctrlq_check_stop(q, wr); | |
2605 | if (q->q.stops != old) { /* suspended anew */ | |
2606 | spin_lock(&q->sendq.lock); | |
2607 | goto ringdb; | |
2608 | } | |
2609 | } | |
2610 | if (written > 16) { | |
a6ec572b | 2611 | cxgb4_ring_tx_db(q->adap, &q->q, written); |
fd3a4790 DM |
2612 | written = 0; |
2613 | } | |
2614 | spin_lock(&q->sendq.lock); | |
2615 | } | |
2616 | q->full = 0; | |
a6ec572b AG |
2617 | ringdb: |
2618 | if (written) | |
2619 | cxgb4_ring_tx_db(q->adap, &q->q, written); | |
fd3a4790 DM |
2620 | spin_unlock(&q->sendq.lock); |
2621 | } | |
2622 | ||
2623 | /** | |
2624 | * t4_mgmt_tx - send a management message | |
2625 | * @adap: the adapter | |
2626 | * @skb: the packet containing the management message | |
2627 | * | |
2628 | * Send a management message through control queue 0. | |
2629 | */ | |
2630 | int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb) | |
2631 | { | |
2632 | int ret; | |
2633 | ||
2634 | local_bh_disable(); | |
2635 | ret = ctrl_xmit(&adap->sge.ctrlq[0], skb); | |
2636 | local_bh_enable(); | |
2637 | return ret; | |
2638 | } | |
2639 | ||
2640 | /** | |
2641 | * is_ofld_imm - check whether a packet can be sent as immediate data | |
2642 | * @skb: the packet | |
2643 | * | |
2644 | * Returns true if a packet can be sent as an offload WR with immediate | |
2645 | * data. We currently use the same limit as for Ethernet packets. | |
2646 | */ | |
2647 | static inline int is_ofld_imm(const struct sk_buff *skb) | |
2648 | { | |
2f47d580 HJ |
2649 | struct work_request_hdr *req = (struct work_request_hdr *)skb->data; |
2650 | unsigned long opcode = FW_WR_OP_G(ntohl(req->wr_hi)); | |
2651 | ||
2652 | if (opcode == FW_CRYPTO_LOOKASIDE_WR) | |
2653 | return skb->len <= SGE_MAX_WR_LEN; | |
2654 | else | |
2655 | return skb->len <= MAX_IMM_TX_PKT_LEN; | |
fd3a4790 DM |
2656 | } |
2657 | ||
2658 | /** | |
2659 | * calc_tx_flits_ofld - calculate # of flits for an offload packet | |
2660 | * @skb: the packet | |
2661 | * | |
2662 | * Returns the number of flits needed for the given offload packet. | |
2663 | * These packets are already fully constructed and no additional headers | |
2664 | * will be added. | |
2665 | */ | |
2666 | static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb) | |
2667 | { | |
2668 | unsigned int flits, cnt; | |
2669 | ||
2670 | if (is_ofld_imm(skb)) | |
2671 | return DIV_ROUND_UP(skb->len, 8); | |
2672 | ||
2673 | flits = skb_transport_offset(skb) / 8U; /* headers */ | |
2674 | cnt = skb_shinfo(skb)->nr_frags; | |
15dd16c2 | 2675 | if (skb_tail_pointer(skb) != skb_transport_header(skb)) |
fd3a4790 DM |
2676 | cnt++; |
2677 | return flits + sgl_len(cnt); | |
2678 | } | |
2679 | ||
2680 | /** | |
2681 | * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion | |
2682 | * @adap: the adapter | |
2683 | * @q: the queue to stop | |
2684 | * | |
2685 | * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting | |
2686 | * inability to map packets. A periodic timer attempts to restart | |
2687 | * queues so marked. | |
2688 | */ | |
ab677ff4 | 2689 | static void txq_stop_maperr(struct sge_uld_txq *q) |
fd3a4790 DM |
2690 | { |
2691 | q->mapping_err++; | |
2692 | q->q.stops++; | |
e46dab4d DM |
2693 | set_bit(q->q.cntxt_id - q->adap->sge.egr_start, |
2694 | q->adap->sge.txq_maperr); | |
fd3a4790 DM |
2695 | } |
2696 | ||
2697 | /** | |
2698 | * ofldtxq_stop - stop an offload Tx queue that has become full | |
2699 | * @q: the queue to stop | |
e383f248 | 2700 | * @wr: the Work Request causing the queue to become full |
fd3a4790 DM |
2701 | * |
2702 | * Stops an offload Tx queue that has become full and modifies the packet | |
2703 | * being written to request a wakeup. | |
2704 | */ | |
e383f248 | 2705 | static void ofldtxq_stop(struct sge_uld_txq *q, struct fw_wr_hdr *wr) |
fd3a4790 | 2706 | { |
e2ac9628 | 2707 | wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F); |
fd3a4790 DM |
2708 | q->q.stops++; |
2709 | q->full = 1; | |
2710 | } | |
2711 | ||
2712 | /** | |
126fca64 | 2713 | * service_ofldq - service/restart a suspended offload queue |
fd3a4790 DM |
2714 | * @q: the offload queue |
2715 | * | |
126fca64 HS |
2716 | * Services an offload Tx queue by moving packets from its Pending Send |
2717 | * Queue to the Hardware TX ring. The function starts and ends with the | |
2718 | * Send Queue locked, but drops the lock while putting the skb at the | |
2719 | * head of the Send Queue onto the Hardware TX Ring. Dropping the lock | |
2720 | * allows more skbs to be added to the Send Queue by other threads. | |
2721 | * The packet being processed at the head of the Pending Send Queue is | |
2722 | * left on the queue in case we experience DMA Mapping errors, etc. | |
2723 | * and need to give up and restart later. | |
2724 | * | |
2725 | * service_ofldq() can be thought of as a task which opportunistically | |
2726 | * uses other threads execution contexts. We use the Offload Queue | |
2727 | * boolean "service_ofldq_running" to make sure that only one instance | |
2728 | * is ever running at a time ... | |
fd3a4790 | 2729 | */ |
ab677ff4 | 2730 | static void service_ofldq(struct sge_uld_txq *q) |
cae9566a | 2731 | __must_hold(&q->sendq.lock) |
fd3a4790 | 2732 | { |
8d0557d2 | 2733 | u64 *pos, *before, *end; |
fd3a4790 DM |
2734 | int credits; |
2735 | struct sk_buff *skb; | |
8d0557d2 HS |
2736 | struct sge_txq *txq; |
2737 | unsigned int left; | |
fd3a4790 DM |
2738 | unsigned int written = 0; |
2739 | unsigned int flits, ndesc; | |
2740 | ||
126fca64 HS |
2741 | /* If another thread is currently in service_ofldq() processing the |
2742 | * Pending Send Queue then there's nothing to do. Otherwise, flag | |
2743 | * that we're doing the work and continue. Examining/modifying | |
2744 | * the Offload Queue boolean "service_ofldq_running" must be done | |
2745 | * while holding the Pending Send Queue Lock. | |
2746 | */ | |
2747 | if (q->service_ofldq_running) | |
2748 | return; | |
2749 | q->service_ofldq_running = true; | |
2750 | ||
fd3a4790 | 2751 | while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) { |
126fca64 HS |
2752 | /* We drop the lock while we're working with the skb at the |
2753 | * head of the Pending Send Queue. This allows more skbs to | |
2754 | * be added to the Pending Send Queue while we're working on | |
2755 | * this one. We don't need to lock to guard the TX Ring | |
2756 | * updates because only one thread of execution is ever | |
2757 | * allowed into service_ofldq() at a time. | |
fd3a4790 DM |
2758 | */ |
2759 | spin_unlock(&q->sendq.lock); | |
2760 | ||
a6ec572b | 2761 | cxgb4_reclaim_completed_tx(q->adap, &q->q, false); |
fd3a4790 DM |
2762 | |
2763 | flits = skb->priority; /* previously saved */ | |
2764 | ndesc = flits_to_desc(flits); | |
2765 | credits = txq_avail(&q->q) - ndesc; | |
2766 | BUG_ON(credits < 0); | |
2767 | if (unlikely(credits < TXQ_STOP_THRES)) | |
e383f248 | 2768 | ofldtxq_stop(q, (struct fw_wr_hdr *)skb->data); |
fd3a4790 DM |
2769 | |
2770 | pos = (u64 *)&q->q.desc[q->q.pidx]; | |
2771 | if (is_ofld_imm(skb)) | |
a6ec572b AG |
2772 | cxgb4_inline_tx_skb(skb, &q->q, pos); |
2773 | else if (cxgb4_map_skb(q->adap->pdev_dev, skb, | |
2774 | (dma_addr_t *)skb->head)) { | |
fd3a4790 DM |
2775 | txq_stop_maperr(q); |
2776 | spin_lock(&q->sendq.lock); | |
2777 | break; | |
2778 | } else { | |
2779 | int last_desc, hdr_len = skb_transport_offset(skb); | |
2780 | ||
8d0557d2 HS |
2781 | /* The WR headers may not fit within one descriptor. |
2782 | * So we need to deal with wrap-around here. | |
2783 | */ | |
2784 | before = (u64 *)pos; | |
2785 | end = (u64 *)pos + flits; | |
2786 | txq = &q->q; | |
2787 | pos = (void *)inline_tx_skb_header(skb, &q->q, | |
2788 | (void *)pos, | |
2789 | hdr_len); | |
2790 | if (before > (u64 *)pos) { | |
2791 | left = (u8 *)end - (u8 *)txq->stat; | |
2792 | end = (void *)txq->desc + left; | |
2793 | } | |
2794 | ||
2795 | /* If current position is already at the end of the | |
2796 | * ofld queue, reset the current to point to | |
2797 | * start of the queue and update the end ptr as well. | |
2798 | */ | |
2799 | if (pos == (u64 *)txq->stat) { | |
2800 | left = (u8 *)end - (u8 *)txq->stat; | |
2801 | end = (void *)txq->desc + left; | |
2802 | pos = (void *)txq->desc; | |
2803 | } | |
2804 | ||
a6ec572b AG |
2805 | cxgb4_write_sgl(skb, &q->q, (void *)pos, |
2806 | end, hdr_len, | |
2807 | (dma_addr_t *)skb->head); | |
fd3a4790 DM |
2808 | #ifdef CONFIG_NEED_DMA_MAP_STATE |
2809 | skb->dev = q->adap->port[0]; | |
2810 | skb->destructor = deferred_unmap_destructor; | |
2811 | #endif | |
2812 | last_desc = q->q.pidx + ndesc - 1; | |
2813 | if (last_desc >= q->q.size) | |
2814 | last_desc -= q->q.size; | |
2815 | q->q.sdesc[last_desc].skb = skb; | |
2816 | } | |
2817 | ||
2818 | txq_advance(&q->q, ndesc); | |
2819 | written += ndesc; | |
2820 | if (unlikely(written > 32)) { | |
a6ec572b | 2821 | cxgb4_ring_tx_db(q->adap, &q->q, written); |
fd3a4790 DM |
2822 | written = 0; |
2823 | } | |
2824 | ||
126fca64 HS |
2825 | /* Reacquire the Pending Send Queue Lock so we can unlink the |
2826 | * skb we've just successfully transferred to the TX Ring and | |
2827 | * loop for the next skb which may be at the head of the | |
2828 | * Pending Send Queue. | |
2829 | */ | |
fd3a4790 DM |
2830 | spin_lock(&q->sendq.lock); |
2831 | __skb_unlink(skb, &q->sendq); | |
2832 | if (is_ofld_imm(skb)) | |
2833 | kfree_skb(skb); | |
2834 | } | |
2835 | if (likely(written)) | |
a6ec572b | 2836 | cxgb4_ring_tx_db(q->adap, &q->q, written); |
126fca64 HS |
2837 | |
2838 | /*Indicate that no thread is processing the Pending Send Queue | |
2839 | * currently. | |
2840 | */ | |
2841 | q->service_ofldq_running = false; | |
fd3a4790 DM |
2842 | } |
2843 | ||
2844 | /** | |
2845 | * ofld_xmit - send a packet through an offload queue | |
2846 | * @q: the Tx offload queue | |
2847 | * @skb: the packet | |
2848 | * | |
2849 | * Send an offload packet through an SGE offload queue. | |
2850 | */ | |
ab677ff4 | 2851 | static int ofld_xmit(struct sge_uld_txq *q, struct sk_buff *skb) |
fd3a4790 DM |
2852 | { |
2853 | skb->priority = calc_tx_flits_ofld(skb); /* save for restart */ | |
2854 | spin_lock(&q->sendq.lock); | |
126fca64 HS |
2855 | |
2856 | /* Queue the new skb onto the Offload Queue's Pending Send Queue. If | |
2857 | * that results in this new skb being the only one on the queue, start | |
2858 | * servicing it. If there are other skbs already on the list, then | |
2859 | * either the queue is currently being processed or it's been stopped | |
2860 | * for some reason and it'll be restarted at a later time. Restart | |
2861 | * paths are triggered by events like experiencing a DMA Mapping Error | |
2862 | * or filling the Hardware TX Ring. | |
2863 | */ | |
fd3a4790 DM |
2864 | __skb_queue_tail(&q->sendq, skb); |
2865 | if (q->sendq.qlen == 1) | |
2866 | service_ofldq(q); | |
126fca64 | 2867 | |
fd3a4790 DM |
2868 | spin_unlock(&q->sendq.lock); |
2869 | return NET_XMIT_SUCCESS; | |
2870 | } | |
2871 | ||
2872 | /** | |
2873 | * restart_ofldq - restart a suspended offload queue | |
2874 | * @data: the offload queue to restart | |
2875 | * | |
2876 | * Resumes transmission on a suspended Tx offload queue. | |
2877 | */ | |
2878 | static void restart_ofldq(unsigned long data) | |
2879 | { | |
ab677ff4 | 2880 | struct sge_uld_txq *q = (struct sge_uld_txq *)data; |
fd3a4790 DM |
2881 | |
2882 | spin_lock(&q->sendq.lock); | |
2883 | q->full = 0; /* the queue actually is completely empty now */ | |
2884 | service_ofldq(q); | |
2885 | spin_unlock(&q->sendq.lock); | |
2886 | } | |
2887 | ||
2888 | /** | |
2889 | * skb_txq - return the Tx queue an offload packet should use | |
2890 | * @skb: the packet | |
2891 | * | |
2892 | * Returns the Tx queue an offload packet should use as indicated by bits | |
2893 | * 1-15 in the packet's queue_mapping. | |
2894 | */ | |
2895 | static inline unsigned int skb_txq(const struct sk_buff *skb) | |
2896 | { | |
2897 | return skb->queue_mapping >> 1; | |
2898 | } | |
2899 | ||
2900 | /** | |
2901 | * is_ctrl_pkt - return whether an offload packet is a control packet | |
2902 | * @skb: the packet | |
2903 | * | |
2904 | * Returns whether an offload packet should use an OFLD or a CTRL | |
2905 | * Tx queue as indicated by bit 0 in the packet's queue_mapping. | |
2906 | */ | |
2907 | static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb) | |
2908 | { | |
2909 | return skb->queue_mapping & 1; | |
2910 | } | |
2911 | ||
ab677ff4 HS |
2912 | static inline int uld_send(struct adapter *adap, struct sk_buff *skb, |
2913 | unsigned int tx_uld_type) | |
fd3a4790 | 2914 | { |
ab677ff4 HS |
2915 | struct sge_uld_txq_info *txq_info; |
2916 | struct sge_uld_txq *txq; | |
fd3a4790 DM |
2917 | unsigned int idx = skb_txq(skb); |
2918 | ||
4fe44dd7 KS |
2919 | if (unlikely(is_ctrl_pkt(skb))) { |
2920 | /* Single ctrl queue is a requirement for LE workaround path */ | |
2921 | if (adap->tids.nsftids) | |
2922 | idx = 0; | |
fd3a4790 | 2923 | return ctrl_xmit(&adap->sge.ctrlq[idx], skb); |
4fe44dd7 | 2924 | } |
0d4b729d A |
2925 | |
2926 | txq_info = adap->sge.uld_txq_info[tx_uld_type]; | |
2927 | if (unlikely(!txq_info)) { | |
2928 | WARN_ON(true); | |
2929 | return NET_XMIT_DROP; | |
2930 | } | |
2931 | ||
2932 | txq = &txq_info->uldtxq[idx]; | |
ab677ff4 | 2933 | return ofld_xmit(txq, skb); |
fd3a4790 DM |
2934 | } |
2935 | ||
2936 | /** | |
2937 | * t4_ofld_send - send an offload packet | |
2938 | * @adap: the adapter | |
2939 | * @skb: the packet | |
2940 | * | |
2941 | * Sends an offload packet. We use the packet queue_mapping to select the | |
2942 | * appropriate Tx queue as follows: bit 0 indicates whether the packet | |
2943 | * should be sent as regular or control, bits 1-15 select the queue. | |
2944 | */ | |
2945 | int t4_ofld_send(struct adapter *adap, struct sk_buff *skb) | |
2946 | { | |
2947 | int ret; | |
2948 | ||
2949 | local_bh_disable(); | |
ab677ff4 | 2950 | ret = uld_send(adap, skb, CXGB4_TX_OFLD); |
fd3a4790 DM |
2951 | local_bh_enable(); |
2952 | return ret; | |
2953 | } | |
2954 | ||
2955 | /** | |
2956 | * cxgb4_ofld_send - send an offload packet | |
2957 | * @dev: the net device | |
2958 | * @skb: the packet | |
2959 | * | |
2960 | * Sends an offload packet. This is an exported version of @t4_ofld_send, | |
2961 | * intended for ULDs. | |
2962 | */ | |
2963 | int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb) | |
2964 | { | |
2965 | return t4_ofld_send(netdev2adap(dev), skb); | |
2966 | } | |
2967 | EXPORT_SYMBOL(cxgb4_ofld_send); | |
2968 | ||
e383f248 AG |
2969 | static void *inline_tx_header(const void *src, |
2970 | const struct sge_txq *q, | |
2971 | void *pos, int length) | |
2972 | { | |
2973 | int left = (void *)q->stat - pos; | |
2974 | u64 *p; | |
2975 | ||
2976 | if (likely(length <= left)) { | |
2977 | memcpy(pos, src, length); | |
2978 | pos += length; | |
2979 | } else { | |
2980 | memcpy(pos, src, left); | |
2981 | memcpy(q->desc, src + left, length - left); | |
2982 | pos = (void *)q->desc + (length - left); | |
2983 | } | |
2984 | /* 0-pad to multiple of 16 */ | |
2985 | p = PTR_ALIGN(pos, 8); | |
2986 | if ((uintptr_t)p & 8) { | |
2987 | *p = 0; | |
2988 | return p + 1; | |
2989 | } | |
2990 | return p; | |
2991 | } | |
2992 | ||
2993 | /** | |
2994 | * ofld_xmit_direct - copy a WR into offload queue | |
2995 | * @q: the Tx offload queue | |
2996 | * @src: location of WR | |
2997 | * @len: WR length | |
2998 | * | |
2999 | * Copy an immediate WR into an uncontended SGE offload queue. | |
3000 | */ | |
3001 | static int ofld_xmit_direct(struct sge_uld_txq *q, const void *src, | |
3002 | unsigned int len) | |
3003 | { | |
3004 | unsigned int ndesc; | |
3005 | int credits; | |
3006 | u64 *pos; | |
3007 | ||
3008 | /* Use the lower limit as the cut-off */ | |
3009 | if (len > MAX_IMM_OFLD_TX_DATA_WR_LEN) { | |
3010 | WARN_ON(1); | |
3011 | return NET_XMIT_DROP; | |
3012 | } | |
3013 | ||
3014 | /* Don't return NET_XMIT_CN here as the current | |
3015 | * implementation doesn't queue the request | |
3016 | * using an skb when the following conditions not met | |
3017 | */ | |
3018 | if (!spin_trylock(&q->sendq.lock)) | |
3019 | return NET_XMIT_DROP; | |
3020 | ||
3021 | if (q->full || !skb_queue_empty(&q->sendq) || | |
3022 | q->service_ofldq_running) { | |
3023 | spin_unlock(&q->sendq.lock); | |
3024 | return NET_XMIT_DROP; | |
3025 | } | |
3026 | ndesc = flits_to_desc(DIV_ROUND_UP(len, 8)); | |
3027 | credits = txq_avail(&q->q) - ndesc; | |
3028 | pos = (u64 *)&q->q.desc[q->q.pidx]; | |
3029 | ||
3030 | /* ofldtxq_stop modifies WR header in-situ */ | |
3031 | inline_tx_header(src, &q->q, pos, len); | |
3032 | if (unlikely(credits < TXQ_STOP_THRES)) | |
3033 | ofldtxq_stop(q, (struct fw_wr_hdr *)pos); | |
3034 | txq_advance(&q->q, ndesc); | |
3035 | cxgb4_ring_tx_db(q->adap, &q->q, ndesc); | |
3036 | ||
3037 | spin_unlock(&q->sendq.lock); | |
3038 | return NET_XMIT_SUCCESS; | |
3039 | } | |
3040 | ||
3041 | int cxgb4_immdata_send(struct net_device *dev, unsigned int idx, | |
3042 | const void *src, unsigned int len) | |
3043 | { | |
3044 | struct sge_uld_txq_info *txq_info; | |
3045 | struct sge_uld_txq *txq; | |
3046 | struct adapter *adap; | |
3047 | int ret; | |
3048 | ||
3049 | adap = netdev2adap(dev); | |
3050 | ||
3051 | local_bh_disable(); | |
3052 | txq_info = adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
3053 | if (unlikely(!txq_info)) { | |
3054 | WARN_ON(true); | |
3055 | local_bh_enable(); | |
3056 | return NET_XMIT_DROP; | |
3057 | } | |
3058 | txq = &txq_info->uldtxq[idx]; | |
3059 | ||
3060 | ret = ofld_xmit_direct(txq, src, len); | |
3061 | local_bh_enable(); | |
3062 | return net_xmit_eval(ret); | |
3063 | } | |
3064 | EXPORT_SYMBOL(cxgb4_immdata_send); | |
3065 | ||
ab677ff4 HS |
3066 | /** |
3067 | * t4_crypto_send - send crypto packet | |
3068 | * @adap: the adapter | |
3069 | * @skb: the packet | |
3070 | * | |
3071 | * Sends crypto packet. We use the packet queue_mapping to select the | |
3072 | * appropriate Tx queue as follows: bit 0 indicates whether the packet | |
3073 | * should be sent as regular or control, bits 1-15 select the queue. | |
3074 | */ | |
3075 | static int t4_crypto_send(struct adapter *adap, struct sk_buff *skb) | |
3076 | { | |
3077 | int ret; | |
3078 | ||
3079 | local_bh_disable(); | |
3080 | ret = uld_send(adap, skb, CXGB4_TX_CRYPTO); | |
3081 | local_bh_enable(); | |
3082 | return ret; | |
3083 | } | |
3084 | ||
3085 | /** | |
3086 | * cxgb4_crypto_send - send crypto packet | |
3087 | * @dev: the net device | |
3088 | * @skb: the packet | |
3089 | * | |
3090 | * Sends crypto packet. This is an exported version of @t4_crypto_send, | |
3091 | * intended for ULDs. | |
3092 | */ | |
3093 | int cxgb4_crypto_send(struct net_device *dev, struct sk_buff *skb) | |
3094 | { | |
3095 | return t4_crypto_send(netdev2adap(dev), skb); | |
3096 | } | |
3097 | EXPORT_SYMBOL(cxgb4_crypto_send); | |
3098 | ||
e91b0f24 | 3099 | static inline void copy_frags(struct sk_buff *skb, |
fd3a4790 DM |
3100 | const struct pkt_gl *gl, unsigned int offset) |
3101 | { | |
e91b0f24 | 3102 | int i; |
fd3a4790 DM |
3103 | |
3104 | /* usually there's just one frag */ | |
e91b0f24 IC |
3105 | __skb_fill_page_desc(skb, 0, gl->frags[0].page, |
3106 | gl->frags[0].offset + offset, | |
3107 | gl->frags[0].size - offset); | |
3108 | skb_shinfo(skb)->nr_frags = gl->nfrags; | |
3109 | for (i = 1; i < gl->nfrags; i++) | |
3110 | __skb_fill_page_desc(skb, i, gl->frags[i].page, | |
3111 | gl->frags[i].offset, | |
3112 | gl->frags[i].size); | |
fd3a4790 DM |
3113 | |
3114 | /* get a reference to the last page, we don't own it */ | |
e91b0f24 | 3115 | get_page(gl->frags[gl->nfrags - 1].page); |
fd3a4790 DM |
3116 | } |
3117 | ||
3118 | /** | |
3119 | * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list | |
3120 | * @gl: the gather list | |
3121 | * @skb_len: size of sk_buff main body if it carries fragments | |
3122 | * @pull_len: amount of data to move to the sk_buff's main body | |
3123 | * | |
3124 | * Builds an sk_buff from the given packet gather list. Returns the | |
3125 | * sk_buff or %NULL if sk_buff allocation failed. | |
3126 | */ | |
3127 | struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl, | |
3128 | unsigned int skb_len, unsigned int pull_len) | |
3129 | { | |
3130 | struct sk_buff *skb; | |
3131 | ||
3132 | /* | |
3133 | * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer | |
3134 | * size, which is expected since buffers are at least PAGE_SIZEd. | |
3135 | * In this case packets up to RX_COPY_THRES have only one fragment. | |
3136 | */ | |
3137 | if (gl->tot_len <= RX_COPY_THRES) { | |
3138 | skb = dev_alloc_skb(gl->tot_len); | |
3139 | if (unlikely(!skb)) | |
3140 | goto out; | |
3141 | __skb_put(skb, gl->tot_len); | |
3142 | skb_copy_to_linear_data(skb, gl->va, gl->tot_len); | |
3143 | } else { | |
3144 | skb = dev_alloc_skb(skb_len); | |
3145 | if (unlikely(!skb)) | |
3146 | goto out; | |
3147 | __skb_put(skb, pull_len); | |
3148 | skb_copy_to_linear_data(skb, gl->va, pull_len); | |
3149 | ||
e91b0f24 | 3150 | copy_frags(skb, gl, pull_len); |
fd3a4790 DM |
3151 | skb->len = gl->tot_len; |
3152 | skb->data_len = skb->len - pull_len; | |
3153 | skb->truesize += skb->data_len; | |
3154 | } | |
3155 | out: return skb; | |
3156 | } | |
3157 | EXPORT_SYMBOL(cxgb4_pktgl_to_skb); | |
3158 | ||
3159 | /** | |
3160 | * t4_pktgl_free - free a packet gather list | |
3161 | * @gl: the gather list | |
3162 | * | |
3163 | * Releases the pages of a packet gather list. We do not own the last | |
3164 | * page on the list and do not free it. | |
3165 | */ | |
de498c89 | 3166 | static void t4_pktgl_free(const struct pkt_gl *gl) |
fd3a4790 DM |
3167 | { |
3168 | int n; | |
e91b0f24 | 3169 | const struct page_frag *p; |
fd3a4790 DM |
3170 | |
3171 | for (p = gl->frags, n = gl->nfrags - 1; n--; p++) | |
3172 | put_page(p->page); | |
3173 | } | |
3174 | ||
3175 | /* | |
3176 | * Process an MPS trace packet. Give it an unused protocol number so it won't | |
3177 | * be delivered to anyone and send it to the stack for capture. | |
3178 | */ | |
3179 | static noinline int handle_trace_pkt(struct adapter *adap, | |
3180 | const struct pkt_gl *gl) | |
3181 | { | |
3182 | struct sk_buff *skb; | |
fd3a4790 DM |
3183 | |
3184 | skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN); | |
3185 | if (unlikely(!skb)) { | |
3186 | t4_pktgl_free(gl); | |
3187 | return 0; | |
3188 | } | |
3189 | ||
d14807dd | 3190 | if (is_t4(adap->params.chip)) |
0a57a536 SR |
3191 | __skb_pull(skb, sizeof(struct cpl_trace_pkt)); |
3192 | else | |
3193 | __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt)); | |
3194 | ||
fd3a4790 DM |
3195 | skb_reset_mac_header(skb); |
3196 | skb->protocol = htons(0xffff); | |
3197 | skb->dev = adap->port[0]; | |
3198 | netif_receive_skb(skb); | |
3199 | return 0; | |
3200 | } | |
3201 | ||
5e2a5ebc HS |
3202 | /** |
3203 | * cxgb4_sgetim_to_hwtstamp - convert sge time stamp to hw time stamp | |
3204 | * @adap: the adapter | |
3205 | * @hwtstamps: time stamp structure to update | |
3206 | * @sgetstamp: 60bit iqe timestamp | |
3207 | * | |
3208 | * Every ingress queue entry has the 60-bit timestamp, convert that timestamp | |
3209 | * which is in Core Clock ticks into ktime_t and assign it | |
3210 | **/ | |
3211 | static void cxgb4_sgetim_to_hwtstamp(struct adapter *adap, | |
3212 | struct skb_shared_hwtstamps *hwtstamps, | |
3213 | u64 sgetstamp) | |
3214 | { | |
3215 | u64 ns; | |
3216 | u64 tmp = (sgetstamp * 1000 * 1000 + adap->params.vpd.cclk / 2); | |
3217 | ||
3218 | ns = div_u64(tmp, adap->params.vpd.cclk); | |
3219 | ||
3220 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
3221 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
3222 | } | |
3223 | ||
fd3a4790 | 3224 | static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl, |
c50ae55e | 3225 | const struct cpl_rx_pkt *pkt, unsigned long tnl_hdr_len) |
fd3a4790 | 3226 | { |
52367a76 VP |
3227 | struct adapter *adapter = rxq->rspq.adap; |
3228 | struct sge *s = &adapter->sge; | |
5e2a5ebc | 3229 | struct port_info *pi; |
fd3a4790 DM |
3230 | int ret; |
3231 | struct sk_buff *skb; | |
3232 | ||
3233 | skb = napi_get_frags(&rxq->rspq.napi); | |
3234 | if (unlikely(!skb)) { | |
3235 | t4_pktgl_free(gl); | |
3236 | rxq->stats.rx_drops++; | |
3237 | return; | |
3238 | } | |
3239 | ||
52367a76 | 3240 | copy_frags(skb, gl, s->pktshift); |
c50ae55e GG |
3241 | if (tnl_hdr_len) |
3242 | skb->csum_level = 1; | |
52367a76 | 3243 | skb->len = gl->tot_len - s->pktshift; |
fd3a4790 DM |
3244 | skb->data_len = skb->len; |
3245 | skb->truesize += skb->data_len; | |
3246 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
3247 | skb_record_rx_queue(skb, rxq->rspq.idx); | |
5e2a5ebc HS |
3248 | pi = netdev_priv(skb->dev); |
3249 | if (pi->rxtstamp) | |
3250 | cxgb4_sgetim_to_hwtstamp(adapter, skb_hwtstamps(skb), | |
3251 | gl->sgetstamp); | |
87b6cf51 | 3252 | if (rxq->rspq.netdev->features & NETIF_F_RXHASH) |
8264989c TH |
3253 | skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, |
3254 | PKT_HASH_TYPE_L3); | |
fd3a4790 DM |
3255 | |
3256 | if (unlikely(pkt->vlan_ex)) { | |
86a9bad3 | 3257 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); |
fd3a4790 | 3258 | rxq->stats.vlan_ex++; |
fd3a4790 DM |
3259 | } |
3260 | ret = napi_gro_frags(&rxq->rspq.napi); | |
19ecae2c | 3261 | if (ret == GRO_HELD) |
fd3a4790 DM |
3262 | rxq->stats.lro_pkts++; |
3263 | else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE) | |
3264 | rxq->stats.lro_merged++; | |
3265 | rxq->stats.pkts++; | |
3266 | rxq->stats.rx_cso++; | |
3267 | } | |
3268 | ||
a4569504 AG |
3269 | enum { |
3270 | RX_NON_PTP_PKT = 0, | |
3271 | RX_PTP_PKT_SUC = 1, | |
3272 | RX_PTP_PKT_ERR = 2 | |
3273 | }; | |
3274 | ||
3275 | /** | |
3276 | * t4_systim_to_hwstamp - read hardware time stamp | |
3277 | * @adap: the adapter | |
3278 | * @skb: the packet | |
3279 | * | |
3280 | * Read Time Stamp from MPS packet and insert in skb which | |
3281 | * is forwarded to PTP application | |
3282 | */ | |
3283 | static noinline int t4_systim_to_hwstamp(struct adapter *adapter, | |
3284 | struct sk_buff *skb) | |
3285 | { | |
3286 | struct skb_shared_hwtstamps *hwtstamps; | |
3287 | struct cpl_rx_mps_pkt *cpl = NULL; | |
3288 | unsigned char *data; | |
3289 | int offset; | |
3290 | ||
3291 | cpl = (struct cpl_rx_mps_pkt *)skb->data; | |
3292 | if (!(CPL_RX_MPS_PKT_TYPE_G(ntohl(cpl->op_to_r1_hi)) & | |
3293 | X_CPL_RX_MPS_PKT_TYPE_PTP)) | |
3294 | return RX_PTP_PKT_ERR; | |
3295 | ||
3296 | data = skb->data + sizeof(*cpl); | |
3297 | skb_pull(skb, 2 * sizeof(u64) + sizeof(struct cpl_rx_mps_pkt)); | |
3298 | offset = ETH_HLEN + IPV4_HLEN(skb->data) + UDP_HLEN; | |
3299 | if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(short)) | |
3300 | return RX_PTP_PKT_ERR; | |
3301 | ||
3302 | hwtstamps = skb_hwtstamps(skb); | |
3303 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
3304 | hwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*((u64 *)data))); | |
3305 | ||
3306 | return RX_PTP_PKT_SUC; | |
3307 | } | |
3308 | ||
3309 | /** | |
3310 | * t4_rx_hststamp - Recv PTP Event Message | |
3311 | * @adap: the adapter | |
3312 | * @rsp: the response queue descriptor holding the RX_PKT message | |
3313 | * @skb: the packet | |
3314 | * | |
3315 | * PTP enabled and MPS packet, read HW timestamp | |
3316 | */ | |
3317 | static int t4_rx_hststamp(struct adapter *adapter, const __be64 *rsp, | |
3318 | struct sge_eth_rxq *rxq, struct sk_buff *skb) | |
3319 | { | |
3320 | int ret; | |
3321 | ||
3322 | if (unlikely((*(u8 *)rsp == CPL_RX_MPS_PKT) && | |
3323 | !is_t4(adapter->params.chip))) { | |
3324 | ret = t4_systim_to_hwstamp(adapter, skb); | |
3325 | if (ret == RX_PTP_PKT_ERR) { | |
3326 | kfree_skb(skb); | |
3327 | rxq->stats.rx_drops++; | |
3328 | } | |
3329 | return ret; | |
3330 | } | |
3331 | return RX_NON_PTP_PKT; | |
3332 | } | |
3333 | ||
3334 | /** | |
3335 | * t4_tx_hststamp - Loopback PTP Transmit Event Message | |
3336 | * @adap: the adapter | |
3337 | * @skb: the packet | |
3338 | * @dev: the ingress net device | |
3339 | * | |
3340 | * Read hardware timestamp for the loopback PTP Tx event message | |
3341 | */ | |
3342 | static int t4_tx_hststamp(struct adapter *adapter, struct sk_buff *skb, | |
3343 | struct net_device *dev) | |
3344 | { | |
3345 | struct port_info *pi = netdev_priv(dev); | |
3346 | ||
3347 | if (!is_t4(adapter->params.chip) && adapter->ptp_tx_skb) { | |
3348 | cxgb4_ptp_read_hwstamp(adapter, pi); | |
3349 | kfree_skb(skb); | |
3350 | return 0; | |
3351 | } | |
3352 | return 1; | |
3353 | } | |
3354 | ||
d429005f VK |
3355 | /** |
3356 | * t4_tx_completion_handler - handle CPL_SGE_EGR_UPDATE messages | |
3357 | * @rspq: Ethernet RX Response Queue associated with Ethernet TX Queue | |
3358 | * @rsp: Response Entry pointer into Response Queue | |
3359 | * @gl: Gather List pointer | |
3360 | * | |
3361 | * For adapters which support the SGE Doorbell Queue Timer facility, | |
3362 | * we configure the Ethernet TX Queues to send CIDX Updates to the | |
3363 | * Associated Ethernet RX Response Queue with CPL_SGE_EGR_UPDATE | |
3364 | * messages. This adds a small load to PCIe Link RX bandwidth and, | |
3365 | * potentially, higher CPU Interrupt load, but allows us to respond | |
3366 | * much more quickly to the CIDX Updates. This is important for | |
3367 | * Upper Layer Software which isn't willing to have a large amount | |
3368 | * of TX Data outstanding before receiving DMA Completions. | |
3369 | */ | |
3370 | static void t4_tx_completion_handler(struct sge_rspq *rspq, | |
3371 | const __be64 *rsp, | |
3372 | const struct pkt_gl *gl) | |
3373 | { | |
3374 | u8 opcode = ((const struct rss_header *)rsp)->opcode; | |
3375 | struct port_info *pi = netdev_priv(rspq->netdev); | |
3376 | struct adapter *adapter = rspq->adap; | |
3377 | struct sge *s = &adapter->sge; | |
3378 | struct sge_eth_txq *txq; | |
3379 | ||
3380 | /* skip RSS header */ | |
3381 | rsp++; | |
3382 | ||
3383 | /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. | |
3384 | */ | |
3385 | if (unlikely(opcode == CPL_FW4_MSG && | |
3386 | ((const struct cpl_fw4_msg *)rsp)->type == | |
3387 | FW_TYPE_RSSCPL)) { | |
3388 | rsp++; | |
3389 | opcode = ((const struct rss_header *)rsp)->opcode; | |
3390 | rsp++; | |
3391 | } | |
3392 | ||
3393 | if (unlikely(opcode != CPL_SGE_EGR_UPDATE)) { | |
3394 | pr_info("%s: unexpected FW4/CPL %#x on Rx queue\n", | |
3395 | __func__, opcode); | |
3396 | return; | |
3397 | } | |
3398 | ||
3399 | txq = &s->ethtxq[pi->first_qset + rspq->idx]; | |
d429005f VK |
3400 | t4_sge_eth_txq_egress_update(adapter, txq, -1); |
3401 | } | |
3402 | ||
fd3a4790 DM |
3403 | /** |
3404 | * t4_ethrx_handler - process an ingress ethernet packet | |
3405 | * @q: the response queue that received the packet | |
3406 | * @rsp: the response queue descriptor holding the RX_PKT message | |
3407 | * @si: the gather list of packet fragments | |
3408 | * | |
3409 | * Process an ingress ethernet packet and deliver it to the stack. | |
3410 | */ | |
3411 | int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, | |
3412 | const struct pkt_gl *si) | |
3413 | { | |
3414 | bool csum_ok; | |
3415 | struct sk_buff *skb; | |
fd3a4790 DM |
3416 | const struct cpl_rx_pkt *pkt; |
3417 | struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); | |
a4569504 | 3418 | struct adapter *adapter = q->adap; |
52367a76 | 3419 | struct sge *s = &q->adap->sge; |
d14807dd | 3420 | int cpl_trace_pkt = is_t4(q->adap->params.chip) ? |
0a57a536 | 3421 | CPL_TRACE_PKT : CPL_TRACE_PKT_T5; |
c50ae55e | 3422 | u16 err_vec, tnl_hdr_len = 0; |
84a200b3 | 3423 | struct port_info *pi; |
a4569504 | 3424 | int ret = 0; |
fd3a4790 | 3425 | |
d429005f VK |
3426 | /* If we're looking at TX Queue CIDX Update, handle that separately |
3427 | * and return. | |
3428 | */ | |
3429 | if (unlikely((*(u8 *)rsp == CPL_FW4_MSG) || | |
3430 | (*(u8 *)rsp == CPL_SGE_EGR_UPDATE))) { | |
3431 | t4_tx_completion_handler(q, rsp, si); | |
3432 | return 0; | |
3433 | } | |
3434 | ||
0a57a536 | 3435 | if (unlikely(*(u8 *)rsp == cpl_trace_pkt)) |
fd3a4790 DM |
3436 | return handle_trace_pkt(q->adap, si); |
3437 | ||
87b6cf51 | 3438 | pkt = (const struct cpl_rx_pkt *)rsp; |
8eb9f2f9 | 3439 | /* Compressed error vector is enabled for T6 only */ |
c50ae55e | 3440 | if (q->adap->params.tp.rx_pkt_encap) { |
8eb9f2f9 | 3441 | err_vec = T6_COMPR_RXERR_VEC_G(be16_to_cpu(pkt->err_vec)); |
c50ae55e GG |
3442 | tnl_hdr_len = T6_RX_TNLHDR_LEN_G(ntohs(pkt->err_vec)); |
3443 | } else { | |
8eb9f2f9 | 3444 | err_vec = be16_to_cpu(pkt->err_vec); |
c50ae55e | 3445 | } |
8eb9f2f9 A |
3446 | |
3447 | csum_ok = pkt->csum_calc && !err_vec && | |
cca2822d | 3448 | (q->netdev->features & NETIF_F_RXCSUM); |
992bea8e GG |
3449 | |
3450 | if (err_vec) | |
3451 | rxq->stats.bad_rx_pkts++; | |
3452 | ||
c50ae55e GG |
3453 | if (((pkt->l2info & htonl(RXF_TCP_F)) || |
3454 | tnl_hdr_len) && | |
fd3a4790 | 3455 | (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) { |
c50ae55e | 3456 | do_gro(rxq, si, pkt, tnl_hdr_len); |
fd3a4790 DM |
3457 | return 0; |
3458 | } | |
3459 | ||
3460 | skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN); | |
3461 | if (unlikely(!skb)) { | |
3462 | t4_pktgl_free(si); | |
3463 | rxq->stats.rx_drops++; | |
3464 | return 0; | |
3465 | } | |
a4569504 AG |
3466 | pi = netdev_priv(q->netdev); |
3467 | ||
3468 | /* Handle PTP Event Rx packet */ | |
3469 | if (unlikely(pi->ptp_enable)) { | |
3470 | ret = t4_rx_hststamp(adapter, rsp, rxq, skb); | |
3471 | if (ret == RX_PTP_PKT_ERR) | |
3472 | return 0; | |
3473 | } | |
3474 | if (likely(!ret)) | |
3475 | __skb_pull(skb, s->pktshift); /* remove ethernet header pad */ | |
3476 | ||
3477 | /* Handle the PTP Event Tx Loopback packet */ | |
3478 | if (unlikely(pi->ptp_enable && !ret && | |
3479 | (pkt->l2info & htonl(RXF_UDP_F)) && | |
3480 | cxgb4_ptp_is_ptp_rx(skb))) { | |
3481 | if (!t4_tx_hststamp(adapter, skb, q->netdev)) | |
3482 | return 0; | |
3483 | } | |
fd3a4790 | 3484 | |
fd3a4790 DM |
3485 | skb->protocol = eth_type_trans(skb, q->netdev); |
3486 | skb_record_rx_queue(skb, q->idx); | |
87b6cf51 | 3487 | if (skb->dev->features & NETIF_F_RXHASH) |
8264989c TH |
3488 | skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val, |
3489 | PKT_HASH_TYPE_L3); | |
87b6cf51 | 3490 | |
fd3a4790 DM |
3491 | rxq->stats.pkts++; |
3492 | ||
5e2a5ebc HS |
3493 | if (pi->rxtstamp) |
3494 | cxgb4_sgetim_to_hwtstamp(q->adap, skb_hwtstamps(skb), | |
3495 | si->sgetstamp); | |
bdc590b9 | 3496 | if (csum_ok && (pkt->l2info & htonl(RXF_UDP_F | RXF_TCP_F))) { |
ba5d3c66 | 3497 | if (!pkt->ip_frag) { |
fd3a4790 | 3498 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
ba5d3c66 | 3499 | rxq->stats.rx_cso++; |
bdc590b9 | 3500 | } else if (pkt->l2info & htonl(RXF_IP_F)) { |
fd3a4790 DM |
3501 | __sum16 c = (__force __sum16)pkt->csum; |
3502 | skb->csum = csum_unfold(c); | |
c50ae55e GG |
3503 | |
3504 | if (tnl_hdr_len) { | |
3505 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
3506 | skb->csum_level = 1; | |
3507 | } else { | |
3508 | skb->ip_summed = CHECKSUM_COMPLETE; | |
3509 | } | |
ba5d3c66 | 3510 | rxq->stats.rx_cso++; |
fd3a4790 | 3511 | } |
84a200b3 | 3512 | } else { |
bc8acf2c | 3513 | skb_checksum_none_assert(skb); |
84a200b3 VP |
3514 | #ifdef CONFIG_CHELSIO_T4_FCOE |
3515 | #define CPL_RX_PKT_FLAGS (RXF_PSH_F | RXF_SYN_F | RXF_UDP_F | \ | |
3516 | RXF_TCP_F | RXF_IP_F | RXF_IP6_F | RXF_LRO_F) | |
3517 | ||
84a200b3 VP |
3518 | if (!(pkt->l2info & cpu_to_be32(CPL_RX_PKT_FLAGS))) { |
3519 | if ((pkt->l2info & cpu_to_be32(RXF_FCOE_F)) && | |
3520 | (pi->fcoe.flags & CXGB_FCOE_ENABLED)) { | |
8eb9f2f9 A |
3521 | if (q->adap->params.tp.rx_pkt_encap) |
3522 | csum_ok = err_vec & | |
3523 | T6_COMPR_RXERR_SUM_F; | |
3524 | else | |
3525 | csum_ok = err_vec & RXERR_CSUM_F; | |
3526 | if (!csum_ok) | |
84a200b3 VP |
3527 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
3528 | } | |
3529 | } | |
3530 | ||
3531 | #undef CPL_RX_PKT_FLAGS | |
3532 | #endif /* CONFIG_CHELSIO_T4_FCOE */ | |
3533 | } | |
fd3a4790 DM |
3534 | |
3535 | if (unlikely(pkt->vlan_ex)) { | |
86a9bad3 | 3536 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan)); |
fd3a4790 | 3537 | rxq->stats.vlan_ex++; |
19ecae2c | 3538 | } |
3a336cb1 | 3539 | skb_mark_napi_id(skb, &q->napi); |
19ecae2c | 3540 | netif_receive_skb(skb); |
fd3a4790 DM |
3541 | return 0; |
3542 | } | |
3543 | ||
3544 | /** | |
3545 | * restore_rx_bufs - put back a packet's Rx buffers | |
3546 | * @si: the packet gather list | |
3547 | * @q: the SGE free list | |
3548 | * @frags: number of FL buffers to restore | |
3549 | * | |
3550 | * Puts back on an FL the Rx buffers associated with @si. The buffers | |
3551 | * have already been unmapped and are left unmapped, we mark them so to | |
3552 | * prevent further unmapping attempts. | |
3553 | * | |
3554 | * This function undoes a series of @unmap_rx_buf calls when we find out | |
3555 | * that the current packet can't be processed right away afterall and we | |
3556 | * need to come back to it later. This is a very rare event and there's | |
3557 | * no effort to make this particularly efficient. | |
3558 | */ | |
3559 | static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q, | |
3560 | int frags) | |
3561 | { | |
3562 | struct rx_sw_desc *d; | |
3563 | ||
3564 | while (frags--) { | |
3565 | if (q->cidx == 0) | |
3566 | q->cidx = q->size - 1; | |
3567 | else | |
3568 | q->cidx--; | |
3569 | d = &q->sdesc[q->cidx]; | |
3570 | d->page = si->frags[frags].page; | |
3571 | d->dma_addr |= RX_UNMAPPED_BUF; | |
3572 | q->avail++; | |
3573 | } | |
3574 | } | |
3575 | ||
3576 | /** | |
3577 | * is_new_response - check if a response is newly written | |
3578 | * @r: the response descriptor | |
3579 | * @q: the response queue | |
3580 | * | |
3581 | * Returns true if a response descriptor contains a yet unprocessed | |
3582 | * response. | |
3583 | */ | |
3584 | static inline bool is_new_response(const struct rsp_ctrl *r, | |
3585 | const struct sge_rspq *q) | |
3586 | { | |
1ecc7b7a | 3587 | return (r->type_gen >> RSPD_GEN_S) == q->gen; |
fd3a4790 DM |
3588 | } |
3589 | ||
3590 | /** | |
3591 | * rspq_next - advance to the next entry in a response queue | |
3592 | * @q: the queue | |
3593 | * | |
3594 | * Updates the state of a response queue to advance it to the next entry. | |
3595 | */ | |
3596 | static inline void rspq_next(struct sge_rspq *q) | |
3597 | { | |
3598 | q->cur_desc = (void *)q->cur_desc + q->iqe_len; | |
3599 | if (unlikely(++q->cidx == q->size)) { | |
3600 | q->cidx = 0; | |
3601 | q->gen ^= 1; | |
3602 | q->cur_desc = q->desc; | |
3603 | } | |
3604 | } | |
3605 | ||
3606 | /** | |
3607 | * process_responses - process responses from an SGE response queue | |
3608 | * @q: the ingress queue to process | |
3609 | * @budget: how many responses can be processed in this round | |
3610 | * | |
3611 | * Process responses from an SGE response queue up to the supplied budget. | |
3612 | * Responses include received packets as well as control messages from FW | |
3613 | * or HW. | |
3614 | * | |
3615 | * Additionally choose the interrupt holdoff time for the next interrupt | |
3616 | * on this queue. If the system is under memory shortage use a fairly | |
3617 | * long delay to help recovery. | |
3618 | */ | |
3619 | static int process_responses(struct sge_rspq *q, int budget) | |
3620 | { | |
3621 | int ret, rsp_type; | |
3622 | int budget_left = budget; | |
3623 | const struct rsp_ctrl *rc; | |
3624 | struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); | |
52367a76 VP |
3625 | struct adapter *adapter = q->adap; |
3626 | struct sge *s = &adapter->sge; | |
fd3a4790 DM |
3627 | |
3628 | while (likely(budget_left)) { | |
3629 | rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); | |
2337ba42 VP |
3630 | if (!is_new_response(rc, q)) { |
3631 | if (q->flush_handler) | |
3632 | q->flush_handler(q); | |
fd3a4790 | 3633 | break; |
2337ba42 | 3634 | } |
fd3a4790 | 3635 | |
019be1cf | 3636 | dma_rmb(); |
1ecc7b7a HS |
3637 | rsp_type = RSPD_TYPE_G(rc->type_gen); |
3638 | if (likely(rsp_type == RSPD_TYPE_FLBUF_X)) { | |
e91b0f24 | 3639 | struct page_frag *fp; |
fd3a4790 DM |
3640 | struct pkt_gl si; |
3641 | const struct rx_sw_desc *rsd; | |
3642 | u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags; | |
3643 | ||
1ecc7b7a | 3644 | if (len & RSPD_NEWBUF_F) { |
fd3a4790 DM |
3645 | if (likely(q->offset > 0)) { |
3646 | free_rx_bufs(q->adap, &rxq->fl, 1); | |
3647 | q->offset = 0; | |
3648 | } | |
1ecc7b7a | 3649 | len = RSPD_LEN_G(len); |
fd3a4790 DM |
3650 | } |
3651 | si.tot_len = len; | |
3652 | ||
3653 | /* gather packet fragments */ | |
3654 | for (frags = 0, fp = si.frags; ; frags++, fp++) { | |
3655 | rsd = &rxq->fl.sdesc[rxq->fl.cidx]; | |
52367a76 | 3656 | bufsz = get_buf_size(adapter, rsd); |
fd3a4790 | 3657 | fp->page = rsd->page; |
e91b0f24 IC |
3658 | fp->offset = q->offset; |
3659 | fp->size = min(bufsz, len); | |
3660 | len -= fp->size; | |
fd3a4790 DM |
3661 | if (!len) |
3662 | break; | |
3663 | unmap_rx_buf(q->adap, &rxq->fl); | |
3664 | } | |
3665 | ||
5e2a5ebc HS |
3666 | si.sgetstamp = SGE_TIMESTAMP_G( |
3667 | be64_to_cpu(rc->last_flit)); | |
fd3a4790 DM |
3668 | /* |
3669 | * Last buffer remains mapped so explicitly make it | |
3670 | * coherent for CPU access. | |
3671 | */ | |
3672 | dma_sync_single_for_cpu(q->adap->pdev_dev, | |
3673 | get_buf_addr(rsd), | |
e91b0f24 | 3674 | fp->size, DMA_FROM_DEVICE); |
fd3a4790 DM |
3675 | |
3676 | si.va = page_address(si.frags[0].page) + | |
e91b0f24 | 3677 | si.frags[0].offset; |
fd3a4790 DM |
3678 | prefetch(si.va); |
3679 | ||
3680 | si.nfrags = frags + 1; | |
3681 | ret = q->handler(q, q->cur_desc, &si); | |
3682 | if (likely(ret == 0)) | |
52367a76 | 3683 | q->offset += ALIGN(fp->size, s->fl_align); |
fd3a4790 DM |
3684 | else |
3685 | restore_rx_bufs(&si, &rxq->fl, frags); | |
1ecc7b7a | 3686 | } else if (likely(rsp_type == RSPD_TYPE_CPL_X)) { |
fd3a4790 DM |
3687 | ret = q->handler(q, q->cur_desc, NULL); |
3688 | } else { | |
3689 | ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN); | |
3690 | } | |
3691 | ||
3692 | if (unlikely(ret)) { | |
3693 | /* couldn't process descriptor, back off for recovery */ | |
1ecc7b7a | 3694 | q->next_intr_params = QINTR_TIMER_IDX_V(NOMEM_TMR_IDX); |
fd3a4790 DM |
3695 | break; |
3696 | } | |
3697 | ||
3698 | rspq_next(q); | |
3699 | budget_left--; | |
3700 | } | |
3701 | ||
da08e425 | 3702 | if (q->offset >= 0 && fl_cap(&rxq->fl) - rxq->fl.avail >= 16) |
fd3a4790 DM |
3703 | __refill_fl(q->adap, &rxq->fl); |
3704 | return budget - budget_left; | |
3705 | } | |
3706 | ||
3707 | /** | |
3708 | * napi_rx_handler - the NAPI handler for Rx processing | |
3709 | * @napi: the napi instance | |
3710 | * @budget: how many packets we can process in this round | |
3711 | * | |
3712 | * Handler for new data events when using NAPI. This does not need any | |
3713 | * locking or protection from interrupts as data interrupts are off at | |
3714 | * this point and other adapter interrupts do not interfere (the latter | |
3715 | * in not a concern at all with MSI-X as non-data interrupts then have | |
3716 | * a separate handler). | |
3717 | */ | |
3718 | static int napi_rx_handler(struct napi_struct *napi, int budget) | |
3719 | { | |
3720 | unsigned int params; | |
3721 | struct sge_rspq *q = container_of(napi, struct sge_rspq, napi); | |
3a336cb1 | 3722 | int work_done; |
d63a6dcf | 3723 | u32 val; |
fd3a4790 | 3724 | |
3a336cb1 | 3725 | work_done = process_responses(q, budget); |
fd3a4790 | 3726 | if (likely(work_done < budget)) { |
e553ec3f HS |
3727 | int timer_index; |
3728 | ||
812787b8 | 3729 | napi_complete_done(napi, work_done); |
1ecc7b7a | 3730 | timer_index = QINTR_TIMER_IDX_G(q->next_intr_params); |
e553ec3f HS |
3731 | |
3732 | if (q->adaptive_rx) { | |
3733 | if (work_done > max(timer_pkt_quota[timer_index], | |
3734 | MIN_NAPI_WORK)) | |
3735 | timer_index = (timer_index + 1); | |
3736 | else | |
3737 | timer_index = timer_index - 1; | |
3738 | ||
3739 | timer_index = clamp(timer_index, 0, SGE_TIMERREGS - 1); | |
1ecc7b7a HS |
3740 | q->next_intr_params = |
3741 | QINTR_TIMER_IDX_V(timer_index) | | |
3742 | QINTR_CNT_EN_V(0); | |
e553ec3f HS |
3743 | params = q->next_intr_params; |
3744 | } else { | |
3745 | params = q->next_intr_params; | |
3746 | q->next_intr_params = q->intr_params; | |
3747 | } | |
fd3a4790 | 3748 | } else |
1ecc7b7a | 3749 | params = QINTR_TIMER_IDX_V(7); |
fd3a4790 | 3750 | |
f612b815 | 3751 | val = CIDXINC_V(work_done) | SEINTARM_V(params); |
df64e4d3 HS |
3752 | |
3753 | /* If we don't have access to the new User GTS (T5+), use the old | |
3754 | * doorbell mechanism; otherwise use the new BAR2 mechanism. | |
3755 | */ | |
3756 | if (unlikely(q->bar2_addr == NULL)) { | |
f612b815 HS |
3757 | t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A), |
3758 | val | INGRESSQID_V((u32)q->cntxt_id)); | |
d63a6dcf | 3759 | } else { |
f612b815 | 3760 | writel(val | INGRESSQID_V(q->bar2_qid), |
df64e4d3 | 3761 | q->bar2_addr + SGE_UDB_GTS); |
d63a6dcf HS |
3762 | wmb(); |
3763 | } | |
fd3a4790 DM |
3764 | return work_done; |
3765 | } | |
3766 | ||
b1396c2b RL |
3767 | void cxgb4_ethofld_restart(unsigned long data) |
3768 | { | |
3769 | struct sge_eosw_txq *eosw_txq = (struct sge_eosw_txq *)data; | |
3770 | int pktcount; | |
3771 | ||
3772 | spin_lock(&eosw_txq->lock); | |
3773 | pktcount = eosw_txq->cidx - eosw_txq->last_cidx; | |
3774 | if (pktcount < 0) | |
3775 | pktcount += eosw_txq->ndesc; | |
3776 | ||
4846d533 | 3777 | if (pktcount) { |
b1396c2b RL |
3778 | cxgb4_eosw_txq_free_desc(netdev2adap(eosw_txq->netdev), |
3779 | eosw_txq, pktcount); | |
4846d533 RL |
3780 | eosw_txq->inuse -= pktcount; |
3781 | } | |
3782 | ||
3783 | /* There may be some packets waiting for completions. So, | |
3784 | * attempt to send these packets now. | |
3785 | */ | |
3786 | ethofld_xmit(eosw_txq->netdev, eosw_txq); | |
b1396c2b RL |
3787 | spin_unlock(&eosw_txq->lock); |
3788 | } | |
3789 | ||
4846d533 RL |
3790 | /* cxgb4_ethofld_rx_handler - Process ETHOFLD Tx completions |
3791 | * @q: the response queue that received the packet | |
3792 | * @rsp: the response queue descriptor holding the CPL message | |
3793 | * @si: the gather list of packet fragments | |
3794 | * | |
3795 | * Process a ETHOFLD Tx completion. Increment the cidx here, but | |
3796 | * free up the descriptors in a tasklet later. | |
3797 | */ | |
3798 | int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp, | |
3799 | const struct pkt_gl *si) | |
3800 | { | |
3801 | u8 opcode = ((const struct rss_header *)rsp)->opcode; | |
3802 | ||
3803 | /* skip RSS header */ | |
3804 | rsp++; | |
3805 | ||
3806 | if (opcode == CPL_FW4_ACK) { | |
3807 | const struct cpl_fw4_ack *cpl; | |
3808 | struct sge_eosw_txq *eosw_txq; | |
3809 | struct eotid_entry *entry; | |
3810 | struct sk_buff *skb; | |
3811 | u32 hdr_len, eotid; | |
3812 | u8 flits, wrlen16; | |
3813 | int credits; | |
3814 | ||
3815 | cpl = (const struct cpl_fw4_ack *)rsp; | |
3816 | eotid = CPL_FW4_ACK_FLOWID_G(ntohl(OPCODE_TID(cpl))) - | |
3817 | q->adap->tids.eotid_base; | |
3818 | entry = cxgb4_lookup_eotid(&q->adap->tids, eotid); | |
3819 | if (!entry) | |
3820 | goto out_done; | |
3821 | ||
3822 | eosw_txq = (struct sge_eosw_txq *)entry->data; | |
3823 | if (!eosw_txq) | |
3824 | goto out_done; | |
3825 | ||
3826 | spin_lock(&eosw_txq->lock); | |
3827 | credits = cpl->credits; | |
3828 | while (credits > 0) { | |
3829 | skb = eosw_txq->desc[eosw_txq->cidx].skb; | |
3830 | if (!skb) | |
3831 | break; | |
3832 | ||
0e395b3c RL |
3833 | if (unlikely((eosw_txq->state == |
3834 | CXGB4_EO_STATE_FLOWC_OPEN_REPLY || | |
3835 | eosw_txq->state == | |
3836 | CXGB4_EO_STATE_FLOWC_CLOSE_REPLY) && | |
3837 | eosw_txq->cidx == eosw_txq->flowc_idx)) { | |
0e395b3c RL |
3838 | flits = DIV_ROUND_UP(skb->len, 8); |
3839 | if (eosw_txq->state == | |
3840 | CXGB4_EO_STATE_FLOWC_OPEN_REPLY) | |
3841 | eosw_txq->state = CXGB4_EO_STATE_ACTIVE; | |
3842 | else | |
3843 | eosw_txq->state = CXGB4_EO_STATE_CLOSED; | |
3844 | complete(&eosw_txq->completion); | |
3845 | } else { | |
3846 | hdr_len = eth_get_headlen(eosw_txq->netdev, | |
3847 | skb->data, | |
3848 | skb_headlen(skb)); | |
3849 | flits = ethofld_calc_tx_flits(q->adap, skb, | |
3850 | hdr_len); | |
3851 | } | |
4846d533 RL |
3852 | eosw_txq_advance_index(&eosw_txq->cidx, 1, |
3853 | eosw_txq->ndesc); | |
3854 | wrlen16 = DIV_ROUND_UP(flits * 8, 16); | |
3855 | credits -= wrlen16; | |
3856 | } | |
3857 | ||
3858 | eosw_txq->cred += cpl->credits; | |
3859 | eosw_txq->ncompl--; | |
3860 | ||
3861 | spin_unlock(&eosw_txq->lock); | |
3862 | ||
3863 | /* Schedule a tasklet to reclaim SKBs and restart ETHOFLD Tx, | |
3864 | * if there were packets waiting for completion. | |
3865 | */ | |
3866 | tasklet_schedule(&eosw_txq->qresume_tsk); | |
3867 | } | |
3868 | ||
3869 | out_done: | |
3870 | return 0; | |
3871 | } | |
3872 | ||
fd3a4790 DM |
3873 | /* |
3874 | * The MSI-X interrupt handler for an SGE response queue. | |
3875 | */ | |
3876 | irqreturn_t t4_sge_intr_msix(int irq, void *cookie) | |
3877 | { | |
3878 | struct sge_rspq *q = cookie; | |
3879 | ||
3880 | napi_schedule(&q->napi); | |
3881 | return IRQ_HANDLED; | |
3882 | } | |
3883 | ||
3884 | /* | |
3885 | * Process the indirect interrupt entries in the interrupt queue and kick off | |
3886 | * NAPI for each queue that has generated an entry. | |
3887 | */ | |
3888 | static unsigned int process_intrq(struct adapter *adap) | |
3889 | { | |
3890 | unsigned int credits; | |
3891 | const struct rsp_ctrl *rc; | |
3892 | struct sge_rspq *q = &adap->sge.intrq; | |
d63a6dcf | 3893 | u32 val; |
fd3a4790 DM |
3894 | |
3895 | spin_lock(&adap->sge.intrq_lock); | |
3896 | for (credits = 0; ; credits++) { | |
3897 | rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc)); | |
3898 | if (!is_new_response(rc, q)) | |
3899 | break; | |
3900 | ||
019be1cf | 3901 | dma_rmb(); |
1ecc7b7a | 3902 | if (RSPD_TYPE_G(rc->type_gen) == RSPD_TYPE_INTR_X) { |
fd3a4790 DM |
3903 | unsigned int qid = ntohl(rc->pldbuflen_qid); |
3904 | ||
e46dab4d | 3905 | qid -= adap->sge.ingr_start; |
fd3a4790 DM |
3906 | napi_schedule(&adap->sge.ingr_map[qid]->napi); |
3907 | } | |
3908 | ||
3909 | rspq_next(q); | |
3910 | } | |
3911 | ||
f612b815 | 3912 | val = CIDXINC_V(credits) | SEINTARM_V(q->intr_params); |
df64e4d3 HS |
3913 | |
3914 | /* If we don't have access to the new User GTS (T5+), use the old | |
3915 | * doorbell mechanism; otherwise use the new BAR2 mechanism. | |
3916 | */ | |
3917 | if (unlikely(q->bar2_addr == NULL)) { | |
f612b815 HS |
3918 | t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), |
3919 | val | INGRESSQID_V(q->cntxt_id)); | |
d63a6dcf | 3920 | } else { |
f612b815 | 3921 | writel(val | INGRESSQID_V(q->bar2_qid), |
df64e4d3 | 3922 | q->bar2_addr + SGE_UDB_GTS); |
d63a6dcf HS |
3923 | wmb(); |
3924 | } | |
fd3a4790 DM |
3925 | spin_unlock(&adap->sge.intrq_lock); |
3926 | return credits; | |
3927 | } | |
3928 | ||
3929 | /* | |
3930 | * The MSI interrupt handler, which handles data events from SGE response queues | |
3931 | * as well as error and other async events as they all use the same MSI vector. | |
3932 | */ | |
3933 | static irqreturn_t t4_intr_msi(int irq, void *cookie) | |
3934 | { | |
3935 | struct adapter *adap = cookie; | |
3936 | ||
80f61f19 | 3937 | if (adap->flags & CXGB4_MASTER_PF) |
c3c7b121 | 3938 | t4_slow_intr_handler(adap); |
fd3a4790 DM |
3939 | process_intrq(adap); |
3940 | return IRQ_HANDLED; | |
3941 | } | |
3942 | ||
3943 | /* | |
3944 | * Interrupt handler for legacy INTx interrupts. | |
3945 | * Handles data events from SGE response queues as well as error and other | |
3946 | * async events as they all use the same interrupt line. | |
3947 | */ | |
3948 | static irqreturn_t t4_intr_intx(int irq, void *cookie) | |
3949 | { | |
3950 | struct adapter *adap = cookie; | |
3951 | ||
f061de42 | 3952 | t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0); |
80f61f19 | 3953 | if (((adap->flags & CXGB4_MASTER_PF) && t4_slow_intr_handler(adap)) | |
c3c7b121 | 3954 | process_intrq(adap)) |
fd3a4790 DM |
3955 | return IRQ_HANDLED; |
3956 | return IRQ_NONE; /* probably shared interrupt */ | |
3957 | } | |
3958 | ||
3959 | /** | |
3960 | * t4_intr_handler - select the top-level interrupt handler | |
3961 | * @adap: the adapter | |
3962 | * | |
3963 | * Selects the top-level interrupt handler based on the type of interrupts | |
3964 | * (MSI-X, MSI, or INTx). | |
3965 | */ | |
3966 | irq_handler_t t4_intr_handler(struct adapter *adap) | |
3967 | { | |
80f61f19 | 3968 | if (adap->flags & CXGB4_USING_MSIX) |
fd3a4790 | 3969 | return t4_sge_intr_msix; |
80f61f19 | 3970 | if (adap->flags & CXGB4_USING_MSI) |
fd3a4790 DM |
3971 | return t4_intr_msi; |
3972 | return t4_intr_intx; | |
3973 | } | |
3974 | ||
0e23daeb | 3975 | static void sge_rx_timer_cb(struct timer_list *t) |
fd3a4790 DM |
3976 | { |
3977 | unsigned long m; | |
a3bfb617 | 3978 | unsigned int i; |
0e23daeb | 3979 | struct adapter *adap = from_timer(adap, t, sge.rx_timer); |
fd3a4790 DM |
3980 | struct sge *s = &adap->sge; |
3981 | ||
4b8e27a8 | 3982 | for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++) |
fd3a4790 DM |
3983 | for (m = s->starving_fl[i]; m; m &= m - 1) { |
3984 | struct sge_eth_rxq *rxq; | |
3985 | unsigned int id = __ffs(m) + i * BITS_PER_LONG; | |
3986 | struct sge_fl *fl = s->egr_map[id]; | |
3987 | ||
3988 | clear_bit(id, s->starving_fl); | |
4e857c58 | 3989 | smp_mb__after_atomic(); |
fd3a4790 | 3990 | |
c098b026 | 3991 | if (fl_starving(adap, fl)) { |
fd3a4790 DM |
3992 | rxq = container_of(fl, struct sge_eth_rxq, fl); |
3993 | if (napi_reschedule(&rxq->rspq.napi)) | |
3994 | fl->starving++; | |
3995 | else | |
3996 | set_bit(id, s->starving_fl); | |
3997 | } | |
3998 | } | |
a3bfb617 HS |
3999 | /* The remainder of the SGE RX Timer Callback routine is dedicated to |
4000 | * global Master PF activities like checking for chip ingress stalls, | |
4001 | * etc. | |
4002 | */ | |
80f61f19 | 4003 | if (!(adap->flags & CXGB4_MASTER_PF)) |
a3bfb617 | 4004 | goto done; |
fd3a4790 | 4005 | |
a3bfb617 | 4006 | t4_idma_monitor(adap, &s->idma_monitor, HZ, RX_QCHECK_PERIOD); |
fd3a4790 | 4007 | |
a3bfb617 | 4008 | done: |
fd3a4790 DM |
4009 | mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD); |
4010 | } | |
4011 | ||
0e23daeb | 4012 | static void sge_tx_timer_cb(struct timer_list *t) |
fd3a4790 | 4013 | { |
0e23daeb | 4014 | struct adapter *adap = from_timer(adap, t, sge.tx_timer); |
fd3a4790 | 4015 | struct sge *s = &adap->sge; |
d429005f VK |
4016 | unsigned long m, period; |
4017 | unsigned int i, budget; | |
fd3a4790 | 4018 | |
4b8e27a8 | 4019 | for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++) |
fd3a4790 DM |
4020 | for (m = s->txq_maperr[i]; m; m &= m - 1) { |
4021 | unsigned long id = __ffs(m) + i * BITS_PER_LONG; | |
ab677ff4 | 4022 | struct sge_uld_txq *txq = s->egr_map[id]; |
fd3a4790 DM |
4023 | |
4024 | clear_bit(id, s->txq_maperr); | |
4025 | tasklet_schedule(&txq->qresume_tsk); | |
4026 | } | |
4027 | ||
a4569504 AG |
4028 | if (!is_t4(adap->params.chip)) { |
4029 | struct sge_eth_txq *q = &s->ptptxq; | |
4030 | int avail; | |
4031 | ||
4032 | spin_lock(&adap->ptp_lock); | |
4033 | avail = reclaimable(&q->q); | |
4034 | ||
4035 | if (avail) { | |
4036 | free_tx_desc(adap, &q->q, avail, false); | |
4037 | q->q.in_use -= avail; | |
4038 | } | |
4039 | spin_unlock(&adap->ptp_lock); | |
4040 | } | |
4041 | ||
fd3a4790 DM |
4042 | budget = MAX_TIMER_TX_RECLAIM; |
4043 | i = s->ethtxq_rover; | |
4044 | do { | |
d429005f VK |
4045 | budget -= t4_sge_eth_txq_egress_update(adap, &s->ethtxq[i], |
4046 | budget); | |
4047 | if (!budget) | |
4048 | break; | |
fd3a4790 DM |
4049 | |
4050 | if (++i >= s->ethqsets) | |
4051 | i = 0; | |
d429005f | 4052 | } while (i != s->ethtxq_rover); |
fd3a4790 | 4053 | s->ethtxq_rover = i; |
d429005f VK |
4054 | |
4055 | if (budget == 0) { | |
4056 | /* If we found too many reclaimable packets schedule a timer | |
4057 | * in the near future to continue where we left off. | |
4058 | */ | |
4059 | period = 2; | |
4060 | } else { | |
4061 | /* We reclaimed all reclaimable TX Descriptors, so reschedule | |
4062 | * at the normal period. | |
4063 | */ | |
4064 | period = TX_QCHECK_PERIOD; | |
4065 | } | |
4066 | ||
4067 | mod_timer(&s->tx_timer, jiffies + period); | |
fd3a4790 DM |
4068 | } |
4069 | ||
d63a6dcf | 4070 | /** |
df64e4d3 HS |
4071 | * bar2_address - return the BAR2 address for an SGE Queue's Registers |
4072 | * @adapter: the adapter | |
4073 | * @qid: the SGE Queue ID | |
4074 | * @qtype: the SGE Queue Type (Egress or Ingress) | |
4075 | * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues | |
d63a6dcf | 4076 | * |
df64e4d3 HS |
4077 | * Returns the BAR2 address for the SGE Queue Registers associated with |
4078 | * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also | |
4079 | * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE | |
4080 | * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID" | |
4081 | * Registers are supported (e.g. the Write Combining Doorbell Buffer). | |
4082 | */ | |
4083 | static void __iomem *bar2_address(struct adapter *adapter, | |
4084 | unsigned int qid, | |
4085 | enum t4_bar2_qtype qtype, | |
4086 | unsigned int *pbar2_qid) | |
4087 | { | |
4088 | u64 bar2_qoffset; | |
4089 | int ret; | |
d63a6dcf | 4090 | |
e0456717 | 4091 | ret = t4_bar2_sge_qregs(adapter, qid, qtype, 0, |
df64e4d3 HS |
4092 | &bar2_qoffset, pbar2_qid); |
4093 | if (ret) | |
4094 | return NULL; | |
d63a6dcf | 4095 | |
df64e4d3 | 4096 | return adapter->bar2 + bar2_qoffset; |
d63a6dcf HS |
4097 | } |
4098 | ||
145ef8a5 HS |
4099 | /* @intr_idx: MSI/MSI-X vector if >=0, -(absolute qid + 1) if < 0 |
4100 | * @cong: < 0 -> no congestion feedback, >= 0 -> congestion channel map | |
4101 | */ | |
fd3a4790 DM |
4102 | int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, |
4103 | struct net_device *dev, int intr_idx, | |
2337ba42 VP |
4104 | struct sge_fl *fl, rspq_handler_t hnd, |
4105 | rspq_flush_handler_t flush_hnd, int cong) | |
fd3a4790 DM |
4106 | { |
4107 | int ret, flsz = 0; | |
4108 | struct fw_iq_cmd c; | |
52367a76 | 4109 | struct sge *s = &adap->sge; |
fd3a4790 | 4110 | struct port_info *pi = netdev_priv(dev); |
80f61f19 | 4111 | int relaxed = !(adap->flags & CXGB4_ROOT_NO_RELAXED_ORDERING); |
fd3a4790 DM |
4112 | |
4113 | /* Size needs to be multiple of 16, including status entry. */ | |
4114 | iq->size = roundup(iq->size, 16); | |
4115 | ||
4116 | iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0, | |
0ac5b708 HS |
4117 | &iq->phys_addr, NULL, 0, |
4118 | dev_to_node(adap->pdev_dev)); | |
fd3a4790 DM |
4119 | if (!iq->desc) |
4120 | return -ENOMEM; | |
4121 | ||
4122 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
4123 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F | |
4124 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | | |
b2612722 | 4125 | FW_IQ_CMD_PFN_V(adap->pf) | FW_IQ_CMD_VFN_V(0)); |
6e4b51a6 | 4126 | c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | FW_IQ_CMD_IQSTART_F | |
fd3a4790 | 4127 | FW_LEN16(c)); |
6e4b51a6 HS |
4128 | c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) | |
4129 | FW_IQ_CMD_IQASYNCH_V(fwevtq) | FW_IQ_CMD_VIID_V(pi->viid) | | |
1ecc7b7a HS |
4130 | FW_IQ_CMD_IQANDST_V(intr_idx < 0) | |
4131 | FW_IQ_CMD_IQANUD_V(UPDATEDELIVERY_INTERRUPT_X) | | |
6e4b51a6 | 4132 | FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx : |
fd3a4790 | 4133 | -intr_idx - 1)); |
6e4b51a6 HS |
4134 | c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) | |
4135 | FW_IQ_CMD_IQGTSMODE_F | | |
4136 | FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) | | |
4137 | FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4)); | |
fd3a4790 DM |
4138 | c.iqsize = htons(iq->size); |
4139 | c.iqaddr = cpu_to_be64(iq->phys_addr); | |
145ef8a5 | 4140 | if (cong >= 0) |
8dce04f1 AV |
4141 | c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F | |
4142 | FW_IQ_CMD_IQTYPE_V(cong ? FW_IQ_IQTYPE_NIC | |
4143 | : FW_IQ_IQTYPE_OFLD)); | |
fd3a4790 DM |
4144 | |
4145 | if (fl) { | |
d429005f VK |
4146 | unsigned int chip_ver = |
4147 | CHELSIO_CHIP_VERSION(adap->params.chip); | |
3ccc6cf7 | 4148 | |
13432997 HS |
4149 | /* Allocate the ring for the hardware free list (with space |
4150 | * for its status page) along with the associated software | |
4151 | * descriptor ring. The free list size needs to be a multiple | |
4152 | * of the Egress Queue Unit and at least 2 Egress Units larger | |
4153 | * than the SGE's Egress Congrestion Threshold | |
4154 | * (fl_starve_thres - 1). | |
4155 | */ | |
4156 | if (fl->size < s->fl_starve_thres - 1 + 2 * 8) | |
4157 | fl->size = s->fl_starve_thres - 1 + 2 * 8; | |
fd3a4790 DM |
4158 | fl->size = roundup(fl->size, 8); |
4159 | fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64), | |
4160 | sizeof(struct rx_sw_desc), &fl->addr, | |
0ac5b708 HS |
4161 | &fl->sdesc, s->stat_len, |
4162 | dev_to_node(adap->pdev_dev)); | |
fd3a4790 DM |
4163 | if (!fl->desc) |
4164 | goto fl_nomem; | |
4165 | ||
52367a76 | 4166 | flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc); |
145ef8a5 | 4167 | c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F | |
b0ba9d5f CL |
4168 | FW_IQ_CMD_FL0FETCHRO_V(relaxed) | |
4169 | FW_IQ_CMD_FL0DATARO_V(relaxed) | | |
145ef8a5 HS |
4170 | FW_IQ_CMD_FL0PADEN_F); |
4171 | if (cong >= 0) | |
4172 | c.iqns_to_fl0congen |= | |
4173 | htonl(FW_IQ_CMD_FL0CNGCHMAP_V(cong) | | |
4174 | FW_IQ_CMD_FL0CONGCIF_F | | |
4175 | FW_IQ_CMD_FL0CONGEN_F); | |
edadad80 HS |
4176 | /* In T6, for egress queue type FL there is internal overhead |
4177 | * of 16B for header going into FLM module. Hence the maximum | |
4178 | * allowed burst size is 448 bytes. For T4/T5, the hardware | |
4179 | * doesn't coalesce fetch requests if more than 64 bytes of | |
4180 | * Free List pointers are provided, so we use a 128-byte Fetch | |
4181 | * Burst Minimum there (T6 implements coalescing so we can use | |
4182 | * the smaller 64-byte value there). | |
4183 | */ | |
1ecc7b7a | 4184 | c.fl0dcaen_to_fl0cidxfthresh = |
d429005f | 4185 | htons(FW_IQ_CMD_FL0FBMIN_V(chip_ver <= CHELSIO_T5 ? |
edadad80 | 4186 | FETCHBURSTMIN_128B_X : |
d429005f VK |
4187 | FETCHBURSTMIN_64B_T6_X) | |
4188 | FW_IQ_CMD_FL0FBMAX_V((chip_ver <= CHELSIO_T5) ? | |
3ccc6cf7 HS |
4189 | FETCHBURSTMAX_512B_X : |
4190 | FETCHBURSTMAX_256B_X)); | |
fd3a4790 DM |
4191 | c.fl0size = htons(flsz); |
4192 | c.fl0addr = cpu_to_be64(fl->addr); | |
4193 | } | |
4194 | ||
b2612722 | 4195 | ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); |
fd3a4790 DM |
4196 | if (ret) |
4197 | goto err; | |
4198 | ||
4199 | netif_napi_add(dev, &iq->napi, napi_rx_handler, 64); | |
4200 | iq->cur_desc = iq->desc; | |
4201 | iq->cidx = 0; | |
4202 | iq->gen = 1; | |
4203 | iq->next_intr_params = iq->intr_params; | |
4204 | iq->cntxt_id = ntohs(c.iqid); | |
4205 | iq->abs_id = ntohs(c.physiqid); | |
df64e4d3 HS |
4206 | iq->bar2_addr = bar2_address(adap, |
4207 | iq->cntxt_id, | |
4208 | T4_BAR2_QTYPE_INGRESS, | |
4209 | &iq->bar2_qid); | |
fd3a4790 | 4210 | iq->size--; /* subtract status entry */ |
fd3a4790 DM |
4211 | iq->netdev = dev; |
4212 | iq->handler = hnd; | |
2337ba42 VP |
4213 | iq->flush_handler = flush_hnd; |
4214 | ||
4215 | memset(&iq->lro_mgr, 0, sizeof(struct t4_lro_mgr)); | |
4216 | skb_queue_head_init(&iq->lro_mgr.lroq); | |
fd3a4790 DM |
4217 | |
4218 | /* set offset to -1 to distinguish ingress queues without FL */ | |
4219 | iq->offset = fl ? 0 : -1; | |
4220 | ||
e46dab4d | 4221 | adap->sge.ingr_map[iq->cntxt_id - adap->sge.ingr_start] = iq; |
fd3a4790 DM |
4222 | |
4223 | if (fl) { | |
62718b32 | 4224 | fl->cntxt_id = ntohs(c.fl0id); |
fd3a4790 DM |
4225 | fl->avail = fl->pend_cred = 0; |
4226 | fl->pidx = fl->cidx = 0; | |
4227 | fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0; | |
e46dab4d | 4228 | adap->sge.egr_map[fl->cntxt_id - adap->sge.egr_start] = fl; |
d63a6dcf | 4229 | |
df64e4d3 HS |
4230 | /* Note, we must initialize the BAR2 Free List User Doorbell |
4231 | * information before refilling the Free List! | |
d63a6dcf | 4232 | */ |
df64e4d3 HS |
4233 | fl->bar2_addr = bar2_address(adap, |
4234 | fl->cntxt_id, | |
4235 | T4_BAR2_QTYPE_EGRESS, | |
4236 | &fl->bar2_qid); | |
fd3a4790 DM |
4237 | refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL); |
4238 | } | |
b8b1ae99 HS |
4239 | |
4240 | /* For T5 and later we attempt to set up the Congestion Manager values | |
4241 | * of the new RX Ethernet Queue. This should really be handled by | |
4242 | * firmware because it's more complex than any host driver wants to | |
4243 | * get involved with and it's different per chip and this is almost | |
4244 | * certainly wrong. Firmware would be wrong as well, but it would be | |
4245 | * a lot easier to fix in one place ... For now we do something very | |
4246 | * simple (and hopefully less wrong). | |
4247 | */ | |
4248 | if (!is_t4(adap->params.chip) && cong >= 0) { | |
2216d014 | 4249 | u32 param, val, ch_map = 0; |
b8b1ae99 | 4250 | int i; |
2216d014 | 4251 | u16 cng_ch_bits_log = adap->params.arch.cng_ch_bits_log; |
b8b1ae99 HS |
4252 | |
4253 | param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | | |
4254 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | | |
4255 | FW_PARAMS_PARAM_YZ_V(iq->cntxt_id)); | |
4256 | if (cong == 0) { | |
4257 | val = CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_QUEUE_X); | |
4258 | } else { | |
4259 | val = | |
4260 | CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X); | |
4261 | for (i = 0; i < 4; i++) { | |
4262 | if (cong & (1 << i)) | |
2216d014 | 4263 | ch_map |= 1 << (i << cng_ch_bits_log); |
b8b1ae99 | 4264 | } |
2216d014 | 4265 | val |= CONMCTXT_CNGCHMAP_V(ch_map); |
b8b1ae99 | 4266 | } |
b2612722 | 4267 | ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, |
b8b1ae99 HS |
4268 | ¶m, &val); |
4269 | if (ret) | |
4270 | dev_warn(adap->pdev_dev, "Failed to set Congestion" | |
4271 | " Manager Context for Ingress Queue %d: %d\n", | |
4272 | iq->cntxt_id, -ret); | |
4273 | } | |
4274 | ||
fd3a4790 DM |
4275 | return 0; |
4276 | ||
4277 | fl_nomem: | |
4278 | ret = -ENOMEM; | |
4279 | err: | |
4280 | if (iq->desc) { | |
4281 | dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len, | |
4282 | iq->desc, iq->phys_addr); | |
4283 | iq->desc = NULL; | |
4284 | } | |
4285 | if (fl && fl->desc) { | |
4286 | kfree(fl->sdesc); | |
4287 | fl->sdesc = NULL; | |
4288 | dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc), | |
4289 | fl->desc, fl->addr); | |
4290 | fl->desc = NULL; | |
4291 | } | |
4292 | return ret; | |
4293 | } | |
4294 | ||
4295 | static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id) | |
4296 | { | |
22adfe0a | 4297 | q->cntxt_id = id; |
df64e4d3 HS |
4298 | q->bar2_addr = bar2_address(adap, |
4299 | q->cntxt_id, | |
4300 | T4_BAR2_QTYPE_EGRESS, | |
4301 | &q->bar2_qid); | |
fd3a4790 DM |
4302 | q->in_use = 0; |
4303 | q->cidx = q->pidx = 0; | |
4304 | q->stops = q->restarts = 0; | |
4305 | q->stat = (void *)&q->desc[q->size]; | |
3069ee9b | 4306 | spin_lock_init(&q->db_lock); |
e46dab4d | 4307 | adap->sge.egr_map[id - adap->sge.egr_start] = q; |
fd3a4790 DM |
4308 | } |
4309 | ||
d429005f VK |
4310 | /** |
4311 | * t4_sge_alloc_eth_txq - allocate an Ethernet TX Queue | |
4312 | * @adap: the adapter | |
4313 | * @txq: the SGE Ethernet TX Queue to initialize | |
4314 | * @dev: the Linux Network Device | |
4315 | * @netdevq: the corresponding Linux TX Queue | |
4316 | * @iqid: the Ingress Queue to which to deliver CIDX Update messages | |
4317 | * @dbqt: whether this TX Queue will use the SGE Doorbell Queue Timers | |
4318 | */ | |
fd3a4790 DM |
4319 | int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, |
4320 | struct net_device *dev, struct netdev_queue *netdevq, | |
d429005f | 4321 | unsigned int iqid, u8 dbqt) |
fd3a4790 | 4322 | { |
d429005f | 4323 | unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); |
fd3a4790 | 4324 | struct port_info *pi = netdev_priv(dev); |
d429005f VK |
4325 | struct sge *s = &adap->sge; |
4326 | struct fw_eq_eth_cmd c; | |
4327 | int ret, nentries; | |
fd3a4790 DM |
4328 | |
4329 | /* Add status entries */ | |
52367a76 | 4330 | nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); |
fd3a4790 DM |
4331 | |
4332 | txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size, | |
4333 | sizeof(struct tx_desc), sizeof(struct tx_sw_desc), | |
52367a76 | 4334 | &txq->q.phys_addr, &txq->q.sdesc, s->stat_len, |
ad6bad3e | 4335 | netdev_queue_numa_node_read(netdevq)); |
fd3a4790 DM |
4336 | if (!txq->q.desc) |
4337 | return -ENOMEM; | |
4338 | ||
4339 | memset(&c, 0, sizeof(c)); | |
e2ac9628 HS |
4340 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F | |
4341 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | | |
b2612722 | 4342 | FW_EQ_ETH_CMD_PFN_V(adap->pf) | |
6e4b51a6 HS |
4343 | FW_EQ_ETH_CMD_VFN_V(0)); |
4344 | c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F | | |
4345 | FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c)); | |
d429005f VK |
4346 | |
4347 | /* For TX Ethernet Queues using the SGE Doorbell Queue Timer | |
4348 | * mechanism, we use Ingress Queue messages for Hardware Consumer | |
4349 | * Index Updates on the TX Queue. Otherwise we have the Hardware | |
4350 | * write the CIDX Updates into the Status Page at the end of the | |
4351 | * TX Queue. | |
4352 | */ | |
7c3bebc3 | 4353 | c.autoequiqe_to_viid = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE_F | |
d429005f VK |
4354 | FW_EQ_ETH_CMD_VIID_V(pi->viid)); |
4355 | ||
1ecc7b7a | 4356 | c.fetchszm_to_iqid = |
7c3bebc3 | 4357 | htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) | |
1ecc7b7a HS |
4358 | FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) | |
4359 | FW_EQ_ETH_CMD_FETCHRO_F | FW_EQ_ETH_CMD_IQID_V(iqid)); | |
d429005f VK |
4360 | |
4361 | /* Note that the CIDX Flush Threshold should match MAX_TX_RECLAIM. */ | |
1ecc7b7a | 4362 | c.dcaen_to_eqsize = |
d429005f VK |
4363 | htonl(FW_EQ_ETH_CMD_FBMIN_V(chip_ver <= CHELSIO_T5 |
4364 | ? FETCHBURSTMIN_64B_X | |
4365 | : FETCHBURSTMIN_64B_T6_X) | | |
1ecc7b7a HS |
4366 | FW_EQ_ETH_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) | |
4367 | FW_EQ_ETH_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) | | |
4368 | FW_EQ_ETH_CMD_EQSIZE_V(nentries)); | |
d429005f | 4369 | |
fd3a4790 DM |
4370 | c.eqaddr = cpu_to_be64(txq->q.phys_addr); |
4371 | ||
d429005f VK |
4372 | /* If we're using the SGE Doorbell Queue Timer mechanism, pass in the |
4373 | * currently configured Timer Index. THis can be changed later via an | |
4374 | * ethtool -C tx-usecs {Timer Val} command. Note that the SGE | |
4375 | * Doorbell Queue mode is currently automatically enabled in the | |
4376 | * Firmware by setting either AUTOEQUEQE or AUTOEQUIQE ... | |
4377 | */ | |
4378 | if (dbqt) | |
4379 | c.timeren_timerix = | |
4380 | cpu_to_be32(FW_EQ_ETH_CMD_TIMEREN_F | | |
4381 | FW_EQ_ETH_CMD_TIMERIX_V(txq->dbqtimerix)); | |
4382 | ||
b2612722 | 4383 | ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); |
fd3a4790 DM |
4384 | if (ret) { |
4385 | kfree(txq->q.sdesc); | |
4386 | txq->q.sdesc = NULL; | |
4387 | dma_free_coherent(adap->pdev_dev, | |
4388 | nentries * sizeof(struct tx_desc), | |
4389 | txq->q.desc, txq->q.phys_addr); | |
4390 | txq->q.desc = NULL; | |
4391 | return ret; | |
4392 | } | |
4393 | ||
ab677ff4 | 4394 | txq->q.q_type = CXGB4_TXQ_ETH; |
6e4b51a6 | 4395 | init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd))); |
fd3a4790 | 4396 | txq->txq = netdevq; |
1a2a14fb RL |
4397 | txq->tso = 0; |
4398 | txq->uso = 0; | |
4399 | txq->tx_cso = 0; | |
4400 | txq->vlan_ins = 0; | |
fd3a4790 | 4401 | txq->mapping_err = 0; |
d429005f VK |
4402 | txq->dbqt = dbqt; |
4403 | ||
fd3a4790 DM |
4404 | return 0; |
4405 | } | |
4406 | ||
4407 | int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, | |
4408 | struct net_device *dev, unsigned int iqid, | |
4409 | unsigned int cmplqid) | |
4410 | { | |
d429005f | 4411 | unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); |
fd3a4790 | 4412 | struct port_info *pi = netdev_priv(dev); |
d429005f VK |
4413 | struct sge *s = &adap->sge; |
4414 | struct fw_eq_ctrl_cmd c; | |
4415 | int ret, nentries; | |
fd3a4790 DM |
4416 | |
4417 | /* Add status entries */ | |
52367a76 | 4418 | nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc); |
fd3a4790 DM |
4419 | |
4420 | txq->q.desc = alloc_ring(adap->pdev_dev, nentries, | |
4421 | sizeof(struct tx_desc), 0, &txq->q.phys_addr, | |
982b81eb | 4422 | NULL, 0, dev_to_node(adap->pdev_dev)); |
fd3a4790 DM |
4423 | if (!txq->q.desc) |
4424 | return -ENOMEM; | |
4425 | ||
e2ac9628 HS |
4426 | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F | |
4427 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | | |
b2612722 | 4428 | FW_EQ_CTRL_CMD_PFN_V(adap->pf) | |
6e4b51a6 HS |
4429 | FW_EQ_CTRL_CMD_VFN_V(0)); |
4430 | c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F | | |
4431 | FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c)); | |
4432 | c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid)); | |
fd3a4790 | 4433 | c.physeqid_pkd = htonl(0); |
1ecc7b7a HS |
4434 | c.fetchszm_to_iqid = |
4435 | htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) | | |
4436 | FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) | | |
4437 | FW_EQ_CTRL_CMD_FETCHRO_F | FW_EQ_CTRL_CMD_IQID_V(iqid)); | |
4438 | c.dcaen_to_eqsize = | |
d429005f VK |
4439 | htonl(FW_EQ_CTRL_CMD_FBMIN_V(chip_ver <= CHELSIO_T5 |
4440 | ? FETCHBURSTMIN_64B_X | |
4441 | : FETCHBURSTMIN_64B_T6_X) | | |
1ecc7b7a HS |
4442 | FW_EQ_CTRL_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) | |
4443 | FW_EQ_CTRL_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) | | |
4444 | FW_EQ_CTRL_CMD_EQSIZE_V(nentries)); | |
fd3a4790 DM |
4445 | c.eqaddr = cpu_to_be64(txq->q.phys_addr); |
4446 | ||
b2612722 | 4447 | ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); |
fd3a4790 DM |
4448 | if (ret) { |
4449 | dma_free_coherent(adap->pdev_dev, | |
4450 | nentries * sizeof(struct tx_desc), | |
4451 | txq->q.desc, txq->q.phys_addr); | |
4452 | txq->q.desc = NULL; | |
4453 | return ret; | |
4454 | } | |
4455 | ||
ab677ff4 | 4456 | txq->q.q_type = CXGB4_TXQ_CTRL; |
6e4b51a6 | 4457 | init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid))); |
fd3a4790 DM |
4458 | txq->adap = adap; |
4459 | skb_queue_head_init(&txq->sendq); | |
4460 | tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq); | |
4461 | txq->full = 0; | |
4462 | return 0; | |
4463 | } | |
4464 | ||
0fbc81b3 HS |
4465 | int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid, |
4466 | unsigned int cmplqid) | |
4467 | { | |
4468 | u32 param, val; | |
4469 | ||
4470 | param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | | |
4471 | FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL) | | |
4472 | FW_PARAMS_PARAM_YZ_V(eqid)); | |
4473 | val = cmplqid; | |
4474 | return t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); | |
4475 | } | |
4476 | ||
2d0cb84d RL |
4477 | static int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_txq *q, |
4478 | struct net_device *dev, u32 cmd, u32 iqid) | |
fd3a4790 | 4479 | { |
d429005f | 4480 | unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip); |
fd3a4790 | 4481 | struct port_info *pi = netdev_priv(dev); |
2d0cb84d RL |
4482 | struct sge *s = &adap->sge; |
4483 | struct fw_eq_ofld_cmd c; | |
4484 | u32 fb_min, nentries; | |
4485 | int ret; | |
fd3a4790 DM |
4486 | |
4487 | /* Add status entries */ | |
2d0cb84d RL |
4488 | nentries = q->size + s->stat_len / sizeof(struct tx_desc); |
4489 | q->desc = alloc_ring(adap->pdev_dev, q->size, sizeof(struct tx_desc), | |
4490 | sizeof(struct tx_sw_desc), &q->phys_addr, | |
4491 | &q->sdesc, s->stat_len, NUMA_NO_NODE); | |
4492 | if (!q->desc) | |
fd3a4790 DM |
4493 | return -ENOMEM; |
4494 | ||
2d0cb84d RL |
4495 | if (chip_ver <= CHELSIO_T5) |
4496 | fb_min = FETCHBURSTMIN_64B_X; | |
4497 | else | |
4498 | fb_min = FETCHBURSTMIN_64B_T6_X; | |
4499 | ||
fd3a4790 | 4500 | memset(&c, 0, sizeof(c)); |
ab677ff4 | 4501 | c.op_to_vfn = htonl(FW_CMD_OP_V(cmd) | FW_CMD_REQUEST_F | |
e2ac9628 | 4502 | FW_CMD_WRITE_F | FW_CMD_EXEC_F | |
b2612722 | 4503 | FW_EQ_OFLD_CMD_PFN_V(adap->pf) | |
6e4b51a6 HS |
4504 | FW_EQ_OFLD_CMD_VFN_V(0)); |
4505 | c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F | | |
4506 | FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c)); | |
1ecc7b7a HS |
4507 | c.fetchszm_to_iqid = |
4508 | htonl(FW_EQ_OFLD_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) | | |
4509 | FW_EQ_OFLD_CMD_PCIECHN_V(pi->tx_chan) | | |
4510 | FW_EQ_OFLD_CMD_FETCHRO_F | FW_EQ_OFLD_CMD_IQID_V(iqid)); | |
4511 | c.dcaen_to_eqsize = | |
2d0cb84d | 4512 | htonl(FW_EQ_OFLD_CMD_FBMIN_V(fb_min) | |
1ecc7b7a HS |
4513 | FW_EQ_OFLD_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) | |
4514 | FW_EQ_OFLD_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) | | |
4515 | FW_EQ_OFLD_CMD_EQSIZE_V(nentries)); | |
2d0cb84d | 4516 | c.eqaddr = cpu_to_be64(q->phys_addr); |
fd3a4790 | 4517 | |
b2612722 | 4518 | ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); |
fd3a4790 | 4519 | if (ret) { |
2d0cb84d RL |
4520 | kfree(q->sdesc); |
4521 | q->sdesc = NULL; | |
fd3a4790 DM |
4522 | dma_free_coherent(adap->pdev_dev, |
4523 | nentries * sizeof(struct tx_desc), | |
2d0cb84d RL |
4524 | q->desc, q->phys_addr); |
4525 | q->desc = NULL; | |
fd3a4790 DM |
4526 | return ret; |
4527 | } | |
4528 | ||
2d0cb84d RL |
4529 | init_txq(adap, q, FW_EQ_OFLD_CMD_EQID_G(ntohl(c.eqid_pkd))); |
4530 | return 0; | |
4531 | } | |
4532 | ||
4533 | int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq, | |
4534 | struct net_device *dev, unsigned int iqid, | |
4535 | unsigned int uld_type) | |
4536 | { | |
4537 | u32 cmd = FW_EQ_OFLD_CMD; | |
4538 | int ret; | |
4539 | ||
4540 | if (unlikely(uld_type == CXGB4_TX_CRYPTO)) | |
4541 | cmd = FW_EQ_CTRL_CMD; | |
4542 | ||
4543 | ret = t4_sge_alloc_ofld_txq(adap, &txq->q, dev, cmd, iqid); | |
4544 | if (ret) | |
4545 | return ret; | |
4546 | ||
ab677ff4 | 4547 | txq->q.q_type = CXGB4_TXQ_ULD; |
fd3a4790 DM |
4548 | txq->adap = adap; |
4549 | skb_queue_head_init(&txq->sendq); | |
4550 | tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq); | |
4551 | txq->full = 0; | |
4552 | txq->mapping_err = 0; | |
4553 | return 0; | |
4554 | } | |
4555 | ||
2d0cb84d RL |
4556 | int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq, |
4557 | struct net_device *dev, u32 iqid) | |
4558 | { | |
4559 | int ret; | |
4560 | ||
4561 | ret = t4_sge_alloc_ofld_txq(adap, &txq->q, dev, FW_EQ_OFLD_CMD, iqid); | |
4562 | if (ret) | |
4563 | return ret; | |
4564 | ||
4565 | txq->q.q_type = CXGB4_TXQ_ULD; | |
4566 | spin_lock_init(&txq->lock); | |
4567 | txq->adap = adap; | |
4568 | txq->tso = 0; | |
8311f0be | 4569 | txq->uso = 0; |
2d0cb84d RL |
4570 | txq->tx_cso = 0; |
4571 | txq->vlan_ins = 0; | |
4572 | txq->mapping_err = 0; | |
4573 | return 0; | |
4574 | } | |
4575 | ||
ab677ff4 | 4576 | void free_txq(struct adapter *adap, struct sge_txq *q) |
fd3a4790 | 4577 | { |
52367a76 VP |
4578 | struct sge *s = &adap->sge; |
4579 | ||
fd3a4790 | 4580 | dma_free_coherent(adap->pdev_dev, |
52367a76 | 4581 | q->size * sizeof(struct tx_desc) + s->stat_len, |
fd3a4790 DM |
4582 | q->desc, q->phys_addr); |
4583 | q->cntxt_id = 0; | |
4584 | q->sdesc = NULL; | |
4585 | q->desc = NULL; | |
4586 | } | |
4587 | ||
94cdb8bb HS |
4588 | void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, |
4589 | struct sge_fl *fl) | |
fd3a4790 | 4590 | { |
52367a76 | 4591 | struct sge *s = &adap->sge; |
fd3a4790 DM |
4592 | unsigned int fl_id = fl ? fl->cntxt_id : 0xffff; |
4593 | ||
e46dab4d | 4594 | adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL; |
b2612722 | 4595 | t4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP, |
060e0c75 | 4596 | rq->cntxt_id, fl_id, 0xffff); |
fd3a4790 DM |
4597 | dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len, |
4598 | rq->desc, rq->phys_addr); | |
4599 | netif_napi_del(&rq->napi); | |
4600 | rq->netdev = NULL; | |
4601 | rq->cntxt_id = rq->abs_id = 0; | |
4602 | rq->desc = NULL; | |
4603 | ||
4604 | if (fl) { | |
4605 | free_rx_bufs(adap, fl, fl->avail); | |
52367a76 | 4606 | dma_free_coherent(adap->pdev_dev, fl->size * 8 + s->stat_len, |
fd3a4790 DM |
4607 | fl->desc, fl->addr); |
4608 | kfree(fl->sdesc); | |
4609 | fl->sdesc = NULL; | |
4610 | fl->cntxt_id = 0; | |
4611 | fl->desc = NULL; | |
4612 | } | |
4613 | } | |
4614 | ||
5fa76694 HS |
4615 | /** |
4616 | * t4_free_ofld_rxqs - free a block of consecutive Rx queues | |
4617 | * @adap: the adapter | |
4618 | * @n: number of queues | |
4619 | * @q: pointer to first queue | |
4620 | * | |
4621 | * Release the resources of a consecutive block of offload Rx queues. | |
4622 | */ | |
4623 | void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q) | |
4624 | { | |
4625 | for ( ; n; n--, q++) | |
4626 | if (q->rspq.desc) | |
4627 | free_rspq_fl(adap, &q->rspq, | |
4628 | q->fl.size ? &q->fl : NULL); | |
4629 | } | |
4630 | ||
2d0cb84d RL |
4631 | void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq) |
4632 | { | |
4633 | if (txq->q.desc) { | |
4634 | t4_ofld_eq_free(adap, adap->mbox, adap->pf, 0, | |
4635 | txq->q.cntxt_id); | |
4636 | free_tx_desc(adap, &txq->q, txq->q.in_use, false); | |
4637 | kfree(txq->q.sdesc); | |
4638 | free_txq(adap, &txq->q); | |
4639 | } | |
4640 | } | |
4641 | ||
fd3a4790 DM |
4642 | /** |
4643 | * t4_free_sge_resources - free SGE resources | |
4644 | * @adap: the adapter | |
4645 | * | |
4646 | * Frees resources used by the SGE queue sets. | |
4647 | */ | |
4648 | void t4_free_sge_resources(struct adapter *adap) | |
4649 | { | |
4650 | int i; | |
ebf4dc2b HS |
4651 | struct sge_eth_rxq *eq; |
4652 | struct sge_eth_txq *etq; | |
4653 | ||
4654 | /* stop all Rx queues in order to start them draining */ | |
4655 | for (i = 0; i < adap->sge.ethqsets; i++) { | |
4656 | eq = &adap->sge.ethrxq[i]; | |
4657 | if (eq->rspq.desc) | |
4658 | t4_iq_stop(adap, adap->mbox, adap->pf, 0, | |
4659 | FW_IQ_TYPE_FL_INT_CAP, | |
4660 | eq->rspq.cntxt_id, | |
4661 | eq->fl.size ? eq->fl.cntxt_id : 0xffff, | |
4662 | 0xffff); | |
4663 | } | |
fd3a4790 DM |
4664 | |
4665 | /* clean up Ethernet Tx/Rx queues */ | |
ebf4dc2b HS |
4666 | for (i = 0; i < adap->sge.ethqsets; i++) { |
4667 | eq = &adap->sge.ethrxq[i]; | |
fd3a4790 | 4668 | if (eq->rspq.desc) |
5fa76694 HS |
4669 | free_rspq_fl(adap, &eq->rspq, |
4670 | eq->fl.size ? &eq->fl : NULL); | |
76c3a552 RL |
4671 | if (eq->msix) { |
4672 | cxgb4_free_msix_idx_in_bmap(adap, eq->msix->idx); | |
4673 | eq->msix = NULL; | |
4674 | } | |
ebf4dc2b HS |
4675 | |
4676 | etq = &adap->sge.ethtxq[i]; | |
fd3a4790 | 4677 | if (etq->q.desc) { |
b2612722 | 4678 | t4_eth_eq_free(adap, adap->mbox, adap->pf, 0, |
060e0c75 | 4679 | etq->q.cntxt_id); |
fbe80776 | 4680 | __netif_tx_lock_bh(etq->txq); |
fd3a4790 | 4681 | free_tx_desc(adap, &etq->q, etq->q.in_use, true); |
fbe80776 | 4682 | __netif_tx_unlock_bh(etq->txq); |
fd3a4790 DM |
4683 | kfree(etq->q.sdesc); |
4684 | free_txq(adap, &etq->q); | |
4685 | } | |
4686 | } | |
4687 | ||
fd3a4790 DM |
4688 | /* clean up control Tx queues */ |
4689 | for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) { | |
4690 | struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i]; | |
4691 | ||
4692 | if (cq->q.desc) { | |
4693 | tasklet_kill(&cq->qresume_tsk); | |
b2612722 | 4694 | t4_ctrl_eq_free(adap, adap->mbox, adap->pf, 0, |
060e0c75 | 4695 | cq->q.cntxt_id); |
fd3a4790 DM |
4696 | __skb_queue_purge(&cq->sendq); |
4697 | free_txq(adap, &cq->q); | |
4698 | } | |
4699 | } | |
4700 | ||
76c3a552 | 4701 | if (adap->sge.fw_evtq.desc) { |
fd3a4790 | 4702 | free_rspq_fl(adap, &adap->sge.fw_evtq, NULL); |
76c3a552 RL |
4703 | if (adap->sge.fwevtq_msix_idx >= 0) |
4704 | cxgb4_free_msix_idx_in_bmap(adap, | |
4705 | adap->sge.fwevtq_msix_idx); | |
4706 | } | |
4707 | ||
4708 | if (adap->sge.nd_msix_idx >= 0) | |
4709 | cxgb4_free_msix_idx_in_bmap(adap, adap->sge.nd_msix_idx); | |
fd3a4790 DM |
4710 | |
4711 | if (adap->sge.intrq.desc) | |
4712 | free_rspq_fl(adap, &adap->sge.intrq, NULL); | |
4713 | ||
a4569504 AG |
4714 | if (!is_t4(adap->params.chip)) { |
4715 | etq = &adap->sge.ptptxq; | |
4716 | if (etq->q.desc) { | |
4717 | t4_eth_eq_free(adap, adap->mbox, adap->pf, 0, | |
4718 | etq->q.cntxt_id); | |
4719 | spin_lock_bh(&adap->ptp_lock); | |
4720 | free_tx_desc(adap, &etq->q, etq->q.in_use, true); | |
4721 | spin_unlock_bh(&adap->ptp_lock); | |
4722 | kfree(etq->q.sdesc); | |
4723 | free_txq(adap, &etq->q); | |
4724 | } | |
4725 | } | |
4726 | ||
fd3a4790 | 4727 | /* clear the reverse egress queue map */ |
4b8e27a8 HS |
4728 | memset(adap->sge.egr_map, 0, |
4729 | adap->sge.egr_sz * sizeof(*adap->sge.egr_map)); | |
fd3a4790 DM |
4730 | } |
4731 | ||
4732 | void t4_sge_start(struct adapter *adap) | |
4733 | { | |
4734 | adap->sge.ethtxq_rover = 0; | |
4735 | mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD); | |
4736 | mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD); | |
4737 | } | |
4738 | ||
4739 | /** | |
4740 | * t4_sge_stop - disable SGE operation | |
4741 | * @adap: the adapter | |
4742 | * | |
4743 | * Stop tasklets and timers associated with the DMA engine. Note that | |
4744 | * this is effective only if measures have been taken to disable any HW | |
4745 | * events that may restart them. | |
4746 | */ | |
4747 | void t4_sge_stop(struct adapter *adap) | |
4748 | { | |
4749 | int i; | |
4750 | struct sge *s = &adap->sge; | |
4751 | ||
4752 | if (in_interrupt()) /* actions below require waiting */ | |
4753 | return; | |
4754 | ||
4755 | if (s->rx_timer.function) | |
4756 | del_timer_sync(&s->rx_timer); | |
4757 | if (s->tx_timer.function) | |
4758 | del_timer_sync(&s->tx_timer); | |
4759 | ||
ab677ff4 HS |
4760 | if (is_offload(adap)) { |
4761 | struct sge_uld_txq_info *txq_info; | |
4762 | ||
4763 | txq_info = adap->sge.uld_txq_info[CXGB4_TX_OFLD]; | |
4764 | if (txq_info) { | |
4765 | struct sge_uld_txq *txq = txq_info->uldtxq; | |
fd3a4790 | 4766 | |
ab677ff4 HS |
4767 | for_each_ofldtxq(&adap->sge, i) { |
4768 | if (txq->q.desc) | |
4769 | tasklet_kill(&txq->qresume_tsk); | |
4770 | } | |
4771 | } | |
fd3a4790 | 4772 | } |
ab677ff4 HS |
4773 | |
4774 | if (is_pci_uld(adap)) { | |
4775 | struct sge_uld_txq_info *txq_info; | |
4776 | ||
4777 | txq_info = adap->sge.uld_txq_info[CXGB4_TX_CRYPTO]; | |
4778 | if (txq_info) { | |
4779 | struct sge_uld_txq *txq = txq_info->uldtxq; | |
4780 | ||
4781 | for_each_ofldtxq(&adap->sge, i) { | |
4782 | if (txq->q.desc) | |
4783 | tasklet_kill(&txq->qresume_tsk); | |
4784 | } | |
4785 | } | |
4786 | } | |
4787 | ||
fd3a4790 DM |
4788 | for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) { |
4789 | struct sge_ctrl_txq *cq = &s->ctrlq[i]; | |
4790 | ||
4791 | if (cq->q.desc) | |
4792 | tasklet_kill(&cq->qresume_tsk); | |
4793 | } | |
4794 | } | |
4795 | ||
4796 | /** | |
06640310 | 4797 | * t4_sge_init_soft - grab core SGE values needed by SGE code |
fd3a4790 DM |
4798 | * @adap: the adapter |
4799 | * | |
06640310 HS |
4800 | * We need to grab the SGE operating parameters that we need to have |
4801 | * in order to do our job and make sure we can live with them. | |
fd3a4790 | 4802 | */ |
52367a76 VP |
4803 | |
4804 | static int t4_sge_init_soft(struct adapter *adap) | |
fd3a4790 DM |
4805 | { |
4806 | struct sge *s = &adap->sge; | |
52367a76 VP |
4807 | u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu; |
4808 | u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5; | |
4809 | u32 ingress_rx_threshold; | |
fd3a4790 | 4810 | |
52367a76 VP |
4811 | /* |
4812 | * Verify that CPL messages are going to the Ingress Queue for | |
4813 | * process_responses() and that only packet data is going to the | |
4814 | * Free Lists. | |
4815 | */ | |
f612b815 HS |
4816 | if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) != |
4817 | RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) { | |
52367a76 VP |
4818 | dev_err(adap->pdev_dev, "bad SGE CPL MODE\n"); |
4819 | return -EINVAL; | |
4820 | } | |
4821 | ||
4822 | /* | |
4823 | * Validate the Host Buffer Register Array indices that we want to | |
4824 | * use ... | |
4825 | * | |
4826 | * XXX Note that we should really read through the Host Buffer Size | |
4827 | * XXX register array and find the indices of the Buffer Sizes which | |
4828 | * XXX meet our needs! | |
4829 | */ | |
4830 | #define READ_FL_BUF(x) \ | |
f612b815 | 4831 | t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32)) |
52367a76 VP |
4832 | |
4833 | fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF); | |
4834 | fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF); | |
4835 | fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF); | |
4836 | fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF); | |
4837 | ||
92ddcc7b KS |
4838 | /* We only bother using the Large Page logic if the Large Page Buffer |
4839 | * is larger than our Page Size Buffer. | |
4840 | */ | |
4841 | if (fl_large_pg <= fl_small_pg) | |
4842 | fl_large_pg = 0; | |
4843 | ||
52367a76 VP |
4844 | #undef READ_FL_BUF |
4845 | ||
92ddcc7b KS |
4846 | /* The Page Size Buffer must be exactly equal to our Page Size and the |
4847 | * Large Page Size Buffer should be 0 (per above) or a power of 2. | |
4848 | */ | |
52367a76 | 4849 | if (fl_small_pg != PAGE_SIZE || |
92ddcc7b | 4850 | (fl_large_pg & (fl_large_pg-1)) != 0) { |
52367a76 VP |
4851 | dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n", |
4852 | fl_small_pg, fl_large_pg); | |
4853 | return -EINVAL; | |
4854 | } | |
4855 | if (fl_large_pg) | |
4856 | s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT; | |
4857 | ||
4858 | if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap) || | |
4859 | fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) { | |
4860 | dev_err(adap->pdev_dev, "bad SGE FL MTU sizes [%d, %d]\n", | |
4861 | fl_small_mtu, fl_large_mtu); | |
4862 | return -EINVAL; | |
4863 | } | |
4864 | ||
4865 | /* | |
4866 | * Retrieve our RX interrupt holdoff timer values and counter | |
4867 | * threshold values from the SGE parameters. | |
4868 | */ | |
f061de42 HS |
4869 | timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A); |
4870 | timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A); | |
4871 | timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A); | |
52367a76 | 4872 | s->timer_val[0] = core_ticks_to_us(adap, |
f061de42 | 4873 | TIMERVALUE0_G(timer_value_0_and_1)); |
52367a76 | 4874 | s->timer_val[1] = core_ticks_to_us(adap, |
f061de42 | 4875 | TIMERVALUE1_G(timer_value_0_and_1)); |
52367a76 | 4876 | s->timer_val[2] = core_ticks_to_us(adap, |
f061de42 | 4877 | TIMERVALUE2_G(timer_value_2_and_3)); |
52367a76 | 4878 | s->timer_val[3] = core_ticks_to_us(adap, |
f061de42 | 4879 | TIMERVALUE3_G(timer_value_2_and_3)); |
52367a76 | 4880 | s->timer_val[4] = core_ticks_to_us(adap, |
f061de42 | 4881 | TIMERVALUE4_G(timer_value_4_and_5)); |
52367a76 | 4882 | s->timer_val[5] = core_ticks_to_us(adap, |
f061de42 | 4883 | TIMERVALUE5_G(timer_value_4_and_5)); |
52367a76 | 4884 | |
f612b815 HS |
4885 | ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A); |
4886 | s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold); | |
4887 | s->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold); | |
4888 | s->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold); | |
4889 | s->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold); | |
52367a76 VP |
4890 | |
4891 | return 0; | |
4892 | } | |
4893 | ||
06640310 HS |
4894 | /** |
4895 | * t4_sge_init - initialize SGE | |
4896 | * @adap: the adapter | |
4897 | * | |
4898 | * Perform low-level SGE code initialization needed every time after a | |
4899 | * chip reset. | |
4900 | */ | |
52367a76 VP |
4901 | int t4_sge_init(struct adapter *adap) |
4902 | { | |
4903 | struct sge *s = &adap->sge; | |
acac5962 | 4904 | u32 sge_control, sge_conm_ctrl; |
c2b955e0 | 4905 | int ret, egress_threshold; |
52367a76 VP |
4906 | |
4907 | /* | |
4908 | * Ingress Padding Boundary and Egress Status Page Size are set up by | |
4909 | * t4_fixup_host_params(). | |
4910 | */ | |
f612b815 HS |
4911 | sge_control = t4_read_reg(adap, SGE_CONTROL_A); |
4912 | s->pktshift = PKTSHIFT_G(sge_control); | |
4913 | s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64; | |
ce8f407a | 4914 | |
acac5962 | 4915 | s->fl_align = t4_fl_pkt_align(adap); |
06640310 | 4916 | ret = t4_sge_init_soft(adap); |
52367a76 VP |
4917 | if (ret < 0) |
4918 | return ret; | |
4919 | ||
4920 | /* | |
4921 | * A FL with <= fl_starve_thres buffers is starving and a periodic | |
4922 | * timer will attempt to refill it. This needs to be larger than the | |
4923 | * SGE's Egress Congestion Threshold. If it isn't, then we can get | |
4924 | * stuck waiting for new packets while the SGE is waiting for us to | |
4925 | * give it more Free List entries. (Note that the SGE's Egress | |
c2b955e0 KS |
4926 | * Congestion Threshold is in units of 2 Free List pointers.) For T4, |
4927 | * there was only a single field to control this. For T5 there's the | |
4928 | * original field which now only applies to Unpacked Mode Free List | |
4929 | * buffers and a new field which only applies to Packed Mode Free List | |
4930 | * buffers. | |
52367a76 | 4931 | */ |
f612b815 | 4932 | sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A); |
676d6a75 HS |
4933 | switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { |
4934 | case CHELSIO_T4: | |
f612b815 | 4935 | egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl); |
676d6a75 HS |
4936 | break; |
4937 | case CHELSIO_T5: | |
f612b815 | 4938 | egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl); |
676d6a75 HS |
4939 | break; |
4940 | case CHELSIO_T6: | |
4941 | egress_threshold = T6_EGRTHRESHOLDPACKING_G(sge_conm_ctrl); | |
4942 | break; | |
4943 | default: | |
4944 | dev_err(adap->pdev_dev, "Unsupported Chip version %d\n", | |
4945 | CHELSIO_CHIP_VERSION(adap->params.chip)); | |
4946 | return -EINVAL; | |
4947 | } | |
c2b955e0 | 4948 | s->fl_starve_thres = 2*egress_threshold + 1; |
52367a76 | 4949 | |
a3bfb617 HS |
4950 | t4_idma_monitor_init(adap, &s->idma_monitor); |
4951 | ||
1ecc7b7a HS |
4952 | /* Set up timers used for recuring callbacks to process RX and TX |
4953 | * administrative tasks. | |
4954 | */ | |
0e23daeb KC |
4955 | timer_setup(&s->rx_timer, sge_rx_timer_cb, 0); |
4956 | timer_setup(&s->tx_timer, sge_tx_timer_cb, 0); | |
a3bfb617 | 4957 | |
fd3a4790 | 4958 | spin_lock_init(&s->intrq_lock); |
52367a76 VP |
4959 | |
4960 | return 0; | |
fd3a4790 | 4961 | } |