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cxgb4: Added support in debugfs to dump PM module stats
[thirdparty/kernel/stable.git] / drivers / net / ethernet / chelsio / cxgb4 / t4_hw.c
CommitLineData
56d36be4
DM
1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
56d36be4
DM
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
56d36be4
DM
35#include <linux/delay.h>
36#include "cxgb4.h"
37#include "t4_regs.h"
f612b815 38#include "t4_values.h"
56d36be4
DM
39#include "t4fw_api.h"
40
41/**
42 * t4_wait_op_done_val - wait until an operation is completed
43 * @adapter: the adapter performing the operation
44 * @reg: the register to check for completion
45 * @mask: a single-bit field within @reg that indicates completion
46 * @polarity: the value of the field when the operation is completed
47 * @attempts: number of check iterations
48 * @delay: delay in usecs between iterations
49 * @valp: where to store the value of the register at completion time
50 *
51 * Wait until an operation is completed by checking a bit in a register
52 * up to @attempts times. If @valp is not NULL the value of the register
53 * at the time it indicated completion is stored there. Returns 0 if the
54 * operation completes and -EAGAIN otherwise.
55 */
de498c89
RD
56static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
57 int polarity, int attempts, int delay, u32 *valp)
56d36be4
DM
58{
59 while (1) {
60 u32 val = t4_read_reg(adapter, reg);
61
62 if (!!(val & mask) == polarity) {
63 if (valp)
64 *valp = val;
65 return 0;
66 }
67 if (--attempts == 0)
68 return -EAGAIN;
69 if (delay)
70 udelay(delay);
71 }
72}
73
74static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
75 int polarity, int attempts, int delay)
76{
77 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
78 delay, NULL);
79}
80
81/**
82 * t4_set_reg_field - set a register field to a value
83 * @adapter: the adapter to program
84 * @addr: the register address
85 * @mask: specifies the portion of the register to modify
86 * @val: the new value for the register field
87 *
88 * Sets a register field specified by the supplied mask to the
89 * given value.
90 */
91void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
92 u32 val)
93{
94 u32 v = t4_read_reg(adapter, addr) & ~mask;
95
96 t4_write_reg(adapter, addr, v | val);
97 (void) t4_read_reg(adapter, addr); /* flush */
98}
99
100/**
101 * t4_read_indirect - read indirectly addressed registers
102 * @adap: the adapter
103 * @addr_reg: register holding the indirect address
104 * @data_reg: register holding the value of the indirect register
105 * @vals: where the read register values are stored
106 * @nregs: how many indirect registers to read
107 * @start_idx: index of first indirect register to read
108 *
109 * Reads registers that are accessed indirectly through an address/data
110 * register pair.
111 */
f2b7e78d 112void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
de498c89
RD
113 unsigned int data_reg, u32 *vals,
114 unsigned int nregs, unsigned int start_idx)
56d36be4
DM
115{
116 while (nregs--) {
117 t4_write_reg(adap, addr_reg, start_idx);
118 *vals++ = t4_read_reg(adap, data_reg);
119 start_idx++;
120 }
121}
122
13ee15d3
VP
123/**
124 * t4_write_indirect - write indirectly addressed registers
125 * @adap: the adapter
126 * @addr_reg: register holding the indirect addresses
127 * @data_reg: register holding the value for the indirect registers
128 * @vals: values to write
129 * @nregs: how many indirect registers to write
130 * @start_idx: address of first indirect register to write
131 *
132 * Writes a sequential block of registers that are accessed indirectly
133 * through an address/data register pair.
134 */
135void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
136 unsigned int data_reg, const u32 *vals,
137 unsigned int nregs, unsigned int start_idx)
138{
139 while (nregs--) {
140 t4_write_reg(adap, addr_reg, start_idx++);
141 t4_write_reg(adap, data_reg, *vals++);
142 }
143}
144
0abfd152
HS
145/*
146 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
147 * mechanism. This guarantees that we get the real value even if we're
148 * operating within a Virtual Machine and the Hypervisor is trapping our
149 * Configuration Space accesses.
150 */
151void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
152{
f061de42 153 u32 req = ENABLE_F | FUNCTION_V(adap->fn) | REGISTER_V(reg);
0abfd152
HS
154
155 if (is_t4(adap->params.chip))
f061de42 156 req |= LOCALCFG_F;
0abfd152 157
f061de42
HS
158 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
159 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
0abfd152
HS
160
161 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
162 * Configuration Space read. (None of the other fields matter when
163 * ENABLE is 0 so a simple register write is easier than a
164 * read-modify-write via t4_set_reg_field().)
165 */
f061de42 166 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
0abfd152
HS
167}
168
31d55c2d
HS
169/*
170 * t4_report_fw_error - report firmware error
171 * @adap: the adapter
172 *
173 * The adapter firmware can indicate error conditions to the host.
174 * If the firmware has indicated an error, print out the reason for
175 * the firmware error.
176 */
177static void t4_report_fw_error(struct adapter *adap)
178{
179 static const char *const reason[] = {
180 "Crash", /* PCIE_FW_EVAL_CRASH */
181 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
182 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
183 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
184 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
185 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
186 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
187 "Reserved", /* reserved */
188 };
189 u32 pcie_fw;
190
f061de42
HS
191 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
192 if (pcie_fw & PCIE_FW_ERR_F)
31d55c2d 193 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
b2e1a3f0 194 reason[PCIE_FW_EVAL_G(pcie_fw)]);
31d55c2d
HS
195}
196
56d36be4
DM
197/*
198 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
199 */
200static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
201 u32 mbox_addr)
202{
203 for ( ; nflit; nflit--, mbox_addr += 8)
204 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
205}
206
207/*
208 * Handle a FW assertion reported in a mailbox.
209 */
210static void fw_asrt(struct adapter *adap, u32 mbox_addr)
211{
212 struct fw_debug_cmd asrt;
213
214 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
215 dev_alert(adap->pdev_dev,
216 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
217 asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line),
218 ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y));
219}
220
221static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
222{
223 dev_err(adap->pdev_dev,
224 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
225 (unsigned long long)t4_read_reg64(adap, data_reg),
226 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
227 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
228 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
229 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
230 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
231 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
232 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
233}
234
235/**
236 * t4_wr_mbox_meat - send a command to FW through the given mailbox
237 * @adap: the adapter
238 * @mbox: index of the mailbox to use
239 * @cmd: the command to write
240 * @size: command length in bytes
241 * @rpl: where to optionally store the reply
242 * @sleep_ok: if true we may sleep while awaiting command completion
243 *
244 * Sends the given command to FW through the selected mailbox and waits
245 * for the FW to execute the command. If @rpl is not %NULL it is used to
246 * store the FW's reply to the command. The command and its optional
247 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
248 * to respond. @sleep_ok determines whether we may sleep while awaiting
249 * the response. If sleeping is allowed we use progressive backoff
250 * otherwise we spin.
251 *
252 * The return value is 0 on success or a negative errno on failure. A
253 * failure can happen either because we are not able to execute the
254 * command or FW executes it but signals an error. In the latter case
255 * the return value is the error code indicated by FW (negated).
256 */
257int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
258 void *rpl, bool sleep_ok)
259{
005b5717 260 static const int delay[] = {
56d36be4
DM
261 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
262 };
263
264 u32 v;
265 u64 res;
266 int i, ms, delay_idx;
267 const __be64 *p = cmd;
89c3a86c
HS
268 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
269 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
56d36be4
DM
270
271 if ((size & 15) || size > MBOX_LEN)
272 return -EINVAL;
273
204dc3c0
DM
274 /*
275 * If the device is off-line, as in EEH, commands will time out.
276 * Fail them early so we don't waste time waiting.
277 */
278 if (adap->pdev->error_state != pci_channel_io_normal)
279 return -EIO;
280
89c3a86c 281 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
56d36be4 282 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
89c3a86c 283 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
56d36be4
DM
284
285 if (v != MBOX_OWNER_DRV)
286 return v ? -EBUSY : -ETIMEDOUT;
287
288 for (i = 0; i < size; i += 8)
289 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
290
89c3a86c 291 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
56d36be4
DM
292 t4_read_reg(adap, ctl_reg); /* flush write */
293
294 delay_idx = 0;
295 ms = delay[0];
296
297 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
298 if (sleep_ok) {
299 ms = delay[delay_idx]; /* last element may repeat */
300 if (delay_idx < ARRAY_SIZE(delay) - 1)
301 delay_idx++;
302 msleep(ms);
303 } else
304 mdelay(ms);
305
306 v = t4_read_reg(adap, ctl_reg);
89c3a86c
HS
307 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
308 if (!(v & MBMSGVALID_F)) {
56d36be4
DM
309 t4_write_reg(adap, ctl_reg, 0);
310 continue;
311 }
312
313 res = t4_read_reg64(adap, data_reg);
e2ac9628 314 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
56d36be4 315 fw_asrt(adap, data_reg);
e2ac9628
HS
316 res = FW_CMD_RETVAL_V(EIO);
317 } else if (rpl) {
56d36be4 318 get_mbox_rpl(adap, rpl, size / 8, data_reg);
e2ac9628 319 }
56d36be4 320
e2ac9628 321 if (FW_CMD_RETVAL_G((int)res))
56d36be4
DM
322 dump_mbox(adap, mbox, data_reg);
323 t4_write_reg(adap, ctl_reg, 0);
e2ac9628 324 return -FW_CMD_RETVAL_G((int)res);
56d36be4
DM
325 }
326 }
327
328 dump_mbox(adap, mbox, data_reg);
329 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
330 *(const u8 *)cmd, mbox);
31d55c2d 331 t4_report_fw_error(adap);
56d36be4
DM
332 return -ETIMEDOUT;
333}
334
335/**
336 * t4_mc_read - read from MC through backdoor accesses
337 * @adap: the adapter
338 * @addr: address of first byte requested
19dd37ba 339 * @idx: which MC to access
56d36be4
DM
340 * @data: 64 bytes of data containing the requested address
341 * @ecc: where to store the corresponding 64-bit ECC word
342 *
343 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
344 * that covers the requested address @addr. If @parity is not %NULL it
345 * is assigned the 64-bit ECC word for the read data.
346 */
19dd37ba 347int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
56d36be4
DM
348{
349 int i;
19dd37ba
SR
350 u32 mc_bist_cmd, mc_bist_cmd_addr, mc_bist_cmd_len;
351 u32 mc_bist_status_rdata, mc_bist_data_pattern;
56d36be4 352
d14807dd 353 if (is_t4(adap->params.chip)) {
89c3a86c
HS
354 mc_bist_cmd = MC_BIST_CMD_A;
355 mc_bist_cmd_addr = MC_BIST_CMD_ADDR_A;
356 mc_bist_cmd_len = MC_BIST_CMD_LEN_A;
357 mc_bist_status_rdata = MC_BIST_STATUS_RDATA_A;
358 mc_bist_data_pattern = MC_BIST_DATA_PATTERN_A;
19dd37ba 359 } else {
89c3a86c
HS
360 mc_bist_cmd = MC_REG(MC_P_BIST_CMD_A, idx);
361 mc_bist_cmd_addr = MC_REG(MC_P_BIST_CMD_ADDR_A, idx);
362 mc_bist_cmd_len = MC_REG(MC_P_BIST_CMD_LEN_A, idx);
363 mc_bist_status_rdata = MC_REG(MC_P_BIST_STATUS_RDATA_A, idx);
364 mc_bist_data_pattern = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx);
19dd37ba
SR
365 }
366
89c3a86c 367 if (t4_read_reg(adap, mc_bist_cmd) & START_BIST_F)
56d36be4 368 return -EBUSY;
19dd37ba
SR
369 t4_write_reg(adap, mc_bist_cmd_addr, addr & ~0x3fU);
370 t4_write_reg(adap, mc_bist_cmd_len, 64);
371 t4_write_reg(adap, mc_bist_data_pattern, 0xc);
89c3a86c
HS
372 t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE_V(1) | START_BIST_F |
373 BIST_CMD_GAP_V(1));
374 i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST_F, 0, 10, 1);
56d36be4
DM
375 if (i)
376 return i;
377
19dd37ba 378#define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata, i)
56d36be4
DM
379
380 for (i = 15; i >= 0; i--)
381 *data++ = htonl(t4_read_reg(adap, MC_DATA(i)));
382 if (ecc)
383 *ecc = t4_read_reg64(adap, MC_DATA(16));
384#undef MC_DATA
385 return 0;
386}
387
388/**
389 * t4_edc_read - read from EDC through backdoor accesses
390 * @adap: the adapter
391 * @idx: which EDC to access
392 * @addr: address of first byte requested
393 * @data: 64 bytes of data containing the requested address
394 * @ecc: where to store the corresponding 64-bit ECC word
395 *
396 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
397 * that covers the requested address @addr. If @parity is not %NULL it
398 * is assigned the 64-bit ECC word for the read data.
399 */
400int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
401{
402 int i;
19dd37ba
SR
403 u32 edc_bist_cmd, edc_bist_cmd_addr, edc_bist_cmd_len;
404 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata;
56d36be4 405
d14807dd 406 if (is_t4(adap->params.chip)) {
89c3a86c
HS
407 edc_bist_cmd = EDC_REG(EDC_BIST_CMD_A, idx);
408 edc_bist_cmd_addr = EDC_REG(EDC_BIST_CMD_ADDR_A, idx);
409 edc_bist_cmd_len = EDC_REG(EDC_BIST_CMD_LEN_A, idx);
410 edc_bist_cmd_data_pattern = EDC_REG(EDC_BIST_DATA_PATTERN_A,
19dd37ba 411 idx);
89c3a86c
HS
412 edc_bist_status_rdata = EDC_REG(EDC_BIST_STATUS_RDATA_A,
413 idx);
19dd37ba 414 } else {
89c3a86c
HS
415 edc_bist_cmd = EDC_REG_T5(EDC_H_BIST_CMD_A, idx);
416 edc_bist_cmd_addr = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx);
417 edc_bist_cmd_len = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx);
19dd37ba 418 edc_bist_cmd_data_pattern =
89c3a86c 419 EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx);
19dd37ba 420 edc_bist_status_rdata =
89c3a86c 421 EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A, idx);
19dd37ba
SR
422 }
423
89c3a86c 424 if (t4_read_reg(adap, edc_bist_cmd) & START_BIST_F)
56d36be4 425 return -EBUSY;
19dd37ba
SR
426 t4_write_reg(adap, edc_bist_cmd_addr, addr & ~0x3fU);
427 t4_write_reg(adap, edc_bist_cmd_len, 64);
428 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
429 t4_write_reg(adap, edc_bist_cmd,
89c3a86c
HS
430 BIST_OPCODE_V(1) | BIST_CMD_GAP_V(1) | START_BIST_F);
431 i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST_F, 0, 10, 1);
56d36be4
DM
432 if (i)
433 return i;
434
19dd37ba 435#define EDC_DATA(i) (EDC_BIST_STATUS_REG(edc_bist_status_rdata, i))
56d36be4
DM
436
437 for (i = 15; i >= 0; i--)
438 *data++ = htonl(t4_read_reg(adap, EDC_DATA(i)));
439 if (ecc)
440 *ecc = t4_read_reg64(adap, EDC_DATA(16));
441#undef EDC_DATA
442 return 0;
443}
444
5afc8b84
VP
445/**
446 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
447 * @adap: the adapter
fc5ab020 448 * @win: PCI-E Memory Window to use
5afc8b84
VP
449 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
450 * @addr: address within indicated memory type
451 * @len: amount of memory to transfer
452 * @buf: host memory buffer
fc5ab020 453 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
5afc8b84
VP
454 *
455 * Reads/writes an [almost] arbitrary memory region in the firmware: the
fc5ab020
HS
456 * firmware memory address and host buffer must be aligned on 32-bit
457 * boudaries; the length may be arbitrary. The memory is transferred as
458 * a raw byte sequence from/to the firmware's memory. If this memory
459 * contains data structures which contain multi-byte integers, it's the
460 * caller's responsibility to perform appropriate byte order conversions.
5afc8b84 461 */
fc5ab020
HS
462int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
463 u32 len, __be32 *buf, int dir)
5afc8b84 464{
fc5ab020
HS
465 u32 pos, offset, resid, memoffset;
466 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
5afc8b84 467
fc5ab020 468 /* Argument sanity checks ...
5afc8b84 469 */
fc5ab020 470 if (addr & 0x3)
5afc8b84
VP
471 return -EINVAL;
472
fc5ab020
HS
473 /* It's convenient to be able to handle lengths which aren't a
474 * multiple of 32-bits because we often end up transferring files to
475 * the firmware. So we'll handle that by normalizing the length here
476 * and then handling any residual transfer at the end.
477 */
478 resid = len & 0x3;
479 len -= resid;
8c357ebd 480
19dd37ba 481 /* Offset into the region of memory which is being accessed
5afc8b84
VP
482 * MEM_EDC0 = 0
483 * MEM_EDC1 = 1
19dd37ba
SR
484 * MEM_MC = 2 -- T4
485 * MEM_MC0 = 2 -- For T5
486 * MEM_MC1 = 3 -- For T5
5afc8b84 487 */
6559a7e8 488 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
19dd37ba
SR
489 if (mtype != MEM_MC1)
490 memoffset = (mtype * (edc_size * 1024 * 1024));
491 else {
6559a7e8
HS
492 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
493 MA_EXT_MEMORY1_BAR_A));
19dd37ba
SR
494 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
495 }
5afc8b84
VP
496
497 /* Determine the PCIE_MEM_ACCESS_OFFSET */
498 addr = addr + memoffset;
499
fc5ab020
HS
500 /* Each PCI-E Memory Window is programmed with a window size -- or
501 * "aperture" -- which controls the granularity of its mapping onto
502 * adapter memory. We need to grab that aperture in order to know
503 * how to use the specified window. The window is also programmed
504 * with the base address of the Memory Window in BAR0's address
505 * space. For T4 this is an absolute PCI-E Bus Address. For T5
506 * the address is relative to BAR0.
5afc8b84 507 */
fc5ab020 508 mem_reg = t4_read_reg(adap,
f061de42 509 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
fc5ab020 510 win));
f061de42
HS
511 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
512 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
fc5ab020
HS
513 if (is_t4(adap->params.chip))
514 mem_base -= adap->t4_bar0;
f061de42 515 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->fn);
5afc8b84 516
fc5ab020
HS
517 /* Calculate our initial PCI-E Memory Window Position and Offset into
518 * that Window.
519 */
520 pos = addr & ~(mem_aperture-1);
521 offset = addr - pos;
5afc8b84 522
fc5ab020
HS
523 /* Set up initial PCI-E Memory Window to cover the start of our
524 * transfer. (Read it back to ensure that changes propagate before we
525 * attempt to use the new value.)
526 */
527 t4_write_reg(adap,
f061de42 528 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
fc5ab020
HS
529 pos | win_pf);
530 t4_read_reg(adap,
f061de42 531 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
fc5ab020
HS
532
533 /* Transfer data to/from the adapter as long as there's an integral
534 * number of 32-bit transfers to complete.
535 */
536 while (len > 0) {
537 if (dir == T4_MEMORY_READ)
538 *buf++ = (__force __be32) t4_read_reg(adap,
539 mem_base + offset);
540 else
541 t4_write_reg(adap, mem_base + offset,
542 (__force u32) *buf++);
543 offset += sizeof(__be32);
544 len -= sizeof(__be32);
545
546 /* If we've reached the end of our current window aperture,
547 * move the PCI-E Memory Window on to the next. Note that
548 * doing this here after "len" may be 0 allows us to set up
549 * the PCI-E Memory Window for a possible final residual
550 * transfer below ...
5afc8b84 551 */
fc5ab020
HS
552 if (offset == mem_aperture) {
553 pos += mem_aperture;
554 offset = 0;
555 t4_write_reg(adap,
f061de42
HS
556 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
557 win), pos | win_pf);
fc5ab020 558 t4_read_reg(adap,
f061de42
HS
559 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
560 win));
5afc8b84 561 }
5afc8b84
VP
562 }
563
fc5ab020
HS
564 /* If the original transfer had a length which wasn't a multiple of
565 * 32-bits, now's where we need to finish off the transfer of the
566 * residual amount. The PCI-E Memory Window has already been moved
567 * above (if necessary) to cover this final transfer.
568 */
569 if (resid) {
570 union {
571 __be32 word;
572 char byte[4];
573 } last;
574 unsigned char *bp;
575 int i;
576
c81576c2 577 if (dir == T4_MEMORY_READ) {
fc5ab020
HS
578 last.word = (__force __be32) t4_read_reg(adap,
579 mem_base + offset);
580 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
581 bp[i] = last.byte[i];
582 } else {
583 last.word = *buf;
584 for (i = resid; i < 4; i++)
585 last.byte[i] = 0;
586 t4_write_reg(adap, mem_base + offset,
587 (__force u32) last.word);
588 }
589 }
5afc8b84 590
fc5ab020 591 return 0;
5afc8b84
VP
592}
593
56d36be4 594#define EEPROM_STAT_ADDR 0x7bfc
47ce9c48
SR
595#define VPD_BASE 0x400
596#define VPD_BASE_OLD 0
0a57a536 597#define VPD_LEN 1024
63a92fe6 598#define CHELSIO_VPD_UNIQUE_ID 0x82
56d36be4
DM
599
600/**
601 * t4_seeprom_wp - enable/disable EEPROM write protection
602 * @adapter: the adapter
603 * @enable: whether to enable or disable write protection
604 *
605 * Enables or disables write protection on the serial EEPROM.
606 */
607int t4_seeprom_wp(struct adapter *adapter, bool enable)
608{
609 unsigned int v = enable ? 0xc : 0;
610 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
611 return ret < 0 ? ret : 0;
612}
613
614/**
615 * get_vpd_params - read VPD parameters from VPD EEPROM
616 * @adapter: adapter to read
617 * @p: where to store the parameters
618 *
619 * Reads card parameters stored in VPD EEPROM.
620 */
636f9d37 621int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
56d36be4 622{
636f9d37 623 u32 cclk_param, cclk_val;
47ce9c48 624 int i, ret, addr;
a94cd705 625 int ec, sn, pn;
8c357ebd 626 u8 *vpd, csum;
23d88e1d 627 unsigned int vpdr_len, kw_offset, id_len;
56d36be4 628
8c357ebd
VP
629 vpd = vmalloc(VPD_LEN);
630 if (!vpd)
631 return -ENOMEM;
632
47ce9c48
SR
633 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
634 if (ret < 0)
635 goto out;
63a92fe6
HS
636
637 /* The VPD shall have a unique identifier specified by the PCI SIG.
638 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
639 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
640 * is expected to automatically put this entry at the
641 * beginning of the VPD.
642 */
643 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
47ce9c48
SR
644
645 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
56d36be4 646 if (ret < 0)
8c357ebd 647 goto out;
56d36be4 648
23d88e1d
DM
649 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
650 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
8c357ebd
VP
651 ret = -EINVAL;
652 goto out;
23d88e1d
DM
653 }
654
655 id_len = pci_vpd_lrdt_size(vpd);
656 if (id_len > ID_LEN)
657 id_len = ID_LEN;
658
659 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
660 if (i < 0) {
661 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
8c357ebd
VP
662 ret = -EINVAL;
663 goto out;
23d88e1d
DM
664 }
665
666 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
667 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
668 if (vpdr_len + kw_offset > VPD_LEN) {
226ec5fd 669 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
8c357ebd
VP
670 ret = -EINVAL;
671 goto out;
226ec5fd
DM
672 }
673
674#define FIND_VPD_KW(var, name) do { \
23d88e1d 675 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
226ec5fd
DM
676 if (var < 0) { \
677 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
8c357ebd
VP
678 ret = -EINVAL; \
679 goto out; \
226ec5fd
DM
680 } \
681 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
682} while (0)
683
684 FIND_VPD_KW(i, "RV");
685 for (csum = 0; i >= 0; i--)
686 csum += vpd[i];
56d36be4
DM
687
688 if (csum) {
689 dev_err(adapter->pdev_dev,
690 "corrupted VPD EEPROM, actual csum %u\n", csum);
8c357ebd
VP
691 ret = -EINVAL;
692 goto out;
56d36be4
DM
693 }
694
226ec5fd
DM
695 FIND_VPD_KW(ec, "EC");
696 FIND_VPD_KW(sn, "SN");
a94cd705 697 FIND_VPD_KW(pn, "PN");
226ec5fd
DM
698#undef FIND_VPD_KW
699
23d88e1d 700 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
56d36be4 701 strim(p->id);
226ec5fd 702 memcpy(p->ec, vpd + ec, EC_LEN);
56d36be4 703 strim(p->ec);
226ec5fd
DM
704 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
705 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
56d36be4 706 strim(p->sn);
63a92fe6 707 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
a94cd705
KS
708 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
709 strim(p->pn);
636f9d37
VP
710
711 /*
712 * Ask firmware for the Core Clock since it knows how to translate the
713 * Reference Clock ('V2') VPD field into a Core Clock value ...
714 */
5167865a
HS
715 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
716 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
636f9d37
VP
717 ret = t4_query_params(adapter, adapter->mbox, 0, 0,
718 1, &cclk_param, &cclk_val);
8c357ebd
VP
719
720out:
721 vfree(vpd);
636f9d37
VP
722 if (ret)
723 return ret;
724 p->cclk = cclk_val;
725
56d36be4
DM
726 return 0;
727}
728
729/* serial flash and firmware constants */
730enum {
731 SF_ATTEMPTS = 10, /* max retries for SF operations */
732
733 /* flash command opcodes */
734 SF_PROG_PAGE = 2, /* program page */
735 SF_WR_DISABLE = 4, /* disable writes */
736 SF_RD_STATUS = 5, /* read status register */
737 SF_WR_ENABLE = 6, /* enable writes */
738 SF_RD_DATA_FAST = 0xb, /* read flash */
900a6596 739 SF_RD_ID = 0x9f, /* read ID */
56d36be4
DM
740 SF_ERASE_SECTOR = 0xd8, /* erase sector */
741
6f1d7210 742 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
56d36be4
DM
743};
744
745/**
746 * sf1_read - read data from the serial flash
747 * @adapter: the adapter
748 * @byte_cnt: number of bytes to read
749 * @cont: whether another operation will be chained
750 * @lock: whether to lock SF for PL access only
751 * @valp: where to store the read data
752 *
753 * Reads up to 4 bytes of data from the serial flash. The location of
754 * the read needs to be specified prior to calling this by issuing the
755 * appropriate commands to the serial flash.
756 */
757static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
758 int lock, u32 *valp)
759{
760 int ret;
761
762 if (!byte_cnt || byte_cnt > 4)
763 return -EINVAL;
0d804338 764 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
56d36be4 765 return -EBUSY;
0d804338
HS
766 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
767 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
768 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
56d36be4 769 if (!ret)
0d804338 770 *valp = t4_read_reg(adapter, SF_DATA_A);
56d36be4
DM
771 return ret;
772}
773
774/**
775 * sf1_write - write data to the serial flash
776 * @adapter: the adapter
777 * @byte_cnt: number of bytes to write
778 * @cont: whether another operation will be chained
779 * @lock: whether to lock SF for PL access only
780 * @val: value to write
781 *
782 * Writes up to 4 bytes of data to the serial flash. The location of
783 * the write needs to be specified prior to calling this by issuing the
784 * appropriate commands to the serial flash.
785 */
786static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
787 int lock, u32 val)
788{
789 if (!byte_cnt || byte_cnt > 4)
790 return -EINVAL;
0d804338 791 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
56d36be4 792 return -EBUSY;
0d804338
HS
793 t4_write_reg(adapter, SF_DATA_A, val);
794 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
795 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
796 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
56d36be4
DM
797}
798
799/**
800 * flash_wait_op - wait for a flash operation to complete
801 * @adapter: the adapter
802 * @attempts: max number of polls of the status register
803 * @delay: delay between polls in ms
804 *
805 * Wait for a flash operation to complete by polling the status register.
806 */
807static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
808{
809 int ret;
810 u32 status;
811
812 while (1) {
813 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
814 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
815 return ret;
816 if (!(status & 1))
817 return 0;
818 if (--attempts == 0)
819 return -EAGAIN;
820 if (delay)
821 msleep(delay);
822 }
823}
824
825/**
826 * t4_read_flash - read words from serial flash
827 * @adapter: the adapter
828 * @addr: the start address for the read
829 * @nwords: how many 32-bit words to read
830 * @data: where to store the read data
831 * @byte_oriented: whether to store data as bytes or as words
832 *
833 * Read the specified number of 32-bit words from the serial flash.
834 * If @byte_oriented is set the read data is stored as a byte array
835 * (i.e., big-endian), otherwise as 32-bit words in the platform's
836 * natural endianess.
837 */
49216c1c
HS
838int t4_read_flash(struct adapter *adapter, unsigned int addr,
839 unsigned int nwords, u32 *data, int byte_oriented)
56d36be4
DM
840{
841 int ret;
842
900a6596 843 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
56d36be4
DM
844 return -EINVAL;
845
846 addr = swab32(addr) | SF_RD_DATA_FAST;
847
848 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
849 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
850 return ret;
851
852 for ( ; nwords; nwords--, data++) {
853 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
854 if (nwords == 1)
0d804338 855 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
56d36be4
DM
856 if (ret)
857 return ret;
858 if (byte_oriented)
404d9e3f 859 *data = (__force __u32) (htonl(*data));
56d36be4
DM
860 }
861 return 0;
862}
863
864/**
865 * t4_write_flash - write up to a page of data to the serial flash
866 * @adapter: the adapter
867 * @addr: the start address to write
868 * @n: length of data to write in bytes
869 * @data: the data to write
870 *
871 * Writes up to a page of data (256 bytes) to the serial flash starting
872 * at the given address. All the data must be written to the same page.
873 */
874static int t4_write_flash(struct adapter *adapter, unsigned int addr,
875 unsigned int n, const u8 *data)
876{
877 int ret;
878 u32 buf[64];
879 unsigned int i, c, left, val, offset = addr & 0xff;
880
900a6596 881 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
56d36be4
DM
882 return -EINVAL;
883
884 val = swab32(addr) | SF_PROG_PAGE;
885
886 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
887 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
888 goto unlock;
889
890 for (left = n; left; left -= c) {
891 c = min(left, 4U);
892 for (val = 0, i = 0; i < c; ++i)
893 val = (val << 8) + *data++;
894
895 ret = sf1_write(adapter, c, c != left, 1, val);
896 if (ret)
897 goto unlock;
898 }
900a6596 899 ret = flash_wait_op(adapter, 8, 1);
56d36be4
DM
900 if (ret)
901 goto unlock;
902
0d804338 903 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
56d36be4
DM
904
905 /* Read the page to verify the write succeeded */
906 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
907 if (ret)
908 return ret;
909
910 if (memcmp(data - n, (u8 *)buf + offset, n)) {
911 dev_err(adapter->pdev_dev,
912 "failed to correctly write the flash page at %#x\n",
913 addr);
914 return -EIO;
915 }
916 return 0;
917
918unlock:
0d804338 919 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
56d36be4
DM
920 return ret;
921}
922
923/**
16e47624 924 * t4_get_fw_version - read the firmware version
56d36be4
DM
925 * @adapter: the adapter
926 * @vers: where to place the version
927 *
928 * Reads the FW version from flash.
929 */
16e47624 930int t4_get_fw_version(struct adapter *adapter, u32 *vers)
56d36be4 931{
16e47624
HS
932 return t4_read_flash(adapter, FLASH_FW_START +
933 offsetof(struct fw_hdr, fw_ver), 1,
934 vers, 0);
56d36be4
DM
935}
936
937/**
16e47624 938 * t4_get_tp_version - read the TP microcode version
56d36be4
DM
939 * @adapter: the adapter
940 * @vers: where to place the version
941 *
942 * Reads the TP microcode version from flash.
943 */
16e47624 944int t4_get_tp_version(struct adapter *adapter, u32 *vers)
56d36be4 945{
16e47624 946 return t4_read_flash(adapter, FLASH_FW_START +
900a6596 947 offsetof(struct fw_hdr, tp_microcode_ver),
56d36be4
DM
948 1, vers, 0);
949}
950
16e47624
HS
951/* Is the given firmware API compatible with the one the driver was compiled
952 * with?
56d36be4 953 */
16e47624 954static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
56d36be4 955{
56d36be4 956
16e47624
HS
957 /* short circuit if it's the exact same firmware version */
958 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
959 return 1;
56d36be4 960
16e47624
HS
961#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
962 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
963 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
964 return 1;
965#undef SAME_INTF
0a57a536 966
16e47624
HS
967 return 0;
968}
56d36be4 969
16e47624
HS
970/* The firmware in the filesystem is usable, but should it be installed?
971 * This routine explains itself in detail if it indicates the filesystem
972 * firmware should be installed.
973 */
974static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
975 int k, int c)
976{
977 const char *reason;
978
979 if (!card_fw_usable) {
980 reason = "incompatible or unusable";
981 goto install;
e69972f5
JH
982 }
983
16e47624
HS
984 if (k > c) {
985 reason = "older than the version supported with this driver";
986 goto install;
56d36be4
DM
987 }
988
16e47624
HS
989 return 0;
990
991install:
992 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
993 "installing firmware %u.%u.%u.%u on card.\n",
b2e1a3f0
HS
994 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
995 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
996 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
997 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
56d36be4 998
56d36be4
DM
999 return 1;
1000}
1001
16e47624
HS
1002int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1003 const u8 *fw_data, unsigned int fw_size,
1004 struct fw_hdr *card_fw, enum dev_state state,
1005 int *reset)
1006{
1007 int ret, card_fw_usable, fs_fw_usable;
1008 const struct fw_hdr *fs_fw;
1009 const struct fw_hdr *drv_fw;
1010
1011 drv_fw = &fw_info->fw_hdr;
1012
1013 /* Read the header of the firmware on the card */
1014 ret = -t4_read_flash(adap, FLASH_FW_START,
1015 sizeof(*card_fw) / sizeof(uint32_t),
1016 (uint32_t *)card_fw, 1);
1017 if (ret == 0) {
1018 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
1019 } else {
1020 dev_err(adap->pdev_dev,
1021 "Unable to read card's firmware header: %d\n", ret);
1022 card_fw_usable = 0;
1023 }
1024
1025 if (fw_data != NULL) {
1026 fs_fw = (const void *)fw_data;
1027 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
1028 } else {
1029 fs_fw = NULL;
1030 fs_fw_usable = 0;
1031 }
1032
1033 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
1034 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
1035 /* Common case: the firmware on the card is an exact match and
1036 * the filesystem one is an exact match too, or the filesystem
1037 * one is absent/incompatible.
1038 */
1039 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
1040 should_install_fs_fw(adap, card_fw_usable,
1041 be32_to_cpu(fs_fw->fw_ver),
1042 be32_to_cpu(card_fw->fw_ver))) {
1043 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
1044 fw_size, 0);
1045 if (ret != 0) {
1046 dev_err(adap->pdev_dev,
1047 "failed to install firmware: %d\n", ret);
1048 goto bye;
1049 }
1050
1051 /* Installed successfully, update the cached header too. */
1052 memcpy(card_fw, fs_fw, sizeof(*card_fw));
1053 card_fw_usable = 1;
1054 *reset = 0; /* already reset as part of load_fw */
1055 }
1056
1057 if (!card_fw_usable) {
1058 uint32_t d, c, k;
1059
1060 d = be32_to_cpu(drv_fw->fw_ver);
1061 c = be32_to_cpu(card_fw->fw_ver);
1062 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
1063
1064 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
1065 "chip state %d, "
1066 "driver compiled with %d.%d.%d.%d, "
1067 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
1068 state,
b2e1a3f0
HS
1069 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
1070 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
1071 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
1072 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
1073 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
1074 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
16e47624
HS
1075 ret = EINVAL;
1076 goto bye;
1077 }
1078
1079 /* We're using whatever's on the card and it's known to be good. */
1080 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
1081 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
1082
1083bye:
1084 return ret;
1085}
1086
56d36be4
DM
1087/**
1088 * t4_flash_erase_sectors - erase a range of flash sectors
1089 * @adapter: the adapter
1090 * @start: the first sector to erase
1091 * @end: the last sector to erase
1092 *
1093 * Erases the sectors in the given inclusive range.
1094 */
1095static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
1096{
1097 int ret = 0;
1098
c0d5b8cf
HS
1099 if (end >= adapter->params.sf_nsec)
1100 return -EINVAL;
1101
56d36be4
DM
1102 while (start <= end) {
1103 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
1104 (ret = sf1_write(adapter, 4, 0, 1,
1105 SF_ERASE_SECTOR | (start << 8))) != 0 ||
900a6596 1106 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
56d36be4
DM
1107 dev_err(adapter->pdev_dev,
1108 "erase of flash sector %d failed, error %d\n",
1109 start, ret);
1110 break;
1111 }
1112 start++;
1113 }
0d804338 1114 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
56d36be4
DM
1115 return ret;
1116}
1117
636f9d37
VP
1118/**
1119 * t4_flash_cfg_addr - return the address of the flash configuration file
1120 * @adapter: the adapter
1121 *
1122 * Return the address within the flash where the Firmware Configuration
1123 * File is stored.
1124 */
1125unsigned int t4_flash_cfg_addr(struct adapter *adapter)
1126{
1127 if (adapter->params.sf_size == 0x100000)
1128 return FLASH_FPGA_CFG_START;
1129 else
1130 return FLASH_CFG_START;
1131}
1132
79af221d
HS
1133/* Return TRUE if the specified firmware matches the adapter. I.e. T4
1134 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
1135 * and emit an error message for mismatched firmware to save our caller the
1136 * effort ...
1137 */
1138static bool t4_fw_matches_chip(const struct adapter *adap,
1139 const struct fw_hdr *hdr)
1140{
1141 /* The expression below will return FALSE for any unsupported adapter
1142 * which will keep us "honest" in the future ...
1143 */
1144 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
1145 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5))
1146 return true;
1147
1148 dev_err(adap->pdev_dev,
1149 "FW image (%d) is not suitable for this adapter (%d)\n",
1150 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
1151 return false;
1152}
1153
56d36be4
DM
1154/**
1155 * t4_load_fw - download firmware
1156 * @adap: the adapter
1157 * @fw_data: the firmware image to write
1158 * @size: image size
1159 *
1160 * Write the supplied firmware image to the card's serial flash.
1161 */
1162int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
1163{
1164 u32 csum;
1165 int ret, addr;
1166 unsigned int i;
1167 u8 first_page[SF_PAGE_SIZE];
404d9e3f 1168 const __be32 *p = (const __be32 *)fw_data;
56d36be4 1169 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
900a6596
DM
1170 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
1171 unsigned int fw_img_start = adap->params.sf_fw_start;
1172 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
56d36be4
DM
1173
1174 if (!size) {
1175 dev_err(adap->pdev_dev, "FW image has no data\n");
1176 return -EINVAL;
1177 }
1178 if (size & 511) {
1179 dev_err(adap->pdev_dev,
1180 "FW image size not multiple of 512 bytes\n");
1181 return -EINVAL;
1182 }
1183 if (ntohs(hdr->len512) * 512 != size) {
1184 dev_err(adap->pdev_dev,
1185 "FW image size differs from size in FW header\n");
1186 return -EINVAL;
1187 }
1188 if (size > FW_MAX_SIZE) {
1189 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
1190 FW_MAX_SIZE);
1191 return -EFBIG;
1192 }
79af221d
HS
1193 if (!t4_fw_matches_chip(adap, hdr))
1194 return -EINVAL;
56d36be4
DM
1195
1196 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1197 csum += ntohl(p[i]);
1198
1199 if (csum != 0xffffffff) {
1200 dev_err(adap->pdev_dev,
1201 "corrupted firmware image, checksum %#x\n", csum);
1202 return -EINVAL;
1203 }
1204
900a6596
DM
1205 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
1206 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
56d36be4
DM
1207 if (ret)
1208 goto out;
1209
1210 /*
1211 * We write the correct version at the end so the driver can see a bad
1212 * version if the FW write fails. Start by writing a copy of the
1213 * first page with a bad version.
1214 */
1215 memcpy(first_page, fw_data, SF_PAGE_SIZE);
1216 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
900a6596 1217 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
56d36be4
DM
1218 if (ret)
1219 goto out;
1220
900a6596 1221 addr = fw_img_start;
56d36be4
DM
1222 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
1223 addr += SF_PAGE_SIZE;
1224 fw_data += SF_PAGE_SIZE;
1225 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
1226 if (ret)
1227 goto out;
1228 }
1229
1230 ret = t4_write_flash(adap,
900a6596 1231 fw_img_start + offsetof(struct fw_hdr, fw_ver),
56d36be4
DM
1232 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
1233out:
1234 if (ret)
1235 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
1236 ret);
dff04bce
HS
1237 else
1238 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
56d36be4
DM
1239 return ret;
1240}
1241
49216c1c
HS
1242/**
1243 * t4_fwcache - firmware cache operation
1244 * @adap: the adapter
1245 * @op : the operation (flush or flush and invalidate)
1246 */
1247int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
1248{
1249 struct fw_params_cmd c;
1250
1251 memset(&c, 0, sizeof(c));
1252 c.op_to_vfn =
1253 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
1254 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
1255 FW_PARAMS_CMD_PFN_V(adap->fn) |
1256 FW_PARAMS_CMD_VFN_V(0));
1257 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
1258 c.param[0].mnem =
1259 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
1260 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
1261 c.param[0].val = (__force __be32)op;
1262
1263 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
1264}
1265
56d36be4 1266#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
72aca4bf
KS
1267 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
1268 FW_PORT_CAP_ANEG)
56d36be4
DM
1269
1270/**
1271 * t4_link_start - apply link configuration to MAC/PHY
1272 * @phy: the PHY to setup
1273 * @mac: the MAC to setup
1274 * @lc: the requested link configuration
1275 *
1276 * Set up a port's MAC and PHY according to a desired link configuration.
1277 * - If the PHY can auto-negotiate first decide what to advertise, then
1278 * enable/disable auto-negotiation as desired, and reset.
1279 * - If the PHY does not auto-negotiate just reset it.
1280 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1281 * otherwise do it later based on the outcome of auto-negotiation.
1282 */
1283int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1284 struct link_config *lc)
1285{
1286 struct fw_port_cmd c;
2b5fb1f2 1287 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
56d36be4
DM
1288
1289 lc->link_ok = 0;
1290 if (lc->requested_fc & PAUSE_RX)
1291 fc |= FW_PORT_CAP_FC_RX;
1292 if (lc->requested_fc & PAUSE_TX)
1293 fc |= FW_PORT_CAP_FC_TX;
1294
1295 memset(&c, 0, sizeof(c));
e2ac9628 1296 c.op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) | FW_CMD_REQUEST_F |
2b5fb1f2
HS
1297 FW_CMD_EXEC_F | FW_PORT_CMD_PORTID_V(port));
1298 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
56d36be4
DM
1299 FW_LEN16(c));
1300
1301 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1302 c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc);
1303 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1304 } else if (lc->autoneg == AUTONEG_DISABLE) {
1305 c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi);
1306 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1307 } else
1308 c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi);
1309
1310 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1311}
1312
1313/**
1314 * t4_restart_aneg - restart autonegotiation
1315 * @adap: the adapter
1316 * @mbox: mbox to use for the FW command
1317 * @port: the port id
1318 *
1319 * Restarts autonegotiation for the selected port.
1320 */
1321int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
1322{
1323 struct fw_port_cmd c;
1324
1325 memset(&c, 0, sizeof(c));
e2ac9628 1326 c.op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) | FW_CMD_REQUEST_F |
2b5fb1f2
HS
1327 FW_CMD_EXEC_F | FW_PORT_CMD_PORTID_V(port));
1328 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
56d36be4
DM
1329 FW_LEN16(c));
1330 c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG);
1331 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1332}
1333
8caa1e84
VP
1334typedef void (*int_handler_t)(struct adapter *adap);
1335
56d36be4
DM
1336struct intr_info {
1337 unsigned int mask; /* bits to check in interrupt status */
1338 const char *msg; /* message to print or NULL */
1339 short stat_idx; /* stat counter to increment or -1 */
1340 unsigned short fatal; /* whether the condition reported is fatal */
8caa1e84 1341 int_handler_t int_handler; /* platform-specific int handler */
56d36be4
DM
1342};
1343
1344/**
1345 * t4_handle_intr_status - table driven interrupt handler
1346 * @adapter: the adapter that generated the interrupt
1347 * @reg: the interrupt status register to process
1348 * @acts: table of interrupt actions
1349 *
1350 * A table driven interrupt handler that applies a set of masks to an
1351 * interrupt status word and performs the corresponding actions if the
25985edc 1352 * interrupts described by the mask have occurred. The actions include
56d36be4
DM
1353 * optionally emitting a warning or alert message. The table is terminated
1354 * by an entry specifying mask 0. Returns the number of fatal interrupt
1355 * conditions.
1356 */
1357static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
1358 const struct intr_info *acts)
1359{
1360 int fatal = 0;
1361 unsigned int mask = 0;
1362 unsigned int status = t4_read_reg(adapter, reg);
1363
1364 for ( ; acts->mask; ++acts) {
1365 if (!(status & acts->mask))
1366 continue;
1367 if (acts->fatal) {
1368 fatal++;
1369 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1370 status & acts->mask);
1371 } else if (acts->msg && printk_ratelimit())
1372 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1373 status & acts->mask);
8caa1e84
VP
1374 if (acts->int_handler)
1375 acts->int_handler(adapter);
56d36be4
DM
1376 mask |= acts->mask;
1377 }
1378 status &= mask;
1379 if (status) /* clear processed interrupts */
1380 t4_write_reg(adapter, reg, status);
1381 return fatal;
1382}
1383
1384/*
1385 * Interrupt handler for the PCIE module.
1386 */
1387static void pcie_intr_handler(struct adapter *adapter)
1388{
005b5717 1389 static const struct intr_info sysbus_intr_info[] = {
f061de42
HS
1390 { RNPP_F, "RXNP array parity error", -1, 1 },
1391 { RPCP_F, "RXPC array parity error", -1, 1 },
1392 { RCIP_F, "RXCIF array parity error", -1, 1 },
1393 { RCCP_F, "Rx completions control array parity error", -1, 1 },
1394 { RFTP_F, "RXFT array parity error", -1, 1 },
56d36be4
DM
1395 { 0 }
1396 };
005b5717 1397 static const struct intr_info pcie_port_intr_info[] = {
f061de42
HS
1398 { TPCP_F, "TXPC array parity error", -1, 1 },
1399 { TNPP_F, "TXNP array parity error", -1, 1 },
1400 { TFTP_F, "TXFT array parity error", -1, 1 },
1401 { TCAP_F, "TXCA array parity error", -1, 1 },
1402 { TCIP_F, "TXCIF array parity error", -1, 1 },
1403 { RCAP_F, "RXCA array parity error", -1, 1 },
1404 { OTDD_F, "outbound request TLP discarded", -1, 1 },
1405 { RDPE_F, "Rx data parity error", -1, 1 },
1406 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
56d36be4
DM
1407 { 0 }
1408 };
005b5717 1409 static const struct intr_info pcie_intr_info[] = {
f061de42
HS
1410 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
1411 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
1412 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
1413 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
1414 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
1415 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
1416 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
1417 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
1418 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
1419 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
1420 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
1421 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
1422 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
1423 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
1424 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
1425 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
1426 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
1427 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
1428 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
1429 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
1430 { FIDPERR_F, "PCI FID parity error", -1, 1 },
1431 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
1432 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
1433 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
1434 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
1435 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
1436 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
1437 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
1438 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
1439 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
1440 -1, 0 },
56d36be4
DM
1441 { 0 }
1442 };
1443
0a57a536 1444 static struct intr_info t5_pcie_intr_info[] = {
f061de42 1445 { MSTGRPPERR_F, "Master Response Read Queue parity error",
0a57a536 1446 -1, 1 },
f061de42
HS
1447 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
1448 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
1449 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
1450 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
1451 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
1452 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
1453 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
0a57a536 1454 -1, 1 },
f061de42 1455 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
0a57a536 1456 -1, 1 },
f061de42
HS
1457 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
1458 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
1459 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
1460 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
1461 { DREQWRPERR_F, "PCI DMA channel write request parity error",
0a57a536 1462 -1, 1 },
f061de42
HS
1463 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
1464 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
1465 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
1466 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
1467 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
1468 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
1469 { FIDPERR_F, "PCI FID parity error", -1, 1 },
1470 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
1471 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
1472 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
1473 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
0a57a536 1474 -1, 1 },
f061de42
HS
1475 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
1476 -1, 1 },
1477 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
1478 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
1479 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
1480 { READRSPERR_F, "Outbound read error", -1, 0 },
0a57a536
SR
1481 { 0 }
1482 };
1483
56d36be4
DM
1484 int fat;
1485
9bb59b96
HS
1486 if (is_t4(adapter->params.chip))
1487 fat = t4_handle_intr_status(adapter,
f061de42
HS
1488 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
1489 sysbus_intr_info) +
9bb59b96 1490 t4_handle_intr_status(adapter,
f061de42
HS
1491 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
1492 pcie_port_intr_info) +
1493 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
9bb59b96
HS
1494 pcie_intr_info);
1495 else
f061de42 1496 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
9bb59b96 1497 t5_pcie_intr_info);
0a57a536 1498
56d36be4
DM
1499 if (fat)
1500 t4_fatal_err(adapter);
1501}
1502
1503/*
1504 * TP interrupt handler.
1505 */
1506static void tp_intr_handler(struct adapter *adapter)
1507{
005b5717 1508 static const struct intr_info tp_intr_info[] = {
56d36be4 1509 { 0x3fffffff, "TP parity error", -1, 1 },
837e4a42 1510 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
56d36be4
DM
1511 { 0 }
1512 };
1513
837e4a42 1514 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
56d36be4
DM
1515 t4_fatal_err(adapter);
1516}
1517
1518/*
1519 * SGE interrupt handler.
1520 */
1521static void sge_intr_handler(struct adapter *adapter)
1522{
1523 u64 v;
1524
005b5717 1525 static const struct intr_info sge_intr_info[] = {
f612b815 1526 { ERR_CPL_EXCEED_IQE_SIZE_F,
56d36be4 1527 "SGE received CPL exceeding IQE size", -1, 1 },
f612b815 1528 { ERR_INVALID_CIDX_INC_F,
56d36be4 1529 "SGE GTS CIDX increment too large", -1, 0 },
f612b815
HS
1530 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
1531 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
1532 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
1533 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
1534 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
56d36be4 1535 "SGE IQID > 1023 received CPL for FL", -1, 0 },
f612b815 1536 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
56d36be4 1537 0 },
f612b815 1538 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
56d36be4 1539 0 },
f612b815 1540 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
56d36be4 1541 0 },
f612b815 1542 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
56d36be4 1543 0 },
f612b815 1544 { ERR_ING_CTXT_PRIO_F,
56d36be4 1545 "SGE too many priority ingress contexts", -1, 0 },
f612b815 1546 { ERR_EGR_CTXT_PRIO_F,
56d36be4 1547 "SGE too many priority egress contexts", -1, 0 },
f612b815
HS
1548 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
1549 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
56d36be4
DM
1550 { 0 }
1551 };
1552
f612b815
HS
1553 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
1554 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
56d36be4
DM
1555 if (v) {
1556 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
8caa1e84 1557 (unsigned long long)v);
f612b815
HS
1558 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
1559 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
56d36be4
DM
1560 }
1561
f612b815 1562 if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info) ||
56d36be4
DM
1563 v != 0)
1564 t4_fatal_err(adapter);
1565}
1566
89c3a86c
HS
1567#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
1568 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
1569#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
1570 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
1571
56d36be4
DM
1572/*
1573 * CIM interrupt handler.
1574 */
1575static void cim_intr_handler(struct adapter *adapter)
1576{
005b5717 1577 static const struct intr_info cim_intr_info[] = {
89c3a86c
HS
1578 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
1579 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
1580 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
1581 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
1582 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
1583 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
1584 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
56d36be4
DM
1585 { 0 }
1586 };
005b5717 1587 static const struct intr_info cim_upintr_info[] = {
89c3a86c
HS
1588 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
1589 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
1590 { ILLWRINT_F, "CIM illegal write", -1, 1 },
1591 { ILLRDINT_F, "CIM illegal read", -1, 1 },
1592 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
1593 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
1594 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
1595 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
1596 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
1597 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
1598 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
1599 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
1600 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
1601 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
1602 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
1603 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
1604 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
1605 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
1606 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
1607 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
1608 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
1609 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
1610 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
1611 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
1612 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
1613 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
1614 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
1615 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
56d36be4
DM
1616 { 0 }
1617 };
1618
1619 int fat;
1620
f061de42 1621 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
31d55c2d
HS
1622 t4_report_fw_error(adapter);
1623
89c3a86c 1624 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
56d36be4 1625 cim_intr_info) +
89c3a86c 1626 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
56d36be4
DM
1627 cim_upintr_info);
1628 if (fat)
1629 t4_fatal_err(adapter);
1630}
1631
1632/*
1633 * ULP RX interrupt handler.
1634 */
1635static void ulprx_intr_handler(struct adapter *adapter)
1636{
005b5717 1637 static const struct intr_info ulprx_intr_info[] = {
91e9a1ec 1638 { 0x1800000, "ULPRX context error", -1, 1 },
56d36be4
DM
1639 { 0x7fffff, "ULPRX parity error", -1, 1 },
1640 { 0 }
1641 };
1642
0d804338 1643 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
56d36be4
DM
1644 t4_fatal_err(adapter);
1645}
1646
1647/*
1648 * ULP TX interrupt handler.
1649 */
1650static void ulptx_intr_handler(struct adapter *adapter)
1651{
005b5717 1652 static const struct intr_info ulptx_intr_info[] = {
837e4a42 1653 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
56d36be4 1654 0 },
837e4a42 1655 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
56d36be4 1656 0 },
837e4a42 1657 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
56d36be4 1658 0 },
837e4a42 1659 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
56d36be4
DM
1660 0 },
1661 { 0xfffffff, "ULPTX parity error", -1, 1 },
1662 { 0 }
1663 };
1664
837e4a42 1665 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
56d36be4
DM
1666 t4_fatal_err(adapter);
1667}
1668
1669/*
1670 * PM TX interrupt handler.
1671 */
1672static void pmtx_intr_handler(struct adapter *adapter)
1673{
005b5717 1674 static const struct intr_info pmtx_intr_info[] = {
837e4a42
HS
1675 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
1676 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
1677 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
1678 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
1679 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
1680 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
1681 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
1682 -1, 1 },
1683 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
1684 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
56d36be4
DM
1685 { 0 }
1686 };
1687
837e4a42 1688 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
56d36be4
DM
1689 t4_fatal_err(adapter);
1690}
1691
1692/*
1693 * PM RX interrupt handler.
1694 */
1695static void pmrx_intr_handler(struct adapter *adapter)
1696{
005b5717 1697 static const struct intr_info pmrx_intr_info[] = {
837e4a42
HS
1698 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
1699 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
1700 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
1701 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
1702 -1, 1 },
1703 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
1704 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
56d36be4
DM
1705 { 0 }
1706 };
1707
837e4a42 1708 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
56d36be4
DM
1709 t4_fatal_err(adapter);
1710}
1711
1712/*
1713 * CPL switch interrupt handler.
1714 */
1715static void cplsw_intr_handler(struct adapter *adapter)
1716{
005b5717 1717 static const struct intr_info cplsw_intr_info[] = {
0d804338
HS
1718 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
1719 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
1720 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
1721 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
1722 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
1723 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
56d36be4
DM
1724 { 0 }
1725 };
1726
0d804338 1727 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
56d36be4
DM
1728 t4_fatal_err(adapter);
1729}
1730
1731/*
1732 * LE interrupt handler.
1733 */
1734static void le_intr_handler(struct adapter *adap)
1735{
005b5717 1736 static const struct intr_info le_intr_info[] = {
0d804338
HS
1737 { LIPMISS_F, "LE LIP miss", -1, 0 },
1738 { LIP0_F, "LE 0 LIP error", -1, 0 },
1739 { PARITYERR_F, "LE parity error", -1, 1 },
1740 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
1741 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
56d36be4
DM
1742 { 0 }
1743 };
1744
0d804338 1745 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, le_intr_info))
56d36be4
DM
1746 t4_fatal_err(adap);
1747}
1748
1749/*
1750 * MPS interrupt handler.
1751 */
1752static void mps_intr_handler(struct adapter *adapter)
1753{
005b5717 1754 static const struct intr_info mps_rx_intr_info[] = {
56d36be4
DM
1755 { 0xffffff, "MPS Rx parity error", -1, 1 },
1756 { 0 }
1757 };
005b5717 1758 static const struct intr_info mps_tx_intr_info[] = {
837e4a42
HS
1759 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
1760 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
1761 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
1762 -1, 1 },
1763 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
1764 -1, 1 },
1765 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
1766 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
1767 { FRMERR_F, "MPS Tx framing error", -1, 1 },
56d36be4
DM
1768 { 0 }
1769 };
005b5717 1770 static const struct intr_info mps_trc_intr_info[] = {
837e4a42
HS
1771 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
1772 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
1773 -1, 1 },
1774 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
56d36be4
DM
1775 { 0 }
1776 };
005b5717 1777 static const struct intr_info mps_stat_sram_intr_info[] = {
56d36be4
DM
1778 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
1779 { 0 }
1780 };
005b5717 1781 static const struct intr_info mps_stat_tx_intr_info[] = {
56d36be4
DM
1782 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
1783 { 0 }
1784 };
005b5717 1785 static const struct intr_info mps_stat_rx_intr_info[] = {
56d36be4
DM
1786 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
1787 { 0 }
1788 };
005b5717 1789 static const struct intr_info mps_cls_intr_info[] = {
837e4a42
HS
1790 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
1791 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
1792 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
56d36be4
DM
1793 { 0 }
1794 };
1795
1796 int fat;
1797
837e4a42 1798 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
56d36be4 1799 mps_rx_intr_info) +
837e4a42 1800 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
56d36be4 1801 mps_tx_intr_info) +
837e4a42 1802 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
56d36be4 1803 mps_trc_intr_info) +
837e4a42 1804 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
56d36be4 1805 mps_stat_sram_intr_info) +
837e4a42 1806 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
56d36be4 1807 mps_stat_tx_intr_info) +
837e4a42 1808 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
56d36be4 1809 mps_stat_rx_intr_info) +
837e4a42 1810 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
56d36be4
DM
1811 mps_cls_intr_info);
1812
837e4a42
HS
1813 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
1814 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
56d36be4
DM
1815 if (fat)
1816 t4_fatal_err(adapter);
1817}
1818
89c3a86c
HS
1819#define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
1820 ECC_UE_INT_CAUSE_F)
56d36be4
DM
1821
1822/*
1823 * EDC/MC interrupt handler.
1824 */
1825static void mem_intr_handler(struct adapter *adapter, int idx)
1826{
822dd8a8 1827 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
56d36be4
DM
1828
1829 unsigned int addr, cnt_addr, v;
1830
1831 if (idx <= MEM_EDC1) {
89c3a86c
HS
1832 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
1833 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
822dd8a8
HS
1834 } else if (idx == MEM_MC) {
1835 if (is_t4(adapter->params.chip)) {
89c3a86c
HS
1836 addr = MC_INT_CAUSE_A;
1837 cnt_addr = MC_ECC_STATUS_A;
822dd8a8 1838 } else {
89c3a86c
HS
1839 addr = MC_P_INT_CAUSE_A;
1840 cnt_addr = MC_P_ECC_STATUS_A;
822dd8a8 1841 }
56d36be4 1842 } else {
89c3a86c
HS
1843 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
1844 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
56d36be4
DM
1845 }
1846
1847 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
89c3a86c 1848 if (v & PERR_INT_CAUSE_F)
56d36be4
DM
1849 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
1850 name[idx]);
89c3a86c
HS
1851 if (v & ECC_CE_INT_CAUSE_F) {
1852 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
56d36be4 1853
89c3a86c 1854 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
56d36be4
DM
1855 if (printk_ratelimit())
1856 dev_warn(adapter->pdev_dev,
1857 "%u %s correctable ECC data error%s\n",
1858 cnt, name[idx], cnt > 1 ? "s" : "");
1859 }
89c3a86c 1860 if (v & ECC_UE_INT_CAUSE_F)
56d36be4
DM
1861 dev_alert(adapter->pdev_dev,
1862 "%s uncorrectable ECC data error\n", name[idx]);
1863
1864 t4_write_reg(adapter, addr, v);
89c3a86c 1865 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
56d36be4
DM
1866 t4_fatal_err(adapter);
1867}
1868
1869/*
1870 * MA interrupt handler.
1871 */
1872static void ma_intr_handler(struct adapter *adap)
1873{
89c3a86c 1874 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
56d36be4 1875
89c3a86c 1876 if (status & MEM_PERR_INT_CAUSE_F) {
56d36be4
DM
1877 dev_alert(adap->pdev_dev,
1878 "MA parity error, parity status %#x\n",
89c3a86c 1879 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
9bb59b96
HS
1880 if (is_t5(adap->params.chip))
1881 dev_alert(adap->pdev_dev,
1882 "MA parity error, parity status %#x\n",
1883 t4_read_reg(adap,
89c3a86c 1884 MA_PARITY_ERROR_STATUS2_A));
9bb59b96 1885 }
89c3a86c
HS
1886 if (status & MEM_WRAP_INT_CAUSE_F) {
1887 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
56d36be4
DM
1888 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
1889 "client %u to address %#x\n",
89c3a86c
HS
1890 MEM_WRAP_CLIENT_NUM_G(v),
1891 MEM_WRAP_ADDRESS_G(v) << 4);
56d36be4 1892 }
89c3a86c 1893 t4_write_reg(adap, MA_INT_CAUSE_A, status);
56d36be4
DM
1894 t4_fatal_err(adap);
1895}
1896
1897/*
1898 * SMB interrupt handler.
1899 */
1900static void smb_intr_handler(struct adapter *adap)
1901{
005b5717 1902 static const struct intr_info smb_intr_info[] = {
0d804338
HS
1903 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
1904 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
1905 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
56d36be4
DM
1906 { 0 }
1907 };
1908
0d804338 1909 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
56d36be4
DM
1910 t4_fatal_err(adap);
1911}
1912
1913/*
1914 * NC-SI interrupt handler.
1915 */
1916static void ncsi_intr_handler(struct adapter *adap)
1917{
005b5717 1918 static const struct intr_info ncsi_intr_info[] = {
0d804338
HS
1919 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
1920 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
1921 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
1922 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
56d36be4
DM
1923 { 0 }
1924 };
1925
0d804338 1926 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
56d36be4
DM
1927 t4_fatal_err(adap);
1928}
1929
1930/*
1931 * XGMAC interrupt handler.
1932 */
1933static void xgmac_intr_handler(struct adapter *adap, int port)
1934{
0a57a536
SR
1935 u32 v, int_cause_reg;
1936
d14807dd 1937 if (is_t4(adap->params.chip))
0d804338 1938 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
0a57a536 1939 else
0d804338 1940 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
0a57a536
SR
1941
1942 v = t4_read_reg(adap, int_cause_reg);
56d36be4 1943
0d804338 1944 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
56d36be4
DM
1945 if (!v)
1946 return;
1947
0d804338 1948 if (v & TXFIFO_PRTY_ERR_F)
56d36be4
DM
1949 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
1950 port);
0d804338 1951 if (v & RXFIFO_PRTY_ERR_F)
56d36be4
DM
1952 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
1953 port);
0d804338 1954 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
56d36be4
DM
1955 t4_fatal_err(adap);
1956}
1957
1958/*
1959 * PL interrupt handler.
1960 */
1961static void pl_intr_handler(struct adapter *adap)
1962{
005b5717 1963 static const struct intr_info pl_intr_info[] = {
0d804338
HS
1964 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
1965 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
56d36be4
DM
1966 { 0 }
1967 };
1968
0d804338 1969 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
56d36be4
DM
1970 t4_fatal_err(adap);
1971}
1972
0d804338
HS
1973#define PF_INTR_MASK (PFSW_F)
1974#define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
1975 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
1976 CPL_SWITCH_F | SGE_F | ULP_TX_F)
56d36be4
DM
1977
1978/**
1979 * t4_slow_intr_handler - control path interrupt handler
1980 * @adapter: the adapter
1981 *
1982 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
1983 * The designation 'slow' is because it involves register reads, while
1984 * data interrupts typically don't involve any MMIOs.
1985 */
1986int t4_slow_intr_handler(struct adapter *adapter)
1987{
0d804338 1988 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
56d36be4
DM
1989
1990 if (!(cause & GLBL_INTR_MASK))
1991 return 0;
0d804338 1992 if (cause & CIM_F)
56d36be4 1993 cim_intr_handler(adapter);
0d804338 1994 if (cause & MPS_F)
56d36be4 1995 mps_intr_handler(adapter);
0d804338 1996 if (cause & NCSI_F)
56d36be4 1997 ncsi_intr_handler(adapter);
0d804338 1998 if (cause & PL_F)
56d36be4 1999 pl_intr_handler(adapter);
0d804338 2000 if (cause & SMB_F)
56d36be4 2001 smb_intr_handler(adapter);
0d804338 2002 if (cause & XGMAC0_F)
56d36be4 2003 xgmac_intr_handler(adapter, 0);
0d804338 2004 if (cause & XGMAC1_F)
56d36be4 2005 xgmac_intr_handler(adapter, 1);
0d804338 2006 if (cause & XGMAC_KR0_F)
56d36be4 2007 xgmac_intr_handler(adapter, 2);
0d804338 2008 if (cause & XGMAC_KR1_F)
56d36be4 2009 xgmac_intr_handler(adapter, 3);
0d804338 2010 if (cause & PCIE_F)
56d36be4 2011 pcie_intr_handler(adapter);
0d804338 2012 if (cause & MC_F)
56d36be4 2013 mem_intr_handler(adapter, MEM_MC);
0d804338 2014 if (!is_t4(adapter->params.chip) && (cause & MC1_S))
822dd8a8 2015 mem_intr_handler(adapter, MEM_MC1);
0d804338 2016 if (cause & EDC0_F)
56d36be4 2017 mem_intr_handler(adapter, MEM_EDC0);
0d804338 2018 if (cause & EDC1_F)
56d36be4 2019 mem_intr_handler(adapter, MEM_EDC1);
0d804338 2020 if (cause & LE_F)
56d36be4 2021 le_intr_handler(adapter);
0d804338 2022 if (cause & TP_F)
56d36be4 2023 tp_intr_handler(adapter);
0d804338 2024 if (cause & MA_F)
56d36be4 2025 ma_intr_handler(adapter);
0d804338 2026 if (cause & PM_TX_F)
56d36be4 2027 pmtx_intr_handler(adapter);
0d804338 2028 if (cause & PM_RX_F)
56d36be4 2029 pmrx_intr_handler(adapter);
0d804338 2030 if (cause & ULP_RX_F)
56d36be4 2031 ulprx_intr_handler(adapter);
0d804338 2032 if (cause & CPL_SWITCH_F)
56d36be4 2033 cplsw_intr_handler(adapter);
0d804338 2034 if (cause & SGE_F)
56d36be4 2035 sge_intr_handler(adapter);
0d804338 2036 if (cause & ULP_TX_F)
56d36be4
DM
2037 ulptx_intr_handler(adapter);
2038
2039 /* Clear the interrupts just processed for which we are the master. */
0d804338
HS
2040 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
2041 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
56d36be4
DM
2042 return 1;
2043}
2044
2045/**
2046 * t4_intr_enable - enable interrupts
2047 * @adapter: the adapter whose interrupts should be enabled
2048 *
2049 * Enable PF-specific interrupts for the calling function and the top-level
2050 * interrupt concentrator for global interrupts. Interrupts are already
2051 * enabled at each module, here we just enable the roots of the interrupt
2052 * hierarchies.
2053 *
2054 * Note: this function should be called only when the driver manages
2055 * non PF-specific interrupts from the various HW modules. Only one PCI
2056 * function at a time should be doing this.
2057 */
2058void t4_intr_enable(struct adapter *adapter)
2059{
0d804338 2060 u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A));
56d36be4 2061
f612b815
HS
2062 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
2063 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
2064 ERR_DROPPED_DB_F | ERR_DATA_CPL_ON_HIGH_QID1_F |
2065 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
2066 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
2067 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
2068 ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F |
2069 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F |
2070 EGRESS_SIZE_ERR_F);
0d804338
HS
2071 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
2072 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
56d36be4
DM
2073}
2074
2075/**
2076 * t4_intr_disable - disable interrupts
2077 * @adapter: the adapter whose interrupts should be disabled
2078 *
2079 * Disable interrupts. We only disable the top-level interrupt
2080 * concentrators. The caller must be a PCI function managing global
2081 * interrupts.
2082 */
2083void t4_intr_disable(struct adapter *adapter)
2084{
0d804338 2085 u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A));
56d36be4 2086
0d804338
HS
2087 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
2088 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
56d36be4
DM
2089}
2090
56d36be4
DM
2091/**
2092 * hash_mac_addr - return the hash value of a MAC address
2093 * @addr: the 48-bit Ethernet MAC address
2094 *
2095 * Hashes a MAC address according to the hash function used by HW inexact
2096 * (hash) address matching.
2097 */
2098static int hash_mac_addr(const u8 *addr)
2099{
2100 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
2101 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
2102 a ^= b;
2103 a ^= (a >> 12);
2104 a ^= (a >> 6);
2105 return a & 0x3f;
2106}
2107
2108/**
2109 * t4_config_rss_range - configure a portion of the RSS mapping table
2110 * @adapter: the adapter
2111 * @mbox: mbox to use for the FW command
2112 * @viid: virtual interface whose RSS subtable is to be written
2113 * @start: start entry in the table to write
2114 * @n: how many table entries to write
2115 * @rspq: values for the response queue lookup table
2116 * @nrspq: number of values in @rspq
2117 *
2118 * Programs the selected part of the VI's RSS mapping table with the
2119 * provided values. If @nrspq < @n the supplied values are used repeatedly
2120 * until the full table range is populated.
2121 *
2122 * The caller must ensure the values in @rspq are in the range allowed for
2123 * @viid.
2124 */
2125int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2126 int start, int n, const u16 *rspq, unsigned int nrspq)
2127{
2128 int ret;
2129 const u16 *rsp = rspq;
2130 const u16 *rsp_end = rspq + nrspq;
2131 struct fw_rss_ind_tbl_cmd cmd;
2132
2133 memset(&cmd, 0, sizeof(cmd));
e2ac9628
HS
2134 cmd.op_to_viid = htonl(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
2135 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
b2e1a3f0 2136 FW_RSS_IND_TBL_CMD_VIID_V(viid));
56d36be4
DM
2137 cmd.retval_len16 = htonl(FW_LEN16(cmd));
2138
2139 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
2140 while (n > 0) {
2141 int nq = min(n, 32);
2142 __be32 *qp = &cmd.iq0_to_iq2;
2143
2144 cmd.niqid = htons(nq);
2145 cmd.startidx = htons(start);
2146
2147 start += nq;
2148 n -= nq;
2149
2150 while (nq > 0) {
2151 unsigned int v;
2152
b2e1a3f0 2153 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
56d36be4
DM
2154 if (++rsp >= rsp_end)
2155 rsp = rspq;
b2e1a3f0 2156 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
56d36be4
DM
2157 if (++rsp >= rsp_end)
2158 rsp = rspq;
b2e1a3f0 2159 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
56d36be4
DM
2160 if (++rsp >= rsp_end)
2161 rsp = rspq;
2162
2163 *qp++ = htonl(v);
2164 nq -= 3;
2165 }
2166
2167 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2168 if (ret)
2169 return ret;
2170 }
2171 return 0;
2172}
2173
2174/**
2175 * t4_config_glbl_rss - configure the global RSS mode
2176 * @adapter: the adapter
2177 * @mbox: mbox to use for the FW command
2178 * @mode: global RSS mode
2179 * @flags: mode-specific flags
2180 *
2181 * Sets the global RSS mode.
2182 */
2183int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
2184 unsigned int flags)
2185{
2186 struct fw_rss_glb_config_cmd c;
2187
2188 memset(&c, 0, sizeof(c));
e2ac9628
HS
2189 c.op_to_write = htonl(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
2190 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
56d36be4
DM
2191 c.retval_len16 = htonl(FW_LEN16(c));
2192 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
b2e1a3f0 2193 c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
56d36be4
DM
2194 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
2195 c.u.basicvirtual.mode_pkd =
b2e1a3f0 2196 htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
56d36be4
DM
2197 c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags);
2198 } else
2199 return -EINVAL;
2200 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2201}
2202
688ea5fe
HS
2203/* Read an RSS table row */
2204static int rd_rss_row(struct adapter *adap, int row, u32 *val)
2205{
2206 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
2207 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
2208 5, 0, val);
2209}
2210
2211/**
2212 * t4_read_rss - read the contents of the RSS mapping table
2213 * @adapter: the adapter
2214 * @map: holds the contents of the RSS mapping table
2215 *
2216 * Reads the contents of the RSS hash->queue mapping table.
2217 */
2218int t4_read_rss(struct adapter *adapter, u16 *map)
2219{
2220 u32 val;
2221 int i, ret;
2222
2223 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
2224 ret = rd_rss_row(adapter, i, &val);
2225 if (ret)
2226 return ret;
2227 *map++ = LKPTBLQUEUE0_G(val);
2228 *map++ = LKPTBLQUEUE1_G(val);
2229 }
2230 return 0;
2231}
2232
2233/**
2234 * t4_read_rss_key - read the global RSS key
2235 * @adap: the adapter
2236 * @key: 10-entry array holding the 320-bit RSS key
2237 *
2238 * Reads the global 320-bit RSS key.
2239 */
2240void t4_read_rss_key(struct adapter *adap, u32 *key)
2241{
2242 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
2243 TP_RSS_SECRET_KEY0_A);
2244}
2245
2246/**
2247 * t4_write_rss_key - program one of the RSS keys
2248 * @adap: the adapter
2249 * @key: 10-entry array holding the 320-bit RSS key
2250 * @idx: which RSS key to write
2251 *
2252 * Writes one of the RSS keys with the given 320-bit value. If @idx is
2253 * 0..15 the corresponding entry in the RSS key table is written,
2254 * otherwise the global RSS key is written.
2255 */
2256void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
2257{
2258 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
2259 TP_RSS_SECRET_KEY0_A);
2260 if (idx >= 0 && idx < 16)
2261 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
2262 KEYWRADDR_V(idx) | KEYWREN_F);
2263}
2264
2265/**
2266 * t4_read_rss_pf_config - read PF RSS Configuration Table
2267 * @adapter: the adapter
2268 * @index: the entry in the PF RSS table to read
2269 * @valp: where to store the returned value
2270 *
2271 * Reads the PF RSS Configuration Table at the specified index and returns
2272 * the value found there.
2273 */
2274void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
2275 u32 *valp)
2276{
2277 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
2278 valp, 1, TP_RSS_PF0_CONFIG_A + index);
2279}
2280
2281/**
2282 * t4_read_rss_vf_config - read VF RSS Configuration Table
2283 * @adapter: the adapter
2284 * @index: the entry in the VF RSS table to read
2285 * @vfl: where to store the returned VFL
2286 * @vfh: where to store the returned VFH
2287 *
2288 * Reads the VF RSS Configuration Table at the specified index and returns
2289 * the (VFL, VFH) values found there.
2290 */
2291void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
2292 u32 *vfl, u32 *vfh)
2293{
2294 u32 vrt, mask, data;
2295
2296 mask = VFWRADDR_V(VFWRADDR_M);
2297 data = VFWRADDR_V(index);
2298
2299 /* Request that the index'th VF Table values be read into VFL/VFH.
2300 */
2301 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
2302 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
2303 vrt |= data | VFRDEN_F;
2304 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
2305
2306 /* Grab the VFL/VFH values ...
2307 */
2308 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
2309 vfl, 1, TP_RSS_VFL_CONFIG_A);
2310 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
2311 vfh, 1, TP_RSS_VFH_CONFIG_A);
2312}
2313
2314/**
2315 * t4_read_rss_pf_map - read PF RSS Map
2316 * @adapter: the adapter
2317 *
2318 * Reads the PF RSS Map register and returns its value.
2319 */
2320u32 t4_read_rss_pf_map(struct adapter *adapter)
2321{
2322 u32 pfmap;
2323
2324 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
2325 &pfmap, 1, TP_RSS_PF_MAP_A);
2326 return pfmap;
2327}
2328
2329/**
2330 * t4_read_rss_pf_mask - read PF RSS Mask
2331 * @adapter: the adapter
2332 *
2333 * Reads the PF RSS Mask register and returns its value.
2334 */
2335u32 t4_read_rss_pf_mask(struct adapter *adapter)
2336{
2337 u32 pfmask;
2338
2339 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
2340 &pfmask, 1, TP_RSS_PF_MSK_A);
2341 return pfmask;
2342}
2343
56d36be4
DM
2344/**
2345 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
2346 * @adap: the adapter
2347 * @v4: holds the TCP/IP counter values
2348 * @v6: holds the TCP/IPv6 counter values
2349 *
2350 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
2351 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
2352 */
2353void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
2354 struct tp_tcp_stats *v6)
2355{
837e4a42 2356 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
56d36be4 2357
837e4a42 2358#define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
56d36be4
DM
2359#define STAT(x) val[STAT_IDX(x)]
2360#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
2361
2362 if (v4) {
837e4a42
HS
2363 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
2364 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
56d36be4
DM
2365 v4->tcpOutRsts = STAT(OUT_RST);
2366 v4->tcpInSegs = STAT64(IN_SEG);
2367 v4->tcpOutSegs = STAT64(OUT_SEG);
2368 v4->tcpRetransSegs = STAT64(RXT_SEG);
2369 }
2370 if (v6) {
837e4a42
HS
2371 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
2372 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
56d36be4
DM
2373 v6->tcpOutRsts = STAT(OUT_RST);
2374 v6->tcpInSegs = STAT64(IN_SEG);
2375 v6->tcpOutSegs = STAT64(OUT_SEG);
2376 v6->tcpRetransSegs = STAT64(RXT_SEG);
2377 }
2378#undef STAT64
2379#undef STAT
2380#undef STAT_IDX
2381}
2382
56d36be4
DM
2383/**
2384 * t4_read_mtu_tbl - returns the values in the HW path MTU table
2385 * @adap: the adapter
2386 * @mtus: where to store the MTU values
2387 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
2388 *
2389 * Reads the HW path MTU table.
2390 */
2391void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
2392{
2393 u32 v;
2394 int i;
2395
2396 for (i = 0; i < NMTUS; ++i) {
837e4a42
HS
2397 t4_write_reg(adap, TP_MTU_TABLE_A,
2398 MTUINDEX_V(0xff) | MTUVALUE_V(i));
2399 v = t4_read_reg(adap, TP_MTU_TABLE_A);
2400 mtus[i] = MTUVALUE_G(v);
56d36be4 2401 if (mtu_log)
837e4a42 2402 mtu_log[i] = MTUWIDTH_G(v);
56d36be4
DM
2403 }
2404}
2405
636f9d37
VP
2406/**
2407 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
2408 * @adap: the adapter
2409 * @addr: the indirect TP register address
2410 * @mask: specifies the field within the register to modify
2411 * @val: new value for the field
2412 *
2413 * Sets a field of an indirect TP register to the given value.
2414 */
2415void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
2416 unsigned int mask, unsigned int val)
2417{
837e4a42
HS
2418 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
2419 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
2420 t4_write_reg(adap, TP_PIO_DATA_A, val);
636f9d37
VP
2421}
2422
56d36be4
DM
2423/**
2424 * init_cong_ctrl - initialize congestion control parameters
2425 * @a: the alpha values for congestion control
2426 * @b: the beta values for congestion control
2427 *
2428 * Initialize the congestion control parameters.
2429 */
91744948 2430static void init_cong_ctrl(unsigned short *a, unsigned short *b)
56d36be4
DM
2431{
2432 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
2433 a[9] = 2;
2434 a[10] = 3;
2435 a[11] = 4;
2436 a[12] = 5;
2437 a[13] = 6;
2438 a[14] = 7;
2439 a[15] = 8;
2440 a[16] = 9;
2441 a[17] = 10;
2442 a[18] = 14;
2443 a[19] = 17;
2444 a[20] = 21;
2445 a[21] = 25;
2446 a[22] = 30;
2447 a[23] = 35;
2448 a[24] = 45;
2449 a[25] = 60;
2450 a[26] = 80;
2451 a[27] = 100;
2452 a[28] = 200;
2453 a[29] = 300;
2454 a[30] = 400;
2455 a[31] = 500;
2456
2457 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
2458 b[9] = b[10] = 1;
2459 b[11] = b[12] = 2;
2460 b[13] = b[14] = b[15] = b[16] = 3;
2461 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
2462 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
2463 b[28] = b[29] = 6;
2464 b[30] = b[31] = 7;
2465}
2466
2467/* The minimum additive increment value for the congestion control table */
2468#define CC_MIN_INCR 2U
2469
2470/**
2471 * t4_load_mtus - write the MTU and congestion control HW tables
2472 * @adap: the adapter
2473 * @mtus: the values for the MTU table
2474 * @alpha: the values for the congestion control alpha parameter
2475 * @beta: the values for the congestion control beta parameter
2476 *
2477 * Write the HW MTU table with the supplied MTUs and the high-speed
2478 * congestion control table with the supplied alpha, beta, and MTUs.
2479 * We write the two tables together because the additive increments
2480 * depend on the MTUs.
2481 */
2482void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
2483 const unsigned short *alpha, const unsigned short *beta)
2484{
2485 static const unsigned int avg_pkts[NCCTRL_WIN] = {
2486 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2487 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2488 28672, 40960, 57344, 81920, 114688, 163840, 229376
2489 };
2490
2491 unsigned int i, w;
2492
2493 for (i = 0; i < NMTUS; ++i) {
2494 unsigned int mtu = mtus[i];
2495 unsigned int log2 = fls(mtu);
2496
2497 if (!(mtu & ((1 << log2) >> 2))) /* round */
2498 log2--;
837e4a42
HS
2499 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
2500 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
56d36be4
DM
2501
2502 for (w = 0; w < NCCTRL_WIN; ++w) {
2503 unsigned int inc;
2504
2505 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2506 CC_MIN_INCR);
2507
837e4a42 2508 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
56d36be4
DM
2509 (w << 16) | (beta[w] << 13) | inc);
2510 }
2511 }
2512}
2513
b3bbe36a
HS
2514/**
2515 * t4_pmtx_get_stats - returns the HW stats from PMTX
2516 * @adap: the adapter
2517 * @cnt: where to store the count statistics
2518 * @cycles: where to store the cycle statistics
2519 *
2520 * Returns performance statistics from PMTX.
2521 */
2522void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
2523{
2524 int i;
2525 u32 data[2];
2526
2527 for (i = 0; i < PM_NSTATS; i++) {
2528 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
2529 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
2530 if (is_t4(adap->params.chip)) {
2531 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
2532 } else {
2533 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
2534 PM_TX_DBG_DATA_A, data, 2,
2535 PM_TX_DBG_STAT_MSB_A);
2536 cycles[i] = (((u64)data[0] << 32) | data[1]);
2537 }
2538 }
2539}
2540
2541/**
2542 * t4_pmrx_get_stats - returns the HW stats from PMRX
2543 * @adap: the adapter
2544 * @cnt: where to store the count statistics
2545 * @cycles: where to store the cycle statistics
2546 *
2547 * Returns performance statistics from PMRX.
2548 */
2549void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
2550{
2551 int i;
2552 u32 data[2];
2553
2554 for (i = 0; i < PM_NSTATS; i++) {
2555 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
2556 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
2557 if (is_t4(adap->params.chip)) {
2558 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
2559 } else {
2560 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
2561 PM_RX_DBG_DATA_A, data, 2,
2562 PM_RX_DBG_STAT_MSB_A);
2563 cycles[i] = (((u64)data[0] << 32) | data[1]);
2564 }
2565 }
2566}
2567
56d36be4
DM
2568/**
2569 * get_mps_bg_map - return the buffer groups associated with a port
2570 * @adap: the adapter
2571 * @idx: the port index
2572 *
2573 * Returns a bitmap indicating which MPS buffer groups are associated
2574 * with the given port. Bit i is set if buffer group i is used by the
2575 * port.
2576 */
2577static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
2578{
837e4a42 2579 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
56d36be4
DM
2580
2581 if (n == 0)
2582 return idx == 0 ? 0xf : 0;
2583 if (n == 1)
2584 return idx < 2 ? (3 << (2 * idx)) : 0;
2585 return 1 << idx;
2586}
2587
72aca4bf
KS
2588/**
2589 * t4_get_port_type_description - return Port Type string description
2590 * @port_type: firmware Port Type enumeration
2591 */
2592const char *t4_get_port_type_description(enum fw_port_type port_type)
2593{
2594 static const char *const port_type_description[] = {
2595 "R XFI",
2596 "R XAUI",
2597 "T SGMII",
2598 "T XFI",
2599 "T XAUI",
2600 "KX4",
2601 "CX4",
2602 "KX",
2603 "KR",
2604 "R SFP+",
2605 "KR/KX",
2606 "KR/KX/KX4",
2607 "R QSFP_10G",
5aa80e51 2608 "R QSA",
72aca4bf
KS
2609 "R QSFP",
2610 "R BP40_BA",
2611 };
2612
2613 if (port_type < ARRAY_SIZE(port_type_description))
2614 return port_type_description[port_type];
2615 return "UNKNOWN";
2616}
2617
56d36be4
DM
2618/**
2619 * t4_get_port_stats - collect port statistics
2620 * @adap: the adapter
2621 * @idx: the port index
2622 * @p: the stats structure to fill
2623 *
2624 * Collect statistics related to the given port from HW.
2625 */
2626void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2627{
2628 u32 bgmap = get_mps_bg_map(adap, idx);
2629
2630#define GET_STAT(name) \
0a57a536 2631 t4_read_reg64(adap, \
d14807dd 2632 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
0a57a536 2633 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
56d36be4
DM
2634#define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
2635
2636 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2637 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2638 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2639 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2640 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2641 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2642 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2643 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2644 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2645 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2646 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2647 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2648 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2649 p->tx_drop = GET_STAT(TX_PORT_DROP);
2650 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2651 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2652 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2653 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2654 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2655 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2656 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2657 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2658 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2659
2660 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2661 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2662 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2663 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2664 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2665 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2666 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2667 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2668 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2669 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2670 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2671 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2672 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2673 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2674 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2675 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2676 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2677 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2678 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2679 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2680 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2681 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2682 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2683 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2684 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2685 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2686 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2687
2688 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2689 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2690 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2691 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2692 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2693 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2694 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2695 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2696
2697#undef GET_STAT
2698#undef GET_STAT_COM
2699}
2700
56d36be4
DM
2701/**
2702 * t4_wol_magic_enable - enable/disable magic packet WoL
2703 * @adap: the adapter
2704 * @port: the physical port index
2705 * @addr: MAC address expected in magic packets, %NULL to disable
2706 *
2707 * Enables/disables magic packet wake-on-LAN for the selected port.
2708 */
2709void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2710 const u8 *addr)
2711{
0a57a536
SR
2712 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
2713
d14807dd 2714 if (is_t4(adap->params.chip)) {
0a57a536
SR
2715 mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO);
2716 mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI);
0d804338 2717 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2_A);
0a57a536
SR
2718 } else {
2719 mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO);
2720 mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI);
837e4a42 2721 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A);
0a57a536
SR
2722 }
2723
56d36be4 2724 if (addr) {
0a57a536 2725 t4_write_reg(adap, mag_id_reg_l,
56d36be4
DM
2726 (addr[2] << 24) | (addr[3] << 16) |
2727 (addr[4] << 8) | addr[5]);
0a57a536 2728 t4_write_reg(adap, mag_id_reg_h,
56d36be4
DM
2729 (addr[0] << 8) | addr[1]);
2730 }
0d804338
HS
2731 t4_set_reg_field(adap, port_cfg_reg, MAGICEN_F,
2732 addr ? MAGICEN_F : 0);
56d36be4
DM
2733}
2734
2735/**
2736 * t4_wol_pat_enable - enable/disable pattern-based WoL
2737 * @adap: the adapter
2738 * @port: the physical port index
2739 * @map: bitmap of which HW pattern filters to set
2740 * @mask0: byte mask for bytes 0-63 of a packet
2741 * @mask1: byte mask for bytes 64-127 of a packet
2742 * @crc: Ethernet CRC for selected bytes
2743 * @enable: enable/disable switch
2744 *
2745 * Sets the pattern filters indicated in @map to mask out the bytes
2746 * specified in @mask0/@mask1 in received packets and compare the CRC of
2747 * the resulting packet against @crc. If @enable is %true pattern-based
2748 * WoL is enabled, otherwise disabled.
2749 */
2750int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2751 u64 mask0, u64 mask1, unsigned int crc, bool enable)
2752{
2753 int i;
0a57a536
SR
2754 u32 port_cfg_reg;
2755
d14807dd 2756 if (is_t4(adap->params.chip))
0d804338 2757 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2_A);
0a57a536 2758 else
837e4a42 2759 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A);
56d36be4
DM
2760
2761 if (!enable) {
0d804338 2762 t4_set_reg_field(adap, port_cfg_reg, PATEN_F, 0);
56d36be4
DM
2763 return 0;
2764 }
2765 if (map > 0xff)
2766 return -EINVAL;
2767
0a57a536 2768#define EPIO_REG(name) \
0d804338
HS
2769 (is_t4(adap->params.chip) ? \
2770 PORT_REG(port, XGMAC_PORT_EPIO_##name##_A) : \
2771 T5_PORT_REG(port, MAC_PORT_EPIO_##name##_A))
56d36be4
DM
2772
2773 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
2774 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
2775 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
2776
2777 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
2778 if (!(map & 1))
2779 continue;
2780
2781 /* write byte masks */
2782 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
0d804338 2783 t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i) | EPIOWR_F);
56d36be4 2784 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
0d804338 2785 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F)
56d36be4
DM
2786 return -ETIMEDOUT;
2787
2788 /* write CRC */
2789 t4_write_reg(adap, EPIO_REG(DATA0), crc);
0d804338 2790 t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i + 32) | EPIOWR_F);
56d36be4 2791 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
0d804338 2792 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F)
56d36be4
DM
2793 return -ETIMEDOUT;
2794 }
2795#undef EPIO_REG
2796
0d804338 2797 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2_A), 0, PATEN_F);
56d36be4
DM
2798 return 0;
2799}
2800
f2b7e78d
VP
2801/* t4_mk_filtdelwr - create a delete filter WR
2802 * @ftid: the filter ID
2803 * @wr: the filter work request to populate
2804 * @qid: ingress queue to receive the delete notification
2805 *
2806 * Creates a filter work request to delete the supplied filter. If @qid is
2807 * negative the delete notification is suppressed.
2808 */
2809void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
2810{
2811 memset(wr, 0, sizeof(*wr));
e2ac9628
HS
2812 wr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
2813 wr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*wr) / 16));
77a80e23
HS
2814 wr->tid_to_iq = htonl(FW_FILTER_WR_TID_V(ftid) |
2815 FW_FILTER_WR_NOREPLY_V(qid < 0));
2816 wr->del_filter_to_l2tix = htonl(FW_FILTER_WR_DEL_FILTER_F);
f2b7e78d 2817 if (qid >= 0)
77a80e23 2818 wr->rx_chan_rx_rpl_iq = htons(FW_FILTER_WR_RX_RPL_IQ_V(qid));
f2b7e78d
VP
2819}
2820
56d36be4 2821#define INIT_CMD(var, cmd, rd_wr) do { \
e2ac9628
HS
2822 (var).op_to_write = htonl(FW_CMD_OP_V(FW_##cmd##_CMD) | \
2823 FW_CMD_REQUEST_F | FW_CMD_##rd_wr##_F); \
56d36be4
DM
2824 (var).retval_len16 = htonl(FW_LEN16(var)); \
2825} while (0)
2826
8caa1e84
VP
2827int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
2828 u32 addr, u32 val)
2829{
2830 struct fw_ldst_cmd c;
2831
2832 memset(&c, 0, sizeof(c));
e2ac9628
HS
2833 c.op_to_addrspace = htonl(FW_CMD_OP_V(FW_LDST_CMD) | FW_CMD_REQUEST_F |
2834 FW_CMD_WRITE_F |
5167865a 2835 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE));
8caa1e84
VP
2836 c.cycles_to_len16 = htonl(FW_LEN16(c));
2837 c.u.addrval.addr = htonl(addr);
2838 c.u.addrval.val = htonl(val);
2839
2840 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2841}
2842
56d36be4
DM
2843/**
2844 * t4_mdio_rd - read a PHY register through MDIO
2845 * @adap: the adapter
2846 * @mbox: mailbox to use for the FW command
2847 * @phy_addr: the PHY address
2848 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2849 * @reg: the register to read
2850 * @valp: where to store the value
2851 *
2852 * Issues a FW command through the given mailbox to read a PHY register.
2853 */
2854int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2855 unsigned int mmd, unsigned int reg, u16 *valp)
2856{
2857 int ret;
2858 struct fw_ldst_cmd c;
2859
2860 memset(&c, 0, sizeof(c));
e2ac9628 2861 c.op_to_addrspace = htonl(FW_CMD_OP_V(FW_LDST_CMD) | FW_CMD_REQUEST_F |
5167865a 2862 FW_CMD_READ_F | FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO));
56d36be4 2863 c.cycles_to_len16 = htonl(FW_LEN16(c));
5167865a
HS
2864 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR_V(phy_addr) |
2865 FW_LDST_CMD_MMD_V(mmd));
56d36be4
DM
2866 c.u.mdio.raddr = htons(reg);
2867
2868 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2869 if (ret == 0)
2870 *valp = ntohs(c.u.mdio.rval);
2871 return ret;
2872}
2873
2874/**
2875 * t4_mdio_wr - write a PHY register through MDIO
2876 * @adap: the adapter
2877 * @mbox: mailbox to use for the FW command
2878 * @phy_addr: the PHY address
2879 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2880 * @reg: the register to write
2881 * @valp: value to write
2882 *
2883 * Issues a FW command through the given mailbox to write a PHY register.
2884 */
2885int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2886 unsigned int mmd, unsigned int reg, u16 val)
2887{
2888 struct fw_ldst_cmd c;
2889
2890 memset(&c, 0, sizeof(c));
e2ac9628 2891 c.op_to_addrspace = htonl(FW_CMD_OP_V(FW_LDST_CMD) | FW_CMD_REQUEST_F |
5167865a 2892 FW_CMD_WRITE_F | FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO));
56d36be4 2893 c.cycles_to_len16 = htonl(FW_LEN16(c));
5167865a
HS
2894 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR_V(phy_addr) |
2895 FW_LDST_CMD_MMD_V(mmd));
56d36be4
DM
2896 c.u.mdio.raddr = htons(reg);
2897 c.u.mdio.rval = htons(val);
2898
2899 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2900}
2901
68bce192
KS
2902/**
2903 * t4_sge_decode_idma_state - decode the idma state
2904 * @adap: the adapter
2905 * @state: the state idma is stuck in
2906 */
2907void t4_sge_decode_idma_state(struct adapter *adapter, int state)
2908{
2909 static const char * const t4_decode[] = {
2910 "IDMA_IDLE",
2911 "IDMA_PUSH_MORE_CPL_FIFO",
2912 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
2913 "Not used",
2914 "IDMA_PHYSADDR_SEND_PCIEHDR",
2915 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
2916 "IDMA_PHYSADDR_SEND_PAYLOAD",
2917 "IDMA_SEND_FIFO_TO_IMSG",
2918 "IDMA_FL_REQ_DATA_FL_PREP",
2919 "IDMA_FL_REQ_DATA_FL",
2920 "IDMA_FL_DROP",
2921 "IDMA_FL_H_REQ_HEADER_FL",
2922 "IDMA_FL_H_SEND_PCIEHDR",
2923 "IDMA_FL_H_PUSH_CPL_FIFO",
2924 "IDMA_FL_H_SEND_CPL",
2925 "IDMA_FL_H_SEND_IP_HDR_FIRST",
2926 "IDMA_FL_H_SEND_IP_HDR",
2927 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
2928 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
2929 "IDMA_FL_H_SEND_IP_HDR_PADDING",
2930 "IDMA_FL_D_SEND_PCIEHDR",
2931 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
2932 "IDMA_FL_D_REQ_NEXT_DATA_FL",
2933 "IDMA_FL_SEND_PCIEHDR",
2934 "IDMA_FL_PUSH_CPL_FIFO",
2935 "IDMA_FL_SEND_CPL",
2936 "IDMA_FL_SEND_PAYLOAD_FIRST",
2937 "IDMA_FL_SEND_PAYLOAD",
2938 "IDMA_FL_REQ_NEXT_DATA_FL",
2939 "IDMA_FL_SEND_NEXT_PCIEHDR",
2940 "IDMA_FL_SEND_PADDING",
2941 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
2942 "IDMA_FL_SEND_FIFO_TO_IMSG",
2943 "IDMA_FL_REQ_DATAFL_DONE",
2944 "IDMA_FL_REQ_HEADERFL_DONE",
2945 };
2946 static const char * const t5_decode[] = {
2947 "IDMA_IDLE",
2948 "IDMA_ALMOST_IDLE",
2949 "IDMA_PUSH_MORE_CPL_FIFO",
2950 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
2951 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
2952 "IDMA_PHYSADDR_SEND_PCIEHDR",
2953 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
2954 "IDMA_PHYSADDR_SEND_PAYLOAD",
2955 "IDMA_SEND_FIFO_TO_IMSG",
2956 "IDMA_FL_REQ_DATA_FL",
2957 "IDMA_FL_DROP",
2958 "IDMA_FL_DROP_SEND_INC",
2959 "IDMA_FL_H_REQ_HEADER_FL",
2960 "IDMA_FL_H_SEND_PCIEHDR",
2961 "IDMA_FL_H_PUSH_CPL_FIFO",
2962 "IDMA_FL_H_SEND_CPL",
2963 "IDMA_FL_H_SEND_IP_HDR_FIRST",
2964 "IDMA_FL_H_SEND_IP_HDR",
2965 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
2966 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
2967 "IDMA_FL_H_SEND_IP_HDR_PADDING",
2968 "IDMA_FL_D_SEND_PCIEHDR",
2969 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
2970 "IDMA_FL_D_REQ_NEXT_DATA_FL",
2971 "IDMA_FL_SEND_PCIEHDR",
2972 "IDMA_FL_PUSH_CPL_FIFO",
2973 "IDMA_FL_SEND_CPL",
2974 "IDMA_FL_SEND_PAYLOAD_FIRST",
2975 "IDMA_FL_SEND_PAYLOAD",
2976 "IDMA_FL_REQ_NEXT_DATA_FL",
2977 "IDMA_FL_SEND_NEXT_PCIEHDR",
2978 "IDMA_FL_SEND_PADDING",
2979 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
2980 };
2981 static const u32 sge_regs[] = {
f061de42
HS
2982 SGE_DEBUG_DATA_LOW_INDEX_2_A,
2983 SGE_DEBUG_DATA_LOW_INDEX_3_A,
2984 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
68bce192
KS
2985 };
2986 const char **sge_idma_decode;
2987 int sge_idma_decode_nstates;
2988 int i;
2989
2990 if (is_t4(adapter->params.chip)) {
2991 sge_idma_decode = (const char **)t4_decode;
2992 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
2993 } else {
2994 sge_idma_decode = (const char **)t5_decode;
2995 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
2996 }
2997
2998 if (state < sge_idma_decode_nstates)
2999 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
3000 else
3001 CH_WARN(adapter, "idma state %d unknown\n", state);
3002
3003 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
3004 CH_WARN(adapter, "SGE register %#x value %#x\n",
3005 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
3006}
3007
56d36be4 3008/**
636f9d37
VP
3009 * t4_fw_hello - establish communication with FW
3010 * @adap: the adapter
3011 * @mbox: mailbox to use for the FW command
3012 * @evt_mbox: mailbox to receive async FW events
3013 * @master: specifies the caller's willingness to be the device master
3014 * @state: returns the current device state (if non-NULL)
56d36be4 3015 *
636f9d37
VP
3016 * Issues a command to establish communication with FW. Returns either
3017 * an error (negative integer) or the mailbox of the Master PF.
56d36be4
DM
3018 */
3019int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3020 enum dev_master master, enum dev_state *state)
3021{
3022 int ret;
3023 struct fw_hello_cmd c;
636f9d37
VP
3024 u32 v;
3025 unsigned int master_mbox;
3026 int retries = FW_CMD_HELLO_RETRIES;
56d36be4 3027
636f9d37
VP
3028retry:
3029 memset(&c, 0, sizeof(c));
56d36be4 3030 INIT_CMD(c, HELLO, WRITE);
ce91a923 3031 c.err_to_clearinit = htonl(
5167865a
HS
3032 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
3033 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
3034 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ? mbox :
3035 FW_HELLO_CMD_MBMASTER_M) |
3036 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
3037 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
3038 FW_HELLO_CMD_CLEARINIT_F);
56d36be4 3039
636f9d37
VP
3040 /*
3041 * Issue the HELLO command to the firmware. If it's not successful
3042 * but indicates that we got a "busy" or "timeout" condition, retry
31d55c2d
HS
3043 * the HELLO until we exhaust our retry limit. If we do exceed our
3044 * retry limit, check to see if the firmware left us any error
3045 * information and report that if so.
636f9d37 3046 */
56d36be4 3047 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
636f9d37
VP
3048 if (ret < 0) {
3049 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3050 goto retry;
f061de42 3051 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
31d55c2d 3052 t4_report_fw_error(adap);
636f9d37
VP
3053 return ret;
3054 }
3055
ce91a923 3056 v = ntohl(c.err_to_clearinit);
5167865a 3057 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
636f9d37 3058 if (state) {
5167865a 3059 if (v & FW_HELLO_CMD_ERR_F)
56d36be4 3060 *state = DEV_STATE_ERR;
5167865a 3061 else if (v & FW_HELLO_CMD_INIT_F)
636f9d37 3062 *state = DEV_STATE_INIT;
56d36be4
DM
3063 else
3064 *state = DEV_STATE_UNINIT;
3065 }
636f9d37
VP
3066
3067 /*
3068 * If we're not the Master PF then we need to wait around for the
3069 * Master PF Driver to finish setting up the adapter.
3070 *
3071 * Note that we also do this wait if we're a non-Master-capable PF and
3072 * there is no current Master PF; a Master PF may show up momentarily
3073 * and we wouldn't want to fail pointlessly. (This can happen when an
3074 * OS loads lots of different drivers rapidly at the same time). In
3075 * this case, the Master PF returned by the firmware will be
b2e1a3f0 3076 * PCIE_FW_MASTER_M so the test below will work ...
636f9d37 3077 */
5167865a 3078 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
636f9d37
VP
3079 master_mbox != mbox) {
3080 int waiting = FW_CMD_HELLO_TIMEOUT;
3081
3082 /*
3083 * Wait for the firmware to either indicate an error or
3084 * initialized state. If we see either of these we bail out
3085 * and report the issue to the caller. If we exhaust the
3086 * "hello timeout" and we haven't exhausted our retries, try
3087 * again. Otherwise bail with a timeout error.
3088 */
3089 for (;;) {
3090 u32 pcie_fw;
3091
3092 msleep(50);
3093 waiting -= 50;
3094
3095 /*
3096 * If neither Error nor Initialialized are indicated
3097 * by the firmware keep waiting till we exaust our
3098 * timeout ... and then retry if we haven't exhausted
3099 * our retries ...
3100 */
f061de42
HS
3101 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
3102 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
636f9d37
VP
3103 if (waiting <= 0) {
3104 if (retries-- > 0)
3105 goto retry;
3106
3107 return -ETIMEDOUT;
3108 }
3109 continue;
3110 }
3111
3112 /*
3113 * We either have an Error or Initialized condition
3114 * report errors preferentially.
3115 */
3116 if (state) {
f061de42 3117 if (pcie_fw & PCIE_FW_ERR_F)
636f9d37 3118 *state = DEV_STATE_ERR;
f061de42 3119 else if (pcie_fw & PCIE_FW_INIT_F)
636f9d37
VP
3120 *state = DEV_STATE_INIT;
3121 }
3122
3123 /*
3124 * If we arrived before a Master PF was selected and
3125 * there's not a valid Master PF, grab its identity
3126 * for our caller.
3127 */
b2e1a3f0 3128 if (master_mbox == PCIE_FW_MASTER_M &&
f061de42 3129 (pcie_fw & PCIE_FW_MASTER_VLD_F))
b2e1a3f0 3130 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
636f9d37
VP
3131 break;
3132 }
3133 }
3134
3135 return master_mbox;
56d36be4
DM
3136}
3137
3138/**
3139 * t4_fw_bye - end communication with FW
3140 * @adap: the adapter
3141 * @mbox: mailbox to use for the FW command
3142 *
3143 * Issues a command to terminate communication with FW.
3144 */
3145int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3146{
3147 struct fw_bye_cmd c;
3148
0062b15c 3149 memset(&c, 0, sizeof(c));
56d36be4
DM
3150 INIT_CMD(c, BYE, WRITE);
3151 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3152}
3153
3154/**
3155 * t4_init_cmd - ask FW to initialize the device
3156 * @adap: the adapter
3157 * @mbox: mailbox to use for the FW command
3158 *
3159 * Issues a command to FW to partially initialize the device. This
3160 * performs initialization that generally doesn't depend on user input.
3161 */
3162int t4_early_init(struct adapter *adap, unsigned int mbox)
3163{
3164 struct fw_initialize_cmd c;
3165
0062b15c 3166 memset(&c, 0, sizeof(c));
56d36be4
DM
3167 INIT_CMD(c, INITIALIZE, WRITE);
3168 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3169}
3170
3171/**
3172 * t4_fw_reset - issue a reset to FW
3173 * @adap: the adapter
3174 * @mbox: mailbox to use for the FW command
3175 * @reset: specifies the type of reset to perform
3176 *
3177 * Issues a reset command of the specified type to FW.
3178 */
3179int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3180{
3181 struct fw_reset_cmd c;
3182
0062b15c 3183 memset(&c, 0, sizeof(c));
56d36be4
DM
3184 INIT_CMD(c, RESET, WRITE);
3185 c.val = htonl(reset);
3186 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3187}
3188
26f7cbc0
VP
3189/**
3190 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3191 * @adap: the adapter
3192 * @mbox: mailbox to use for the FW RESET command (if desired)
3193 * @force: force uP into RESET even if FW RESET command fails
3194 *
3195 * Issues a RESET command to firmware (if desired) with a HALT indication
3196 * and then puts the microprocessor into RESET state. The RESET command
3197 * will only be issued if a legitimate mailbox is provided (mbox <=
b2e1a3f0 3198 * PCIE_FW_MASTER_M).
26f7cbc0
VP
3199 *
3200 * This is generally used in order for the host to safely manipulate the
3201 * adapter without fear of conflicting with whatever the firmware might
3202 * be doing. The only way out of this state is to RESTART the firmware
3203 * ...
3204 */
de5b8677 3205static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
26f7cbc0
VP
3206{
3207 int ret = 0;
3208
3209 /*
3210 * If a legitimate mailbox is provided, issue a RESET command
3211 * with a HALT indication.
3212 */
b2e1a3f0 3213 if (mbox <= PCIE_FW_MASTER_M) {
26f7cbc0
VP
3214 struct fw_reset_cmd c;
3215
3216 memset(&c, 0, sizeof(c));
3217 INIT_CMD(c, RESET, WRITE);
0d804338 3218 c.val = htonl(PIORST_F | PIORSTMODE_F);
5167865a 3219 c.halt_pkd = htonl(FW_RESET_CMD_HALT_F);
26f7cbc0
VP
3220 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3221 }
3222
3223 /*
3224 * Normally we won't complete the operation if the firmware RESET
3225 * command fails but if our caller insists we'll go ahead and put the
3226 * uP into RESET. This can be useful if the firmware is hung or even
3227 * missing ... We'll have to take the risk of putting the uP into
3228 * RESET without the cooperation of firmware in that case.
3229 *
3230 * We also force the firmware's HALT flag to be on in case we bypassed
3231 * the firmware RESET command above or we're dealing with old firmware
3232 * which doesn't have the HALT capability. This will serve as a flag
3233 * for the incoming firmware to know that it's coming out of a HALT
3234 * rather than a RESET ... if it's new enough to understand that ...
3235 */
3236 if (ret == 0 || force) {
89c3a86c 3237 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
f061de42 3238 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
b2e1a3f0 3239 PCIE_FW_HALT_F);
26f7cbc0
VP
3240 }
3241
3242 /*
3243 * And we always return the result of the firmware RESET command
3244 * even when we force the uP into RESET ...
3245 */
3246 return ret;
3247}
3248
3249/**
3250 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3251 * @adap: the adapter
3252 * @reset: if we want to do a RESET to restart things
3253 *
3254 * Restart firmware previously halted by t4_fw_halt(). On successful
3255 * return the previous PF Master remains as the new PF Master and there
3256 * is no need to issue a new HELLO command, etc.
3257 *
3258 * We do this in two ways:
3259 *
3260 * 1. If we're dealing with newer firmware we'll simply want to take
3261 * the chip's microprocessor out of RESET. This will cause the
3262 * firmware to start up from its start vector. And then we'll loop
3263 * until the firmware indicates it's started again (PCIE_FW.HALT
3264 * reset to 0) or we timeout.
3265 *
3266 * 2. If we're dealing with older firmware then we'll need to RESET
3267 * the chip since older firmware won't recognize the PCIE_FW.HALT
3268 * flag and automatically RESET itself on startup.
3269 */
de5b8677 3270static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
26f7cbc0
VP
3271{
3272 if (reset) {
3273 /*
3274 * Since we're directing the RESET instead of the firmware
3275 * doing it automatically, we need to clear the PCIE_FW.HALT
3276 * bit.
3277 */
f061de42 3278 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
26f7cbc0
VP
3279
3280 /*
3281 * If we've been given a valid mailbox, first try to get the
3282 * firmware to do the RESET. If that works, great and we can
3283 * return success. Otherwise, if we haven't been given a
3284 * valid mailbox or the RESET command failed, fall back to
3285 * hitting the chip with a hammer.
3286 */
b2e1a3f0 3287 if (mbox <= PCIE_FW_MASTER_M) {
89c3a86c 3288 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
26f7cbc0
VP
3289 msleep(100);
3290 if (t4_fw_reset(adap, mbox,
0d804338 3291 PIORST_F | PIORSTMODE_F) == 0)
26f7cbc0
VP
3292 return 0;
3293 }
3294
0d804338 3295 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
26f7cbc0
VP
3296 msleep(2000);
3297 } else {
3298 int ms;
3299
89c3a86c 3300 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
26f7cbc0 3301 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
f061de42 3302 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
26f7cbc0
VP
3303 return 0;
3304 msleep(100);
3305 ms += 100;
3306 }
3307 return -ETIMEDOUT;
3308 }
3309 return 0;
3310}
3311
3312/**
3313 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
3314 * @adap: the adapter
3315 * @mbox: mailbox to use for the FW RESET command (if desired)
3316 * @fw_data: the firmware image to write
3317 * @size: image size
3318 * @force: force upgrade even if firmware doesn't cooperate
3319 *
3320 * Perform all of the steps necessary for upgrading an adapter's
3321 * firmware image. Normally this requires the cooperation of the
3322 * existing firmware in order to halt all existing activities
3323 * but if an invalid mailbox token is passed in we skip that step
3324 * (though we'll still put the adapter microprocessor into RESET in
3325 * that case).
3326 *
3327 * On successful return the new firmware will have been loaded and
3328 * the adapter will have been fully RESET losing all previous setup
3329 * state. On unsuccessful return the adapter may be completely hosed ...
3330 * positive errno indicates that the adapter is ~probably~ intact, a
3331 * negative errno indicates that things are looking bad ...
3332 */
22c0b963
HS
3333int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
3334 const u8 *fw_data, unsigned int size, int force)
26f7cbc0
VP
3335{
3336 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
3337 int reset, ret;
3338
79af221d
HS
3339 if (!t4_fw_matches_chip(adap, fw_hdr))
3340 return -EINVAL;
3341
26f7cbc0
VP
3342 ret = t4_fw_halt(adap, mbox, force);
3343 if (ret < 0 && !force)
3344 return ret;
3345
3346 ret = t4_load_fw(adap, fw_data, size);
3347 if (ret < 0)
3348 return ret;
3349
3350 /*
3351 * Older versions of the firmware don't understand the new
3352 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
3353 * restart. So for newly loaded older firmware we'll have to do the
3354 * RESET for it so it starts up on a clean slate. We can tell if
3355 * the newly loaded firmware will handle this right by checking
3356 * its header flags to see if it advertises the capability.
3357 */
3358 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
3359 return t4_fw_restart(adap, mbox, reset);
3360}
3361
636f9d37
VP
3362/**
3363 * t4_fixup_host_params - fix up host-dependent parameters
3364 * @adap: the adapter
3365 * @page_size: the host's Base Page Size
3366 * @cache_line_size: the host's Cache Line Size
3367 *
3368 * Various registers in T4 contain values which are dependent on the
3369 * host's Base Page and Cache Line Sizes. This function will fix all of
3370 * those registers with the appropriate values as passed in ...
3371 */
3372int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3373 unsigned int cache_line_size)
3374{
3375 unsigned int page_shift = fls(page_size) - 1;
3376 unsigned int sge_hps = page_shift - 10;
3377 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3378 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3379 unsigned int fl_align_log = fls(fl_align) - 1;
3380
f612b815
HS
3381 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
3382 HOSTPAGESIZEPF0_V(sge_hps) |
3383 HOSTPAGESIZEPF1_V(sge_hps) |
3384 HOSTPAGESIZEPF2_V(sge_hps) |
3385 HOSTPAGESIZEPF3_V(sge_hps) |
3386 HOSTPAGESIZEPF4_V(sge_hps) |
3387 HOSTPAGESIZEPF5_V(sge_hps) |
3388 HOSTPAGESIZEPF6_V(sge_hps) |
3389 HOSTPAGESIZEPF7_V(sge_hps));
636f9d37 3390
ce8f407a 3391 if (is_t4(adap->params.chip)) {
f612b815
HS
3392 t4_set_reg_field(adap, SGE_CONTROL_A,
3393 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
3394 EGRSTATUSPAGESIZE_F,
3395 INGPADBOUNDARY_V(fl_align_log -
3396 INGPADBOUNDARY_SHIFT_X) |
3397 EGRSTATUSPAGESIZE_V(stat_len != 64));
ce8f407a
HS
3398 } else {
3399 /* T5 introduced the separation of the Free List Padding and
3400 * Packing Boundaries. Thus, we can select a smaller Padding
3401 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3402 * Bandwidth, and use a Packing Boundary which is large enough
3403 * to avoid false sharing between CPUs, etc.
3404 *
3405 * For the PCI Link, the smaller the Padding Boundary the
3406 * better. For the Memory Controller, a smaller Padding
3407 * Boundary is better until we cross under the Memory Line
3408 * Size (the minimum unit of transfer to/from Memory). If we
3409 * have a Padding Boundary which is smaller than the Memory
3410 * Line Size, that'll involve a Read-Modify-Write cycle on the
3411 * Memory Controller which is never good. For T5 the smallest
3412 * Padding Boundary which we can select is 32 bytes which is
3413 * larger than any known Memory Controller Line Size so we'll
3414 * use that.
3415 *
3416 * T5 has a different interpretation of the "0" value for the
3417 * Packing Boundary. This corresponds to 16 bytes instead of
3418 * the expected 32 bytes. We never have a Packing Boundary
3419 * less than 32 bytes so we can't use that special value but
3420 * on the other hand, if we wanted 32 bytes, the best we can
3421 * really do is 64 bytes.
3422 */
3423 if (fl_align <= 32) {
3424 fl_align = 64;
3425 fl_align_log = 6;
3426 }
f612b815
HS
3427 t4_set_reg_field(adap, SGE_CONTROL_A,
3428 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
3429 EGRSTATUSPAGESIZE_F,
3430 INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X) |
3431 EGRSTATUSPAGESIZE_V(stat_len != 64));
ce8f407a
HS
3432 t4_set_reg_field(adap, SGE_CONTROL2_A,
3433 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
3434 INGPACKBOUNDARY_V(fl_align_log -
f612b815 3435 INGPACKBOUNDARY_SHIFT_X));
ce8f407a 3436 }
636f9d37
VP
3437 /*
3438 * Adjust various SGE Free List Host Buffer Sizes.
3439 *
3440 * This is something of a crock since we're using fixed indices into
3441 * the array which are also known by the sge.c code and the T4
3442 * Firmware Configuration File. We need to come up with a much better
3443 * approach to managing this array. For now, the first four entries
3444 * are:
3445 *
3446 * 0: Host Page Size
3447 * 1: 64KB
3448 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3449 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3450 *
3451 * For the single-MTU buffers in unpacked mode we need to include
3452 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3453 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3454 * Padding boundry. All of these are accommodated in the Factory
3455 * Default Firmware Configuration File but we need to adjust it for
3456 * this host's cache line size.
3457 */
f612b815
HS
3458 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
3459 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
3460 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
636f9d37 3461 & ~(fl_align-1));
f612b815
HS
3462 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
3463 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
636f9d37
VP
3464 & ~(fl_align-1));
3465
0d804338 3466 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
636f9d37
VP
3467
3468 return 0;
3469}
3470
3471/**
3472 * t4_fw_initialize - ask FW to initialize the device
3473 * @adap: the adapter
3474 * @mbox: mailbox to use for the FW command
3475 *
3476 * Issues a command to FW to partially initialize the device. This
3477 * performs initialization that generally doesn't depend on user input.
3478 */
3479int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3480{
3481 struct fw_initialize_cmd c;
3482
3483 memset(&c, 0, sizeof(c));
3484 INIT_CMD(c, INITIALIZE, WRITE);
3485 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3486}
3487
56d36be4
DM
3488/**
3489 * t4_query_params - query FW or device parameters
3490 * @adap: the adapter
3491 * @mbox: mailbox to use for the FW command
3492 * @pf: the PF
3493 * @vf: the VF
3494 * @nparams: the number of parameters
3495 * @params: the parameter names
3496 * @val: the parameter values
3497 *
3498 * Reads the value of FW or device parameters. Up to 7 parameters can be
3499 * queried at once.
3500 */
3501int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3502 unsigned int vf, unsigned int nparams, const u32 *params,
3503 u32 *val)
3504{
3505 int i, ret;
3506 struct fw_params_cmd c;
3507 __be32 *p = &c.param[0].mnem;
3508
3509 if (nparams > 7)
3510 return -EINVAL;
3511
3512 memset(&c, 0, sizeof(c));
e2ac9628 3513 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_PARAMS_CMD) | FW_CMD_REQUEST_F |
5167865a
HS
3514 FW_CMD_READ_F | FW_PARAMS_CMD_PFN_V(pf) |
3515 FW_PARAMS_CMD_VFN_V(vf));
56d36be4
DM
3516 c.retval_len16 = htonl(FW_LEN16(c));
3517 for (i = 0; i < nparams; i++, p += 2)
3518 *p = htonl(*params++);
3519
3520 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3521 if (ret == 0)
3522 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3523 *val++ = ntohl(*p);
3524 return ret;
3525}
3526
688848b1
AB
3527/**
3528 * t4_set_params_nosleep - sets FW or device parameters
3529 * @adap: the adapter
3530 * @mbox: mailbox to use for the FW command
3531 * @pf: the PF
3532 * @vf: the VF
3533 * @nparams: the number of parameters
3534 * @params: the parameter names
3535 * @val: the parameter values
3536 *
3537 * Does not ever sleep
3538 * Sets the value of FW or device parameters. Up to 7 parameters can be
3539 * specified at once.
3540 */
3541int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox,
3542 unsigned int pf, unsigned int vf,
3543 unsigned int nparams, const u32 *params,
3544 const u32 *val)
3545{
3546 struct fw_params_cmd c;
3547 __be32 *p = &c.param[0].mnem;
3548
3549 if (nparams > 7)
3550 return -EINVAL;
3551
3552 memset(&c, 0, sizeof(c));
e2ac9628
HS
3553 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3554 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5167865a
HS
3555 FW_PARAMS_CMD_PFN_V(pf) |
3556 FW_PARAMS_CMD_VFN_V(vf));
688848b1
AB
3557 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3558
3559 while (nparams--) {
3560 *p++ = cpu_to_be32(*params++);
3561 *p++ = cpu_to_be32(*val++);
3562 }
3563
3564 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3565}
3566
56d36be4
DM
3567/**
3568 * t4_set_params - sets FW or device parameters
3569 * @adap: the adapter
3570 * @mbox: mailbox to use for the FW command
3571 * @pf: the PF
3572 * @vf: the VF
3573 * @nparams: the number of parameters
3574 * @params: the parameter names
3575 * @val: the parameter values
3576 *
3577 * Sets the value of FW or device parameters. Up to 7 parameters can be
3578 * specified at once.
3579 */
3580int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3581 unsigned int vf, unsigned int nparams, const u32 *params,
3582 const u32 *val)
3583{
3584 struct fw_params_cmd c;
3585 __be32 *p = &c.param[0].mnem;
3586
3587 if (nparams > 7)
3588 return -EINVAL;
3589
3590 memset(&c, 0, sizeof(c));
e2ac9628 3591 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_PARAMS_CMD) | FW_CMD_REQUEST_F |
5167865a
HS
3592 FW_CMD_WRITE_F | FW_PARAMS_CMD_PFN_V(pf) |
3593 FW_PARAMS_CMD_VFN_V(vf));
56d36be4
DM
3594 c.retval_len16 = htonl(FW_LEN16(c));
3595 while (nparams--) {
3596 *p++ = htonl(*params++);
3597 *p++ = htonl(*val++);
3598 }
3599
3600 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3601}
3602
3603/**
3604 * t4_cfg_pfvf - configure PF/VF resource limits
3605 * @adap: the adapter
3606 * @mbox: mailbox to use for the FW command
3607 * @pf: the PF being configured
3608 * @vf: the VF being configured
3609 * @txq: the max number of egress queues
3610 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
3611 * @rxqi: the max number of interrupt-capable ingress queues
3612 * @rxq: the max number of interruptless ingress queues
3613 * @tc: the PCI traffic class
3614 * @vi: the max number of virtual interfaces
3615 * @cmask: the channel access rights mask for the PF/VF
3616 * @pmask: the port access rights mask for the PF/VF
3617 * @nexact: the maximum number of exact MPS filters
3618 * @rcaps: read capabilities
3619 * @wxcaps: write/execute capabilities
3620 *
3621 * Configures resource limits and capabilities for a physical or virtual
3622 * function.
3623 */
3624int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
3625 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
3626 unsigned int rxqi, unsigned int rxq, unsigned int tc,
3627 unsigned int vi, unsigned int cmask, unsigned int pmask,
3628 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
3629{
3630 struct fw_pfvf_cmd c;
3631
3632 memset(&c, 0, sizeof(c));
e2ac9628 3633 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
5167865a
HS
3634 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
3635 FW_PFVF_CMD_VFN_V(vf));
56d36be4 3636 c.retval_len16 = htonl(FW_LEN16(c));
5167865a
HS
3637 c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
3638 FW_PFVF_CMD_NIQ_V(rxq));
3639 c.type_to_neq = htonl(FW_PFVF_CMD_CMASK_V(cmask) |
3640 FW_PFVF_CMD_PMASK_V(pmask) |
3641 FW_PFVF_CMD_NEQ_V(txq));
3642 c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC_V(tc) | FW_PFVF_CMD_NVI_V(vi) |
3643 FW_PFVF_CMD_NEXACTF_V(nexact));
3644 c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS_V(rcaps) |
3645 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
3646 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
56d36be4
DM
3647 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3648}
3649
3650/**
3651 * t4_alloc_vi - allocate a virtual interface
3652 * @adap: the adapter
3653 * @mbox: mailbox to use for the FW command
3654 * @port: physical port associated with the VI
3655 * @pf: the PF owning the VI
3656 * @vf: the VF owning the VI
3657 * @nmac: number of MAC addresses needed (1 to 5)
3658 * @mac: the MAC addresses of the VI
3659 * @rss_size: size of RSS table slice associated with this VI
3660 *
3661 * Allocates a virtual interface for the given physical port. If @mac is
3662 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3663 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3664 * stored consecutively so the space needed is @nmac * 6 bytes.
3665 * Returns a negative error number or the non-negative VI id.
3666 */
3667int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3668 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3669 unsigned int *rss_size)
3670{
3671 int ret;
3672 struct fw_vi_cmd c;
3673
3674 memset(&c, 0, sizeof(c));
e2ac9628
HS
3675 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
3676 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
2b5fb1f2
HS
3677 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
3678 c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
3679 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
56d36be4
DM
3680 c.nmac = nmac - 1;
3681
3682 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3683 if (ret)
3684 return ret;
3685
3686 if (mac) {
3687 memcpy(mac, c.mac, sizeof(c.mac));
3688 switch (nmac) {
3689 case 5:
3690 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3691 case 4:
3692 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3693 case 3:
3694 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3695 case 2:
3696 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3697 }
3698 }
3699 if (rss_size)
2b5fb1f2
HS
3700 *rss_size = FW_VI_CMD_RSSSIZE_G(ntohs(c.rsssize_pkd));
3701 return FW_VI_CMD_VIID_G(ntohs(c.type_viid));
56d36be4
DM
3702}
3703
56d36be4
DM
3704/**
3705 * t4_set_rxmode - set Rx properties of a virtual interface
3706 * @adap: the adapter
3707 * @mbox: mailbox to use for the FW command
3708 * @viid: the VI id
3709 * @mtu: the new MTU or -1
3710 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3711 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3712 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
f8f5aafa 3713 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
56d36be4
DM
3714 * @sleep_ok: if true we may sleep while awaiting command completion
3715 *
3716 * Sets Rx properties of a virtual interface.
3717 */
3718int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM
3719 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3720 bool sleep_ok)
56d36be4
DM
3721{
3722 struct fw_vi_rxmode_cmd c;
3723
3724 /* convert to FW values */
3725 if (mtu < 0)
3726 mtu = FW_RXMODE_MTU_NO_CHG;
3727 if (promisc < 0)
2b5fb1f2 3728 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
56d36be4 3729 if (all_multi < 0)
2b5fb1f2 3730 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
56d36be4 3731 if (bcast < 0)
2b5fb1f2 3732 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
f8f5aafa 3733 if (vlanex < 0)
2b5fb1f2 3734 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
56d36be4
DM
3735
3736 memset(&c, 0, sizeof(c));
e2ac9628 3737 c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST_F |
2b5fb1f2 3738 FW_CMD_WRITE_F | FW_VI_RXMODE_CMD_VIID_V(viid));
56d36be4 3739 c.retval_len16 = htonl(FW_LEN16(c));
2b5fb1f2
HS
3740 c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU_V(mtu) |
3741 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
3742 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
3743 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
3744 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
56d36be4
DM
3745 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3746}
3747
3748/**
3749 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
3750 * @adap: the adapter
3751 * @mbox: mailbox to use for the FW command
3752 * @viid: the VI id
3753 * @free: if true any existing filters for this VI id are first removed
3754 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
3755 * @addr: the MAC address(es)
3756 * @idx: where to store the index of each allocated filter
3757 * @hash: pointer to hash address filter bitmap
3758 * @sleep_ok: call is allowed to sleep
3759 *
3760 * Allocates an exact-match filter for each of the supplied addresses and
3761 * sets it to the corresponding address. If @idx is not %NULL it should
3762 * have at least @naddr entries, each of which will be set to the index of
3763 * the filter allocated for the corresponding MAC address. If a filter
3764 * could not be allocated for an address its index is set to 0xffff.
3765 * If @hash is not %NULL addresses that fail to allocate an exact filter
3766 * are hashed and update the hash filter bitmap pointed at by @hash.
3767 *
3768 * Returns a negative error number or the number of filters allocated.
3769 */
3770int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
3771 unsigned int viid, bool free, unsigned int naddr,
3772 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
3773{
3774 int i, ret;
3775 struct fw_vi_mac_cmd c;
3776 struct fw_vi_mac_exact *p;
d14807dd 3777 unsigned int max_naddr = is_t4(adap->params.chip) ?
0a57a536
SR
3778 NUM_MPS_CLS_SRAM_L_INSTANCES :
3779 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
56d36be4
DM
3780
3781 if (naddr > 7)
3782 return -EINVAL;
3783
3784 memset(&c, 0, sizeof(c));
e2ac9628
HS
3785 c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_MAC_CMD) | FW_CMD_REQUEST_F |
3786 FW_CMD_WRITE_F | (free ? FW_CMD_EXEC_F : 0) |
2b5fb1f2
HS
3787 FW_VI_MAC_CMD_VIID_V(viid));
3788 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS_V(free) |
e2ac9628 3789 FW_CMD_LEN16_V((naddr + 2) / 2));
56d36be4
DM
3790
3791 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
2b5fb1f2
HS
3792 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID_F |
3793 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
56d36be4
DM
3794 memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
3795 }
3796
3797 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
3798 if (ret)
3799 return ret;
3800
3801 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
2b5fb1f2 3802 u16 index = FW_VI_MAC_CMD_IDX_G(ntohs(p->valid_to_idx));
56d36be4
DM
3803
3804 if (idx)
0a57a536
SR
3805 idx[i] = index >= max_naddr ? 0xffff : index;
3806 if (index < max_naddr)
56d36be4
DM
3807 ret++;
3808 else if (hash)
ce9aeb58 3809 *hash |= (1ULL << hash_mac_addr(addr[i]));
56d36be4
DM
3810 }
3811 return ret;
3812}
3813
3814/**
3815 * t4_change_mac - modifies the exact-match filter for a MAC address
3816 * @adap: the adapter
3817 * @mbox: mailbox to use for the FW command
3818 * @viid: the VI id
3819 * @idx: index of existing filter for old value of MAC address, or -1
3820 * @addr: the new MAC address value
3821 * @persist: whether a new MAC allocation should be persistent
3822 * @add_smt: if true also add the address to the HW SMT
3823 *
3824 * Modifies an exact-match filter and sets it to the new MAC address.
3825 * Note that in general it is not possible to modify the value of a given
3826 * filter so the generic way to modify an address filter is to free the one
3827 * being used by the old address value and allocate a new filter for the
3828 * new address value. @idx can be -1 if the address is a new addition.
3829 *
3830 * Returns a negative error number or the index of the filter with the new
3831 * MAC value.
3832 */
3833int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3834 int idx, const u8 *addr, bool persist, bool add_smt)
3835{
3836 int ret, mode;
3837 struct fw_vi_mac_cmd c;
3838 struct fw_vi_mac_exact *p = c.u.exact;
d14807dd 3839 unsigned int max_mac_addr = is_t4(adap->params.chip) ?
0a57a536
SR
3840 NUM_MPS_CLS_SRAM_L_INSTANCES :
3841 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
56d36be4
DM
3842
3843 if (idx < 0) /* new allocation */
3844 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3845 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3846
3847 memset(&c, 0, sizeof(c));
e2ac9628 3848 c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_MAC_CMD) | FW_CMD_REQUEST_F |
2b5fb1f2 3849 FW_CMD_WRITE_F | FW_VI_MAC_CMD_VIID_V(viid));
e2ac9628 3850 c.freemacs_to_len16 = htonl(FW_CMD_LEN16_V(1));
2b5fb1f2
HS
3851 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID_F |
3852 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
3853 FW_VI_MAC_CMD_IDX_V(idx));
56d36be4
DM
3854 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3855
3856 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3857 if (ret == 0) {
2b5fb1f2 3858 ret = FW_VI_MAC_CMD_IDX_G(ntohs(p->valid_to_idx));
0a57a536 3859 if (ret >= max_mac_addr)
56d36be4
DM
3860 ret = -ENOMEM;
3861 }
3862 return ret;
3863}
3864
3865/**
3866 * t4_set_addr_hash - program the MAC inexact-match hash filter
3867 * @adap: the adapter
3868 * @mbox: mailbox to use for the FW command
3869 * @viid: the VI id
3870 * @ucast: whether the hash filter should also match unicast addresses
3871 * @vec: the value to be written to the hash filter
3872 * @sleep_ok: call is allowed to sleep
3873 *
3874 * Sets the 64-bit inexact-match hash filter for a virtual interface.
3875 */
3876int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
3877 bool ucast, u64 vec, bool sleep_ok)
3878{
3879 struct fw_vi_mac_cmd c;
3880
3881 memset(&c, 0, sizeof(c));
e2ac9628 3882 c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_MAC_CMD) | FW_CMD_REQUEST_F |
2b5fb1f2
HS
3883 FW_CMD_WRITE_F | FW_VI_ENABLE_CMD_VIID_V(viid));
3884 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN_F |
3885 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
e2ac9628 3886 FW_CMD_LEN16_V(1));
56d36be4
DM
3887 c.u.hash.hashvec = cpu_to_be64(vec);
3888 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3889}
3890
688848b1
AB
3891/**
3892 * t4_enable_vi_params - enable/disable a virtual interface
3893 * @adap: the adapter
3894 * @mbox: mailbox to use for the FW command
3895 * @viid: the VI id
3896 * @rx_en: 1=enable Rx, 0=disable Rx
3897 * @tx_en: 1=enable Tx, 0=disable Tx
3898 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3899 *
3900 * Enables/disables a virtual interface. Note that setting DCB Enable
3901 * only makes sense when enabling a Virtual Interface ...
3902 */
3903int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3904 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3905{
3906 struct fw_vi_enable_cmd c;
3907
3908 memset(&c, 0, sizeof(c));
e2ac9628 3909 c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST_F |
2b5fb1f2 3910 FW_CMD_EXEC_F | FW_VI_ENABLE_CMD_VIID_V(viid));
688848b1 3911
2b5fb1f2
HS
3912 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
3913 FW_VI_ENABLE_CMD_EEN_V(tx_en) | FW_LEN16(c) |
3914 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en));
30f00847 3915 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
688848b1
AB
3916}
3917
56d36be4
DM
3918/**
3919 * t4_enable_vi - enable/disable a virtual interface
3920 * @adap: the adapter
3921 * @mbox: mailbox to use for the FW command
3922 * @viid: the VI id
3923 * @rx_en: 1=enable Rx, 0=disable Rx
3924 * @tx_en: 1=enable Tx, 0=disable Tx
3925 *
3926 * Enables/disables a virtual interface.
3927 */
3928int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3929 bool rx_en, bool tx_en)
3930{
688848b1 3931 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
56d36be4
DM
3932}
3933
3934/**
3935 * t4_identify_port - identify a VI's port by blinking its LED
3936 * @adap: the adapter
3937 * @mbox: mailbox to use for the FW command
3938 * @viid: the VI id
3939 * @nblinks: how many times to blink LED at 2.5 Hz
3940 *
3941 * Identifies a VI's port by blinking its LED.
3942 */
3943int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
3944 unsigned int nblinks)
3945{
3946 struct fw_vi_enable_cmd c;
3947
0062b15c 3948 memset(&c, 0, sizeof(c));
e2ac9628 3949 c.op_to_viid = htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST_F |
2b5fb1f2
HS
3950 FW_CMD_EXEC_F | FW_VI_ENABLE_CMD_VIID_V(viid));
3951 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
56d36be4
DM
3952 c.blinkdur = htons(nblinks);
3953 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
56d36be4
DM
3954}
3955
3956/**
3957 * t4_iq_free - free an ingress queue and its FLs
3958 * @adap: the adapter
3959 * @mbox: mailbox to use for the FW command
3960 * @pf: the PF owning the queues
3961 * @vf: the VF owning the queues
3962 * @iqtype: the ingress queue type
3963 * @iqid: ingress queue id
3964 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3965 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3966 *
3967 * Frees an ingress queue and its associated FLs, if any.
3968 */
3969int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3970 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3971 unsigned int fl0id, unsigned int fl1id)
3972{
3973 struct fw_iq_cmd c;
3974
3975 memset(&c, 0, sizeof(c));
e2ac9628 3976 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
6e4b51a6
HS
3977 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
3978 FW_IQ_CMD_VFN_V(vf));
3979 c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE_F | FW_LEN16(c));
3980 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(iqtype));
56d36be4
DM
3981 c.iqid = htons(iqid);
3982 c.fl0id = htons(fl0id);
3983 c.fl1id = htons(fl1id);
3984 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3985}
3986
3987/**
3988 * t4_eth_eq_free - free an Ethernet egress queue
3989 * @adap: the adapter
3990 * @mbox: mailbox to use for the FW command
3991 * @pf: the PF owning the queue
3992 * @vf: the VF owning the queue
3993 * @eqid: egress queue id
3994 *
3995 * Frees an Ethernet egress queue.
3996 */
3997int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3998 unsigned int vf, unsigned int eqid)
3999{
4000 struct fw_eq_eth_cmd c;
4001
4002 memset(&c, 0, sizeof(c));
e2ac9628 4003 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F |
6e4b51a6
HS
4004 FW_CMD_EXEC_F | FW_EQ_ETH_CMD_PFN_V(pf) |
4005 FW_EQ_ETH_CMD_VFN_V(vf));
4006 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
4007 c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID_V(eqid));
56d36be4
DM
4008 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4009}
4010
4011/**
4012 * t4_ctrl_eq_free - free a control egress queue
4013 * @adap: the adapter
4014 * @mbox: mailbox to use for the FW command
4015 * @pf: the PF owning the queue
4016 * @vf: the VF owning the queue
4017 * @eqid: egress queue id
4018 *
4019 * Frees a control egress queue.
4020 */
4021int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4022 unsigned int vf, unsigned int eqid)
4023{
4024 struct fw_eq_ctrl_cmd c;
4025
4026 memset(&c, 0, sizeof(c));
e2ac9628 4027 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F |
6e4b51a6
HS
4028 FW_CMD_EXEC_F | FW_EQ_CTRL_CMD_PFN_V(pf) |
4029 FW_EQ_CTRL_CMD_VFN_V(vf));
4030 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
4031 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID_V(eqid));
56d36be4
DM
4032 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4033}
4034
4035/**
4036 * t4_ofld_eq_free - free an offload egress queue
4037 * @adap: the adapter
4038 * @mbox: mailbox to use for the FW command
4039 * @pf: the PF owning the queue
4040 * @vf: the VF owning the queue
4041 * @eqid: egress queue id
4042 *
4043 * Frees a control egress queue.
4044 */
4045int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4046 unsigned int vf, unsigned int eqid)
4047{
4048 struct fw_eq_ofld_cmd c;
4049
4050 memset(&c, 0, sizeof(c));
e2ac9628 4051 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F |
6e4b51a6
HS
4052 FW_CMD_EXEC_F | FW_EQ_OFLD_CMD_PFN_V(pf) |
4053 FW_EQ_OFLD_CMD_VFN_V(vf));
4054 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
4055 c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID_V(eqid));
56d36be4
DM
4056 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4057}
4058
4059/**
4060 * t4_handle_fw_rpl - process a FW reply message
4061 * @adap: the adapter
4062 * @rpl: start of the FW message
4063 *
4064 * Processes a FW message, such as link state change messages.
4065 */
4066int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4067{
4068 u8 opcode = *(const u8 *)rpl;
4069
4070 if (opcode == FW_PORT_CMD) { /* link/module state change message */
4071 int speed = 0, fc = 0;
4072 const struct fw_port_cmd *p = (void *)rpl;
2b5fb1f2 4073 int chan = FW_PORT_CMD_PORTID_G(ntohl(p->op_to_portid));
56d36be4
DM
4074 int port = adap->chan_map[chan];
4075 struct port_info *pi = adap2pinfo(adap, port);
4076 struct link_config *lc = &pi->link_cfg;
4077 u32 stat = ntohl(p->u.info.lstatus_to_modtype);
2b5fb1f2
HS
4078 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
4079 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
56d36be4 4080
2b5fb1f2 4081 if (stat & FW_PORT_CMD_RXPAUSE_F)
56d36be4 4082 fc |= PAUSE_RX;
2b5fb1f2 4083 if (stat & FW_PORT_CMD_TXPAUSE_F)
56d36be4 4084 fc |= PAUSE_TX;
2b5fb1f2 4085 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
e8b39015 4086 speed = 100;
2b5fb1f2 4087 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
e8b39015 4088 speed = 1000;
2b5fb1f2 4089 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
e8b39015 4090 speed = 10000;
2b5fb1f2 4091 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
e8b39015 4092 speed = 40000;
56d36be4
DM
4093
4094 if (link_ok != lc->link_ok || speed != lc->speed ||
4095 fc != lc->fc) { /* something changed */
4096 lc->link_ok = link_ok;
4097 lc->speed = speed;
4098 lc->fc = fc;
444018a7 4099 lc->supported = be16_to_cpu(p->u.info.pcap);
56d36be4
DM
4100 t4_os_link_changed(adap, port, link_ok);
4101 }
4102 if (mod != pi->mod_type) {
4103 pi->mod_type = mod;
4104 t4_os_portmod_changed(adap, port);
4105 }
4106 }
4107 return 0;
4108}
4109
1dd06ae8 4110static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
56d36be4
DM
4111{
4112 u16 val;
56d36be4 4113
e5c8ae5f
JL
4114 if (pci_is_pcie(adapter->pdev)) {
4115 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
56d36be4
DM
4116 p->speed = val & PCI_EXP_LNKSTA_CLS;
4117 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
4118 }
4119}
4120
4121/**
4122 * init_link_config - initialize a link's SW state
4123 * @lc: structure holding the link state
4124 * @caps: link capabilities
4125 *
4126 * Initializes the SW state maintained for each link, including the link's
4127 * capabilities and default speed/flow-control/autonegotiation settings.
4128 */
1dd06ae8 4129static void init_link_config(struct link_config *lc, unsigned int caps)
56d36be4
DM
4130{
4131 lc->supported = caps;
4132 lc->requested_speed = 0;
4133 lc->speed = 0;
4134 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
4135 if (lc->supported & FW_PORT_CAP_ANEG) {
4136 lc->advertising = lc->supported & ADVERT_MASK;
4137 lc->autoneg = AUTONEG_ENABLE;
4138 lc->requested_fc |= PAUSE_AUTONEG;
4139 } else {
4140 lc->advertising = 0;
4141 lc->autoneg = AUTONEG_DISABLE;
4142 }
4143}
4144
8203b509
HS
4145#define CIM_PF_NOACCESS 0xeeeeeeee
4146
4147int t4_wait_dev_ready(void __iomem *regs)
56d36be4 4148{
8203b509
HS
4149 u32 whoami;
4150
0d804338 4151 whoami = readl(regs + PL_WHOAMI_A);
8203b509 4152 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
56d36be4 4153 return 0;
8203b509 4154
56d36be4 4155 msleep(500);
0d804338 4156 whoami = readl(regs + PL_WHOAMI_A);
8203b509 4157 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
56d36be4
DM
4158}
4159
fe2ee139
HS
4160struct flash_desc {
4161 u32 vendor_and_model_id;
4162 u32 size_mb;
4163};
4164
91744948 4165static int get_flash_params(struct adapter *adap)
900a6596 4166{
fe2ee139
HS
4167 /* Table for non-Numonix supported flash parts. Numonix parts are left
4168 * to the preexisting code. All flash parts have 64KB sectors.
4169 */
4170 static struct flash_desc supported_flash[] = {
4171 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
4172 };
4173
900a6596
DM
4174 int ret;
4175 u32 info;
4176
4177 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
4178 if (!ret)
4179 ret = sf1_read(adap, 3, 0, 1, &info);
0d804338 4180 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
900a6596
DM
4181 if (ret)
4182 return ret;
4183
fe2ee139
HS
4184 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
4185 if (supported_flash[ret].vendor_and_model_id == info) {
4186 adap->params.sf_size = supported_flash[ret].size_mb;
4187 adap->params.sf_nsec =
4188 adap->params.sf_size / SF_SEC_SIZE;
4189 return 0;
4190 }
4191
900a6596
DM
4192 if ((info & 0xff) != 0x20) /* not a Numonix flash */
4193 return -EINVAL;
4194 info >>= 16; /* log2 of size */
4195 if (info >= 0x14 && info < 0x18)
4196 adap->params.sf_nsec = 1 << (info - 16);
4197 else if (info == 0x18)
4198 adap->params.sf_nsec = 64;
4199 else
4200 return -EINVAL;
4201 adap->params.sf_size = 1 << info;
4202 adap->params.sf_fw_start =
89c3a86c 4203 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
c290607e
HS
4204
4205 if (adap->params.sf_size < FLASH_MIN_SIZE)
4206 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
4207 adap->params.sf_size, FLASH_MIN_SIZE);
900a6596
DM
4208 return 0;
4209}
4210
56d36be4
DM
4211/**
4212 * t4_prep_adapter - prepare SW and HW for operation
4213 * @adapter: the adapter
4214 * @reset: if true perform a HW reset
4215 *
4216 * Initialize adapter SW state for the various HW modules, set initial
4217 * values for some adapter tunables, take PHYs out of reset, and
4218 * initialize the MDIO interface.
4219 */
91744948 4220int t4_prep_adapter(struct adapter *adapter)
56d36be4 4221{
0a57a536
SR
4222 int ret, ver;
4223 uint16_t device_id;
d14807dd 4224 u32 pl_rev;
56d36be4 4225
56d36be4 4226 get_pci_mode(adapter, &adapter->params.pci);
0d804338 4227 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
56d36be4 4228
900a6596
DM
4229 ret = get_flash_params(adapter);
4230 if (ret < 0) {
4231 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
4232 return ret;
4233 }
4234
0a57a536
SR
4235 /* Retrieve adapter's device ID
4236 */
4237 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
4238 ver = device_id >> 12;
d14807dd 4239 adapter->params.chip = 0;
0a57a536
SR
4240 switch (ver) {
4241 case CHELSIO_T4:
d14807dd 4242 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
0a57a536
SR
4243 break;
4244 case CHELSIO_T5:
d14807dd 4245 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
0a57a536
SR
4246 break;
4247 default:
4248 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
4249 device_id);
4250 return -EINVAL;
4251 }
4252
f1ff24aa 4253 adapter->params.cim_la_size = CIMLA_SIZE;
56d36be4
DM
4254 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4255
4256 /*
4257 * Default port for debugging in case we can't reach FW.
4258 */
4259 adapter->params.nports = 1;
4260 adapter->params.portvec = 1;
636f9d37 4261 adapter->params.vpd.cclk = 50000;
56d36be4
DM
4262 return 0;
4263}
4264
e85c9a7a 4265/**
dd0bcc0b 4266 * cxgb4_t4_bar2_sge_qregs - return BAR2 SGE Queue register information
e85c9a7a
HS
4267 * @adapter: the adapter
4268 * @qid: the Queue ID
4269 * @qtype: the Ingress or Egress type for @qid
4270 * @pbar2_qoffset: BAR2 Queue Offset
4271 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4272 *
4273 * Returns the BAR2 SGE Queue Registers information associated with the
4274 * indicated Absolute Queue ID. These are passed back in return value
4275 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4276 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4277 *
4278 * This may return an error which indicates that BAR2 SGE Queue
4279 * registers aren't available. If an error is not returned, then the
4280 * following values are returned:
4281 *
4282 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4283 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4284 *
4285 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4286 * require the "Inferred Queue ID" ability may be used. E.g. the
4287 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4288 * then these "Inferred Queue ID" register may not be used.
4289 */
dd0bcc0b 4290int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS
4291 unsigned int qid,
4292 enum t4_bar2_qtype qtype,
4293 u64 *pbar2_qoffset,
4294 unsigned int *pbar2_qid)
4295{
4296 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4297 u64 bar2_page_offset, bar2_qoffset;
4298 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4299
4300 /* T4 doesn't support BAR2 SGE Queue registers.
4301 */
4302 if (is_t4(adapter->params.chip))
4303 return -EINVAL;
4304
4305 /* Get our SGE Page Size parameters.
4306 */
4307 page_shift = adapter->params.sge.hps + 10;
4308 page_size = 1 << page_shift;
4309
4310 /* Get the right Queues per Page parameters for our Queue.
4311 */
4312 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
4313 ? adapter->params.sge.eq_qpp
4314 : adapter->params.sge.iq_qpp);
4315 qpp_mask = (1 << qpp_shift) - 1;
4316
4317 /* Calculate the basics of the BAR2 SGE Queue register area:
4318 * o The BAR2 page the Queue registers will be in.
4319 * o The BAR2 Queue ID.
4320 * o The BAR2 Queue ID Offset into the BAR2 page.
4321 */
4322 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4323 bar2_qid = qid & qpp_mask;
4324 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4325
4326 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
4327 * hardware will infer the Absolute Queue ID simply from the writes to
4328 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4329 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
4330 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4331 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4332 * from the BAR2 Page and BAR2 Queue ID.
4333 *
4334 * One important censequence of this is that some BAR2 SGE registers
4335 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4336 * there. But other registers synthesize the SGE Queue ID purely
4337 * from the writes to the registers -- the Write Combined Doorbell
4338 * Buffer is a good example. These BAR2 SGE Registers are only
4339 * available for those BAR2 SGE Register areas where the SGE Absolute
4340 * Queue ID can be inferred from simple writes.
4341 */
4342 bar2_qoffset = bar2_page_offset;
4343 bar2_qinferred = (bar2_qid_offset < page_size);
4344 if (bar2_qinferred) {
4345 bar2_qoffset += bar2_qid_offset;
4346 bar2_qid = 0;
4347 }
4348
4349 *pbar2_qoffset = bar2_qoffset;
4350 *pbar2_qid = bar2_qid;
4351 return 0;
4352}
4353
4354/**
4355 * t4_init_sge_params - initialize adap->params.sge
4356 * @adapter: the adapter
4357 *
4358 * Initialize various fields of the adapter's SGE Parameters structure.
4359 */
4360int t4_init_sge_params(struct adapter *adapter)
4361{
4362 struct sge_params *sge_params = &adapter->params.sge;
4363 u32 hps, qpp;
4364 unsigned int s_hps, s_qpp;
4365
4366 /* Extract the SGE Page Size for our PF.
4367 */
f612b815 4368 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
e85c9a7a
HS
4369 s_hps = (HOSTPAGESIZEPF0_S +
4370 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->fn);
4371 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
4372
4373 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
4374 */
4375 s_qpp = (QUEUESPERPAGEPF0_S +
4376 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->fn);
f612b815
HS
4377 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
4378 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
f061de42 4379 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
f612b815 4380 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
e85c9a7a
HS
4381
4382 return 0;
4383}
4384
dcf7b6f5
KS
4385/**
4386 * t4_init_tp_params - initialize adap->params.tp
4387 * @adap: the adapter
4388 *
4389 * Initialize various fields of the adapter's TP Parameters structure.
4390 */
4391int t4_init_tp_params(struct adapter *adap)
4392{
4393 int chan;
4394 u32 v;
4395
837e4a42
HS
4396 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
4397 adap->params.tp.tre = TIMERRESOLUTION_G(v);
4398 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
dcf7b6f5
KS
4399
4400 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4401 for (chan = 0; chan < NCHAN; chan++)
4402 adap->params.tp.tx_modq[chan] = chan;
4403
4404 /* Cache the adapter's Compressed Filter Mode and global Incress
4405 * Configuration.
4406 */
837e4a42 4407 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
dcf7b6f5 4408 &adap->params.tp.vlan_pri_map, 1,
837e4a42
HS
4409 TP_VLAN_PRI_MAP_A);
4410 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
dcf7b6f5 4411 &adap->params.tp.ingress_config, 1,
837e4a42 4412 TP_INGRESS_CONFIG_A);
dcf7b6f5
KS
4413
4414 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4415 * shift positions of several elements of the Compressed Filter Tuple
4416 * for this adapter which we need frequently ...
4417 */
0d804338
HS
4418 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
4419 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
4420 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
dcf7b6f5 4421 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
0d804338 4422 PROTOCOL_F);
dcf7b6f5
KS
4423
4424 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4425 * represents the presense of an Outer VLAN instead of a VNIC ID.
4426 */
0d804338 4427 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
dcf7b6f5
KS
4428 adap->params.tp.vnic_shift = -1;
4429
4430 return 0;
4431}
4432
4433/**
4434 * t4_filter_field_shift - calculate filter field shift
4435 * @adap: the adapter
4436 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4437 *
4438 * Return the shift position of a filter field within the Compressed
4439 * Filter Tuple. The filter field is specified via its selection bit
4440 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4441 */
4442int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
4443{
4444 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4445 unsigned int sel;
4446 int field_shift;
4447
4448 if ((filter_mode & filter_sel) == 0)
4449 return -1;
4450
4451 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4452 switch (filter_mode & sel) {
0d804338
HS
4453 case FCOE_F:
4454 field_shift += FT_FCOE_W;
dcf7b6f5 4455 break;
0d804338
HS
4456 case PORT_F:
4457 field_shift += FT_PORT_W;
dcf7b6f5 4458 break;
0d804338
HS
4459 case VNIC_ID_F:
4460 field_shift += FT_VNIC_ID_W;
dcf7b6f5 4461 break;
0d804338
HS
4462 case VLAN_F:
4463 field_shift += FT_VLAN_W;
dcf7b6f5 4464 break;
0d804338
HS
4465 case TOS_F:
4466 field_shift += FT_TOS_W;
dcf7b6f5 4467 break;
0d804338
HS
4468 case PROTOCOL_F:
4469 field_shift += FT_PROTOCOL_W;
dcf7b6f5 4470 break;
0d804338
HS
4471 case ETHERTYPE_F:
4472 field_shift += FT_ETHERTYPE_W;
dcf7b6f5 4473 break;
0d804338
HS
4474 case MACMATCH_F:
4475 field_shift += FT_MACMATCH_W;
dcf7b6f5 4476 break;
0d804338
HS
4477 case MPSHITTYPE_F:
4478 field_shift += FT_MPSHITTYPE_W;
dcf7b6f5 4479 break;
0d804338
HS
4480 case FRAGMENTATION_F:
4481 field_shift += FT_FRAGMENTATION_W;
dcf7b6f5
KS
4482 break;
4483 }
4484 }
4485 return field_shift;
4486}
4487
91744948 4488int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
56d36be4
DM
4489{
4490 u8 addr[6];
4491 int ret, i, j = 0;
4492 struct fw_port_cmd c;
f796564a 4493 struct fw_rss_vi_config_cmd rvc;
56d36be4
DM
4494
4495 memset(&c, 0, sizeof(c));
f796564a 4496 memset(&rvc, 0, sizeof(rvc));
56d36be4
DM
4497
4498 for_each_port(adap, i) {
4499 unsigned int rss_size;
4500 struct port_info *p = adap2pinfo(adap, i);
4501
4502 while ((adap->params.portvec & (1 << j)) == 0)
4503 j++;
4504
e2ac9628
HS
4505 c.op_to_portid = htonl(FW_CMD_OP_V(FW_PORT_CMD) |
4506 FW_CMD_REQUEST_F | FW_CMD_READ_F |
2b5fb1f2 4507 FW_PORT_CMD_PORTID_V(j));
56d36be4 4508 c.action_to_len16 = htonl(
2b5fb1f2 4509 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
56d36be4
DM
4510 FW_LEN16(c));
4511 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4512 if (ret)
4513 return ret;
4514
4515 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4516 if (ret < 0)
4517 return ret;
4518
4519 p->viid = ret;
4520 p->tx_chan = j;
4521 p->lport = j;
4522 p->rss_size = rss_size;
4523 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
40c9f8ab 4524 adap->port[i]->dev_port = j;
56d36be4
DM
4525
4526 ret = ntohl(c.u.info.lstatus_to_modtype);
2b5fb1f2
HS
4527 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
4528 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
4529 p->port_type = FW_PORT_CMD_PTYPE_G(ret);
a0881cab 4530 p->mod_type = FW_PORT_MOD_TYPE_NA;
56d36be4 4531
e2ac9628
HS
4532 rvc.op_to_viid = htonl(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4533 FW_CMD_REQUEST_F | FW_CMD_READ_F |
f796564a
DM
4534 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4535 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4536 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4537 if (ret)
4538 return ret;
4539 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4540
56d36be4
DM
4541 init_link_config(&p->link_cfg, ntohs(c.u.info.pcap));
4542 j++;
4543 }
4544 return 0;
4545}
f1ff24aa 4546
74b3092c
HS
4547/**
4548 * t4_read_cimq_cfg - read CIM queue configuration
4549 * @adap: the adapter
4550 * @base: holds the queue base addresses in bytes
4551 * @size: holds the queue sizes in bytes
4552 * @thres: holds the queue full thresholds in bytes
4553 *
4554 * Returns the current configuration of the CIM queues, starting with
4555 * the IBQs, then the OBQs.
4556 */
4557void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
4558{
4559 unsigned int i, v;
4560 int cim_num_obq = is_t4(adap->params.chip) ?
4561 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
4562
4563 for (i = 0; i < CIM_NUM_IBQ; i++) {
4564 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
4565 QUENUMSELECT_V(i));
4566 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
4567 /* value is in 256-byte units */
4568 *base++ = CIMQBASE_G(v) * 256;
4569 *size++ = CIMQSIZE_G(v) * 256;
4570 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
4571 }
4572 for (i = 0; i < cim_num_obq; i++) {
4573 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
4574 QUENUMSELECT_V(i));
4575 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
4576 /* value is in 256-byte units */
4577 *base++ = CIMQBASE_G(v) * 256;
4578 *size++ = CIMQSIZE_G(v) * 256;
4579 }
4580}
4581
e5f0e43b
HS
4582/**
4583 * t4_read_cim_ibq - read the contents of a CIM inbound queue
4584 * @adap: the adapter
4585 * @qid: the queue index
4586 * @data: where to store the queue contents
4587 * @n: capacity of @data in 32-bit words
4588 *
4589 * Reads the contents of the selected CIM queue starting at address 0 up
4590 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
4591 * error and the number of 32-bit words actually read on success.
4592 */
4593int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
4594{
4595 int i, err, attempts;
4596 unsigned int addr;
4597 const unsigned int nwords = CIM_IBQ_SIZE * 4;
4598
4599 if (qid > 5 || (n & 3))
4600 return -EINVAL;
4601
4602 addr = qid * nwords;
4603 if (n > nwords)
4604 n = nwords;
4605
4606 /* It might take 3-10ms before the IBQ debug read access is allowed.
4607 * Wait for 1 Sec with a delay of 1 usec.
4608 */
4609 attempts = 1000000;
4610
4611 for (i = 0; i < n; i++, addr++) {
4612 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
4613 IBQDBGEN_F);
4614 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
4615 attempts, 1);
4616 if (err)
4617 return err;
4618 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
4619 }
4620 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
c778af7d
HS
4621 return i;
4622}
4623
4624/**
4625 * t4_read_cim_obq - read the contents of a CIM outbound queue
4626 * @adap: the adapter
4627 * @qid: the queue index
4628 * @data: where to store the queue contents
4629 * @n: capacity of @data in 32-bit words
4630 *
4631 * Reads the contents of the selected CIM queue starting at address 0 up
4632 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
4633 * error and the number of 32-bit words actually read on success.
4634 */
4635int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
4636{
4637 int i, err;
4638 unsigned int addr, v, nwords;
4639 int cim_num_obq = is_t4(adap->params.chip) ?
4640 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
4641
4642 if ((qid > (cim_num_obq - 1)) || (n & 3))
4643 return -EINVAL;
4644
4645 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
4646 QUENUMSELECT_V(qid));
4647 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
4648
4649 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
4650 nwords = CIMQSIZE_G(v) * 64; /* same */
4651 if (n > nwords)
4652 n = nwords;
4653
4654 for (i = 0; i < n; i++, addr++) {
4655 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
4656 OBQDBGEN_F);
4657 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
4658 2, 1);
4659 if (err)
4660 return err;
4661 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
4662 }
4663 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
e5f0e43b
HS
4664 return i;
4665}
4666
f1ff24aa
HS
4667/**
4668 * t4_cim_read - read a block from CIM internal address space
4669 * @adap: the adapter
4670 * @addr: the start address within the CIM address space
4671 * @n: number of words to read
4672 * @valp: where to store the result
4673 *
4674 * Reads a block of 4-byte words from the CIM intenal address space.
4675 */
4676int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
4677 unsigned int *valp)
4678{
4679 int ret = 0;
4680
4681 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
4682 return -EBUSY;
4683
4684 for ( ; !ret && n--; addr += 4) {
4685 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
4686 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
4687 0, 5, 2);
4688 if (!ret)
4689 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
4690 }
4691 return ret;
4692}
4693
4694/**
4695 * t4_cim_write - write a block into CIM internal address space
4696 * @adap: the adapter
4697 * @addr: the start address within the CIM address space
4698 * @n: number of words to write
4699 * @valp: set of values to write
4700 *
4701 * Writes a block of 4-byte words into the CIM intenal address space.
4702 */
4703int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
4704 const unsigned int *valp)
4705{
4706 int ret = 0;
4707
4708 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
4709 return -EBUSY;
4710
4711 for ( ; !ret && n--; addr += 4) {
4712 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
4713 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
4714 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
4715 0, 5, 2);
4716 }
4717 return ret;
4718}
4719
4720static int t4_cim_write1(struct adapter *adap, unsigned int addr,
4721 unsigned int val)
4722{
4723 return t4_cim_write(adap, addr, 1, &val);
4724}
4725
4726/**
4727 * t4_cim_read_la - read CIM LA capture buffer
4728 * @adap: the adapter
4729 * @la_buf: where to store the LA data
4730 * @wrptr: the HW write pointer within the capture buffer
4731 *
4732 * Reads the contents of the CIM LA buffer with the most recent entry at
4733 * the end of the returned data and with the entry at @wrptr first.
4734 * We try to leave the LA in the running state we find it in.
4735 */
4736int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
4737{
4738 int i, ret;
4739 unsigned int cfg, val, idx;
4740
4741 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
4742 if (ret)
4743 return ret;
4744
4745 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
4746 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
4747 if (ret)
4748 return ret;
4749 }
4750
4751 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
4752 if (ret)
4753 goto restart;
4754
4755 idx = UPDBGLAWRPTR_G(val);
4756 if (wrptr)
4757 *wrptr = idx;
4758
4759 for (i = 0; i < adap->params.cim_la_size; i++) {
4760 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
4761 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
4762 if (ret)
4763 break;
4764 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
4765 if (ret)
4766 break;
4767 if (val & UPDBGLARDEN_F) {
4768 ret = -ETIMEDOUT;
4769 break;
4770 }
4771 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
4772 if (ret)
4773 break;
4774 idx = (idx + 1) & UPDBGLARDPTR_M;
4775 }
4776restart:
4777 if (cfg & UPDBGLAEN_F) {
4778 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
4779 cfg & ~UPDBGLARDEN_F);
4780 if (!ret)
4781 ret = r;
4782 }
4783 return ret;
4784}