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Commit | Line | Data |
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0bb29b25 | 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ |
6e2387e8 IR |
2 | /* Copyright 2014-2016 Freescale Semiconductor Inc. |
3 | * Copyright 2016 NXP | |
6e2387e8 IR |
4 | */ |
5 | ||
6 | #ifndef __DPAA2_ETH_H | |
7 | #define __DPAA2_ETH_H | |
8 | ||
9 | #include <linux/netdevice.h> | |
10 | #include <linux/if_vlan.h> | |
9c692d5a | 11 | #include <linux/fsl/mc.h> |
6e2387e8 | 12 | |
c89105c9 RP |
13 | #include <soc/fsl/dpaa2-io.h> |
14 | #include <soc/fsl/dpaa2-fd.h> | |
6e2387e8 IR |
15 | #include "dpni.h" |
16 | #include "dpni-cmd.h" | |
17 | ||
5636187b | 18 | #include "dpaa2-eth-trace.h" |
091a19ea | 19 | #include "dpaa2-eth-debugfs.h" |
71947923 | 20 | #include "dpaa2-mac.h" |
5636187b | 21 | |
8a4fd877 BP |
22 | #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0) |
23 | ||
6e2387e8 IR |
24 | #define DPAA2_ETH_STORE_SIZE 16 |
25 | ||
26 | /* Maximum number of scatter-gather entries in an ingress frame, | |
27 | * considering the maximum receive frame size is 64K | |
28 | */ | |
29 | #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE) | |
30 | ||
31 | /* Maximum acceptable MTU value. It is in direct relation with the hardware | |
32 | * enforced Max Frame Length (currently 10k). | |
33 | */ | |
34 | #define DPAA2_ETH_MFL (10 * 1024) | |
35 | #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN) | |
36 | /* Convert L3 MTU to L2 MFL */ | |
37 | #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN) | |
38 | ||
39 | /* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo | |
40 | * frames in the Rx queues (length of the current frame is not | |
41 | * taken into account when making the taildrop decision) | |
42 | */ | |
43 | #define DPAA2_ETH_TAILDROP_THRESH (64 * 1024) | |
44 | ||
68049a5f ICR |
45 | /* Maximum number of Tx confirmation frames to be processed |
46 | * in a single NAPI call | |
47 | */ | |
48 | #define DPAA2_ETH_TXCONF_PER_NAPI 256 | |
49 | ||
6e2387e8 IR |
50 | /* Buffer quota per queue. Must be large enough such that for minimum sized |
51 | * frames taildrop kicks in before the bpool gets depleted, so we compute | |
52 | * how many 64B frames fit inside the taildrop threshold and add a margin | |
53 | * to accommodate the buffer refill delay. | |
54 | */ | |
55 | #define DPAA2_ETH_MAX_FRAMES_PER_QUEUE (DPAA2_ETH_TAILDROP_THRESH / 64) | |
56 | #define DPAA2_ETH_NUM_BUFS (DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256) | |
20fb0572 ICR |
57 | #define DPAA2_ETH_REFILL_THRESH \ |
58 | (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD) | |
6e2387e8 IR |
59 | |
60 | /* Maximum number of buffers that can be acquired/released through a single | |
61 | * QBMan command | |
62 | */ | |
63 | #define DPAA2_ETH_BUFS_PER_CMD 7 | |
64 | ||
4b2d9fe8 | 65 | /* Hardware requires alignment for ingress/egress buffer addresses */ |
6e2387e8 | 66 | #define DPAA2_ETH_TX_BUF_ALIGN 64 |
8a4fd877 | 67 | |
27c87486 ICR |
68 | #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE |
69 | #define DPAA2_ETH_RX_BUF_TAILROOM \ | |
70 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) | |
71 | #define DPAA2_ETH_RX_BUF_SIZE \ | |
72 | (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM) | |
4b2d9fe8 | 73 | |
859f998e | 74 | /* Hardware annotation area in RX/TX buffers */ |
4b2d9fe8 | 75 | #define DPAA2_ETH_RX_HWA_SIZE 64 |
859f998e IR |
76 | #define DPAA2_ETH_TX_HWA_SIZE 128 |
77 | ||
78 | /* PTP nominal frequency 1GHz */ | |
79 | #define DPAA2_PTP_CLK_PERIOD_NS 1 | |
6e2387e8 | 80 | |
8a4fd877 BP |
81 | /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned |
82 | * to 256B. For newer revisions, the requirement is only for 64B alignment | |
6e2387e8 | 83 | */ |
8a4fd877 BP |
84 | #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256 |
85 | #define DPAA2_ETH_RX_BUF_ALIGN 64 | |
6e2387e8 IR |
86 | |
87 | /* We are accommodating a skb backpointer and some S/G info | |
88 | * in the frame's software annotation. The hardware | |
89 | * options are either 0 or 64, so we choose the latter. | |
90 | */ | |
91 | #define DPAA2_ETH_SWA_SIZE 64 | |
92 | ||
e3fdf6ba IR |
93 | /* We store different information in the software annotation area of a Tx frame |
94 | * based on what type of frame it is | |
95 | */ | |
96 | enum dpaa2_eth_swa_type { | |
97 | DPAA2_ETH_SWA_SINGLE, | |
98 | DPAA2_ETH_SWA_SG, | |
d678be1d | 99 | DPAA2_ETH_SWA_XDP, |
e3fdf6ba IR |
100 | }; |
101 | ||
6e2387e8 IR |
102 | /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */ |
103 | struct dpaa2_eth_swa { | |
e3fdf6ba IR |
104 | enum dpaa2_eth_swa_type type; |
105 | union { | |
106 | struct { | |
107 | struct sk_buff *skb; | |
108 | } single; | |
109 | struct { | |
110 | struct sk_buff *skb; | |
111 | struct scatterlist *scl; | |
112 | int num_sg; | |
113 | int sgt_size; | |
114 | } sg; | |
d678be1d IR |
115 | struct { |
116 | int dma_size; | |
117 | struct xdp_frame *xdpf; | |
118 | } xdp; | |
e3fdf6ba | 119 | }; |
6e2387e8 IR |
120 | }; |
121 | ||
122 | /* Annotation valid bits in FD FRC */ | |
123 | #define DPAA2_FD_FRC_FASV 0x8000 | |
124 | #define DPAA2_FD_FRC_FAEADV 0x4000 | |
125 | #define DPAA2_FD_FRC_FAPRV 0x2000 | |
126 | #define DPAA2_FD_FRC_FAIADV 0x1000 | |
127 | #define DPAA2_FD_FRC_FASWOV 0x0800 | |
128 | #define DPAA2_FD_FRC_FAICFDV 0x0400 | |
129 | ||
39163c0c | 130 | /* Error bits in FD CTRL */ |
58ad0d02 HG |
131 | #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR) |
132 | #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \ | |
133 | FD_CTRL_SBE | \ | |
134 | FD_CTRL_FSE | \ | |
135 | FD_CTRL_FAERR) | |
39163c0c | 136 | |
6e2387e8 | 137 | /* Annotation bits in FD CTRL */ |
859f998e | 138 | #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */ |
6e2387e8 IR |
139 | |
140 | /* Frame annotation status */ | |
141 | struct dpaa2_fas { | |
142 | u8 reserved; | |
143 | u8 ppid; | |
144 | __le16 ifpid; | |
145 | __le32 status; | |
2a6c7f34 | 146 | }; |
6e2387e8 IR |
147 | |
148 | /* Frame annotation status word is located in the first 8 bytes | |
149 | * of the buffer's hardware annoatation area | |
150 | */ | |
151 | #define DPAA2_FAS_OFFSET 0 | |
152 | #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas)) | |
153 | ||
859f998e IR |
154 | /* Timestamp is located in the next 8 bytes of the buffer's |
155 | * hardware annotation area | |
156 | */ | |
157 | #define DPAA2_TS_OFFSET 0x8 | |
158 | ||
159 | /* Frame annotation egress action descriptor */ | |
160 | #define DPAA2_FAEAD_OFFSET 0x58 | |
161 | ||
162 | struct dpaa2_faead { | |
163 | __le32 conf_fqid; | |
164 | __le32 ctrl; | |
165 | }; | |
166 | ||
167 | #define DPAA2_FAEAD_A2V 0x20000000 | |
99e43521 | 168 | #define DPAA2_FAEAD_A4V 0x08000000 |
859f998e | 169 | #define DPAA2_FAEAD_UPDV 0x00001000 |
99e43521 | 170 | #define DPAA2_FAEAD_EBDDV 0x00002000 |
859f998e IR |
171 | #define DPAA2_FAEAD_UPD 0x00000010 |
172 | ||
d695e764 | 173 | /* Accessors for the hardware annotation fields that we use */ |
54ce8917 IR |
174 | static inline void *dpaa2_get_hwa(void *buf_addr, bool swa) |
175 | { | |
176 | return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0); | |
177 | } | |
178 | ||
179 | static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa) | |
180 | { | |
181 | return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET; | |
182 | } | |
d695e764 | 183 | |
859f998e IR |
184 | static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa) |
185 | { | |
186 | return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET; | |
187 | } | |
188 | ||
189 | static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa) | |
190 | { | |
191 | return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET; | |
192 | } | |
193 | ||
6e2387e8 IR |
194 | /* Error and status bits in the frame annotation status word */ |
195 | /* Debug frame, otherwise supposed to be discarded */ | |
196 | #define DPAA2_FAS_DISC 0x80000000 | |
197 | /* MACSEC frame */ | |
198 | #define DPAA2_FAS_MS 0x40000000 | |
199 | #define DPAA2_FAS_PTP 0x08000000 | |
200 | /* Ethernet multicast frame */ | |
201 | #define DPAA2_FAS_MC 0x04000000 | |
202 | /* Ethernet broadcast frame */ | |
203 | #define DPAA2_FAS_BC 0x02000000 | |
204 | #define DPAA2_FAS_KSE 0x00040000 | |
205 | #define DPAA2_FAS_EOFHE 0x00020000 | |
206 | #define DPAA2_FAS_MNLE 0x00010000 | |
207 | #define DPAA2_FAS_TIDE 0x00008000 | |
208 | #define DPAA2_FAS_PIEE 0x00004000 | |
209 | /* Frame length error */ | |
210 | #define DPAA2_FAS_FLE 0x00002000 | |
211 | /* Frame physical error */ | |
212 | #define DPAA2_FAS_FPE 0x00001000 | |
213 | #define DPAA2_FAS_PTE 0x00000080 | |
214 | #define DPAA2_FAS_ISP 0x00000040 | |
215 | #define DPAA2_FAS_PHE 0x00000020 | |
216 | #define DPAA2_FAS_BLE 0x00000010 | |
217 | /* L3 csum validation performed */ | |
218 | #define DPAA2_FAS_L3CV 0x00000008 | |
219 | /* L3 csum error */ | |
220 | #define DPAA2_FAS_L3CE 0x00000004 | |
221 | /* L4 csum validation performed */ | |
222 | #define DPAA2_FAS_L4CV 0x00000002 | |
223 | /* L4 csum error */ | |
224 | #define DPAA2_FAS_L4CE 0x00000001 | |
225 | /* Possible errors on the ingress path */ | |
39163c0c | 226 | #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \ |
6e2387e8 IR |
227 | DPAA2_FAS_EOFHE | \ |
228 | DPAA2_FAS_MNLE | \ | |
229 | DPAA2_FAS_TIDE | \ | |
230 | DPAA2_FAS_PIEE | \ | |
231 | DPAA2_FAS_FLE | \ | |
232 | DPAA2_FAS_FPE | \ | |
233 | DPAA2_FAS_PTE | \ | |
234 | DPAA2_FAS_ISP | \ | |
235 | DPAA2_FAS_PHE | \ | |
236 | DPAA2_FAS_BLE | \ | |
237 | DPAA2_FAS_L3CE | \ | |
238 | DPAA2_FAS_L4CE) | |
6e2387e8 IR |
239 | |
240 | /* Time in milliseconds between link state updates */ | |
241 | #define DPAA2_ETH_LINK_STATE_REFRESH 1000 | |
242 | ||
243 | /* Number of times to retry a frame enqueue before giving up. | |
244 | * Value determined empirically, in order to minimize the number | |
245 | * of frames dropped on Tx | |
246 | */ | |
247 | #define DPAA2_ETH_ENQUEUE_RETRIES 10 | |
248 | ||
ef17bd7c IR |
249 | /* Number of times to retry DPIO portal operations while waiting |
250 | * for portal to finish executing current command and become | |
251 | * available. We want to avoid being stuck in a while loop in case | |
252 | * hardware becomes unresponsive, but not give up too easily if | |
253 | * the portal really is busy for valid reasons | |
254 | */ | |
255 | #define DPAA2_ETH_SWP_BUSY_RETRIES 1000 | |
256 | ||
85047abd IR |
257 | /* Driver statistics, other than those in struct rtnl_link_stats64. |
258 | * These are usually collected per-CPU and aggregated by ethtool. | |
259 | */ | |
260 | struct dpaa2_eth_drv_stats { | |
261 | __u64 tx_conf_frames; | |
262 | __u64 tx_conf_bytes; | |
263 | __u64 tx_sg_frames; | |
264 | __u64 tx_sg_bytes; | |
6662b5e4 | 265 | __u64 tx_reallocs; |
85047abd IR |
266 | __u64 rx_sg_frames; |
267 | __u64 rx_sg_bytes; | |
268 | /* Enqueues retried due to portal busy */ | |
269 | __u64 tx_portal_busy; | |
270 | }; | |
271 | ||
272 | /* Per-FQ statistics */ | |
273 | struct dpaa2_eth_fq_stats { | |
274 | /* Number of frames received on this queue */ | |
275 | __u64 frames; | |
276 | }; | |
277 | ||
278 | /* Per-channel statistics */ | |
279 | struct dpaa2_eth_ch_stats { | |
280 | /* Volatile dequeues retried due to portal busy */ | |
281 | __u64 dequeue_portal_busy; | |
85047abd IR |
282 | /* Pull errors */ |
283 | __u64 pull_err; | |
0ff8f0aa ICR |
284 | /* Number of CDANs; useful to estimate avg NAPI len */ |
285 | __u64 cdan; | |
a4a7b762 ICR |
286 | /* XDP counters */ |
287 | __u64 xdp_drop; | |
288 | __u64 xdp_tx; | |
289 | __u64 xdp_tx_err; | |
d678be1d | 290 | __u64 xdp_redirect; |
85047abd IR |
291 | }; |
292 | ||
6e2387e8 | 293 | /* Maximum number of queues associated with a DPNI */ |
15c87f6b | 294 | #define DPAA2_ETH_MAX_TCS 8 |
6e2387e8 | 295 | #define DPAA2_ETH_MAX_RX_QUEUES 16 |
009749d7 | 296 | #define DPAA2_ETH_MAX_TX_QUEUES 16 |
6e2387e8 IR |
297 | #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \ |
298 | DPAA2_ETH_MAX_TX_QUEUES) | |
ab1e6de2 IR |
299 | #define DPAA2_ETH_MAX_NETDEV_QUEUES \ |
300 | (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS) | |
6e2387e8 | 301 | |
009749d7 | 302 | #define DPAA2_ETH_MAX_DPCONS 16 |
6e2387e8 IR |
303 | |
304 | enum dpaa2_eth_fq_type { | |
305 | DPAA2_RX_FQ = 0, | |
306 | DPAA2_TX_CONF_FQ, | |
307 | }; | |
308 | ||
309 | struct dpaa2_eth_priv; | |
310 | ||
311 | struct dpaa2_eth_fq { | |
312 | u32 fqid; | |
313 | u32 tx_qdbin; | |
15c87f6b | 314 | u32 tx_fqid[DPAA2_ETH_MAX_TCS]; |
6e2387e8 | 315 | u16 flowid; |
15c87f6b | 316 | u8 tc; |
6e2387e8 | 317 | int target_cpu; |
569dac6a ICR |
318 | u32 dq_frames; |
319 | u32 dq_bytes; | |
6e2387e8 IR |
320 | struct dpaa2_eth_channel *channel; |
321 | enum dpaa2_eth_fq_type type; | |
322 | ||
2ec34a43 IR |
323 | void (*consume)(struct dpaa2_eth_priv *priv, |
324 | struct dpaa2_eth_channel *ch, | |
325 | const struct dpaa2_fd *fd, | |
dbcdf728 | 326 | struct dpaa2_eth_fq *fq); |
85047abd | 327 | struct dpaa2_eth_fq_stats stats; |
6e2387e8 IR |
328 | }; |
329 | ||
7e273a8e ICR |
330 | struct dpaa2_eth_ch_xdp { |
331 | struct bpf_prog *prog; | |
5d39dc21 ICR |
332 | u64 drop_bufs[DPAA2_ETH_BUFS_PER_CMD]; |
333 | int drop_cnt; | |
d678be1d | 334 | unsigned int res; |
7e273a8e ICR |
335 | }; |
336 | ||
6e2387e8 IR |
337 | struct dpaa2_eth_channel { |
338 | struct dpaa2_io_notification_ctx nctx; | |
339 | struct fsl_mc_device *dpcon; | |
340 | int dpcon_id; | |
341 | int ch_id; | |
6e2387e8 | 342 | struct napi_struct napi; |
7ec0596f | 343 | struct dpaa2_io *dpio; |
6e2387e8 IR |
344 | struct dpaa2_io_store *store; |
345 | struct dpaa2_eth_priv *priv; | |
346 | int buf_count; | |
85047abd | 347 | struct dpaa2_eth_ch_stats stats; |
7e273a8e | 348 | struct dpaa2_eth_ch_xdp xdp; |
d678be1d | 349 | struct xdp_rxq_info xdp_rxq; |
0a25d92c | 350 | struct list_head *rx_list; |
6e2387e8 IR |
351 | }; |
352 | ||
f76c483a | 353 | struct dpaa2_eth_dist_fields { |
6e2387e8 IR |
354 | u64 rxnfc_field; |
355 | enum net_prot cls_prot; | |
356 | int cls_field; | |
357 | int size; | |
3a1e6b84 | 358 | u64 id; |
6e2387e8 IR |
359 | }; |
360 | ||
afb90dbb IR |
361 | struct dpaa2_eth_cls_rule { |
362 | struct ethtool_rx_flow_spec fs; | |
363 | u8 in_use; | |
364 | }; | |
365 | ||
6e2387e8 IR |
366 | /* Driver private data */ |
367 | struct dpaa2_eth_priv { | |
368 | struct net_device *net_dev; | |
369 | ||
370 | u8 num_fqs; | |
371 | struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES]; | |
1fa0f68c ICR |
372 | int (*enqueue)(struct dpaa2_eth_priv *priv, |
373 | struct dpaa2_eth_fq *fq, | |
374 | struct dpaa2_fd *fd, u8 prio); | |
6e2387e8 IR |
375 | |
376 | u8 num_channels; | |
377 | struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; | |
378 | ||
6e2387e8 | 379 | struct dpni_attr dpni_attrs; |
311cffa5 IR |
380 | u16 dpni_ver_major; |
381 | u16 dpni_ver_minor; | |
6e2387e8 IR |
382 | u16 tx_data_offset; |
383 | ||
384 | struct fsl_mc_device *dpbp_dev; | |
efa6a7d0 | 385 | u16 rx_buf_size; |
05fa39c6 | 386 | u16 bpid; |
08eb2397 | 387 | struct iommu_domain *iommu_domain; |
6e2387e8 | 388 | |
859f998e IR |
389 | bool tx_tstamp; /* Tx timestamping enabled */ |
390 | bool rx_tstamp; /* Rx timestamping enabled */ | |
391 | ||
6e2387e8 IR |
392 | u16 tx_qdid; |
393 | struct fsl_mc_io *mc_io; | |
394 | /* Cores which have an affine DPIO/DPCON. | |
395 | * This is the cpu set on which Rx and Tx conf frames are processed | |
396 | */ | |
397 | struct cpumask dpio_cpumask; | |
398 | ||
399 | /* Standard statistics */ | |
400 | struct rtnl_link_stats64 __percpu *percpu_stats; | |
85047abd IR |
401 | /* Extra stats, in addition to the ones known by the kernel */ |
402 | struct dpaa2_eth_drv_stats __percpu *percpu_extras; | |
6e2387e8 IR |
403 | |
404 | u16 mc_token; | |
8eb3cef8 | 405 | u8 rx_td_enabled; |
6e2387e8 IR |
406 | |
407 | struct dpni_link_state link_state; | |
408 | bool do_link_poll; | |
409 | struct task_struct *poll_thread; | |
34196740 IR |
410 | |
411 | /* enabled ethtool hashing bits */ | |
412 | u64 rx_hash_fields; | |
2d680237 | 413 | u64 rx_cls_fields; |
afb90dbb | 414 | struct dpaa2_eth_cls_rule *cls_rules; |
4aaaf9b9 | 415 | u8 rx_cls_enabled; |
7e273a8e | 416 | struct bpf_prog *xdp_prog; |
091a19ea IR |
417 | #ifdef CONFIG_DEBUG_FS |
418 | struct dpaa2_debugfs dbg; | |
419 | #endif | |
71947923 IC |
420 | |
421 | struct dpaa2_mac *mac; | |
6e2387e8 IR |
422 | }; |
423 | ||
6e2387e8 IR |
424 | #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \ |
425 | | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \ | |
426 | | RXH_L4_B_2_3) | |
427 | ||
227686b6 IR |
428 | /* default Rx hash options, set during probing */ |
429 | #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \ | |
430 | RXH_L4_B_0_1 | RXH_L4_B_2_3) | |
431 | ||
6e2387e8 IR |
432 | #define dpaa2_eth_hash_enabled(priv) \ |
433 | ((priv)->dpni_attrs.num_queues > 1) | |
434 | ||
435 | /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */ | |
436 | #define DPAA2_CLASSIFIER_DMA_SIZE 256 | |
437 | ||
34196740 | 438 | extern const struct ethtool_ops dpaa2_ethtool_ops; |
8c03fa03 | 439 | extern int dpaa2_phc_index; |
34196740 | 440 | |
311cffa5 IR |
441 | static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv, |
442 | u16 ver_major, u16 ver_minor) | |
443 | { | |
444 | if (priv->dpni_ver_major == ver_major) | |
445 | return priv->dpni_ver_minor - ver_minor; | |
446 | return priv->dpni_ver_major - ver_major; | |
447 | } | |
448 | ||
df85aeb9 IR |
449 | /* Minimum firmware version that supports a more flexible API |
450 | * for configuring the Rx flow hash key | |
451 | */ | |
452 | #define DPNI_RX_DIST_KEY_VER_MAJOR 7 | |
453 | #define DPNI_RX_DIST_KEY_VER_MINOR 5 | |
454 | ||
455 | #define dpaa2_eth_has_legacy_dist(priv) \ | |
456 | (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \ | |
457 | DPNI_RX_DIST_KEY_VER_MINOR) < 0) | |
458 | ||
61f9bf00 ICR |
459 | #define dpaa2_eth_fs_enabled(priv) \ |
460 | (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS)) | |
461 | ||
462 | #define dpaa2_eth_fs_mask_enabled(priv) \ | |
463 | ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING) | |
464 | ||
afb90dbb IR |
465 | #define dpaa2_eth_fs_count(priv) \ |
466 | ((priv)->dpni_attrs.fs_entries) | |
467 | ||
15c87f6b IR |
468 | #define dpaa2_eth_tc_count(priv) \ |
469 | ((priv)->dpni_attrs.num_tcs) | |
470 | ||
186f21be IC |
471 | /* We have exactly one {Rx, Tx conf} queue per channel */ |
472 | #define dpaa2_eth_queue_count(priv) \ | |
473 | ((priv)->num_channels) | |
474 | ||
4aaaf9b9 IR |
475 | enum dpaa2_eth_rx_dist { |
476 | DPAA2_ETH_RX_DIST_HASH, | |
477 | DPAA2_ETH_RX_DIST_CLS | |
478 | }; | |
479 | ||
3a1e6b84 ICR |
480 | /* Unique IDs for the supported Rx classification header fields */ |
481 | #define DPAA2_ETH_DIST_ETHDST BIT(0) | |
482 | #define DPAA2_ETH_DIST_ETHSRC BIT(1) | |
483 | #define DPAA2_ETH_DIST_ETHTYPE BIT(2) | |
484 | #define DPAA2_ETH_DIST_VLAN BIT(3) | |
485 | #define DPAA2_ETH_DIST_IPSRC BIT(4) | |
486 | #define DPAA2_ETH_DIST_IPDST BIT(5) | |
487 | #define DPAA2_ETH_DIST_IPPROTO BIT(6) | |
488 | #define DPAA2_ETH_DIST_L4SRC BIT(7) | |
489 | #define DPAA2_ETH_DIST_L4DST BIT(8) | |
4ca6dee5 | 490 | #define DPAA2_ETH_DIST_ALL (~0ULL) |
3a1e6b84 | 491 | |
8eb3cef8 IR |
492 | #define DPNI_PAUSE_VER_MAJOR 7 |
493 | #define DPNI_PAUSE_VER_MINOR 13 | |
494 | #define dpaa2_eth_has_pause_support(priv) \ | |
495 | (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \ | |
496 | DPNI_PAUSE_VER_MINOR) >= 0) | |
497 | ||
4b2d9fe8 | 498 | static inline |
18c21467 IR |
499 | unsigned int dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv, |
500 | struct sk_buff *skb) | |
4b2d9fe8 | 501 | { |
859f998e IR |
502 | unsigned int headroom = DPAA2_ETH_SWA_SIZE; |
503 | ||
d678be1d IR |
504 | /* If we don't have an skb (e.g. XDP buffer), we only need space for |
505 | * the software annotation area | |
506 | */ | |
507 | if (!skb) | |
508 | return headroom; | |
509 | ||
859f998e IR |
510 | /* For non-linear skbs we have no headroom requirement, as we build a |
511 | * SG frame with a newly allocated SGT buffer | |
512 | */ | |
18c21467 IR |
513 | if (skb_is_nonlinear(skb)) |
514 | return 0; | |
515 | ||
859f998e IR |
516 | /* If we have Tx timestamping, need 128B hardware annotation */ |
517 | if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) | |
518 | headroom += DPAA2_ETH_TX_HWA_SIZE; | |
519 | ||
520 | return headroom; | |
4b2d9fe8 BP |
521 | } |
522 | ||
523 | /* Extra headroom space requested to hardware, in order to make sure there's | |
524 | * no realloc'ing in forwarding scenarios | |
525 | */ | |
526 | static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv) | |
527 | { | |
27c87486 | 528 | return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE; |
8a4fd877 BP |
529 | } |
530 | ||
edad8d26 | 531 | int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); |
2d680237 ICR |
532 | int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key); |
533 | int dpaa2_eth_cls_key_size(u64 key); | |
afb90dbb | 534 | int dpaa2_eth_cls_fld_off(int prot, int field); |
2d680237 | 535 | void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields); |
edad8d26 | 536 | |
6e2387e8 | 537 | #endif /* __DPAA2_H */ |