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Commit | Line | Data |
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0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
6c43e046 | 12 | * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/init.h> | |
74 | #include <linux/delay.h> | |
75 | #include <linux/netdevice.h> | |
76 | #include <linux/etherdevice.h> | |
77 | #include <linux/skbuff.h> | |
0bbaf069 | 78 | #include <linux/if_vlan.h> |
1da177e4 LT |
79 | #include <linux/spinlock.h> |
80 | #include <linux/mm.h> | |
fe192a49 | 81 | #include <linux/of_mdio.h> |
b31a1d8b | 82 | #include <linux/of_platform.h> |
0bbaf069 KG |
83 | #include <linux/ip.h> |
84 | #include <linux/tcp.h> | |
85 | #include <linux/udp.h> | |
9c07b884 | 86 | #include <linux/in.h> |
cc772ab7 | 87 | #include <linux/net_tstamp.h> |
1da177e4 LT |
88 | |
89 | #include <asm/io.h> | |
7d350977 | 90 | #include <asm/reg.h> |
1da177e4 LT |
91 | #include <asm/irq.h> |
92 | #include <asm/uaccess.h> | |
93 | #include <linux/module.h> | |
1da177e4 LT |
94 | #include <linux/dma-mapping.h> |
95 | #include <linux/crc32.h> | |
bb40dcbb AF |
96 | #include <linux/mii.h> |
97 | #include <linux/phy.h> | |
b31a1d8b AF |
98 | #include <linux/phy_fixed.h> |
99 | #include <linux/of.h> | |
4b6ba8aa | 100 | #include <linux/of_net.h> |
1da177e4 LT |
101 | |
102 | #include "gianfar.h" | |
1da177e4 LT |
103 | |
104 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 105 | |
7f7f5316 | 106 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 107 | |
1da177e4 LT |
108 | static int gfar_enet_open(struct net_device *dev); |
109 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 110 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
111 | static void gfar_timeout(struct net_device *dev); |
112 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 113 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 114 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 115 | struct sk_buff *skb); |
1da177e4 LT |
116 | static int gfar_set_mac_address(struct net_device *dev); |
117 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
118 | static irqreturn_t gfar_error(int irq, void *dev_id); |
119 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
120 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
121 | static void adjust_link(struct net_device *dev); |
122 | static void init_registers(struct net_device *dev); | |
123 | static int init_phy(struct net_device *dev); | |
74888760 | 124 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 125 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 126 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
127 | static void gfar_set_multi(struct net_device *dev); |
128 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 129 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 130 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
131 | #ifdef CONFIG_NET_POLL_CONTROLLER |
132 | static void gfar_netpoll(struct net_device *dev); | |
133 | #endif | |
a12f801d SG |
134 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
135 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); | |
2c2db48a | 136 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
cd754a57 | 137 | int amount_pull, struct napi_struct *napi); |
7f7f5316 | 138 | void gfar_halt(struct net_device *dev); |
d87eb127 | 139 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
140 | void gfar_start(struct net_device *dev); |
141 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
142 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
143 | const u8 *addr); | |
26ccfc37 | 144 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 145 | |
1da177e4 LT |
146 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
147 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | ||
a12f801d | 150 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
151 | dma_addr_t buf) |
152 | { | |
8a102fe0 AV |
153 | u32 lstatus; |
154 | ||
155 | bdp->bufPtr = buf; | |
156 | ||
157 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 158 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
159 | lstatus |= BD_LFLAG(RXBD_WRAP); |
160 | ||
161 | eieio(); | |
162 | ||
163 | bdp->lstatus = lstatus; | |
164 | } | |
165 | ||
8728327e | 166 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 167 | { |
8728327e | 168 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
169 | struct gfar_priv_tx_q *tx_queue = NULL; |
170 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
171 | struct txbd8 *txbdp; |
172 | struct rxbd8 *rxbdp; | |
fba4ed03 | 173 | int i, j; |
a12f801d | 174 | |
fba4ed03 SG |
175 | for (i = 0; i < priv->num_tx_queues; i++) { |
176 | tx_queue = priv->tx_queue[i]; | |
177 | /* Initialize some variables in our dev structure */ | |
178 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
179 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
180 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
181 | tx_queue->skb_curtx = 0; | |
182 | tx_queue->skb_dirtytx = 0; | |
183 | ||
184 | /* Initialize Transmit Descriptor Ring */ | |
185 | txbdp = tx_queue->tx_bd_base; | |
186 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
187 | txbdp->lstatus = 0; | |
188 | txbdp->bufPtr = 0; | |
189 | txbdp++; | |
190 | } | |
8728327e | 191 | |
fba4ed03 SG |
192 | /* Set the last descriptor in the ring to indicate wrap */ |
193 | txbdp--; | |
194 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
195 | } |
196 | ||
fba4ed03 SG |
197 | for (i = 0; i < priv->num_rx_queues; i++) { |
198 | rx_queue = priv->rx_queue[i]; | |
199 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
200 | rx_queue->skb_currx = 0; | |
201 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 202 | |
fba4ed03 SG |
203 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
204 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 205 | |
fba4ed03 SG |
206 | if (skb) { |
207 | gfar_init_rxbdp(rx_queue, rxbdp, | |
208 | rxbdp->bufPtr); | |
209 | } else { | |
210 | skb = gfar_new_skb(ndev); | |
211 | if (!skb) { | |
59deab26 | 212 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
1eb8f7a7 | 213 | return -ENOMEM; |
fba4ed03 SG |
214 | } |
215 | rx_queue->rx_skbuff[j] = skb; | |
216 | ||
217 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 218 | } |
8728327e | 219 | |
fba4ed03 | 220 | rxbdp++; |
8728327e AV |
221 | } |
222 | ||
8728327e AV |
223 | } |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
229 | { | |
826aa4a0 | 230 | void *vaddr; |
fba4ed03 SG |
231 | dma_addr_t addr; |
232 | int i, j, k; | |
826aa4a0 AV |
233 | struct gfar_private *priv = netdev_priv(ndev); |
234 | struct device *dev = &priv->ofdev->dev; | |
a12f801d SG |
235 | struct gfar_priv_tx_q *tx_queue = NULL; |
236 | struct gfar_priv_rx_q *rx_queue = NULL; | |
237 | ||
fba4ed03 SG |
238 | priv->total_tx_ring_size = 0; |
239 | for (i = 0; i < priv->num_tx_queues; i++) | |
240 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
241 | ||
242 | priv->total_rx_ring_size = 0; | |
243 | for (i = 0; i < priv->num_rx_queues; i++) | |
244 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
245 | |
246 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 247 | vaddr = dma_alloc_coherent(dev, |
fba4ed03 SG |
248 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
249 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
250 | &addr, GFP_KERNEL); | |
826aa4a0 | 251 | if (!vaddr) { |
59deab26 JP |
252 | netif_err(priv, ifup, ndev, |
253 | "Could not allocate buffer descriptors!\n"); | |
826aa4a0 AV |
254 | return -ENOMEM; |
255 | } | |
256 | ||
fba4ed03 SG |
257 | for (i = 0; i < priv->num_tx_queues; i++) { |
258 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 259 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
260 | tx_queue->tx_bd_dma_base = addr; |
261 | tx_queue->dev = ndev; | |
262 | /* enet DMA only understands physical addresses */ | |
bc4598bc JC |
263 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
264 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 265 | } |
826aa4a0 | 266 | |
826aa4a0 | 267 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
268 | for (i = 0; i < priv->num_rx_queues; i++) { |
269 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 270 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
271 | rx_queue->rx_bd_dma_base = addr; |
272 | rx_queue->dev = ndev; | |
bc4598bc JC |
273 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
274 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 275 | } |
826aa4a0 AV |
276 | |
277 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
278 | for (i = 0; i < priv->num_tx_queues; i++) { |
279 | tx_queue = priv->tx_queue[i]; | |
280 | tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) * | |
bc4598bc JC |
281 | tx_queue->tx_ring_size, |
282 | GFP_KERNEL); | |
fba4ed03 | 283 | if (!tx_queue->tx_skbuff) { |
59deab26 JP |
284 | netif_err(priv, ifup, ndev, |
285 | "Could not allocate tx_skbuff\n"); | |
fba4ed03 SG |
286 | goto cleanup; |
287 | } | |
826aa4a0 | 288 | |
fba4ed03 SG |
289 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
290 | tx_queue->tx_skbuff[k] = NULL; | |
291 | } | |
826aa4a0 | 292 | |
fba4ed03 SG |
293 | for (i = 0; i < priv->num_rx_queues; i++) { |
294 | rx_queue = priv->rx_queue[i]; | |
295 | rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) * | |
bc4598bc JC |
296 | rx_queue->rx_ring_size, |
297 | GFP_KERNEL); | |
826aa4a0 | 298 | |
fba4ed03 | 299 | if (!rx_queue->rx_skbuff) { |
59deab26 JP |
300 | netif_err(priv, ifup, ndev, |
301 | "Could not allocate rx_skbuff\n"); | |
fba4ed03 SG |
302 | goto cleanup; |
303 | } | |
304 | ||
305 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
306 | rx_queue->rx_skbuff[j] = NULL; | |
307 | } | |
826aa4a0 | 308 | |
8728327e AV |
309 | if (gfar_init_bds(ndev)) |
310 | goto cleanup; | |
826aa4a0 AV |
311 | |
312 | return 0; | |
313 | ||
314 | cleanup: | |
315 | free_skb_resources(priv); | |
316 | return -ENOMEM; | |
317 | } | |
318 | ||
fba4ed03 SG |
319 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
320 | { | |
46ceb60c | 321 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 322 | u32 __iomem *baddr; |
fba4ed03 SG |
323 | int i; |
324 | ||
325 | baddr = ®s->tbase0; | |
bc4598bc | 326 | for (i = 0; i < priv->num_tx_queues; i++) { |
fba4ed03 | 327 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); |
bc4598bc | 328 | baddr += 2; |
fba4ed03 SG |
329 | } |
330 | ||
331 | baddr = ®s->rbase0; | |
bc4598bc | 332 | for (i = 0; i < priv->num_rx_queues; i++) { |
fba4ed03 | 333 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); |
bc4598bc | 334 | baddr += 2; |
fba4ed03 SG |
335 | } |
336 | } | |
337 | ||
826aa4a0 AV |
338 | static void gfar_init_mac(struct net_device *ndev) |
339 | { | |
340 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 341 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
342 | u32 rctrl = 0; |
343 | u32 tctrl = 0; | |
344 | u32 attrs = 0; | |
345 | ||
fba4ed03 SG |
346 | /* write the tx/rx base registers */ |
347 | gfar_init_tx_rx_base(priv); | |
32c513bc | 348 | |
826aa4a0 | 349 | /* Configure the coalescing support */ |
46ceb60c | 350 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
fba4ed03 | 351 | |
1ccb8389 | 352 | if (priv->rx_filer_enable) { |
fba4ed03 | 353 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
354 | /* Program the RIR0 reg with the required distribution */ |
355 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
356 | } | |
826aa4a0 | 357 | |
f5ae6279 CM |
358 | /* Restore PROMISC mode */ |
359 | if (ndev->flags & IFF_PROMISC) | |
360 | rctrl |= RCTRL_PROM; | |
361 | ||
8b3afe95 | 362 | if (ndev->features & NETIF_F_RXCSUM) |
826aa4a0 AV |
363 | rctrl |= RCTRL_CHECKSUMMING; |
364 | ||
365 | if (priv->extended_hash) { | |
366 | rctrl |= RCTRL_EXTHASH; | |
367 | ||
368 | gfar_clear_exact_match(ndev); | |
369 | rctrl |= RCTRL_EMEN; | |
370 | } | |
371 | ||
372 | if (priv->padding) { | |
373 | rctrl &= ~RCTRL_PAL_MASK; | |
374 | rctrl |= RCTRL_PADDING(priv->padding); | |
375 | } | |
376 | ||
cc772ab7 MR |
377 | /* Insert receive time stamps into padding alignment bytes */ |
378 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
379 | rctrl &= ~RCTRL_PAL_MASK; | |
97553f7f | 380 | rctrl |= RCTRL_PADDING(8); |
cc772ab7 MR |
381 | priv->padding = 8; |
382 | } | |
383 | ||
97553f7f MR |
384 | /* Enable HW time stamping if requested from user space */ |
385 | if (priv->hwts_rx_en) | |
386 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; | |
387 | ||
87c288c6 | 388 | if (ndev->features & NETIF_F_HW_VLAN_RX) |
b852b720 | 389 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
826aa4a0 AV |
390 | |
391 | /* Init rctrl based on our settings */ | |
392 | gfar_write(®s->rctrl, rctrl); | |
393 | ||
394 | if (ndev->features & NETIF_F_IP_CSUM) | |
395 | tctrl |= TCTRL_INIT_CSUM; | |
396 | ||
b98b8bab CM |
397 | if (priv->prio_sched_en) |
398 | tctrl |= TCTRL_TXSCHED_PRIO; | |
399 | else { | |
400 | tctrl |= TCTRL_TXSCHED_WRRS; | |
401 | gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); | |
402 | gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); | |
403 | } | |
fba4ed03 | 404 | |
826aa4a0 AV |
405 | gfar_write(®s->tctrl, tctrl); |
406 | ||
407 | /* Set the extraction length and index */ | |
408 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
409 | ATTRELI_EI(priv->rx_stash_index); | |
410 | ||
411 | gfar_write(®s->attreli, attrs); | |
412 | ||
413 | /* Start with defaults, and add stashing or locking | |
0977f817 JC |
414 | * depending on the approprate variables |
415 | */ | |
826aa4a0 AV |
416 | attrs = ATTR_INIT_SETTINGS; |
417 | ||
418 | if (priv->bd_stash_en) | |
419 | attrs |= ATTR_BDSTASH; | |
420 | ||
421 | if (priv->rx_stash_size != 0) | |
422 | attrs |= ATTR_BUFSTASH; | |
423 | ||
424 | gfar_write(®s->attr, attrs); | |
425 | ||
426 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
427 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
428 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
429 | } | |
430 | ||
a7f38041 SG |
431 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
432 | { | |
433 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
434 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
435 | unsigned long tx_packets = 0, tx_bytes = 0; | |
3a2e16c8 | 436 | int i; |
a7f38041 SG |
437 | |
438 | for (i = 0; i < priv->num_rx_queues; i++) { | |
439 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
bc4598bc | 440 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; |
a7f38041 SG |
441 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; |
442 | } | |
443 | ||
444 | dev->stats.rx_packets = rx_packets; | |
bc4598bc | 445 | dev->stats.rx_bytes = rx_bytes; |
a7f38041 SG |
446 | dev->stats.rx_dropped = rx_dropped; |
447 | ||
448 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
449 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
450 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
451 | } |
452 | ||
bc4598bc | 453 | dev->stats.tx_bytes = tx_bytes; |
a7f38041 SG |
454 | dev->stats.tx_packets = tx_packets; |
455 | ||
456 | return &dev->stats; | |
457 | } | |
458 | ||
26ccfc37 AF |
459 | static const struct net_device_ops gfar_netdev_ops = { |
460 | .ndo_open = gfar_enet_open, | |
461 | .ndo_start_xmit = gfar_start_xmit, | |
462 | .ndo_stop = gfar_close, | |
463 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 464 | .ndo_set_features = gfar_set_features, |
afc4b13d | 465 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
466 | .ndo_tx_timeout = gfar_timeout, |
467 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 468 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
469 | .ndo_set_mac_address = eth_mac_addr, |
470 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
471 | #ifdef CONFIG_NET_POLL_CONTROLLER |
472 | .ndo_poll_controller = gfar_netpoll, | |
473 | #endif | |
474 | }; | |
475 | ||
fba4ed03 SG |
476 | void lock_rx_qs(struct gfar_private *priv) |
477 | { | |
3a2e16c8 | 478 | int i; |
fba4ed03 SG |
479 | |
480 | for (i = 0; i < priv->num_rx_queues; i++) | |
481 | spin_lock(&priv->rx_queue[i]->rxlock); | |
482 | } | |
483 | ||
484 | void lock_tx_qs(struct gfar_private *priv) | |
485 | { | |
3a2e16c8 | 486 | int i; |
fba4ed03 SG |
487 | |
488 | for (i = 0; i < priv->num_tx_queues; i++) | |
489 | spin_lock(&priv->tx_queue[i]->txlock); | |
490 | } | |
491 | ||
492 | void unlock_rx_qs(struct gfar_private *priv) | |
493 | { | |
3a2e16c8 | 494 | int i; |
fba4ed03 SG |
495 | |
496 | for (i = 0; i < priv->num_rx_queues; i++) | |
497 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
498 | } | |
499 | ||
500 | void unlock_tx_qs(struct gfar_private *priv) | |
501 | { | |
3a2e16c8 | 502 | int i; |
fba4ed03 SG |
503 | |
504 | for (i = 0; i < priv->num_tx_queues; i++) | |
505 | spin_unlock(&priv->tx_queue[i]->txlock); | |
506 | } | |
507 | ||
87c288c6 JP |
508 | static bool gfar_is_vlan_on(struct gfar_private *priv) |
509 | { | |
510 | return (priv->ndev->features & NETIF_F_HW_VLAN_RX) || | |
511 | (priv->ndev->features & NETIF_F_HW_VLAN_TX); | |
512 | } | |
513 | ||
7f7f5316 AF |
514 | /* Returns 1 if incoming frames use an FCB */ |
515 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 516 | { |
87c288c6 | 517 | return gfar_is_vlan_on(priv) || |
bc4598bc JC |
518 | (priv->ndev->features & NETIF_F_RXCSUM) || |
519 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER); | |
0bbaf069 | 520 | } |
bb40dcbb | 521 | |
fba4ed03 SG |
522 | static void free_tx_pointers(struct gfar_private *priv) |
523 | { | |
3a2e16c8 | 524 | int i; |
fba4ed03 SG |
525 | |
526 | for (i = 0; i < priv->num_tx_queues; i++) | |
527 | kfree(priv->tx_queue[i]); | |
528 | } | |
529 | ||
530 | static void free_rx_pointers(struct gfar_private *priv) | |
531 | { | |
3a2e16c8 | 532 | int i; |
fba4ed03 SG |
533 | |
534 | for (i = 0; i < priv->num_rx_queues; i++) | |
535 | kfree(priv->rx_queue[i]); | |
536 | } | |
537 | ||
46ceb60c SG |
538 | static void unmap_group_regs(struct gfar_private *priv) |
539 | { | |
3a2e16c8 | 540 | int i; |
46ceb60c SG |
541 | |
542 | for (i = 0; i < MAXGROUPS; i++) | |
543 | if (priv->gfargrp[i].regs) | |
544 | iounmap(priv->gfargrp[i].regs); | |
545 | } | |
546 | ||
547 | static void disable_napi(struct gfar_private *priv) | |
548 | { | |
3a2e16c8 | 549 | int i; |
46ceb60c SG |
550 | |
551 | for (i = 0; i < priv->num_grps; i++) | |
552 | napi_disable(&priv->gfargrp[i].napi); | |
553 | } | |
554 | ||
555 | static void enable_napi(struct gfar_private *priv) | |
556 | { | |
3a2e16c8 | 557 | int i; |
46ceb60c SG |
558 | |
559 | for (i = 0; i < priv->num_grps; i++) | |
560 | napi_enable(&priv->gfargrp[i].napi); | |
561 | } | |
562 | ||
563 | static int gfar_parse_group(struct device_node *np, | |
bc4598bc | 564 | struct gfar_private *priv, const char *model) |
46ceb60c SG |
565 | { |
566 | u32 *queue_mask; | |
46ceb60c | 567 | |
7ce97d4f | 568 | priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0); |
46ceb60c SG |
569 | if (!priv->gfargrp[priv->num_grps].regs) |
570 | return -ENOMEM; | |
571 | ||
572 | priv->gfargrp[priv->num_grps].interruptTransmit = | |
573 | irq_of_parse_and_map(np, 0); | |
574 | ||
575 | /* If we aren't the FEC we have multiple interrupts */ | |
576 | if (model && strcasecmp(model, "FEC")) { | |
577 | priv->gfargrp[priv->num_grps].interruptReceive = | |
578 | irq_of_parse_and_map(np, 1); | |
579 | priv->gfargrp[priv->num_grps].interruptError = | |
580 | irq_of_parse_and_map(np,2); | |
28cb6ccd NK |
581 | if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ || |
582 | priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ || | |
583 | priv->gfargrp[priv->num_grps].interruptError == NO_IRQ) | |
46ceb60c | 584 | return -EINVAL; |
46ceb60c SG |
585 | } |
586 | ||
587 | priv->gfargrp[priv->num_grps].grp_id = priv->num_grps; | |
588 | priv->gfargrp[priv->num_grps].priv = priv; | |
589 | spin_lock_init(&priv->gfargrp[priv->num_grps].grplock); | |
bc4598bc JC |
590 | if (priv->mode == MQ_MG_MODE) { |
591 | queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); | |
592 | priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ? | |
593 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); | |
594 | queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); | |
595 | priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ? | |
596 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); | |
46ceb60c SG |
597 | } else { |
598 | priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF; | |
599 | priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF; | |
600 | } | |
601 | priv->num_grps++; | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
2dc11581 | 606 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 607 | { |
b31a1d8b AF |
608 | const char *model; |
609 | const char *ctype; | |
610 | const void *mac_addr; | |
fba4ed03 SG |
611 | int err = 0, i; |
612 | struct net_device *dev = NULL; | |
613 | struct gfar_private *priv = NULL; | |
61c7a080 | 614 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 615 | struct device_node *child = NULL; |
4d7902f2 AF |
616 | const u32 *stash; |
617 | const u32 *stash_len; | |
618 | const u32 *stash_idx; | |
fba4ed03 SG |
619 | unsigned int num_tx_qs, num_rx_qs; |
620 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
621 | |
622 | if (!np || !of_device_is_available(np)) | |
623 | return -ENODEV; | |
624 | ||
fba4ed03 SG |
625 | /* parse the num of tx and rx queues */ |
626 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
627 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
628 | ||
629 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
630 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
631 | num_tx_qs, MAX_TX_QS); | |
632 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
633 | return -EINVAL; |
634 | } | |
635 | ||
636 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
637 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
638 | ||
639 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
640 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
641 | num_rx_qs, MAX_RX_QS); | |
642 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
643 | return -EINVAL; |
644 | } | |
645 | ||
646 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
647 | dev = *pdev; | |
648 | if (NULL == dev) | |
649 | return -ENOMEM; | |
650 | ||
651 | priv = netdev_priv(dev); | |
61c7a080 | 652 | priv->node = ofdev->dev.of_node; |
fba4ed03 SG |
653 | priv->ndev = dev; |
654 | ||
fba4ed03 | 655 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 656 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 657 | priv->num_rx_queues = num_rx_qs; |
46ceb60c | 658 | priv->num_grps = 0x0; |
b31a1d8b | 659 | |
0977f817 | 660 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
661 | INIT_LIST_HEAD(&priv->rx_list.list); |
662 | priv->rx_list.count = 0; | |
663 | mutex_init(&priv->rx_queue_access); | |
664 | ||
b31a1d8b AF |
665 | model = of_get_property(np, "model", NULL); |
666 | ||
46ceb60c SG |
667 | for (i = 0; i < MAXGROUPS; i++) |
668 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 669 | |
46ceb60c SG |
670 | /* Parse and initialize group specific information */ |
671 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
672 | priv->mode = MQ_MG_MODE; | |
673 | for_each_child_of_node(np, child) { | |
674 | err = gfar_parse_group(child, priv, model); | |
675 | if (err) | |
676 | goto err_grp_init; | |
b31a1d8b | 677 | } |
46ceb60c SG |
678 | } else { |
679 | priv->mode = SQ_SG_MODE; | |
680 | err = gfar_parse_group(np, priv, model); | |
bc4598bc | 681 | if (err) |
46ceb60c | 682 | goto err_grp_init; |
b31a1d8b AF |
683 | } |
684 | ||
fba4ed03 SG |
685 | for (i = 0; i < priv->num_tx_queues; i++) |
686 | priv->tx_queue[i] = NULL; | |
687 | for (i = 0; i < priv->num_rx_queues; i++) | |
688 | priv->rx_queue[i] = NULL; | |
689 | ||
690 | for (i = 0; i < priv->num_tx_queues; i++) { | |
de47f072 JP |
691 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), |
692 | GFP_KERNEL); | |
fba4ed03 SG |
693 | if (!priv->tx_queue[i]) { |
694 | err = -ENOMEM; | |
695 | goto tx_alloc_failed; | |
696 | } | |
697 | priv->tx_queue[i]->tx_skbuff = NULL; | |
698 | priv->tx_queue[i]->qindex = i; | |
699 | priv->tx_queue[i]->dev = dev; | |
700 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
701 | } | |
702 | ||
703 | for (i = 0; i < priv->num_rx_queues; i++) { | |
de47f072 JP |
704 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), |
705 | GFP_KERNEL); | |
fba4ed03 SG |
706 | if (!priv->rx_queue[i]) { |
707 | err = -ENOMEM; | |
708 | goto rx_alloc_failed; | |
709 | } | |
710 | priv->rx_queue[i]->rx_skbuff = NULL; | |
711 | priv->rx_queue[i]->qindex = i; | |
712 | priv->rx_queue[i]->dev = dev; | |
713 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
714 | } | |
715 | ||
716 | ||
4d7902f2 AF |
717 | stash = of_get_property(np, "bd-stash", NULL); |
718 | ||
a12f801d | 719 | if (stash) { |
4d7902f2 AF |
720 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
721 | priv->bd_stash_en = 1; | |
722 | } | |
723 | ||
724 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
725 | ||
726 | if (stash_len) | |
727 | priv->rx_stash_size = *stash_len; | |
728 | ||
729 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
730 | ||
731 | if (stash_idx) | |
732 | priv->rx_stash_index = *stash_idx; | |
733 | ||
734 | if (stash_len || stash_idx) | |
735 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
736 | ||
b31a1d8b | 737 | mac_addr = of_get_mac_address(np); |
bc4598bc | 738 | |
b31a1d8b | 739 | if (mac_addr) |
6a3c910c | 740 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
741 | |
742 | if (model && !strcasecmp(model, "TSEC")) | |
bc4598bc JC |
743 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
744 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
745 | FSL_GIANFAR_DEV_HAS_RMON | | |
746 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
747 | ||
b31a1d8b | 748 | if (model && !strcasecmp(model, "eTSEC")) |
bc4598bc JC |
749 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
750 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
751 | FSL_GIANFAR_DEV_HAS_RMON | | |
752 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
753 | FSL_GIANFAR_DEV_HAS_PADDING | | |
754 | FSL_GIANFAR_DEV_HAS_CSUM | | |
755 | FSL_GIANFAR_DEV_HAS_VLAN | | |
756 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
757 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | | |
758 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
759 | |
760 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
761 | ||
762 | /* We only care about rgmii-id. The rest are autodetected */ | |
763 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
764 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
765 | else | |
766 | priv->interface = PHY_INTERFACE_MODE_MII; | |
767 | ||
768 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
769 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
770 | ||
fe192a49 | 771 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
772 | |
773 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 774 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
775 | |
776 | return 0; | |
777 | ||
fba4ed03 SG |
778 | rx_alloc_failed: |
779 | free_rx_pointers(priv); | |
780 | tx_alloc_failed: | |
781 | free_tx_pointers(priv); | |
46ceb60c SG |
782 | err_grp_init: |
783 | unmap_group_regs(priv); | |
fba4ed03 | 784 | free_netdev(dev); |
b31a1d8b AF |
785 | return err; |
786 | } | |
787 | ||
cc772ab7 | 788 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
bc4598bc | 789 | struct ifreq *ifr, int cmd) |
cc772ab7 MR |
790 | { |
791 | struct hwtstamp_config config; | |
792 | struct gfar_private *priv = netdev_priv(netdev); | |
793 | ||
794 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
795 | return -EFAULT; | |
796 | ||
797 | /* reserved for future extensions */ | |
798 | if (config.flags) | |
799 | return -EINVAL; | |
800 | ||
f0ee7acf MR |
801 | switch (config.tx_type) { |
802 | case HWTSTAMP_TX_OFF: | |
803 | priv->hwts_tx_en = 0; | |
804 | break; | |
805 | case HWTSTAMP_TX_ON: | |
806 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
807 | return -ERANGE; | |
808 | priv->hwts_tx_en = 1; | |
809 | break; | |
810 | default: | |
cc772ab7 | 811 | return -ERANGE; |
f0ee7acf | 812 | } |
cc772ab7 MR |
813 | |
814 | switch (config.rx_filter) { | |
815 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
816 | if (priv->hwts_rx_en) { |
817 | stop_gfar(netdev); | |
818 | priv->hwts_rx_en = 0; | |
819 | startup_gfar(netdev); | |
820 | } | |
cc772ab7 MR |
821 | break; |
822 | default: | |
823 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
824 | return -ERANGE; | |
97553f7f MR |
825 | if (!priv->hwts_rx_en) { |
826 | stop_gfar(netdev); | |
827 | priv->hwts_rx_en = 1; | |
828 | startup_gfar(netdev); | |
829 | } | |
cc772ab7 MR |
830 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
831 | break; | |
832 | } | |
833 | ||
834 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
835 | -EFAULT : 0; | |
836 | } | |
837 | ||
0faac9f7 CW |
838 | /* Ioctl MII Interface */ |
839 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
840 | { | |
841 | struct gfar_private *priv = netdev_priv(dev); | |
842 | ||
843 | if (!netif_running(dev)) | |
844 | return -EINVAL; | |
845 | ||
cc772ab7 MR |
846 | if (cmd == SIOCSHWTSTAMP) |
847 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
848 | ||
0faac9f7 CW |
849 | if (!priv->phydev) |
850 | return -ENODEV; | |
851 | ||
28b04113 | 852 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
853 | } |
854 | ||
fba4ed03 SG |
855 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
856 | { | |
857 | unsigned int new_bit_map = 0x0; | |
858 | int mask = 0x1 << (max_qs - 1), i; | |
bc4598bc | 859 | |
fba4ed03 SG |
860 | for (i = 0; i < max_qs; i++) { |
861 | if (bit_map & mask) | |
862 | new_bit_map = new_bit_map + (1 << i); | |
863 | mask = mask >> 0x1; | |
864 | } | |
865 | return new_bit_map; | |
866 | } | |
7a8b3372 | 867 | |
18294ad1 AV |
868 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
869 | u32 class) | |
7a8b3372 SG |
870 | { |
871 | u32 rqfpr = FPR_FILER_MASK; | |
872 | u32 rqfcr = 0x0; | |
873 | ||
874 | rqfar--; | |
875 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
876 | priv->ftp_rqfpr[rqfar] = rqfpr; |
877 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
878 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
879 | ||
880 | rqfar--; | |
881 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
882 | priv->ftp_rqfpr[rqfar] = rqfpr; |
883 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
884 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
885 | ||
886 | rqfar--; | |
887 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
888 | rqfpr = class; | |
6c43e046 WJB |
889 | priv->ftp_rqfcr[rqfar] = rqfcr; |
890 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
891 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
892 | ||
893 | rqfar--; | |
894 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
895 | rqfpr = class; | |
6c43e046 WJB |
896 | priv->ftp_rqfcr[rqfar] = rqfcr; |
897 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
898 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
899 | ||
900 | return rqfar; | |
901 | } | |
902 | ||
903 | static void gfar_init_filer_table(struct gfar_private *priv) | |
904 | { | |
905 | int i = 0x0; | |
906 | u32 rqfar = MAX_FILER_IDX; | |
907 | u32 rqfcr = 0x0; | |
908 | u32 rqfpr = FPR_FILER_MASK; | |
909 | ||
910 | /* Default rule */ | |
911 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
912 | priv->ftp_rqfcr[rqfar] = rqfcr; |
913 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
914 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
915 | ||
916 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
917 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
918 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
919 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
920 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
921 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
922 | ||
85dd08eb | 923 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
924 | priv->cur_filer_idx = rqfar; |
925 | ||
926 | /* Rest are masked rules */ | |
927 | rqfcr = RQFCR_CMP_NOMATCH; | |
928 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
929 | priv->ftp_rqfcr[i] = rqfcr; |
930 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
931 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
932 | } | |
933 | } | |
934 | ||
7d350977 AV |
935 | static void gfar_detect_errata(struct gfar_private *priv) |
936 | { | |
937 | struct device *dev = &priv->ofdev->dev; | |
938 | unsigned int pvr = mfspr(SPRN_PVR); | |
939 | unsigned int svr = mfspr(SPRN_SVR); | |
940 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
941 | unsigned int rev = svr & 0xffff; | |
942 | ||
943 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
944 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
bc4598bc | 945 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
7d350977 AV |
946 | priv->errata |= GFAR_ERRATA_74; |
947 | ||
deb90eac AV |
948 | /* MPC8313 and MPC837x all rev */ |
949 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 950 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
deb90eac AV |
951 | priv->errata |= GFAR_ERRATA_76; |
952 | ||
511d934f AV |
953 | /* MPC8313 and MPC837x all rev */ |
954 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 955 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
511d934f AV |
956 | priv->errata |= GFAR_ERRATA_A002; |
957 | ||
4363c2fd AD |
958 | /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ |
959 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || | |
bc4598bc | 960 | (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) |
4363c2fd AD |
961 | priv->errata |= GFAR_ERRATA_12; |
962 | ||
7d350977 AV |
963 | if (priv->errata) |
964 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
965 | priv->errata); | |
966 | } | |
967 | ||
bb40dcbb | 968 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
969 | * and anything else we need before we start |
970 | */ | |
74888760 | 971 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 LT |
972 | { |
973 | u32 tempval; | |
974 | struct net_device *dev = NULL; | |
975 | struct gfar_private *priv = NULL; | |
f4983704 | 976 | struct gfar __iomem *regs = NULL; |
46ceb60c | 977 | int err = 0, i, grp_idx = 0; |
fba4ed03 | 978 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 979 | u32 isrg = 0; |
18294ad1 | 980 | u32 __iomem *baddr; |
1da177e4 | 981 | |
fba4ed03 | 982 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 983 | |
fba4ed03 SG |
984 | if (err) |
985 | return err; | |
1da177e4 LT |
986 | |
987 | priv = netdev_priv(dev); | |
4826857f KG |
988 | priv->ndev = dev; |
989 | priv->ofdev = ofdev; | |
61c7a080 | 990 | priv->node = ofdev->dev.of_node; |
4826857f | 991 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 992 | |
d87eb127 | 993 | spin_lock_init(&priv->bflock); |
ab939905 | 994 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 995 | |
b31a1d8b | 996 | dev_set_drvdata(&ofdev->dev, priv); |
46ceb60c | 997 | regs = priv->gfargrp[0].regs; |
1da177e4 | 998 | |
7d350977 AV |
999 | gfar_detect_errata(priv); |
1000 | ||
0977f817 JC |
1001 | /* Stop the DMA engine now, in case it was running before |
1002 | * (The firmware could have used it, and left it running). | |
1003 | */ | |
257d938a | 1004 | gfar_halt(dev); |
1da177e4 LT |
1005 | |
1006 | /* Reset MAC layer */ | |
f4983704 | 1007 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 1008 | |
b98ac702 AF |
1009 | /* We need to delay at least 3 TX clocks */ |
1010 | udelay(2); | |
1011 | ||
1da177e4 | 1012 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
f4983704 | 1013 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
1014 | |
1015 | /* Initialize MACCFG2. */ | |
7d350977 AV |
1016 | tempval = MACCFG2_INIT_SETTINGS; |
1017 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1018 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1019 | gfar_write(®s->maccfg2, tempval); | |
1da177e4 LT |
1020 | |
1021 | /* Initialize ECNTRL */ | |
f4983704 | 1022 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 1023 | |
1da177e4 | 1024 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 1025 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 1026 | |
b31a1d8b | 1027 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
1028 | |
1029 | /* Fill in the dev structure */ | |
1da177e4 | 1030 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1031 | dev->mtu = 1500; |
26ccfc37 | 1032 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1033 | dev->ethtool_ops = &gfar_ethtool_ops; |
1034 | ||
fba4ed03 | 1035 | /* Register for napi ...We are registering NAPI for each grp */ |
46ceb60c | 1036 | for (i = 0; i < priv->num_grps; i++) |
bc4598bc JC |
1037 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, |
1038 | GFAR_DEV_WEIGHT); | |
a12f801d | 1039 | |
b31a1d8b | 1040 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 | 1041 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1042 | NETIF_F_RXCSUM; |
8b3afe95 | 1043 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1044 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; |
8b3afe95 | 1045 | } |
0bbaf069 | 1046 | |
87c288c6 JP |
1047 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
1048 | dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
e2c53be2 | 1049 | dev->features |= NETIF_F_HW_VLAN_RX; |
87c288c6 | 1050 | } |
0bbaf069 | 1051 | |
b31a1d8b | 1052 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
1053 | priv->extended_hash = 1; |
1054 | priv->hash_width = 9; | |
1055 | ||
f4983704 SG |
1056 | priv->hash_regs[0] = ®s->igaddr0; |
1057 | priv->hash_regs[1] = ®s->igaddr1; | |
1058 | priv->hash_regs[2] = ®s->igaddr2; | |
1059 | priv->hash_regs[3] = ®s->igaddr3; | |
1060 | priv->hash_regs[4] = ®s->igaddr4; | |
1061 | priv->hash_regs[5] = ®s->igaddr5; | |
1062 | priv->hash_regs[6] = ®s->igaddr6; | |
1063 | priv->hash_regs[7] = ®s->igaddr7; | |
1064 | priv->hash_regs[8] = ®s->gaddr0; | |
1065 | priv->hash_regs[9] = ®s->gaddr1; | |
1066 | priv->hash_regs[10] = ®s->gaddr2; | |
1067 | priv->hash_regs[11] = ®s->gaddr3; | |
1068 | priv->hash_regs[12] = ®s->gaddr4; | |
1069 | priv->hash_regs[13] = ®s->gaddr5; | |
1070 | priv->hash_regs[14] = ®s->gaddr6; | |
1071 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1072 | |
1073 | } else { | |
1074 | priv->extended_hash = 0; | |
1075 | priv->hash_width = 8; | |
1076 | ||
f4983704 SG |
1077 | priv->hash_regs[0] = ®s->gaddr0; |
1078 | priv->hash_regs[1] = ®s->gaddr1; | |
1079 | priv->hash_regs[2] = ®s->gaddr2; | |
1080 | priv->hash_regs[3] = ®s->gaddr3; | |
1081 | priv->hash_regs[4] = ®s->gaddr4; | |
1082 | priv->hash_regs[5] = ®s->gaddr5; | |
1083 | priv->hash_regs[6] = ®s->gaddr6; | |
1084 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1085 | } |
1086 | ||
b31a1d8b | 1087 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1088 | priv->padding = DEFAULT_PADDING; |
1089 | else | |
1090 | priv->padding = 0; | |
1091 | ||
cc772ab7 | 1092 | if (dev->features & NETIF_F_IP_CSUM || |
bc4598bc | 1093 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) |
bee9e58c | 1094 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 | 1095 | |
46ceb60c SG |
1096 | /* Program the isrg regs only if number of grps > 1 */ |
1097 | if (priv->num_grps > 1) { | |
1098 | baddr = ®s->isrg0; | |
1099 | for (i = 0; i < priv->num_grps; i++) { | |
1100 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1101 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1102 | gfar_write(baddr, isrg); | |
1103 | baddr++; | |
1104 | isrg = 0x0; | |
1105 | } | |
1106 | } | |
1107 | ||
fba4ed03 | 1108 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1109 | * but, for_each_set_bit parses from right to left, which |
0977f817 JC |
1110 | * basically reverses the queue numbers |
1111 | */ | |
46ceb60c | 1112 | for (i = 0; i< priv->num_grps; i++) { |
bc4598bc JC |
1113 | priv->gfargrp[i].tx_bit_map = |
1114 | reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1115 | priv->gfargrp[i].rx_bit_map = | |
1116 | reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
46ceb60c SG |
1117 | } |
1118 | ||
1119 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
0977f817 JC |
1120 | * also assign queues to groups |
1121 | */ | |
46ceb60c SG |
1122 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { |
1123 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
bc4598bc | 1124 | |
984b3f57 | 1125 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
bc4598bc | 1126 | priv->num_rx_queues) { |
46ceb60c SG |
1127 | priv->gfargrp[grp_idx].num_rx_queues++; |
1128 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1129 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1130 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1131 | } | |
1132 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
bc4598bc | 1133 | |
984b3f57 | 1134 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
bc4598bc | 1135 | priv->num_tx_queues) { |
46ceb60c SG |
1136 | priv->gfargrp[grp_idx].num_tx_queues++; |
1137 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1138 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1139 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1140 | } | |
1141 | priv->gfargrp[grp_idx].rstat = rstat; | |
1142 | priv->gfargrp[grp_idx].tstat = tstat; | |
1143 | rstat = tstat =0; | |
fba4ed03 | 1144 | } |
fba4ed03 SG |
1145 | |
1146 | gfar_write(®s->rqueue, rqueue); | |
1147 | gfar_write(®s->tqueue, tqueue); | |
1148 | ||
1da177e4 | 1149 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1150 | |
a12f801d | 1151 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1152 | for (i = 0; i < priv->num_tx_queues; i++) { |
1153 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1154 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1155 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1156 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1157 | } | |
a12f801d | 1158 | |
fba4ed03 SG |
1159 | for (i = 0; i < priv->num_rx_queues; i++) { |
1160 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1161 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1162 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1163 | } | |
1da177e4 | 1164 | |
0977f817 | 1165 | /* always enable rx filer */ |
4aa3a715 | 1166 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1167 | /* Enable most messages by default */ |
1168 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
b98b8bab CM |
1169 | /* use pritority h/w tx queue scheduling for single queue devices */ |
1170 | if (priv->num_tx_queues == 1) | |
1171 | priv->prio_sched_en = 1; | |
0bbaf069 | 1172 | |
d3eab82b TP |
1173 | /* Carrier starts down, phylib will bring it up */ |
1174 | netif_carrier_off(dev); | |
1175 | ||
1da177e4 LT |
1176 | err = register_netdev(dev); |
1177 | ||
1178 | if (err) { | |
59deab26 | 1179 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1180 | goto register_fail; |
1181 | } | |
1182 | ||
2884e5cc | 1183 | device_init_wakeup(&dev->dev, |
bc4598bc JC |
1184 | priv->device_flags & |
1185 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
2884e5cc | 1186 | |
c50a5d9a | 1187 | /* fill out IRQ number and name fields */ |
46ceb60c | 1188 | for (i = 0; i < priv->num_grps; i++) { |
46ceb60c | 1189 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0015e551 JP |
1190 | sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s", |
1191 | dev->name, "_g", '0' + i, "_tx"); | |
1192 | sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s", | |
1193 | dev->name, "_g", '0' + i, "_rx"); | |
1194 | sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s", | |
1195 | dev->name, "_g", '0' + i, "_er"); | |
46ceb60c | 1196 | } else |
0015e551 | 1197 | strcpy(priv->gfargrp[i].int_name_tx, dev->name); |
46ceb60c | 1198 | } |
c50a5d9a | 1199 | |
7a8b3372 SG |
1200 | /* Initialize the filer table */ |
1201 | gfar_init_filer_table(priv); | |
1202 | ||
7f7f5316 AF |
1203 | /* Create all the sysfs files */ |
1204 | gfar_init_sysfs(dev); | |
1205 | ||
1da177e4 | 1206 | /* Print out the device info */ |
59deab26 | 1207 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1208 | |
0977f817 JC |
1209 | /* Even more device info helps when determining which kernel |
1210 | * provided which set of benchmarks. | |
1211 | */ | |
59deab26 | 1212 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1213 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1214 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1215 | i, priv->rx_queue[i]->rx_ring_size); | |
bc4598bc | 1216 | for (i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1217 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1218 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1219 | |
1220 | return 0; | |
1221 | ||
1222 | register_fail: | |
46ceb60c | 1223 | unmap_group_regs(priv); |
fba4ed03 SG |
1224 | free_tx_pointers(priv); |
1225 | free_rx_pointers(priv); | |
fe192a49 GL |
1226 | if (priv->phy_node) |
1227 | of_node_put(priv->phy_node); | |
1228 | if (priv->tbi_node) | |
1229 | of_node_put(priv->tbi_node); | |
1da177e4 | 1230 | free_netdev(dev); |
bb40dcbb | 1231 | return err; |
1da177e4 LT |
1232 | } |
1233 | ||
2dc11581 | 1234 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1235 | { |
b31a1d8b | 1236 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 1237 | |
fe192a49 GL |
1238 | if (priv->phy_node) |
1239 | of_node_put(priv->phy_node); | |
1240 | if (priv->tbi_node) | |
1241 | of_node_put(priv->tbi_node); | |
1242 | ||
b31a1d8b | 1243 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 1244 | |
d9d8e041 | 1245 | unregister_netdev(priv->ndev); |
46ceb60c | 1246 | unmap_group_regs(priv); |
4826857f | 1247 | free_netdev(priv->ndev); |
1da177e4 LT |
1248 | |
1249 | return 0; | |
1250 | } | |
1251 | ||
d87eb127 | 1252 | #ifdef CONFIG_PM |
be926fc4 AV |
1253 | |
1254 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1255 | { |
be926fc4 AV |
1256 | struct gfar_private *priv = dev_get_drvdata(dev); |
1257 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1258 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1259 | unsigned long flags; |
1260 | u32 tempval; | |
1261 | ||
1262 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1263 | (priv->device_flags & |
1264 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1265 | |
be926fc4 | 1266 | netif_device_detach(ndev); |
d87eb127 | 1267 | |
be926fc4 | 1268 | if (netif_running(ndev)) { |
fba4ed03 SG |
1269 | |
1270 | local_irq_save(flags); | |
1271 | lock_tx_qs(priv); | |
1272 | lock_rx_qs(priv); | |
d87eb127 | 1273 | |
be926fc4 | 1274 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1275 | |
1276 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1277 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1278 | |
1279 | tempval &= ~MACCFG1_TX_EN; | |
1280 | ||
1281 | if (!magic_packet) | |
1282 | tempval &= ~MACCFG1_RX_EN; | |
1283 | ||
f4983704 | 1284 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1285 | |
fba4ed03 SG |
1286 | unlock_rx_qs(priv); |
1287 | unlock_tx_qs(priv); | |
1288 | local_irq_restore(flags); | |
d87eb127 | 1289 | |
46ceb60c | 1290 | disable_napi(priv); |
d87eb127 SW |
1291 | |
1292 | if (magic_packet) { | |
1293 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1294 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1295 | |
1296 | /* Enable Magic Packet mode */ | |
f4983704 | 1297 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1298 | tempval |= MACCFG2_MPEN; |
f4983704 | 1299 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1300 | } else { |
1301 | phy_stop(priv->phydev); | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
be926fc4 | 1308 | static int gfar_resume(struct device *dev) |
d87eb127 | 1309 | { |
be926fc4 AV |
1310 | struct gfar_private *priv = dev_get_drvdata(dev); |
1311 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1312 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1313 | unsigned long flags; |
1314 | u32 tempval; | |
1315 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1316 | (priv->device_flags & |
1317 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1318 | |
be926fc4 AV |
1319 | if (!netif_running(ndev)) { |
1320 | netif_device_attach(ndev); | |
d87eb127 SW |
1321 | return 0; |
1322 | } | |
1323 | ||
1324 | if (!magic_packet && priv->phydev) | |
1325 | phy_start(priv->phydev); | |
1326 | ||
1327 | /* Disable Magic Packet mode, in case something | |
1328 | * else woke us up. | |
1329 | */ | |
fba4ed03 SG |
1330 | local_irq_save(flags); |
1331 | lock_tx_qs(priv); | |
1332 | lock_rx_qs(priv); | |
d87eb127 | 1333 | |
f4983704 | 1334 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1335 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1336 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1337 | |
be926fc4 | 1338 | gfar_start(ndev); |
d87eb127 | 1339 | |
fba4ed03 SG |
1340 | unlock_rx_qs(priv); |
1341 | unlock_tx_qs(priv); | |
1342 | local_irq_restore(flags); | |
d87eb127 | 1343 | |
be926fc4 AV |
1344 | netif_device_attach(ndev); |
1345 | ||
46ceb60c | 1346 | enable_napi(priv); |
be926fc4 AV |
1347 | |
1348 | return 0; | |
1349 | } | |
1350 | ||
1351 | static int gfar_restore(struct device *dev) | |
1352 | { | |
1353 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1354 | struct net_device *ndev = priv->ndev; | |
1355 | ||
103cdd1d WD |
1356 | if (!netif_running(ndev)) { |
1357 | netif_device_attach(ndev); | |
1358 | ||
be926fc4 | 1359 | return 0; |
103cdd1d | 1360 | } |
be926fc4 | 1361 | |
1eb8f7a7 CM |
1362 | if (gfar_init_bds(ndev)) { |
1363 | free_skb_resources(priv); | |
1364 | return -ENOMEM; | |
1365 | } | |
1366 | ||
be926fc4 AV |
1367 | init_registers(ndev); |
1368 | gfar_set_mac_address(ndev); | |
1369 | gfar_init_mac(ndev); | |
1370 | gfar_start(ndev); | |
1371 | ||
1372 | priv->oldlink = 0; | |
1373 | priv->oldspeed = 0; | |
1374 | priv->oldduplex = -1; | |
1375 | ||
1376 | if (priv->phydev) | |
1377 | phy_start(priv->phydev); | |
d87eb127 | 1378 | |
be926fc4 | 1379 | netif_device_attach(ndev); |
5ea681d4 | 1380 | enable_napi(priv); |
d87eb127 SW |
1381 | |
1382 | return 0; | |
1383 | } | |
be926fc4 AV |
1384 | |
1385 | static struct dev_pm_ops gfar_pm_ops = { | |
1386 | .suspend = gfar_suspend, | |
1387 | .resume = gfar_resume, | |
1388 | .freeze = gfar_suspend, | |
1389 | .thaw = gfar_resume, | |
1390 | .restore = gfar_restore, | |
1391 | }; | |
1392 | ||
1393 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1394 | ||
d87eb127 | 1395 | #else |
be926fc4 AV |
1396 | |
1397 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1398 | |
d87eb127 | 1399 | #endif |
1da177e4 | 1400 | |
e8a2b6a4 AF |
1401 | /* Reads the controller's registers to determine what interface |
1402 | * connects it to the PHY. | |
1403 | */ | |
1404 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1405 | { | |
1406 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1407 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1408 | u32 ecntrl; |
1409 | ||
f4983704 | 1410 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1411 | |
1412 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1413 | return PHY_INTERFACE_MODE_SGMII; | |
1414 | ||
1415 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1416 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1417 | return PHY_INTERFACE_MODE_RTBI; | |
1418 | else | |
1419 | return PHY_INTERFACE_MODE_TBI; | |
1420 | } | |
1421 | ||
1422 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
bc4598bc | 1423 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) { |
e8a2b6a4 | 1424 | return PHY_INTERFACE_MODE_RMII; |
bc4598bc | 1425 | } |
7132ab7f | 1426 | else { |
b31a1d8b | 1427 | phy_interface_t interface = priv->interface; |
7132ab7f | 1428 | |
0977f817 | 1429 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1430 | * be set by the device tree or platform code. |
1431 | */ | |
1432 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1433 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1434 | ||
e8a2b6a4 | 1435 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1436 | } |
e8a2b6a4 AF |
1437 | } |
1438 | ||
b31a1d8b | 1439 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1440 | return PHY_INTERFACE_MODE_GMII; |
1441 | ||
1442 | return PHY_INTERFACE_MODE_MII; | |
1443 | } | |
1444 | ||
1445 | ||
bb40dcbb AF |
1446 | /* Initializes driver's PHY state, and attaches to the PHY. |
1447 | * Returns 0 on success. | |
1da177e4 LT |
1448 | */ |
1449 | static int init_phy(struct net_device *dev) | |
1450 | { | |
1451 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1452 | uint gigabit_support = |
b31a1d8b | 1453 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 1454 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 1455 | phy_interface_t interface; |
1da177e4 LT |
1456 | |
1457 | priv->oldlink = 0; | |
1458 | priv->oldspeed = 0; | |
1459 | priv->oldduplex = -1; | |
1460 | ||
e8a2b6a4 AF |
1461 | interface = gfar_get_interface(dev); |
1462 | ||
1db780f8 AV |
1463 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1464 | interface); | |
1465 | if (!priv->phydev) | |
1466 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1467 | interface); | |
1468 | if (!priv->phydev) { | |
1469 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1470 | return -ENODEV; | |
fe192a49 | 1471 | } |
1da177e4 | 1472 | |
d3c12873 KJ |
1473 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1474 | gfar_configure_serdes(dev); | |
1475 | ||
bb40dcbb | 1476 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1477 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1478 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1479 | |
1480 | return 0; | |
1da177e4 LT |
1481 | } |
1482 | ||
0977f817 | 1483 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1484 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1485 | * through the MDIO bus on each controller, treating it as a | |
1486 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1487 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1488 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1489 | * value doesn't matter, as there are no other PHYs on the bus. | |
1490 | */ | |
d3c12873 KJ |
1491 | static void gfar_configure_serdes(struct net_device *dev) |
1492 | { | |
1493 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1494 | struct phy_device *tbiphy; |
1495 | ||
1496 | if (!priv->tbi_node) { | |
1497 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1498 | "device tree specify a tbi-handle\n"); | |
1499 | return; | |
1500 | } | |
c132419e | 1501 | |
fe192a49 GL |
1502 | tbiphy = of_phy_find_device(priv->tbi_node); |
1503 | if (!tbiphy) { | |
1504 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1505 | return; |
1506 | } | |
d3c12873 | 1507 | |
0977f817 | 1508 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1509 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1510 | * everything for us? Resetting it takes the link down and requires | |
1511 | * several seconds for it to come back. | |
1512 | */ | |
fe192a49 | 1513 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1514 | return; |
d3c12873 | 1515 | |
d0313587 | 1516 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1517 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1518 | |
fe192a49 | 1519 | phy_write(tbiphy, MII_ADVERTISE, |
bc4598bc JC |
1520 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1521 | ADVERTISE_1000XPSE_ASYM); | |
d3c12873 | 1522 | |
bc4598bc JC |
1523 | phy_write(tbiphy, MII_BMCR, |
1524 | BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | | |
1525 | BMCR_SPEED1000); | |
d3c12873 KJ |
1526 | } |
1527 | ||
1da177e4 LT |
1528 | static void init_registers(struct net_device *dev) |
1529 | { | |
1530 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1531 | struct gfar __iomem *regs = NULL; |
3a2e16c8 | 1532 | int i; |
1da177e4 | 1533 | |
46ceb60c SG |
1534 | for (i = 0; i < priv->num_grps; i++) { |
1535 | regs = priv->gfargrp[i].regs; | |
1536 | /* Clear IEVENT */ | |
1537 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1538 | |
46ceb60c SG |
1539 | /* Initialize IMASK */ |
1540 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1541 | } | |
1da177e4 | 1542 | |
46ceb60c | 1543 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1544 | /* Init hash registers to zero */ |
f4983704 SG |
1545 | gfar_write(®s->igaddr0, 0); |
1546 | gfar_write(®s->igaddr1, 0); | |
1547 | gfar_write(®s->igaddr2, 0); | |
1548 | gfar_write(®s->igaddr3, 0); | |
1549 | gfar_write(®s->igaddr4, 0); | |
1550 | gfar_write(®s->igaddr5, 0); | |
1551 | gfar_write(®s->igaddr6, 0); | |
1552 | gfar_write(®s->igaddr7, 0); | |
1553 | ||
1554 | gfar_write(®s->gaddr0, 0); | |
1555 | gfar_write(®s->gaddr1, 0); | |
1556 | gfar_write(®s->gaddr2, 0); | |
1557 | gfar_write(®s->gaddr3, 0); | |
1558 | gfar_write(®s->gaddr4, 0); | |
1559 | gfar_write(®s->gaddr5, 0); | |
1560 | gfar_write(®s->gaddr6, 0); | |
1561 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1562 | |
1da177e4 | 1563 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1564 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1565 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1566 | |
1567 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1568 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1569 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1570 | } |
1571 | ||
1572 | /* Initialize the max receive buffer length */ | |
f4983704 | 1573 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1574 | |
1da177e4 | 1575 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1576 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1577 | } |
1578 | ||
511d934f AV |
1579 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1580 | { | |
1581 | u32 res; | |
1582 | ||
0977f817 | 1583 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1584 | * actually wait for IEVENT_GRSC flag. |
1585 | */ | |
1586 | if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) | |
1587 | return 0; | |
1588 | ||
0977f817 | 1589 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1590 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1591 | * and the Rx can be safely reset. | |
1592 | */ | |
1593 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1594 | res &= 0x7f807f80; | |
1595 | if ((res & 0xffff) == (res >> 16)) | |
1596 | return 1; | |
1597 | ||
1598 | return 0; | |
1599 | } | |
0bbaf069 KG |
1600 | |
1601 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1602 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1603 | { |
1604 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1605 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1606 | u32 tempval; |
3a2e16c8 | 1607 | int i; |
1da177e4 | 1608 | |
46ceb60c SG |
1609 | for (i = 0; i < priv->num_grps; i++) { |
1610 | regs = priv->gfargrp[i].regs; | |
1611 | /* Mask all interrupts */ | |
1612 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1613 | |
46ceb60c SG |
1614 | /* Clear all interrupts */ |
1615 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1616 | } | |
1da177e4 | 1617 | |
46ceb60c | 1618 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1619 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1620 | tempval = gfar_read(®s->dmactrl); |
bc4598bc JC |
1621 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != |
1622 | (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1623 | int ret; |
1624 | ||
1da177e4 | 1625 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1626 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1627 | |
511d934f AV |
1628 | do { |
1629 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1630 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1631 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1632 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1633 | ret = __gfar_is_rx_idle(priv); | |
1634 | } while (!ret); | |
1da177e4 | 1635 | } |
d87eb127 | 1636 | } |
d87eb127 SW |
1637 | |
1638 | /* Halt the receive and transmit queues */ | |
1639 | void gfar_halt(struct net_device *dev) | |
1640 | { | |
1641 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1642 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1643 | u32 tempval; |
1da177e4 | 1644 | |
2a54adc3 SW |
1645 | gfar_halt_nodisable(dev); |
1646 | ||
1da177e4 LT |
1647 | /* Disable Rx and Tx */ |
1648 | tempval = gfar_read(®s->maccfg1); | |
1649 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1650 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1651 | } |
1652 | ||
46ceb60c SG |
1653 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1654 | { | |
1655 | free_irq(grp->interruptError, grp); | |
1656 | free_irq(grp->interruptTransmit, grp); | |
1657 | free_irq(grp->interruptReceive, grp); | |
1658 | } | |
1659 | ||
0bbaf069 KG |
1660 | void stop_gfar(struct net_device *dev) |
1661 | { | |
1662 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1663 | unsigned long flags; |
46ceb60c | 1664 | int i; |
0bbaf069 | 1665 | |
bb40dcbb AF |
1666 | phy_stop(priv->phydev); |
1667 | ||
a12f801d | 1668 | |
0bbaf069 | 1669 | /* Lock it down */ |
fba4ed03 SG |
1670 | local_irq_save(flags); |
1671 | lock_tx_qs(priv); | |
1672 | lock_rx_qs(priv); | |
0bbaf069 | 1673 | |
0bbaf069 | 1674 | gfar_halt(dev); |
1da177e4 | 1675 | |
fba4ed03 SG |
1676 | unlock_rx_qs(priv); |
1677 | unlock_tx_qs(priv); | |
1678 | local_irq_restore(flags); | |
1da177e4 LT |
1679 | |
1680 | /* Free the IRQs */ | |
b31a1d8b | 1681 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1682 | for (i = 0; i < priv->num_grps; i++) |
1683 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1684 | } else { |
46ceb60c SG |
1685 | for (i = 0; i < priv->num_grps; i++) |
1686 | free_irq(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 1687 | &priv->gfargrp[i]); |
1da177e4 LT |
1688 | } |
1689 | ||
1690 | free_skb_resources(priv); | |
1da177e4 LT |
1691 | } |
1692 | ||
fba4ed03 | 1693 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1694 | { |
1da177e4 | 1695 | struct txbd8 *txbdp; |
fba4ed03 | 1696 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1697 | int i, j; |
1da177e4 | 1698 | |
a12f801d | 1699 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1700 | |
a12f801d SG |
1701 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1702 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1703 | continue; |
1da177e4 | 1704 | |
4826857f | 1705 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
bc4598bc | 1706 | txbdp->length, DMA_TO_DEVICE); |
4669bc90 | 1707 | txbdp->lstatus = 0; |
fba4ed03 | 1708 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
bc4598bc | 1709 | j++) { |
4669bc90 | 1710 | txbdp++; |
4826857f | 1711 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
bc4598bc | 1712 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1713 | } |
ad5da7ab | 1714 | txbdp++; |
a12f801d SG |
1715 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1716 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1717 | } |
a12f801d | 1718 | kfree(tx_queue->tx_skbuff); |
1eb8f7a7 | 1719 | tx_queue->tx_skbuff = NULL; |
fba4ed03 | 1720 | } |
1da177e4 | 1721 | |
fba4ed03 SG |
1722 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1723 | { | |
1724 | struct rxbd8 *rxbdp; | |
1725 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1726 | int i; | |
1da177e4 | 1727 | |
fba4ed03 | 1728 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1729 | |
a12f801d SG |
1730 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1731 | if (rx_queue->rx_skbuff[i]) { | |
fba4ed03 | 1732 | dma_unmap_single(&priv->ofdev->dev, |
bc4598bc JC |
1733 | rxbdp->bufPtr, priv->rx_buffer_size, |
1734 | DMA_FROM_DEVICE); | |
a12f801d SG |
1735 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1736 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1737 | } |
e69edd21 AV |
1738 | rxbdp->lstatus = 0; |
1739 | rxbdp->bufPtr = 0; | |
1740 | rxbdp++; | |
1da177e4 | 1741 | } |
a12f801d | 1742 | kfree(rx_queue->rx_skbuff); |
1eb8f7a7 | 1743 | rx_queue->rx_skbuff = NULL; |
fba4ed03 | 1744 | } |
e69edd21 | 1745 | |
fba4ed03 | 1746 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1747 | * Then free tx_skbuff and rx_skbuff |
1748 | */ | |
fba4ed03 SG |
1749 | static void free_skb_resources(struct gfar_private *priv) |
1750 | { | |
1751 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1752 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1753 | int i; | |
1754 | ||
1755 | /* Go through all the buffer descriptors and free their data buffers */ | |
1756 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1757 | struct netdev_queue *txq; |
bc4598bc | 1758 | |
fba4ed03 | 1759 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1760 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
bc4598bc | 1761 | if (tx_queue->tx_skbuff) |
fba4ed03 | 1762 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1763 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1764 | } |
1765 | ||
1766 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1767 | rx_queue = priv->rx_queue[i]; | |
bc4598bc | 1768 | if (rx_queue->rx_skbuff) |
fba4ed03 SG |
1769 | free_skb_rx_queue(rx_queue); |
1770 | } | |
1771 | ||
1772 | dma_free_coherent(&priv->ofdev->dev, | |
bc4598bc JC |
1773 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
1774 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1775 | priv->tx_queue[0]->tx_bd_base, | |
1776 | priv->tx_queue[0]->tx_bd_dma_base); | |
1da177e4 LT |
1777 | } |
1778 | ||
0bbaf069 KG |
1779 | void gfar_start(struct net_device *dev) |
1780 | { | |
1781 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1782 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1783 | u32 tempval; |
46ceb60c | 1784 | int i = 0; |
0bbaf069 KG |
1785 | |
1786 | /* Enable Rx and Tx in MACCFG1 */ | |
1787 | tempval = gfar_read(®s->maccfg1); | |
1788 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1789 | gfar_write(®s->maccfg1, tempval); | |
1790 | ||
1791 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1792 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1793 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1794 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1795 | |
0bbaf069 | 1796 | /* Make sure we aren't stopped */ |
f4983704 | 1797 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1798 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1799 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1800 | |
46ceb60c SG |
1801 | for (i = 0; i < priv->num_grps; i++) { |
1802 | regs = priv->gfargrp[i].regs; | |
1803 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1804 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1805 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1806 | /* Unmask the interrupts we look for */ | |
1807 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1808 | } | |
12dea57b | 1809 | |
1ae5dc34 | 1810 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1811 | } |
1812 | ||
46ceb60c | 1813 | void gfar_configure_coalescing(struct gfar_private *priv, |
bc4598bc | 1814 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1815 | { |
46ceb60c | 1816 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1817 | u32 __iomem *baddr; |
46ceb60c | 1818 | int i = 0; |
1da177e4 | 1819 | |
46ceb60c SG |
1820 | /* Backward compatible case ---- even if we enable |
1821 | * multiple queues, there's only single reg to program | |
1822 | */ | |
1823 | gfar_write(®s->txic, 0); | |
bc4598bc | 1824 | if (likely(priv->tx_queue[0]->txcoalescing)) |
46ceb60c | 1825 | gfar_write(®s->txic, priv->tx_queue[0]->txic); |
1da177e4 | 1826 | |
46ceb60c | 1827 | gfar_write(®s->rxic, 0); |
bc4598bc | 1828 | if (unlikely(priv->rx_queue[0]->rxcoalescing)) |
46ceb60c | 1829 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); |
815b97c6 | 1830 | |
46ceb60c SG |
1831 | if (priv->mode == MQ_MG_MODE) { |
1832 | baddr = ®s->txic0; | |
984b3f57 | 1833 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
9740e001 CM |
1834 | gfar_write(baddr + i, 0); |
1835 | if (likely(priv->tx_queue[i]->txcoalescing)) | |
46ceb60c | 1836 | gfar_write(baddr + i, priv->tx_queue[i]->txic); |
46ceb60c SG |
1837 | } |
1838 | ||
1839 | baddr = ®s->rxic0; | |
984b3f57 | 1840 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
9740e001 CM |
1841 | gfar_write(baddr + i, 0); |
1842 | if (likely(priv->rx_queue[i]->rxcoalescing)) | |
46ceb60c | 1843 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); |
46ceb60c SG |
1844 | } |
1845 | } | |
1846 | } | |
1847 | ||
1848 | static int register_grp_irqs(struct gfar_priv_grp *grp) | |
1849 | { | |
1850 | struct gfar_private *priv = grp->priv; | |
1851 | struct net_device *dev = priv->ndev; | |
1852 | int err; | |
1da177e4 | 1853 | |
1da177e4 | 1854 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1855 | * them. Otherwise, only register for the one |
1856 | */ | |
b31a1d8b | 1857 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1858 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1859 | * Transmit, and Receive |
1860 | */ | |
bc4598bc JC |
1861 | if ((err = request_irq(grp->interruptError, gfar_error, |
1862 | 0, grp->int_name_er, grp)) < 0) { | |
59deab26 JP |
1863 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1864 | grp->interruptError); | |
46ceb60c | 1865 | |
2145f1af | 1866 | goto err_irq_fail; |
1da177e4 LT |
1867 | } |
1868 | ||
46ceb60c | 1869 | if ((err = request_irq(grp->interruptTransmit, gfar_transmit, |
bc4598bc | 1870 | 0, grp->int_name_tx, grp)) < 0) { |
59deab26 JP |
1871 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1872 | grp->interruptTransmit); | |
1da177e4 LT |
1873 | goto tx_irq_fail; |
1874 | } | |
1875 | ||
bc4598bc JC |
1876 | if ((err = request_irq(grp->interruptReceive, gfar_receive, |
1877 | 0, grp->int_name_rx, grp)) < 0) { | |
59deab26 JP |
1878 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1879 | grp->interruptReceive); | |
1da177e4 LT |
1880 | goto rx_irq_fail; |
1881 | } | |
1882 | } else { | |
bc4598bc JC |
1883 | if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, |
1884 | 0, grp->int_name_tx, grp)) < 0) { | |
59deab26 JP |
1885 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1886 | grp->interruptTransmit); | |
1da177e4 LT |
1887 | goto err_irq_fail; |
1888 | } | |
1889 | } | |
1890 | ||
46ceb60c SG |
1891 | return 0; |
1892 | ||
1893 | rx_irq_fail: | |
1894 | free_irq(grp->interruptTransmit, grp); | |
1895 | tx_irq_fail: | |
1896 | free_irq(grp->interruptError, grp); | |
1897 | err_irq_fail: | |
1898 | return err; | |
1899 | ||
1900 | } | |
1901 | ||
1902 | /* Bring the controller up and running */ | |
1903 | int startup_gfar(struct net_device *ndev) | |
1904 | { | |
1905 | struct gfar_private *priv = netdev_priv(ndev); | |
1906 | struct gfar __iomem *regs = NULL; | |
1907 | int err, i, j; | |
1908 | ||
1909 | for (i = 0; i < priv->num_grps; i++) { | |
1910 | regs= priv->gfargrp[i].regs; | |
1911 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1912 | } | |
1913 | ||
1914 | regs= priv->gfargrp[0].regs; | |
1915 | err = gfar_alloc_skb_resources(ndev); | |
1916 | if (err) | |
1917 | return err; | |
1918 | ||
1919 | gfar_init_mac(ndev); | |
1920 | ||
1921 | for (i = 0; i < priv->num_grps; i++) { | |
1922 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1923 | if (err) { | |
1924 | for (j = 0; j < i; j++) | |
1925 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1926 | goto irq_fail; |
46ceb60c SG |
1927 | } |
1928 | } | |
1929 | ||
7f7f5316 | 1930 | /* Start the controller */ |
ccc05c6e | 1931 | gfar_start(ndev); |
1da177e4 | 1932 | |
826aa4a0 AV |
1933 | phy_start(priv->phydev); |
1934 | ||
46ceb60c SG |
1935 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
1936 | ||
1da177e4 LT |
1937 | return 0; |
1938 | ||
46ceb60c | 1939 | irq_fail: |
e69edd21 | 1940 | free_skb_resources(priv); |
1da177e4 LT |
1941 | return err; |
1942 | } | |
1943 | ||
0977f817 JC |
1944 | /* Called when something needs to use the ethernet device |
1945 | * Returns 0 for success. | |
1946 | */ | |
1da177e4 LT |
1947 | static int gfar_enet_open(struct net_device *dev) |
1948 | { | |
94e8cc35 | 1949 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1950 | int err; |
1951 | ||
46ceb60c | 1952 | enable_napi(priv); |
bea3348e | 1953 | |
1da177e4 LT |
1954 | /* Initialize a bunch of registers */ |
1955 | init_registers(dev); | |
1956 | ||
1957 | gfar_set_mac_address(dev); | |
1958 | ||
1959 | err = init_phy(dev); | |
1960 | ||
a12f801d | 1961 | if (err) { |
46ceb60c | 1962 | disable_napi(priv); |
1da177e4 | 1963 | return err; |
bea3348e | 1964 | } |
1da177e4 LT |
1965 | |
1966 | err = startup_gfar(dev); | |
db0e8e3f | 1967 | if (err) { |
46ceb60c | 1968 | disable_napi(priv); |
db0e8e3f AV |
1969 | return err; |
1970 | } | |
1da177e4 | 1971 | |
fba4ed03 | 1972 | netif_tx_start_all_queues(dev); |
1da177e4 | 1973 | |
2884e5cc AV |
1974 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1975 | ||
1da177e4 LT |
1976 | return err; |
1977 | } | |
1978 | ||
54dc79fe | 1979 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1980 | { |
54dc79fe | 1981 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1982 | |
1983 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1984 | |
0bbaf069 KG |
1985 | return fcb; |
1986 | } | |
1987 | ||
9c4886e5 | 1988 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
bc4598bc | 1989 | int fcb_length) |
0bbaf069 | 1990 | { |
0bbaf069 KG |
1991 | /* If we're here, it's a IP packet with a TCP or UDP |
1992 | * payload. We set it to checksum, using a pseudo-header | |
1993 | * we provide | |
1994 | */ | |
3a2e16c8 | 1995 | u8 flags = TXFCB_DEFAULT; |
0bbaf069 | 1996 | |
0977f817 JC |
1997 | /* Tell the controller what the protocol is |
1998 | * And provide the already calculated phcs | |
1999 | */ | |
eddc9ec5 | 2000 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 2001 | flags |= TXFCB_UDP; |
4bedb452 | 2002 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 2003 | } else |
8da32de5 | 2004 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
2005 | |
2006 | /* l3os is the distance between the start of the | |
2007 | * frame (skb->data) and the start of the IP hdr. | |
2008 | * l4os is the distance between the start of the | |
0977f817 JC |
2009 | * l3 hdr and the l4 hdr |
2010 | */ | |
9c4886e5 | 2011 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 2012 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2013 | |
7f7f5316 | 2014 | fcb->flags = flags; |
0bbaf069 KG |
2015 | } |
2016 | ||
7f7f5316 | 2017 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2018 | { |
7f7f5316 | 2019 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2020 | fcb->vlctl = vlan_tx_tag_get(skb); |
2021 | } | |
2022 | ||
4669bc90 | 2023 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
bc4598bc | 2024 | struct txbd8 *base, int ring_size) |
4669bc90 DH |
2025 | { |
2026 | struct txbd8 *new_bd = bdp + stride; | |
2027 | ||
2028 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2029 | } | |
2030 | ||
2031 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
bc4598bc | 2032 | int ring_size) |
4669bc90 DH |
2033 | { |
2034 | return skip_txbd(bdp, 1, base, ring_size); | |
2035 | } | |
2036 | ||
0977f817 JC |
2037 | /* This is called by the kernel when a frame is ready for transmission. |
2038 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2039 | */ | |
1da177e4 LT |
2040 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2041 | { | |
2042 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2043 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2044 | struct netdev_queue *txq; |
f4983704 | 2045 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2046 | struct txfcb *fcb = NULL; |
f0ee7acf | 2047 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2048 | u32 lstatus; |
f0ee7acf | 2049 | int i, rq = 0, do_tstamp = 0; |
4669bc90 | 2050 | u32 bufaddr; |
fef6108d | 2051 | unsigned long flags; |
9c4886e5 | 2052 | unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN; |
fba4ed03 | 2053 | |
0977f817 | 2054 | /* TOE=1 frames larger than 2500 bytes may see excess delays |
deb90eac AV |
2055 | * before start of transmission. |
2056 | */ | |
2057 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) && | |
bc4598bc JC |
2058 | skb->ip_summed == CHECKSUM_PARTIAL && |
2059 | skb->len > 2500)) { | |
deb90eac AV |
2060 | int ret; |
2061 | ||
2062 | ret = skb_checksum_help(skb); | |
2063 | if (ret) | |
2064 | return ret; | |
2065 | } | |
2066 | ||
fba4ed03 SG |
2067 | rq = skb->queue_mapping; |
2068 | tx_queue = priv->tx_queue[rq]; | |
2069 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2070 | base = tx_queue->tx_bd_base; |
46ceb60c | 2071 | regs = tx_queue->grp->regs; |
f0ee7acf MR |
2072 | |
2073 | /* check if time stamp should be generated */ | |
2244d07b | 2074 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
bc4598bc | 2075 | priv->hwts_tx_en)) { |
f0ee7acf | 2076 | do_tstamp = 1; |
9c4886e5 MR |
2077 | fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
2078 | } | |
4669bc90 | 2079 | |
5b28beaf LY |
2080 | /* make space for additional header when fcb is needed */ |
2081 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
bc4598bc JC |
2082 | vlan_tx_tag_present(skb) || |
2083 | unlikely(do_tstamp)) && | |
2084 | (skb_headroom(skb) < fcb_length)) { | |
54dc79fe SH |
2085 | struct sk_buff *skb_new; |
2086 | ||
9c4886e5 | 2087 | skb_new = skb_realloc_headroom(skb, fcb_length); |
54dc79fe SH |
2088 | if (!skb_new) { |
2089 | dev->stats.tx_errors++; | |
bd14ba84 | 2090 | kfree_skb(skb); |
54dc79fe SH |
2091 | return NETDEV_TX_OK; |
2092 | } | |
db83d136 | 2093 | |
313b037c ED |
2094 | if (skb->sk) |
2095 | skb_set_owner_w(skb_new, skb->sk); | |
2096 | consume_skb(skb); | |
54dc79fe SH |
2097 | skb = skb_new; |
2098 | } | |
2099 | ||
4669bc90 DH |
2100 | /* total number of fragments in the SKB */ |
2101 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2102 | ||
f0ee7acf MR |
2103 | /* calculate the required number of TxBDs for this skb */ |
2104 | if (unlikely(do_tstamp)) | |
2105 | nr_txbds = nr_frags + 2; | |
2106 | else | |
2107 | nr_txbds = nr_frags + 1; | |
2108 | ||
4669bc90 | 2109 | /* check if there is space to queue this packet */ |
f0ee7acf | 2110 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2111 | /* no space, stop the queue */ |
fba4ed03 | 2112 | netif_tx_stop_queue(txq); |
4669bc90 | 2113 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2114 | return NETDEV_TX_BUSY; |
2115 | } | |
1da177e4 LT |
2116 | |
2117 | /* Update transmit stats */ | |
1ac9ad13 ED |
2118 | tx_queue->stats.tx_bytes += skb->len; |
2119 | tx_queue->stats.tx_packets++; | |
1da177e4 | 2120 | |
a12f801d | 2121 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2122 | lstatus = txbdp->lstatus; |
2123 | ||
2124 | /* Time stamp insertion requires one additional TxBD */ | |
2125 | if (unlikely(do_tstamp)) | |
2126 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
bc4598bc | 2127 | tx_queue->tx_ring_size); |
1da177e4 | 2128 | |
4669bc90 | 2129 | if (nr_frags == 0) { |
f0ee7acf MR |
2130 | if (unlikely(do_tstamp)) |
2131 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
bc4598bc | 2132 | TXBD_INTERRUPT); |
f0ee7acf MR |
2133 | else |
2134 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2135 | } else { |
2136 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2137 | for (i = 0; i < nr_frags; i++) { | |
2138 | /* Point at the next BD, wrapping as needed */ | |
a12f801d | 2139 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2140 | |
2141 | length = skb_shinfo(skb)->frags[i].size; | |
2142 | ||
2143 | lstatus = txbdp->lstatus | length | | |
bc4598bc | 2144 | BD_LFLAG(TXBD_READY); |
4669bc90 DH |
2145 | |
2146 | /* Handle the last BD specially */ | |
2147 | if (i == nr_frags - 1) | |
2148 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2149 | |
2234a722 IC |
2150 | bufaddr = skb_frag_dma_map(&priv->ofdev->dev, |
2151 | &skb_shinfo(skb)->frags[i], | |
2152 | 0, | |
2153 | length, | |
2154 | DMA_TO_DEVICE); | |
4669bc90 DH |
2155 | |
2156 | /* set the TxBD length and buffer pointer */ | |
2157 | txbdp->bufPtr = bufaddr; | |
2158 | txbdp->lstatus = lstatus; | |
2159 | } | |
2160 | ||
2161 | lstatus = txbdp_start->lstatus; | |
2162 | } | |
1da177e4 | 2163 | |
9c4886e5 MR |
2164 | /* Add TxPAL between FCB and frame if required */ |
2165 | if (unlikely(do_tstamp)) { | |
2166 | skb_push(skb, GMAC_TXPAL_LEN); | |
2167 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2168 | } | |
2169 | ||
0bbaf069 | 2170 | /* Set up checksumming */ |
12dea57b | 2171 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe | 2172 | fcb = gfar_add_fcb(skb); |
4363c2fd | 2173 | /* as specified by errata */ |
bc4598bc JC |
2174 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) && |
2175 | ((unsigned long)fcb % 0x20) > 0x18)) { | |
4363c2fd AD |
2176 | __skb_pull(skb, GMAC_FCB_LEN); |
2177 | skb_checksum_help(skb); | |
2178 | } else { | |
2179 | lstatus |= BD_LFLAG(TXBD_TOE); | |
9c4886e5 | 2180 | gfar_tx_checksum(skb, fcb, fcb_length); |
4363c2fd | 2181 | } |
0bbaf069 KG |
2182 | } |
2183 | ||
eab6d18d | 2184 | if (vlan_tx_tag_present(skb)) { |
54dc79fe SH |
2185 | if (unlikely(NULL == fcb)) { |
2186 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 2187 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 2188 | } |
54dc79fe SH |
2189 | |
2190 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
2191 | } |
2192 | ||
f0ee7acf MR |
2193 | /* Setup tx hardware time stamping if requested */ |
2194 | if (unlikely(do_tstamp)) { | |
2244d07b | 2195 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf MR |
2196 | if (fcb == NULL) |
2197 | fcb = gfar_add_fcb(skb); | |
2198 | fcb->ptp = 1; | |
2199 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2200 | } | |
2201 | ||
4826857f | 2202 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
bc4598bc | 2203 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2204 | |
0977f817 | 2205 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2206 | * first TxBD points to the FCB and must have a data length of |
2207 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2208 | * the full frame length. | |
2209 | */ | |
2210 | if (unlikely(do_tstamp)) { | |
9c4886e5 | 2211 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length; |
f0ee7acf | 2212 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
bc4598bc | 2213 | (skb_headlen(skb) - fcb_length); |
f0ee7acf MR |
2214 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2215 | } else { | |
2216 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2217 | } | |
1da177e4 | 2218 | |
d8a0f1b0 PG |
2219 | netdev_tx_sent_queue(txq, skb->len); |
2220 | ||
0977f817 | 2221 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2222 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2223 | * when we were reading the num_txbdfree and checking for available | |
2224 | * space, that's because outside of this function it can only grow, | |
2225 | * and once we've got needed space, it cannot suddenly disappear. | |
2226 | * | |
2227 | * The lock also protects us from gfar_error(), which can modify | |
2228 | * regs->tstat and thus retrigger the transfers, which is why we | |
2229 | * also must grab the lock before setting ready bit for the first | |
2230 | * to be transmitted BD. | |
2231 | */ | |
2232 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2233 | ||
0977f817 | 2234 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2235 | * semantics (it requires synchronization between cacheable and |
2236 | * uncacheable mappings, which eieio doesn't provide and which we | |
2237 | * don't need), thus requiring a more expensive sync instruction. At | |
2238 | * some point, the set of architecture-independent barrier functions | |
2239 | * should be expanded to include weaker barriers. | |
2240 | */ | |
3b6330ce | 2241 | eieio(); |
7f7f5316 | 2242 | |
4669bc90 DH |
2243 | txbdp_start->lstatus = lstatus; |
2244 | ||
0eddba52 AV |
2245 | eieio(); /* force lstatus write before tx_skbuff */ |
2246 | ||
2247 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2248 | ||
4669bc90 | 2249 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2250 | * (wrapping if necessary) |
2251 | */ | |
a12f801d | 2252 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
bc4598bc | 2253 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); |
4669bc90 | 2254 | |
a12f801d | 2255 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2256 | |
2257 | /* reduce TxBD free count */ | |
f0ee7acf | 2258 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2259 | |
2260 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2261 | * are full. We need to tell the kernel to stop sending us stuff. |
2262 | */ | |
a12f801d | 2263 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2264 | netif_tx_stop_queue(txq); |
1da177e4 | 2265 | |
09f75cd7 | 2266 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2267 | } |
2268 | ||
1da177e4 | 2269 | /* Tell the DMA to go go go */ |
fba4ed03 | 2270 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2271 | |
2272 | /* Unlock priv */ | |
a12f801d | 2273 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2274 | |
54dc79fe | 2275 | return NETDEV_TX_OK; |
1da177e4 LT |
2276 | } |
2277 | ||
2278 | /* Stops the kernel queue, and halts the controller */ | |
2279 | static int gfar_close(struct net_device *dev) | |
2280 | { | |
2281 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2282 | |
46ceb60c | 2283 | disable_napi(priv); |
bea3348e | 2284 | |
ab939905 | 2285 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2286 | stop_gfar(dev); |
2287 | ||
bb40dcbb AF |
2288 | /* Disconnect from the PHY */ |
2289 | phy_disconnect(priv->phydev); | |
2290 | priv->phydev = NULL; | |
1da177e4 | 2291 | |
fba4ed03 | 2292 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2293 | |
2294 | return 0; | |
2295 | } | |
2296 | ||
1da177e4 | 2297 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2298 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2299 | { |
7f7f5316 | 2300 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2301 | |
2302 | return 0; | |
2303 | } | |
2304 | ||
f3dc1586 SP |
2305 | /* Check if rx parser should be activated */ |
2306 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2307 | { | |
2308 | struct gfar __iomem *regs; | |
2309 | u32 tempval; | |
2310 | ||
2311 | regs = priv->gfargrp[0].regs; | |
2312 | ||
2313 | tempval = gfar_read(®s->rctrl); | |
2314 | /* If parse is no longer required, then disable parser */ | |
2315 | if (tempval & RCTRL_REQ_PARSER) | |
2316 | tempval |= RCTRL_PRSDEP_INIT; | |
2317 | else | |
2318 | tempval &= ~RCTRL_PRSDEP_INIT; | |
2319 | gfar_write(®s->rctrl, tempval); | |
2320 | } | |
2321 | ||
0bbaf069 | 2322 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2323 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2324 | { |
2325 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2326 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2327 | unsigned long flags; |
2328 | u32 tempval; | |
2329 | ||
46ceb60c | 2330 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2331 | local_irq_save(flags); |
2332 | lock_rx_qs(priv); | |
0bbaf069 | 2333 | |
87c288c6 | 2334 | if (features & NETIF_F_HW_VLAN_TX) { |
0bbaf069 | 2335 | /* Enable VLAN tag insertion */ |
f4983704 | 2336 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2337 | tempval |= TCTRL_VLINS; |
f4983704 | 2338 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2339 | } else { |
2340 | /* Disable VLAN tag insertion */ | |
f4983704 | 2341 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2342 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2343 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2344 | } |
0bbaf069 | 2345 | |
87c288c6 JP |
2346 | if (features & NETIF_F_HW_VLAN_RX) { |
2347 | /* Enable VLAN tag extraction */ | |
2348 | tempval = gfar_read(®s->rctrl); | |
2349 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2350 | gfar_write(®s->rctrl, tempval); | |
2351 | } else { | |
0bbaf069 | 2352 | /* Disable VLAN tag extraction */ |
f4983704 | 2353 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2354 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2355 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2356 | |
2357 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2358 | } |
2359 | ||
77ecaf2d DH |
2360 | gfar_change_mtu(dev, dev->mtu); |
2361 | ||
fba4ed03 SG |
2362 | unlock_rx_qs(priv); |
2363 | local_irq_restore(flags); | |
0bbaf069 KG |
2364 | } |
2365 | ||
1da177e4 LT |
2366 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2367 | { | |
2368 | int tempsize, tempval; | |
2369 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2370 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2371 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2372 | int frame_size = new_mtu + ETH_HLEN; |
2373 | ||
87c288c6 | 2374 | if (gfar_is_vlan_on(priv)) |
faa89577 | 2375 | frame_size += VLAN_HLEN; |
0bbaf069 | 2376 | |
1da177e4 | 2377 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2378 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2379 | return -EINVAL; |
2380 | } | |
2381 | ||
77ecaf2d DH |
2382 | if (gfar_uses_fcb(priv)) |
2383 | frame_size += GMAC_FCB_LEN; | |
2384 | ||
2385 | frame_size += priv->padding; | |
2386 | ||
bc4598bc JC |
2387 | tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + |
2388 | INCREMENTAL_BUFFER_SIZE; | |
1da177e4 LT |
2389 | |
2390 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2391 | * stopped, and we changed something |
2392 | */ | |
1da177e4 LT |
2393 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2394 | stop_gfar(dev); | |
2395 | ||
2396 | priv->rx_buffer_size = tempsize; | |
2397 | ||
2398 | dev->mtu = new_mtu; | |
2399 | ||
f4983704 SG |
2400 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2401 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2402 | |
2403 | /* If the mtu is larger than the max size for standard | |
2404 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2405 | * to allow huge frames, and to check the length |
2406 | */ | |
f4983704 | 2407 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2408 | |
7d350977 | 2409 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
bc4598bc | 2410 | gfar_has_errata(priv, GFAR_ERRATA_74)) |
1da177e4 LT |
2411 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2412 | else | |
2413 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2414 | ||
f4983704 | 2415 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2416 | |
2417 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2418 | startup_gfar(dev); | |
2419 | ||
2420 | return 0; | |
2421 | } | |
2422 | ||
ab939905 | 2423 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2424 | * transmitted after a set amount of time. |
2425 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2426 | * starting over will fix the problem. |
2427 | */ | |
2428 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2429 | { |
ab939905 | 2430 | struct gfar_private *priv = container_of(work, struct gfar_private, |
bc4598bc | 2431 | reset_task); |
4826857f | 2432 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2433 | |
2434 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2435 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2436 | stop_gfar(dev); |
2437 | startup_gfar(dev); | |
fba4ed03 | 2438 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2439 | } |
2440 | ||
263ba320 | 2441 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2442 | } |
2443 | ||
ab939905 SS |
2444 | static void gfar_timeout(struct net_device *dev) |
2445 | { | |
2446 | struct gfar_private *priv = netdev_priv(dev); | |
2447 | ||
2448 | dev->stats.tx_errors++; | |
2449 | schedule_work(&priv->reset_task); | |
2450 | } | |
2451 | ||
acbc0f03 EL |
2452 | static void gfar_align_skb(struct sk_buff *skb) |
2453 | { | |
2454 | /* We need the data buffer to be aligned properly. We will reserve | |
2455 | * as many bytes as needed to align the data properly | |
2456 | */ | |
2457 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
bc4598bc | 2458 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); |
acbc0f03 EL |
2459 | } |
2460 | ||
1da177e4 | 2461 | /* Interrupt Handler for Transmit complete */ |
a12f801d | 2462 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2463 | { |
a12f801d | 2464 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2465 | struct netdev_queue *txq; |
d080cd63 | 2466 | struct gfar_private *priv = netdev_priv(dev); |
a12f801d | 2467 | struct gfar_priv_rx_q *rx_queue = NULL; |
f0ee7acf | 2468 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2469 | struct txbd8 *lbdp = NULL; |
a12f801d | 2470 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2471 | struct sk_buff *skb; |
2472 | int skb_dirtytx; | |
a12f801d | 2473 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2474 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2475 | int i; |
d080cd63 | 2476 | int howmany = 0; |
d8a0f1b0 PG |
2477 | int tqi = tx_queue->qindex; |
2478 | unsigned int bytes_sent = 0; | |
4669bc90 | 2479 | u32 lstatus; |
f0ee7acf | 2480 | size_t buflen; |
1da177e4 | 2481 | |
d8a0f1b0 PG |
2482 | rx_queue = priv->rx_queue[tqi]; |
2483 | txq = netdev_get_tx_queue(dev, tqi); | |
a12f801d SG |
2484 | bdp = tx_queue->dirty_tx; |
2485 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2486 | |
a12f801d | 2487 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2488 | unsigned long flags; |
2489 | ||
4669bc90 | 2490 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2491 | |
0977f817 | 2492 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2493 | * Also, we need to dma_unmap_single() the TxPAL. |
2494 | */ | |
2244d07b | 2495 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2496 | nr_txbds = frags + 2; |
2497 | else | |
2498 | nr_txbds = frags + 1; | |
2499 | ||
2500 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2501 | |
4669bc90 | 2502 | lstatus = lbdp->lstatus; |
1da177e4 | 2503 | |
4669bc90 DH |
2504 | /* Only clean completed frames */ |
2505 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
bc4598bc | 2506 | (lstatus & BD_LENGTH_MASK)) |
4669bc90 DH |
2507 | break; |
2508 | ||
2244d07b | 2509 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2510 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2511 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2512 | } else |
2513 | buflen = bdp->length; | |
2514 | ||
2515 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, | |
bc4598bc | 2516 | buflen, DMA_TO_DEVICE); |
f0ee7acf | 2517 | |
2244d07b | 2518 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2519 | struct skb_shared_hwtstamps shhwtstamps; |
2520 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
bc4598bc | 2521 | |
f0ee7acf MR |
2522 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2523 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2524 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2525 | skb_tstamp_tx(skb, &shhwtstamps); |
2526 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2527 | bdp = next; | |
2528 | } | |
81183059 | 2529 | |
4669bc90 DH |
2530 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2531 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2532 | |
4669bc90 | 2533 | for (i = 0; i < frags; i++) { |
bc4598bc JC |
2534 | dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr, |
2535 | bdp->length, DMA_TO_DEVICE); | |
4669bc90 DH |
2536 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2537 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2538 | } | |
1da177e4 | 2539 | |
d8a0f1b0 PG |
2540 | bytes_sent += skb->len; |
2541 | ||
acb600de | 2542 | dev_kfree_skb_any(skb); |
0fd56bb5 | 2543 | |
a12f801d | 2544 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2545 | |
4669bc90 | 2546 | skb_dirtytx = (skb_dirtytx + 1) & |
bc4598bc | 2547 | TX_RING_MOD_MASK(tx_ring_size); |
4669bc90 DH |
2548 | |
2549 | howmany++; | |
a3bc1f11 | 2550 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2551 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2552 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2553 | } |
1da177e4 | 2554 | |
4669bc90 | 2555 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2556 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2557 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2558 | |
4669bc90 | 2559 | /* Update dirty indicators */ |
a12f801d SG |
2560 | tx_queue->skb_dirtytx = skb_dirtytx; |
2561 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2562 | |
d8a0f1b0 PG |
2563 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
2564 | ||
d080cd63 DH |
2565 | return howmany; |
2566 | } | |
2567 | ||
f4983704 | 2568 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2569 | { |
a6d0b91a AV |
2570 | unsigned long flags; |
2571 | ||
fba4ed03 SG |
2572 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2573 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2574 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2575 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2576 | } else { |
0977f817 | 2577 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2578 | * because of the packets that have already arrived. |
2579 | */ | |
f4983704 | 2580 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2581 | } |
fba4ed03 | 2582 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2583 | |
8c7396ae | 2584 | } |
1da177e4 | 2585 | |
8c7396ae | 2586 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2587 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2588 | { |
f4983704 | 2589 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2590 | return IRQ_HANDLED; |
2591 | } | |
2592 | ||
a12f801d | 2593 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 2594 | struct sk_buff *skb) |
815b97c6 | 2595 | { |
a12f801d | 2596 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2597 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2598 | dma_addr_t buf; |
815b97c6 | 2599 | |
8a102fe0 AV |
2600 | buf = dma_map_single(&priv->ofdev->dev, skb->data, |
2601 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
a12f801d | 2602 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2603 | } |
2604 | ||
2281a0f3 | 2605 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2606 | { |
2607 | struct gfar_private *priv = netdev_priv(dev); | |
acb600de | 2608 | struct sk_buff *skb; |
1da177e4 | 2609 | |
acbc0f03 | 2610 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2611 | if (!skb) |
1da177e4 LT |
2612 | return NULL; |
2613 | ||
acbc0f03 | 2614 | gfar_align_skb(skb); |
7f7f5316 | 2615 | |
acbc0f03 EL |
2616 | return skb; |
2617 | } | |
2618 | ||
2281a0f3 | 2619 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 | 2620 | { |
acb600de | 2621 | return gfar_alloc_skb(dev); |
1da177e4 LT |
2622 | } |
2623 | ||
298e1a9e | 2624 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2625 | { |
298e1a9e | 2626 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2627 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2628 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2629 | ||
0977f817 | 2630 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2631 | if (status & RXBD_TRUNCATED) { |
2632 | stats->rx_length_errors++; | |
2633 | ||
2634 | estats->rx_trunc++; | |
2635 | ||
2636 | return; | |
2637 | } | |
2638 | /* Count the errors, if there were any */ | |
2639 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2640 | stats->rx_length_errors++; | |
2641 | ||
2642 | if (status & RXBD_LARGE) | |
2643 | estats->rx_large++; | |
2644 | else | |
2645 | estats->rx_short++; | |
2646 | } | |
2647 | if (status & RXBD_NONOCTET) { | |
2648 | stats->rx_frame_errors++; | |
2649 | estats->rx_nonoctet++; | |
2650 | } | |
2651 | if (status & RXBD_CRCERR) { | |
2652 | estats->rx_crcerr++; | |
2653 | stats->rx_crc_errors++; | |
2654 | } | |
2655 | if (status & RXBD_OVERRUN) { | |
2656 | estats->rx_overrun++; | |
2657 | stats->rx_crc_errors++; | |
2658 | } | |
2659 | } | |
2660 | ||
f4983704 | 2661 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2662 | { |
f4983704 | 2663 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2664 | return IRQ_HANDLED; |
2665 | } | |
2666 | ||
0bbaf069 KG |
2667 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2668 | { | |
2669 | /* If valid headers were found, and valid sums | |
2670 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2671 | * checksumming is necessary. Otherwise, it is [FIXME] |
2672 | */ | |
7f7f5316 | 2673 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2674 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2675 | else | |
bc8acf2c | 2676 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2677 | } |
2678 | ||
2679 | ||
0977f817 | 2680 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
1da177e4 | 2681 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
cd754a57 | 2682 | int amount_pull, struct napi_struct *napi) |
1da177e4 LT |
2683 | { |
2684 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2685 | struct rxfcb *fcb = NULL; |
1da177e4 | 2686 | |
cd754a57 | 2687 | gro_result_t ret; |
1da177e4 | 2688 | |
2c2db48a DH |
2689 | /* fcb is at the beginning if exists */ |
2690 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2691 | |
0977f817 JC |
2692 | /* Remove the FCB from the skb |
2693 | * Remove the padded bytes, if there are any | |
2694 | */ | |
f74dac08 SG |
2695 | if (amount_pull) { |
2696 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2697 | skb_pull(skb, amount_pull); |
f74dac08 | 2698 | } |
0bbaf069 | 2699 | |
cc772ab7 MR |
2700 | /* Get receive timestamp from the skb */ |
2701 | if (priv->hwts_rx_en) { | |
2702 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2703 | u64 *ns = (u64 *) skb->data; | |
bc4598bc | 2704 | |
cc772ab7 MR |
2705 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2706 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2707 | } | |
2708 | ||
2709 | if (priv->padding) | |
2710 | skb_pull(skb, priv->padding); | |
2711 | ||
8b3afe95 | 2712 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2713 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2714 | |
2c2db48a DH |
2715 | /* Tell the skb what kind of packet this is */ |
2716 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2717 | |
0977f817 | 2718 | /* There's need to check for NETIF_F_HW_VLAN_RX here. |
32f7fd44 JP |
2719 | * Even if vlan rx accel is disabled, on some chips |
2720 | * RXFCB_VLN is pseudo randomly set. | |
2721 | */ | |
2722 | if (dev->features & NETIF_F_HW_VLAN_RX && | |
2723 | fcb->flags & RXFCB_VLN) | |
87c288c6 JP |
2724 | __vlan_hwaccel_put_tag(skb, fcb->vlctl); |
2725 | ||
2c2db48a | 2726 | /* Send the packet up the stack */ |
cd754a57 | 2727 | ret = napi_gro_receive(napi, skb); |
0bbaf069 | 2728 | |
cd754a57 | 2729 | if (GRO_DROP == ret) |
2c2db48a | 2730 | priv->extra_stats.kernel_dropped++; |
1da177e4 LT |
2731 | |
2732 | return 0; | |
2733 | } | |
2734 | ||
2735 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2736 | * until the budget/quota has been reached. Returns the number |
2737 | * of frames handled | |
1da177e4 | 2738 | */ |
a12f801d | 2739 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2740 | { |
a12f801d | 2741 | struct net_device *dev = rx_queue->dev; |
31de198b | 2742 | struct rxbd8 *bdp, *base; |
1da177e4 | 2743 | struct sk_buff *skb; |
2c2db48a DH |
2744 | int pkt_len; |
2745 | int amount_pull; | |
1da177e4 LT |
2746 | int howmany = 0; |
2747 | struct gfar_private *priv = netdev_priv(dev); | |
2748 | ||
2749 | /* Get the first full descriptor */ | |
a12f801d SG |
2750 | bdp = rx_queue->cur_rx; |
2751 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2752 | |
cc772ab7 | 2753 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0); |
2c2db48a | 2754 | |
1da177e4 | 2755 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2756 | struct sk_buff *newskb; |
bc4598bc | 2757 | |
3b6330ce | 2758 | rmb(); |
815b97c6 AF |
2759 | |
2760 | /* Add another skb for the future */ | |
2761 | newskb = gfar_new_skb(dev); | |
2762 | ||
a12f801d | 2763 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2764 | |
4826857f | 2765 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
bc4598bc | 2766 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
81183059 | 2767 | |
63b88b90 | 2768 | if (unlikely(!(bdp->status & RXBD_ERR) && |
bc4598bc | 2769 | bdp->length > priv->rx_buffer_size)) |
63b88b90 AV |
2770 | bdp->status = RXBD_LARGE; |
2771 | ||
815b97c6 AF |
2772 | /* We drop the frame if we failed to allocate a new buffer */ |
2773 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
bc4598bc | 2774 | bdp->status & RXBD_ERR)) { |
815b97c6 AF |
2775 | count_errors(bdp->status, dev); |
2776 | ||
2777 | if (unlikely(!newskb)) | |
2778 | newskb = skb; | |
acbc0f03 | 2779 | else if (skb) |
acb600de | 2780 | dev_kfree_skb(skb); |
815b97c6 | 2781 | } else { |
1da177e4 | 2782 | /* Increment the number of packets */ |
a7f38041 | 2783 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2784 | howmany++; |
2785 | ||
2c2db48a DH |
2786 | if (likely(skb)) { |
2787 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2788 | /* Remove the FCS from the packet length */ | |
2789 | skb_put(skb, pkt_len); | |
a7f38041 | 2790 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2791 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 | 2792 | gfar_process_frame(dev, skb, amount_pull, |
bc4598bc | 2793 | &rx_queue->grp->napi); |
2c2db48a DH |
2794 | |
2795 | } else { | |
59deab26 | 2796 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2797 | rx_queue->stats.rx_dropped++; |
2c2db48a DH |
2798 | priv->extra_stats.rx_skbmissing++; |
2799 | } | |
1da177e4 | 2800 | |
1da177e4 LT |
2801 | } |
2802 | ||
a12f801d | 2803 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2804 | |
815b97c6 | 2805 | /* Setup the new bdp */ |
a12f801d | 2806 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2807 | |
2808 | /* Update to the next pointer */ | |
a12f801d | 2809 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2810 | |
2811 | /* update to point at the next skb */ | |
bc4598bc JC |
2812 | rx_queue->skb_currx = (rx_queue->skb_currx + 1) & |
2813 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2814 | } |
2815 | ||
2816 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2817 | rx_queue->cur_rx = bdp; |
1da177e4 | 2818 | |
1da177e4 LT |
2819 | return howmany; |
2820 | } | |
2821 | ||
bea3348e | 2822 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2823 | { |
bc4598bc JC |
2824 | struct gfar_priv_grp *gfargrp = |
2825 | container_of(napi, struct gfar_priv_grp, napi); | |
fba4ed03 | 2826 | struct gfar_private *priv = gfargrp->priv; |
46ceb60c | 2827 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2828 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 SG |
2829 | struct gfar_priv_rx_q *rx_queue = NULL; |
2830 | int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0; | |
18294ad1 AV |
2831 | int tx_cleaned = 0, i, left_over_budget = budget; |
2832 | unsigned long serviced_queues = 0; | |
fba4ed03 | 2833 | int num_queues = 0; |
d080cd63 | 2834 | |
fba4ed03 SG |
2835 | num_queues = gfargrp->num_rx_queues; |
2836 | budget_per_queue = budget/num_queues; | |
2837 | ||
8c7396ae | 2838 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2839 | * because of the packets that have already arrived |
2840 | */ | |
f4983704 | 2841 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2842 | |
fba4ed03 | 2843 | while (num_queues && left_over_budget) { |
fba4ed03 SG |
2844 | budget_per_queue = left_over_budget/num_queues; |
2845 | left_over_budget = 0; | |
2846 | ||
984b3f57 | 2847 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
fba4ed03 SG |
2848 | if (test_bit(i, &serviced_queues)) |
2849 | continue; | |
2850 | rx_queue = priv->rx_queue[i]; | |
2851 | tx_queue = priv->tx_queue[rx_queue->qindex]; | |
2852 | ||
a3bc1f11 | 2853 | tx_cleaned += gfar_clean_tx_ring(tx_queue); |
bc4598bc JC |
2854 | rx_cleaned_per_queue = |
2855 | gfar_clean_rx_ring(rx_queue, budget_per_queue); | |
fba4ed03 | 2856 | rx_cleaned += rx_cleaned_per_queue; |
bc4598bc | 2857 | if (rx_cleaned_per_queue < budget_per_queue) { |
fba4ed03 | 2858 | left_over_budget = left_over_budget + |
bc4598bc JC |
2859 | (budget_per_queue - |
2860 | rx_cleaned_per_queue); | |
fba4ed03 SG |
2861 | set_bit(i, &serviced_queues); |
2862 | num_queues--; | |
2863 | } | |
2864 | } | |
2865 | } | |
1da177e4 | 2866 | |
42199884 AF |
2867 | if (tx_cleaned) |
2868 | return budget; | |
2869 | ||
2870 | if (rx_cleaned < budget) { | |
288379f0 | 2871 | napi_complete(napi); |
1da177e4 LT |
2872 | |
2873 | /* Clear the halt bit in RSTAT */ | |
fba4ed03 | 2874 | gfar_write(®s->rstat, gfargrp->rstat); |
1da177e4 | 2875 | |
f4983704 | 2876 | gfar_write(®s->imask, IMASK_DEFAULT); |
1da177e4 | 2877 | |
0977f817 JC |
2878 | /* If we are coalescing interrupts, update the timer |
2879 | * Otherwise, clear it | |
2880 | */ | |
bc4598bc JC |
2881 | gfar_configure_coalescing(priv, gfargrp->rx_bit_map, |
2882 | gfargrp->tx_bit_map); | |
1da177e4 LT |
2883 | } |
2884 | ||
42199884 | 2885 | return rx_cleaned; |
1da177e4 | 2886 | } |
1da177e4 | 2887 | |
f2d71c2d | 2888 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2889 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2890 | * without having to re-enable interrupts. It's not called while |
2891 | * the interrupt routine is executing. | |
2892 | */ | |
2893 | static void gfar_netpoll(struct net_device *dev) | |
2894 | { | |
2895 | struct gfar_private *priv = netdev_priv(dev); | |
3a2e16c8 | 2896 | int i; |
f2d71c2d VW |
2897 | |
2898 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2899 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
2900 | for (i = 0; i < priv->num_grps; i++) { |
2901 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2902 | disable_irq(priv->gfargrp[i].interruptReceive); | |
2903 | disable_irq(priv->gfargrp[i].interruptError); | |
2904 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 2905 | &priv->gfargrp[i]); |
46ceb60c SG |
2906 | enable_irq(priv->gfargrp[i].interruptError); |
2907 | enable_irq(priv->gfargrp[i].interruptReceive); | |
2908 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
2909 | } | |
f2d71c2d | 2910 | } else { |
46ceb60c SG |
2911 | for (i = 0; i < priv->num_grps; i++) { |
2912 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2913 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 2914 | &priv->gfargrp[i]); |
46ceb60c | 2915 | enable_irq(priv->gfargrp[i].interruptTransmit); |
43de004b | 2916 | } |
f2d71c2d VW |
2917 | } |
2918 | } | |
2919 | #endif | |
2920 | ||
1da177e4 | 2921 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 2922 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 2923 | { |
f4983704 | 2924 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
2925 | |
2926 | /* Save ievent for future reference */ | |
f4983704 | 2927 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 2928 | |
1da177e4 | 2929 | /* Check for reception */ |
538cc7ee | 2930 | if (events & IEVENT_RX_MASK) |
f4983704 | 2931 | gfar_receive(irq, grp_id); |
1da177e4 LT |
2932 | |
2933 | /* Check for transmit completion */ | |
538cc7ee | 2934 | if (events & IEVENT_TX_MASK) |
f4983704 | 2935 | gfar_transmit(irq, grp_id); |
1da177e4 | 2936 | |
538cc7ee SS |
2937 | /* Check for errors */ |
2938 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 2939 | gfar_error(irq, grp_id); |
1da177e4 LT |
2940 | |
2941 | return IRQ_HANDLED; | |
2942 | } | |
2943 | ||
1da177e4 LT |
2944 | /* Called every time the controller might need to be made |
2945 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2946 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2947 | * function converts those variables into the appropriate |
2948 | * register values, and can bring down the device if needed. | |
2949 | */ | |
2950 | static void adjust_link(struct net_device *dev) | |
2951 | { | |
2952 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2953 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
2954 | unsigned long flags; |
2955 | struct phy_device *phydev = priv->phydev; | |
2956 | int new_state = 0; | |
2957 | ||
fba4ed03 SG |
2958 | local_irq_save(flags); |
2959 | lock_tx_qs(priv); | |
2960 | ||
bb40dcbb AF |
2961 | if (phydev->link) { |
2962 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2963 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2964 | |
1da177e4 | 2965 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
2966 | * If not, we operate in half-duplex mode. |
2967 | */ | |
bb40dcbb AF |
2968 | if (phydev->duplex != priv->oldduplex) { |
2969 | new_state = 1; | |
2970 | if (!(phydev->duplex)) | |
1da177e4 | 2971 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2972 | else |
1da177e4 | 2973 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2974 | |
bb40dcbb | 2975 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2976 | } |
2977 | ||
bb40dcbb AF |
2978 | if (phydev->speed != priv->oldspeed) { |
2979 | new_state = 1; | |
2980 | switch (phydev->speed) { | |
1da177e4 | 2981 | case 1000: |
1da177e4 LT |
2982 | tempval = |
2983 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2984 | |
2985 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2986 | break; |
2987 | case 100: | |
2988 | case 10: | |
1da177e4 LT |
2989 | tempval = |
2990 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2991 | |
2992 | /* Reduced mode distinguishes | |
0977f817 JC |
2993 | * between 10 and 100 |
2994 | */ | |
7f7f5316 AF |
2995 | if (phydev->speed == SPEED_100) |
2996 | ecntrl |= ECNTRL_R100; | |
2997 | else | |
2998 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2999 | break; |
3000 | default: | |
59deab26 JP |
3001 | netif_warn(priv, link, dev, |
3002 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
3003 | phydev->speed); | |
1da177e4 LT |
3004 | break; |
3005 | } | |
3006 | ||
bb40dcbb | 3007 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3008 | } |
3009 | ||
bb40dcbb | 3010 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3011 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3012 | |
1da177e4 | 3013 | if (!priv->oldlink) { |
bb40dcbb | 3014 | new_state = 1; |
1da177e4 | 3015 | priv->oldlink = 1; |
1da177e4 | 3016 | } |
bb40dcbb AF |
3017 | } else if (priv->oldlink) { |
3018 | new_state = 1; | |
3019 | priv->oldlink = 0; | |
3020 | priv->oldspeed = 0; | |
3021 | priv->oldduplex = -1; | |
1da177e4 | 3022 | } |
1da177e4 | 3023 | |
bb40dcbb AF |
3024 | if (new_state && netif_msg_link(priv)) |
3025 | phy_print_status(phydev); | |
fba4ed03 SG |
3026 | unlock_tx_qs(priv); |
3027 | local_irq_restore(flags); | |
bb40dcbb | 3028 | } |
1da177e4 LT |
3029 | |
3030 | /* Update the hash table based on the current list of multicast | |
3031 | * addresses we subscribe to. Also, change the promiscuity of | |
3032 | * the device based on the flags (this function is called | |
0977f817 JC |
3033 | * whenever dev->flags is changed |
3034 | */ | |
1da177e4 LT |
3035 | static void gfar_set_multi(struct net_device *dev) |
3036 | { | |
22bedad3 | 3037 | struct netdev_hw_addr *ha; |
1da177e4 | 3038 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3039 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3040 | u32 tempval; |
3041 | ||
a12f801d | 3042 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3043 | /* Set RCTRL to PROM */ |
3044 | tempval = gfar_read(®s->rctrl); | |
3045 | tempval |= RCTRL_PROM; | |
3046 | gfar_write(®s->rctrl, tempval); | |
3047 | } else { | |
3048 | /* Set RCTRL to not PROM */ | |
3049 | tempval = gfar_read(®s->rctrl); | |
3050 | tempval &= ~(RCTRL_PROM); | |
3051 | gfar_write(®s->rctrl, tempval); | |
3052 | } | |
6aa20a22 | 3053 | |
a12f801d | 3054 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3055 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3056 | gfar_write(®s->igaddr0, 0xffffffff); |
3057 | gfar_write(®s->igaddr1, 0xffffffff); | |
3058 | gfar_write(®s->igaddr2, 0xffffffff); | |
3059 | gfar_write(®s->igaddr3, 0xffffffff); | |
3060 | gfar_write(®s->igaddr4, 0xffffffff); | |
3061 | gfar_write(®s->igaddr5, 0xffffffff); | |
3062 | gfar_write(®s->igaddr6, 0xffffffff); | |
3063 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3064 | gfar_write(®s->gaddr0, 0xffffffff); |
3065 | gfar_write(®s->gaddr1, 0xffffffff); | |
3066 | gfar_write(®s->gaddr2, 0xffffffff); | |
3067 | gfar_write(®s->gaddr3, 0xffffffff); | |
3068 | gfar_write(®s->gaddr4, 0xffffffff); | |
3069 | gfar_write(®s->gaddr5, 0xffffffff); | |
3070 | gfar_write(®s->gaddr6, 0xffffffff); | |
3071 | gfar_write(®s->gaddr7, 0xffffffff); | |
3072 | } else { | |
7f7f5316 AF |
3073 | int em_num; |
3074 | int idx; | |
3075 | ||
1da177e4 | 3076 | /* zero out the hash */ |
0bbaf069 KG |
3077 | gfar_write(®s->igaddr0, 0x0); |
3078 | gfar_write(®s->igaddr1, 0x0); | |
3079 | gfar_write(®s->igaddr2, 0x0); | |
3080 | gfar_write(®s->igaddr3, 0x0); | |
3081 | gfar_write(®s->igaddr4, 0x0); | |
3082 | gfar_write(®s->igaddr5, 0x0); | |
3083 | gfar_write(®s->igaddr6, 0x0); | |
3084 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3085 | gfar_write(®s->gaddr0, 0x0); |
3086 | gfar_write(®s->gaddr1, 0x0); | |
3087 | gfar_write(®s->gaddr2, 0x0); | |
3088 | gfar_write(®s->gaddr3, 0x0); | |
3089 | gfar_write(®s->gaddr4, 0x0); | |
3090 | gfar_write(®s->gaddr5, 0x0); | |
3091 | gfar_write(®s->gaddr6, 0x0); | |
3092 | gfar_write(®s->gaddr7, 0x0); | |
3093 | ||
7f7f5316 AF |
3094 | /* If we have extended hash tables, we need to |
3095 | * clear the exact match registers to prepare for | |
0977f817 JC |
3096 | * setting them |
3097 | */ | |
7f7f5316 AF |
3098 | if (priv->extended_hash) { |
3099 | em_num = GFAR_EM_NUM + 1; | |
3100 | gfar_clear_exact_match(dev); | |
3101 | idx = 1; | |
3102 | } else { | |
3103 | idx = 0; | |
3104 | em_num = 0; | |
3105 | } | |
3106 | ||
4cd24eaf | 3107 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3108 | return; |
3109 | ||
3110 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3111 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3112 | if (idx < em_num) { |
22bedad3 | 3113 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3114 | idx++; |
3115 | } else | |
22bedad3 | 3116 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3117 | } |
3118 | } | |
1da177e4 LT |
3119 | } |
3120 | ||
7f7f5316 AF |
3121 | |
3122 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3123 | * don't interfere with normal reception |
3124 | */ | |
7f7f5316 AF |
3125 | static void gfar_clear_exact_match(struct net_device *dev) |
3126 | { | |
3127 | int idx; | |
6a3c910c | 3128 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 | 3129 | |
bc4598bc | 3130 | for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) |
b6bc7650 | 3131 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3132 | } |
3133 | ||
1da177e4 LT |
3134 | /* Set the appropriate hash bit for the given addr */ |
3135 | /* The algorithm works like so: | |
3136 | * 1) Take the Destination Address (ie the multicast address), and | |
3137 | * do a CRC on it (little endian), and reverse the bits of the | |
3138 | * result. | |
3139 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3140 | * table. The table is controlled through 8 32-bit registers: | |
3141 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3142 | * gaddr7. This means that the 3 most significant bits in the | |
3143 | * hash index which gaddr register to use, and the 5 other bits | |
3144 | * indicate which bit (assuming an IBM numbering scheme, which | |
3145 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3146 | * the entry. |
3147 | */ | |
1da177e4 LT |
3148 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3149 | { | |
3150 | u32 tempval; | |
3151 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3152 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3153 | int width = priv->hash_width; |
3154 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3155 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3156 | u32 value = (1 << (31-whichbit)); |
3157 | ||
0bbaf069 | 3158 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3159 | tempval |= value; |
0bbaf069 | 3160 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3161 | } |
3162 | ||
7f7f5316 AF |
3163 | |
3164 | /* There are multiple MAC Address register pairs on some controllers | |
3165 | * This function sets the numth pair to a given address | |
3166 | */ | |
b6bc7650 JP |
3167 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3168 | const u8 *addr) | |
7f7f5316 AF |
3169 | { |
3170 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3171 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3172 | int idx; |
6a3c910c | 3173 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3174 | u32 tempval; |
f4983704 | 3175 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3176 | |
3177 | macptr += num*2; | |
3178 | ||
0977f817 JC |
3179 | /* Now copy it into the mac registers backwards, cuz |
3180 | * little endian is silly | |
3181 | */ | |
6a3c910c JP |
3182 | for (idx = 0; idx < ETH_ALEN; idx++) |
3183 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3184 | |
3185 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3186 | ||
3187 | tempval = *((u32 *) (tmpbuf + 4)); | |
3188 | ||
3189 | gfar_write(macptr+1, tempval); | |
3190 | } | |
3191 | ||
1da177e4 | 3192 | /* GFAR error interrupt handler */ |
f4983704 | 3193 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3194 | { |
f4983704 SG |
3195 | struct gfar_priv_grp *gfargrp = grp_id; |
3196 | struct gfar __iomem *regs = gfargrp->regs; | |
3197 | struct gfar_private *priv= gfargrp->priv; | |
3198 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3199 | |
3200 | /* Save ievent for future reference */ | |
f4983704 | 3201 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3202 | |
3203 | /* Clear IEVENT */ | |
f4983704 | 3204 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3205 | |
3206 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3207 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3208 | (events & IEVENT_MAG)) |
3209 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3210 | |
3211 | /* Hmm... */ | |
0bbaf069 | 3212 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
bc4598bc JC |
3213 | netdev_dbg(dev, |
3214 | "error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
59deab26 | 3215 | events, gfar_read(®s->imask)); |
1da177e4 LT |
3216 | |
3217 | /* Update the error counters */ | |
3218 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3219 | dev->stats.tx_errors++; |
1da177e4 LT |
3220 | |
3221 | if (events & IEVENT_LC) | |
09f75cd7 | 3222 | dev->stats.tx_window_errors++; |
1da177e4 | 3223 | if (events & IEVENT_CRL) |
09f75cd7 | 3224 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3225 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3226 | unsigned long flags; |
3227 | ||
59deab26 JP |
3228 | netif_dbg(priv, tx_err, dev, |
3229 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3230 | dev->stats.tx_dropped++; |
1da177e4 LT |
3231 | priv->extra_stats.tx_underrun++; |
3232 | ||
836cf7fa AV |
3233 | local_irq_save(flags); |
3234 | lock_tx_qs(priv); | |
3235 | ||
1da177e4 | 3236 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3237 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3238 | |
3239 | unlock_tx_qs(priv); | |
3240 | local_irq_restore(flags); | |
1da177e4 | 3241 | } |
59deab26 | 3242 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3243 | } |
3244 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3245 | dev->stats.rx_errors++; |
1da177e4 LT |
3246 | priv->extra_stats.rx_bsy++; |
3247 | ||
f4983704 | 3248 | gfar_receive(irq, grp_id); |
1da177e4 | 3249 | |
59deab26 JP |
3250 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3251 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3252 | } |
3253 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3254 | dev->stats.rx_errors++; |
1da177e4 LT |
3255 | priv->extra_stats.rx_babr++; |
3256 | ||
59deab26 | 3257 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3258 | } |
3259 | if (events & IEVENT_EBERR) { | |
3260 | priv->extra_stats.eberr++; | |
59deab26 | 3261 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3262 | } |
59deab26 JP |
3263 | if (events & IEVENT_RXC) |
3264 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3265 | |
3266 | if (events & IEVENT_BABT) { | |
3267 | priv->extra_stats.tx_babt++; | |
59deab26 | 3268 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3269 | } |
3270 | return IRQ_HANDLED; | |
3271 | } | |
3272 | ||
b31a1d8b AF |
3273 | static struct of_device_id gfar_match[] = |
3274 | { | |
3275 | { | |
3276 | .type = "network", | |
3277 | .compatible = "gianfar", | |
3278 | }, | |
46ceb60c SG |
3279 | { |
3280 | .compatible = "fsl,etsec2", | |
3281 | }, | |
b31a1d8b AF |
3282 | {}, |
3283 | }; | |
e72701ac | 3284 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3285 | |
1da177e4 | 3286 | /* Structure for a device driver */ |
74888760 | 3287 | static struct platform_driver gfar_driver = { |
4018294b GL |
3288 | .driver = { |
3289 | .name = "fsl-gianfar", | |
3290 | .owner = THIS_MODULE, | |
3291 | .pm = GFAR_PM_OPS, | |
3292 | .of_match_table = gfar_match, | |
3293 | }, | |
1da177e4 LT |
3294 | .probe = gfar_probe, |
3295 | .remove = gfar_remove, | |
3296 | }; | |
3297 | ||
db62f684 | 3298 | module_platform_driver(gfar_driver); |