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Commit | Line | Data |
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0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
6c43e046 | 12 | * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/init.h> | |
74 | #include <linux/delay.h> | |
75 | #include <linux/netdevice.h> | |
76 | #include <linux/etherdevice.h> | |
77 | #include <linux/skbuff.h> | |
0bbaf069 | 78 | #include <linux/if_vlan.h> |
1da177e4 LT |
79 | #include <linux/spinlock.h> |
80 | #include <linux/mm.h> | |
fe192a49 | 81 | #include <linux/of_mdio.h> |
b31a1d8b | 82 | #include <linux/of_platform.h> |
0bbaf069 KG |
83 | #include <linux/ip.h> |
84 | #include <linux/tcp.h> | |
85 | #include <linux/udp.h> | |
9c07b884 | 86 | #include <linux/in.h> |
cc772ab7 | 87 | #include <linux/net_tstamp.h> |
1da177e4 LT |
88 | |
89 | #include <asm/io.h> | |
7d350977 | 90 | #include <asm/reg.h> |
1da177e4 LT |
91 | #include <asm/irq.h> |
92 | #include <asm/uaccess.h> | |
93 | #include <linux/module.h> | |
1da177e4 LT |
94 | #include <linux/dma-mapping.h> |
95 | #include <linux/crc32.h> | |
bb40dcbb AF |
96 | #include <linux/mii.h> |
97 | #include <linux/phy.h> | |
b31a1d8b AF |
98 | #include <linux/phy_fixed.h> |
99 | #include <linux/of.h> | |
4b6ba8aa | 100 | #include <linux/of_net.h> |
1da177e4 LT |
101 | |
102 | #include "gianfar.h" | |
1577ecef | 103 | #include "fsl_pq_mdio.h" |
1da177e4 LT |
104 | |
105 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 106 | |
7f7f5316 | 107 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 108 | |
1da177e4 LT |
109 | static int gfar_enet_open(struct net_device *dev); |
110 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 111 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
112 | static void gfar_timeout(struct net_device *dev); |
113 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 114 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 115 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 116 | struct sk_buff *skb); |
1da177e4 LT |
117 | static int gfar_set_mac_address(struct net_device *dev); |
118 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
119 | static irqreturn_t gfar_error(int irq, void *dev_id); |
120 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
121 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
122 | static void adjust_link(struct net_device *dev); |
123 | static void init_registers(struct net_device *dev); | |
124 | static int init_phy(struct net_device *dev); | |
74888760 | 125 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 126 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 127 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
128 | static void gfar_set_multi(struct net_device *dev); |
129 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 130 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 131 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
132 | #ifdef CONFIG_NET_POLL_CONTROLLER |
133 | static void gfar_netpoll(struct net_device *dev); | |
134 | #endif | |
a12f801d SG |
135 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
136 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); | |
2c2db48a | 137 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
cd754a57 | 138 | int amount_pull, struct napi_struct *napi); |
7f7f5316 | 139 | void gfar_halt(struct net_device *dev); |
d87eb127 | 140 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
141 | void gfar_start(struct net_device *dev); |
142 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
143 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
144 | const u8 *addr); | |
26ccfc37 | 145 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 146 | |
1da177e4 LT |
147 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
148 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
149 | MODULE_LICENSE("GPL"); | |
150 | ||
a12f801d | 151 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
152 | dma_addr_t buf) |
153 | { | |
8a102fe0 AV |
154 | u32 lstatus; |
155 | ||
156 | bdp->bufPtr = buf; | |
157 | ||
158 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 159 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
160 | lstatus |= BD_LFLAG(RXBD_WRAP); |
161 | ||
162 | eieio(); | |
163 | ||
164 | bdp->lstatus = lstatus; | |
165 | } | |
166 | ||
8728327e | 167 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 168 | { |
8728327e | 169 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
170 | struct gfar_priv_tx_q *tx_queue = NULL; |
171 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
172 | struct txbd8 *txbdp; |
173 | struct rxbd8 *rxbdp; | |
fba4ed03 | 174 | int i, j; |
a12f801d | 175 | |
fba4ed03 SG |
176 | for (i = 0; i < priv->num_tx_queues; i++) { |
177 | tx_queue = priv->tx_queue[i]; | |
178 | /* Initialize some variables in our dev structure */ | |
179 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
180 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
181 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
182 | tx_queue->skb_curtx = 0; | |
183 | tx_queue->skb_dirtytx = 0; | |
184 | ||
185 | /* Initialize Transmit Descriptor Ring */ | |
186 | txbdp = tx_queue->tx_bd_base; | |
187 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
188 | txbdp->lstatus = 0; | |
189 | txbdp->bufPtr = 0; | |
190 | txbdp++; | |
191 | } | |
8728327e | 192 | |
fba4ed03 SG |
193 | /* Set the last descriptor in the ring to indicate wrap */ |
194 | txbdp--; | |
195 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
196 | } |
197 | ||
fba4ed03 SG |
198 | for (i = 0; i < priv->num_rx_queues; i++) { |
199 | rx_queue = priv->rx_queue[i]; | |
200 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
201 | rx_queue->skb_currx = 0; | |
202 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 203 | |
fba4ed03 SG |
204 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
205 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 206 | |
fba4ed03 SG |
207 | if (skb) { |
208 | gfar_init_rxbdp(rx_queue, rxbdp, | |
209 | rxbdp->bufPtr); | |
210 | } else { | |
211 | skb = gfar_new_skb(ndev); | |
212 | if (!skb) { | |
59deab26 | 213 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
fba4ed03 SG |
214 | goto err_rxalloc_fail; |
215 | } | |
216 | rx_queue->rx_skbuff[j] = skb; | |
217 | ||
218 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 219 | } |
8728327e | 220 | |
fba4ed03 | 221 | rxbdp++; |
8728327e AV |
222 | } |
223 | ||
8728327e AV |
224 | } |
225 | ||
226 | return 0; | |
fba4ed03 SG |
227 | |
228 | err_rxalloc_fail: | |
229 | free_skb_resources(priv); | |
230 | return -ENOMEM; | |
8728327e AV |
231 | } |
232 | ||
233 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
234 | { | |
826aa4a0 | 235 | void *vaddr; |
fba4ed03 SG |
236 | dma_addr_t addr; |
237 | int i, j, k; | |
826aa4a0 AV |
238 | struct gfar_private *priv = netdev_priv(ndev); |
239 | struct device *dev = &priv->ofdev->dev; | |
a12f801d SG |
240 | struct gfar_priv_tx_q *tx_queue = NULL; |
241 | struct gfar_priv_rx_q *rx_queue = NULL; | |
242 | ||
fba4ed03 SG |
243 | priv->total_tx_ring_size = 0; |
244 | for (i = 0; i < priv->num_tx_queues; i++) | |
245 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
246 | ||
247 | priv->total_rx_ring_size = 0; | |
248 | for (i = 0; i < priv->num_rx_queues; i++) | |
249 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
250 | |
251 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 252 | vaddr = dma_alloc_coherent(dev, |
fba4ed03 SG |
253 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
254 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
255 | &addr, GFP_KERNEL); | |
826aa4a0 | 256 | if (!vaddr) { |
59deab26 JP |
257 | netif_err(priv, ifup, ndev, |
258 | "Could not allocate buffer descriptors!\n"); | |
826aa4a0 AV |
259 | return -ENOMEM; |
260 | } | |
261 | ||
fba4ed03 SG |
262 | for (i = 0; i < priv->num_tx_queues; i++) { |
263 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 264 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
265 | tx_queue->tx_bd_dma_base = addr; |
266 | tx_queue->dev = ndev; | |
267 | /* enet DMA only understands physical addresses */ | |
bc4598bc JC |
268 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
269 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 270 | } |
826aa4a0 | 271 | |
826aa4a0 | 272 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
273 | for (i = 0; i < priv->num_rx_queues; i++) { |
274 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 275 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
276 | rx_queue->rx_bd_dma_base = addr; |
277 | rx_queue->dev = ndev; | |
bc4598bc JC |
278 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
279 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 280 | } |
826aa4a0 AV |
281 | |
282 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
283 | for (i = 0; i < priv->num_tx_queues; i++) { |
284 | tx_queue = priv->tx_queue[i]; | |
285 | tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) * | |
bc4598bc JC |
286 | tx_queue->tx_ring_size, |
287 | GFP_KERNEL); | |
fba4ed03 | 288 | if (!tx_queue->tx_skbuff) { |
59deab26 JP |
289 | netif_err(priv, ifup, ndev, |
290 | "Could not allocate tx_skbuff\n"); | |
fba4ed03 SG |
291 | goto cleanup; |
292 | } | |
826aa4a0 | 293 | |
fba4ed03 SG |
294 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
295 | tx_queue->tx_skbuff[k] = NULL; | |
296 | } | |
826aa4a0 | 297 | |
fba4ed03 SG |
298 | for (i = 0; i < priv->num_rx_queues; i++) { |
299 | rx_queue = priv->rx_queue[i]; | |
300 | rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) * | |
bc4598bc JC |
301 | rx_queue->rx_ring_size, |
302 | GFP_KERNEL); | |
826aa4a0 | 303 | |
fba4ed03 | 304 | if (!rx_queue->rx_skbuff) { |
59deab26 JP |
305 | netif_err(priv, ifup, ndev, |
306 | "Could not allocate rx_skbuff\n"); | |
fba4ed03 SG |
307 | goto cleanup; |
308 | } | |
309 | ||
310 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
311 | rx_queue->rx_skbuff[j] = NULL; | |
312 | } | |
826aa4a0 | 313 | |
8728327e AV |
314 | if (gfar_init_bds(ndev)) |
315 | goto cleanup; | |
826aa4a0 AV |
316 | |
317 | return 0; | |
318 | ||
319 | cleanup: | |
320 | free_skb_resources(priv); | |
321 | return -ENOMEM; | |
322 | } | |
323 | ||
fba4ed03 SG |
324 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
325 | { | |
46ceb60c | 326 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 327 | u32 __iomem *baddr; |
fba4ed03 SG |
328 | int i; |
329 | ||
330 | baddr = ®s->tbase0; | |
bc4598bc | 331 | for (i = 0; i < priv->num_tx_queues; i++) { |
fba4ed03 | 332 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); |
bc4598bc | 333 | baddr += 2; |
fba4ed03 SG |
334 | } |
335 | ||
336 | baddr = ®s->rbase0; | |
bc4598bc | 337 | for (i = 0; i < priv->num_rx_queues; i++) { |
fba4ed03 | 338 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); |
bc4598bc | 339 | baddr += 2; |
fba4ed03 SG |
340 | } |
341 | } | |
342 | ||
826aa4a0 AV |
343 | static void gfar_init_mac(struct net_device *ndev) |
344 | { | |
345 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 346 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
347 | u32 rctrl = 0; |
348 | u32 tctrl = 0; | |
349 | u32 attrs = 0; | |
350 | ||
fba4ed03 SG |
351 | /* write the tx/rx base registers */ |
352 | gfar_init_tx_rx_base(priv); | |
32c513bc | 353 | |
826aa4a0 | 354 | /* Configure the coalescing support */ |
46ceb60c | 355 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
fba4ed03 | 356 | |
1ccb8389 | 357 | if (priv->rx_filer_enable) { |
fba4ed03 | 358 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
359 | /* Program the RIR0 reg with the required distribution */ |
360 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
361 | } | |
826aa4a0 | 362 | |
8b3afe95 | 363 | if (ndev->features & NETIF_F_RXCSUM) |
826aa4a0 AV |
364 | rctrl |= RCTRL_CHECKSUMMING; |
365 | ||
366 | if (priv->extended_hash) { | |
367 | rctrl |= RCTRL_EXTHASH; | |
368 | ||
369 | gfar_clear_exact_match(ndev); | |
370 | rctrl |= RCTRL_EMEN; | |
371 | } | |
372 | ||
373 | if (priv->padding) { | |
374 | rctrl &= ~RCTRL_PAL_MASK; | |
375 | rctrl |= RCTRL_PADDING(priv->padding); | |
376 | } | |
377 | ||
cc772ab7 MR |
378 | /* Insert receive time stamps into padding alignment bytes */ |
379 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
380 | rctrl &= ~RCTRL_PAL_MASK; | |
97553f7f | 381 | rctrl |= RCTRL_PADDING(8); |
cc772ab7 MR |
382 | priv->padding = 8; |
383 | } | |
384 | ||
97553f7f MR |
385 | /* Enable HW time stamping if requested from user space */ |
386 | if (priv->hwts_rx_en) | |
387 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; | |
388 | ||
87c288c6 | 389 | if (ndev->features & NETIF_F_HW_VLAN_RX) |
b852b720 | 390 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
826aa4a0 AV |
391 | |
392 | /* Init rctrl based on our settings */ | |
393 | gfar_write(®s->rctrl, rctrl); | |
394 | ||
395 | if (ndev->features & NETIF_F_IP_CSUM) | |
396 | tctrl |= TCTRL_INIT_CSUM; | |
397 | ||
fba4ed03 SG |
398 | tctrl |= TCTRL_TXSCHED_PRIO; |
399 | ||
826aa4a0 AV |
400 | gfar_write(®s->tctrl, tctrl); |
401 | ||
402 | /* Set the extraction length and index */ | |
403 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
404 | ATTRELI_EI(priv->rx_stash_index); | |
405 | ||
406 | gfar_write(®s->attreli, attrs); | |
407 | ||
408 | /* Start with defaults, and add stashing or locking | |
0977f817 JC |
409 | * depending on the approprate variables |
410 | */ | |
826aa4a0 AV |
411 | attrs = ATTR_INIT_SETTINGS; |
412 | ||
413 | if (priv->bd_stash_en) | |
414 | attrs |= ATTR_BDSTASH; | |
415 | ||
416 | if (priv->rx_stash_size != 0) | |
417 | attrs |= ATTR_BUFSTASH; | |
418 | ||
419 | gfar_write(®s->attr, attrs); | |
420 | ||
421 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
422 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
423 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
424 | } | |
425 | ||
a7f38041 SG |
426 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
427 | { | |
428 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
429 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
430 | unsigned long tx_packets = 0, tx_bytes = 0; | |
431 | int i = 0; | |
432 | ||
433 | for (i = 0; i < priv->num_rx_queues; i++) { | |
434 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
bc4598bc | 435 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; |
a7f38041 SG |
436 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; |
437 | } | |
438 | ||
439 | dev->stats.rx_packets = rx_packets; | |
bc4598bc | 440 | dev->stats.rx_bytes = rx_bytes; |
a7f38041 SG |
441 | dev->stats.rx_dropped = rx_dropped; |
442 | ||
443 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
444 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
445 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
446 | } |
447 | ||
bc4598bc | 448 | dev->stats.tx_bytes = tx_bytes; |
a7f38041 SG |
449 | dev->stats.tx_packets = tx_packets; |
450 | ||
451 | return &dev->stats; | |
452 | } | |
453 | ||
26ccfc37 AF |
454 | static const struct net_device_ops gfar_netdev_ops = { |
455 | .ndo_open = gfar_enet_open, | |
456 | .ndo_start_xmit = gfar_start_xmit, | |
457 | .ndo_stop = gfar_close, | |
458 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 459 | .ndo_set_features = gfar_set_features, |
afc4b13d | 460 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
461 | .ndo_tx_timeout = gfar_timeout, |
462 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 463 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
464 | .ndo_set_mac_address = eth_mac_addr, |
465 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
466 | #ifdef CONFIG_NET_POLL_CONTROLLER |
467 | .ndo_poll_controller = gfar_netpoll, | |
468 | #endif | |
469 | }; | |
470 | ||
fba4ed03 SG |
471 | void lock_rx_qs(struct gfar_private *priv) |
472 | { | |
473 | int i = 0x0; | |
474 | ||
475 | for (i = 0; i < priv->num_rx_queues; i++) | |
476 | spin_lock(&priv->rx_queue[i]->rxlock); | |
477 | } | |
478 | ||
479 | void lock_tx_qs(struct gfar_private *priv) | |
480 | { | |
481 | int i = 0x0; | |
482 | ||
483 | for (i = 0; i < priv->num_tx_queues; i++) | |
484 | spin_lock(&priv->tx_queue[i]->txlock); | |
485 | } | |
486 | ||
487 | void unlock_rx_qs(struct gfar_private *priv) | |
488 | { | |
489 | int i = 0x0; | |
490 | ||
491 | for (i = 0; i < priv->num_rx_queues; i++) | |
492 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
493 | } | |
494 | ||
495 | void unlock_tx_qs(struct gfar_private *priv) | |
496 | { | |
497 | int i = 0x0; | |
498 | ||
499 | for (i = 0; i < priv->num_tx_queues; i++) | |
500 | spin_unlock(&priv->tx_queue[i]->txlock); | |
501 | } | |
502 | ||
87c288c6 JP |
503 | static bool gfar_is_vlan_on(struct gfar_private *priv) |
504 | { | |
505 | return (priv->ndev->features & NETIF_F_HW_VLAN_RX) || | |
506 | (priv->ndev->features & NETIF_F_HW_VLAN_TX); | |
507 | } | |
508 | ||
7f7f5316 AF |
509 | /* Returns 1 if incoming frames use an FCB */ |
510 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 511 | { |
87c288c6 | 512 | return gfar_is_vlan_on(priv) || |
bc4598bc JC |
513 | (priv->ndev->features & NETIF_F_RXCSUM) || |
514 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER); | |
0bbaf069 | 515 | } |
bb40dcbb | 516 | |
fba4ed03 SG |
517 | static void free_tx_pointers(struct gfar_private *priv) |
518 | { | |
519 | int i = 0; | |
520 | ||
521 | for (i = 0; i < priv->num_tx_queues; i++) | |
522 | kfree(priv->tx_queue[i]); | |
523 | } | |
524 | ||
525 | static void free_rx_pointers(struct gfar_private *priv) | |
526 | { | |
527 | int i = 0; | |
528 | ||
529 | for (i = 0; i < priv->num_rx_queues; i++) | |
530 | kfree(priv->rx_queue[i]); | |
531 | } | |
532 | ||
46ceb60c SG |
533 | static void unmap_group_regs(struct gfar_private *priv) |
534 | { | |
535 | int i = 0; | |
536 | ||
537 | for (i = 0; i < MAXGROUPS; i++) | |
538 | if (priv->gfargrp[i].regs) | |
539 | iounmap(priv->gfargrp[i].regs); | |
540 | } | |
541 | ||
542 | static void disable_napi(struct gfar_private *priv) | |
543 | { | |
544 | int i = 0; | |
545 | ||
546 | for (i = 0; i < priv->num_grps; i++) | |
547 | napi_disable(&priv->gfargrp[i].napi); | |
548 | } | |
549 | ||
550 | static void enable_napi(struct gfar_private *priv) | |
551 | { | |
552 | int i = 0; | |
553 | ||
554 | for (i = 0; i < priv->num_grps; i++) | |
555 | napi_enable(&priv->gfargrp[i].napi); | |
556 | } | |
557 | ||
558 | static int gfar_parse_group(struct device_node *np, | |
bc4598bc | 559 | struct gfar_private *priv, const char *model) |
46ceb60c SG |
560 | { |
561 | u32 *queue_mask; | |
46ceb60c | 562 | |
7ce97d4f | 563 | priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0); |
46ceb60c SG |
564 | if (!priv->gfargrp[priv->num_grps].regs) |
565 | return -ENOMEM; | |
566 | ||
567 | priv->gfargrp[priv->num_grps].interruptTransmit = | |
568 | irq_of_parse_and_map(np, 0); | |
569 | ||
570 | /* If we aren't the FEC we have multiple interrupts */ | |
571 | if (model && strcasecmp(model, "FEC")) { | |
572 | priv->gfargrp[priv->num_grps].interruptReceive = | |
573 | irq_of_parse_and_map(np, 1); | |
574 | priv->gfargrp[priv->num_grps].interruptError = | |
575 | irq_of_parse_and_map(np,2); | |
28cb6ccd NK |
576 | if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ || |
577 | priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ || | |
578 | priv->gfargrp[priv->num_grps].interruptError == NO_IRQ) | |
46ceb60c | 579 | return -EINVAL; |
46ceb60c SG |
580 | } |
581 | ||
582 | priv->gfargrp[priv->num_grps].grp_id = priv->num_grps; | |
583 | priv->gfargrp[priv->num_grps].priv = priv; | |
584 | spin_lock_init(&priv->gfargrp[priv->num_grps].grplock); | |
bc4598bc JC |
585 | if (priv->mode == MQ_MG_MODE) { |
586 | queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); | |
587 | priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ? | |
588 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); | |
589 | queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); | |
590 | priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ? | |
591 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); | |
46ceb60c SG |
592 | } else { |
593 | priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF; | |
594 | priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF; | |
595 | } | |
596 | priv->num_grps++; | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
2dc11581 | 601 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 602 | { |
b31a1d8b AF |
603 | const char *model; |
604 | const char *ctype; | |
605 | const void *mac_addr; | |
fba4ed03 SG |
606 | int err = 0, i; |
607 | struct net_device *dev = NULL; | |
608 | struct gfar_private *priv = NULL; | |
61c7a080 | 609 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 610 | struct device_node *child = NULL; |
4d7902f2 AF |
611 | const u32 *stash; |
612 | const u32 *stash_len; | |
613 | const u32 *stash_idx; | |
fba4ed03 SG |
614 | unsigned int num_tx_qs, num_rx_qs; |
615 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
616 | |
617 | if (!np || !of_device_is_available(np)) | |
618 | return -ENODEV; | |
619 | ||
fba4ed03 SG |
620 | /* parse the num of tx and rx queues */ |
621 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
622 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
623 | ||
624 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
625 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
626 | num_tx_qs, MAX_TX_QS); | |
627 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
628 | return -EINVAL; |
629 | } | |
630 | ||
631 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
632 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
633 | ||
634 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
635 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
636 | num_rx_qs, MAX_RX_QS); | |
637 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
638 | return -EINVAL; |
639 | } | |
640 | ||
641 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
642 | dev = *pdev; | |
643 | if (NULL == dev) | |
644 | return -ENOMEM; | |
645 | ||
646 | priv = netdev_priv(dev); | |
61c7a080 | 647 | priv->node = ofdev->dev.of_node; |
fba4ed03 SG |
648 | priv->ndev = dev; |
649 | ||
fba4ed03 | 650 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 651 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 652 | priv->num_rx_queues = num_rx_qs; |
46ceb60c | 653 | priv->num_grps = 0x0; |
b31a1d8b | 654 | |
0977f817 | 655 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
656 | INIT_LIST_HEAD(&priv->rx_list.list); |
657 | priv->rx_list.count = 0; | |
658 | mutex_init(&priv->rx_queue_access); | |
659 | ||
b31a1d8b AF |
660 | model = of_get_property(np, "model", NULL); |
661 | ||
46ceb60c SG |
662 | for (i = 0; i < MAXGROUPS; i++) |
663 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 664 | |
46ceb60c SG |
665 | /* Parse and initialize group specific information */ |
666 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
667 | priv->mode = MQ_MG_MODE; | |
668 | for_each_child_of_node(np, child) { | |
669 | err = gfar_parse_group(child, priv, model); | |
670 | if (err) | |
671 | goto err_grp_init; | |
b31a1d8b | 672 | } |
46ceb60c SG |
673 | } else { |
674 | priv->mode = SQ_SG_MODE; | |
675 | err = gfar_parse_group(np, priv, model); | |
bc4598bc | 676 | if (err) |
46ceb60c | 677 | goto err_grp_init; |
b31a1d8b AF |
678 | } |
679 | ||
fba4ed03 SG |
680 | for (i = 0; i < priv->num_tx_queues; i++) |
681 | priv->tx_queue[i] = NULL; | |
682 | for (i = 0; i < priv->num_rx_queues; i++) | |
683 | priv->rx_queue[i] = NULL; | |
684 | ||
685 | for (i = 0; i < priv->num_tx_queues; i++) { | |
de47f072 JP |
686 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), |
687 | GFP_KERNEL); | |
fba4ed03 SG |
688 | if (!priv->tx_queue[i]) { |
689 | err = -ENOMEM; | |
690 | goto tx_alloc_failed; | |
691 | } | |
692 | priv->tx_queue[i]->tx_skbuff = NULL; | |
693 | priv->tx_queue[i]->qindex = i; | |
694 | priv->tx_queue[i]->dev = dev; | |
695 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
696 | } | |
697 | ||
698 | for (i = 0; i < priv->num_rx_queues; i++) { | |
de47f072 JP |
699 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), |
700 | GFP_KERNEL); | |
fba4ed03 SG |
701 | if (!priv->rx_queue[i]) { |
702 | err = -ENOMEM; | |
703 | goto rx_alloc_failed; | |
704 | } | |
705 | priv->rx_queue[i]->rx_skbuff = NULL; | |
706 | priv->rx_queue[i]->qindex = i; | |
707 | priv->rx_queue[i]->dev = dev; | |
708 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
709 | } | |
710 | ||
711 | ||
4d7902f2 AF |
712 | stash = of_get_property(np, "bd-stash", NULL); |
713 | ||
a12f801d | 714 | if (stash) { |
4d7902f2 AF |
715 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
716 | priv->bd_stash_en = 1; | |
717 | } | |
718 | ||
719 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
720 | ||
721 | if (stash_len) | |
722 | priv->rx_stash_size = *stash_len; | |
723 | ||
724 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
725 | ||
726 | if (stash_idx) | |
727 | priv->rx_stash_index = *stash_idx; | |
728 | ||
729 | if (stash_len || stash_idx) | |
730 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
731 | ||
b31a1d8b | 732 | mac_addr = of_get_mac_address(np); |
bc4598bc | 733 | |
b31a1d8b | 734 | if (mac_addr) |
6a3c910c | 735 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
736 | |
737 | if (model && !strcasecmp(model, "TSEC")) | |
bc4598bc JC |
738 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
739 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
740 | FSL_GIANFAR_DEV_HAS_RMON | | |
741 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
742 | ||
b31a1d8b | 743 | if (model && !strcasecmp(model, "eTSEC")) |
bc4598bc JC |
744 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
745 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
746 | FSL_GIANFAR_DEV_HAS_RMON | | |
747 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
748 | FSL_GIANFAR_DEV_HAS_PADDING | | |
749 | FSL_GIANFAR_DEV_HAS_CSUM | | |
750 | FSL_GIANFAR_DEV_HAS_VLAN | | |
751 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
752 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | | |
753 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
754 | |
755 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
756 | ||
757 | /* We only care about rgmii-id. The rest are autodetected */ | |
758 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
759 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
760 | else | |
761 | priv->interface = PHY_INTERFACE_MODE_MII; | |
762 | ||
763 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
764 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
765 | ||
fe192a49 | 766 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
767 | |
768 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 769 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
770 | |
771 | return 0; | |
772 | ||
fba4ed03 SG |
773 | rx_alloc_failed: |
774 | free_rx_pointers(priv); | |
775 | tx_alloc_failed: | |
776 | free_tx_pointers(priv); | |
46ceb60c SG |
777 | err_grp_init: |
778 | unmap_group_regs(priv); | |
fba4ed03 | 779 | free_netdev(dev); |
b31a1d8b AF |
780 | return err; |
781 | } | |
782 | ||
cc772ab7 | 783 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
bc4598bc | 784 | struct ifreq *ifr, int cmd) |
cc772ab7 MR |
785 | { |
786 | struct hwtstamp_config config; | |
787 | struct gfar_private *priv = netdev_priv(netdev); | |
788 | ||
789 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
790 | return -EFAULT; | |
791 | ||
792 | /* reserved for future extensions */ | |
793 | if (config.flags) | |
794 | return -EINVAL; | |
795 | ||
f0ee7acf MR |
796 | switch (config.tx_type) { |
797 | case HWTSTAMP_TX_OFF: | |
798 | priv->hwts_tx_en = 0; | |
799 | break; | |
800 | case HWTSTAMP_TX_ON: | |
801 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
802 | return -ERANGE; | |
803 | priv->hwts_tx_en = 1; | |
804 | break; | |
805 | default: | |
cc772ab7 | 806 | return -ERANGE; |
f0ee7acf | 807 | } |
cc772ab7 MR |
808 | |
809 | switch (config.rx_filter) { | |
810 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
811 | if (priv->hwts_rx_en) { |
812 | stop_gfar(netdev); | |
813 | priv->hwts_rx_en = 0; | |
814 | startup_gfar(netdev); | |
815 | } | |
cc772ab7 MR |
816 | break; |
817 | default: | |
818 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
819 | return -ERANGE; | |
97553f7f MR |
820 | if (!priv->hwts_rx_en) { |
821 | stop_gfar(netdev); | |
822 | priv->hwts_rx_en = 1; | |
823 | startup_gfar(netdev); | |
824 | } | |
cc772ab7 MR |
825 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
826 | break; | |
827 | } | |
828 | ||
829 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
830 | -EFAULT : 0; | |
831 | } | |
832 | ||
0faac9f7 CW |
833 | /* Ioctl MII Interface */ |
834 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
835 | { | |
836 | struct gfar_private *priv = netdev_priv(dev); | |
837 | ||
838 | if (!netif_running(dev)) | |
839 | return -EINVAL; | |
840 | ||
cc772ab7 MR |
841 | if (cmd == SIOCSHWTSTAMP) |
842 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
843 | ||
0faac9f7 CW |
844 | if (!priv->phydev) |
845 | return -ENODEV; | |
846 | ||
28b04113 | 847 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
848 | } |
849 | ||
fba4ed03 SG |
850 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
851 | { | |
852 | unsigned int new_bit_map = 0x0; | |
853 | int mask = 0x1 << (max_qs - 1), i; | |
bc4598bc | 854 | |
fba4ed03 SG |
855 | for (i = 0; i < max_qs; i++) { |
856 | if (bit_map & mask) | |
857 | new_bit_map = new_bit_map + (1 << i); | |
858 | mask = mask >> 0x1; | |
859 | } | |
860 | return new_bit_map; | |
861 | } | |
7a8b3372 | 862 | |
18294ad1 AV |
863 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
864 | u32 class) | |
7a8b3372 SG |
865 | { |
866 | u32 rqfpr = FPR_FILER_MASK; | |
867 | u32 rqfcr = 0x0; | |
868 | ||
869 | rqfar--; | |
870 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
871 | priv->ftp_rqfpr[rqfar] = rqfpr; |
872 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
873 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
874 | ||
875 | rqfar--; | |
876 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
877 | priv->ftp_rqfpr[rqfar] = rqfpr; |
878 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
879 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
880 | ||
881 | rqfar--; | |
882 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
883 | rqfpr = class; | |
6c43e046 WJB |
884 | priv->ftp_rqfcr[rqfar] = rqfcr; |
885 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
886 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
887 | ||
888 | rqfar--; | |
889 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
890 | rqfpr = class; | |
6c43e046 WJB |
891 | priv->ftp_rqfcr[rqfar] = rqfcr; |
892 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
893 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
894 | ||
895 | return rqfar; | |
896 | } | |
897 | ||
898 | static void gfar_init_filer_table(struct gfar_private *priv) | |
899 | { | |
900 | int i = 0x0; | |
901 | u32 rqfar = MAX_FILER_IDX; | |
902 | u32 rqfcr = 0x0; | |
903 | u32 rqfpr = FPR_FILER_MASK; | |
904 | ||
905 | /* Default rule */ | |
906 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
907 | priv->ftp_rqfcr[rqfar] = rqfcr; |
908 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
909 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
910 | ||
911 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
912 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
913 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
914 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
915 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
916 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
917 | ||
85dd08eb | 918 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
919 | priv->cur_filer_idx = rqfar; |
920 | ||
921 | /* Rest are masked rules */ | |
922 | rqfcr = RQFCR_CMP_NOMATCH; | |
923 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
924 | priv->ftp_rqfcr[i] = rqfcr; |
925 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
926 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
927 | } | |
928 | } | |
929 | ||
7d350977 AV |
930 | static void gfar_detect_errata(struct gfar_private *priv) |
931 | { | |
932 | struct device *dev = &priv->ofdev->dev; | |
933 | unsigned int pvr = mfspr(SPRN_PVR); | |
934 | unsigned int svr = mfspr(SPRN_SVR); | |
935 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
936 | unsigned int rev = svr & 0xffff; | |
937 | ||
938 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
939 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
bc4598bc | 940 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
7d350977 AV |
941 | priv->errata |= GFAR_ERRATA_74; |
942 | ||
deb90eac AV |
943 | /* MPC8313 and MPC837x all rev */ |
944 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 945 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
deb90eac AV |
946 | priv->errata |= GFAR_ERRATA_76; |
947 | ||
511d934f AV |
948 | /* MPC8313 and MPC837x all rev */ |
949 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 950 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
511d934f AV |
951 | priv->errata |= GFAR_ERRATA_A002; |
952 | ||
4363c2fd AD |
953 | /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ |
954 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || | |
bc4598bc | 955 | (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) |
4363c2fd AD |
956 | priv->errata |= GFAR_ERRATA_12; |
957 | ||
7d350977 AV |
958 | if (priv->errata) |
959 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
960 | priv->errata); | |
961 | } | |
962 | ||
bb40dcbb | 963 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
964 | * and anything else we need before we start |
965 | */ | |
74888760 | 966 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 LT |
967 | { |
968 | u32 tempval; | |
969 | struct net_device *dev = NULL; | |
970 | struct gfar_private *priv = NULL; | |
f4983704 | 971 | struct gfar __iomem *regs = NULL; |
46ceb60c | 972 | int err = 0, i, grp_idx = 0; |
fba4ed03 | 973 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 974 | u32 isrg = 0; |
18294ad1 | 975 | u32 __iomem *baddr; |
1da177e4 | 976 | |
fba4ed03 | 977 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 978 | |
fba4ed03 SG |
979 | if (err) |
980 | return err; | |
1da177e4 LT |
981 | |
982 | priv = netdev_priv(dev); | |
4826857f KG |
983 | priv->ndev = dev; |
984 | priv->ofdev = ofdev; | |
61c7a080 | 985 | priv->node = ofdev->dev.of_node; |
4826857f | 986 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 987 | |
d87eb127 | 988 | spin_lock_init(&priv->bflock); |
ab939905 | 989 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 990 | |
b31a1d8b | 991 | dev_set_drvdata(&ofdev->dev, priv); |
46ceb60c | 992 | regs = priv->gfargrp[0].regs; |
1da177e4 | 993 | |
7d350977 AV |
994 | gfar_detect_errata(priv); |
995 | ||
0977f817 JC |
996 | /* Stop the DMA engine now, in case it was running before |
997 | * (The firmware could have used it, and left it running). | |
998 | */ | |
257d938a | 999 | gfar_halt(dev); |
1da177e4 LT |
1000 | |
1001 | /* Reset MAC layer */ | |
f4983704 | 1002 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 1003 | |
b98ac702 AF |
1004 | /* We need to delay at least 3 TX clocks */ |
1005 | udelay(2); | |
1006 | ||
1da177e4 | 1007 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
f4983704 | 1008 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
1009 | |
1010 | /* Initialize MACCFG2. */ | |
7d350977 AV |
1011 | tempval = MACCFG2_INIT_SETTINGS; |
1012 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1013 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1014 | gfar_write(®s->maccfg2, tempval); | |
1da177e4 LT |
1015 | |
1016 | /* Initialize ECNTRL */ | |
f4983704 | 1017 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 1018 | |
1da177e4 | 1019 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 1020 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 1021 | |
b31a1d8b | 1022 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
1023 | |
1024 | /* Fill in the dev structure */ | |
1da177e4 | 1025 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1026 | dev->mtu = 1500; |
26ccfc37 | 1027 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1028 | dev->ethtool_ops = &gfar_ethtool_ops; |
1029 | ||
fba4ed03 | 1030 | /* Register for napi ...We are registering NAPI for each grp */ |
46ceb60c | 1031 | for (i = 0; i < priv->num_grps; i++) |
bc4598bc JC |
1032 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, |
1033 | GFAR_DEV_WEIGHT); | |
a12f801d | 1034 | |
b31a1d8b | 1035 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 | 1036 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1037 | NETIF_F_RXCSUM; |
8b3afe95 | 1038 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1039 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; |
8b3afe95 | 1040 | } |
0bbaf069 | 1041 | |
87c288c6 JP |
1042 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
1043 | dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
0bbaf069 | 1044 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
87c288c6 | 1045 | } |
0bbaf069 | 1046 | |
b31a1d8b | 1047 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
1048 | priv->extended_hash = 1; |
1049 | priv->hash_width = 9; | |
1050 | ||
f4983704 SG |
1051 | priv->hash_regs[0] = ®s->igaddr0; |
1052 | priv->hash_regs[1] = ®s->igaddr1; | |
1053 | priv->hash_regs[2] = ®s->igaddr2; | |
1054 | priv->hash_regs[3] = ®s->igaddr3; | |
1055 | priv->hash_regs[4] = ®s->igaddr4; | |
1056 | priv->hash_regs[5] = ®s->igaddr5; | |
1057 | priv->hash_regs[6] = ®s->igaddr6; | |
1058 | priv->hash_regs[7] = ®s->igaddr7; | |
1059 | priv->hash_regs[8] = ®s->gaddr0; | |
1060 | priv->hash_regs[9] = ®s->gaddr1; | |
1061 | priv->hash_regs[10] = ®s->gaddr2; | |
1062 | priv->hash_regs[11] = ®s->gaddr3; | |
1063 | priv->hash_regs[12] = ®s->gaddr4; | |
1064 | priv->hash_regs[13] = ®s->gaddr5; | |
1065 | priv->hash_regs[14] = ®s->gaddr6; | |
1066 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1067 | |
1068 | } else { | |
1069 | priv->extended_hash = 0; | |
1070 | priv->hash_width = 8; | |
1071 | ||
f4983704 SG |
1072 | priv->hash_regs[0] = ®s->gaddr0; |
1073 | priv->hash_regs[1] = ®s->gaddr1; | |
1074 | priv->hash_regs[2] = ®s->gaddr2; | |
1075 | priv->hash_regs[3] = ®s->gaddr3; | |
1076 | priv->hash_regs[4] = ®s->gaddr4; | |
1077 | priv->hash_regs[5] = ®s->gaddr5; | |
1078 | priv->hash_regs[6] = ®s->gaddr6; | |
1079 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1080 | } |
1081 | ||
b31a1d8b | 1082 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1083 | priv->padding = DEFAULT_PADDING; |
1084 | else | |
1085 | priv->padding = 0; | |
1086 | ||
cc772ab7 | 1087 | if (dev->features & NETIF_F_IP_CSUM || |
bc4598bc | 1088 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) |
bee9e58c | 1089 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 | 1090 | |
46ceb60c SG |
1091 | /* Program the isrg regs only if number of grps > 1 */ |
1092 | if (priv->num_grps > 1) { | |
1093 | baddr = ®s->isrg0; | |
1094 | for (i = 0; i < priv->num_grps; i++) { | |
1095 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1096 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1097 | gfar_write(baddr, isrg); | |
1098 | baddr++; | |
1099 | isrg = 0x0; | |
1100 | } | |
1101 | } | |
1102 | ||
fba4ed03 | 1103 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1104 | * but, for_each_set_bit parses from right to left, which |
0977f817 JC |
1105 | * basically reverses the queue numbers |
1106 | */ | |
46ceb60c | 1107 | for (i = 0; i< priv->num_grps; i++) { |
bc4598bc JC |
1108 | priv->gfargrp[i].tx_bit_map = |
1109 | reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1110 | priv->gfargrp[i].rx_bit_map = | |
1111 | reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
46ceb60c SG |
1112 | } |
1113 | ||
1114 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
0977f817 JC |
1115 | * also assign queues to groups |
1116 | */ | |
46ceb60c SG |
1117 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { |
1118 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
bc4598bc | 1119 | |
984b3f57 | 1120 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
bc4598bc | 1121 | priv->num_rx_queues) { |
46ceb60c SG |
1122 | priv->gfargrp[grp_idx].num_rx_queues++; |
1123 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1124 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1125 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1126 | } | |
1127 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
bc4598bc | 1128 | |
984b3f57 | 1129 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
bc4598bc | 1130 | priv->num_tx_queues) { |
46ceb60c SG |
1131 | priv->gfargrp[grp_idx].num_tx_queues++; |
1132 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1133 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1134 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1135 | } | |
1136 | priv->gfargrp[grp_idx].rstat = rstat; | |
1137 | priv->gfargrp[grp_idx].tstat = tstat; | |
1138 | rstat = tstat =0; | |
fba4ed03 | 1139 | } |
fba4ed03 SG |
1140 | |
1141 | gfar_write(®s->rqueue, rqueue); | |
1142 | gfar_write(®s->tqueue, tqueue); | |
1143 | ||
1da177e4 | 1144 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1145 | |
a12f801d | 1146 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1147 | for (i = 0; i < priv->num_tx_queues; i++) { |
1148 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1149 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1150 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1151 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1152 | } | |
a12f801d | 1153 | |
fba4ed03 SG |
1154 | for (i = 0; i < priv->num_rx_queues; i++) { |
1155 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1156 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1157 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1158 | } | |
1da177e4 | 1159 | |
0977f817 | 1160 | /* always enable rx filer */ |
4aa3a715 | 1161 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1162 | /* Enable most messages by default */ |
1163 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1164 | ||
d3eab82b TP |
1165 | /* Carrier starts down, phylib will bring it up */ |
1166 | netif_carrier_off(dev); | |
1167 | ||
1da177e4 LT |
1168 | err = register_netdev(dev); |
1169 | ||
1170 | if (err) { | |
59deab26 | 1171 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1172 | goto register_fail; |
1173 | } | |
1174 | ||
2884e5cc | 1175 | device_init_wakeup(&dev->dev, |
bc4598bc JC |
1176 | priv->device_flags & |
1177 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
2884e5cc | 1178 | |
c50a5d9a | 1179 | /* fill out IRQ number and name fields */ |
46ceb60c | 1180 | for (i = 0; i < priv->num_grps; i++) { |
46ceb60c | 1181 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0015e551 JP |
1182 | sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s", |
1183 | dev->name, "_g", '0' + i, "_tx"); | |
1184 | sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s", | |
1185 | dev->name, "_g", '0' + i, "_rx"); | |
1186 | sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s", | |
1187 | dev->name, "_g", '0' + i, "_er"); | |
46ceb60c | 1188 | } else |
0015e551 | 1189 | strcpy(priv->gfargrp[i].int_name_tx, dev->name); |
46ceb60c | 1190 | } |
c50a5d9a | 1191 | |
7a8b3372 SG |
1192 | /* Initialize the filer table */ |
1193 | gfar_init_filer_table(priv); | |
1194 | ||
7f7f5316 AF |
1195 | /* Create all the sysfs files */ |
1196 | gfar_init_sysfs(dev); | |
1197 | ||
1da177e4 | 1198 | /* Print out the device info */ |
59deab26 | 1199 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1200 | |
0977f817 JC |
1201 | /* Even more device info helps when determining which kernel |
1202 | * provided which set of benchmarks. | |
1203 | */ | |
59deab26 | 1204 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1205 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1206 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1207 | i, priv->rx_queue[i]->rx_ring_size); | |
bc4598bc | 1208 | for (i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1209 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1210 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1211 | |
1212 | return 0; | |
1213 | ||
1214 | register_fail: | |
46ceb60c | 1215 | unmap_group_regs(priv); |
fba4ed03 SG |
1216 | free_tx_pointers(priv); |
1217 | free_rx_pointers(priv); | |
fe192a49 GL |
1218 | if (priv->phy_node) |
1219 | of_node_put(priv->phy_node); | |
1220 | if (priv->tbi_node) | |
1221 | of_node_put(priv->tbi_node); | |
1da177e4 | 1222 | free_netdev(dev); |
bb40dcbb | 1223 | return err; |
1da177e4 LT |
1224 | } |
1225 | ||
2dc11581 | 1226 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1227 | { |
b31a1d8b | 1228 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 1229 | |
fe192a49 GL |
1230 | if (priv->phy_node) |
1231 | of_node_put(priv->phy_node); | |
1232 | if (priv->tbi_node) | |
1233 | of_node_put(priv->tbi_node); | |
1234 | ||
b31a1d8b | 1235 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 1236 | |
d9d8e041 | 1237 | unregister_netdev(priv->ndev); |
46ceb60c | 1238 | unmap_group_regs(priv); |
4826857f | 1239 | free_netdev(priv->ndev); |
1da177e4 LT |
1240 | |
1241 | return 0; | |
1242 | } | |
1243 | ||
d87eb127 | 1244 | #ifdef CONFIG_PM |
be926fc4 AV |
1245 | |
1246 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1247 | { |
be926fc4 AV |
1248 | struct gfar_private *priv = dev_get_drvdata(dev); |
1249 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1250 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1251 | unsigned long flags; |
1252 | u32 tempval; | |
1253 | ||
1254 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1255 | (priv->device_flags & |
1256 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1257 | |
be926fc4 | 1258 | netif_device_detach(ndev); |
d87eb127 | 1259 | |
be926fc4 | 1260 | if (netif_running(ndev)) { |
fba4ed03 SG |
1261 | |
1262 | local_irq_save(flags); | |
1263 | lock_tx_qs(priv); | |
1264 | lock_rx_qs(priv); | |
d87eb127 | 1265 | |
be926fc4 | 1266 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1267 | |
1268 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1269 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1270 | |
1271 | tempval &= ~MACCFG1_TX_EN; | |
1272 | ||
1273 | if (!magic_packet) | |
1274 | tempval &= ~MACCFG1_RX_EN; | |
1275 | ||
f4983704 | 1276 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1277 | |
fba4ed03 SG |
1278 | unlock_rx_qs(priv); |
1279 | unlock_tx_qs(priv); | |
1280 | local_irq_restore(flags); | |
d87eb127 | 1281 | |
46ceb60c | 1282 | disable_napi(priv); |
d87eb127 SW |
1283 | |
1284 | if (magic_packet) { | |
1285 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1286 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1287 | |
1288 | /* Enable Magic Packet mode */ | |
f4983704 | 1289 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1290 | tempval |= MACCFG2_MPEN; |
f4983704 | 1291 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1292 | } else { |
1293 | phy_stop(priv->phydev); | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | return 0; | |
1298 | } | |
1299 | ||
be926fc4 | 1300 | static int gfar_resume(struct device *dev) |
d87eb127 | 1301 | { |
be926fc4 AV |
1302 | struct gfar_private *priv = dev_get_drvdata(dev); |
1303 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1304 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1305 | unsigned long flags; |
1306 | u32 tempval; | |
1307 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1308 | (priv->device_flags & |
1309 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1310 | |
be926fc4 AV |
1311 | if (!netif_running(ndev)) { |
1312 | netif_device_attach(ndev); | |
d87eb127 SW |
1313 | return 0; |
1314 | } | |
1315 | ||
1316 | if (!magic_packet && priv->phydev) | |
1317 | phy_start(priv->phydev); | |
1318 | ||
1319 | /* Disable Magic Packet mode, in case something | |
1320 | * else woke us up. | |
1321 | */ | |
fba4ed03 SG |
1322 | local_irq_save(flags); |
1323 | lock_tx_qs(priv); | |
1324 | lock_rx_qs(priv); | |
d87eb127 | 1325 | |
f4983704 | 1326 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1327 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1328 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1329 | |
be926fc4 | 1330 | gfar_start(ndev); |
d87eb127 | 1331 | |
fba4ed03 SG |
1332 | unlock_rx_qs(priv); |
1333 | unlock_tx_qs(priv); | |
1334 | local_irq_restore(flags); | |
d87eb127 | 1335 | |
be926fc4 AV |
1336 | netif_device_attach(ndev); |
1337 | ||
46ceb60c | 1338 | enable_napi(priv); |
be926fc4 AV |
1339 | |
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static int gfar_restore(struct device *dev) | |
1344 | { | |
1345 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1346 | struct net_device *ndev = priv->ndev; | |
1347 | ||
1348 | if (!netif_running(ndev)) | |
1349 | return 0; | |
1350 | ||
1351 | gfar_init_bds(ndev); | |
1352 | init_registers(ndev); | |
1353 | gfar_set_mac_address(ndev); | |
1354 | gfar_init_mac(ndev); | |
1355 | gfar_start(ndev); | |
1356 | ||
1357 | priv->oldlink = 0; | |
1358 | priv->oldspeed = 0; | |
1359 | priv->oldduplex = -1; | |
1360 | ||
1361 | if (priv->phydev) | |
1362 | phy_start(priv->phydev); | |
d87eb127 | 1363 | |
be926fc4 | 1364 | netif_device_attach(ndev); |
5ea681d4 | 1365 | enable_napi(priv); |
d87eb127 SW |
1366 | |
1367 | return 0; | |
1368 | } | |
be926fc4 AV |
1369 | |
1370 | static struct dev_pm_ops gfar_pm_ops = { | |
1371 | .suspend = gfar_suspend, | |
1372 | .resume = gfar_resume, | |
1373 | .freeze = gfar_suspend, | |
1374 | .thaw = gfar_resume, | |
1375 | .restore = gfar_restore, | |
1376 | }; | |
1377 | ||
1378 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1379 | ||
d87eb127 | 1380 | #else |
be926fc4 AV |
1381 | |
1382 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1383 | |
d87eb127 | 1384 | #endif |
1da177e4 | 1385 | |
e8a2b6a4 AF |
1386 | /* Reads the controller's registers to determine what interface |
1387 | * connects it to the PHY. | |
1388 | */ | |
1389 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1390 | { | |
1391 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1392 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1393 | u32 ecntrl; |
1394 | ||
f4983704 | 1395 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1396 | |
1397 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1398 | return PHY_INTERFACE_MODE_SGMII; | |
1399 | ||
1400 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1401 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1402 | return PHY_INTERFACE_MODE_RTBI; | |
1403 | else | |
1404 | return PHY_INTERFACE_MODE_TBI; | |
1405 | } | |
1406 | ||
1407 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
bc4598bc | 1408 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) { |
e8a2b6a4 | 1409 | return PHY_INTERFACE_MODE_RMII; |
bc4598bc | 1410 | } |
7132ab7f | 1411 | else { |
b31a1d8b | 1412 | phy_interface_t interface = priv->interface; |
7132ab7f | 1413 | |
0977f817 | 1414 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1415 | * be set by the device tree or platform code. |
1416 | */ | |
1417 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1418 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1419 | ||
e8a2b6a4 | 1420 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1421 | } |
e8a2b6a4 AF |
1422 | } |
1423 | ||
b31a1d8b | 1424 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1425 | return PHY_INTERFACE_MODE_GMII; |
1426 | ||
1427 | return PHY_INTERFACE_MODE_MII; | |
1428 | } | |
1429 | ||
1430 | ||
bb40dcbb AF |
1431 | /* Initializes driver's PHY state, and attaches to the PHY. |
1432 | * Returns 0 on success. | |
1da177e4 LT |
1433 | */ |
1434 | static int init_phy(struct net_device *dev) | |
1435 | { | |
1436 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1437 | uint gigabit_support = |
b31a1d8b | 1438 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 1439 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 1440 | phy_interface_t interface; |
1da177e4 LT |
1441 | |
1442 | priv->oldlink = 0; | |
1443 | priv->oldspeed = 0; | |
1444 | priv->oldduplex = -1; | |
1445 | ||
e8a2b6a4 AF |
1446 | interface = gfar_get_interface(dev); |
1447 | ||
1db780f8 AV |
1448 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1449 | interface); | |
1450 | if (!priv->phydev) | |
1451 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1452 | interface); | |
1453 | if (!priv->phydev) { | |
1454 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1455 | return -ENODEV; | |
fe192a49 | 1456 | } |
1da177e4 | 1457 | |
d3c12873 KJ |
1458 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1459 | gfar_configure_serdes(dev); | |
1460 | ||
bb40dcbb | 1461 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1462 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1463 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1464 | |
1465 | return 0; | |
1da177e4 LT |
1466 | } |
1467 | ||
0977f817 | 1468 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1469 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1470 | * through the MDIO bus on each controller, treating it as a | |
1471 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1472 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1473 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1474 | * value doesn't matter, as there are no other PHYs on the bus. | |
1475 | */ | |
d3c12873 KJ |
1476 | static void gfar_configure_serdes(struct net_device *dev) |
1477 | { | |
1478 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1479 | struct phy_device *tbiphy; |
1480 | ||
1481 | if (!priv->tbi_node) { | |
1482 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1483 | "device tree specify a tbi-handle\n"); | |
1484 | return; | |
1485 | } | |
c132419e | 1486 | |
fe192a49 GL |
1487 | tbiphy = of_phy_find_device(priv->tbi_node); |
1488 | if (!tbiphy) { | |
1489 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1490 | return; |
1491 | } | |
d3c12873 | 1492 | |
0977f817 | 1493 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1494 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1495 | * everything for us? Resetting it takes the link down and requires | |
1496 | * several seconds for it to come back. | |
1497 | */ | |
fe192a49 | 1498 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1499 | return; |
d3c12873 | 1500 | |
d0313587 | 1501 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1502 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1503 | |
fe192a49 | 1504 | phy_write(tbiphy, MII_ADVERTISE, |
bc4598bc JC |
1505 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1506 | ADVERTISE_1000XPSE_ASYM); | |
d3c12873 | 1507 | |
bc4598bc JC |
1508 | phy_write(tbiphy, MII_BMCR, |
1509 | BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | | |
1510 | BMCR_SPEED1000); | |
d3c12873 KJ |
1511 | } |
1512 | ||
1da177e4 LT |
1513 | static void init_registers(struct net_device *dev) |
1514 | { | |
1515 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1516 | struct gfar __iomem *regs = NULL; |
46ceb60c | 1517 | int i = 0; |
1da177e4 | 1518 | |
46ceb60c SG |
1519 | for (i = 0; i < priv->num_grps; i++) { |
1520 | regs = priv->gfargrp[i].regs; | |
1521 | /* Clear IEVENT */ | |
1522 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1523 | |
46ceb60c SG |
1524 | /* Initialize IMASK */ |
1525 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1526 | } | |
1da177e4 | 1527 | |
46ceb60c | 1528 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1529 | /* Init hash registers to zero */ |
f4983704 SG |
1530 | gfar_write(®s->igaddr0, 0); |
1531 | gfar_write(®s->igaddr1, 0); | |
1532 | gfar_write(®s->igaddr2, 0); | |
1533 | gfar_write(®s->igaddr3, 0); | |
1534 | gfar_write(®s->igaddr4, 0); | |
1535 | gfar_write(®s->igaddr5, 0); | |
1536 | gfar_write(®s->igaddr6, 0); | |
1537 | gfar_write(®s->igaddr7, 0); | |
1538 | ||
1539 | gfar_write(®s->gaddr0, 0); | |
1540 | gfar_write(®s->gaddr1, 0); | |
1541 | gfar_write(®s->gaddr2, 0); | |
1542 | gfar_write(®s->gaddr3, 0); | |
1543 | gfar_write(®s->gaddr4, 0); | |
1544 | gfar_write(®s->gaddr5, 0); | |
1545 | gfar_write(®s->gaddr6, 0); | |
1546 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1547 | |
1da177e4 | 1548 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1549 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1550 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1551 | |
1552 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1553 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1554 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1555 | } |
1556 | ||
1557 | /* Initialize the max receive buffer length */ | |
f4983704 | 1558 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1559 | |
1da177e4 | 1560 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1561 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1562 | } |
1563 | ||
511d934f AV |
1564 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1565 | { | |
1566 | u32 res; | |
1567 | ||
0977f817 | 1568 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1569 | * actually wait for IEVENT_GRSC flag. |
1570 | */ | |
1571 | if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) | |
1572 | return 0; | |
1573 | ||
0977f817 | 1574 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1575 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1576 | * and the Rx can be safely reset. | |
1577 | */ | |
1578 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1579 | res &= 0x7f807f80; | |
1580 | if ((res & 0xffff) == (res >> 16)) | |
1581 | return 1; | |
1582 | ||
1583 | return 0; | |
1584 | } | |
0bbaf069 KG |
1585 | |
1586 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1587 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1588 | { |
1589 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1590 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1591 | u32 tempval; |
46ceb60c | 1592 | int i = 0; |
1da177e4 | 1593 | |
46ceb60c SG |
1594 | for (i = 0; i < priv->num_grps; i++) { |
1595 | regs = priv->gfargrp[i].regs; | |
1596 | /* Mask all interrupts */ | |
1597 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1598 | |
46ceb60c SG |
1599 | /* Clear all interrupts */ |
1600 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1601 | } | |
1da177e4 | 1602 | |
46ceb60c | 1603 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1604 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1605 | tempval = gfar_read(®s->dmactrl); |
bc4598bc JC |
1606 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != |
1607 | (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1608 | int ret; |
1609 | ||
1da177e4 | 1610 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1611 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1612 | |
511d934f AV |
1613 | do { |
1614 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1615 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1616 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1617 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1618 | ret = __gfar_is_rx_idle(priv); | |
1619 | } while (!ret); | |
1da177e4 | 1620 | } |
d87eb127 | 1621 | } |
d87eb127 SW |
1622 | |
1623 | /* Halt the receive and transmit queues */ | |
1624 | void gfar_halt(struct net_device *dev) | |
1625 | { | |
1626 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1627 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1628 | u32 tempval; |
1da177e4 | 1629 | |
2a54adc3 SW |
1630 | gfar_halt_nodisable(dev); |
1631 | ||
1da177e4 LT |
1632 | /* Disable Rx and Tx */ |
1633 | tempval = gfar_read(®s->maccfg1); | |
1634 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1635 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1636 | } |
1637 | ||
46ceb60c SG |
1638 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1639 | { | |
1640 | free_irq(grp->interruptError, grp); | |
1641 | free_irq(grp->interruptTransmit, grp); | |
1642 | free_irq(grp->interruptReceive, grp); | |
1643 | } | |
1644 | ||
0bbaf069 KG |
1645 | void stop_gfar(struct net_device *dev) |
1646 | { | |
1647 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1648 | unsigned long flags; |
46ceb60c | 1649 | int i; |
0bbaf069 | 1650 | |
bb40dcbb AF |
1651 | phy_stop(priv->phydev); |
1652 | ||
a12f801d | 1653 | |
0bbaf069 | 1654 | /* Lock it down */ |
fba4ed03 SG |
1655 | local_irq_save(flags); |
1656 | lock_tx_qs(priv); | |
1657 | lock_rx_qs(priv); | |
0bbaf069 | 1658 | |
0bbaf069 | 1659 | gfar_halt(dev); |
1da177e4 | 1660 | |
fba4ed03 SG |
1661 | unlock_rx_qs(priv); |
1662 | unlock_tx_qs(priv); | |
1663 | local_irq_restore(flags); | |
1da177e4 LT |
1664 | |
1665 | /* Free the IRQs */ | |
b31a1d8b | 1666 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1667 | for (i = 0; i < priv->num_grps; i++) |
1668 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1669 | } else { |
46ceb60c SG |
1670 | for (i = 0; i < priv->num_grps; i++) |
1671 | free_irq(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 1672 | &priv->gfargrp[i]); |
1da177e4 LT |
1673 | } |
1674 | ||
1675 | free_skb_resources(priv); | |
1da177e4 LT |
1676 | } |
1677 | ||
fba4ed03 | 1678 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1679 | { |
1da177e4 | 1680 | struct txbd8 *txbdp; |
fba4ed03 | 1681 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1682 | int i, j; |
1da177e4 | 1683 | |
a12f801d | 1684 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1685 | |
a12f801d SG |
1686 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1687 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1688 | continue; |
1da177e4 | 1689 | |
4826857f | 1690 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
bc4598bc | 1691 | txbdp->length, DMA_TO_DEVICE); |
4669bc90 | 1692 | txbdp->lstatus = 0; |
fba4ed03 | 1693 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
bc4598bc | 1694 | j++) { |
4669bc90 | 1695 | txbdp++; |
4826857f | 1696 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
bc4598bc | 1697 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1698 | } |
ad5da7ab | 1699 | txbdp++; |
a12f801d SG |
1700 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1701 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1702 | } |
a12f801d | 1703 | kfree(tx_queue->tx_skbuff); |
fba4ed03 | 1704 | } |
1da177e4 | 1705 | |
fba4ed03 SG |
1706 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1707 | { | |
1708 | struct rxbd8 *rxbdp; | |
1709 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1710 | int i; | |
1da177e4 | 1711 | |
fba4ed03 | 1712 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1713 | |
a12f801d SG |
1714 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1715 | if (rx_queue->rx_skbuff[i]) { | |
fba4ed03 | 1716 | dma_unmap_single(&priv->ofdev->dev, |
bc4598bc JC |
1717 | rxbdp->bufPtr, priv->rx_buffer_size, |
1718 | DMA_FROM_DEVICE); | |
a12f801d SG |
1719 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1720 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1721 | } |
e69edd21 AV |
1722 | rxbdp->lstatus = 0; |
1723 | rxbdp->bufPtr = 0; | |
1724 | rxbdp++; | |
1da177e4 | 1725 | } |
a12f801d | 1726 | kfree(rx_queue->rx_skbuff); |
fba4ed03 | 1727 | } |
e69edd21 | 1728 | |
fba4ed03 | 1729 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1730 | * Then free tx_skbuff and rx_skbuff |
1731 | */ | |
fba4ed03 SG |
1732 | static void free_skb_resources(struct gfar_private *priv) |
1733 | { | |
1734 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1735 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1736 | int i; | |
1737 | ||
1738 | /* Go through all the buffer descriptors and free their data buffers */ | |
1739 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1740 | struct netdev_queue *txq; |
bc4598bc | 1741 | |
fba4ed03 | 1742 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1743 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
bc4598bc | 1744 | if (tx_queue->tx_skbuff) |
fba4ed03 | 1745 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1746 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1747 | } |
1748 | ||
1749 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1750 | rx_queue = priv->rx_queue[i]; | |
bc4598bc | 1751 | if (rx_queue->rx_skbuff) |
fba4ed03 SG |
1752 | free_skb_rx_queue(rx_queue); |
1753 | } | |
1754 | ||
1755 | dma_free_coherent(&priv->ofdev->dev, | |
bc4598bc JC |
1756 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
1757 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1758 | priv->tx_queue[0]->tx_bd_base, | |
1759 | priv->tx_queue[0]->tx_bd_dma_base); | |
7df9c43f | 1760 | skb_queue_purge(&priv->rx_recycle); |
1da177e4 LT |
1761 | } |
1762 | ||
0bbaf069 KG |
1763 | void gfar_start(struct net_device *dev) |
1764 | { | |
1765 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1766 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1767 | u32 tempval; |
46ceb60c | 1768 | int i = 0; |
0bbaf069 KG |
1769 | |
1770 | /* Enable Rx and Tx in MACCFG1 */ | |
1771 | tempval = gfar_read(®s->maccfg1); | |
1772 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1773 | gfar_write(®s->maccfg1, tempval); | |
1774 | ||
1775 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1776 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1777 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1778 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1779 | |
0bbaf069 | 1780 | /* Make sure we aren't stopped */ |
f4983704 | 1781 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1782 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1783 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1784 | |
46ceb60c SG |
1785 | for (i = 0; i < priv->num_grps; i++) { |
1786 | regs = priv->gfargrp[i].regs; | |
1787 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1788 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1789 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1790 | /* Unmask the interrupts we look for */ | |
1791 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1792 | } | |
12dea57b | 1793 | |
1ae5dc34 | 1794 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1795 | } |
1796 | ||
46ceb60c | 1797 | void gfar_configure_coalescing(struct gfar_private *priv, |
bc4598bc | 1798 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1799 | { |
46ceb60c | 1800 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1801 | u32 __iomem *baddr; |
46ceb60c | 1802 | int i = 0; |
1da177e4 | 1803 | |
46ceb60c SG |
1804 | /* Backward compatible case ---- even if we enable |
1805 | * multiple queues, there's only single reg to program | |
1806 | */ | |
1807 | gfar_write(®s->txic, 0); | |
bc4598bc | 1808 | if (likely(priv->tx_queue[0]->txcoalescing)) |
46ceb60c | 1809 | gfar_write(®s->txic, priv->tx_queue[0]->txic); |
1da177e4 | 1810 | |
46ceb60c | 1811 | gfar_write(®s->rxic, 0); |
bc4598bc | 1812 | if (unlikely(priv->rx_queue[0]->rxcoalescing)) |
46ceb60c | 1813 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); |
815b97c6 | 1814 | |
46ceb60c SG |
1815 | if (priv->mode == MQ_MG_MODE) { |
1816 | baddr = ®s->txic0; | |
984b3f57 | 1817 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
46ceb60c SG |
1818 | if (likely(priv->tx_queue[i]->txcoalescing)) { |
1819 | gfar_write(baddr + i, 0); | |
1820 | gfar_write(baddr + i, priv->tx_queue[i]->txic); | |
1821 | } | |
1822 | } | |
1823 | ||
1824 | baddr = ®s->rxic0; | |
984b3f57 | 1825 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
46ceb60c SG |
1826 | if (likely(priv->rx_queue[i]->rxcoalescing)) { |
1827 | gfar_write(baddr + i, 0); | |
1828 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); | |
1829 | } | |
1830 | } | |
1831 | } | |
1832 | } | |
1833 | ||
1834 | static int register_grp_irqs(struct gfar_priv_grp *grp) | |
1835 | { | |
1836 | struct gfar_private *priv = grp->priv; | |
1837 | struct net_device *dev = priv->ndev; | |
1838 | int err; | |
1da177e4 | 1839 | |
1da177e4 | 1840 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1841 | * them. Otherwise, only register for the one |
1842 | */ | |
b31a1d8b | 1843 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1844 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1845 | * Transmit, and Receive |
1846 | */ | |
bc4598bc JC |
1847 | if ((err = request_irq(grp->interruptError, gfar_error, |
1848 | 0, grp->int_name_er, grp)) < 0) { | |
59deab26 JP |
1849 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1850 | grp->interruptError); | |
46ceb60c | 1851 | |
2145f1af | 1852 | goto err_irq_fail; |
1da177e4 LT |
1853 | } |
1854 | ||
46ceb60c | 1855 | if ((err = request_irq(grp->interruptTransmit, gfar_transmit, |
bc4598bc | 1856 | 0, grp->int_name_tx, grp)) < 0) { |
59deab26 JP |
1857 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1858 | grp->interruptTransmit); | |
1da177e4 LT |
1859 | goto tx_irq_fail; |
1860 | } | |
1861 | ||
bc4598bc JC |
1862 | if ((err = request_irq(grp->interruptReceive, gfar_receive, |
1863 | 0, grp->int_name_rx, grp)) < 0) { | |
59deab26 JP |
1864 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1865 | grp->interruptReceive); | |
1da177e4 LT |
1866 | goto rx_irq_fail; |
1867 | } | |
1868 | } else { | |
bc4598bc JC |
1869 | if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, |
1870 | 0, grp->int_name_tx, grp)) < 0) { | |
59deab26 JP |
1871 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1872 | grp->interruptTransmit); | |
1da177e4 LT |
1873 | goto err_irq_fail; |
1874 | } | |
1875 | } | |
1876 | ||
46ceb60c SG |
1877 | return 0; |
1878 | ||
1879 | rx_irq_fail: | |
1880 | free_irq(grp->interruptTransmit, grp); | |
1881 | tx_irq_fail: | |
1882 | free_irq(grp->interruptError, grp); | |
1883 | err_irq_fail: | |
1884 | return err; | |
1885 | ||
1886 | } | |
1887 | ||
1888 | /* Bring the controller up and running */ | |
1889 | int startup_gfar(struct net_device *ndev) | |
1890 | { | |
1891 | struct gfar_private *priv = netdev_priv(ndev); | |
1892 | struct gfar __iomem *regs = NULL; | |
1893 | int err, i, j; | |
1894 | ||
1895 | for (i = 0; i < priv->num_grps; i++) { | |
1896 | regs= priv->gfargrp[i].regs; | |
1897 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1898 | } | |
1899 | ||
1900 | regs= priv->gfargrp[0].regs; | |
1901 | err = gfar_alloc_skb_resources(ndev); | |
1902 | if (err) | |
1903 | return err; | |
1904 | ||
1905 | gfar_init_mac(ndev); | |
1906 | ||
1907 | for (i = 0; i < priv->num_grps; i++) { | |
1908 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1909 | if (err) { | |
1910 | for (j = 0; j < i; j++) | |
1911 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1912 | goto irq_fail; |
46ceb60c SG |
1913 | } |
1914 | } | |
1915 | ||
7f7f5316 | 1916 | /* Start the controller */ |
ccc05c6e | 1917 | gfar_start(ndev); |
1da177e4 | 1918 | |
826aa4a0 AV |
1919 | phy_start(priv->phydev); |
1920 | ||
46ceb60c SG |
1921 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
1922 | ||
1da177e4 LT |
1923 | return 0; |
1924 | ||
46ceb60c | 1925 | irq_fail: |
e69edd21 | 1926 | free_skb_resources(priv); |
1da177e4 LT |
1927 | return err; |
1928 | } | |
1929 | ||
0977f817 JC |
1930 | /* Called when something needs to use the ethernet device |
1931 | * Returns 0 for success. | |
1932 | */ | |
1da177e4 LT |
1933 | static int gfar_enet_open(struct net_device *dev) |
1934 | { | |
94e8cc35 | 1935 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1936 | int err; |
1937 | ||
46ceb60c | 1938 | enable_napi(priv); |
bea3348e | 1939 | |
0fd56bb5 AF |
1940 | skb_queue_head_init(&priv->rx_recycle); |
1941 | ||
1da177e4 LT |
1942 | /* Initialize a bunch of registers */ |
1943 | init_registers(dev); | |
1944 | ||
1945 | gfar_set_mac_address(dev); | |
1946 | ||
1947 | err = init_phy(dev); | |
1948 | ||
a12f801d | 1949 | if (err) { |
46ceb60c | 1950 | disable_napi(priv); |
1da177e4 | 1951 | return err; |
bea3348e | 1952 | } |
1da177e4 LT |
1953 | |
1954 | err = startup_gfar(dev); | |
db0e8e3f | 1955 | if (err) { |
46ceb60c | 1956 | disable_napi(priv); |
db0e8e3f AV |
1957 | return err; |
1958 | } | |
1da177e4 | 1959 | |
fba4ed03 | 1960 | netif_tx_start_all_queues(dev); |
1da177e4 | 1961 | |
2884e5cc AV |
1962 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1963 | ||
1da177e4 LT |
1964 | return err; |
1965 | } | |
1966 | ||
54dc79fe | 1967 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1968 | { |
54dc79fe | 1969 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1970 | |
1971 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1972 | |
0bbaf069 KG |
1973 | return fcb; |
1974 | } | |
1975 | ||
9c4886e5 | 1976 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
bc4598bc | 1977 | int fcb_length) |
0bbaf069 | 1978 | { |
7f7f5316 | 1979 | u8 flags = 0; |
0bbaf069 KG |
1980 | |
1981 | /* If we're here, it's a IP packet with a TCP or UDP | |
1982 | * payload. We set it to checksum, using a pseudo-header | |
1983 | * we provide | |
1984 | */ | |
7f7f5316 | 1985 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1986 | |
0977f817 JC |
1987 | /* Tell the controller what the protocol is |
1988 | * And provide the already calculated phcs | |
1989 | */ | |
eddc9ec5 | 1990 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1991 | flags |= TXFCB_UDP; |
4bedb452 | 1992 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1993 | } else |
8da32de5 | 1994 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
1995 | |
1996 | /* l3os is the distance between the start of the | |
1997 | * frame (skb->data) and the start of the IP hdr. | |
1998 | * l4os is the distance between the start of the | |
0977f817 JC |
1999 | * l3 hdr and the l4 hdr |
2000 | */ | |
9c4886e5 | 2001 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 2002 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2003 | |
7f7f5316 | 2004 | fcb->flags = flags; |
0bbaf069 KG |
2005 | } |
2006 | ||
7f7f5316 | 2007 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2008 | { |
7f7f5316 | 2009 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2010 | fcb->vlctl = vlan_tx_tag_get(skb); |
2011 | } | |
2012 | ||
4669bc90 | 2013 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
bc4598bc | 2014 | struct txbd8 *base, int ring_size) |
4669bc90 DH |
2015 | { |
2016 | struct txbd8 *new_bd = bdp + stride; | |
2017 | ||
2018 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2019 | } | |
2020 | ||
2021 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
bc4598bc | 2022 | int ring_size) |
4669bc90 DH |
2023 | { |
2024 | return skip_txbd(bdp, 1, base, ring_size); | |
2025 | } | |
2026 | ||
0977f817 JC |
2027 | /* This is called by the kernel when a frame is ready for transmission. |
2028 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2029 | */ | |
1da177e4 LT |
2030 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2031 | { | |
2032 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2033 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2034 | struct netdev_queue *txq; |
f4983704 | 2035 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2036 | struct txfcb *fcb = NULL; |
f0ee7acf | 2037 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2038 | u32 lstatus; |
f0ee7acf | 2039 | int i, rq = 0, do_tstamp = 0; |
4669bc90 | 2040 | u32 bufaddr; |
fef6108d | 2041 | unsigned long flags; |
9c4886e5 | 2042 | unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN; |
fba4ed03 | 2043 | |
0977f817 | 2044 | /* TOE=1 frames larger than 2500 bytes may see excess delays |
deb90eac AV |
2045 | * before start of transmission. |
2046 | */ | |
2047 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) && | |
bc4598bc JC |
2048 | skb->ip_summed == CHECKSUM_PARTIAL && |
2049 | skb->len > 2500)) { | |
deb90eac AV |
2050 | int ret; |
2051 | ||
2052 | ret = skb_checksum_help(skb); | |
2053 | if (ret) | |
2054 | return ret; | |
2055 | } | |
2056 | ||
fba4ed03 SG |
2057 | rq = skb->queue_mapping; |
2058 | tx_queue = priv->tx_queue[rq]; | |
2059 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2060 | base = tx_queue->tx_bd_base; |
46ceb60c | 2061 | regs = tx_queue->grp->regs; |
f0ee7acf MR |
2062 | |
2063 | /* check if time stamp should be generated */ | |
2244d07b | 2064 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
bc4598bc | 2065 | priv->hwts_tx_en)) { |
f0ee7acf | 2066 | do_tstamp = 1; |
9c4886e5 MR |
2067 | fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
2068 | } | |
4669bc90 | 2069 | |
5b28beaf LY |
2070 | /* make space for additional header when fcb is needed */ |
2071 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
bc4598bc JC |
2072 | vlan_tx_tag_present(skb) || |
2073 | unlikely(do_tstamp)) && | |
2074 | (skb_headroom(skb) < fcb_length)) { | |
54dc79fe SH |
2075 | struct sk_buff *skb_new; |
2076 | ||
9c4886e5 | 2077 | skb_new = skb_realloc_headroom(skb, fcb_length); |
54dc79fe SH |
2078 | if (!skb_new) { |
2079 | dev->stats.tx_errors++; | |
bd14ba84 | 2080 | kfree_skb(skb); |
54dc79fe SH |
2081 | return NETDEV_TX_OK; |
2082 | } | |
db83d136 MR |
2083 | |
2084 | /* Steal sock reference for processing TX time stamps */ | |
2085 | swap(skb_new->sk, skb->sk); | |
2086 | swap(skb_new->destructor, skb->destructor); | |
54dc79fe SH |
2087 | kfree_skb(skb); |
2088 | skb = skb_new; | |
2089 | } | |
2090 | ||
4669bc90 DH |
2091 | /* total number of fragments in the SKB */ |
2092 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2093 | ||
f0ee7acf MR |
2094 | /* calculate the required number of TxBDs for this skb */ |
2095 | if (unlikely(do_tstamp)) | |
2096 | nr_txbds = nr_frags + 2; | |
2097 | else | |
2098 | nr_txbds = nr_frags + 1; | |
2099 | ||
4669bc90 | 2100 | /* check if there is space to queue this packet */ |
f0ee7acf | 2101 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2102 | /* no space, stop the queue */ |
fba4ed03 | 2103 | netif_tx_stop_queue(txq); |
4669bc90 | 2104 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2105 | return NETDEV_TX_BUSY; |
2106 | } | |
1da177e4 LT |
2107 | |
2108 | /* Update transmit stats */ | |
1ac9ad13 ED |
2109 | tx_queue->stats.tx_bytes += skb->len; |
2110 | tx_queue->stats.tx_packets++; | |
1da177e4 | 2111 | |
a12f801d | 2112 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2113 | lstatus = txbdp->lstatus; |
2114 | ||
2115 | /* Time stamp insertion requires one additional TxBD */ | |
2116 | if (unlikely(do_tstamp)) | |
2117 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
bc4598bc | 2118 | tx_queue->tx_ring_size); |
1da177e4 | 2119 | |
4669bc90 | 2120 | if (nr_frags == 0) { |
f0ee7acf MR |
2121 | if (unlikely(do_tstamp)) |
2122 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
bc4598bc | 2123 | TXBD_INTERRUPT); |
f0ee7acf MR |
2124 | else |
2125 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2126 | } else { |
2127 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2128 | for (i = 0; i < nr_frags; i++) { | |
2129 | /* Point at the next BD, wrapping as needed */ | |
a12f801d | 2130 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2131 | |
2132 | length = skb_shinfo(skb)->frags[i].size; | |
2133 | ||
2134 | lstatus = txbdp->lstatus | length | | |
bc4598bc | 2135 | BD_LFLAG(TXBD_READY); |
4669bc90 DH |
2136 | |
2137 | /* Handle the last BD specially */ | |
2138 | if (i == nr_frags - 1) | |
2139 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2140 | |
2234a722 IC |
2141 | bufaddr = skb_frag_dma_map(&priv->ofdev->dev, |
2142 | &skb_shinfo(skb)->frags[i], | |
2143 | 0, | |
2144 | length, | |
2145 | DMA_TO_DEVICE); | |
4669bc90 DH |
2146 | |
2147 | /* set the TxBD length and buffer pointer */ | |
2148 | txbdp->bufPtr = bufaddr; | |
2149 | txbdp->lstatus = lstatus; | |
2150 | } | |
2151 | ||
2152 | lstatus = txbdp_start->lstatus; | |
2153 | } | |
1da177e4 | 2154 | |
9c4886e5 MR |
2155 | /* Add TxPAL between FCB and frame if required */ |
2156 | if (unlikely(do_tstamp)) { | |
2157 | skb_push(skb, GMAC_TXPAL_LEN); | |
2158 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2159 | } | |
2160 | ||
0bbaf069 | 2161 | /* Set up checksumming */ |
12dea57b | 2162 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe | 2163 | fcb = gfar_add_fcb(skb); |
4363c2fd | 2164 | /* as specified by errata */ |
bc4598bc JC |
2165 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) && |
2166 | ((unsigned long)fcb % 0x20) > 0x18)) { | |
4363c2fd AD |
2167 | __skb_pull(skb, GMAC_FCB_LEN); |
2168 | skb_checksum_help(skb); | |
2169 | } else { | |
2170 | lstatus |= BD_LFLAG(TXBD_TOE); | |
9c4886e5 | 2171 | gfar_tx_checksum(skb, fcb, fcb_length); |
4363c2fd | 2172 | } |
0bbaf069 KG |
2173 | } |
2174 | ||
eab6d18d | 2175 | if (vlan_tx_tag_present(skb)) { |
54dc79fe SH |
2176 | if (unlikely(NULL == fcb)) { |
2177 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 2178 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 2179 | } |
54dc79fe SH |
2180 | |
2181 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
2182 | } |
2183 | ||
f0ee7acf MR |
2184 | /* Setup tx hardware time stamping if requested */ |
2185 | if (unlikely(do_tstamp)) { | |
2244d07b | 2186 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf MR |
2187 | if (fcb == NULL) |
2188 | fcb = gfar_add_fcb(skb); | |
2189 | fcb->ptp = 1; | |
2190 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2191 | } | |
2192 | ||
4826857f | 2193 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
bc4598bc | 2194 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2195 | |
0977f817 | 2196 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2197 | * first TxBD points to the FCB and must have a data length of |
2198 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2199 | * the full frame length. | |
2200 | */ | |
2201 | if (unlikely(do_tstamp)) { | |
9c4886e5 | 2202 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length; |
f0ee7acf | 2203 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
bc4598bc | 2204 | (skb_headlen(skb) - fcb_length); |
f0ee7acf MR |
2205 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2206 | } else { | |
2207 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2208 | } | |
1da177e4 | 2209 | |
d8a0f1b0 PG |
2210 | netdev_tx_sent_queue(txq, skb->len); |
2211 | ||
0977f817 | 2212 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2213 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2214 | * when we were reading the num_txbdfree and checking for available | |
2215 | * space, that's because outside of this function it can only grow, | |
2216 | * and once we've got needed space, it cannot suddenly disappear. | |
2217 | * | |
2218 | * The lock also protects us from gfar_error(), which can modify | |
2219 | * regs->tstat and thus retrigger the transfers, which is why we | |
2220 | * also must grab the lock before setting ready bit for the first | |
2221 | * to be transmitted BD. | |
2222 | */ | |
2223 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2224 | ||
0977f817 | 2225 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2226 | * semantics (it requires synchronization between cacheable and |
2227 | * uncacheable mappings, which eieio doesn't provide and which we | |
2228 | * don't need), thus requiring a more expensive sync instruction. At | |
2229 | * some point, the set of architecture-independent barrier functions | |
2230 | * should be expanded to include weaker barriers. | |
2231 | */ | |
3b6330ce | 2232 | eieio(); |
7f7f5316 | 2233 | |
4669bc90 DH |
2234 | txbdp_start->lstatus = lstatus; |
2235 | ||
0eddba52 AV |
2236 | eieio(); /* force lstatus write before tx_skbuff */ |
2237 | ||
2238 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2239 | ||
4669bc90 | 2240 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2241 | * (wrapping if necessary) |
2242 | */ | |
a12f801d | 2243 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
bc4598bc | 2244 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); |
4669bc90 | 2245 | |
a12f801d | 2246 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2247 | |
2248 | /* reduce TxBD free count */ | |
f0ee7acf | 2249 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2250 | |
2251 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2252 | * are full. We need to tell the kernel to stop sending us stuff. |
2253 | */ | |
a12f801d | 2254 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2255 | netif_tx_stop_queue(txq); |
1da177e4 | 2256 | |
09f75cd7 | 2257 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2258 | } |
2259 | ||
1da177e4 | 2260 | /* Tell the DMA to go go go */ |
fba4ed03 | 2261 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2262 | |
2263 | /* Unlock priv */ | |
a12f801d | 2264 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2265 | |
54dc79fe | 2266 | return NETDEV_TX_OK; |
1da177e4 LT |
2267 | } |
2268 | ||
2269 | /* Stops the kernel queue, and halts the controller */ | |
2270 | static int gfar_close(struct net_device *dev) | |
2271 | { | |
2272 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2273 | |
46ceb60c | 2274 | disable_napi(priv); |
bea3348e | 2275 | |
ab939905 | 2276 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2277 | stop_gfar(dev); |
2278 | ||
bb40dcbb AF |
2279 | /* Disconnect from the PHY */ |
2280 | phy_disconnect(priv->phydev); | |
2281 | priv->phydev = NULL; | |
1da177e4 | 2282 | |
fba4ed03 | 2283 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2284 | |
2285 | return 0; | |
2286 | } | |
2287 | ||
1da177e4 | 2288 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2289 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2290 | { |
7f7f5316 | 2291 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2292 | |
2293 | return 0; | |
2294 | } | |
2295 | ||
f3dc1586 SP |
2296 | /* Check if rx parser should be activated */ |
2297 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2298 | { | |
2299 | struct gfar __iomem *regs; | |
2300 | u32 tempval; | |
2301 | ||
2302 | regs = priv->gfargrp[0].regs; | |
2303 | ||
2304 | tempval = gfar_read(®s->rctrl); | |
2305 | /* If parse is no longer required, then disable parser */ | |
2306 | if (tempval & RCTRL_REQ_PARSER) | |
2307 | tempval |= RCTRL_PRSDEP_INIT; | |
2308 | else | |
2309 | tempval &= ~RCTRL_PRSDEP_INIT; | |
2310 | gfar_write(®s->rctrl, tempval); | |
2311 | } | |
2312 | ||
0bbaf069 | 2313 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2314 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2315 | { |
2316 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2317 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2318 | unsigned long flags; |
2319 | u32 tempval; | |
2320 | ||
46ceb60c | 2321 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2322 | local_irq_save(flags); |
2323 | lock_rx_qs(priv); | |
0bbaf069 | 2324 | |
87c288c6 | 2325 | if (features & NETIF_F_HW_VLAN_TX) { |
0bbaf069 | 2326 | /* Enable VLAN tag insertion */ |
f4983704 | 2327 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2328 | tempval |= TCTRL_VLINS; |
f4983704 | 2329 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2330 | } else { |
2331 | /* Disable VLAN tag insertion */ | |
f4983704 | 2332 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2333 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2334 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2335 | } |
0bbaf069 | 2336 | |
87c288c6 JP |
2337 | if (features & NETIF_F_HW_VLAN_RX) { |
2338 | /* Enable VLAN tag extraction */ | |
2339 | tempval = gfar_read(®s->rctrl); | |
2340 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2341 | gfar_write(®s->rctrl, tempval); | |
2342 | } else { | |
0bbaf069 | 2343 | /* Disable VLAN tag extraction */ |
f4983704 | 2344 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2345 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2346 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2347 | |
2348 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2349 | } |
2350 | ||
77ecaf2d DH |
2351 | gfar_change_mtu(dev, dev->mtu); |
2352 | ||
fba4ed03 SG |
2353 | unlock_rx_qs(priv); |
2354 | local_irq_restore(flags); | |
0bbaf069 KG |
2355 | } |
2356 | ||
1da177e4 LT |
2357 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2358 | { | |
2359 | int tempsize, tempval; | |
2360 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2361 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2362 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2363 | int frame_size = new_mtu + ETH_HLEN; |
2364 | ||
87c288c6 | 2365 | if (gfar_is_vlan_on(priv)) |
faa89577 | 2366 | frame_size += VLAN_HLEN; |
0bbaf069 | 2367 | |
1da177e4 | 2368 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2369 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2370 | return -EINVAL; |
2371 | } | |
2372 | ||
77ecaf2d DH |
2373 | if (gfar_uses_fcb(priv)) |
2374 | frame_size += GMAC_FCB_LEN; | |
2375 | ||
2376 | frame_size += priv->padding; | |
2377 | ||
bc4598bc JC |
2378 | tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + |
2379 | INCREMENTAL_BUFFER_SIZE; | |
1da177e4 LT |
2380 | |
2381 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2382 | * stopped, and we changed something |
2383 | */ | |
1da177e4 LT |
2384 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2385 | stop_gfar(dev); | |
2386 | ||
2387 | priv->rx_buffer_size = tempsize; | |
2388 | ||
2389 | dev->mtu = new_mtu; | |
2390 | ||
f4983704 SG |
2391 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2392 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2393 | |
2394 | /* If the mtu is larger than the max size for standard | |
2395 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2396 | * to allow huge frames, and to check the length |
2397 | */ | |
f4983704 | 2398 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2399 | |
7d350977 | 2400 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
bc4598bc | 2401 | gfar_has_errata(priv, GFAR_ERRATA_74)) |
1da177e4 LT |
2402 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2403 | else | |
2404 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2405 | ||
f4983704 | 2406 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2407 | |
2408 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2409 | startup_gfar(dev); | |
2410 | ||
2411 | return 0; | |
2412 | } | |
2413 | ||
ab939905 | 2414 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2415 | * transmitted after a set amount of time. |
2416 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2417 | * starting over will fix the problem. |
2418 | */ | |
2419 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2420 | { |
ab939905 | 2421 | struct gfar_private *priv = container_of(work, struct gfar_private, |
bc4598bc | 2422 | reset_task); |
4826857f | 2423 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2424 | |
2425 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2426 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2427 | stop_gfar(dev); |
2428 | startup_gfar(dev); | |
fba4ed03 | 2429 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2430 | } |
2431 | ||
263ba320 | 2432 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2433 | } |
2434 | ||
ab939905 SS |
2435 | static void gfar_timeout(struct net_device *dev) |
2436 | { | |
2437 | struct gfar_private *priv = netdev_priv(dev); | |
2438 | ||
2439 | dev->stats.tx_errors++; | |
2440 | schedule_work(&priv->reset_task); | |
2441 | } | |
2442 | ||
acbc0f03 EL |
2443 | static void gfar_align_skb(struct sk_buff *skb) |
2444 | { | |
2445 | /* We need the data buffer to be aligned properly. We will reserve | |
2446 | * as many bytes as needed to align the data properly | |
2447 | */ | |
2448 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
bc4598bc | 2449 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); |
acbc0f03 EL |
2450 | } |
2451 | ||
1da177e4 | 2452 | /* Interrupt Handler for Transmit complete */ |
a12f801d | 2453 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2454 | { |
a12f801d | 2455 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2456 | struct netdev_queue *txq; |
d080cd63 | 2457 | struct gfar_private *priv = netdev_priv(dev); |
a12f801d | 2458 | struct gfar_priv_rx_q *rx_queue = NULL; |
f0ee7acf | 2459 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2460 | struct txbd8 *lbdp = NULL; |
a12f801d | 2461 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2462 | struct sk_buff *skb; |
2463 | int skb_dirtytx; | |
a12f801d | 2464 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2465 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2466 | int i; |
d080cd63 | 2467 | int howmany = 0; |
d8a0f1b0 PG |
2468 | int tqi = tx_queue->qindex; |
2469 | unsigned int bytes_sent = 0; | |
4669bc90 | 2470 | u32 lstatus; |
f0ee7acf | 2471 | size_t buflen; |
1da177e4 | 2472 | |
d8a0f1b0 PG |
2473 | rx_queue = priv->rx_queue[tqi]; |
2474 | txq = netdev_get_tx_queue(dev, tqi); | |
a12f801d SG |
2475 | bdp = tx_queue->dirty_tx; |
2476 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2477 | |
a12f801d | 2478 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2479 | unsigned long flags; |
2480 | ||
4669bc90 | 2481 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2482 | |
0977f817 | 2483 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2484 | * Also, we need to dma_unmap_single() the TxPAL. |
2485 | */ | |
2244d07b | 2486 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2487 | nr_txbds = frags + 2; |
2488 | else | |
2489 | nr_txbds = frags + 1; | |
2490 | ||
2491 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2492 | |
4669bc90 | 2493 | lstatus = lbdp->lstatus; |
1da177e4 | 2494 | |
4669bc90 DH |
2495 | /* Only clean completed frames */ |
2496 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
bc4598bc | 2497 | (lstatus & BD_LENGTH_MASK)) |
4669bc90 DH |
2498 | break; |
2499 | ||
2244d07b | 2500 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2501 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2502 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2503 | } else |
2504 | buflen = bdp->length; | |
2505 | ||
2506 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, | |
bc4598bc | 2507 | buflen, DMA_TO_DEVICE); |
f0ee7acf | 2508 | |
2244d07b | 2509 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2510 | struct skb_shared_hwtstamps shhwtstamps; |
2511 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
bc4598bc | 2512 | |
f0ee7acf MR |
2513 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2514 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2515 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2516 | skb_tstamp_tx(skb, &shhwtstamps); |
2517 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2518 | bdp = next; | |
2519 | } | |
81183059 | 2520 | |
4669bc90 DH |
2521 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2522 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2523 | |
4669bc90 | 2524 | for (i = 0; i < frags; i++) { |
bc4598bc JC |
2525 | dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr, |
2526 | bdp->length, DMA_TO_DEVICE); | |
4669bc90 DH |
2527 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2528 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2529 | } | |
1da177e4 | 2530 | |
d8a0f1b0 PG |
2531 | bytes_sent += skb->len; |
2532 | ||
0977f817 | 2533 | /* If there's room in the queue (limit it to rx_buffer_size) |
0fd56bb5 AF |
2534 | * we add this skb back into the pool, if it's the right size |
2535 | */ | |
a12f801d | 2536 | if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size && |
bc4598bc JC |
2537 | skb_recycle_check(skb, priv->rx_buffer_size + |
2538 | RXBUF_ALIGNMENT)) { | |
acbc0f03 | 2539 | gfar_align_skb(skb); |
cd0ea241 | 2540 | skb_queue_head(&priv->rx_recycle, skb); |
acbc0f03 | 2541 | } else |
0fd56bb5 AF |
2542 | dev_kfree_skb_any(skb); |
2543 | ||
a12f801d | 2544 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2545 | |
4669bc90 | 2546 | skb_dirtytx = (skb_dirtytx + 1) & |
bc4598bc | 2547 | TX_RING_MOD_MASK(tx_ring_size); |
4669bc90 DH |
2548 | |
2549 | howmany++; | |
a3bc1f11 | 2550 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2551 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2552 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2553 | } |
1da177e4 | 2554 | |
4669bc90 | 2555 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2556 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2557 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2558 | |
4669bc90 | 2559 | /* Update dirty indicators */ |
a12f801d SG |
2560 | tx_queue->skb_dirtytx = skb_dirtytx; |
2561 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2562 | |
d8a0f1b0 PG |
2563 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
2564 | ||
d080cd63 DH |
2565 | return howmany; |
2566 | } | |
2567 | ||
f4983704 | 2568 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2569 | { |
a6d0b91a AV |
2570 | unsigned long flags; |
2571 | ||
fba4ed03 SG |
2572 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2573 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2574 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2575 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2576 | } else { |
0977f817 | 2577 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2578 | * because of the packets that have already arrived. |
2579 | */ | |
f4983704 | 2580 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2581 | } |
fba4ed03 | 2582 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2583 | |
8c7396ae | 2584 | } |
1da177e4 | 2585 | |
8c7396ae | 2586 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2587 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2588 | { |
f4983704 | 2589 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2590 | return IRQ_HANDLED; |
2591 | } | |
2592 | ||
a12f801d | 2593 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 2594 | struct sk_buff *skb) |
815b97c6 | 2595 | { |
a12f801d | 2596 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2597 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2598 | dma_addr_t buf; |
815b97c6 | 2599 | |
8a102fe0 AV |
2600 | buf = dma_map_single(&priv->ofdev->dev, skb->data, |
2601 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
a12f801d | 2602 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2603 | } |
2604 | ||
2281a0f3 | 2605 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2606 | { |
2607 | struct gfar_private *priv = netdev_priv(dev); | |
2608 | struct sk_buff *skb = NULL; | |
1da177e4 | 2609 | |
acbc0f03 | 2610 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2611 | if (!skb) |
1da177e4 LT |
2612 | return NULL; |
2613 | ||
acbc0f03 | 2614 | gfar_align_skb(skb); |
7f7f5316 | 2615 | |
acbc0f03 EL |
2616 | return skb; |
2617 | } | |
2618 | ||
2281a0f3 | 2619 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 EL |
2620 | { |
2621 | struct gfar_private *priv = netdev_priv(dev); | |
2622 | struct sk_buff *skb = NULL; | |
2623 | ||
cd0ea241 | 2624 | skb = skb_dequeue(&priv->rx_recycle); |
acbc0f03 EL |
2625 | if (!skb) |
2626 | skb = gfar_alloc_skb(dev); | |
1da177e4 | 2627 | |
1da177e4 LT |
2628 | return skb; |
2629 | } | |
2630 | ||
298e1a9e | 2631 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2632 | { |
298e1a9e | 2633 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2634 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2635 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2636 | ||
0977f817 | 2637 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2638 | if (status & RXBD_TRUNCATED) { |
2639 | stats->rx_length_errors++; | |
2640 | ||
2641 | estats->rx_trunc++; | |
2642 | ||
2643 | return; | |
2644 | } | |
2645 | /* Count the errors, if there were any */ | |
2646 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2647 | stats->rx_length_errors++; | |
2648 | ||
2649 | if (status & RXBD_LARGE) | |
2650 | estats->rx_large++; | |
2651 | else | |
2652 | estats->rx_short++; | |
2653 | } | |
2654 | if (status & RXBD_NONOCTET) { | |
2655 | stats->rx_frame_errors++; | |
2656 | estats->rx_nonoctet++; | |
2657 | } | |
2658 | if (status & RXBD_CRCERR) { | |
2659 | estats->rx_crcerr++; | |
2660 | stats->rx_crc_errors++; | |
2661 | } | |
2662 | if (status & RXBD_OVERRUN) { | |
2663 | estats->rx_overrun++; | |
2664 | stats->rx_crc_errors++; | |
2665 | } | |
2666 | } | |
2667 | ||
f4983704 | 2668 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2669 | { |
f4983704 | 2670 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2671 | return IRQ_HANDLED; |
2672 | } | |
2673 | ||
0bbaf069 KG |
2674 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2675 | { | |
2676 | /* If valid headers were found, and valid sums | |
2677 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2678 | * checksumming is necessary. Otherwise, it is [FIXME] |
2679 | */ | |
7f7f5316 | 2680 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2681 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2682 | else | |
bc8acf2c | 2683 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2684 | } |
2685 | ||
2686 | ||
0977f817 | 2687 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
1da177e4 | 2688 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
cd754a57 | 2689 | int amount_pull, struct napi_struct *napi) |
1da177e4 LT |
2690 | { |
2691 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2692 | struct rxfcb *fcb = NULL; |
1da177e4 | 2693 | |
cd754a57 | 2694 | gro_result_t ret; |
1da177e4 | 2695 | |
2c2db48a DH |
2696 | /* fcb is at the beginning if exists */ |
2697 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2698 | |
0977f817 JC |
2699 | /* Remove the FCB from the skb |
2700 | * Remove the padded bytes, if there are any | |
2701 | */ | |
f74dac08 SG |
2702 | if (amount_pull) { |
2703 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2704 | skb_pull(skb, amount_pull); |
f74dac08 | 2705 | } |
0bbaf069 | 2706 | |
cc772ab7 MR |
2707 | /* Get receive timestamp from the skb */ |
2708 | if (priv->hwts_rx_en) { | |
2709 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2710 | u64 *ns = (u64 *) skb->data; | |
bc4598bc | 2711 | |
cc772ab7 MR |
2712 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2713 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2714 | } | |
2715 | ||
2716 | if (priv->padding) | |
2717 | skb_pull(skb, priv->padding); | |
2718 | ||
8b3afe95 | 2719 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2720 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2721 | |
2c2db48a DH |
2722 | /* Tell the skb what kind of packet this is */ |
2723 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2724 | |
0977f817 | 2725 | /* There's need to check for NETIF_F_HW_VLAN_RX here. |
32f7fd44 JP |
2726 | * Even if vlan rx accel is disabled, on some chips |
2727 | * RXFCB_VLN is pseudo randomly set. | |
2728 | */ | |
2729 | if (dev->features & NETIF_F_HW_VLAN_RX && | |
2730 | fcb->flags & RXFCB_VLN) | |
87c288c6 JP |
2731 | __vlan_hwaccel_put_tag(skb, fcb->vlctl); |
2732 | ||
2c2db48a | 2733 | /* Send the packet up the stack */ |
cd754a57 | 2734 | ret = napi_gro_receive(napi, skb); |
0bbaf069 | 2735 | |
cd754a57 | 2736 | if (GRO_DROP == ret) |
2c2db48a | 2737 | priv->extra_stats.kernel_dropped++; |
1da177e4 LT |
2738 | |
2739 | return 0; | |
2740 | } | |
2741 | ||
2742 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2743 | * until the budget/quota has been reached. Returns the number |
2744 | * of frames handled | |
1da177e4 | 2745 | */ |
a12f801d | 2746 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2747 | { |
a12f801d | 2748 | struct net_device *dev = rx_queue->dev; |
31de198b | 2749 | struct rxbd8 *bdp, *base; |
1da177e4 | 2750 | struct sk_buff *skb; |
2c2db48a DH |
2751 | int pkt_len; |
2752 | int amount_pull; | |
1da177e4 LT |
2753 | int howmany = 0; |
2754 | struct gfar_private *priv = netdev_priv(dev); | |
2755 | ||
2756 | /* Get the first full descriptor */ | |
a12f801d SG |
2757 | bdp = rx_queue->cur_rx; |
2758 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2759 | |
cc772ab7 | 2760 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0); |
2c2db48a | 2761 | |
1da177e4 | 2762 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2763 | struct sk_buff *newskb; |
bc4598bc | 2764 | |
3b6330ce | 2765 | rmb(); |
815b97c6 AF |
2766 | |
2767 | /* Add another skb for the future */ | |
2768 | newskb = gfar_new_skb(dev); | |
2769 | ||
a12f801d | 2770 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2771 | |
4826857f | 2772 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
bc4598bc | 2773 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
81183059 | 2774 | |
63b88b90 | 2775 | if (unlikely(!(bdp->status & RXBD_ERR) && |
bc4598bc | 2776 | bdp->length > priv->rx_buffer_size)) |
63b88b90 AV |
2777 | bdp->status = RXBD_LARGE; |
2778 | ||
815b97c6 AF |
2779 | /* We drop the frame if we failed to allocate a new buffer */ |
2780 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
bc4598bc | 2781 | bdp->status & RXBD_ERR)) { |
815b97c6 AF |
2782 | count_errors(bdp->status, dev); |
2783 | ||
2784 | if (unlikely(!newskb)) | |
2785 | newskb = skb; | |
acbc0f03 | 2786 | else if (skb) |
cd0ea241 | 2787 | skb_queue_head(&priv->rx_recycle, skb); |
815b97c6 | 2788 | } else { |
1da177e4 | 2789 | /* Increment the number of packets */ |
a7f38041 | 2790 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2791 | howmany++; |
2792 | ||
2c2db48a DH |
2793 | if (likely(skb)) { |
2794 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2795 | /* Remove the FCS from the packet length */ | |
2796 | skb_put(skb, pkt_len); | |
a7f38041 | 2797 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2798 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 | 2799 | gfar_process_frame(dev, skb, amount_pull, |
bc4598bc | 2800 | &rx_queue->grp->napi); |
2c2db48a DH |
2801 | |
2802 | } else { | |
59deab26 | 2803 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2804 | rx_queue->stats.rx_dropped++; |
2c2db48a DH |
2805 | priv->extra_stats.rx_skbmissing++; |
2806 | } | |
1da177e4 | 2807 | |
1da177e4 LT |
2808 | } |
2809 | ||
a12f801d | 2810 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2811 | |
815b97c6 | 2812 | /* Setup the new bdp */ |
a12f801d | 2813 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2814 | |
2815 | /* Update to the next pointer */ | |
a12f801d | 2816 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2817 | |
2818 | /* update to point at the next skb */ | |
bc4598bc JC |
2819 | rx_queue->skb_currx = (rx_queue->skb_currx + 1) & |
2820 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2821 | } |
2822 | ||
2823 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2824 | rx_queue->cur_rx = bdp; |
1da177e4 | 2825 | |
1da177e4 LT |
2826 | return howmany; |
2827 | } | |
2828 | ||
bea3348e | 2829 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2830 | { |
bc4598bc JC |
2831 | struct gfar_priv_grp *gfargrp = |
2832 | container_of(napi, struct gfar_priv_grp, napi); | |
fba4ed03 | 2833 | struct gfar_private *priv = gfargrp->priv; |
46ceb60c | 2834 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2835 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 SG |
2836 | struct gfar_priv_rx_q *rx_queue = NULL; |
2837 | int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0; | |
18294ad1 AV |
2838 | int tx_cleaned = 0, i, left_over_budget = budget; |
2839 | unsigned long serviced_queues = 0; | |
fba4ed03 | 2840 | int num_queues = 0; |
d080cd63 | 2841 | |
fba4ed03 SG |
2842 | num_queues = gfargrp->num_rx_queues; |
2843 | budget_per_queue = budget/num_queues; | |
2844 | ||
8c7396ae | 2845 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2846 | * because of the packets that have already arrived |
2847 | */ | |
f4983704 | 2848 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2849 | |
fba4ed03 | 2850 | while (num_queues && left_over_budget) { |
fba4ed03 SG |
2851 | budget_per_queue = left_over_budget/num_queues; |
2852 | left_over_budget = 0; | |
2853 | ||
984b3f57 | 2854 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
fba4ed03 SG |
2855 | if (test_bit(i, &serviced_queues)) |
2856 | continue; | |
2857 | rx_queue = priv->rx_queue[i]; | |
2858 | tx_queue = priv->tx_queue[rx_queue->qindex]; | |
2859 | ||
a3bc1f11 | 2860 | tx_cleaned += gfar_clean_tx_ring(tx_queue); |
bc4598bc JC |
2861 | rx_cleaned_per_queue = |
2862 | gfar_clean_rx_ring(rx_queue, budget_per_queue); | |
fba4ed03 | 2863 | rx_cleaned += rx_cleaned_per_queue; |
bc4598bc | 2864 | if (rx_cleaned_per_queue < budget_per_queue) { |
fba4ed03 | 2865 | left_over_budget = left_over_budget + |
bc4598bc JC |
2866 | (budget_per_queue - |
2867 | rx_cleaned_per_queue); | |
fba4ed03 SG |
2868 | set_bit(i, &serviced_queues); |
2869 | num_queues--; | |
2870 | } | |
2871 | } | |
2872 | } | |
1da177e4 | 2873 | |
42199884 AF |
2874 | if (tx_cleaned) |
2875 | return budget; | |
2876 | ||
2877 | if (rx_cleaned < budget) { | |
288379f0 | 2878 | napi_complete(napi); |
1da177e4 LT |
2879 | |
2880 | /* Clear the halt bit in RSTAT */ | |
fba4ed03 | 2881 | gfar_write(®s->rstat, gfargrp->rstat); |
1da177e4 | 2882 | |
f4983704 | 2883 | gfar_write(®s->imask, IMASK_DEFAULT); |
1da177e4 | 2884 | |
0977f817 JC |
2885 | /* If we are coalescing interrupts, update the timer |
2886 | * Otherwise, clear it | |
2887 | */ | |
bc4598bc JC |
2888 | gfar_configure_coalescing(priv, gfargrp->rx_bit_map, |
2889 | gfargrp->tx_bit_map); | |
1da177e4 LT |
2890 | } |
2891 | ||
42199884 | 2892 | return rx_cleaned; |
1da177e4 | 2893 | } |
1da177e4 | 2894 | |
f2d71c2d | 2895 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2896 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2897 | * without having to re-enable interrupts. It's not called while |
2898 | * the interrupt routine is executing. | |
2899 | */ | |
2900 | static void gfar_netpoll(struct net_device *dev) | |
2901 | { | |
2902 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2903 | int i = 0; |
f2d71c2d VW |
2904 | |
2905 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2906 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
2907 | for (i = 0; i < priv->num_grps; i++) { |
2908 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2909 | disable_irq(priv->gfargrp[i].interruptReceive); | |
2910 | disable_irq(priv->gfargrp[i].interruptError); | |
2911 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 2912 | &priv->gfargrp[i]); |
46ceb60c SG |
2913 | enable_irq(priv->gfargrp[i].interruptError); |
2914 | enable_irq(priv->gfargrp[i].interruptReceive); | |
2915 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
2916 | } | |
f2d71c2d | 2917 | } else { |
46ceb60c SG |
2918 | for (i = 0; i < priv->num_grps; i++) { |
2919 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2920 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 2921 | &priv->gfargrp[i]); |
46ceb60c | 2922 | enable_irq(priv->gfargrp[i].interruptTransmit); |
43de004b | 2923 | } |
f2d71c2d VW |
2924 | } |
2925 | } | |
2926 | #endif | |
2927 | ||
1da177e4 | 2928 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 2929 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 2930 | { |
f4983704 | 2931 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
2932 | |
2933 | /* Save ievent for future reference */ | |
f4983704 | 2934 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 2935 | |
1da177e4 | 2936 | /* Check for reception */ |
538cc7ee | 2937 | if (events & IEVENT_RX_MASK) |
f4983704 | 2938 | gfar_receive(irq, grp_id); |
1da177e4 LT |
2939 | |
2940 | /* Check for transmit completion */ | |
538cc7ee | 2941 | if (events & IEVENT_TX_MASK) |
f4983704 | 2942 | gfar_transmit(irq, grp_id); |
1da177e4 | 2943 | |
538cc7ee SS |
2944 | /* Check for errors */ |
2945 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 2946 | gfar_error(irq, grp_id); |
1da177e4 LT |
2947 | |
2948 | return IRQ_HANDLED; | |
2949 | } | |
2950 | ||
1da177e4 LT |
2951 | /* Called every time the controller might need to be made |
2952 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2953 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2954 | * function converts those variables into the appropriate |
2955 | * register values, and can bring down the device if needed. | |
2956 | */ | |
2957 | static void adjust_link(struct net_device *dev) | |
2958 | { | |
2959 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2960 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
2961 | unsigned long flags; |
2962 | struct phy_device *phydev = priv->phydev; | |
2963 | int new_state = 0; | |
2964 | ||
fba4ed03 SG |
2965 | local_irq_save(flags); |
2966 | lock_tx_qs(priv); | |
2967 | ||
bb40dcbb AF |
2968 | if (phydev->link) { |
2969 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2970 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2971 | |
1da177e4 | 2972 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
2973 | * If not, we operate in half-duplex mode. |
2974 | */ | |
bb40dcbb AF |
2975 | if (phydev->duplex != priv->oldduplex) { |
2976 | new_state = 1; | |
2977 | if (!(phydev->duplex)) | |
1da177e4 | 2978 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2979 | else |
1da177e4 | 2980 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2981 | |
bb40dcbb | 2982 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2983 | } |
2984 | ||
bb40dcbb AF |
2985 | if (phydev->speed != priv->oldspeed) { |
2986 | new_state = 1; | |
2987 | switch (phydev->speed) { | |
1da177e4 | 2988 | case 1000: |
1da177e4 LT |
2989 | tempval = |
2990 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2991 | |
2992 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2993 | break; |
2994 | case 100: | |
2995 | case 10: | |
1da177e4 LT |
2996 | tempval = |
2997 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2998 | |
2999 | /* Reduced mode distinguishes | |
0977f817 JC |
3000 | * between 10 and 100 |
3001 | */ | |
7f7f5316 AF |
3002 | if (phydev->speed == SPEED_100) |
3003 | ecntrl |= ECNTRL_R100; | |
3004 | else | |
3005 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3006 | break; |
3007 | default: | |
59deab26 JP |
3008 | netif_warn(priv, link, dev, |
3009 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
3010 | phydev->speed); | |
1da177e4 LT |
3011 | break; |
3012 | } | |
3013 | ||
bb40dcbb | 3014 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3015 | } |
3016 | ||
bb40dcbb | 3017 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3018 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3019 | |
1da177e4 | 3020 | if (!priv->oldlink) { |
bb40dcbb | 3021 | new_state = 1; |
1da177e4 | 3022 | priv->oldlink = 1; |
1da177e4 | 3023 | } |
bb40dcbb AF |
3024 | } else if (priv->oldlink) { |
3025 | new_state = 1; | |
3026 | priv->oldlink = 0; | |
3027 | priv->oldspeed = 0; | |
3028 | priv->oldduplex = -1; | |
1da177e4 | 3029 | } |
1da177e4 | 3030 | |
bb40dcbb AF |
3031 | if (new_state && netif_msg_link(priv)) |
3032 | phy_print_status(phydev); | |
fba4ed03 SG |
3033 | unlock_tx_qs(priv); |
3034 | local_irq_restore(flags); | |
bb40dcbb | 3035 | } |
1da177e4 LT |
3036 | |
3037 | /* Update the hash table based on the current list of multicast | |
3038 | * addresses we subscribe to. Also, change the promiscuity of | |
3039 | * the device based on the flags (this function is called | |
0977f817 JC |
3040 | * whenever dev->flags is changed |
3041 | */ | |
1da177e4 LT |
3042 | static void gfar_set_multi(struct net_device *dev) |
3043 | { | |
22bedad3 | 3044 | struct netdev_hw_addr *ha; |
1da177e4 | 3045 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3046 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3047 | u32 tempval; |
3048 | ||
a12f801d | 3049 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3050 | /* Set RCTRL to PROM */ |
3051 | tempval = gfar_read(®s->rctrl); | |
3052 | tempval |= RCTRL_PROM; | |
3053 | gfar_write(®s->rctrl, tempval); | |
3054 | } else { | |
3055 | /* Set RCTRL to not PROM */ | |
3056 | tempval = gfar_read(®s->rctrl); | |
3057 | tempval &= ~(RCTRL_PROM); | |
3058 | gfar_write(®s->rctrl, tempval); | |
3059 | } | |
6aa20a22 | 3060 | |
a12f801d | 3061 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3062 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3063 | gfar_write(®s->igaddr0, 0xffffffff); |
3064 | gfar_write(®s->igaddr1, 0xffffffff); | |
3065 | gfar_write(®s->igaddr2, 0xffffffff); | |
3066 | gfar_write(®s->igaddr3, 0xffffffff); | |
3067 | gfar_write(®s->igaddr4, 0xffffffff); | |
3068 | gfar_write(®s->igaddr5, 0xffffffff); | |
3069 | gfar_write(®s->igaddr6, 0xffffffff); | |
3070 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3071 | gfar_write(®s->gaddr0, 0xffffffff); |
3072 | gfar_write(®s->gaddr1, 0xffffffff); | |
3073 | gfar_write(®s->gaddr2, 0xffffffff); | |
3074 | gfar_write(®s->gaddr3, 0xffffffff); | |
3075 | gfar_write(®s->gaddr4, 0xffffffff); | |
3076 | gfar_write(®s->gaddr5, 0xffffffff); | |
3077 | gfar_write(®s->gaddr6, 0xffffffff); | |
3078 | gfar_write(®s->gaddr7, 0xffffffff); | |
3079 | } else { | |
7f7f5316 AF |
3080 | int em_num; |
3081 | int idx; | |
3082 | ||
1da177e4 | 3083 | /* zero out the hash */ |
0bbaf069 KG |
3084 | gfar_write(®s->igaddr0, 0x0); |
3085 | gfar_write(®s->igaddr1, 0x0); | |
3086 | gfar_write(®s->igaddr2, 0x0); | |
3087 | gfar_write(®s->igaddr3, 0x0); | |
3088 | gfar_write(®s->igaddr4, 0x0); | |
3089 | gfar_write(®s->igaddr5, 0x0); | |
3090 | gfar_write(®s->igaddr6, 0x0); | |
3091 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3092 | gfar_write(®s->gaddr0, 0x0); |
3093 | gfar_write(®s->gaddr1, 0x0); | |
3094 | gfar_write(®s->gaddr2, 0x0); | |
3095 | gfar_write(®s->gaddr3, 0x0); | |
3096 | gfar_write(®s->gaddr4, 0x0); | |
3097 | gfar_write(®s->gaddr5, 0x0); | |
3098 | gfar_write(®s->gaddr6, 0x0); | |
3099 | gfar_write(®s->gaddr7, 0x0); | |
3100 | ||
7f7f5316 AF |
3101 | /* If we have extended hash tables, we need to |
3102 | * clear the exact match registers to prepare for | |
0977f817 JC |
3103 | * setting them |
3104 | */ | |
7f7f5316 AF |
3105 | if (priv->extended_hash) { |
3106 | em_num = GFAR_EM_NUM + 1; | |
3107 | gfar_clear_exact_match(dev); | |
3108 | idx = 1; | |
3109 | } else { | |
3110 | idx = 0; | |
3111 | em_num = 0; | |
3112 | } | |
3113 | ||
4cd24eaf | 3114 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3115 | return; |
3116 | ||
3117 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3118 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3119 | if (idx < em_num) { |
22bedad3 | 3120 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3121 | idx++; |
3122 | } else | |
22bedad3 | 3123 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3124 | } |
3125 | } | |
1da177e4 LT |
3126 | } |
3127 | ||
7f7f5316 AF |
3128 | |
3129 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3130 | * don't interfere with normal reception |
3131 | */ | |
7f7f5316 AF |
3132 | static void gfar_clear_exact_match(struct net_device *dev) |
3133 | { | |
3134 | int idx; | |
6a3c910c | 3135 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 | 3136 | |
bc4598bc | 3137 | for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) |
b6bc7650 | 3138 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3139 | } |
3140 | ||
1da177e4 LT |
3141 | /* Set the appropriate hash bit for the given addr */ |
3142 | /* The algorithm works like so: | |
3143 | * 1) Take the Destination Address (ie the multicast address), and | |
3144 | * do a CRC on it (little endian), and reverse the bits of the | |
3145 | * result. | |
3146 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3147 | * table. The table is controlled through 8 32-bit registers: | |
3148 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3149 | * gaddr7. This means that the 3 most significant bits in the | |
3150 | * hash index which gaddr register to use, and the 5 other bits | |
3151 | * indicate which bit (assuming an IBM numbering scheme, which | |
3152 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3153 | * the entry. |
3154 | */ | |
1da177e4 LT |
3155 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3156 | { | |
3157 | u32 tempval; | |
3158 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3159 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3160 | int width = priv->hash_width; |
3161 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3162 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3163 | u32 value = (1 << (31-whichbit)); |
3164 | ||
0bbaf069 | 3165 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3166 | tempval |= value; |
0bbaf069 | 3167 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3168 | } |
3169 | ||
7f7f5316 AF |
3170 | |
3171 | /* There are multiple MAC Address register pairs on some controllers | |
3172 | * This function sets the numth pair to a given address | |
3173 | */ | |
b6bc7650 JP |
3174 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3175 | const u8 *addr) | |
7f7f5316 AF |
3176 | { |
3177 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3178 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3179 | int idx; |
6a3c910c | 3180 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3181 | u32 tempval; |
f4983704 | 3182 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3183 | |
3184 | macptr += num*2; | |
3185 | ||
0977f817 JC |
3186 | /* Now copy it into the mac registers backwards, cuz |
3187 | * little endian is silly | |
3188 | */ | |
6a3c910c JP |
3189 | for (idx = 0; idx < ETH_ALEN; idx++) |
3190 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3191 | |
3192 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3193 | ||
3194 | tempval = *((u32 *) (tmpbuf + 4)); | |
3195 | ||
3196 | gfar_write(macptr+1, tempval); | |
3197 | } | |
3198 | ||
1da177e4 | 3199 | /* GFAR error interrupt handler */ |
f4983704 | 3200 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3201 | { |
f4983704 SG |
3202 | struct gfar_priv_grp *gfargrp = grp_id; |
3203 | struct gfar __iomem *regs = gfargrp->regs; | |
3204 | struct gfar_private *priv= gfargrp->priv; | |
3205 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3206 | |
3207 | /* Save ievent for future reference */ | |
f4983704 | 3208 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3209 | |
3210 | /* Clear IEVENT */ | |
f4983704 | 3211 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3212 | |
3213 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3214 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3215 | (events & IEVENT_MAG)) |
3216 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3217 | |
3218 | /* Hmm... */ | |
0bbaf069 | 3219 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
bc4598bc JC |
3220 | netdev_dbg(dev, |
3221 | "error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
59deab26 | 3222 | events, gfar_read(®s->imask)); |
1da177e4 LT |
3223 | |
3224 | /* Update the error counters */ | |
3225 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3226 | dev->stats.tx_errors++; |
1da177e4 LT |
3227 | |
3228 | if (events & IEVENT_LC) | |
09f75cd7 | 3229 | dev->stats.tx_window_errors++; |
1da177e4 | 3230 | if (events & IEVENT_CRL) |
09f75cd7 | 3231 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3232 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3233 | unsigned long flags; |
3234 | ||
59deab26 JP |
3235 | netif_dbg(priv, tx_err, dev, |
3236 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3237 | dev->stats.tx_dropped++; |
1da177e4 LT |
3238 | priv->extra_stats.tx_underrun++; |
3239 | ||
836cf7fa AV |
3240 | local_irq_save(flags); |
3241 | lock_tx_qs(priv); | |
3242 | ||
1da177e4 | 3243 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3244 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3245 | |
3246 | unlock_tx_qs(priv); | |
3247 | local_irq_restore(flags); | |
1da177e4 | 3248 | } |
59deab26 | 3249 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3250 | } |
3251 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3252 | dev->stats.rx_errors++; |
1da177e4 LT |
3253 | priv->extra_stats.rx_bsy++; |
3254 | ||
f4983704 | 3255 | gfar_receive(irq, grp_id); |
1da177e4 | 3256 | |
59deab26 JP |
3257 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3258 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3259 | } |
3260 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3261 | dev->stats.rx_errors++; |
1da177e4 LT |
3262 | priv->extra_stats.rx_babr++; |
3263 | ||
59deab26 | 3264 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3265 | } |
3266 | if (events & IEVENT_EBERR) { | |
3267 | priv->extra_stats.eberr++; | |
59deab26 | 3268 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3269 | } |
59deab26 JP |
3270 | if (events & IEVENT_RXC) |
3271 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3272 | |
3273 | if (events & IEVENT_BABT) { | |
3274 | priv->extra_stats.tx_babt++; | |
59deab26 | 3275 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3276 | } |
3277 | return IRQ_HANDLED; | |
3278 | } | |
3279 | ||
b31a1d8b AF |
3280 | static struct of_device_id gfar_match[] = |
3281 | { | |
3282 | { | |
3283 | .type = "network", | |
3284 | .compatible = "gianfar", | |
3285 | }, | |
46ceb60c SG |
3286 | { |
3287 | .compatible = "fsl,etsec2", | |
3288 | }, | |
b31a1d8b AF |
3289 | {}, |
3290 | }; | |
e72701ac | 3291 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3292 | |
1da177e4 | 3293 | /* Structure for a device driver */ |
74888760 | 3294 | static struct platform_driver gfar_driver = { |
4018294b GL |
3295 | .driver = { |
3296 | .name = "fsl-gianfar", | |
3297 | .owner = THIS_MODULE, | |
3298 | .pm = GFAR_PM_OPS, | |
3299 | .of_match_table = gfar_match, | |
3300 | }, | |
1da177e4 LT |
3301 | .probe = gfar_probe, |
3302 | .remove = gfar_remove, | |
3303 | }; | |
3304 | ||
db62f684 | 3305 | module_platform_driver(gfar_driver); |