]> git.ipfire.org Git - thirdparty/linux.git/blame - drivers/net/ethernet/freescale/ucc_geth.c
projects / thirdparty / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'x86-fpu-2020-06-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
[thirdparty/linux.git] / drivers / net / ethernet / freescale / ucc_geth.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
ce973b14 2/*
047584ce 3 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
ce973b14
LY		 4 *
5 * Author: Shlomi Gridish <gridish@freescale.com>
18a8e864 6 * Li Yang <leoli@freescale.com>
ce973b14
LY		 7 *
8 * Description:
9 * QE UCC Gigabit Ethernet Driver
ce973b14 10 */
c84d8055
JP		 11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
ce973b14
LY		 14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
9d9779e7 19#include <linux/module.h>
ce973b14
LY		 20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/spinlock.h>
25#include <linux/mm.h>
ce973b14 26#include <linux/dma-mapping.h>
ce973b14 27#include <linux/mii.h>
728de4c9 28#include <linux/phy.h>
a28777f2 29#include <linux/phy_fixed.h>
df19b6b0 30#include <linux/workqueue.h>
5af50730
RH		 31#include <linux/of_address.h>
32#include <linux/of_irq.h>
0b9da337 33#include <linux/of_mdio.h>
4b6ba8aa 34#include <linux/of_net.h>
55b6c8e9 35#include <linux/of_platform.h>
ce973b14 36
7c0f6ba6 37#include <linux/uaccess.h>
ce973b14
LY		 38#include <asm/irq.h>
39#include <asm/io.h>
7aa1aa6e
ZQ		 40#include <soc/fsl/qe/immap_qe.h>
41#include <soc/fsl/qe/qe.h>
42#include <soc/fsl/qe/ucc.h>
43#include <soc/fsl/qe/ucc_fast.h>
81abb43a 44#include <asm/machdep.h>
79dde73c 45#include <net/sch_generic.h>
ce973b14
LY		 46
47#include "ucc_geth.h"
ce973b14
LY		 48
49#undef DEBUG
50
ce973b14
LY		 51#define ugeth_printk(level, format, arg...) \
52 printk(level format "\n", ## arg)
53
54#define ugeth_dbg(format, arg...) \
55 ugeth_printk(KERN_DEBUG , format , ## arg)
ce973b14
LY		 56
57#ifdef UGETH_VERBOSE_DEBUG
58#define ugeth_vdbg ugeth_dbg
59#else
60#define ugeth_vdbg(fmt, args...) do { } while (0)
61#endif /* UGETH_VERBOSE_DEBUG */
890de95e 62#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
ce973b14 63
88a15f2e 64
ce973b14
LY		 65static DEFINE_SPINLOCK(ugeth_lock);
66
890de95e
LY		 67static struct {
68 u32 msg_enable;
69} debug = { -1 };
70
71module_param_named(debug, debug.msg_enable, int, 0);
72MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
73
18a8e864 74static struct ucc_geth_info ugeth_primary_info = {
ce973b14
LY		 75 .uf_info = {
76 .bd_mem_part = MEM_PART_SYSTEM,
77 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
78 .max_rx_buf_length = 1536,
728de4c9 79 /* adjusted at startup if max-speed 1000 */
ce973b14
LY		 80 .urfs = UCC_GETH_URFS_INIT,
81 .urfet = UCC_GETH_URFET_INIT,
82 .urfset = UCC_GETH_URFSET_INIT,
83 .utfs = UCC_GETH_UTFS_INIT,
84 .utfet = UCC_GETH_UTFET_INIT,
85 .utftt = UCC_GETH_UTFTT_INIT,
ce973b14
LY		 86 .ufpt = 256,
87 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
88 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
89 .tenc = UCC_FAST_TX_ENCODING_NRZ,
90 .renc = UCC_FAST_RX_ENCODING_NRZ,
91 .tcrc = UCC_FAST_16_BIT_CRC,
92 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
93 },
94 .numQueuesTx = 1,
95 .numQueuesRx = 1,
96 .extendedFilteringChainPointer = ((uint32_t) NULL),
97 .typeorlen = 3072 /*1536 */ ,
98 .nonBackToBackIfgPart1 = 0x40,
99 .nonBackToBackIfgPart2 = 0x60,
100 .miminumInterFrameGapEnforcement = 0x50,
101 .backToBackInterFrameGap = 0x60,
102 .mblinterval = 128,
103 .nortsrbytetime = 5,
104 .fracsiz = 1,
105 .strictpriorityq = 0xff,
106 .altBebTruncation = 0xa,
107 .excessDefer = 1,
108 .maxRetransmission = 0xf,
109 .collisionWindow = 0x37,
110 .receiveFlowControl = 1,
ac421852 111 .transmitFlowControl = 1,
ce973b14
LY		 112 .maxGroupAddrInHash = 4,
113 .maxIndAddrInHash = 4,
114 .prel = 7,
70f8002d 115 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */
ce973b14 116 .minFrameLength = 64,
70f8002d
JT		 117 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */
118 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */
ce973b14
LY		 119 .vlantype = 0x8100,
120 .ecamptr = ((uint32_t) NULL),
121 .eventRegMask = UCCE_OTHER,
122 .pausePeriod = 0xf000,
123 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
124 .bdRingLenTx = {
125 TX_BD_RING_LEN,
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN},
133
134 .bdRingLenRx = {
135 RX_BD_RING_LEN,
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN},
143
144 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
145 .largestexternallookupkeysize =
146 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
ac421852
LY		 147 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
148 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
ce973b14
LY		 150 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
151 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
152 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
153 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
154 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
ffea31ed
JT		 155 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
156 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
ce973b14
LY		 157 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
158 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159};
160
18a8e864 161static struct ucc_geth_info ugeth_info[8];
ce973b14
LY		 162
163#ifdef DEBUG
164static void mem_disp(u8 *addr, int size)
165{
166 u8 *i;
167 int size16Aling = (size >> 4) << 4;
168 int size4Aling = (size >> 2) << 2;
169 int notAlign = 0;
170 if (size % 16)
171 notAlign = 1;
172
173 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
174 printk("0x%08x: %08x %08x %08x %08x\r\n",
175 (u32) i,
176 *((u32 *) (i)),
177 *((u32 *) (i + 4)),
178 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
179 if (notAlign == 1)
180 printk("0x%08x: ", (u32) i);
181 for (; (u32) i < (u32) addr + size4Aling; i += 4)
182 printk("%08x ", *((u32 *) (i)));
183 for (; (u32) i < (u32) addr + size; i++)
64699336 184 printk("%02x", *((i)));
ce973b14
LY		 185 if (notAlign == 1)
186 printk("\r\n");
187}
188#endif /* DEBUG */
189
ce973b14
LY		 190static struct list_head *dequeue(struct list_head *lh)
191{
192 unsigned long flags;
193
1083cfe1 194 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14
LY		 195 if (!list_empty(lh)) {
196 struct list_head *node = lh->next;
197 list_del(node);
1083cfe1 198 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 199 return node;
200 } else {
1083cfe1 201 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 202 return NULL;
203 }
204}
205
6fee40e9
AF		 206static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
207 u8 __iomem *bd)
ce973b14 208{
acb600de 209 struct sk_buff *skb;
ce973b14 210
acb600de
ED		 211 skb = netdev_alloc_skb(ugeth->ndev,
212 ugeth->ug_info->uf_info.max_rx_buf_length +
213 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
50f238fd 214 if (!skb)
ce973b14
LY		 215 return NULL;
216
217 /* We need the data buffer to be aligned properly. We will reserve
218 * as many bytes as needed to align the data properly
219 */
220 skb_reserve(skb,
221 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
222 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
223 1)));
224
6fee40e9 225 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 226 dma_map_single(ugeth->dev,
ce973b14
LY		 227 skb->data,
228 ugeth->ug_info->uf_info.max_rx_buf_length +
229 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
230 DMA_FROM_DEVICE));
231
6fee40e9
AF		 232 out_be32((u32 __iomem *)bd,
233 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
ce973b14
LY		 234
235 return skb;
236}
237
18a8e864 238static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
ce973b14 239{
6fee40e9 240 u8 __iomem *bd;
ce973b14
LY		 241 u32 bd_status;
242 struct sk_buff *skb;
243 int i;
244
245 bd = ugeth->p_rx_bd_ring[rxQ];
246 i = 0;
247
248 do {
6fee40e9 249 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 250 skb = get_new_skb(ugeth, bd);
251
252 if (!skb) /* If can not allocate data buffer,
253 abort. Cleanup will be elsewhere */
254 return -ENOMEM;
255
256 ugeth->rx_skbuff[rxQ][i] = skb;
257
258 /* advance the BD pointer */
18a8e864 259 bd += sizeof(struct qe_bd);
ce973b14
LY		 260 i++;
261 } while (!(bd_status & R_W));
262
263 return 0;
264}
265
18a8e864 266static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 267 u32 *p_start,
ce973b14
LY		 268 u8 num_entries,
269 u32 thread_size,
270 u32 thread_alignment,
345f8422 271 unsigned int risc,
ce973b14
LY		 272 int skip_page_for_first_entry)
273{
274 u32 init_enet_offset;
275 u8 i;
276 int snum;
277
278 for (i = 0; i < num_entries; i++) {
279 if ((snum = qe_get_snum()) < 0) {
890de95e 280 if (netif_msg_ifup(ugeth))
c84d8055 281 pr_err("Can not get SNUM\n");
ce973b14
LY		 282 return snum;
283 }
284 if ((i == 0) && skip_page_for_first_entry)
285 /* First entry of Rx does not have page */
286 init_enet_offset = 0;
287 else {
288 init_enet_offset =
289 qe_muram_alloc(thread_size, thread_alignment);
4c35630c 290 if (IS_ERR_VALUE(init_enet_offset)) {
890de95e 291 if (netif_msg_ifup(ugeth))
c84d8055 292 pr_err("Can not allocate DPRAM memory\n");
ce973b14
LY		 293 qe_put_snum((u8) snum);
294 return -ENOMEM;
295 }
296 }
297 *(p_start++) =
298 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
299 | risc;
300 }
301
302 return 0;
303}
304
18a8e864 305static int return_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 306 u32 *p_start,
ce973b14 307 u8 num_entries,
345f8422 308 unsigned int risc,
ce973b14
LY		 309 int skip_page_for_first_entry)
310{
311 u32 init_enet_offset;
312 u8 i;
313 int snum;
314
315 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 316 u32 val = *p_start;
317
ce973b14
LY		 318 /* Check that this entry was actually valid --
319 needed in case failed in allocations */
6fee40e9 320 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 321 snum =
6fee40e9 322 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 323 ENET_INIT_PARAM_SNUM_SHIFT;
324 qe_put_snum((u8) snum);
325 if (!((i == 0) && skip_page_for_first_entry)) {
326 /* First entry of Rx does not have page */
327 init_enet_offset =
6fee40e9 328 (val & ENET_INIT_PARAM_PTR_MASK);
ce973b14
LY		 329 qe_muram_free(init_enet_offset);
330 }
6fee40e9 331 *p_start++ = 0;
ce973b14
LY		 332 }
333 }
334
335 return 0;
336}
337
338#ifdef DEBUG
18a8e864 339static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 340 u32 __iomem *p_start,
ce973b14
LY		 341 u8 num_entries,
342 u32 thread_size,
345f8422 343 unsigned int risc,
ce973b14
LY		 344 int skip_page_for_first_entry)
345{
346 u32 init_enet_offset;
347 u8 i;
348 int snum;
349
350 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 351 u32 val = in_be32(p_start);
352
ce973b14
LY		 353 /* Check that this entry was actually valid --
354 needed in case failed in allocations */
6fee40e9 355 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 356 snum =
6fee40e9 357 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 358 ENET_INIT_PARAM_SNUM_SHIFT;
359 qe_put_snum((u8) snum);
360 if (!((i == 0) && skip_page_for_first_entry)) {
361 /* First entry of Rx does not have page */
362 init_enet_offset =
363 (in_be32(p_start) &
364 ENET_INIT_PARAM_PTR_MASK);
c84d8055
JP		 365 pr_info("Init enet entry %d:\n", i);
366 pr_info("Base address: 0x%08x\n",
367 (u32)qe_muram_addr(init_enet_offset));
ce973b14
LY		 368 mem_disp(qe_muram_addr(init_enet_offset),
369 thread_size);
370 }
371 p_start++;
372 }
373 }
374
375 return 0;
376}
377#endif
378
18a8e864 379static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
ce973b14
LY		 380{
381 kfree(enet_addr_cont);
382}
383
df19b6b0 384static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
18a8e864
LY		 385{
386 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
387 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
388 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
389}
390
18a8e864 391static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
ce973b14 392{
6fee40e9 393 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14 394
c84d8055
JP		 395 if (paddr_num >= NUM_OF_PADDRS) {
396 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num);
ce973b14
LY		 397 return -EINVAL;
398 }
399
400 p_82xx_addr_filt =
6fee40e9 401 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 402 addressfiltering;
403
404 /* Writing address ff.ff.ff.ff.ff.ff disables address
405 recognition for this register */
406 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
407 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
408 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
409
410 return 0;
411}
412
18a8e864
LY		 413static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
414 u8 *p_enet_addr)
ce973b14 415{
6fee40e9 416 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 417 u32 cecr_subblock;
418
419 p_82xx_addr_filt =
6fee40e9 420 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 421 addressfiltering;
422
423 cecr_subblock =
424 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
425
426 /* Ethernet frames are defined in Little Endian mode,
3ad2f3fb 427 therefore to insert */
ce973b14 428 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
18a8e864
LY		 429
430 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
ce973b14
LY		 431
432 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
18a8e864 433 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 434}
435
ce973b14 436#ifdef DEBUG
18a8e864
LY		 437static void get_statistics(struct ucc_geth_private *ugeth,
438 struct ucc_geth_tx_firmware_statistics *
ce973b14 439 tx_firmware_statistics,
18a8e864 440 struct ucc_geth_rx_firmware_statistics *
ce973b14 441 rx_firmware_statistics,
18a8e864 442 struct ucc_geth_hardware_statistics *hardware_statistics)
ce973b14 443{
6fee40e9
AF		 444 struct ucc_fast __iomem *uf_regs;
445 struct ucc_geth __iomem *ug_regs;
18a8e864
LY		 446 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
447 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ce973b14
LY		 448
449 ug_regs = ugeth->ug_regs;
6fee40e9 450 uf_regs = (struct ucc_fast __iomem *) ug_regs;
ce973b14
LY		 451 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
452 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
453
454 /* Tx firmware only if user handed pointer and driver actually
455 gathers Tx firmware statistics */
456 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
457 tx_firmware_statistics->sicoltx =
458 in_be32(&p_tx_fw_statistics_pram->sicoltx);
459 tx_firmware_statistics->mulcoltx =
460 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
461 tx_firmware_statistics->latecoltxfr =
462 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
463 tx_firmware_statistics->frabortduecol =
464 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
465 tx_firmware_statistics->frlostinmactxer =
466 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
467 tx_firmware_statistics->carriersenseertx =
468 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
469 tx_firmware_statistics->frtxok =
470 in_be32(&p_tx_fw_statistics_pram->frtxok);
471 tx_firmware_statistics->txfrexcessivedefer =
472 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
473 tx_firmware_statistics->txpkts256 =
474 in_be32(&p_tx_fw_statistics_pram->txpkts256);
475 tx_firmware_statistics->txpkts512 =
476 in_be32(&p_tx_fw_statistics_pram->txpkts512);
477 tx_firmware_statistics->txpkts1024 =
478 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
479 tx_firmware_statistics->txpktsjumbo =
480 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
481 }
482
483 /* Rx firmware only if user handed pointer and driver actually
484 * gathers Rx firmware statistics */
485 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
486 int i;
487 rx_firmware_statistics->frrxfcser =
488 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
489 rx_firmware_statistics->fraligner =
490 in_be32(&p_rx_fw_statistics_pram->fraligner);
491 rx_firmware_statistics->inrangelenrxer =
492 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
493 rx_firmware_statistics->outrangelenrxer =
494 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
495 rx_firmware_statistics->frtoolong =
496 in_be32(&p_rx_fw_statistics_pram->frtoolong);
497 rx_firmware_statistics->runt =
498 in_be32(&p_rx_fw_statistics_pram->runt);
499 rx_firmware_statistics->verylongevent =
500 in_be32(&p_rx_fw_statistics_pram->verylongevent);
501 rx_firmware_statistics->symbolerror =
502 in_be32(&p_rx_fw_statistics_pram->symbolerror);
503 rx_firmware_statistics->dropbsy =
504 in_be32(&p_rx_fw_statistics_pram->dropbsy);
505 for (i = 0; i < 0x8; i++)
506 rx_firmware_statistics->res0[i] =
507 p_rx_fw_statistics_pram->res0[i];
508 rx_firmware_statistics->mismatchdrop =
509 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
510 rx_firmware_statistics->underpkts =
511 in_be32(&p_rx_fw_statistics_pram->underpkts);
512 rx_firmware_statistics->pkts256 =
513 in_be32(&p_rx_fw_statistics_pram->pkts256);
514 rx_firmware_statistics->pkts512 =
515 in_be32(&p_rx_fw_statistics_pram->pkts512);
516 rx_firmware_statistics->pkts1024 =
517 in_be32(&p_rx_fw_statistics_pram->pkts1024);
518 rx_firmware_statistics->pktsjumbo =
519 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
520 rx_firmware_statistics->frlossinmacer =
521 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
522 rx_firmware_statistics->pausefr =
523 in_be32(&p_rx_fw_statistics_pram->pausefr);
524 for (i = 0; i < 0x4; i++)
525 rx_firmware_statistics->res1[i] =
526 p_rx_fw_statistics_pram->res1[i];
527 rx_firmware_statistics->removevlan =
528 in_be32(&p_rx_fw_statistics_pram->removevlan);
529 rx_firmware_statistics->replacevlan =
530 in_be32(&p_rx_fw_statistics_pram->replacevlan);
531 rx_firmware_statistics->insertvlan =
532 in_be32(&p_rx_fw_statistics_pram->insertvlan);
533 }
534
535 /* Hardware only if user handed pointer and driver actually
536 gathers hardware statistics */
3bc53427
TT		 537 if (hardware_statistics &&
538 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
ce973b14
LY		 539 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
540 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
541 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
542 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
543 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
544 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
545 hardware_statistics->txok = in_be32(&ug_regs->txok);
546 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
547 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
548 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
549 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
550 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
551 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
552 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
553 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
554 }
555}
556
18a8e864 557static void dump_bds(struct ucc_geth_private *ugeth)
ce973b14
LY		 558{
559 int i;
560 int length;
561
562 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
563 if (ugeth->p_tx_bd_ring[i]) {
564 length =
565 (ugeth->ug_info->bdRingLenTx[i] *
18a8e864 566 sizeof(struct qe_bd));
c84d8055 567 pr_info("TX BDs[%d]\n", i);
ce973b14
LY		 568 mem_disp(ugeth->p_tx_bd_ring[i], length);
569 }
570 }
571 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
572 if (ugeth->p_rx_bd_ring[i]) {
573 length =
574 (ugeth->ug_info->bdRingLenRx[i] *
18a8e864 575 sizeof(struct qe_bd));
c84d8055 576 pr_info("RX BDs[%d]\n", i);
ce973b14
LY		 577 mem_disp(ugeth->p_rx_bd_ring[i], length);
578 }
579 }
580}
581
18a8e864 582static void dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 583{
584 int i;
585
c84d8055
JP		 586 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1);
587 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs);
588
589 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n",
590 (u32)&ugeth->ug_regs->maccfg1,
591 in_be32(&ugeth->ug_regs->maccfg1));
592 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n",
593 (u32)&ugeth->ug_regs->maccfg2,
594 in_be32(&ugeth->ug_regs->maccfg2));
595 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n",
596 (u32)&ugeth->ug_regs->ipgifg,
597 in_be32(&ugeth->ug_regs->ipgifg));
598 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n",
599 (u32)&ugeth->ug_regs->hafdup,
600 in_be32(&ugeth->ug_regs->hafdup));
601 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n",
602 (u32)&ugeth->ug_regs->ifctl,
603 in_be32(&ugeth->ug_regs->ifctl));
604 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n",
605 (u32)&ugeth->ug_regs->ifstat,
606 in_be32(&ugeth->ug_regs->ifstat));
607 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n",
608 (u32)&ugeth->ug_regs->macstnaddr1,
609 in_be32(&ugeth->ug_regs->macstnaddr1));
610 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n",
611 (u32)&ugeth->ug_regs->macstnaddr2,
612 in_be32(&ugeth->ug_regs->macstnaddr2));
613 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n",
614 (u32)&ugeth->ug_regs->uempr,
615 in_be32(&ugeth->ug_regs->uempr));
616 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n",
617 (u32)&ugeth->ug_regs->utbipar,
618 in_be32(&ugeth->ug_regs->utbipar));
619 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n",
620 (u32)&ugeth->ug_regs->uescr,
621 in_be16(&ugeth->ug_regs->uescr));
622 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n",
623 (u32)&ugeth->ug_regs->tx64,
624 in_be32(&ugeth->ug_regs->tx64));
625 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n",
626 (u32)&ugeth->ug_regs->tx127,
627 in_be32(&ugeth->ug_regs->tx127));
628 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n",
629 (u32)&ugeth->ug_regs->tx255,
630 in_be32(&ugeth->ug_regs->tx255));
631 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n",
632 (u32)&ugeth->ug_regs->rx64,
633 in_be32(&ugeth->ug_regs->rx64));
634 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n",
635 (u32)&ugeth->ug_regs->rx127,
636 in_be32(&ugeth->ug_regs->rx127));
637 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n",
638 (u32)&ugeth->ug_regs->rx255,
639 in_be32(&ugeth->ug_regs->rx255));
640 pr_info("txok : addr - 0x%08x, val - 0x%08x\n",
641 (u32)&ugeth->ug_regs->txok,
642 in_be32(&ugeth->ug_regs->txok));
643 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n",
644 (u32)&ugeth->ug_regs->txcf,
645 in_be16(&ugeth->ug_regs->txcf));
646 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n",
647 (u32)&ugeth->ug_regs->tmca,
648 in_be32(&ugeth->ug_regs->tmca));
649 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n",
650 (u32)&ugeth->ug_regs->tbca,
651 in_be32(&ugeth->ug_regs->tbca));
652 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n",
653 (u32)&ugeth->ug_regs->rxfok,
654 in_be32(&ugeth->ug_regs->rxfok));
655 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n",
656 (u32)&ugeth->ug_regs->rxbok,
657 in_be32(&ugeth->ug_regs->rxbok));
658 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n",
659 (u32)&ugeth->ug_regs->rbyt,
660 in_be32(&ugeth->ug_regs->rbyt));
661 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n",
662 (u32)&ugeth->ug_regs->rmca,
663 in_be32(&ugeth->ug_regs->rmca));
664 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n",
665 (u32)&ugeth->ug_regs->rbca,
666 in_be32(&ugeth->ug_regs->rbca));
667 pr_info("scar : addr - 0x%08x, val - 0x%08x\n",
668 (u32)&ugeth->ug_regs->scar,
669 in_be32(&ugeth->ug_regs->scar));
670 pr_info("scam : addr - 0x%08x, val - 0x%08x\n",
671 (u32)&ugeth->ug_regs->scam,
672 in_be32(&ugeth->ug_regs->scam));
ce973b14
LY		 673
674 if (ugeth->p_thread_data_tx) {
675 int numThreadsTxNumerical;
676 switch (ugeth->ug_info->numThreadsTx) {
677 case UCC_GETH_NUM_OF_THREADS_1:
678 numThreadsTxNumerical = 1;
679 break;
680 case UCC_GETH_NUM_OF_THREADS_2:
681 numThreadsTxNumerical = 2;
682 break;
683 case UCC_GETH_NUM_OF_THREADS_4:
684 numThreadsTxNumerical = 4;
685 break;
686 case UCC_GETH_NUM_OF_THREADS_6:
687 numThreadsTxNumerical = 6;
688 break;
689 case UCC_GETH_NUM_OF_THREADS_8:
690 numThreadsTxNumerical = 8;
691 break;
692 default:
693 numThreadsTxNumerical = 0;
694 break;
695 }
696
c84d8055
JP		 697 pr_info("Thread data TXs:\n");
698 pr_info("Base address: 0x%08x\n",
699 (u32)ugeth->p_thread_data_tx);
ce973b14 700 for (i = 0; i < numThreadsTxNumerical; i++) {
c84d8055
JP		 701 pr_info("Thread data TX[%d]:\n", i);
702 pr_info("Base address: 0x%08x\n",
703 (u32)&ugeth->p_thread_data_tx[i]);
ce973b14 704 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
18a8e864 705 sizeof(struct ucc_geth_thread_data_tx));
ce973b14
LY		 706 }
707 }
708 if (ugeth->p_thread_data_rx) {
709 int numThreadsRxNumerical;
710 switch (ugeth->ug_info->numThreadsRx) {
711 case UCC_GETH_NUM_OF_THREADS_1:
712 numThreadsRxNumerical = 1;
713 break;
714 case UCC_GETH_NUM_OF_THREADS_2:
715 numThreadsRxNumerical = 2;
716 break;
717 case UCC_GETH_NUM_OF_THREADS_4:
718 numThreadsRxNumerical = 4;
719 break;
720 case UCC_GETH_NUM_OF_THREADS_6:
721 numThreadsRxNumerical = 6;
722 break;
723 case UCC_GETH_NUM_OF_THREADS_8:
724 numThreadsRxNumerical = 8;
725 break;
726 default:
727 numThreadsRxNumerical = 0;
728 break;
729 }
730
c84d8055
JP		 731 pr_info("Thread data RX:\n");
732 pr_info("Base address: 0x%08x\n",
733 (u32)ugeth->p_thread_data_rx);
ce973b14 734 for (i = 0; i < numThreadsRxNumerical; i++) {
c84d8055
JP		 735 pr_info("Thread data RX[%d]:\n", i);
736 pr_info("Base address: 0x%08x\n",
737 (u32)&ugeth->p_thread_data_rx[i]);
ce973b14 738 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
18a8e864 739 sizeof(struct ucc_geth_thread_data_rx));
ce973b14
LY		 740 }
741 }
742 if (ugeth->p_exf_glbl_param) {
c84d8055
JP		 743 pr_info("EXF global param:\n");
744 pr_info("Base address: 0x%08x\n",
745 (u32)ugeth->p_exf_glbl_param);
ce973b14
LY		 746 mem_disp((u8 *) ugeth->p_exf_glbl_param,
747 sizeof(*ugeth->p_exf_glbl_param));
748 }
749 if (ugeth->p_tx_glbl_pram) {
c84d8055
JP		 750 pr_info("TX global param:\n");
751 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram);
752 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n",
753 (u32)&ugeth->p_tx_glbl_pram->temoder,
754 in_be16(&ugeth->p_tx_glbl_pram->temoder));
755 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n",
756 (u32)&ugeth->p_tx_glbl_pram->sqptr,
757 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
758 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n",
759 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer,
760 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer));
761 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n",
762 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr,
763 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
764 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n",
765 (u32)&ugeth->p_tx_glbl_pram->tstate,
766 in_be32(&ugeth->p_tx_glbl_pram->tstate));
767 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n",
768 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0],
769 ugeth->p_tx_glbl_pram->iphoffset[0]);
770 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n",
771 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1],
772 ugeth->p_tx_glbl_pram->iphoffset[1]);
773 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n",
774 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2],
775 ugeth->p_tx_glbl_pram->iphoffset[2]);
776 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n",
777 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3],
778 ugeth->p_tx_glbl_pram->iphoffset[3]);
779 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n",
780 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4],
781 ugeth->p_tx_glbl_pram->iphoffset[4]);
782 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n",
783 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5],
784 ugeth->p_tx_glbl_pram->iphoffset[5]);
785 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n",
786 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6],
787 ugeth->p_tx_glbl_pram->iphoffset[6]);
788 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n",
789 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7],
790 ugeth->p_tx_glbl_pram->iphoffset[7]);
791 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n",
792 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0],
793 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
794 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n",
795 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1],
796 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
797 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n",
798 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2],
799 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
800 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n",
801 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3],
802 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
803 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n",
804 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4],
805 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
806 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n",
807 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5],
808 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
809 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n",
810 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6],
811 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
812 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n",
813 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7],
814 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
815 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n",
816 (u32)&ugeth->p_tx_glbl_pram->tqptr,
817 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
ce973b14
LY		 818 }
819 if (ugeth->p_rx_glbl_pram) {
c84d8055
JP		 820 pr_info("RX global param:\n");
821 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram);
822 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n",
823 (u32)&ugeth->p_rx_glbl_pram->remoder,
824 in_be32(&ugeth->p_rx_glbl_pram->remoder));
825 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n",
826 (u32)&ugeth->p_rx_glbl_pram->rqptr,
827 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
828 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n",
829 (u32)&ugeth->p_rx_glbl_pram->typeorlen,
830 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
831 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n",
832 (u32)&ugeth->p_rx_glbl_pram->rxgstpack,
833 ugeth->p_rx_glbl_pram->rxgstpack);
834 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n",
835 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
836 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
837 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n",
838 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr,
839 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
840 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n",
841 (u32)&ugeth->p_rx_glbl_pram->rstate,
842 ugeth->p_rx_glbl_pram->rstate);
843 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n",
844 (u32)&ugeth->p_rx_glbl_pram->mrblr,
845 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
846 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n",
847 (u32)&ugeth->p_rx_glbl_pram->rbdqptr,
848 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
849 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n",
850 (u32)&ugeth->p_rx_glbl_pram->mflr,
851 in_be16(&ugeth->p_rx_glbl_pram->mflr));
852 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n",
853 (u32)&ugeth->p_rx_glbl_pram->minflr,
854 in_be16(&ugeth->p_rx_glbl_pram->minflr));
855 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n",
856 (u32)&ugeth->p_rx_glbl_pram->maxd1,
857 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
858 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n",
859 (u32)&ugeth->p_rx_glbl_pram->maxd2,
860 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
861 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n",
862 (u32)&ugeth->p_rx_glbl_pram->ecamptr,
863 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
864 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n",
865 (u32)&ugeth->p_rx_glbl_pram->l2qt,
866 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
867 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n",
868 (u32)&ugeth->p_rx_glbl_pram->l3qt[0],
869 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
870 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n",
871 (u32)&ugeth->p_rx_glbl_pram->l3qt[1],
872 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
873 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n",
874 (u32)&ugeth->p_rx_glbl_pram->l3qt[2],
875 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
876 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n",
877 (u32)&ugeth->p_rx_glbl_pram->l3qt[3],
878 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
879 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n",
880 (u32)&ugeth->p_rx_glbl_pram->l3qt[4],
881 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
882 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n",
883 (u32)&ugeth->p_rx_glbl_pram->l3qt[5],
884 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
885 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n",
886 (u32)&ugeth->p_rx_glbl_pram->l3qt[6],
887 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
888 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n",
889 (u32)&ugeth->p_rx_glbl_pram->l3qt[7],
890 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
891 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n",
892 (u32)&ugeth->p_rx_glbl_pram->vlantype,
893 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
894 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n",
895 (u32)&ugeth->p_rx_glbl_pram->vlantci,
896 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
ce973b14 897 for (i = 0; i < 64; i++)
c84d8055
JP		 898 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n",
899 i,
900 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i],
901 ugeth->p_rx_glbl_pram->addressfiltering[i]);
902 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n",
903 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam,
904 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
ce973b14
LY		 905 }
906 if (ugeth->p_send_q_mem_reg) {
c84d8055
JP		 907 pr_info("Send Q memory registers:\n");
908 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg);
ce973b14 909 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
c84d8055
JP		 910 pr_info("SQQD[%d]:\n", i);
911 pr_info("Base address: 0x%08x\n",
912 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]);
ce973b14 913 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
18a8e864 914 sizeof(struct ucc_geth_send_queue_qd));
ce973b14
LY		 915 }
916 }
917 if (ugeth->p_scheduler) {
c84d8055
JP		 918 pr_info("Scheduler:\n");
919 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler);
ce973b14
LY		 920 mem_disp((u8 *) ugeth->p_scheduler,
921 sizeof(*ugeth->p_scheduler));
922 }
923 if (ugeth->p_tx_fw_statistics_pram) {
c84d8055
JP		 924 pr_info("TX FW statistics pram:\n");
925 pr_info("Base address: 0x%08x\n",
926 (u32)ugeth->p_tx_fw_statistics_pram);
ce973b14
LY		 927 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
928 sizeof(*ugeth->p_tx_fw_statistics_pram));
929 }
930 if (ugeth->p_rx_fw_statistics_pram) {
c84d8055
JP		 931 pr_info("RX FW statistics pram:\n");
932 pr_info("Base address: 0x%08x\n",
933 (u32)ugeth->p_rx_fw_statistics_pram);
ce973b14
LY		 934 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
935 sizeof(*ugeth->p_rx_fw_statistics_pram));
936 }
937 if (ugeth->p_rx_irq_coalescing_tbl) {
c84d8055
JP		 938 pr_info("RX IRQ coalescing tables:\n");
939 pr_info("Base address: 0x%08x\n",
940 (u32)ugeth->p_rx_irq_coalescing_tbl);
ce973b14 941 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
c84d8055
JP		 942 pr_info("RX IRQ coalescing table entry[%d]:\n", i);
943 pr_info("Base address: 0x%08x\n",
944 (u32)&ugeth->p_rx_irq_coalescing_tbl->
945 coalescingentry[i]);
946 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n",
947 (u32)&ugeth->p_rx_irq_coalescing_tbl->
948 coalescingentry[i].interruptcoalescingmaxvalue,
949 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
950 coalescingentry[i].
951 interruptcoalescingmaxvalue));
952 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n",
953 (u32)&ugeth->p_rx_irq_coalescing_tbl->
954 coalescingentry[i].interruptcoalescingcounter,
955 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
956 coalescingentry[i].
957 interruptcoalescingcounter));
ce973b14
LY		 958 }
959 }
960 if (ugeth->p_rx_bd_qs_tbl) {
c84d8055
JP		 961 pr_info("RX BD QS tables:\n");
962 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl);
ce973b14 963 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
c84d8055
JP		 964 pr_info("RX BD QS table[%d]:\n", i);
965 pr_info("Base address: 0x%08x\n",
966 (u32)&ugeth->p_rx_bd_qs_tbl[i]);
967 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n",
968 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
969 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
970 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n",
971 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr,
972 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
973 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n",
974 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
975 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
976 externalbdbaseptr));
977 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n",
978 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
979 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
980 pr_info("ucode RX Prefetched BDs:\n");
981 pr_info("Base address: 0x%08x\n",
982 (u32)qe_muram_addr(in_be32
983 (&ugeth->p_rx_bd_qs_tbl[i].
984 bdbaseptr)));
ce973b14
LY		 985 mem_disp((u8 *)
986 qe_muram_addr(in_be32
987 (&ugeth->p_rx_bd_qs_tbl[i].
988 bdbaseptr)),
18a8e864 989 sizeof(struct ucc_geth_rx_prefetched_bds));
ce973b14
LY		 990 }
991 }
992 if (ugeth->p_init_enet_param_shadow) {
993 int size;
c84d8055
JP		 994 pr_info("Init enet param shadow:\n");
995 pr_info("Base address: 0x%08x\n",
996 (u32) ugeth->p_init_enet_param_shadow);
ce973b14
LY		 997 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
998 sizeof(*ugeth->p_init_enet_param_shadow));
999
18a8e864 1000 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 1001 if (ugeth->ug_info->rxExtendedFiltering) {
1002 size +=
1003 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1004 if (ugeth->ug_info->largestexternallookupkeysize ==
1005 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1006 size +=
1007 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1008 if (ugeth->ug_info->largestexternallookupkeysize ==
1009 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1010 size +=
1011 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1012 }
1013
1014 dump_init_enet_entries(ugeth,
1015 &(ugeth->p_init_enet_param_shadow->
1016 txthread[0]),
1017 ENET_INIT_PARAM_MAX_ENTRIES_TX,
18a8e864 1018 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 1019 ugeth->ug_info->riscTx, 0);
1020 dump_init_enet_entries(ugeth,
1021 &(ugeth->p_init_enet_param_shadow->
1022 rxthread[0]),
1023 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1024 ugeth->ug_info->riscRx, 1);
1025 }
1026}
1027#endif /* DEBUG */
1028
6fee40e9
AF		 1029static void init_default_reg_vals(u32 __iomem *upsmr_register,
1030 u32 __iomem *maccfg1_register,
1031 u32 __iomem *maccfg2_register)
ce973b14
LY		 1032{
1033 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1034 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1035 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1036}
1037
1038static int init_half_duplex_params(int alt_beb,
1039 int back_pressure_no_backoff,
1040 int no_backoff,
1041 int excess_defer,
1042 u8 alt_beb_truncation,
1043 u8 max_retransmissions,
1044 u8 collision_window,
6fee40e9 1045 u32 __iomem *hafdup_register)
ce973b14
LY		 1046{
1047 u32 value = 0;
1048
1049 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1050 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1051 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1052 return -EINVAL;
1053
1054 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1055
1056 if (alt_beb)
1057 value |= HALFDUP_ALT_BEB;
1058 if (back_pressure_no_backoff)
1059 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1060 if (no_backoff)
1061 value |= HALFDUP_NO_BACKOFF;
1062 if (excess_defer)
1063 value |= HALFDUP_EXCESSIVE_DEFER;
1064
1065 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1066
1067 value |= collision_window;
1068
1069 out_be32(hafdup_register, value);
1070 return 0;
1071}
1072
1073static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1074 u8 non_btb_ipg,
1075 u8 min_ifg,
1076 u8 btb_ipg,
6fee40e9 1077 u32 __iomem *ipgifg_register)
ce973b14
LY		 1078{
1079 u32 value = 0;
1080
1081 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1082 IPG part 2 */
1083 if (non_btb_cs_ipg > non_btb_ipg)
1084 return -EINVAL;
1085
1086 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1087 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1088 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1089 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1090 return -EINVAL;
1091
1092 value |=
1093 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1094 IPGIFG_NBTB_CS_IPG_MASK);
1095 value |=
1096 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1097 IPGIFG_NBTB_IPG_MASK);
1098 value |=
1099 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1100 IPGIFG_MIN_IFG_MASK);
1101 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1102
1103 out_be32(ipgifg_register, value);
1104 return 0;
1105}
1106
ac421852 1107int init_flow_control_params(u32 automatic_flow_control_mode,
ce973b14
LY		 1108 int rx_flow_control_enable,
1109 int tx_flow_control_enable,
1110 u16 pause_period,
1111 u16 extension_field,
6fee40e9
AF		 1112 u32 __iomem *upsmr_register,
1113 u32 __iomem *uempr_register,
1114 u32 __iomem *maccfg1_register)
ce973b14
LY		 1115{
1116 u32 value = 0;
1117
1118 /* Set UEMPR register */
1119 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1120 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1121 out_be32(uempr_register, value);
1122
1123 /* Set UPSMR register */
3bc53427 1124 setbits32(upsmr_register, automatic_flow_control_mode);
ce973b14
LY		 1125
1126 value = in_be32(maccfg1_register);
1127 if (rx_flow_control_enable)
1128 value |= MACCFG1_FLOW_RX;
1129 if (tx_flow_control_enable)
1130 value |= MACCFG1_FLOW_TX;
1131 out_be32(maccfg1_register, value);
1132
1133 return 0;
1134}
1135
1136static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1137 int auto_zero_hardware_statistics,
6fee40e9
AF		 1138 u32 __iomem *upsmr_register,
1139 u16 __iomem *uescr_register)
ce973b14 1140{
ce973b14 1141 u16 uescr_value = 0;
3bc53427 1142
ce973b14 1143 /* Enable hardware statistics gathering if requested */
3bc53427
TT		 1144 if (enable_hardware_statistics)
1145 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
ce973b14
LY		 1146
1147 /* Clear hardware statistics counters */
1148 uescr_value = in_be16(uescr_register);
1149 uescr_value |= UESCR_CLRCNT;
1150 /* Automatically zero hardware statistics counters on read,
1151 if requested */
1152 if (auto_zero_hardware_statistics)
1153 uescr_value |= UESCR_AUTOZ;
1154 out_be16(uescr_register, uescr_value);
1155
1156 return 0;
1157}
1158
1159static int init_firmware_statistics_gathering_mode(int
1160 enable_tx_firmware_statistics,
1161 int enable_rx_firmware_statistics,
6fee40e9 1162 u32 __iomem *tx_rmon_base_ptr,
ce973b14 1163 u32 tx_firmware_statistics_structure_address,
6fee40e9 1164 u32 __iomem *rx_rmon_base_ptr,
ce973b14 1165 u32 rx_firmware_statistics_structure_address,
6fee40e9
AF		 1166 u16 __iomem *temoder_register,
1167 u32 __iomem *remoder_register)
ce973b14
LY		 1168{
1169 /* Note: this function does not check if */
1170 /* the parameters it receives are NULL */
ce973b14
LY		 1171
1172 if (enable_tx_firmware_statistics) {
1173 out_be32(tx_rmon_base_ptr,
1174 tx_firmware_statistics_structure_address);
3bc53427 1175 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1176 }
1177
1178 if (enable_rx_firmware_statistics) {
1179 out_be32(rx_rmon_base_ptr,
1180 rx_firmware_statistics_structure_address);
3bc53427 1181 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1182 }
1183
1184 return 0;
1185}
1186
1187static int init_mac_station_addr_regs(u8 address_byte_0,
1188 u8 address_byte_1,
1189 u8 address_byte_2,
1190 u8 address_byte_3,
1191 u8 address_byte_4,
1192 u8 address_byte_5,
6fee40e9
AF		 1193 u32 __iomem *macstnaddr1_register,
1194 u32 __iomem *macstnaddr2_register)
ce973b14
LY		 1195{
1196 u32 value = 0;
1197
1198 /* Example: for a station address of 0x12345678ABCD, */
1199 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1200
1201 /* MACSTNADDR1 Register: */
1202
1203 /* 0 7 8 15 */
1204 /* station address byte 5 station address byte 4 */
1205 /* 16 23 24 31 */
1206 /* station address byte 3 station address byte 2 */
1207 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1208 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1209 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1210 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1211
1212 out_be32(macstnaddr1_register, value);
1213
1214 /* MACSTNADDR2 Register: */
1215
1216 /* 0 7 8 15 */
1217 /* station address byte 1 station address byte 0 */
1218 /* 16 23 24 31 */
1219 /* reserved reserved */
1220 value = 0;
1221 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1222 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1223
1224 out_be32(macstnaddr2_register, value);
1225
1226 return 0;
1227}
1228
ce973b14 1229static int init_check_frame_length_mode(int length_check,
6fee40e9 1230 u32 __iomem *maccfg2_register)
ce973b14
LY		 1231{
1232 u32 value = 0;
1233
1234 value = in_be32(maccfg2_register);
1235
1236 if (length_check)
1237 value |= MACCFG2_LC;
1238 else
1239 value &= ~MACCFG2_LC;
1240
1241 out_be32(maccfg2_register, value);
1242 return 0;
1243}
1244
1245static int init_preamble_length(u8 preamble_length,
6fee40e9 1246 u32 __iomem *maccfg2_register)
ce973b14 1247{
ce973b14
LY		 1248 if ((preamble_length < 3) || (preamble_length > 7))
1249 return -EINVAL;
1250
3bc53427
TT		 1251 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1252 preamble_length << MACCFG2_PREL_SHIFT);
1253
ce973b14
LY		 1254 return 0;
1255}
1256
ce973b14
LY		 1257static int init_rx_parameters(int reject_broadcast,
1258 int receive_short_frames,
6fee40e9 1259 int promiscuous, u32 __iomem *upsmr_register)
ce973b14
LY		 1260{
1261 u32 value = 0;
1262
1263 value = in_be32(upsmr_register);
1264
1265 if (reject_broadcast)
3bc53427 1266 value |= UCC_GETH_UPSMR_BRO;
ce973b14 1267 else
3bc53427 1268 value &= ~UCC_GETH_UPSMR_BRO;
ce973b14
LY		 1269
1270 if (receive_short_frames)
3bc53427 1271 value |= UCC_GETH_UPSMR_RSH;
ce973b14 1272 else
3bc53427 1273 value &= ~UCC_GETH_UPSMR_RSH;
ce973b14
LY		 1274
1275 if (promiscuous)
3bc53427 1276 value |= UCC_GETH_UPSMR_PRO;
ce973b14 1277 else
3bc53427 1278 value &= ~UCC_GETH_UPSMR_PRO;
ce973b14
LY		 1279
1280 out_be32(upsmr_register, value);
1281
1282 return 0;
1283}
1284
1285static int init_max_rx_buff_len(u16 max_rx_buf_len,
6fee40e9 1286 u16 __iomem *mrblr_register)
ce973b14
LY		 1287{
1288 /* max_rx_buf_len value must be a multiple of 128 */
8e95a202
JP		 1289 if ((max_rx_buf_len == 0) ||
1290 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
ce973b14
LY		 1291 return -EINVAL;
1292
1293 out_be16(mrblr_register, max_rx_buf_len);
1294 return 0;
1295}
1296
1297static int init_min_frame_len(u16 min_frame_length,
6fee40e9
AF		 1298 u16 __iomem *minflr_register,
1299 u16 __iomem *mrblr_register)
ce973b14
LY		 1300{
1301 u16 mrblr_value = 0;
1302
1303 mrblr_value = in_be16(mrblr_register);
1304 if (min_frame_length >= (mrblr_value - 4))
1305 return -EINVAL;
1306
1307 out_be16(minflr_register, min_frame_length);
1308 return 0;
1309}
1310
18a8e864 1311static int adjust_enet_interface(struct ucc_geth_private *ugeth)
ce973b14 1312{
18a8e864 1313 struct ucc_geth_info *ug_info;
6fee40e9
AF		 1314 struct ucc_geth __iomem *ug_regs;
1315 struct ucc_fast __iomem *uf_regs;
728de4c9 1316 int ret_val;
81abb43a 1317 u32 upsmr, maccfg2;
ce973b14
LY		 1318 u16 value;
1319
b39d66a8 1320 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 1321
1322 ug_info = ugeth->ug_info;
1323 ug_regs = ugeth->ug_regs;
1324 uf_regs = ugeth->uccf->uf_regs;
1325
ce973b14
LY		 1326 /* Set MACCFG2 */
1327 maccfg2 = in_be32(&ug_regs->maccfg2);
1328 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
728de4c9
KP		 1329 if ((ugeth->max_speed == SPEED_10) ||
1330 (ugeth->max_speed == SPEED_100))
ce973b14 1331 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
728de4c9 1332 else if (ugeth->max_speed == SPEED_1000)
ce973b14
LY		 1333 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1334 maccfg2 |= ug_info->padAndCrc;
1335 out_be32(&ug_regs->maccfg2, maccfg2);
1336
1337 /* Set UPSMR */
1338 upsmr = in_be32(&uf_regs->upsmr);
3bc53427
TT		 1339 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1340 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
728de4c9
KP		 1341 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1342 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1343 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1344 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1345 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9 1346 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
cef309cf
HS		 1347 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1348 upsmr |= UCC_GETH_UPSMR_RPM;
728de4c9
KP		 1349 switch (ugeth->max_speed) {
1350 case SPEED_10:
3bc53427 1351 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9
KP		 1352 /* FALLTHROUGH */
1353 case SPEED_100:
1354 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
3bc53427 1355 upsmr |= UCC_GETH_UPSMR_RMM;
728de4c9
KP		 1356 }
1357 }
1358 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1359 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
3bc53427 1360 upsmr |= UCC_GETH_UPSMR_TBIM;
728de4c9 1361 }
047584ce
HW		 1362 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1363 upsmr |= UCC_GETH_UPSMR_SGMM;
1364
ce973b14
LY		 1365 out_be32(&uf_regs->upsmr, upsmr);
1366
ce973b14
LY		 1367 /* Disable autonegotiation in tbi mode, because by default it
1368 comes up in autonegotiation mode. */
1369 /* Note that this depends on proper setting in utbipar register. */
728de4c9
KP		 1370 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1371 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
81abb43a
LYB		 1372 struct ucc_geth_info *ug_info = ugeth->ug_info;
1373 struct phy_device *tbiphy;
1374
1375 if (!ug_info->tbi_node)
c84d8055 1376 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n");
81abb43a
LYB		 1377
1378 tbiphy = of_phy_find_device(ug_info->tbi_node);
1379 if (!tbiphy)
c84d8055 1380 pr_warn("Could not get TBI device\n");
81abb43a
LYB		 1381
1382 value = phy_read(tbiphy, ENET_TBI_MII_CR);
ce973b14 1383 value &= ~0x1000; /* Turn off autonegotiation */
81abb43a 1384 phy_write(tbiphy, ENET_TBI_MII_CR, value);
04d53b20 1385
e5a03bfd 1386 put_device(&tbiphy->mdio.dev);
ce973b14
LY		 1387 }
1388
1389 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1390
1391 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1392 if (ret_val != 0) {
890de95e 1393 if (netif_msg_probe(ugeth))
c84d8055 1394 pr_err("Preamble length must be between 3 and 7 inclusive\n");
ce973b14
LY		 1395 return ret_val;
1396 }
1397
1398 return 0;
1399}
1400
7de8ee78
AV		 1401static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1402{
1403 struct ucc_fast_private *uccf;
1404 u32 cecr_subblock;
1405 u32 temp;
1406 int i = 10;
1407
1408 uccf = ugeth->uccf;
1409
1410 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1411 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1412 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1413
1414 /* Issue host command */
1415 cecr_subblock =
1416 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1417 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1418 QE_CR_PROTOCOL_ETHERNET, 0);
1419
1420 /* Wait for command to complete */
1421 do {
1422 msleep(10);
1423 temp = in_be32(uccf->p_ucce);
1424 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1425
1426 uccf->stopped_tx = 1;
1427
1428 return 0;
1429}
1430
1431static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1432{
1433 struct ucc_fast_private *uccf;
1434 u32 cecr_subblock;
1435 u8 temp;
1436 int i = 10;
1437
1438 uccf = ugeth->uccf;
1439
1440 /* Clear acknowledge bit */
1441 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1442 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1443 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1444
1445 /* Keep issuing command and checking acknowledge bit until
1446 it is asserted, according to spec */
1447 do {
1448 /* Issue host command */
1449 cecr_subblock =
1450 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1451 ucc_num);
1452 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1453 QE_CR_PROTOCOL_ETHERNET, 0);
1454 msleep(10);
1455 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1456 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1457
1458 uccf->stopped_rx = 1;
1459
1460 return 0;
1461}
1462
1463static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1464{
1465 struct ucc_fast_private *uccf;
1466 u32 cecr_subblock;
1467
1468 uccf = ugeth->uccf;
1469
1470 cecr_subblock =
1471 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1472 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1473 uccf->stopped_tx = 0;
1474
1475 return 0;
1476}
1477
1478static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1479{
1480 struct ucc_fast_private *uccf;
1481 u32 cecr_subblock;
1482
1483 uccf = ugeth->uccf;
1484
1485 cecr_subblock =
1486 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1487 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1488 0);
1489 uccf->stopped_rx = 0;
1490
1491 return 0;
1492}
1493
1494static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1495{
1496 struct ucc_fast_private *uccf;
1497 int enabled_tx, enabled_rx;
1498
1499 uccf = ugeth->uccf;
1500
1501 /* check if the UCC number is in range. */
1502 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1503 if (netif_msg_probe(ugeth))
c84d8055 1504 pr_err("ucc_num out of range\n");
7de8ee78
AV		 1505 return -EINVAL;
1506 }
1507
1508 enabled_tx = uccf->enabled_tx;
1509 enabled_rx = uccf->enabled_rx;
1510
1511 /* Get Tx and Rx going again, in case this channel was actively
1512 disabled. */
1513 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1514 ugeth_restart_tx(ugeth);
1515 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1516 ugeth_restart_rx(ugeth);
1517
1518 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1519
1520 return 0;
1521
1522}
1523
1524static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1525{
1526 struct ucc_fast_private *uccf;
1527
1528 uccf = ugeth->uccf;
1529
1530 /* check if the UCC number is in range. */
1531 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1532 if (netif_msg_probe(ugeth))
c84d8055 1533 pr_err("ucc_num out of range\n");
7de8ee78
AV		 1534 return -EINVAL;
1535 }
1536
1537 /* Stop any transmissions */
1538 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1539 ugeth_graceful_stop_tx(ugeth);
1540
1541 /* Stop any receptions */
1542 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1543 ugeth_graceful_stop_rx(ugeth);
1544
1545 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1546
1547 return 0;
1548}
1549
864fdf88
AV		 1550static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1551{
79dde73c
VL		 1552 /* Prevent any further xmits */
1553 netif_tx_stop_all_queues(ugeth->ndev);
864fdf88
AV		 1554
1555 /* Disable the interrupt to avoid NAPI rescheduling. */
1556 disable_irq(ugeth->ug_info->uf_info.irq);
1557
1558 /* Stop NAPI, and possibly wait for its completion. */
1559 napi_disable(&ugeth->napi);
1560}
1561
1562static void ugeth_activate(struct ucc_geth_private *ugeth)
1563{
1564 napi_enable(&ugeth->napi);
1565 enable_irq(ugeth->ug_info->uf_info.irq);
79dde73c
VL		 1566
1567 /* allow to xmit again */
1568 netif_tx_wake_all_queues(ugeth->ndev);
1569 __netdev_watchdog_up(ugeth->ndev);
864fdf88
AV		 1570}
1571
ce973b14
LY		 1572/* Called every time the controller might need to be made
1573 * aware of new link state. The PHY code conveys this
1574 * information through variables in the ugeth structure, and this
1575 * function converts those variables into the appropriate
1576 * register values, and can bring down the device if needed.
1577 */
728de4c9 1578
ce973b14
LY		 1579static void adjust_link(struct net_device *dev)
1580{
18a8e864 1581 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9
AF		 1582 struct ucc_geth __iomem *ug_regs;
1583 struct ucc_fast __iomem *uf_regs;
728de4c9 1584 struct phy_device *phydev = ugeth->phydev;
728de4c9 1585 int new_state = 0;
ce973b14
LY		 1586
1587 ug_regs = ugeth->ug_regs;
728de4c9 1588 uf_regs = ugeth->uccf->uf_regs;
ce973b14 1589
728de4c9
KP		 1590 if (phydev->link) {
1591 u32 tempval = in_be32(&ug_regs->maccfg2);
1592 u32 upsmr = in_be32(&uf_regs->upsmr);
ce973b14
LY		 1593 /* Now we make sure that we can be in full duplex mode.
1594 * If not, we operate in half-duplex mode. */
728de4c9
KP		 1595 if (phydev->duplex != ugeth->oldduplex) {
1596 new_state = 1;
1597 if (!(phydev->duplex))
ce973b14 1598 tempval &= ~(MACCFG2_FDX);
728de4c9 1599 else
ce973b14 1600 tempval |= MACCFG2_FDX;
728de4c9 1601 ugeth->oldduplex = phydev->duplex;
ce973b14
LY		 1602 }
1603
728de4c9
KP		 1604 if (phydev->speed != ugeth->oldspeed) {
1605 new_state = 1;
1606 switch (phydev->speed) {
1607 case SPEED_1000:
1608 tempval = ((tempval &
1609 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1610 MACCFG2_INTERFACE_MODE_BYTE);
a1862a53 1611 break;
728de4c9
KP		 1612 case SPEED_100:
1613 case SPEED_10:
1614 tempval = ((tempval &
1615 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1616 MACCFG2_INTERFACE_MODE_NIBBLE);
1617 /* if reduced mode, re-set UPSMR.R10M */
1618 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1619 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1620 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1621 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1622 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9
KP		 1623 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1624 if (phydev->speed == SPEED_10)
3bc53427 1625 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9 1626 else
3bc53427 1627 upsmr &= ~UCC_GETH_UPSMR_R10M;
728de4c9 1628 }
ce973b14
LY		 1629 break;
1630 default:
728de4c9 1631 if (netif_msg_link(ugeth))
c84d8055 1632 pr_warn(
728de4c9
KP		 1633 "%s: Ack! Speed (%d) is not 10/100/1000!",
1634 dev->name, phydev->speed);
ce973b14
LY		 1635 break;
1636 }
728de4c9 1637 ugeth->oldspeed = phydev->speed;
ce973b14
LY		 1638 }
1639
1640 if (!ugeth->oldlink) {
728de4c9 1641 new_state = 1;
ce973b14 1642 ugeth->oldlink = 1;
ce973b14 1643 }
08fafd84
AV		 1644
1645 if (new_state) {
1646 /*
1647 * To change the MAC configuration we need to disable
1648 * the controller. To do so, we have to either grab
1649 * ugeth->lock, which is a bad idea since 'graceful
1650 * stop' commands might take quite a while, or we can
1651 * quiesce driver's activity.
1652 */
1653 ugeth_quiesce(ugeth);
1654 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1655
1656 out_be32(&ug_regs->maccfg2, tempval);
1657 out_be32(&uf_regs->upsmr, upsmr);
1658
1659 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1660 ugeth_activate(ugeth);
1661 }
728de4c9
KP		 1662 } else if (ugeth->oldlink) {
1663 new_state = 1;
ce973b14
LY		 1664 ugeth->oldlink = 0;
1665 ugeth->oldspeed = 0;
1666 ugeth->oldduplex = -1;
ce973b14 1667 }
728de4c9
KP		 1668
1669 if (new_state && netif_msg_link(ugeth))
1670 phy_print_status(phydev);
ce973b14
LY		 1671}
1672
fb1001f3
HW		 1673/* Initialize TBI PHY interface for communicating with the
1674 * SERDES lynx PHY on the chip. We communicate with this PHY
1675 * through the MDIO bus on each controller, treating it as a
1676 * "normal" PHY at the address found in the UTBIPA register. We assume
1677 * that the UTBIPA register is valid. Either the MDIO bus code will set
1678 * it to a value that doesn't conflict with other PHYs on the bus, or the
1679 * value doesn't matter, as there are no other PHYs on the bus.
1680 */
1681static void uec_configure_serdes(struct net_device *dev)
1682{
1683 struct ucc_geth_private *ugeth = netdev_priv(dev);
1684 struct ucc_geth_info *ug_info = ugeth->ug_info;
1685 struct phy_device *tbiphy;
1686
1687 if (!ug_info->tbi_node) {
1688 dev_warn(&dev->dev, "SGMII mode requires that the device "
1689 "tree specify a tbi-handle\n");
1690 return;
1691 }
1692
1693 tbiphy = of_phy_find_device(ug_info->tbi_node);
1694 if (!tbiphy) {
1695 dev_err(&dev->dev, "error: Could not get TBI device\n");
1696 return;
1697 }
1698
1699 /*
1700 * If the link is already up, we must already be ok, and don't need to
1701 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1702 * everything for us? Resetting it takes the link down and requires
1703 * several seconds for it to come back.
1704 */
04d53b20 1705 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) {
e5a03bfd 1706 put_device(&tbiphy->mdio.dev);
fb1001f3 1707 return;
04d53b20 1708 }
fb1001f3
HW		 1709
1710 /* Single clk mode, mii mode off(for serdes communication) */
1711 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1712
1713 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1714
1715 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
04d53b20 1716
5e431650 1717 put_device(&tbiphy->mdio.dev);
fb1001f3
HW		 1718}
1719
ce973b14
LY		 1720/* Configure the PHY for dev.
1721 * returns 0 if success. -1 if failure
1722 */
1723static int init_phy(struct net_device *dev)
1724{
728de4c9 1725 struct ucc_geth_private *priv = netdev_priv(dev);
61fa9dcf 1726 struct ucc_geth_info *ug_info = priv->ug_info;
728de4c9 1727 struct phy_device *phydev;
ce973b14 1728
728de4c9
KP		 1729 priv->oldlink = 0;
1730 priv->oldspeed = 0;
1731 priv->oldduplex = -1;
ce973b14 1732
0b9da337
GL		 1733 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1734 priv->phy_interface);
1735 if (!phydev) {
3104a6ff 1736 dev_err(&dev->dev, "Could not attach to PHY\n");
0b9da337 1737 return -ENODEV;
ce973b14
LY		 1738 }
1739
047584ce
HW		 1740 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1741 uec_configure_serdes(dev);
1742
3c1bcc86 1743 phy_set_max_speed(phydev, priv->max_speed);
68dc44af 1744
728de4c9 1745 priv->phydev = phydev;
ce973b14
LY		 1746
1747 return 0;
ce973b14
LY		 1748}
1749
18a8e864 1750static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 1751{
1752#ifdef DEBUG
1753 ucc_fast_dump_regs(ugeth->uccf);
1754 dump_regs(ugeth);
1755 dump_bds(ugeth);
1756#endif
1757}
1758
18a8e864 1759static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ce973b14 1760 ugeth,
18a8e864 1761 enum enet_addr_type
ce973b14
LY		 1762 enet_addr_type)
1763{
6fee40e9 1764 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
18a8e864
LY		 1765 struct ucc_fast_private *uccf;
1766 enum comm_dir comm_dir;
ce973b14
LY		 1767 struct list_head *p_lh;
1768 u16 i, num;
6fee40e9
AF		 1769 u32 __iomem *addr_h;
1770 u32 __iomem *addr_l;
ce973b14
LY		 1771 u8 *p_counter;
1772
1773 uccf = ugeth->uccf;
1774
1775 p_82xx_addr_filt =
6fee40e9
AF		 1776 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1777 ugeth->p_rx_glbl_pram->addressfiltering;
ce973b14
LY		 1778
1779 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1780 addr_h = &(p_82xx_addr_filt->gaddr_h);
1781 addr_l = &(p_82xx_addr_filt->gaddr_l);
1782 p_lh = &ugeth->group_hash_q;
1783 p_counter = &(ugeth->numGroupAddrInHash);
1784 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1785 addr_h = &(p_82xx_addr_filt->iaddr_h);
1786 addr_l = &(p_82xx_addr_filt->iaddr_l);
1787 p_lh = &ugeth->ind_hash_q;
1788 p_counter = &(ugeth->numIndAddrInHash);
1789 } else
1790 return -EINVAL;
1791
1792 comm_dir = 0;
1793 if (uccf->enabled_tx)
1794 comm_dir |= COMM_DIR_TX;
1795 if (uccf->enabled_rx)
1796 comm_dir |= COMM_DIR_RX;
1797 if (comm_dir)
1798 ugeth_disable(ugeth, comm_dir);
1799
1800 /* Clear the hash table. */
1801 out_be32(addr_h, 0x00000000);
1802 out_be32(addr_l, 0x00000000);
1803
1804 if (!p_lh)
1805 return 0;
1806
1807 num = *p_counter;
1808
1809 /* Delete all remaining CQ elements */
1810 for (i = 0; i < num; i++)
1811 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1812
1813 *p_counter = 0;
1814
1815 if (comm_dir)
1816 ugeth_enable(ugeth, comm_dir);
1817
1818 return 0;
1819}
1820
18a8e864 1821static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
ce973b14
LY		 1822 u8 paddr_num)
1823{
1824 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1825 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1826}
1827
e19a82c1
PG		 1828static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1829{
1830 struct ucc_geth_info *ug_info;
1831 struct ucc_fast_info *uf_info;
1832 u16 i, j;
1833 u8 __iomem *bd;
1834
1835
1836 ug_info = ugeth->ug_info;
1837 uf_info = &ug_info->uf_info;
1838
1839 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1840 if (ugeth->p_rx_bd_ring[i]) {
1841 /* Return existing data buffers in ring */
1842 bd = ugeth->p_rx_bd_ring[i];
1843 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1844 if (ugeth->rx_skbuff[i][j]) {
1845 dma_unmap_single(ugeth->dev,
1846 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1847 ugeth->ug_info->
1848 uf_info.max_rx_buf_length +
1849 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1850 DMA_FROM_DEVICE);
1851 dev_kfree_skb_any(
1852 ugeth->rx_skbuff[i][j]);
1853 ugeth->rx_skbuff[i][j] = NULL;
1854 }
1855 bd += sizeof(struct qe_bd);
1856 }
1857
1858 kfree(ugeth->rx_skbuff[i]);
1859
1860 if (ugeth->ug_info->uf_info.bd_mem_part ==
1861 MEM_PART_SYSTEM)
1862 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1863 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1864 MEM_PART_MURAM)
1865 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1866 ugeth->p_rx_bd_ring[i] = NULL;
1867 }
1868 }
1869
1870}
1871
1872static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
ce973b14 1873{
e19a82c1
PG		 1874 struct ucc_geth_info *ug_info;
1875 struct ucc_fast_info *uf_info;
ce973b14 1876 u16 i, j;
6fee40e9 1877 u8 __iomem *bd;
ce973b14 1878
e15aa3b2
MT		 1879 netdev_reset_queue(ugeth->ndev);
1880
e19a82c1
PG		 1881 ug_info = ugeth->ug_info;
1882 uf_info = &ug_info->uf_info;
1883
1884 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1885 bd = ugeth->p_tx_bd_ring[i];
1886 if (!bd)
1887 continue;
1888 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1889 if (ugeth->tx_skbuff[i][j]) {
1890 dma_unmap_single(ugeth->dev,
1891 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1892 (in_be32((u32 __iomem *)bd) &
1893 BD_LENGTH_MASK),
1894 DMA_TO_DEVICE);
1895 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1896 ugeth->tx_skbuff[i][j] = NULL;
1897 }
1898 }
1899
1900 kfree(ugeth->tx_skbuff[i]);
1901
1902 if (ugeth->p_tx_bd_ring[i]) {
1903 if (ugeth->ug_info->uf_info.bd_mem_part ==
1904 MEM_PART_SYSTEM)
1905 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1906 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1907 MEM_PART_MURAM)
1908 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1909 ugeth->p_tx_bd_ring[i] = NULL;
1910 }
1911 }
1912
1913}
1914
1915static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1916{
ce973b14
LY		 1917 if (!ugeth)
1918 return;
1919
80a9fad8 1920 if (ugeth->uccf) {
ce973b14 1921 ucc_fast_free(ugeth->uccf);
80a9fad8
AV		 1922 ugeth->uccf = NULL;
1923 }
ce973b14
LY		 1924
1925 if (ugeth->p_thread_data_tx) {
1926 qe_muram_free(ugeth->thread_dat_tx_offset);
1927 ugeth->p_thread_data_tx = NULL;
1928 }
1929 if (ugeth->p_thread_data_rx) {
1930 qe_muram_free(ugeth->thread_dat_rx_offset);
1931 ugeth->p_thread_data_rx = NULL;
1932 }
1933 if (ugeth->p_exf_glbl_param) {
1934 qe_muram_free(ugeth->exf_glbl_param_offset);
1935 ugeth->p_exf_glbl_param = NULL;
1936 }
1937 if (ugeth->p_rx_glbl_pram) {
1938 qe_muram_free(ugeth->rx_glbl_pram_offset);
1939 ugeth->p_rx_glbl_pram = NULL;
1940 }
1941 if (ugeth->p_tx_glbl_pram) {
1942 qe_muram_free(ugeth->tx_glbl_pram_offset);
1943 ugeth->p_tx_glbl_pram = NULL;
1944 }
1945 if (ugeth->p_send_q_mem_reg) {
1946 qe_muram_free(ugeth->send_q_mem_reg_offset);
1947 ugeth->p_send_q_mem_reg = NULL;
1948 }
1949 if (ugeth->p_scheduler) {
1950 qe_muram_free(ugeth->scheduler_offset);
1951 ugeth->p_scheduler = NULL;
1952 }
1953 if (ugeth->p_tx_fw_statistics_pram) {
1954 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1955 ugeth->p_tx_fw_statistics_pram = NULL;
1956 }
1957 if (ugeth->p_rx_fw_statistics_pram) {
1958 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1959 ugeth->p_rx_fw_statistics_pram = NULL;
1960 }
1961 if (ugeth->p_rx_irq_coalescing_tbl) {
1962 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1963 ugeth->p_rx_irq_coalescing_tbl = NULL;
1964 }
1965 if (ugeth->p_rx_bd_qs_tbl) {
1966 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1967 ugeth->p_rx_bd_qs_tbl = NULL;
1968 }
1969 if (ugeth->p_init_enet_param_shadow) {
1970 return_init_enet_entries(ugeth,
1971 &(ugeth->p_init_enet_param_shadow->
1972 rxthread[0]),
1973 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1974 ugeth->ug_info->riscRx, 1);
1975 return_init_enet_entries(ugeth,
1976 &(ugeth->p_init_enet_param_shadow->
1977 txthread[0]),
1978 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1979 ugeth->ug_info->riscTx, 0);
1980 kfree(ugeth->p_init_enet_param_shadow);
1981 ugeth->p_init_enet_param_shadow = NULL;
1982 }
e19a82c1
PG		 1983 ucc_geth_free_tx(ugeth);
1984 ucc_geth_free_rx(ugeth);
ce973b14
LY		 1985 while (!list_empty(&ugeth->group_hash_q))
1986 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1987 (dequeue(&ugeth->group_hash_q)));
1988 while (!list_empty(&ugeth->ind_hash_q))
1989 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1990 (dequeue(&ugeth->ind_hash_q)));
3e73fc9a
AV		 1991 if (ugeth->ug_regs) {
1992 iounmap(ugeth->ug_regs);
1993 ugeth->ug_regs = NULL;
1994 }
ce973b14
LY		 1995}
1996
1997static void ucc_geth_set_multi(struct net_device *dev)
1998{
18a8e864 1999 struct ucc_geth_private *ugeth;
22bedad3 2000 struct netdev_hw_addr *ha;
6fee40e9
AF		 2001 struct ucc_fast __iomem *uf_regs;
2002 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 2003
2004 ugeth = netdev_priv(dev);
2005
2006 uf_regs = ugeth->uccf->uf_regs;
2007
2008 if (dev->flags & IFF_PROMISC) {
3bc53427 2009 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14 2010 } else {
3bc53427 2011 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14
LY		 2012
2013 p_82xx_addr_filt =
6fee40e9 2014 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2015 p_rx_glbl_pram->addressfiltering;
2016
2017 if (dev->flags & IFF_ALLMULTI) {
2018 /* Catch all multicast addresses, so set the
2019 * filter to all 1's.
2020 */
2021 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2022 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2023 } else {
2024 /* Clear filter and add the addresses in the list.
2025 */
2026 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2027 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2028
22bedad3 2029 netdev_for_each_mc_addr(ha, dev) {
ce973b14
LY		 2030 /* Ask CPM to run CRC and set bit in
2031 * filter mask.
2032 */
22bedad3 2033 hw_add_addr_in_hash(ugeth, ha->addr);
ce973b14
LY		 2034 }
2035 }
2036 }
2037}
2038
18a8e864 2039static void ucc_geth_stop(struct ucc_geth_private *ugeth)
ce973b14 2040{
6fee40e9 2041 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
728de4c9 2042 struct phy_device *phydev = ugeth->phydev;
ce973b14 2043
b39d66a8 2044 ugeth_vdbg("%s: IN", __func__);
ce973b14 2045
75e60474
JT		 2046 /*
2047 * Tell the kernel the link is down.
2048 * Must be done before disabling the controller
2049 * or deadlock may happen.
2050 */
2051 phy_stop(phydev);
2052
ce973b14
LY		 2053 /* Disable the controller */
2054 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2055
ce973b14 2056 /* Mask all interrupts */
c6f5047b 2057 out_be32(ugeth->uccf->p_uccm, 0x00000000);
ce973b14
LY		 2058
2059 /* Clear all interrupts */
2060 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2061
2062 /* Disable Rx and Tx */
3bc53427 2063 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14 2064
ce973b14
LY		 2065 ucc_geth_memclean(ugeth);
2066}
2067
728de4c9 2068static int ucc_struct_init(struct ucc_geth_private *ugeth)
ce973b14 2069{
18a8e864
LY		 2070 struct ucc_geth_info *ug_info;
2071 struct ucc_fast_info *uf_info;
728de4c9 2072 int i;
ce973b14
LY		 2073
2074 ug_info = ugeth->ug_info;
2075 uf_info = &ug_info->uf_info;
2076
2077 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2078 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
890de95e 2079 if (netif_msg_probe(ugeth))
c84d8055 2080 pr_err("Bad memory partition value\n");
ce973b14
LY		 2081 return -EINVAL;
2082 }
2083
2084 /* Rx BD lengths */
2085 for (i = 0; i < ug_info->numQueuesRx; i++) {
2086 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2087 (ug_info->bdRingLenRx[i] %
2088 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
890de95e 2089 if (netif_msg_probe(ugeth))
c84d8055 2090 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n");
ce973b14
LY		 2091 return -EINVAL;
2092 }
2093 }
2094
2095 /* Tx BD lengths */
2096 for (i = 0; i < ug_info->numQueuesTx; i++) {
2097 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
890de95e 2098 if (netif_msg_probe(ugeth))
c84d8055 2099 pr_err("Tx BD ring length must be no smaller than 2\n");
ce973b14
LY		 2100 return -EINVAL;
2101 }
2102 }
2103
2104 /* mrblr */
2105 if ((uf_info->max_rx_buf_length == 0) ||
2106 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
890de95e 2107 if (netif_msg_probe(ugeth))
c84d8055 2108 pr_err("max_rx_buf_length must be non-zero multiple of 128\n");
ce973b14
LY		 2109 return -EINVAL;
2110 }
2111
2112 /* num Tx queues */
2113 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
890de95e 2114 if (netif_msg_probe(ugeth))
c84d8055 2115 pr_err("number of tx queues too large\n");
ce973b14
LY		 2116 return -EINVAL;
2117 }
2118
2119 /* num Rx queues */
2120 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
890de95e 2121 if (netif_msg_probe(ugeth))
c84d8055 2122 pr_err("number of rx queues too large\n");
ce973b14
LY		 2123 return -EINVAL;
2124 }
2125
2126 /* l2qt */
2127 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2128 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
890de95e 2129 if (netif_msg_probe(ugeth))
c84d8055 2130 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n");
ce973b14
LY		 2131 return -EINVAL;
2132 }
2133 }
2134
2135 /* l3qt */
2136 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2137 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
890de95e 2138 if (netif_msg_probe(ugeth))
c84d8055 2139 pr_err("IP priority table entry must not be larger than number of Rx queues\n");
ce973b14
LY		 2140 return -EINVAL;
2141 }
2142 }
2143
2144 if (ug_info->cam && !ug_info->ecamptr) {
890de95e 2145 if (netif_msg_probe(ugeth))
c84d8055 2146 pr_err("If cam mode is chosen, must supply cam ptr\n");
ce973b14
LY		 2147 return -EINVAL;
2148 }
2149
2150 if ((ug_info->numStationAddresses !=
8e95a202
JP		 2151 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2152 ug_info->rxExtendedFiltering) {
890de95e 2153 if (netif_msg_probe(ugeth))
c84d8055 2154 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n");
ce973b14
LY		 2155 return -EINVAL;
2156 }
2157
2158 /* Generate uccm_mask for receive */
2159 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2160 for (i = 0; i < ug_info->numQueuesRx; i++)
3bc53427 2161 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
ce973b14
LY		 2162
2163 for (i = 0; i < ug_info->numQueuesTx; i++)
3bc53427 2164 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
ce973b14 2165 /* Initialize the general fast UCC block. */
728de4c9 2166 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
890de95e 2167 if (netif_msg_probe(ugeth))
c84d8055 2168 pr_err("Failed to init uccf\n");
ce973b14
LY		 2169 return -ENOMEM;
2170 }
728de4c9 2171
345f8422
HW		 2172 /* read the number of risc engines, update the riscTx and riscRx
2173 * if there are 4 riscs in QE
2174 */
2175 if (qe_get_num_of_risc() == 4) {
2176 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2177 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2178 }
2179
3e73fc9a
AV		 2180 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2181 if (!ugeth->ug_regs) {
2182 if (netif_msg_probe(ugeth))
c84d8055 2183 pr_err("Failed to ioremap regs\n");
3e73fc9a
AV		 2184 return -ENOMEM;
2185 }
728de4c9
KP		 2186
2187 return 0;
2188}
2189
e19a82c1
PG		 2190static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2191{
2192 struct ucc_geth_info *ug_info;
2193 struct ucc_fast_info *uf_info;
2194 int length;
2195 u16 i, j;
2196 u8 __iomem *bd;
2197
2198 ug_info = ugeth->ug_info;
2199 uf_info = &ug_info->uf_info;
2200
2201 /* Allocate Tx bds */
2202 for (j = 0; j < ug_info->numQueuesTx; j++) {
2203 /* Allocate in multiple of
2204 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2205 according to spec */
2206 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2207 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2208 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2209 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2210 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2211 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2212 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2213 u32 align = 4;
2214 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2215 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2216 ugeth->tx_bd_ring_offset[j] =
2217 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2218
2219 if (ugeth->tx_bd_ring_offset[j] != 0)
2220 ugeth->p_tx_bd_ring[j] =
2221 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2222 align) & ~(align - 1));
2223 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2224 ugeth->tx_bd_ring_offset[j] =
2225 qe_muram_alloc(length,
2226 UCC_GETH_TX_BD_RING_ALIGNMENT);
2227 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2228 ugeth->p_tx_bd_ring[j] =
2229 (u8 __iomem *) qe_muram_addr(ugeth->
2230 tx_bd_ring_offset[j]);
2231 }
2232 if (!ugeth->p_tx_bd_ring[j]) {
2233 if (netif_msg_ifup(ugeth))
c84d8055 2234 pr_err("Can not allocate memory for Tx bd rings\n");
e19a82c1
PG		 2235 return -ENOMEM;
2236 }
2237 /* Zero unused end of bd ring, according to spec */
2238 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2239 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2240 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2241 }
2242
2243 /* Init Tx bds */
2244 for (j = 0; j < ug_info->numQueuesTx; j++) {
2245 /* Setup the skbuff rings */
6da2ec56
KC		 2246 ugeth->tx_skbuff[j] =
2247 kmalloc_array(ugeth->ug_info->bdRingLenTx[j],
2248 sizeof(struct sk_buff *), GFP_KERNEL);
e19a82c1
PG		 2249
2250 if (ugeth->tx_skbuff[j] == NULL) {
2251 if (netif_msg_ifup(ugeth))
c84d8055 2252 pr_err("Could not allocate tx_skbuff\n");
e19a82c1
PG		 2253 return -ENOMEM;
2254 }
2255
2256 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2257 ugeth->tx_skbuff[j][i] = NULL;
2258
2259 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2260 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2261 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2262 /* clear bd buffer */
2263 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2264 /* set bd status and length */
2265 out_be32((u32 __iomem *)bd, 0);
2266 bd += sizeof(struct qe_bd);
2267 }
2268 bd -= sizeof(struct qe_bd);
2269 /* set bd status and length */
2270 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2271 }
2272
2273 return 0;
2274}
2275
2276static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2277{
2278 struct ucc_geth_info *ug_info;
2279 struct ucc_fast_info *uf_info;
2280 int length;
2281 u16 i, j;
2282 u8 __iomem *bd;
2283
2284 ug_info = ugeth->ug_info;
2285 uf_info = &ug_info->uf_info;
2286
2287 /* Allocate Rx bds */
2288 for (j = 0; j < ug_info->numQueuesRx; j++) {
2289 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2290 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2291 u32 align = 4;
2292 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2293 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2294 ugeth->rx_bd_ring_offset[j] =
2295 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2296 if (ugeth->rx_bd_ring_offset[j] != 0)
2297 ugeth->p_rx_bd_ring[j] =
2298 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2299 align) & ~(align - 1));
2300 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2301 ugeth->rx_bd_ring_offset[j] =
2302 qe_muram_alloc(length,
2303 UCC_GETH_RX_BD_RING_ALIGNMENT);
2304 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2305 ugeth->p_rx_bd_ring[j] =
2306 (u8 __iomem *) qe_muram_addr(ugeth->
2307 rx_bd_ring_offset[j]);
2308 }
2309 if (!ugeth->p_rx_bd_ring[j]) {
2310 if (netif_msg_ifup(ugeth))
c84d8055 2311 pr_err("Can not allocate memory for Rx bd rings\n");
e19a82c1
PG		 2312 return -ENOMEM;
2313 }
2314 }
2315
2316 /* Init Rx bds */
2317 for (j = 0; j < ug_info->numQueuesRx; j++) {
2318 /* Setup the skbuff rings */
6da2ec56
KC		 2319 ugeth->rx_skbuff[j] =
2320 kmalloc_array(ugeth->ug_info->bdRingLenRx[j],
2321 sizeof(struct sk_buff *), GFP_KERNEL);
e19a82c1
PG		 2322
2323 if (ugeth->rx_skbuff[j] == NULL) {
2324 if (netif_msg_ifup(ugeth))
c84d8055 2325 pr_err("Could not allocate rx_skbuff\n");
e19a82c1
PG		 2326 return -ENOMEM;
2327 }
2328
2329 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2330 ugeth->rx_skbuff[j][i] = NULL;
2331
2332 ugeth->skb_currx[j] = 0;
2333 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2334 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2335 /* set bd status and length */
2336 out_be32((u32 __iomem *)bd, R_I);
2337 /* clear bd buffer */
2338 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2339 bd += sizeof(struct qe_bd);
2340 }
2341 bd -= sizeof(struct qe_bd);
2342 /* set bd status and length */
2343 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2344 }
2345
2346 return 0;
2347}
2348
728de4c9
KP		 2349static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2350{
6fee40e9
AF		 2351 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2352 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
728de4c9
KP		 2353 struct ucc_fast_private *uccf;
2354 struct ucc_geth_info *ug_info;
2355 struct ucc_fast_info *uf_info;
6fee40e9
AF		 2356 struct ucc_fast __iomem *uf_regs;
2357 struct ucc_geth __iomem *ug_regs;
728de4c9
KP		 2358 int ret_val = -EINVAL;
2359 u32 remoder = UCC_GETH_REMODER_INIT;
3bc53427 2360 u32 init_enet_pram_offset, cecr_subblock, command;
e19a82c1 2361 u32 ifstat, i, j, size, l2qt, l3qt;
728de4c9
KP		 2362 u16 temoder = UCC_GETH_TEMODER_INIT;
2363 u16 test;
2364 u8 function_code = 0;
6fee40e9 2365 u8 __iomem *endOfRing;
728de4c9
KP		 2366 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2367
b39d66a8 2368 ugeth_vdbg("%s: IN", __func__);
728de4c9
KP		 2369 uccf = ugeth->uccf;
2370 ug_info = ugeth->ug_info;
2371 uf_info = &ug_info->uf_info;
2372 uf_regs = uccf->uf_regs;
2373 ug_regs = ugeth->ug_regs;
ce973b14
LY		 2374
2375 switch (ug_info->numThreadsRx) {
2376 case UCC_GETH_NUM_OF_THREADS_1:
2377 numThreadsRxNumerical = 1;
2378 break;
2379 case UCC_GETH_NUM_OF_THREADS_2:
2380 numThreadsRxNumerical = 2;
2381 break;
2382 case UCC_GETH_NUM_OF_THREADS_4:
2383 numThreadsRxNumerical = 4;
2384 break;
2385 case UCC_GETH_NUM_OF_THREADS_6:
2386 numThreadsRxNumerical = 6;
2387 break;
2388 case UCC_GETH_NUM_OF_THREADS_8:
2389 numThreadsRxNumerical = 8;
2390 break;
2391 default:
890de95e 2392 if (netif_msg_ifup(ugeth))
c84d8055 2393 pr_err("Bad number of Rx threads value\n");
ce973b14 2394 return -EINVAL;
ce973b14
LY		 2395 }
2396
2397 switch (ug_info->numThreadsTx) {
2398 case UCC_GETH_NUM_OF_THREADS_1:
2399 numThreadsTxNumerical = 1;
2400 break;
2401 case UCC_GETH_NUM_OF_THREADS_2:
2402 numThreadsTxNumerical = 2;
2403 break;
2404 case UCC_GETH_NUM_OF_THREADS_4:
2405 numThreadsTxNumerical = 4;
2406 break;
2407 case UCC_GETH_NUM_OF_THREADS_6:
2408 numThreadsTxNumerical = 6;
2409 break;
2410 case UCC_GETH_NUM_OF_THREADS_8:
2411 numThreadsTxNumerical = 8;
2412 break;
2413 default:
890de95e 2414 if (netif_msg_ifup(ugeth))
c84d8055 2415 pr_err("Bad number of Tx threads value\n");
ce973b14 2416 return -EINVAL;
ce973b14
LY		 2417 }
2418
2419 /* Calculate rx_extended_features */
2420 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2421 ug_info->ipAddressAlignment ||
2422 (ug_info->numStationAddresses !=
2423 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2424
2425 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
8e95a202
JP		 2426 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2427 (ug_info->vlanOperationNonTagged !=
2428 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
ce973b14 2429
ce973b14
LY		 2430 init_default_reg_vals(&uf_regs->upsmr,
2431 &ug_regs->maccfg1, &ug_regs->maccfg2);
2432
2433 /* Set UPSMR */
2434 /* For more details see the hardware spec. */
2435 init_rx_parameters(ug_info->bro,
2436 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2437
2438 /* We're going to ignore other registers for now, */
2439 /* except as needed to get up and running */
2440
2441 /* Set MACCFG1 */
2442 /* For more details see the hardware spec. */
2443 init_flow_control_params(ug_info->aufc,
2444 ug_info->receiveFlowControl,
ac421852 2445 ug_info->transmitFlowControl,
ce973b14
LY		 2446 ug_info->pausePeriod,
2447 ug_info->extensionField,
2448 &uf_regs->upsmr,
2449 &ug_regs->uempr, &ug_regs->maccfg1);
2450
3bc53427 2451 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14
LY		 2452
2453 /* Set IPGIFG */
2454 /* For more details see the hardware spec. */
2455 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2456 ug_info->nonBackToBackIfgPart2,
2457 ug_info->
2458 miminumInterFrameGapEnforcement,
2459 ug_info->backToBackInterFrameGap,
2460 &ug_regs->ipgifg);
2461 if (ret_val != 0) {
890de95e 2462 if (netif_msg_ifup(ugeth))
c84d8055 2463 pr_err("IPGIFG initialization parameter too large\n");
ce973b14
LY		 2464 return ret_val;
2465 }
2466
2467 /* Set HAFDUP */
2468 /* For more details see the hardware spec. */
2469 ret_val = init_half_duplex_params(ug_info->altBeb,
2470 ug_info->backPressureNoBackoff,
2471 ug_info->noBackoff,
2472 ug_info->excessDefer,
2473 ug_info->altBebTruncation,
2474 ug_info->maxRetransmission,
2475 ug_info->collisionWindow,
2476 &ug_regs->hafdup);
2477 if (ret_val != 0) {
890de95e 2478 if (netif_msg_ifup(ugeth))
c84d8055 2479 pr_err("Half Duplex initialization parameter too large\n");
ce973b14
LY		 2480 return ret_val;
2481 }
2482
2483 /* Set IFSTAT */
2484 /* For more details see the hardware spec. */
2485 /* Read only - resets upon read */
2486 ifstat = in_be32(&ug_regs->ifstat);
2487
2488 /* Clear UEMPR */
2489 /* For more details see the hardware spec. */
2490 out_be32(&ug_regs->uempr, 0);
2491
2492 /* Set UESCR */
2493 /* For more details see the hardware spec. */
2494 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2495 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2496 0, &uf_regs->upsmr, &ug_regs->uescr);
2497
e19a82c1
PG		 2498 ret_val = ucc_geth_alloc_tx(ugeth);
2499 if (ret_val != 0)
2500 return ret_val;
ce973b14 2501
e19a82c1
PG		 2502 ret_val = ucc_geth_alloc_rx(ugeth);
2503 if (ret_val != 0)
2504 return ret_val;
ce973b14
LY		 2505
2506 /*
2507 * Global PRAM
2508 */
2509 /* Tx global PRAM */
2510 /* Allocate global tx parameter RAM page */
2511 ugeth->tx_glbl_pram_offset =
18a8e864 2512 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
ce973b14 2513 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2514 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
890de95e 2515 if (netif_msg_ifup(ugeth))
c84d8055 2516 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n");
ce973b14
LY		 2517 return -ENOMEM;
2518 }
2519 ugeth->p_tx_glbl_pram =
6fee40e9 2520 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2521 tx_glbl_pram_offset);
2522 /* Zero out p_tx_glbl_pram */
6fee40e9 2523 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
ce973b14
LY		 2524
2525 /* Fill global PRAM */
2526
2527 /* TQPTR */
2528 /* Size varies with number of Tx threads */
2529 ugeth->thread_dat_tx_offset =
2530 qe_muram_alloc(numThreadsTxNumerical *
18a8e864 2531 sizeof(struct ucc_geth_thread_data_tx) +
ce973b14
LY		 2532 32 * (numThreadsTxNumerical == 1),
2533 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2534 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
890de95e 2535 if (netif_msg_ifup(ugeth))
c84d8055 2536 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n");
ce973b14
LY		 2537 return -ENOMEM;
2538 }
2539
2540 ugeth->p_thread_data_tx =
6fee40e9 2541 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2542 thread_dat_tx_offset);
2543 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2544
2545 /* vtagtable */
2546 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2547 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2548 ug_info->vtagtable[i]);
2549
2550 /* iphoffset */
2551 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
6fee40e9
AF		 2552 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2553 ug_info->iphoffset[i]);
ce973b14
LY		 2554
2555 /* SQPTR */
2556 /* Size varies with number of Tx queues */
2557 ugeth->send_q_mem_reg_offset =
2558 qe_muram_alloc(ug_info->numQueuesTx *
18a8e864 2559 sizeof(struct ucc_geth_send_queue_qd),
ce973b14 2560 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
4c35630c 2561 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
890de95e 2562 if (netif_msg_ifup(ugeth))
c84d8055 2563 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n");
ce973b14
LY		 2564 return -ENOMEM;
2565 }
2566
2567 ugeth->p_send_q_mem_reg =
6fee40e9 2568 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2569 send_q_mem_reg_offset);
2570 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2571
2572 /* Setup the table */
2573 /* Assume BD rings are already established */
2574 for (i = 0; i < ug_info->numQueuesTx; i++) {
2575 endOfRing =
2576 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
18a8e864 2577 1) * sizeof(struct qe_bd);
ce973b14
LY		 2578 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2579 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2580 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2581 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2582 last_bd_completed_address,
2583 (u32) virt_to_phys(endOfRing));
2584 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2585 MEM_PART_MURAM) {
2586 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
8b8642af 2587 (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i]));
ce973b14
LY		 2588 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2589 last_bd_completed_address,
8b8642af 2590 (u32)qe_muram_dma(endOfRing));
ce973b14
LY		 2591 }
2592 }
2593
2594 /* schedulerbasepointer */
2595
2596 if (ug_info->numQueuesTx > 1) {
2597 /* scheduler exists only if more than 1 tx queue */
2598 ugeth->scheduler_offset =
18a8e864 2599 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
ce973b14 2600 UCC_GETH_SCHEDULER_ALIGNMENT);
4c35630c 2601 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
890de95e 2602 if (netif_msg_ifup(ugeth))
c84d8055 2603 pr_err("Can not allocate DPRAM memory for p_scheduler\n");
ce973b14
LY		 2604 return -ENOMEM;
2605 }
2606
2607 ugeth->p_scheduler =
6fee40e9 2608 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2609 scheduler_offset);
2610 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2611 ugeth->scheduler_offset);
2612 /* Zero out p_scheduler */
6fee40e9 2613 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
ce973b14
LY		 2614
2615 /* Set values in scheduler */
2616 out_be32(&ugeth->p_scheduler->mblinterval,
2617 ug_info->mblinterval);
2618 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2619 ug_info->nortsrbytetime);
6fee40e9
AF		 2620 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2621 out_8(&ugeth->p_scheduler->strictpriorityq,
2622 ug_info->strictpriorityq);
2623 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2624 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
ce973b14 2625 for (i = 0; i < NUM_TX_QUEUES; i++)
6fee40e9
AF		 2626 out_8(&ugeth->p_scheduler->weightfactor[i],
2627 ug_info->weightfactor[i]);
ce973b14
LY		 2628
2629 /* Set pointers to cpucount registers in scheduler */
2630 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2631 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2632 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2633 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2634 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2635 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2636 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2637 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2638 }
2639
2640 /* schedulerbasepointer */
2641 /* TxRMON_PTR (statistics) */
2642 if (ug_info->
2643 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2644 ugeth->tx_fw_statistics_pram_offset =
2645 qe_muram_alloc(sizeof
18a8e864 2646 (struct ucc_geth_tx_firmware_statistics_pram),
ce973b14 2647 UCC_GETH_TX_STATISTICS_ALIGNMENT);
4c35630c 2648 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
890de95e 2649 if (netif_msg_ifup(ugeth))
c84d8055 2650 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n");
ce973b14
LY		 2651 return -ENOMEM;
2652 }
2653 ugeth->p_tx_fw_statistics_pram =
6fee40e9 2654 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2655 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2656 /* Zero out p_tx_fw_statistics_pram */
6fee40e9 2657 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
18a8e864 2658 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
ce973b14
LY		 2659 }
2660
2661 /* temoder */
2662 /* Already has speed set */
2663
2664 if (ug_info->numQueuesTx > 1)
2665 temoder |= TEMODER_SCHEDULER_ENABLE;
2666 if (ug_info->ipCheckSumGenerate)
2667 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2668 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2669 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2670
2671 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2672
2673 /* Function code register value to be used later */
6b0b594b 2674 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
ce973b14
LY		 2675 /* Required for QE */
2676
2677 /* function code register */
2678 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2679
2680 /* Rx global PRAM */
2681 /* Allocate global rx parameter RAM page */
2682 ugeth->rx_glbl_pram_offset =
18a8e864 2683 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
ce973b14 2684 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2685 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
890de95e 2686 if (netif_msg_ifup(ugeth))
c84d8055 2687 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n");
ce973b14
LY		 2688 return -ENOMEM;
2689 }
2690 ugeth->p_rx_glbl_pram =
6fee40e9 2691 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2692 rx_glbl_pram_offset);
2693 /* Zero out p_rx_glbl_pram */
6fee40e9 2694 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
ce973b14
LY		 2695
2696 /* Fill global PRAM */
2697
2698 /* RQPTR */
2699 /* Size varies with number of Rx threads */
2700 ugeth->thread_dat_rx_offset =
2701 qe_muram_alloc(numThreadsRxNumerical *
18a8e864 2702 sizeof(struct ucc_geth_thread_data_rx),
ce973b14 2703 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2704 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
890de95e 2705 if (netif_msg_ifup(ugeth))
c84d8055 2706 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n");
ce973b14
LY		 2707 return -ENOMEM;
2708 }
2709
2710 ugeth->p_thread_data_rx =
6fee40e9 2711 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2712 thread_dat_rx_offset);
2713 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2714
2715 /* typeorlen */
2716 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2717
2718 /* rxrmonbaseptr (statistics) */
2719 if (ug_info->
2720 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2721 ugeth->rx_fw_statistics_pram_offset =
2722 qe_muram_alloc(sizeof
18a8e864 2723 (struct ucc_geth_rx_firmware_statistics_pram),
ce973b14 2724 UCC_GETH_RX_STATISTICS_ALIGNMENT);
4c35630c 2725 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
890de95e 2726 if (netif_msg_ifup(ugeth))
c84d8055 2727 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n");
ce973b14
LY		 2728 return -ENOMEM;
2729 }
2730 ugeth->p_rx_fw_statistics_pram =
6fee40e9 2731 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2732 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2733 /* Zero out p_rx_fw_statistics_pram */
6fee40e9 2734 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
18a8e864 2735 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
ce973b14
LY		 2736 }
2737
2738 /* intCoalescingPtr */
2739
2740 /* Size varies with number of Rx queues */
2741 ugeth->rx_irq_coalescing_tbl_offset =
2742 qe_muram_alloc(ug_info->numQueuesRx *
7563907e
MB		 2743 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2744 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
4c35630c 2745 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
890de95e 2746 if (netif_msg_ifup(ugeth))
c84d8055 2747 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n");
ce973b14
LY		 2748 return -ENOMEM;
2749 }
2750
2751 ugeth->p_rx_irq_coalescing_tbl =
6fee40e9 2752 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
ce973b14
LY		 2753 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2754 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2755 ugeth->rx_irq_coalescing_tbl_offset);
2756
2757 /* Fill interrupt coalescing table */
2758 for (i = 0; i < ug_info->numQueuesRx; i++) {
2759 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2760 interruptcoalescingmaxvalue,
2761 ug_info->interruptcoalescingmaxvalue[i]);
2762 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2763 interruptcoalescingcounter,
2764 ug_info->interruptcoalescingmaxvalue[i]);
2765 }
2766
2767 /* MRBLR */
2768 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2769 &ugeth->p_rx_glbl_pram->mrblr);
2770 /* MFLR */
2771 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2772 /* MINFLR */
2773 init_min_frame_len(ug_info->minFrameLength,
2774 &ugeth->p_rx_glbl_pram->minflr,
2775 &ugeth->p_rx_glbl_pram->mrblr);
2776 /* MAXD1 */
2777 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2778 /* MAXD2 */
2779 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2780
2781 /* l2qt */
2782 l2qt = 0;
2783 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2784 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2785 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2786
2787 /* l3qt */
2788 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2789 l3qt = 0;
2790 for (i = 0; i < 8; i++)
2791 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
18a8e864 2792 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
ce973b14
LY		 2793 }
2794
2795 /* vlantype */
2796 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2797
2798 /* vlantci */
2799 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2800
2801 /* ecamptr */
2802 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2803
2804 /* RBDQPTR */
2805 /* Size varies with number of Rx queues */
2806 ugeth->rx_bd_qs_tbl_offset =
2807 qe_muram_alloc(ug_info->numQueuesRx *
18a8e864
LY		 2808 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2809 sizeof(struct ucc_geth_rx_prefetched_bds)),
ce973b14 2810 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
4c35630c 2811 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
890de95e 2812 if (netif_msg_ifup(ugeth))
c84d8055 2813 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n");
ce973b14
LY		 2814 return -ENOMEM;
2815 }
2816
2817 ugeth->p_rx_bd_qs_tbl =
6fee40e9 2818 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2819 rx_bd_qs_tbl_offset);
2820 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2821 /* Zero out p_rx_bd_qs_tbl */
6fee40e9 2822 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
ce973b14 2823 0,
18a8e864
LY		 2824 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2825 sizeof(struct ucc_geth_rx_prefetched_bds)));
ce973b14
LY		 2826
2827 /* Setup the table */
2828 /* Assume BD rings are already established */
2829 for (i = 0; i < ug_info->numQueuesRx; i++) {
2830 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2831 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2832 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2833 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2834 MEM_PART_MURAM) {
2835 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
8b8642af 2836 (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i]));
ce973b14
LY		 2837 }
2838 /* rest of fields handled by QE */
2839 }
2840
2841 /* remoder */
2842 /* Already has speed set */
2843
2844 if (ugeth->rx_extended_features)
2845 remoder |= REMODER_RX_EXTENDED_FEATURES;
2846 if (ug_info->rxExtendedFiltering)
2847 remoder |= REMODER_RX_EXTENDED_FILTERING;
2848 if (ug_info->dynamicMaxFrameLength)
2849 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2850 if (ug_info->dynamicMinFrameLength)
2851 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2852 remoder |=
2853 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2854 remoder |=
2855 ug_info->
2856 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2857 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2858 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2859 if (ug_info->ipCheckSumCheck)
2860 remoder |= REMODER_IP_CHECKSUM_CHECK;
2861 if (ug_info->ipAddressAlignment)
2862 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2863 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2864
2865 /* Note that this function must be called */
2866 /* ONLY AFTER p_tx_fw_statistics_pram */
2867 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2868 init_firmware_statistics_gathering_mode((ug_info->
2869 statisticsMode &
2870 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2871 (ug_info->statisticsMode &
2872 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2873 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2874 ugeth->tx_fw_statistics_pram_offset,
2875 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2876 ugeth->rx_fw_statistics_pram_offset,
2877 &ugeth->p_tx_glbl_pram->temoder,
2878 &ugeth->p_rx_glbl_pram->remoder);
2879
2880 /* function code register */
6fee40e9 2881 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
ce973b14
LY		 2882
2883 /* initialize extended filtering */
2884 if (ug_info->rxExtendedFiltering) {
2885 if (!ug_info->extendedFilteringChainPointer) {
890de95e 2886 if (netif_msg_ifup(ugeth))
c84d8055 2887 pr_err("Null Extended Filtering Chain Pointer\n");
ce973b14
LY		 2888 return -EINVAL;
2889 }
2890
2891 /* Allocate memory for extended filtering Mode Global
2892 Parameters */
2893 ugeth->exf_glbl_param_offset =
18a8e864 2894 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
ce973b14 2895 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
4c35630c 2896 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
890de95e 2897 if (netif_msg_ifup(ugeth))
c84d8055 2898 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n");
ce973b14
LY		 2899 return -ENOMEM;
2900 }
2901
2902 ugeth->p_exf_glbl_param =
6fee40e9 2903 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2904 exf_glbl_param_offset);
2905 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2906 ugeth->exf_glbl_param_offset);
2907 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2908 (u32) ug_info->extendedFilteringChainPointer);
2909
2910 } else { /* initialize 82xx style address filtering */
2911
2912 /* Init individual address recognition registers to disabled */
2913
2914 for (j = 0; j < NUM_OF_PADDRS; j++)
2915 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2916
ce973b14 2917 p_82xx_addr_filt =
6fee40e9 2918 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2919 p_rx_glbl_pram->addressfiltering;
2920
2921 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2922 ENET_ADDR_TYPE_GROUP);
2923 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2924 ENET_ADDR_TYPE_INDIVIDUAL);
2925 }
2926
2927 /*
2928 * Initialize UCC at QE level
2929 */
2930
2931 command = QE_INIT_TX_RX;
2932
2933 /* Allocate shadow InitEnet command parameter structure.
2934 * This is needed because after the InitEnet command is executed,
2935 * the structure in DPRAM is released, because DPRAM is a premium
2936 * resource.
2937 * This shadow structure keeps a copy of what was done so that the
2938 * allocated resources can be released when the channel is freed.
2939 */
2940 if (!(ugeth->p_init_enet_param_shadow =
04b588d7 2941 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
890de95e 2942 if (netif_msg_ifup(ugeth))
c84d8055 2943 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n");
ce973b14
LY		 2944 return -ENOMEM;
2945 }
2946 /* Zero out *p_init_enet_param_shadow */
2947 memset((char *)ugeth->p_init_enet_param_shadow,
18a8e864 2948 0, sizeof(struct ucc_geth_init_pram));
ce973b14
LY		 2949
2950 /* Fill shadow InitEnet command parameter structure */
2951
2952 ugeth->p_init_enet_param_shadow->resinit1 =
2953 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2954 ugeth->p_init_enet_param_shadow->resinit2 =
2955 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2956 ugeth->p_init_enet_param_shadow->resinit3 =
2957 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2958 ugeth->p_init_enet_param_shadow->resinit4 =
2959 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2960 ugeth->p_init_enet_param_shadow->resinit5 =
2961 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2962 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2963 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2964 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2965 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2966
2967 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2968 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2969 if ((ug_info->largestexternallookupkeysize !=
8e95a202
JP		 2970 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2971 (ug_info->largestexternallookupkeysize !=
2972 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2973 (ug_info->largestexternallookupkeysize !=
2974 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
890de95e 2975 if (netif_msg_ifup(ugeth))
c84d8055 2976 pr_err("Invalid largest External Lookup Key Size\n");
ce973b14
LY		 2977 return -EINVAL;
2978 }
2979 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2980 ug_info->largestexternallookupkeysize;
18a8e864 2981 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 2982 if (ug_info->rxExtendedFiltering) {
2983 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2984 if (ug_info->largestexternallookupkeysize ==
8844a006 2985 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
ce973b14
LY		 2986 size +=
2987 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2988 if (ug_info->largestexternallookupkeysize ==
8844a006 2989 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
ce973b14
LY		 2990 size +=
2991 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2992 }
2993
2994 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2995 p_init_enet_param_shadow->rxthread[0]),
2996 (u8) (numThreadsRxNumerical + 1)
2997 /* Rx needs one extra for terminator */
2998 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2999 ug_info->riscRx, 1)) != 0) {
890de95e 3000 if (netif_msg_ifup(ugeth))
c84d8055 3001 pr_err("Can not fill p_init_enet_param_shadow\n");
ce973b14
LY		 3002 return ret_val;
3003 }
3004
3005 ugeth->p_init_enet_param_shadow->txglobal =
3006 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3007 if ((ret_val =
3008 fill_init_enet_entries(ugeth,
3009 &(ugeth->p_init_enet_param_shadow->
3010 txthread[0]), numThreadsTxNumerical,
18a8e864 3011 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 3012 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3013 ug_info->riscTx, 0)) != 0) {
890de95e 3014 if (netif_msg_ifup(ugeth))
c84d8055 3015 pr_err("Can not fill p_init_enet_param_shadow\n");
ce973b14
LY		 3016 return ret_val;
3017 }
3018
3019 /* Load Rx bds with buffers */
3020 for (i = 0; i < ug_info->numQueuesRx; i++) {
3021 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
890de95e 3022 if (netif_msg_ifup(ugeth))
c84d8055 3023 pr_err("Can not fill Rx bds with buffers\n");
ce973b14
LY		 3024 return ret_val;
3025 }
3026 }
3027
3028 /* Allocate InitEnet command parameter structure */
18a8e864 3029 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
4c35630c 3030 if (IS_ERR_VALUE(init_enet_pram_offset)) {
890de95e 3031 if (netif_msg_ifup(ugeth))
c84d8055 3032 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n");
ce973b14
LY		 3033 return -ENOMEM;
3034 }
3035 p_init_enet_pram =
6fee40e9 3036 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
ce973b14
LY		 3037
3038 /* Copy shadow InitEnet command parameter structure into PRAM */
6fee40e9
AF		 3039 out_8(&p_init_enet_pram->resinit1,
3040 ugeth->p_init_enet_param_shadow->resinit1);
3041 out_8(&p_init_enet_pram->resinit2,
3042 ugeth->p_init_enet_param_shadow->resinit2);
3043 out_8(&p_init_enet_pram->resinit3,
3044 ugeth->p_init_enet_param_shadow->resinit3);
3045 out_8(&p_init_enet_pram->resinit4,
3046 ugeth->p_init_enet_param_shadow->resinit4);
ce973b14
LY		 3047 out_be16(&p_init_enet_pram->resinit5,
3048 ugeth->p_init_enet_param_shadow->resinit5);
6fee40e9
AF		 3049 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3050 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
ce973b14
LY		 3051 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3052 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3053 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3054 out_be32(&p_init_enet_pram->rxthread[i],
3055 ugeth->p_init_enet_param_shadow->rxthread[i]);
3056 out_be32(&p_init_enet_pram->txglobal,
3057 ugeth->p_init_enet_param_shadow->txglobal);
3058 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3059 out_be32(&p_init_enet_pram->txthread[i],
3060 ugeth->p_init_enet_param_shadow->txthread[i]);
3061
3062 /* Issue QE command */
3063 cecr_subblock =
3064 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 3065 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 3066 init_enet_pram_offset);
3067
3068 /* Free InitEnet command parameter */
3069 qe_muram_free(init_enet_pram_offset);
3070
3071 return 0;
3072}
3073
ce973b14
LY		 3074/* This is called by the kernel when a frame is ready for transmission. */
3075/* It is pointed to by the dev->hard_start_xmit function pointer */
06983aa5
Y		 3076static netdev_tx_t
3077ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
ce973b14 3078{
18a8e864 3079 struct ucc_geth_private *ugeth = netdev_priv(dev);
d5b9049d
MR		 3080#ifdef CONFIG_UGETH_TX_ON_DEMAND
3081 struct ucc_fast_private *uccf;
3082#endif
6fee40e9 3083 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3084 u32 bd_status;
3085 u8 txQ = 0;
22580f89 3086 unsigned long flags;
ce973b14 3087
b39d66a8 3088 ugeth_vdbg("%s: IN", __func__);
ce973b14 3089
f79e7115 3090 netdev_sent_queue(dev, skb->len);
22580f89 3091 spin_lock_irqsave(&ugeth->lock, flags);
ce973b14 3092
09f75cd7 3093 dev->stats.tx_bytes += skb->len;
ce973b14
LY		 3094
3095 /* Start from the next BD that should be filled */
3096 bd = ugeth->txBd[txQ];
6fee40e9 3097 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3098 /* Save the skb pointer so we can free it later */
3099 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3100
3101 /* Update the current skb pointer (wrapping if this was the last) */
3102 ugeth->skb_curtx[txQ] =
3103 (ugeth->skb_curtx[txQ] +
3104 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3105
3106 /* set up the buffer descriptor */
6fee40e9 3107 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 3108 dma_map_single(ugeth->dev, skb->data,
7f80202b 3109 skb->len, DMA_TO_DEVICE));
ce973b14 3110
18a8e864 3111 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
ce973b14
LY		 3112
3113 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3114
18a8e864 3115 /* set bd status and length */
6fee40e9 3116 out_be32((u32 __iomem *)bd, bd_status);
ce973b14 3117
ce973b14
LY		 3118 /* Move to next BD in the ring */
3119 if (!(bd_status & T_W))
a394f013 3120 bd += sizeof(struct qe_bd);
ce973b14 3121 else
a394f013 3122 bd = ugeth->p_tx_bd_ring[txQ];
ce973b14
LY		 3123
3124 /* If the next BD still needs to be cleaned up, then the bds
3125 are full. We need to tell the kernel to stop sending us stuff. */
3126 if (bd == ugeth->confBd[txQ]) {
3127 if (!netif_queue_stopped(dev))
3128 netif_stop_queue(dev);
3129 }
3130
a394f013
LY		 3131 ugeth->txBd[txQ] = bd;
3132
d13d6bff
RC		 3133 skb_tx_timestamp(skb);
3134
ce973b14
LY		 3135 if (ugeth->p_scheduler) {
3136 ugeth->cpucount[txQ]++;
3137 /* Indicate to QE that there are more Tx bds ready for
3138 transmission */
3139 /* This is done by writing a running counter of the bd
3140 count to the scheduler PRAM. */
3141 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3142 }
3143
d5b9049d
MR		 3144#ifdef CONFIG_UGETH_TX_ON_DEMAND
3145 uccf = ugeth->uccf;
3146 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3147#endif
22580f89 3148 spin_unlock_irqrestore(&ugeth->lock, flags);
ce973b14 3149
6ed10654 3150 return NETDEV_TX_OK;
ce973b14
LY		 3151}
3152
18a8e864 3153static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
ce973b14
LY		 3154{
3155 struct sk_buff *skb;
6fee40e9 3156 u8 __iomem *bd;
ce973b14
LY		 3157 u16 length, howmany = 0;
3158 u32 bd_status;
3159 u8 *bdBuffer;
4b8fdefa 3160 struct net_device *dev;
ce973b14 3161
b39d66a8 3162 ugeth_vdbg("%s: IN", __func__);
ce973b14 3163
da1aa63e 3164 dev = ugeth->ndev;
88a15f2e 3165
ce973b14
LY		 3166 /* collect received buffers */
3167 bd = ugeth->rxBd[rxQ];
3168
6fee40e9 3169 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3170
3171 /* while there are received buffers and BD is full (~R_E) */
3172 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
6fee40e9 3173 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
ce973b14
LY		 3174 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3175 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3176
3177 /* determine whether buffer is first, last, first and last
3178 (single buffer frame) or middle (not first and not last) */
3179 if (!skb ||
3180 (!(bd_status & (R_F | R_L))) ||
3181 (bd_status & R_ERRORS_FATAL)) {
890de95e 3182 if (netif_msg_rx_err(ugeth))
c84d8055
JP		 3183 pr_err("%d: ERROR!!! skb - 0x%08x\n",
3184 __LINE__, (u32)skb);
66eef59f 3185 dev_kfree_skb(skb);
ce973b14
LY		 3186
3187 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
09f75cd7 3188 dev->stats.rx_dropped++;
ce973b14 3189 } else {
09f75cd7 3190 dev->stats.rx_packets++;
ce973b14
LY		 3191 howmany++;
3192
3193 /* Prep the skb for the packet */
3194 skb_put(skb, length);
3195
3196 /* Tell the skb what kind of packet this is */
da1aa63e 3197 skb->protocol = eth_type_trans(skb, ugeth->ndev);
ce973b14 3198
09f75cd7 3199 dev->stats.rx_bytes += length;
ce973b14 3200 /* Send the packet up the stack */
ce973b14 3201 netif_receive_skb(skb);
ce973b14
LY		 3202 }
3203
ce973b14
LY		 3204 skb = get_new_skb(ugeth, bd);
3205 if (!skb) {
890de95e 3206 if (netif_msg_rx_err(ugeth))
c84d8055 3207 pr_warn("No Rx Data Buffer\n");
09f75cd7 3208 dev->stats.rx_dropped++;
ce973b14
LY		 3209 break;
3210 }
3211
3212 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3213
3214 /* update to point at the next skb */
3215 ugeth->skb_currx[rxQ] =
3216 (ugeth->skb_currx[rxQ] +
3217 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3218
3219 if (bd_status & R_W)
3220 bd = ugeth->p_rx_bd_ring[rxQ];
3221 else
18a8e864 3222 bd += sizeof(struct qe_bd);
ce973b14 3223
6fee40e9 3224 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3225 }
3226
3227 ugeth->rxBd[rxQ] = bd;
ce973b14
LY		 3228 return howmany;
3229}
3230
3231static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3232{
3233 /* Start from the next BD that should be filled */
18a8e864 3234 struct ucc_geth_private *ugeth = netdev_priv(dev);
f79e7115
JT		 3235 unsigned int bytes_sent = 0;
3236 int howmany = 0;
6fee40e9 3237 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3238 u32 bd_status;
3239
3240 bd = ugeth->confBd[txQ];
6fee40e9 3241 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3242
3243 /* Normal processing. */
3244 while ((bd_status & T_R) == 0) {
50f238fd
AV		 3245 struct sk_buff *skb;
3246
ce973b14
LY		 3247 /* BD contains already transmitted buffer. */
3248 /* Handle the transmitted buffer and release */
3249 /* the BD to be used with the current frame */
3250
34692421
JW		 3251 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3252 if (!skb)
ce973b14 3253 break;
f79e7115
JT		 3254 howmany++;
3255 bytes_sent += skb->len;
09f75cd7 3256 dev->stats.tx_packets++;
ce973b14 3257
36145741 3258 dev_consume_skb_any(skb);
50f238fd 3259
ce973b14
LY		 3260 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3261 ugeth->skb_dirtytx[txQ] =
3262 (ugeth->skb_dirtytx[txQ] +
3263 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3264
3265 /* We freed a buffer, so now we can restart transmission */
3266 if (netif_queue_stopped(dev))
3267 netif_wake_queue(dev);
3268
3269 /* Advance the confirmation BD pointer */
3270 if (!(bd_status & T_W))
a394f013 3271 bd += sizeof(struct qe_bd);
ce973b14 3272 else
a394f013 3273 bd = ugeth->p_tx_bd_ring[txQ];
6fee40e9 3274 bd_status = in_be32((u32 __iomem *)bd);
ce973b14 3275 }
a394f013 3276 ugeth->confBd[txQ] = bd;
f79e7115 3277 netdev_completed_queue(dev, howmany, bytes_sent);
ce973b14
LY		 3278 return 0;
3279}
3280
bea3348e 3281static int ucc_geth_poll(struct napi_struct *napi, int budget)
ce973b14 3282{
bea3348e 3283 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
702ff12c 3284 struct ucc_geth_info *ug_info;
bea3348e 3285 int howmany, i;
ce973b14 3286
702ff12c
MR		 3287 ug_info = ugeth->ug_info;
3288
0cededf3
JT		 3289 /* Tx event processing */
3290 spin_lock(&ugeth->lock);
3291 for (i = 0; i < ug_info->numQueuesTx; i++)
3292 ucc_geth_tx(ugeth->ndev, i);
3293 spin_unlock(&ugeth->lock);
3294
50f238fd
AV		 3295 howmany = 0;
3296 for (i = 0; i < ug_info->numQueuesRx; i++)
3297 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3298
bea3348e 3299 if (howmany < budget) {
6ad20165 3300 napi_complete_done(napi, howmany);
0cededf3 3301 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3302 }
ce973b14 3303
bea3348e 3304 return howmany;
ce973b14 3305}
ce973b14 3306
7d12e780 3307static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
ce973b14 3308{
06efcad0 3309 struct net_device *dev = info;
18a8e864
LY		 3310 struct ucc_geth_private *ugeth = netdev_priv(dev);
3311 struct ucc_fast_private *uccf;
3312 struct ucc_geth_info *ug_info;
702ff12c
MR		 3313 register u32 ucce;
3314 register u32 uccm;
ce973b14 3315
b39d66a8 3316 ugeth_vdbg("%s: IN", __func__);
ce973b14 3317
ce973b14
LY		 3318 uccf = ugeth->uccf;
3319 ug_info = ugeth->ug_info;
3320
702ff12c
MR		 3321 /* read and clear events */
3322 ucce = (u32) in_be32(uccf->p_ucce);
3323 uccm = (u32) in_be32(uccf->p_uccm);
3324 ucce &= uccm;
3325 out_be32(uccf->p_ucce, ucce);
ce973b14 3326
702ff12c 3327 /* check for receive events that require processing */
0cededf3 3328 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
288379f0 3329 if (napi_schedule_prep(&ugeth->napi)) {
0cededf3 3330 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3331 out_be32(uccf->p_uccm, uccm);
288379f0 3332 __napi_schedule(&ugeth->napi);
702ff12c 3333 }
702ff12c 3334 }
ce973b14 3335
702ff12c
MR		 3336 /* Errors and other events */
3337 if (ucce & UCCE_OTHER) {
3bc53427 3338 if (ucce & UCC_GETH_UCCE_BSY)
09f75cd7 3339 dev->stats.rx_errors++;
3bc53427 3340 if (ucce & UCC_GETH_UCCE_TXE)
09f75cd7 3341 dev->stats.tx_errors++;
ce973b14 3342 }
ce973b14
LY		 3343
3344 return IRQ_HANDLED;
3345}
3346
26d29ea7
AV		 3347#ifdef CONFIG_NET_POLL_CONTROLLER
3348/*
3349 * Polling 'interrupt' - used by things like netconsole to send skbs
3350 * without having to re-enable interrupts. It's not called while
3351 * the interrupt routine is executing.
3352 */
3353static void ucc_netpoll(struct net_device *dev)
3354{
3355 struct ucc_geth_private *ugeth = netdev_priv(dev);
3356 int irq = ugeth->ug_info->uf_info.irq;
3357
3358 disable_irq(irq);
3359 ucc_geth_irq_handler(irq, dev);
3360 enable_irq(irq);
3361}
3362#endif /* CONFIG_NET_POLL_CONTROLLER */
3363
3d6593e9
KH		 3364static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3365{
3366 struct ucc_geth_private *ugeth = netdev_priv(dev);
3367 struct sockaddr *addr = p;
3368
3369 if (!is_valid_ether_addr(addr->sa_data))
3370 return -EADDRNOTAVAIL;
3371
3372 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3373
3374 /*
3375 * If device is not running, we will set mac addr register
3376 * when opening the device.
3377 */
3378 if (!netif_running(dev))
3379 return 0;
3380
3381 spin_lock_irq(&ugeth->lock);
3382 init_mac_station_addr_regs(dev->dev_addr[0],
3383 dev->dev_addr[1],
3384 dev->dev_addr[2],
3385 dev->dev_addr[3],
3386 dev->dev_addr[4],
3387 dev->dev_addr[5],
3388 &ugeth->ug_regs->macstnaddr1,
3389 &ugeth->ug_regs->macstnaddr2);
3390 spin_unlock_irq(&ugeth->lock);
3391
3392 return 0;
3393}
3394
54b15983 3395static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
ce973b14 3396{
54b15983 3397 struct net_device *dev = ugeth->ndev;
ce973b14
LY		 3398 int err;
3399
728de4c9
KP		 3400 err = ucc_struct_init(ugeth);
3401 if (err) {
c84d8055 3402 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n");
54b15983 3403 goto err;
728de4c9
KP		 3404 }
3405
ce973b14
LY		 3406 err = ucc_geth_startup(ugeth);
3407 if (err) {
c84d8055 3408 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
54b15983 3409 goto err;
ce973b14
LY		 3410 }
3411
3412 err = adjust_enet_interface(ugeth);
3413 if (err) {
c84d8055 3414 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
54b15983 3415 goto err;
ce973b14
LY		 3416 }
3417
3418 /* Set MACSTNADDR1, MACSTNADDR2 */
3419 /* For more details see the hardware spec. */
3420 init_mac_station_addr_regs(dev->dev_addr[0],
3421 dev->dev_addr[1],
3422 dev->dev_addr[2],
3423 dev->dev_addr[3],
3424 dev->dev_addr[4],
3425 dev->dev_addr[5],
3426 &ugeth->ug_regs->macstnaddr1,
3427 &ugeth->ug_regs->macstnaddr2);
3428
67c2fb8f 3429 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
ce973b14 3430 if (err) {
c84d8055 3431 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n");
54b15983
AV		 3432 goto err;
3433 }
3434
3435 return 0;
3436err:
3437 ucc_geth_stop(ugeth);
3438 return err;
3439}
3440
3441/* Called when something needs to use the ethernet device */
3442/* Returns 0 for success. */
3443static int ucc_geth_open(struct net_device *dev)
3444{
3445 struct ucc_geth_private *ugeth = netdev_priv(dev);
3446 int err;
3447
3448 ugeth_vdbg("%s: IN", __func__);
3449
3450 /* Test station address */
3451 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
c84d8055
JP		 3452 netif_err(ugeth, ifup, dev,
3453 "Multicast address used for station address - is this what you wanted?\n");
54b15983
AV		 3454 return -EINVAL;
3455 }
3456
3457 err = init_phy(dev);
3458 if (err) {
c84d8055 3459 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n");
54b15983
AV		 3460 return err;
3461 }
3462
3463 err = ucc_geth_init_mac(ugeth);
3464 if (err) {
c84d8055 3465 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n");
54b15983 3466 goto err;
ce973b14 3467 }
ce973b14 3468
67c2fb8f
AV		 3469 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3470 0, "UCC Geth", dev);
ce973b14 3471 if (err) {
c84d8055 3472 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n");
54b15983 3473 goto err;
ce973b14
LY		 3474 }
3475
54b15983
AV		 3476 phy_start(ugeth->phydev);
3477 napi_enable(&ugeth->napi);
f79e7115 3478 netdev_reset_queue(dev);
ce973b14
LY		 3479 netif_start_queue(dev);
3480
2394905f
AV		 3481 device_set_wakeup_capable(&dev->dev,
3482 qe_alive_during_sleep() || ugeth->phydev->irq);
3483 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3484
ce973b14 3485 return err;
bea3348e 3486
54b15983 3487err:
ba574696 3488 ucc_geth_stop(ugeth);
bea3348e 3489 return err;
ce973b14
LY		 3490}
3491
3492/* Stops the kernel queue, and halts the controller */
3493static int ucc_geth_close(struct net_device *dev)
3494{
18a8e864 3495 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14 3496
b39d66a8 3497 ugeth_vdbg("%s: IN", __func__);
ce973b14 3498
bea3348e 3499 napi_disable(&ugeth->napi);
bea3348e 3500
2040bd57 3501 cancel_work_sync(&ugeth->timeout_work);
ce973b14 3502 ucc_geth_stop(ugeth);
2040bd57
JT		 3503 phy_disconnect(ugeth->phydev);
3504 ugeth->phydev = NULL;
ce973b14 3505
da1aa63e 3506 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
67c2fb8f 3507
ce973b14 3508 netif_stop_queue(dev);
f79e7115 3509 netdev_reset_queue(dev);
ce973b14
LY		 3510
3511 return 0;
3512}
3513
fdb614c2
AV		 3514/* Reopen device. This will reset the MAC and PHY. */
3515static void ucc_geth_timeout_work(struct work_struct *work)
3516{
3517 struct ucc_geth_private *ugeth;
3518 struct net_device *dev;
3519
3520 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
da1aa63e 3521 dev = ugeth->ndev;
fdb614c2
AV		 3522
3523 ugeth_vdbg("%s: IN", __func__);
3524
3525 dev->stats.tx_errors++;
3526
3527 ugeth_dump_regs(ugeth);
3528
3529 if (dev->flags & IFF_UP) {
3530 /*
3531 * Must reset MAC *and* PHY. This is done by reopening
3532 * the device.
3533 */
2040bd57
JT		 3534 netif_tx_stop_all_queues(dev);
3535 ucc_geth_stop(ugeth);
3536 ucc_geth_init_mac(ugeth);
3537 /* Must start PHY here */
3538 phy_start(ugeth->phydev);
3539 netif_tx_start_all_queues(dev);
fdb614c2
AV		 3540 }
3541
3542 netif_tx_schedule_all(dev);
3543}
3544
3545/*
3546 * ucc_geth_timeout gets called when a packet has not been
3547 * transmitted after a set amount of time.
3548 */
0290bd29 3549static void ucc_geth_timeout(struct net_device *dev, unsigned int txqueue)
fdb614c2
AV		 3550{
3551 struct ucc_geth_private *ugeth = netdev_priv(dev);
3552
fdb614c2
AV		 3553 schedule_work(&ugeth->timeout_work);
3554}
3555
2394905f
AV		 3556
3557#ifdef CONFIG_PM
3558
2dc11581 3559static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
2394905f 3560{
8513fbd8 3561 struct net_device *ndev = platform_get_drvdata(ofdev);
2394905f
AV		 3562 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3563
3564 if (!netif_running(ndev))
3565 return 0;
3566
29fb00e0 3567 netif_device_detach(ndev);
2394905f
AV		 3568 napi_disable(&ugeth->napi);
3569
3570 /*
3571 * Disable the controller, otherwise we'll wakeup on any network
3572 * activity.
3573 */
3574 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3575
3576 if (ugeth->wol_en & WAKE_MAGIC) {
3577 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3578 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3579 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3580 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3581 phy_stop(ugeth->phydev);
3582 }
3583
3584 return 0;
3585}
3586
2dc11581 3587static int ucc_geth_resume(struct platform_device *ofdev)
2394905f 3588{
8513fbd8 3589 struct net_device *ndev = platform_get_drvdata(ofdev);
2394905f
AV		 3590 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3591 int err;
3592
3593 if (!netif_running(ndev))
3594 return 0;
3595
3596 if (qe_alive_during_sleep()) {
3597 if (ugeth->wol_en & WAKE_MAGIC) {
3598 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3599 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3600 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3601 }
3602 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3603 } else {
3604 /*
3605 * Full reinitialization is required if QE shuts down
3606 * during sleep.
3607 */
3608 ucc_geth_memclean(ugeth);
3609
3610 err = ucc_geth_init_mac(ugeth);
3611 if (err) {
c84d8055 3612 netdev_err(ndev, "Cannot initialize MAC, aborting\n");
2394905f
AV		 3613 return err;
3614 }
3615 }
3616
3617 ugeth->oldlink = 0;
3618 ugeth->oldspeed = 0;
3619 ugeth->oldduplex = -1;
3620
3621 phy_stop(ugeth->phydev);
3622 phy_start(ugeth->phydev);
3623
3624 napi_enable(&ugeth->napi);
29fb00e0 3625 netif_device_attach(ndev);
2394905f
AV		 3626
3627 return 0;
3628}
3629
3630#else
3631#define ucc_geth_suspend NULL
3632#define ucc_geth_resume NULL
3633#endif
3634
4e19b5c1 3635static phy_interface_t to_phy_interface(const char *phy_connection_type)
728de4c9 3636{
4e19b5c1 3637 if (strcasecmp(phy_connection_type, "mii") == 0)
728de4c9 3638 return PHY_INTERFACE_MODE_MII;
4e19b5c1 3639 if (strcasecmp(phy_connection_type, "gmii") == 0)
728de4c9 3640 return PHY_INTERFACE_MODE_GMII;
4e19b5c1 3641 if (strcasecmp(phy_connection_type, "tbi") == 0)
728de4c9 3642 return PHY_INTERFACE_MODE_TBI;
4e19b5c1 3643 if (strcasecmp(phy_connection_type, "rmii") == 0)
728de4c9 3644 return PHY_INTERFACE_MODE_RMII;
4e19b5c1 3645 if (strcasecmp(phy_connection_type, "rgmii") == 0)
728de4c9 3646 return PHY_INTERFACE_MODE_RGMII;
4e19b5c1 3647 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
728de4c9 3648 return PHY_INTERFACE_MODE_RGMII_ID;
bd0ceaab
KP		 3649 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3650 return PHY_INTERFACE_MODE_RGMII_TXID;
3651 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3652 return PHY_INTERFACE_MODE_RGMII_RXID;
4e19b5c1 3653 if (strcasecmp(phy_connection_type, "rtbi") == 0)
728de4c9 3654 return PHY_INTERFACE_MODE_RTBI;
047584ce
HW		 3655 if (strcasecmp(phy_connection_type, "sgmii") == 0)
3656 return PHY_INTERFACE_MODE_SGMII;
728de4c9
KP		 3657
3658 return PHY_INTERFACE_MODE_MII;
3659}
3660
d19b5149
SM		 3661static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3662{
3663 struct ucc_geth_private *ugeth = netdev_priv(dev);
3664
3665 if (!netif_running(dev))
3666 return -EINVAL;
3667
3668 if (!ugeth->phydev)
3669 return -ENODEV;
3670
28b04113 3671 return phy_mii_ioctl(ugeth->phydev, rq, cmd);
d19b5149
SM		 3672}
3673
a9dbae78
JT		 3674static const struct net_device_ops ucc_geth_netdev_ops = {
3675 .ndo_open = ucc_geth_open,
3676 .ndo_stop = ucc_geth_close,
3677 .ndo_start_xmit = ucc_geth_start_xmit,
3678 .ndo_validate_addr = eth_validate_addr,
a28777f2 3679 .ndo_change_carrier = fixed_phy_change_carrier,
3d6593e9 3680 .ndo_set_mac_address = ucc_geth_set_mac_addr,
afc4b13d 3681 .ndo_set_rx_mode = ucc_geth_set_multi,
a9dbae78 3682 .ndo_tx_timeout = ucc_geth_timeout,
d19b5149 3683 .ndo_do_ioctl = ucc_geth_ioctl,
a9dbae78
JT		 3684#ifdef CONFIG_NET_POLL_CONTROLLER
3685 .ndo_poll_controller = ucc_netpoll,
3686#endif
3687};
3688
74888760 3689static int ucc_geth_probe(struct platform_device* ofdev)
ce973b14 3690{
18a8e864 3691 struct device *device = &ofdev->dev;
61c7a080 3692 struct device_node *np = ofdev->dev.of_node;
ce973b14
LY		 3693 struct net_device *dev = NULL;
3694 struct ucc_geth_private *ugeth = NULL;
3695 struct ucc_geth_info *ug_info;
18a8e864 3696 struct resource res;
728de4c9 3697 int err, ucc_num, max_speed = 0;
18a8e864 3698 const unsigned int *prop;
9fb1e350 3699 const char *sprop;
9b4c7a4e 3700 const void *mac_addr;
728de4c9
KP		 3701 phy_interface_t phy_interface;
3702 static const int enet_to_speed[] = {
3703 SPEED_10, SPEED_10, SPEED_10,
3704 SPEED_100, SPEED_100, SPEED_100,
3705 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3706 };
3707 static const phy_interface_t enet_to_phy_interface[] = {
3708 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3709 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3710 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3711 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3712 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
047584ce 3713 PHY_INTERFACE_MODE_SGMII,
728de4c9 3714 };
ce973b14 3715
b39d66a8 3716 ugeth_vdbg("%s: IN", __func__);
ce973b14 3717
56626f33
AV		 3718 prop = of_get_property(np, "cell-index", NULL);
3719 if (!prop) {
3720 prop = of_get_property(np, "device-id", NULL);
3721 if (!prop)
3722 return -ENODEV;
3723 }
3724
18a8e864
LY		 3725 ucc_num = *prop - 1;
3726 if ((ucc_num < 0) || (ucc_num > 7))
3727 return -ENODEV;
3728
3729 ug_info = &ugeth_info[ucc_num];
890de95e
LY		 3730 if (ug_info == NULL) {
3731 if (netif_msg_probe(&debug))
c84d8055 3732 pr_err("[%d] Missing additional data!\n", ucc_num);
890de95e
LY		 3733 return -ENODEV;
3734 }
3735
18a8e864 3736 ug_info->uf_info.ucc_num = ucc_num;
728de4c9 3737
9fb1e350
TT		 3738 sprop = of_get_property(np, "rx-clock-name", NULL);
3739 if (sprop) {
3740 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3741 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3742 (ug_info->uf_info.rx_clock > QE_CLK24)) {
c84d8055 3743 pr_err("invalid rx-clock-name property\n");
9fb1e350
TT		 3744 return -EINVAL;
3745 }
3746 } else {
3747 prop = of_get_property(np, "rx-clock", NULL);
3748 if (!prop) {
3749 /* If both rx-clock-name and rx-clock are missing,
3750 we want to tell people to use rx-clock-name. */
c84d8055 3751 pr_err("missing rx-clock-name property\n");
9fb1e350
TT		 3752 return -EINVAL;
3753 }
3754 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
b9780a81 3755 pr_err("invalid rx-clock property\n");
9fb1e350
TT		 3756 return -EINVAL;
3757 }
3758 ug_info->uf_info.rx_clock = *prop;
3759 }
3760
3761 sprop = of_get_property(np, "tx-clock-name", NULL);
3762 if (sprop) {
3763 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3764 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3765 (ug_info->uf_info.tx_clock > QE_CLK24)) {
c84d8055 3766 pr_err("invalid tx-clock-name property\n");
9fb1e350
TT		 3767 return -EINVAL;
3768 }
3769 } else {
e410553f 3770 prop = of_get_property(np, "tx-clock", NULL);
9fb1e350 3771 if (!prop) {
c84d8055 3772 pr_err("missing tx-clock-name property\n");
9fb1e350
TT		 3773 return -EINVAL;
3774 }
3775 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
c84d8055 3776 pr_err("invalid tx-clock property\n");
9fb1e350
TT		 3777 return -EINVAL;
3778 }
3779 ug_info->uf_info.tx_clock = *prop;
3780 }
3781
18a8e864
LY		 3782 err = of_address_to_resource(np, 0, &res);
3783 if (err)
3784 return -EINVAL;
3785
3786 ug_info->uf_info.regs = res.start;
3787 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3104a6ff
AV		 3788
3789 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
a1f7d81b
UKK		 3790 if (!ug_info->phy_node && of_phy_is_fixed_link(np)) {
3791 /*
3792 * In the case of a fixed PHY, the DT node associated
87009814
FF		 3793 * to the PHY is the Ethernet MAC DT node.
3794 */
a1f7d81b
UKK		 3795 err = of_phy_register_fixed_link(np);
3796 if (err)
3797 return err;
f1f02fa4 3798 ug_info->phy_node = of_node_get(np);
87009814 3799 }
728de4c9 3800
fb1001f3
HW		 3801 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3802 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3803
728de4c9 3804 /* get the phy interface type, or default to MII */
4e19b5c1 3805 prop = of_get_property(np, "phy-connection-type", NULL);
728de4c9
KP		 3806 if (!prop) {
3807 /* handle interface property present in old trees */
3104a6ff 3808 prop = of_get_property(ug_info->phy_node, "interface", NULL);
4e19b5c1 3809 if (prop != NULL) {
728de4c9 3810 phy_interface = enet_to_phy_interface[*prop];
4e19b5c1
KP		 3811 max_speed = enet_to_speed[*prop];
3812 } else
728de4c9
KP		 3813 phy_interface = PHY_INTERFACE_MODE_MII;
3814 } else {
3815 phy_interface = to_phy_interface((const char *)prop);
3816 }
3817
4e19b5c1
KP		 3818 /* get speed, or derive from PHY interface */
3819 if (max_speed == 0)
728de4c9
KP		 3820 switch (phy_interface) {
3821 case PHY_INTERFACE_MODE_GMII:
3822 case PHY_INTERFACE_MODE_RGMII:
3823 case PHY_INTERFACE_MODE_RGMII_ID:
bd0ceaab
KP		 3824 case PHY_INTERFACE_MODE_RGMII_RXID:
3825 case PHY_INTERFACE_MODE_RGMII_TXID:
728de4c9
KP		 3826 case PHY_INTERFACE_MODE_TBI:
3827 case PHY_INTERFACE_MODE_RTBI:
047584ce 3828 case PHY_INTERFACE_MODE_SGMII:
728de4c9
KP		 3829 max_speed = SPEED_1000;
3830 break;
3831 default:
3832 max_speed = SPEED_100;
3833 break;
3834 }
728de4c9
KP		 3835
3836 if (max_speed == SPEED_1000) {
fa1b42b4
DL		 3837 unsigned int snums = qe_get_num_of_snums();
3838
4e19b5c1 3839 /* configure muram FIFOs for gigabit operation */
728de4c9
KP		 3840 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3841 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3842 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3843 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3844 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3845 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ffea31ed 3846 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
674e4f93 3847
fa1b42b4 3848 /* If QE's snum number is 46/76 which means we need to support
674e4f93
HW		 3849 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3850 * more Threads to Rx.
3851 */
fa1b42b4 3852 if ((snums == 76) || (snums == 46))
674e4f93
HW		 3853 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3854 else
3855 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
728de4c9
KP		 3856 }
3857
890de95e 3858 if (netif_msg_probe(&debug))
2df9d673
VL		 3859 pr_info("UCC%1d at 0x%8llx (irq = %d)\n",
3860 ug_info->uf_info.ucc_num + 1,
3861 (u64)ug_info->uf_info.regs,
890de95e 3862 ug_info->uf_info.irq);
ce973b14 3863
ce973b14
LY		 3864 /* Create an ethernet device instance */
3865 dev = alloc_etherdev(sizeof(*ugeth));
3866
fa310789 3867 if (dev == NULL) {
0807c4ce
JH		 3868 err = -ENOMEM;
3869 goto err_deregister_fixed_link;
fa310789 3870 }
ce973b14
LY		 3871
3872 ugeth = netdev_priv(dev);
3873 spin_lock_init(&ugeth->lock);
3874
80a9fad8
AV		 3875 /* Create CQs for hash tables */
3876 INIT_LIST_HEAD(&ugeth->group_hash_q);
3877 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3878
ce973b14
LY		 3879 dev_set_drvdata(device, dev);
3880
3881 /* Set the dev->base_addr to the gfar reg region */
3882 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3883
ce973b14
LY		 3884 SET_NETDEV_DEV(dev, device);
3885
3886 /* Fill in the dev structure */
ac421852 3887 uec_set_ethtool_ops(dev);
a9dbae78 3888 dev->netdev_ops = &ucc_geth_netdev_ops;
ce973b14 3889 dev->watchdog_timeo = TX_TIMEOUT;
1762a29a 3890 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
0cededf3 3891 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
ce973b14 3892 dev->mtu = 1500;
ce973b14 3893
890de95e 3894 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
728de4c9
KP		 3895 ugeth->phy_interface = phy_interface;
3896 ugeth->max_speed = max_speed;
3897
1452db76
CC		 3898 /* Carrier starts down, phylib will bring it up */
3899 netif_carrier_off(dev);
3900
ce973b14
LY		 3901 err = register_netdev(dev);
3902 if (err) {
890de95e 3903 if (netif_msg_probe(ugeth))
c84d8055
JP		 3904 pr_err("%s: Cannot register net device, aborting\n",
3905 dev->name);
0807c4ce 3906 goto err_free_netdev;
ce973b14
LY		 3907 }
3908
e9eb70c9 3909 mac_addr = of_get_mac_address(np);
a51645f7 3910 if (!IS_ERR(mac_addr))
2d2924af 3911 ether_addr_copy(dev->dev_addr, mac_addr);
ce973b14 3912
728de4c9 3913 ugeth->ug_info = ug_info;
da1aa63e
AV		 3914 ugeth->dev = device;
3915 ugeth->ndev = dev;
b1c4a9dd 3916 ugeth->node = np;
728de4c9 3917
ce973b14 3918 return 0;
0807c4ce
JH		 3919
3920err_free_netdev:
3921 free_netdev(dev);
3922err_deregister_fixed_link:
3923 if (of_phy_is_fixed_link(np))
3924 of_phy_deregister_fixed_link(np);
3925 of_node_put(ug_info->tbi_node);
3926 of_node_put(ug_info->phy_node);
3927
3928 return err;
ce973b14
LY		 3929}
3930
2dc11581 3931static int ucc_geth_remove(struct platform_device* ofdev)
ce973b14 3932{
65d7e7ad 3933 struct net_device *dev = platform_get_drvdata(ofdev);
ce973b14 3934 struct ucc_geth_private *ugeth = netdev_priv(dev);
0807c4ce 3935 struct device_node *np = ofdev->dev.of_node;
ce973b14 3936
80a9fad8 3937 unregister_netdev(dev);
ce973b14 3938 free_netdev(dev);
80a9fad8 3939 ucc_geth_memclean(ugeth);
0807c4ce
JH		 3940 if (of_phy_is_fixed_link(np))
3941 of_phy_deregister_fixed_link(np);
4da5e6a0
UKK		 3942 of_node_put(ugeth->ug_info->tbi_node);
3943 of_node_put(ugeth->ug_info->phy_node);
ce973b14
LY		 3944
3945 return 0;
3946}
3947
94e5a2a8 3948static const struct of_device_id ucc_geth_match[] = {
18a8e864
LY		 3949 {
3950 .type = "network",
3951 .compatible = "ucc_geth",
3952 },
3953 {},
3954};
3955
3956MODULE_DEVICE_TABLE(of, ucc_geth_match);
3957
74888760 3958static struct platform_driver ucc_geth_driver = {
4018294b
GL		 3959 .driver = {
3960 .name = DRV_NAME,
4018294b
GL		 3961 .of_match_table = ucc_geth_match,
3962 },
18a8e864
LY		 3963 .probe = ucc_geth_probe,
3964 .remove = ucc_geth_remove,
2394905f
AV		 3965 .suspend = ucc_geth_suspend,
3966 .resume = ucc_geth_resume,
ce973b14
LY		 3967};
3968
3969static int __init ucc_geth_init(void)
3970{
728de4c9
KP		 3971 int i, ret;
3972
890de95e 3973 if (netif_msg_drv(&debug))
c84d8055 3974 pr_info(DRV_DESC "\n");
ce973b14
LY		 3975 for (i = 0; i < 8; i++)
3976 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3977 sizeof(ugeth_primary_info));
3978
74888760 3979 ret = platform_driver_register(&ucc_geth_driver);
728de4c9 3980
728de4c9 3981 return ret;
ce973b14
LY		 3982}
3983
3984static void __exit ucc_geth_exit(void)
3985{
74888760 3986 platform_driver_unregister(&ucc_geth_driver);
ce973b14
LY		 3987}
3988
3989module_init(ucc_geth_init);
3990module_exit(ucc_geth_exit);
3991
3992MODULE_AUTHOR("Freescale Semiconductor, Inc");
3993MODULE_DESCRIPTION(DRV_DESC);
3994MODULE_LICENSE("GPL");
A mirror of Linus' kernel repository