[thirdparty/kernel/linux.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_misc.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "hns_dsaf_mac.h"
#include "hns_dsaf_misc.h"
#include "hns_dsaf_ppe.h"
#include "hns_dsaf_reg.h"

enum _dsm_op_index {
	HNS_OP_RESET_FUNC               = 0x1,
	HNS_OP_SERDES_LP_FUNC           = 0x2,
	HNS_OP_LED_SET_FUNC             = 0x3,
	HNS_OP_GET_PORT_TYPE_FUNC       = 0x4,
	HNS_OP_GET_SFP_STAT_FUNC        = 0x5,
};

enum _dsm_rst_type {
	HNS_DSAF_RESET_FUNC     = 0x1,
	HNS_PPE_RESET_FUNC      = 0x2,
	HNS_XGE_CORE_RESET_FUNC = 0x3,
	HNS_XGE_RESET_FUNC      = 0x4,
	HNS_GE_RESET_FUNC       = 0x5,
};

const u8 hns_dsaf_acpi_dsm_uuid[] = {
	0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41,
	0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A
};

static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
{
	if (dsaf_dev->sub_ctrl)
		dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	else
		dsaf_write_reg(dsaf_dev->sc_base, reg, val);
}

static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
{
	u32 ret;

	if (dsaf_dev->sub_ctrl)
		ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	else
		ret = dsaf_read_reg(dsaf_dev->sc_base, reg);

	return ret;
}

static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
			     u16 speed, int data)
{
	int speed_reg = 0;
	u8 value;

	if (!mac_cb) {
		pr_err("sfp_led_opt mac_dev is null!\n");
		return;
	}
	if (!mac_cb->cpld_ctrl) {
		dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
			mac_cb->mac_id);
		return;
	}

	if (speed == MAC_SPEED_10000)
		speed_reg = 1;

	value = mac_cb->cpld_led_value;

	if (link_status) {
		dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
		dsaf_set_field(value, DSAF_LED_SPEED_M,
			       DSAF_LED_SPEED_S, speed_reg);
		dsaf_set_bit(value, DSAF_LED_DATA_B, data);

		if (value != mac_cb->cpld_led_value) {
			dsaf_write_syscon(mac_cb->cpld_ctrl,
					  mac_cb->cpld_ctrl_reg, value);
			mac_cb->cpld_led_value = value;
		}
	} else {
		value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B);
		dsaf_write_syscon(mac_cb->cpld_ctrl,
				  mac_cb->cpld_ctrl_reg, value);
		mac_cb->cpld_led_value = value;
	}
}

static void cpld_led_reset(struct hns_mac_cb *mac_cb)
{
	if (!mac_cb || !mac_cb->cpld_ctrl)
		return;

	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
			  CPLD_LED_DEFAULT_VALUE);
	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
}

static int cpld_set_led_id(struct hns_mac_cb *mac_cb,
			   enum hnae_led_state status)
{
	switch (status) {
	case HNAE_LED_ACTIVE:
		mac_cb->cpld_led_value =
			dsaf_read_syscon(mac_cb->cpld_ctrl,
					 mac_cb->cpld_ctrl_reg);
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_ON_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		break;
	case HNAE_LED_INACTIVE:
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_DEFAULT_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		break;
	default:
		dev_err(mac_cb->dev, "invalid led state: %d!", status);
		return -EINVAL;
	}

	return 0;
}

#define RESET_REQ_OR_DREQ 1

static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type,
				       u32 port_type, u32 port, u32 val)
{
	union acpi_object *obj;
	union acpi_object obj_args[3], argv4;

	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	obj_args[0].integer.value = port_type;
	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	obj_args[1].integer.value = port;
	obj_args[2].integer.type = ACPI_TYPE_INTEGER;
	obj_args[2].integer.value = val;

	argv4.type = ACPI_TYPE_PACKAGE;
	argv4.package.count = 3;
	argv4.package.elements = obj_args;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev),
				hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4);
	if (!obj) {
		dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!",
			 port_type, port);
		return;
	}

	ACPI_FREE(obj);
}

static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset)
{
	u32 xbar_reg_addr;
	u32 nt_reg_addr;

	if (!dereset) {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	} else {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
}

static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_DSAF_RESET_FUNC,
				   0, dereset);
}

static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
				      bool dereset)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= RESET_REQ_OR_DREQ;
	reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;

	if (!dereset)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
					   u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_XGE_RESET_FUNC, port, dereset);
}

static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
					   u32 port, bool dereset)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= XGMAC_TRX_CORE_SRST_M
		<< dsaf_dev->mac_cb[port]->port_rst_off;

	if (!dereset)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

static void
hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
				    u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_XGE_CORE_RESET_FUNC, port, dereset);
}

static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
				     bool dereset)
{
	u32 reg_val_1;
	u32 reg_val_2;
	u32 port_rst_off;

	if (port >= DSAF_GE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val_1  = 0x1 << port;
		port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
		/* there is difference between V1 and V2 in register.*/
		reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ?
				0x1041041 : 0x2082082;
		reg_val_2 <<= port_rst_off;

		if (!dereset) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
				       reg_val_2);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);
		}
	} else {
		reg_val_1 = 0x15540;
		reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40;

		reg_val_1 <<= dsaf_dev->reset_offset;
		reg_val_2 <<= dsaf_dev->reset_offset;

		if (!dereset) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
				       reg_val_2);
		}
	}
}

static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
					  u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_GE_RESET_FUNC, port, dereset);
}

static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
				 bool dereset)
{
	u32 reg_val = 0;
	u32 reg_addr;

	reg_val |= RESET_REQ_OR_DREQ <<	dsaf_dev->mac_cb[port]->port_rst_off;

	if (!dereset)
		reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

static void
hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_PPE_RESET_FUNC, port, dereset);
}

static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset)
{
	u32 reg_val;
	u32 reg_addr;

	if (!(dev_of_node(dsaf_dev->dev)))
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val = RESET_REQ_OR_DREQ;
		if (!dereset)
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;

	} else {
		reg_val = 0x100 << dsaf_dev->reset_offset;

		if (!dereset)
			reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

/**
 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
 * @mac_cb: mac control block
 * retuen phy interface
 */
static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
{
	u32 mode;
	u32 reg;
	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
	int mac_id = mac_cb->mac_id;
	phy_interface_t phy_if;

	if (is_ver1) {
		if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
			return PHY_INTERFACE_MODE_SGMII;

		if (mac_id >= 0 && mac_id <= 3)
			reg = HNS_MAC_HILINK4_REG;
		else
			reg = HNS_MAC_HILINK3_REG;
	} else{
		if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
			reg = HNS_MAC_HILINK4V2_REG;
		else
			reg = HNS_MAC_HILINK3V2_REG;
	}

	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
	if (dsaf_get_bit(mode, mac_cb->port_mode_off))
		phy_if = PHY_INTERFACE_MODE_XGMII;
	else
		phy_if = PHY_INTERFACE_MODE_SGMII;

	return phy_if;
}

static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb)
{
	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
	union acpi_object *obj;
	union acpi_object obj_args, argv4;

	obj_args.integer.type = ACPI_TYPE_INTEGER;
	obj_args.integer.value = mac_cb->mac_id;

	argv4.type = ACPI_TYPE_PACKAGE,
	argv4.package.count = 1,
	argv4.package.elements = &obj_args,

	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
				hns_dsaf_acpi_dsm_uuid, 0,
				HNS_OP_GET_PORT_TYPE_FUNC, &argv4);

	if (!obj || obj->type != ACPI_TYPE_INTEGER)
		return phy_if;

	phy_if = obj->integer.value ?
		PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII;

	dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if);

	ACPI_FREE(obj);

	return phy_if;
}

int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
{
	if (!mac_cb->cpld_ctrl)
		return -ENODEV;

	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
					+ MAC_SFP_PORT_OFFSET);

	return 0;
}

/**
 * hns_mac_config_sds_loopback - set loop back for serdes
 * @mac_cb: mac control block
 * retuen 0 == success
 */
static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
{
	const u8 lane_id[] = {
		0,	/* mac 0 -> lane 0 */
		1,	/* mac 1 -> lane 1 */
		2,	/* mac 2 -> lane 2 */
		3,	/* mac 3 -> lane 3 */
		2,	/* mac 4 -> lane 2 */
		3,	/* mac 5 -> lane 3 */
		0,	/* mac 6 -> lane 0 */
		1	/* mac 7 -> lane 1 */
	};
#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);

	int sfp_prsnt;
	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);

	if (!mac_cb->phy_dev) {
		if (ret)
			pr_info("please confirm sfp is present or not\n");
		else
			if (!sfp_prsnt)
				pr_info("no sfp in this eth\n");
	}

	if (mac_cb->serdes_ctrl) {
		u32 origin;

		if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) {
#define HILINK_ACCESS_SEL_CFG		0x40008
			/* hilink4 & hilink3 use the same xge training and
			 * xge u adaptor. There is a hilink access sel cfg
			 * register to select which one to be configed
			 */
			if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
			    (mac_cb->mac_id <= 3))
				dsaf_write_syscon(mac_cb->serdes_ctrl,
						  HILINK_ACCESS_SEL_CFG, 0);
			else
				dsaf_write_syscon(mac_cb->serdes_ctrl,
						  HILINK_ACCESS_SEL_CFG, 3);
		}

		origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);

		dsaf_set_field(origin, 1ull << 10, 10, en);
		dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
	} else {
		u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
				(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
		dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
	}

	return 0;
}

static int
hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en)
{
	union acpi_object *obj;
	union acpi_object obj_args[3], argv4;

	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	obj_args[0].integer.value = mac_cb->mac_id;
	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	obj_args[1].integer.value = !!en;

	argv4.type = ACPI_TYPE_PACKAGE;
	argv4.package.count = 2;
	argv4.package.elements = obj_args;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev),
				hns_dsaf_acpi_dsm_uuid, 0,
				HNS_OP_SERDES_LP_FUNC, &argv4);
	if (!obj) {
		dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!",
			 mac_cb->mac_id);

		return -ENOTSUPP;
	}

	ACPI_FREE(obj);

	return 0;
}

struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev)
{
	struct dsaf_misc_op *misc_op;

	misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL);
	if (!misc_op)
		return NULL;

	if (dev_of_node(dsaf_dev->dev)) {
		misc_op->cpld_set_led = hns_cpld_set_led;
		misc_op->cpld_reset_led = cpld_led_reset;
		misc_op->cpld_set_led_id = cpld_set_led_id;

		misc_op->dsaf_reset = hns_dsaf_rst;
		misc_op->xge_srst = hns_dsaf_xge_srst_by_port;
		misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port;
		misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
		misc_op->ppe_srst = hns_ppe_srst_by_port;
		misc_op->ppe_comm_srst = hns_ppe_com_srst;

		misc_op->get_phy_if = hns_mac_get_phy_if;
		misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;

		misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback;
	} else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
		misc_op->cpld_set_led = hns_cpld_set_led;
		misc_op->cpld_reset_led = cpld_led_reset;
		misc_op->cpld_set_led_id = cpld_set_led_id;

		misc_op->dsaf_reset = hns_dsaf_rst_acpi;
		misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi;
		misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi;
		misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
		misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
		misc_op->ppe_comm_srst = hns_ppe_com_srst;

		misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
		misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;

		misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi;
	} else {
		devm_kfree(dsaf_dev->dev, (void *)misc_op);
		misc_op = NULL;
	}

	return (void *)misc_op;
}
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
511e6bc0	10	#include "hns_dsaf_mac.h"
2e2591b1	11	#include "hns_dsaf_misc.h"
511e6bc0	12	#include "hns_dsaf_ppe.h"
2e2591b1	13	#include "hns_dsaf_reg.h"
511e6bc0	14
f00ef863 KY	15	enum _dsm_op_index {
	16	HNS_OP_RESET_FUNC = 0x1,
	17	HNS_OP_SERDES_LP_FUNC = 0x2,
	18	HNS_OP_LED_SET_FUNC = 0x3,
	19	HNS_OP_GET_PORT_TYPE_FUNC = 0x4,
	20	HNS_OP_GET_SFP_STAT_FUNC = 0x5,
	21	};
	22
	23	enum _dsm_rst_type {
	24	HNS_DSAF_RESET_FUNC = 0x1,
	25	HNS_PPE_RESET_FUNC = 0x2,
	26	HNS_XGE_CORE_RESET_FUNC = 0x3,
	27	HNS_XGE_RESET_FUNC = 0x4,
	28	HNS_GE_RESET_FUNC = 0x5,
	29	};
	30
	31	const u8 hns_dsaf_acpi_dsm_uuid[] = {
	32	0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41,
	33	0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A
	34	};
	35
831d828b YZZ	36	static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
	37	{
	38	if (dsaf_dev->sub_ctrl)
	39	dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	40	else
	41	dsaf_write_reg(dsaf_dev->sc_base, reg, val);
	42	}
	43
	44	static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
	45	{
	46	u32 ret;
	47
	48	if (dsaf_dev->sub_ctrl)
	49	ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	50	else
	51	ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
	52
	53	return ret;
	54	}
	55
a24274aa KY	56	static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
a24274aa KY	57	u16 speed, int data)
511e6bc0	58	{
	59	int speed_reg = 0;
	60	u8 value;
	61
	62	if (!mac_cb) {
	63	pr_err("sfp_led_opt mac_dev is null!\n");
	64	return;
	65	}
31d4446d YZZ	66	if (!mac_cb->cpld_ctrl) {
31d4446d YZZ	67	dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
511e6bc0	68	mac_cb->mac_id);
	69	return;
	70	}
	71
	72	if (speed == MAC_SPEED_10000)
	73	speed_reg = 1;
	74
	75	value = mac_cb->cpld_led_value;
	76
	77	if (link_status) {
	78	dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
	79	dsaf_set_field(value, DSAF_LED_SPEED_M,
	80	DSAF_LED_SPEED_S, speed_reg);
	81	dsaf_set_bit(value, DSAF_LED_DATA_B, data);
	82
	83	if (value != mac_cb->cpld_led_value) {
31d4446d YZZ	84	dsaf_write_syscon(mac_cb->cpld_ctrl,
31d4446d YZZ	85	mac_cb->cpld_ctrl_reg, value);
511e6bc0	86	mac_cb->cpld_led_value = value;
	87	}
	88	} else {
d8a8371e DH	89	value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B);
	90	dsaf_write_syscon(mac_cb->cpld_ctrl,
	91	mac_cb->cpld_ctrl_reg, value);
	92	mac_cb->cpld_led_value = value;
511e6bc0	93	}
	94	}
	95
a24274aa	96	static void cpld_led_reset(struct hns_mac_cb *mac_cb)
511e6bc0	97	{
31d4446d	98	if (!mac_cb \|\| !mac_cb->cpld_ctrl)
511e6bc0	99	return;
511e6bc0	100
31d4446d YZZ	101	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	102	CPLD_LED_DEFAULT_VALUE);
511e6bc0	103	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	104	}
	105
a24274aa KY	106	static int cpld_set_led_id(struct hns_mac_cb *mac_cb,
a24274aa KY	107	enum hnae_led_state status)
511e6bc0	108	{
	109	switch (status) {
	110	case HNAE_LED_ACTIVE:
31d4446d YZZ	111	mac_cb->cpld_led_value =
	112	dsaf_read_syscon(mac_cb->cpld_ctrl,
	113	mac_cb->cpld_ctrl_reg);
511e6bc0	114	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
511e6bc0	115	CPLD_LED_ON_VALUE);
31d4446d YZZ	116	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	117	mac_cb->cpld_led_value);
d8a8371e	118	break;
511e6bc0	119	case HNAE_LED_INACTIVE:
	120	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
	121	CPLD_LED_DEFAULT_VALUE);
31d4446d YZZ	122	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	123	mac_cb->cpld_led_value);
511e6bc0	124	break;
511e6bc0	125	default:
d8a8371e DH	126	dev_err(mac_cb->dev, "invalid led state: %d!", status);
d8a8371e DH	127	return -EINVAL;
511e6bc0	128	}
	129
	130	return 0;
	131	}
	132
	133	#define RESET_REQ_OR_DREQ 1
	134
f00ef863 KY	135	static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type,
	136	u32 port_type, u32 port, u32 val)
	137	{
	138	union acpi_object *obj;
	139	union acpi_object obj_args[3], argv4;
	140
	141	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	142	obj_args[0].integer.value = port_type;
	143	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	144	obj_args[1].integer.value = port;
	145	obj_args[2].integer.type = ACPI_TYPE_INTEGER;
	146	obj_args[2].integer.value = val;
	147
	148	argv4.type = ACPI_TYPE_PACKAGE;
	149	argv4.package.count = 3;
	150	argv4.package.elements = obj_args;
	151
	152	obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev),
	153	hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4);
	154	if (!obj) {
	155	dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!",
	156	port_type, port);
	157	return;
	158	}
	159
	160	ACPI_FREE(obj);
	161	}
	162
a24274aa	163	static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset)
511e6bc0	164	{
	165	u32 xbar_reg_addr;
	166	u32 nt_reg_addr;
	167
a24274aa	168	if (!dereset) {
511e6bc0	169	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
	170	nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	171	} else {
	172	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
	173	nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	174	}
	175
831d828b YZZ	176	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
831d828b YZZ	177	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
511e6bc0	178	}
511e6bc0	179
f00ef863 KY	180	static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
	181	{
	182	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	183	HNS_DSAF_RESET_FUNC,
	184	0, dereset);
	185	}
	186
a24274aa KY	187	static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
a24274aa KY	188	bool dereset)
511e6bc0	189	{
	190	u32 reg_val = 0;
	191	u32 reg_addr;
	192
	193	if (port >= DSAF_XGE_NUM)
	194	return;
	195
	196	reg_val \|= RESET_REQ_OR_DREQ;
850bfa3b	197	reg_val \|= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	198
a24274aa	199	if (!dereset)
511e6bc0	200	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	201	else
	202	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	203
831d828b	204	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	205	}
511e6bc0	206
f00ef863 KY	207	static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
	208	u32 port, bool dereset)
	209	{
	210	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	211	HNS_XGE_RESET_FUNC, port, dereset);
	212	}
	213
a24274aa KY	214	static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
a24274aa KY	215	u32 port, bool dereset)
511e6bc0	216	{
	217	u32 reg_val = 0;
	218	u32 reg_addr;
	219
	220	if (port >= DSAF_XGE_NUM)
	221	return;
	222
850bfa3b YZZ	223	reg_val \|= XGMAC_TRX_CORE_SRST_M
850bfa3b YZZ	224	<< dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	225
a24274aa	226	if (!dereset)
511e6bc0	227	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	228	else
	229	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	230
831d828b	231	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	232	}
511e6bc0	233
f00ef863 KY	234	static void
	235	hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
	236	u32 port, bool dereset)
	237	{
	238	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	239	HNS_XGE_CORE_RESET_FUNC, port, dereset);
	240	}
	241
a24274aa KY	242	static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
a24274aa KY	243	bool dereset)
511e6bc0	244	{
	245	u32 reg_val_1;
	246	u32 reg_val_2;
850bfa3b	247	u32 port_rst_off;
511e6bc0	248
	249	if (port >= DSAF_GE_NUM)
	250	return;
	251
89a44093	252	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	253	reg_val_1 = 0x1 << port;
850bfa3b	254	port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
13ac695e	255	/* there is difference between V1 and V2 in register.*/
d9fdb4ed DH	256	reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ?
	257	0x1041041 : 0x2082082;
	258	reg_val_2 <<= port_rst_off;
511e6bc0	259
a24274aa	260	if (!dereset) {
831d828b	261	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	262	reg_val_1);
511e6bc0	263
831d828b	264	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
511e6bc0	265	reg_val_2);
511e6bc0	266	} else {
831d828b	267	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
511e6bc0	268	reg_val_2);
511e6bc0	269
831d828b	270	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	271	reg_val_1);
	272	}
	273	} else {
d9fdb4ed DH	274	reg_val_1 = 0x15540;
d9fdb4ed DH	275	reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40;
0b03fd85	276
d9fdb4ed DH	277	reg_val_1 <<= dsaf_dev->reset_offset;
d9fdb4ed DH	278	reg_val_2 <<= dsaf_dev->reset_offset;
511e6bc0	279
a24274aa	280	if (!dereset) {
831d828b	281	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	282	reg_val_1);
511e6bc0	283
831d828b	284	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
511e6bc0	285	reg_val_2);
511e6bc0	286	} else {
831d828b	287	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	288	reg_val_1);
511e6bc0	289
831d828b	290	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
511e6bc0	291	reg_val_2);
	292	}
	293	}
	294	}
	295
f00ef863 KY	296	static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
	297	u32 port, bool dereset)
	298	{
	299	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	300	HNS_GE_RESET_FUNC, port, dereset);
	301	}
	302
a24274aa KY	303	static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
a24274aa KY	304	bool dereset)
511e6bc0	305	{
	306	u32 reg_val = 0;
	307	u32 reg_addr;
	308
850bfa3b	309	reg_val \|= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	310
a24274aa	311	if (!dereset)
511e6bc0	312	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	313	else
	314	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	315
831d828b	316	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	317	}
511e6bc0	318
f00ef863 KY	319	static void
	320	hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset)
	321	{
	322	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	323	HNS_PPE_RESET_FUNC, port, dereset);
	324	}
	325
a24274aa	326	static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset)
511e6bc0	327	{
511e6bc0	328	u32 reg_val;
	329	u32 reg_addr;
	330
f00ef863 KY	331	if (!(dev_of_node(dsaf_dev->dev)))
	332	return;
	333
89a44093	334	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	335	reg_val = RESET_REQ_OR_DREQ;
a24274aa	336	if (!dereset)
511e6bc0	337	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
	338	else
	339	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
	340
	341	} else {
422c3107	342	reg_val = 0x100 << dsaf_dev->reset_offset;
511e6bc0	343
a24274aa	344	if (!dereset)
511e6bc0	345	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	346	else
	347	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	348	}
	349
831d828b	350	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	351	}
	352
	353	/**
	354	* hns_mac_get_sds_mode - get phy ifterface form serdes mode
	355	* @mac_cb: mac control block
	356	* retuen phy interface
	357	*/
a24274aa	358	static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
511e6bc0	359	{
c1203fe7 SL	360	u32 mode;
c1203fe7 SL	361	u32 reg;
c1203fe7	362	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
c1203fe7	363	int mac_id = mac_cb->mac_id;
0d768fc6	364	phy_interface_t phy_if;
511e6bc0	365
0d768fc6 YZZ	366	if (is_ver1) {
	367	if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
	368	return PHY_INTERFACE_MODE_SGMII;
	369
	370	if (mac_id >= 0 && mac_id <= 3)
	371	reg = HNS_MAC_HILINK4_REG;
511e6bc0	372	else
0d768fc6 YZZ	373	reg = HNS_MAC_HILINK3_REG;
	374	} else{
	375	if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
	376	reg = HNS_MAC_HILINK4V2_REG;
c1203fe7	377	else
0d768fc6	378	reg = HNS_MAC_HILINK3V2_REG;
511e6bc0	379	}
0d768fc6 YZZ	380
	381	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
	382	if (dsaf_get_bit(mode, mac_cb->port_mode_off))
	383	phy_if = PHY_INTERFACE_MODE_XGMII;
	384	else
	385	phy_if = PHY_INTERFACE_MODE_SGMII;
	386
511e6bc0	387	return phy_if;
	388	}
	389
f00ef863 KY	390	static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb)
	391	{
	392	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
	393	union acpi_object *obj;
	394	union acpi_object obj_args, argv4;
	395
	396	obj_args.integer.type = ACPI_TYPE_INTEGER;
	397	obj_args.integer.value = mac_cb->mac_id;
	398
	399	argv4.type = ACPI_TYPE_PACKAGE,
	400	argv4.package.count = 1,
	401	argv4.package.elements = &obj_args,
	402
	403	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
	404	hns_dsaf_acpi_dsm_uuid, 0,
	405	HNS_OP_GET_PORT_TYPE_FUNC, &argv4);
	406
	407	if (!obj \|\| obj->type != ACPI_TYPE_INTEGER)
	408	return phy_if;
	409
	410	phy_if = obj->integer.value ?
	411	PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII;
	412
	413	dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if);
	414
	415	ACPI_FREE(obj);
	416
	417	return phy_if;
	418	}
	419
31d4446d YZZ	420	int hns_mac_get_sfp_prsnt(struct hns_mac_cb mac_cb, int sfp_prsnt)
	421	{
	422	if (!mac_cb->cpld_ctrl)
	423	return -ENODEV;
	424
	425	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
	426	+ MAC_SFP_PORT_OFFSET);
	427
	428	return 0;
	429	}
	430
511e6bc0	431	/**
	432	* hns_mac_config_sds_loopback - set loop back for serdes
	433	* @mac_cb: mac control block
	434	* retuen 0 == success
	435	*/
a24274aa	436	static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
511e6bc0	437	{
511e6bc0	438	const u8 lane_id[] = {
	439	0, /* mac 0 -> lane 0 */
	440	1, /* mac 1 -> lane 1 */
	441	2, /* mac 2 -> lane 2 */
	442	3, /* mac 3 -> lane 3 */
	443	2, /* mac 4 -> lane 2 */
	444	3, /* mac 5 -> lane 3 */
	445	0, /* mac 6 -> lane 0 */
	446	1 /* mac 7 -> lane 1 */
	447	};
	448	#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	449	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
	450
	451	int sfp_prsnt;
	452	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
	453
652d39b0	454	if (!mac_cb->phy_dev) {
511e6bc0	455	if (ret)
	456	pr_info("please confirm sfp is present or not\n");
	457	else
	458	if (!sfp_prsnt)
	459	pr_info("no sfp in this eth\n");
	460	}
	461
831d828b	462	if (mac_cb->serdes_ctrl) {
89a6b1aa KY	463	u32 origin;
	464
	465	if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) {
	466	#define HILINK_ACCESS_SEL_CFG 0x40008
	467	/* hilink4 & hilink3 use the same xge training and
	468	* xge u adaptor. There is a hilink access sel cfg
	469	* register to select which one to be configed
	470	*/
	471	if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
	472	(mac_cb->mac_id <= 3))
	473	dsaf_write_syscon(mac_cb->serdes_ctrl,
	474	HILINK_ACCESS_SEL_CFG, 0);
	475	else
	476	dsaf_write_syscon(mac_cb->serdes_ctrl,
	477	HILINK_ACCESS_SEL_CFG, 3);
	478	}
	479
	480	origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
831d828b	481
a24274aa	482	dsaf_set_field(origin, 1ull << 10, 10, en);
831d828b YZZ	483	dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
831d828b YZZ	484	} else {
89a6b1aa KY	485	u8 base_addr = (u8 )mac_cb->serdes_vaddr +
89a6b1aa KY	486	(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
a24274aa	487	dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
831d828b	488	}
511e6bc0	489
	490	return 0;
	491	}
a24274aa	492
f00ef863 KY	493	static int
	494	hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en)
	495	{
	496	union acpi_object *obj;
	497	union acpi_object obj_args[3], argv4;
	498
	499	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	500	obj_args[0].integer.value = mac_cb->mac_id;
	501	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	502	obj_args[1].integer.value = !!en;
	503
	504	argv4.type = ACPI_TYPE_PACKAGE;
	505	argv4.package.count = 2;
	506	argv4.package.elements = obj_args;
	507
	508	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev),
	509	hns_dsaf_acpi_dsm_uuid, 0,
	510	HNS_OP_SERDES_LP_FUNC, &argv4);
	511	if (!obj) {
	512	dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!",
	513	mac_cb->mac_id);
	514
	515	return -ENOTSUPP;
	516	}
	517
	518	ACPI_FREE(obj);
	519
	520	return 0;
	521	}
	522
a24274aa KY	523	struct dsaf_misc_op hns_misc_op_get(struct dsaf_device dsaf_dev)
	524	{
	525	struct dsaf_misc_op *misc_op;
	526
	527	misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL);
	528	if (!misc_op)
	529	return NULL;
	530
8413b3be KY	531	if (dev_of_node(dsaf_dev->dev)) {
	532	misc_op->cpld_set_led = hns_cpld_set_led;
	533	misc_op->cpld_reset_led = cpld_led_reset;
	534	misc_op->cpld_set_led_id = cpld_set_led_id;
	535
	536	misc_op->dsaf_reset = hns_dsaf_rst;
	537	misc_op->xge_srst = hns_dsaf_xge_srst_by_port;
	538	misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port;
	539	misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
	540	misc_op->ppe_srst = hns_ppe_srst_by_port;
	541	misc_op->ppe_comm_srst = hns_ppe_com_srst;
	542
	543	misc_op->get_phy_if = hns_mac_get_phy_if;
	544	misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
	545
	546	misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback;
f00ef863 KY	547	} else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
	548	misc_op->cpld_set_led = hns_cpld_set_led;
	549	misc_op->cpld_reset_led = cpld_led_reset;
	550	misc_op->cpld_set_led_id = cpld_set_led_id;
	551
	552	misc_op->dsaf_reset = hns_dsaf_rst_acpi;
	553	misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi;
	554	misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi;
	555	misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
	556	misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
	557	misc_op->ppe_comm_srst = hns_ppe_com_srst;
	558
	559	misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
	560	misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
	561
	562	misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi;
	563	} else {
	564	devm_kfree(dsaf_dev->dev, (void *)misc_op);
	565	misc_op = NULL;
8413b3be	566	}
a24274aa KY	567
	568	return (void *)misc_op;
	569	}