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511e6bc0 | 1 | /* |
2 | * Copyright (c) 2014-2015 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
511e6bc0 | 10 | #include "hns_dsaf_mac.h" |
2e2591b1 | 11 | #include "hns_dsaf_misc.h" |
511e6bc0 | 12 | #include "hns_dsaf_ppe.h" |
2e2591b1 | 13 | #include "hns_dsaf_reg.h" |
511e6bc0 | 14 | |
f00ef863 KY |
15 | enum _dsm_op_index { |
16 | HNS_OP_RESET_FUNC = 0x1, | |
17 | HNS_OP_SERDES_LP_FUNC = 0x2, | |
18 | HNS_OP_LED_SET_FUNC = 0x3, | |
19 | HNS_OP_GET_PORT_TYPE_FUNC = 0x4, | |
20 | HNS_OP_GET_SFP_STAT_FUNC = 0x5, | |
21 | }; | |
22 | ||
23 | enum _dsm_rst_type { | |
24 | HNS_DSAF_RESET_FUNC = 0x1, | |
25 | HNS_PPE_RESET_FUNC = 0x2, | |
26 | HNS_XGE_CORE_RESET_FUNC = 0x3, | |
27 | HNS_XGE_RESET_FUNC = 0x4, | |
28 | HNS_GE_RESET_FUNC = 0x5, | |
29 | }; | |
30 | ||
31 | const u8 hns_dsaf_acpi_dsm_uuid[] = { | |
32 | 0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41, | |
33 | 0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A | |
34 | }; | |
35 | ||
831d828b YZZ |
36 | static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val) |
37 | { | |
38 | if (dsaf_dev->sub_ctrl) | |
39 | dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val); | |
40 | else | |
41 | dsaf_write_reg(dsaf_dev->sc_base, reg, val); | |
42 | } | |
43 | ||
44 | static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg) | |
45 | { | |
46 | u32 ret; | |
47 | ||
48 | if (dsaf_dev->sub_ctrl) | |
49 | ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg); | |
50 | else | |
51 | ret = dsaf_read_reg(dsaf_dev->sc_base, reg); | |
52 | ||
53 | return ret; | |
54 | } | |
55 | ||
a24274aa KY |
56 | static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status, |
57 | u16 speed, int data) | |
511e6bc0 | 58 | { |
59 | int speed_reg = 0; | |
60 | u8 value; | |
61 | ||
62 | if (!mac_cb) { | |
63 | pr_err("sfp_led_opt mac_dev is null!\n"); | |
64 | return; | |
65 | } | |
31d4446d YZZ |
66 | if (!mac_cb->cpld_ctrl) { |
67 | dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n", | |
511e6bc0 | 68 | mac_cb->mac_id); |
69 | return; | |
70 | } | |
71 | ||
72 | if (speed == MAC_SPEED_10000) | |
73 | speed_reg = 1; | |
74 | ||
75 | value = mac_cb->cpld_led_value; | |
76 | ||
77 | if (link_status) { | |
78 | dsaf_set_bit(value, DSAF_LED_LINK_B, link_status); | |
79 | dsaf_set_field(value, DSAF_LED_SPEED_M, | |
80 | DSAF_LED_SPEED_S, speed_reg); | |
81 | dsaf_set_bit(value, DSAF_LED_DATA_B, data); | |
82 | ||
83 | if (value != mac_cb->cpld_led_value) { | |
31d4446d YZZ |
84 | dsaf_write_syscon(mac_cb->cpld_ctrl, |
85 | mac_cb->cpld_ctrl_reg, value); | |
511e6bc0 | 86 | mac_cb->cpld_led_value = value; |
87 | } | |
88 | } else { | |
d8a8371e DH |
89 | value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B); |
90 | dsaf_write_syscon(mac_cb->cpld_ctrl, | |
91 | mac_cb->cpld_ctrl_reg, value); | |
92 | mac_cb->cpld_led_value = value; | |
511e6bc0 | 93 | } |
94 | } | |
95 | ||
a24274aa | 96 | static void cpld_led_reset(struct hns_mac_cb *mac_cb) |
511e6bc0 | 97 | { |
31d4446d | 98 | if (!mac_cb || !mac_cb->cpld_ctrl) |
511e6bc0 | 99 | return; |
100 | ||
31d4446d YZZ |
101 | dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg, |
102 | CPLD_LED_DEFAULT_VALUE); | |
511e6bc0 | 103 | mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE; |
104 | } | |
105 | ||
a24274aa KY |
106 | static int cpld_set_led_id(struct hns_mac_cb *mac_cb, |
107 | enum hnae_led_state status) | |
511e6bc0 | 108 | { |
109 | switch (status) { | |
110 | case HNAE_LED_ACTIVE: | |
31d4446d YZZ |
111 | mac_cb->cpld_led_value = |
112 | dsaf_read_syscon(mac_cb->cpld_ctrl, | |
113 | mac_cb->cpld_ctrl_reg); | |
511e6bc0 | 114 | dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B, |
115 | CPLD_LED_ON_VALUE); | |
31d4446d YZZ |
116 | dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg, |
117 | mac_cb->cpld_led_value); | |
d8a8371e | 118 | break; |
511e6bc0 | 119 | case HNAE_LED_INACTIVE: |
120 | dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B, | |
121 | CPLD_LED_DEFAULT_VALUE); | |
31d4446d YZZ |
122 | dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg, |
123 | mac_cb->cpld_led_value); | |
511e6bc0 | 124 | break; |
125 | default: | |
d8a8371e DH |
126 | dev_err(mac_cb->dev, "invalid led state: %d!", status); |
127 | return -EINVAL; | |
511e6bc0 | 128 | } |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | #define RESET_REQ_OR_DREQ 1 | |
134 | ||
f00ef863 KY |
135 | static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type, |
136 | u32 port_type, u32 port, u32 val) | |
137 | { | |
138 | union acpi_object *obj; | |
139 | union acpi_object obj_args[3], argv4; | |
140 | ||
141 | obj_args[0].integer.type = ACPI_TYPE_INTEGER; | |
142 | obj_args[0].integer.value = port_type; | |
143 | obj_args[1].integer.type = ACPI_TYPE_INTEGER; | |
144 | obj_args[1].integer.value = port; | |
145 | obj_args[2].integer.type = ACPI_TYPE_INTEGER; | |
146 | obj_args[2].integer.value = val; | |
147 | ||
148 | argv4.type = ACPI_TYPE_PACKAGE; | |
149 | argv4.package.count = 3; | |
150 | argv4.package.elements = obj_args; | |
151 | ||
152 | obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev), | |
153 | hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4); | |
154 | if (!obj) { | |
155 | dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!", | |
156 | port_type, port); | |
157 | return; | |
158 | } | |
159 | ||
160 | ACPI_FREE(obj); | |
161 | } | |
162 | ||
a24274aa | 163 | static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset) |
511e6bc0 | 164 | { |
165 | u32 xbar_reg_addr; | |
166 | u32 nt_reg_addr; | |
167 | ||
a24274aa | 168 | if (!dereset) { |
511e6bc0 | 169 | xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG; |
170 | nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG; | |
171 | } else { | |
172 | xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG; | |
173 | nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG; | |
174 | } | |
175 | ||
831d828b YZZ |
176 | dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ); |
177 | dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ); | |
511e6bc0 | 178 | } |
179 | ||
f00ef863 KY |
180 | static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset) |
181 | { | |
182 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
183 | HNS_DSAF_RESET_FUNC, | |
184 | 0, dereset); | |
185 | } | |
186 | ||
a24274aa KY |
187 | static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, |
188 | bool dereset) | |
511e6bc0 | 189 | { |
190 | u32 reg_val = 0; | |
191 | u32 reg_addr; | |
192 | ||
193 | if (port >= DSAF_XGE_NUM) | |
194 | return; | |
195 | ||
196 | reg_val |= RESET_REQ_OR_DREQ; | |
850bfa3b | 197 | reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off; |
511e6bc0 | 198 | |
a24274aa | 199 | if (!dereset) |
511e6bc0 | 200 | reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG; |
201 | else | |
202 | reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG; | |
203 | ||
831d828b | 204 | dsaf_write_sub(dsaf_dev, reg_addr, reg_val); |
511e6bc0 | 205 | } |
206 | ||
f00ef863 KY |
207 | static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev, |
208 | u32 port, bool dereset) | |
209 | { | |
210 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
211 | HNS_XGE_RESET_FUNC, port, dereset); | |
212 | } | |
213 | ||
a24274aa KY |
214 | static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev, |
215 | u32 port, bool dereset) | |
511e6bc0 | 216 | { |
217 | u32 reg_val = 0; | |
218 | u32 reg_addr; | |
219 | ||
220 | if (port >= DSAF_XGE_NUM) | |
221 | return; | |
222 | ||
850bfa3b YZZ |
223 | reg_val |= XGMAC_TRX_CORE_SRST_M |
224 | << dsaf_dev->mac_cb[port]->port_rst_off; | |
511e6bc0 | 225 | |
a24274aa | 226 | if (!dereset) |
511e6bc0 | 227 | reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG; |
228 | else | |
229 | reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG; | |
230 | ||
831d828b | 231 | dsaf_write_sub(dsaf_dev, reg_addr, reg_val); |
511e6bc0 | 232 | } |
233 | ||
f00ef863 KY |
234 | static void |
235 | hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev, | |
236 | u32 port, bool dereset) | |
237 | { | |
238 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
239 | HNS_XGE_CORE_RESET_FUNC, port, dereset); | |
240 | } | |
241 | ||
a24274aa KY |
242 | static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, |
243 | bool dereset) | |
511e6bc0 | 244 | { |
245 | u32 reg_val_1; | |
246 | u32 reg_val_2; | |
850bfa3b | 247 | u32 port_rst_off; |
511e6bc0 | 248 | |
249 | if (port >= DSAF_GE_NUM) | |
250 | return; | |
251 | ||
89a44093 | 252 | if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { |
511e6bc0 | 253 | reg_val_1 = 0x1 << port; |
850bfa3b | 254 | port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off; |
13ac695e S |
255 | /* there is difference between V1 and V2 in register.*/ |
256 | if (AE_IS_VER1(dsaf_dev->dsaf_ver)) | |
850bfa3b | 257 | reg_val_2 = 0x1041041 << port_rst_off; |
13ac695e | 258 | else |
850bfa3b | 259 | reg_val_2 = 0x2082082 << port_rst_off; |
511e6bc0 | 260 | |
a24274aa | 261 | if (!dereset) { |
831d828b | 262 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG, |
511e6bc0 | 263 | reg_val_1); |
264 | ||
831d828b | 265 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG, |
511e6bc0 | 266 | reg_val_2); |
267 | } else { | |
831d828b | 268 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG, |
511e6bc0 | 269 | reg_val_2); |
270 | ||
831d828b | 271 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG, |
511e6bc0 | 272 | reg_val_1); |
273 | } | |
274 | } else { | |
422c3107 | 275 | reg_val_1 = 0x15540 << dsaf_dev->reset_offset; |
0b03fd85 QX |
276 | |
277 | if (AE_IS_VER1(dsaf_dev->dsaf_ver)) | |
278 | reg_val_2 = 0x100 << dsaf_dev->reset_offset; | |
279 | else | |
280 | reg_val_2 = 0x40 << dsaf_dev->reset_offset; | |
511e6bc0 | 281 | |
a24274aa | 282 | if (!dereset) { |
831d828b | 283 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG, |
511e6bc0 | 284 | reg_val_1); |
285 | ||
831d828b | 286 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG, |
511e6bc0 | 287 | reg_val_2); |
288 | } else { | |
831d828b | 289 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG, |
511e6bc0 | 290 | reg_val_1); |
291 | ||
831d828b | 292 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG, |
511e6bc0 | 293 | reg_val_2); |
294 | } | |
295 | } | |
296 | } | |
297 | ||
f00ef863 KY |
298 | static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev, |
299 | u32 port, bool dereset) | |
300 | { | |
301 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
302 | HNS_GE_RESET_FUNC, port, dereset); | |
303 | } | |
304 | ||
a24274aa KY |
305 | static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, |
306 | bool dereset) | |
511e6bc0 | 307 | { |
308 | u32 reg_val = 0; | |
309 | u32 reg_addr; | |
310 | ||
850bfa3b | 311 | reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off; |
511e6bc0 | 312 | |
a24274aa | 313 | if (!dereset) |
511e6bc0 | 314 | reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG; |
315 | else | |
316 | reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG; | |
317 | ||
831d828b | 318 | dsaf_write_sub(dsaf_dev, reg_addr, reg_val); |
511e6bc0 | 319 | } |
320 | ||
f00ef863 KY |
321 | static void |
322 | hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset) | |
323 | { | |
324 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
325 | HNS_PPE_RESET_FUNC, port, dereset); | |
326 | } | |
327 | ||
a24274aa | 328 | static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset) |
511e6bc0 | 329 | { |
511e6bc0 | 330 | u32 reg_val; |
331 | u32 reg_addr; | |
332 | ||
f00ef863 KY |
333 | if (!(dev_of_node(dsaf_dev->dev))) |
334 | return; | |
335 | ||
89a44093 | 336 | if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { |
511e6bc0 | 337 | reg_val = RESET_REQ_OR_DREQ; |
a24274aa | 338 | if (!dereset) |
511e6bc0 | 339 | reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG; |
340 | else | |
341 | reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG; | |
342 | ||
343 | } else { | |
422c3107 | 344 | reg_val = 0x100 << dsaf_dev->reset_offset; |
511e6bc0 | 345 | |
a24274aa | 346 | if (!dereset) |
511e6bc0 | 347 | reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG; |
348 | else | |
349 | reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG; | |
350 | } | |
351 | ||
831d828b | 352 | dsaf_write_sub(dsaf_dev, reg_addr, reg_val); |
511e6bc0 | 353 | } |
354 | ||
355 | /** | |
356 | * hns_mac_get_sds_mode - get phy ifterface form serdes mode | |
357 | * @mac_cb: mac control block | |
358 | * retuen phy interface | |
359 | */ | |
a24274aa | 360 | static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb) |
511e6bc0 | 361 | { |
c1203fe7 SL |
362 | u32 mode; |
363 | u32 reg; | |
c1203fe7 | 364 | bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver); |
c1203fe7 | 365 | int mac_id = mac_cb->mac_id; |
0d768fc6 | 366 | phy_interface_t phy_if; |
511e6bc0 | 367 | |
0d768fc6 YZZ |
368 | if (is_ver1) { |
369 | if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) | |
370 | return PHY_INTERFACE_MODE_SGMII; | |
371 | ||
372 | if (mac_id >= 0 && mac_id <= 3) | |
373 | reg = HNS_MAC_HILINK4_REG; | |
511e6bc0 | 374 | else |
0d768fc6 YZZ |
375 | reg = HNS_MAC_HILINK3_REG; |
376 | } else{ | |
377 | if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3) | |
378 | reg = HNS_MAC_HILINK4V2_REG; | |
c1203fe7 | 379 | else |
0d768fc6 | 380 | reg = HNS_MAC_HILINK3V2_REG; |
511e6bc0 | 381 | } |
0d768fc6 YZZ |
382 | |
383 | mode = dsaf_read_sub(mac_cb->dsaf_dev, reg); | |
384 | if (dsaf_get_bit(mode, mac_cb->port_mode_off)) | |
385 | phy_if = PHY_INTERFACE_MODE_XGMII; | |
386 | else | |
387 | phy_if = PHY_INTERFACE_MODE_SGMII; | |
388 | ||
511e6bc0 | 389 | return phy_if; |
390 | } | |
391 | ||
f00ef863 KY |
392 | static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb) |
393 | { | |
394 | phy_interface_t phy_if = PHY_INTERFACE_MODE_NA; | |
395 | union acpi_object *obj; | |
396 | union acpi_object obj_args, argv4; | |
397 | ||
398 | obj_args.integer.type = ACPI_TYPE_INTEGER; | |
399 | obj_args.integer.value = mac_cb->mac_id; | |
400 | ||
401 | argv4.type = ACPI_TYPE_PACKAGE, | |
402 | argv4.package.count = 1, | |
403 | argv4.package.elements = &obj_args, | |
404 | ||
405 | obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev), | |
406 | hns_dsaf_acpi_dsm_uuid, 0, | |
407 | HNS_OP_GET_PORT_TYPE_FUNC, &argv4); | |
408 | ||
409 | if (!obj || obj->type != ACPI_TYPE_INTEGER) | |
410 | return phy_if; | |
411 | ||
412 | phy_if = obj->integer.value ? | |
413 | PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII; | |
414 | ||
415 | dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if); | |
416 | ||
417 | ACPI_FREE(obj); | |
418 | ||
419 | return phy_if; | |
420 | } | |
421 | ||
31d4446d YZZ |
422 | int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt) |
423 | { | |
424 | if (!mac_cb->cpld_ctrl) | |
425 | return -ENODEV; | |
426 | ||
427 | *sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg | |
428 | + MAC_SFP_PORT_OFFSET); | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
511e6bc0 | 433 | /** |
434 | * hns_mac_config_sds_loopback - set loop back for serdes | |
435 | * @mac_cb: mac control block | |
436 | * retuen 0 == success | |
437 | */ | |
a24274aa | 438 | static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en) |
511e6bc0 | 439 | { |
511e6bc0 | 440 | const u8 lane_id[] = { |
441 | 0, /* mac 0 -> lane 0 */ | |
442 | 1, /* mac 1 -> lane 1 */ | |
443 | 2, /* mac 2 -> lane 2 */ | |
444 | 3, /* mac 3 -> lane 3 */ | |
445 | 2, /* mac 4 -> lane 2 */ | |
446 | 3, /* mac 5 -> lane 3 */ | |
447 | 0, /* mac 6 -> lane 0 */ | |
448 | 1 /* mac 7 -> lane 1 */ | |
449 | }; | |
450 | #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2) | |
451 | u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0); | |
452 | ||
453 | int sfp_prsnt; | |
454 | int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt); | |
455 | ||
652d39b0 | 456 | if (!mac_cb->phy_dev) { |
511e6bc0 | 457 | if (ret) |
458 | pr_info("please confirm sfp is present or not\n"); | |
459 | else | |
460 | if (!sfp_prsnt) | |
461 | pr_info("no sfp in this eth\n"); | |
462 | } | |
463 | ||
831d828b | 464 | if (mac_cb->serdes_ctrl) { |
89a6b1aa KY |
465 | u32 origin; |
466 | ||
467 | if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) { | |
468 | #define HILINK_ACCESS_SEL_CFG 0x40008 | |
469 | /* hilink4 & hilink3 use the same xge training and | |
470 | * xge u adaptor. There is a hilink access sel cfg | |
471 | * register to select which one to be configed | |
472 | */ | |
473 | if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) && | |
474 | (mac_cb->mac_id <= 3)) | |
475 | dsaf_write_syscon(mac_cb->serdes_ctrl, | |
476 | HILINK_ACCESS_SEL_CFG, 0); | |
477 | else | |
478 | dsaf_write_syscon(mac_cb->serdes_ctrl, | |
479 | HILINK_ACCESS_SEL_CFG, 3); | |
480 | } | |
481 | ||
482 | origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset); | |
831d828b | 483 | |
a24274aa | 484 | dsaf_set_field(origin, 1ull << 10, 10, en); |
831d828b YZZ |
485 | dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin); |
486 | } else { | |
89a6b1aa KY |
487 | u8 *base_addr = (u8 *)mac_cb->serdes_vaddr + |
488 | (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000); | |
a24274aa | 489 | dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en); |
831d828b | 490 | } |
511e6bc0 | 491 | |
492 | return 0; | |
493 | } | |
a24274aa | 494 | |
f00ef863 KY |
495 | static int |
496 | hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en) | |
497 | { | |
498 | union acpi_object *obj; | |
499 | union acpi_object obj_args[3], argv4; | |
500 | ||
501 | obj_args[0].integer.type = ACPI_TYPE_INTEGER; | |
502 | obj_args[0].integer.value = mac_cb->mac_id; | |
503 | obj_args[1].integer.type = ACPI_TYPE_INTEGER; | |
504 | obj_args[1].integer.value = !!en; | |
505 | ||
506 | argv4.type = ACPI_TYPE_PACKAGE; | |
507 | argv4.package.count = 2; | |
508 | argv4.package.elements = obj_args; | |
509 | ||
510 | obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev), | |
511 | hns_dsaf_acpi_dsm_uuid, 0, | |
512 | HNS_OP_SERDES_LP_FUNC, &argv4); | |
513 | if (!obj) { | |
514 | dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!", | |
515 | mac_cb->mac_id); | |
516 | ||
517 | return -ENOTSUPP; | |
518 | } | |
519 | ||
520 | ACPI_FREE(obj); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
a24274aa KY |
525 | struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev) |
526 | { | |
527 | struct dsaf_misc_op *misc_op; | |
528 | ||
529 | misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL); | |
530 | if (!misc_op) | |
531 | return NULL; | |
532 | ||
8413b3be KY |
533 | if (dev_of_node(dsaf_dev->dev)) { |
534 | misc_op->cpld_set_led = hns_cpld_set_led; | |
535 | misc_op->cpld_reset_led = cpld_led_reset; | |
536 | misc_op->cpld_set_led_id = cpld_set_led_id; | |
537 | ||
538 | misc_op->dsaf_reset = hns_dsaf_rst; | |
539 | misc_op->xge_srst = hns_dsaf_xge_srst_by_port; | |
540 | misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port; | |
541 | misc_op->ge_srst = hns_dsaf_ge_srst_by_port; | |
542 | misc_op->ppe_srst = hns_ppe_srst_by_port; | |
543 | misc_op->ppe_comm_srst = hns_ppe_com_srst; | |
544 | ||
545 | misc_op->get_phy_if = hns_mac_get_phy_if; | |
546 | misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt; | |
547 | ||
548 | misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback; | |
f00ef863 KY |
549 | } else if (is_acpi_node(dsaf_dev->dev->fwnode)) { |
550 | misc_op->cpld_set_led = hns_cpld_set_led; | |
551 | misc_op->cpld_reset_led = cpld_led_reset; | |
552 | misc_op->cpld_set_led_id = cpld_set_led_id; | |
553 | ||
554 | misc_op->dsaf_reset = hns_dsaf_rst_acpi; | |
555 | misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi; | |
556 | misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi; | |
557 | misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi; | |
558 | misc_op->ppe_srst = hns_ppe_srst_by_port_acpi; | |
559 | misc_op->ppe_comm_srst = hns_ppe_com_srst; | |
560 | ||
561 | misc_op->get_phy_if = hns_mac_get_phy_if_acpi; | |
562 | misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt; | |
563 | ||
564 | misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi; | |
565 | } else { | |
566 | devm_kfree(dsaf_dev->dev, (void *)misc_op); | |
567 | misc_op = NULL; | |
8413b3be | 568 | } |
a24274aa KY |
569 | |
570 | return (void *)misc_op; | |
571 | } |