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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
076bb0c8 | 34 | #include <net/busy_poll.h> |
47a38e15 | 35 | #include <linux/bpf.h> |
c27a02cd | 36 | #include <linux/mlx4/cq.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c27a02cd YP |
38 | #include <linux/mlx4/qp.h> |
39 | #include <linux/skbuff.h> | |
b67bfe0d | 40 | #include <linux/rculist.h> |
c27a02cd YP |
41 | #include <linux/if_ether.h> |
42 | #include <linux/if_vlan.h> | |
43 | #include <linux/vmalloc.h> | |
35f6f453 | 44 | #include <linux/irq.h> |
c27a02cd | 45 | |
f8c6455b SM |
46 | #if IS_ENABLED(CONFIG_IPV6) |
47 | #include <net/ip6_checksum.h> | |
48 | #endif | |
49 | ||
c27a02cd YP |
50 | #include "mlx4_en.h" |
51 | ||
51151a16 ED |
52 | static int mlx4_alloc_pages(struct mlx4_en_priv *priv, |
53 | struct mlx4_en_rx_alloc *page_alloc, | |
54 | const struct mlx4_en_frag_info *frag_info, | |
55 | gfp_t _gfp) | |
56 | { | |
57 | int order; | |
58 | struct page *page; | |
59 | dma_addr_t dma; | |
60 | ||
d576acf0 | 61 | for (order = frag_info->order; ;) { |
51151a16 ED |
62 | gfp_t gfp = _gfp; |
63 | ||
64 | if (order) | |
04aeb56a | 65 | gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC; |
51151a16 ED |
66 | page = alloc_pages(gfp, order); |
67 | if (likely(page)) | |
68 | break; | |
69 | if (--order < 0 || | |
70 | ((PAGE_SIZE << order) < frag_info->frag_size)) | |
71 | return -ENOMEM; | |
72 | } | |
73 | dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, | |
d576acf0 | 74 | frag_info->dma_dir); |
51151a16 ED |
75 | if (dma_mapping_error(priv->ddev, dma)) { |
76 | put_page(page); | |
77 | return -ENOMEM; | |
78 | } | |
70fbe079 | 79 | page_alloc->page_size = PAGE_SIZE << order; |
51151a16 ED |
80 | page_alloc->page = page; |
81 | page_alloc->dma = dma; | |
5f6e9800 | 82 | page_alloc->page_offset = 0; |
51151a16 | 83 | /* Not doing get_page() for each frag is a big win |
98226208 | 84 | * on asymetric workloads. Note we can not use atomic_set(). |
51151a16 | 85 | */ |
fe896d18 | 86 | page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1); |
51151a16 ED |
87 | return 0; |
88 | } | |
89 | ||
4cce66cd TLSC |
90 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
91 | struct mlx4_en_rx_desc *rx_desc, | |
92 | struct mlx4_en_rx_alloc *frags, | |
51151a16 ED |
93 | struct mlx4_en_rx_alloc *ring_alloc, |
94 | gfp_t gfp) | |
c27a02cd | 95 | { |
4cce66cd | 96 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
51151a16 | 97 | const struct mlx4_en_frag_info *frag_info; |
c27a02cd YP |
98 | struct page *page; |
99 | dma_addr_t dma; | |
4cce66cd | 100 | int i; |
c27a02cd | 101 | |
4cce66cd TLSC |
102 | for (i = 0; i < priv->num_frags; i++) { |
103 | frag_info = &priv->frag_info[i]; | |
51151a16 | 104 | page_alloc[i] = ring_alloc[i]; |
70fbe079 AV |
105 | page_alloc[i].page_offset += frag_info->frag_stride; |
106 | ||
107 | if (page_alloc[i].page_offset + frag_info->frag_stride <= | |
108 | ring_alloc[i].page_size) | |
51151a16 | 109 | continue; |
70fbe079 | 110 | |
51151a16 ED |
111 | if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) |
112 | goto out; | |
4cce66cd | 113 | } |
c27a02cd | 114 | |
4cce66cd TLSC |
115 | for (i = 0; i < priv->num_frags; i++) { |
116 | frags[i] = ring_alloc[i]; | |
70fbe079 | 117 | dma = ring_alloc[i].dma + ring_alloc[i].page_offset; |
4cce66cd TLSC |
118 | ring_alloc[i] = page_alloc[i]; |
119 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
c27a02cd | 120 | } |
4cce66cd | 121 | |
c27a02cd | 122 | return 0; |
4cce66cd | 123 | |
4cce66cd TLSC |
124 | out: |
125 | while (i--) { | |
51151a16 | 126 | if (page_alloc[i].page != ring_alloc[i].page) { |
4cce66cd | 127 | dma_unmap_page(priv->ddev, page_alloc[i].dma, |
d576acf0 BB |
128 | page_alloc[i].page_size, |
129 | priv->frag_info[i].dma_dir); | |
51151a16 | 130 | page = page_alloc[i].page; |
851b10d6 KK |
131 | /* Revert changes done by mlx4_alloc_pages */ |
132 | page_ref_sub(page, page_alloc[i].page_size / | |
133 | priv->frag_info[i].frag_stride - 1); | |
51151a16 ED |
134 | put_page(page); |
135 | } | |
4cce66cd TLSC |
136 | } |
137 | return -ENOMEM; | |
138 | } | |
139 | ||
140 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
141 | struct mlx4_en_rx_alloc *frags, | |
142 | int i) | |
143 | { | |
51151a16 | 144 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
021f1107 | 145 | u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; |
4cce66cd | 146 | |
021f1107 AV |
147 | |
148 | if (next_frag_end > frags[i].page_size) | |
70fbe079 | 149 | dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, |
d576acf0 | 150 | frag_info->dma_dir); |
51151a16 | 151 | |
4cce66cd TLSC |
152 | if (frags[i].page) |
153 | put_page(frags[i].page); | |
c27a02cd YP |
154 | } |
155 | ||
156 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
157 | struct mlx4_en_rx_ring *ring) | |
158 | { | |
c27a02cd | 159 | int i; |
51151a16 | 160 | struct mlx4_en_rx_alloc *page_alloc; |
c27a02cd YP |
161 | |
162 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 | 163 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
c27a02cd | 164 | |
51151a16 | 165 | if (mlx4_alloc_pages(priv, &ring->page_alloc[i], |
1ab25f86 | 166 | frag_info, GFP_KERNEL | __GFP_COLD)) |
4cce66cd | 167 | goto out; |
b110d2ce IS |
168 | |
169 | en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n", | |
170 | i, ring->page_alloc[i].page_size, | |
fe896d18 | 171 | page_ref_count(ring->page_alloc[i].page)); |
c27a02cd YP |
172 | } |
173 | return 0; | |
174 | ||
175 | out: | |
176 | while (i--) { | |
51151a16 ED |
177 | struct page *page; |
178 | ||
c27a02cd | 179 | page_alloc = &ring->page_alloc[i]; |
4cce66cd | 180 | dma_unmap_page(priv->ddev, page_alloc->dma, |
d576acf0 BB |
181 | page_alloc->page_size, |
182 | priv->frag_info[i].dma_dir); | |
51151a16 | 183 | page = page_alloc->page; |
851b10d6 KK |
184 | /* Revert changes done by mlx4_alloc_pages */ |
185 | page_ref_sub(page, page_alloc->page_size / | |
186 | priv->frag_info[i].frag_stride - 1); | |
51151a16 | 187 | put_page(page); |
c27a02cd YP |
188 | page_alloc->page = NULL; |
189 | } | |
190 | return -ENOMEM; | |
191 | } | |
192 | ||
193 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
194 | struct mlx4_en_rx_ring *ring) | |
195 | { | |
196 | struct mlx4_en_rx_alloc *page_alloc; | |
197 | int i; | |
198 | ||
199 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
200 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
201 | ||
c27a02cd | 202 | page_alloc = &ring->page_alloc[i]; |
453a6082 YP |
203 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
204 | i, page_count(page_alloc->page)); | |
c27a02cd | 205 | |
4cce66cd | 206 | dma_unmap_page(priv->ddev, page_alloc->dma, |
d576acf0 | 207 | page_alloc->page_size, frag_info->dma_dir); |
70fbe079 AV |
208 | while (page_alloc->page_offset + frag_info->frag_stride < |
209 | page_alloc->page_size) { | |
51151a16 | 210 | put_page(page_alloc->page); |
70fbe079 | 211 | page_alloc->page_offset += frag_info->frag_stride; |
51151a16 | 212 | } |
c27a02cd YP |
213 | page_alloc->page = NULL; |
214 | } | |
215 | } | |
216 | ||
c27a02cd YP |
217 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
218 | struct mlx4_en_rx_ring *ring, int index) | |
219 | { | |
220 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
221 | int possible_frags; |
222 | int i; | |
223 | ||
c27a02cd YP |
224 | /* Set size and memtype fields */ |
225 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
226 | rx_desc->data[i].byte_count = |
227 | cpu_to_be32(priv->frag_info[i].frag_size); | |
228 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
229 | } | |
230 | ||
231 | /* If the number of used fragments does not fill up the ring stride, | |
232 | * remaining (unused) fragments must be padded with null address/size | |
233 | * and a special memory key */ | |
234 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
235 | for (i = priv->num_frags; i < possible_frags; i++) { | |
236 | rx_desc->data[i].byte_count = 0; | |
237 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
238 | rx_desc->data[i].addr = 0; | |
239 | } | |
240 | } | |
241 | ||
c27a02cd | 242 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
51151a16 ED |
243 | struct mlx4_en_rx_ring *ring, int index, |
244 | gfp_t gfp) | |
c27a02cd YP |
245 | { |
246 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
247 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
248 | (index << priv->log_rx_info); | |
c27a02cd | 249 | |
d576acf0 BB |
250 | if (ring->page_cache.index > 0) { |
251 | frags[0] = ring->page_cache.buf[--ring->page_cache.index]; | |
252 | rx_desc->data[0].addr = cpu_to_be64(frags[0].dma); | |
253 | return 0; | |
254 | } | |
255 | ||
51151a16 | 256 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); |
c27a02cd YP |
257 | } |
258 | ||
07841f9d IS |
259 | static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring) |
260 | { | |
07841f9d IS |
261 | return ring->prod == ring->cons; |
262 | } | |
263 | ||
c27a02cd YP |
264 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) |
265 | { | |
266 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
267 | } | |
268 | ||
38aab07c YP |
269 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
270 | struct mlx4_en_rx_ring *ring, | |
271 | int index) | |
272 | { | |
4cce66cd | 273 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
274 | int nr; |
275 | ||
4cce66cd | 276 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 277 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 278 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 279 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
280 | } |
281 | } | |
282 | ||
c27a02cd YP |
283 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
284 | { | |
c27a02cd YP |
285 | struct mlx4_en_rx_ring *ring; |
286 | int ring_ind; | |
287 | int buf_ind; | |
38aab07c | 288 | int new_size; |
c27a02cd YP |
289 | |
290 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
291 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 292 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
293 | |
294 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
51151a16 | 295 | ring->actual_size, |
1ab25f86 | 296 | GFP_KERNEL | __GFP_COLD)) { |
c27a02cd | 297 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { |
1a91de28 | 298 | en_err(priv, "Failed to allocate enough rx buffers\n"); |
c27a02cd YP |
299 | return -ENOMEM; |
300 | } else { | |
38aab07c | 301 | new_size = rounddown_pow_of_two(ring->actual_size); |
1a91de28 | 302 | en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", |
453a6082 | 303 | ring->actual_size, new_size); |
38aab07c | 304 | goto reduce_rings; |
c27a02cd YP |
305 | } |
306 | } | |
307 | ring->actual_size++; | |
308 | ring->prod++; | |
309 | } | |
310 | } | |
38aab07c YP |
311 | return 0; |
312 | ||
313 | reduce_rings: | |
314 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 315 | ring = priv->rx_ring[ring_ind]; |
38aab07c YP |
316 | while (ring->actual_size > new_size) { |
317 | ring->actual_size--; | |
318 | ring->prod--; | |
319 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
320 | } | |
38aab07c YP |
321 | } |
322 | ||
c27a02cd YP |
323 | return 0; |
324 | } | |
325 | ||
c27a02cd YP |
326 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
327 | struct mlx4_en_rx_ring *ring) | |
328 | { | |
c27a02cd | 329 | int index; |
c27a02cd | 330 | |
453a6082 YP |
331 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
332 | ring->cons, ring->prod); | |
c27a02cd YP |
333 | |
334 | /* Unmap and free Rx buffers */ | |
07841f9d | 335 | while (!mlx4_en_is_ring_empty(ring)) { |
c27a02cd | 336 | index = ring->cons & ring->size_mask; |
453a6082 | 337 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 338 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
339 | ++ring->cons; |
340 | } | |
341 | } | |
342 | ||
02512482 IS |
343 | void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) |
344 | { | |
345 | int i; | |
346 | int num_of_eqs; | |
bb2146bc | 347 | int num_rx_rings; |
02512482 IS |
348 | struct mlx4_dev *dev = mdev->dev; |
349 | ||
350 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
c66fa19c MB |
351 | num_of_eqs = max_t(int, MIN_RX_RINGS, |
352 | min_t(int, | |
353 | mlx4_get_eqs_per_port(mdev->dev, i), | |
354 | DEF_RX_RINGS)); | |
02512482 | 355 | |
ea1c1af1 AV |
356 | num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : |
357 | min_t(int, num_of_eqs, | |
358 | netif_get_num_default_rss_queues()); | |
02512482 | 359 | mdev->profile.prof[i].rx_ring_num = |
bb2146bc | 360 | rounddown_pow_of_two(num_rx_rings); |
02512482 IS |
361 | } |
362 | } | |
363 | ||
c27a02cd | 364 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 365 | struct mlx4_en_rx_ring **pring, |
163561a4 | 366 | u32 size, u16 stride, int node) |
c27a02cd YP |
367 | { |
368 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 369 | struct mlx4_en_rx_ring *ring; |
4cce66cd | 370 | int err = -ENOMEM; |
c27a02cd YP |
371 | int tmp; |
372 | ||
163561a4 | 373 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 374 | if (!ring) { |
163561a4 EE |
375 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
376 | if (!ring) { | |
377 | en_err(priv, "Failed to allocate RX ring structure\n"); | |
378 | return -ENOMEM; | |
379 | } | |
41d942d5 EE |
380 | } |
381 | ||
c27a02cd YP |
382 | ring->prod = 0; |
383 | ring->cons = 0; | |
384 | ring->size = size; | |
385 | ring->size_mask = size - 1; | |
386 | ring->stride = stride; | |
387 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 388 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
389 | |
390 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 391 | sizeof(struct mlx4_en_rx_alloc)); |
163561a4 | 392 | ring->rx_info = vmalloc_node(tmp, node); |
41d942d5 | 393 | if (!ring->rx_info) { |
163561a4 EE |
394 | ring->rx_info = vmalloc(tmp); |
395 | if (!ring->rx_info) { | |
396 | err = -ENOMEM; | |
397 | goto err_ring; | |
398 | } | |
41d942d5 | 399 | } |
e404decb | 400 | |
453a6082 | 401 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
402 | ring->rx_info, tmp); |
403 | ||
163561a4 | 404 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 405 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
73898db0 | 406 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); |
872bf2fb | 407 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 408 | if (err) |
41d942d5 | 409 | goto err_info; |
c27a02cd | 410 | |
c27a02cd YP |
411 | ring->buf = ring->wqres.buf.direct.buf; |
412 | ||
ec693d47 AV |
413 | ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; |
414 | ||
41d942d5 | 415 | *pring = ring; |
c27a02cd YP |
416 | return 0; |
417 | ||
41d942d5 | 418 | err_info: |
c27a02cd YP |
419 | vfree(ring->rx_info); |
420 | ring->rx_info = NULL; | |
41d942d5 EE |
421 | err_ring: |
422 | kfree(ring); | |
423 | *pring = NULL; | |
424 | ||
c27a02cd YP |
425 | return err; |
426 | } | |
427 | ||
428 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
429 | { | |
c27a02cd YP |
430 | struct mlx4_en_rx_ring *ring; |
431 | int i; | |
432 | int ring_ind; | |
433 | int err; | |
434 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
435 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
436 | |
437 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 438 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
439 | |
440 | ring->prod = 0; | |
441 | ring->cons = 0; | |
442 | ring->actual_size = 0; | |
41d942d5 | 443 | ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; |
c27a02cd YP |
444 | |
445 | ring->stride = stride; | |
9f519f68 YP |
446 | if (ring->stride <= TXBB_SIZE) |
447 | ring->buf += TXBB_SIZE; | |
448 | ||
c27a02cd YP |
449 | ring->log_stride = ffs(ring->stride) - 1; |
450 | ring->buf_size = ring->size * ring->stride; | |
451 | ||
452 | memset(ring->buf, 0, ring->buf_size); | |
453 | mlx4_en_update_rx_prod_db(ring); | |
454 | ||
4cce66cd | 455 | /* Initialize all descriptors */ |
c27a02cd YP |
456 | for (i = 0; i < ring->size; i++) |
457 | mlx4_en_init_rx_desc(priv, ring, i); | |
458 | ||
459 | /* Initialize page allocators */ | |
460 | err = mlx4_en_init_allocator(priv, ring); | |
461 | if (err) { | |
453a6082 | 462 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
463 | if (ring->stride <= TXBB_SIZE) |
464 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
465 | ring_ind--; |
466 | goto err_allocator; | |
c27a02cd | 467 | } |
c27a02cd | 468 | } |
b58515be IM |
469 | err = mlx4_en_fill_rx_buffers(priv); |
470 | if (err) | |
c27a02cd YP |
471 | goto err_buffers; |
472 | ||
473 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 474 | ring = priv->rx_ring[ring_ind]; |
c27a02cd | 475 | |
00d7d7bc | 476 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 477 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
478 | } |
479 | ||
480 | return 0; | |
481 | ||
c27a02cd YP |
482 | err_buffers: |
483 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
41d942d5 | 484 | mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); |
c27a02cd YP |
485 | |
486 | ring_ind = priv->rx_ring_num - 1; | |
487 | err_allocator: | |
488 | while (ring_ind >= 0) { | |
41d942d5 EE |
489 | if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) |
490 | priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; | |
491 | mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); | |
c27a02cd YP |
492 | ring_ind--; |
493 | } | |
494 | return err; | |
495 | } | |
496 | ||
07841f9d IS |
497 | /* We recover from out of memory by scheduling our napi poll |
498 | * function (mlx4_en_process_cq), which tries to allocate | |
499 | * all missing RX buffers (call to mlx4_en_refill_rx_buffers). | |
500 | */ | |
501 | void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv) | |
502 | { | |
503 | int ring; | |
504 | ||
505 | if (!priv->port_up) | |
506 | return; | |
507 | ||
508 | for (ring = 0; ring < priv->rx_ring_num; ring++) { | |
509 | if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) | |
510 | napi_reschedule(&priv->rx_cq[ring]->napi); | |
511 | } | |
512 | } | |
513 | ||
d576acf0 BB |
514 | /* When the rx ring is running in page-per-packet mode, a released frame can go |
515 | * directly into a small cache, to avoid unmapping or touching the page | |
516 | * allocator. In bpf prog performance scenarios, buffers are either forwarded | |
517 | * or dropped, never converted to skbs, so every page can come directly from | |
518 | * this cache when it is sized to be a multiple of the napi budget. | |
519 | */ | |
520 | bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, | |
521 | struct mlx4_en_rx_alloc *frame) | |
522 | { | |
523 | struct mlx4_en_page_cache *cache = &ring->page_cache; | |
524 | ||
525 | if (cache->index >= MLX4_EN_CACHE_SIZE) | |
526 | return false; | |
527 | ||
528 | cache->buf[cache->index++] = *frame; | |
529 | return true; | |
530 | } | |
531 | ||
c27a02cd | 532 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 EE |
533 | struct mlx4_en_rx_ring **pring, |
534 | u32 size, u16 stride) | |
c27a02cd YP |
535 | { |
536 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 537 | struct mlx4_en_rx_ring *ring = *pring; |
c27a02cd | 538 | |
47a38e15 BB |
539 | if (ring->xdp_prog) |
540 | bpf_prog_put(ring->xdp_prog); | |
68355f71 | 541 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
542 | vfree(ring->rx_info); |
543 | ring->rx_info = NULL; | |
41d942d5 EE |
544 | kfree(ring); |
545 | *pring = NULL; | |
1eb8c695 | 546 | #ifdef CONFIG_RFS_ACCEL |
41d942d5 | 547 | mlx4_en_cleanup_filters(priv); |
1eb8c695 | 548 | #endif |
c27a02cd YP |
549 | } |
550 | ||
551 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
552 | struct mlx4_en_rx_ring *ring) | |
553 | { | |
d576acf0 BB |
554 | int i; |
555 | ||
556 | for (i = 0; i < ring->page_cache.index; i++) { | |
557 | struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i]; | |
558 | ||
559 | dma_unmap_page(priv->ddev, frame->dma, frame->page_size, | |
560 | priv->frag_info[0].dma_dir); | |
561 | put_page(frame->page); | |
562 | } | |
563 | ring->page_cache.index = 0; | |
c27a02cd | 564 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
565 | if (ring->stride <= TXBB_SIZE) |
566 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
567 | mlx4_en_destroy_allocator(priv, ring); |
568 | } | |
569 | ||
570 | ||
c27a02cd YP |
571 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
572 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 573 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 574 | struct sk_buff *skb, |
c27a02cd YP |
575 | int length) |
576 | { | |
90278c9f | 577 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
578 | struct mlx4_en_frag_info *frag_info; |
579 | int nr; | |
580 | dma_addr_t dma; | |
581 | ||
4cce66cd | 582 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
583 | for (nr = 0; nr < priv->num_frags; nr++) { |
584 | frag_info = &priv->frag_info[nr]; | |
585 | if (length <= frag_info->frag_prefix_size) | |
586 | break; | |
4cce66cd TLSC |
587 | if (!frags[nr].page) |
588 | goto fail; | |
c27a02cd | 589 | |
c27a02cd | 590 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
591 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
592 | DMA_FROM_DEVICE); | |
c27a02cd | 593 | |
4cce66cd | 594 | /* Save page reference in skb */ |
4cce66cd TLSC |
595 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); |
596 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
70fbe079 | 597 | skb_frags_rx[nr].page_offset = frags[nr].page_offset; |
4cce66cd | 598 | skb->truesize += frag_info->frag_stride; |
51151a16 | 599 | frags[nr].page = NULL; |
c27a02cd YP |
600 | } |
601 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 602 | if (nr > 0) |
9e903e08 ED |
603 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
604 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
605 | return nr; |
606 | ||
607 | fail: | |
c27a02cd YP |
608 | while (nr > 0) { |
609 | nr--; | |
311761c8 | 610 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
611 | } |
612 | return 0; | |
613 | } | |
614 | ||
615 | ||
616 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
617 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 618 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
619 | unsigned int length) |
620 | { | |
c27a02cd YP |
621 | struct sk_buff *skb; |
622 | void *va; | |
623 | int used_frags; | |
624 | dma_addr_t dma; | |
625 | ||
c056b734 | 626 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
c27a02cd | 627 | if (!skb) { |
453a6082 | 628 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
629 | return NULL; |
630 | } | |
c27a02cd YP |
631 | skb_reserve(skb, NET_IP_ALIGN); |
632 | skb->len = length; | |
c27a02cd YP |
633 | |
634 | /* Get pointer to first fragment so we could copy the headers into the | |
635 | * (linear part of the) skb */ | |
70fbe079 | 636 | va = page_address(frags[0].page) + frags[0].page_offset; |
c27a02cd YP |
637 | |
638 | if (length <= SMALL_PACKET_SIZE) { | |
639 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 640 | * sync buffers for the copy */ |
c27a02cd | 641 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 642 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 643 | DMA_FROM_DEVICE); |
c27a02cd | 644 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
645 | skb->tail += length; |
646 | } else { | |
cfecec56 ED |
647 | unsigned int pull_len; |
648 | ||
c27a02cd | 649 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
650 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
651 | skb, length); | |
785a0982 YP |
652 | if (unlikely(!used_frags)) { |
653 | kfree_skb(skb); | |
654 | return NULL; | |
655 | } | |
c27a02cd YP |
656 | skb_shinfo(skb)->nr_frags = used_frags; |
657 | ||
cfecec56 | 658 | pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE); |
c27a02cd | 659 | /* Copy headers into the skb linear buffer */ |
cfecec56 ED |
660 | memcpy(skb->data, va, pull_len); |
661 | skb->tail += pull_len; | |
c27a02cd YP |
662 | |
663 | /* Skip headers in first fragment */ | |
cfecec56 | 664 | skb_shinfo(skb)->frags[0].page_offset += pull_len; |
c27a02cd YP |
665 | |
666 | /* Adjust size of first fragment */ | |
cfecec56 ED |
667 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len); |
668 | skb->data_len = length - pull_len; | |
c27a02cd YP |
669 | } |
670 | return skb; | |
671 | } | |
672 | ||
e7c1c2c4 YP |
673 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
674 | { | |
675 | int i; | |
676 | int offset = ETH_HLEN; | |
677 | ||
678 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
679 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
680 | goto out_loopback; | |
681 | } | |
682 | /* Loopback found */ | |
683 | priv->loopback_ok = 1; | |
684 | ||
685 | out_loopback: | |
686 | dev_kfree_skb_any(skb); | |
687 | } | |
c27a02cd | 688 | |
4cce66cd TLSC |
689 | static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
690 | struct mlx4_en_rx_ring *ring) | |
691 | { | |
692 | int index = ring->prod & ring->size_mask; | |
693 | ||
694 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
1ab25f86 IS |
695 | if (mlx4_en_prepare_rx_desc(priv, ring, index, |
696 | GFP_ATOMIC | __GFP_COLD)) | |
4cce66cd TLSC |
697 | break; |
698 | ring->prod++; | |
699 | index = ring->prod & ring->size_mask; | |
700 | } | |
701 | } | |
702 | ||
f8c6455b SM |
703 | /* When hardware doesn't strip the vlan, we need to calculate the checksum |
704 | * over it and add it to the hardware's checksum calculation | |
705 | */ | |
706 | static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum, | |
707 | struct vlan_hdr *vlanh) | |
708 | { | |
709 | return csum_add(hw_checksum, *(__wsum *)vlanh); | |
710 | } | |
711 | ||
712 | /* Although the stack expects checksum which doesn't include the pseudo | |
713 | * header, the HW adds it. To address that, we are subtracting the pseudo | |
714 | * header checksum from the checksum value provided by the HW. | |
715 | */ | |
716 | static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb, | |
717 | struct iphdr *iph) | |
718 | { | |
719 | __u16 length_for_csum = 0; | |
720 | __wsum csum_pseudo_header = 0; | |
721 | ||
722 | length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2)); | |
723 | csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr, | |
724 | length_for_csum, iph->protocol, 0); | |
725 | skb->csum = csum_sub(hw_checksum, csum_pseudo_header); | |
726 | } | |
727 | ||
728 | #if IS_ENABLED(CONFIG_IPV6) | |
729 | /* In IPv6 packets, besides subtracting the pseudo header checksum, | |
730 | * we also compute/add the IP header checksum which | |
731 | * is not added by the HW. | |
732 | */ | |
733 | static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb, | |
734 | struct ipv6hdr *ipv6h) | |
735 | { | |
736 | __wsum csum_pseudo_hdr = 0; | |
737 | ||
738 | if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS) | |
739 | return -1; | |
82d69203 | 740 | hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr)); |
f8c6455b SM |
741 | |
742 | csum_pseudo_hdr = csum_partial(&ipv6h->saddr, | |
743 | sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0); | |
744 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len); | |
745 | csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr)); | |
746 | ||
747 | skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr); | |
748 | skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0)); | |
749 | return 0; | |
750 | } | |
751 | #endif | |
752 | static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va, | |
79a25852 | 753 | netdev_features_t dev_features) |
f8c6455b SM |
754 | { |
755 | __wsum hw_checksum = 0; | |
756 | ||
757 | void *hdr = (u8 *)va + sizeof(struct ethhdr); | |
758 | ||
759 | hw_checksum = csum_unfold((__force __sum16)cqe->checksum); | |
760 | ||
e802f8e4 | 761 | if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) && |
79a25852 | 762 | !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) { |
f8c6455b SM |
763 | hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr); |
764 | hdr += sizeof(struct vlan_hdr); | |
765 | } | |
766 | ||
767 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4)) | |
768 | get_fixed_ipv4_csum(hw_checksum, skb, hdr); | |
769 | #if IS_ENABLED(CONFIG_IPV6) | |
770 | else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6)) | |
771 | if (get_fixed_ipv6_csum(hw_checksum, skb, hdr)) | |
772 | return -1; | |
773 | #endif | |
774 | return 0; | |
775 | } | |
776 | ||
c27a02cd YP |
777 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
778 | { | |
779 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
ec693d47 | 780 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd | 781 | struct mlx4_cqe *cqe; |
41d942d5 | 782 | struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; |
4cce66cd | 783 | struct mlx4_en_rx_alloc *frags; |
c27a02cd | 784 | struct mlx4_en_rx_desc *rx_desc; |
47a38e15 | 785 | struct bpf_prog *xdp_prog; |
c27a02cd YP |
786 | struct sk_buff *skb; |
787 | int index; | |
788 | int nr; | |
789 | unsigned int length; | |
790 | int polled = 0; | |
791 | int ip_summed; | |
08ff3235 | 792 | int factor = priv->cqe_factor; |
ec693d47 | 793 | u64 timestamp; |
837052d0 | 794 | bool l2_tunnel; |
c27a02cd YP |
795 | |
796 | if (!priv->port_up) | |
797 | return 0; | |
798 | ||
38be0a34 EB |
799 | if (budget <= 0) |
800 | return polled; | |
801 | ||
47a38e15 BB |
802 | xdp_prog = READ_ONCE(ring->xdp_prog); |
803 | ||
c27a02cd YP |
804 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx |
805 | * descriptor offset can be deduced from the CQE index instead of | |
806 | * reading 'cqe->index' */ | |
807 | index = cq->mcq.cons_index & ring->size_mask; | |
b1b6b4da | 808 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
c27a02cd YP |
809 | |
810 | /* Process all completed CQEs */ | |
811 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
812 | cq->mcq.cons_index & cq->size)) { | |
813 | ||
4cce66cd | 814 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
815 | rx_desc = ring->buf + (index << ring->log_stride); |
816 | ||
817 | /* | |
818 | * make sure we read the CQE after we read the ownership bit | |
819 | */ | |
12b3375f | 820 | dma_rmb(); |
c27a02cd YP |
821 | |
822 | /* Drop packet on bad receive or bad checksum */ | |
823 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
824 | MLX4_CQE_OPCODE_ERROR)) { | |
1a91de28 JP |
825 | en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", |
826 | ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, | |
827 | ((struct mlx4_err_cqe *)cqe)->syndrome); | |
c27a02cd YP |
828 | goto next; |
829 | } | |
830 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 831 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
832 | goto next; |
833 | } | |
834 | ||
79aeaccd YB |
835 | /* Check if we need to drop the packet if SRIOV is not enabled |
836 | * and not performing the selftest or flb disabled | |
837 | */ | |
838 | if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { | |
839 | struct ethhdr *ethh; | |
840 | dma_addr_t dma; | |
79aeaccd YB |
841 | /* Get pointer to first fragment since we haven't |
842 | * skb yet and cast it to ethhdr struct | |
843 | */ | |
844 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
845 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
846 | DMA_FROM_DEVICE); | |
847 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
70fbe079 | 848 | frags[0].page_offset); |
79aeaccd | 849 | |
c07cb4b0 YB |
850 | if (is_multicast_ether_addr(ethh->h_dest)) { |
851 | struct mlx4_mac_entry *entry; | |
c07cb4b0 YB |
852 | struct hlist_head *bucket; |
853 | unsigned int mac_hash; | |
854 | ||
855 | /* Drop the packet, since HW loopback-ed it */ | |
856 | mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; | |
857 | bucket = &priv->mac_hash[mac_hash]; | |
858 | rcu_read_lock(); | |
b67bfe0d | 859 | hlist_for_each_entry_rcu(entry, bucket, hlist) { |
c07cb4b0 YB |
860 | if (ether_addr_equal_64bits(entry->mac, |
861 | ethh->h_source)) { | |
862 | rcu_read_unlock(); | |
863 | goto next; | |
864 | } | |
865 | } | |
866 | rcu_read_unlock(); | |
867 | } | |
79aeaccd | 868 | } |
5b4c4d36 | 869 | |
c27a02cd YP |
870 | /* |
871 | * Packet is OK - process it. | |
872 | */ | |
873 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 874 | length -= ring->fcs_del; |
c27a02cd YP |
875 | ring->bytes += length; |
876 | ring->packets++; | |
837052d0 OG |
877 | l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && |
878 | (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); | |
c27a02cd | 879 | |
47a38e15 BB |
880 | /* A bpf program gets first chance to drop the packet. It may |
881 | * read bytes but not past the end of the frag. | |
882 | */ | |
883 | if (xdp_prog) { | |
884 | struct xdp_buff xdp; | |
885 | dma_addr_t dma; | |
886 | u32 act; | |
887 | ||
888 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
889 | dma_sync_single_for_cpu(priv->ddev, dma, | |
890 | priv->frag_info[0].frag_size, | |
891 | DMA_FROM_DEVICE); | |
892 | ||
893 | xdp.data = page_address(frags[0].page) + | |
894 | frags[0].page_offset; | |
895 | xdp.data_end = xdp.data + length; | |
896 | ||
897 | act = bpf_prog_run_xdp(xdp_prog, &xdp); | |
898 | switch (act) { | |
899 | case XDP_PASS: | |
900 | break; | |
901 | default: | |
902 | bpf_warn_invalid_xdp_action(act); | |
903 | case XDP_ABORTED: | |
904 | case XDP_DROP: | |
d576acf0 BB |
905 | if (mlx4_en_rx_recycle(ring, frags)) |
906 | goto consumed; | |
47a38e15 BB |
907 | goto next; |
908 | } | |
909 | } | |
910 | ||
c8c64cff | 911 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
f8c6455b SM |
912 | if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP | |
913 | MLX4_CQE_STATUS_UDP)) { | |
914 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && | |
915 | cqe->checksum == cpu_to_be16(0xffff)) { | |
916 | ip_summed = CHECKSUM_UNNECESSARY; | |
917 | ring->csum_ok++; | |
918 | } else { | |
919 | ip_summed = CHECKSUM_NONE; | |
920 | ring->csum_none++; | |
921 | } | |
c27a02cd | 922 | } else { |
f8c6455b SM |
923 | if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP && |
924 | (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | | |
925 | MLX4_CQE_STATUS_IPV6))) { | |
926 | ip_summed = CHECKSUM_COMPLETE; | |
927 | ring->csum_complete++; | |
928 | } else { | |
929 | ip_summed = CHECKSUM_NONE; | |
930 | ring->csum_none++; | |
931 | } | |
c27a02cd YP |
932 | } |
933 | } else { | |
934 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 935 | ring->csum_none++; |
c27a02cd YP |
936 | } |
937 | ||
dd65beac SM |
938 | /* This packet is eligible for GRO if it is: |
939 | * - DIX Ethernet (type interpretation) | |
940 | * - TCP/IP (v4) | |
941 | * - without IP options | |
942 | * - not an IP fragment | |
dd65beac | 943 | */ |
868fdb06 | 944 | if (dev->features & NETIF_F_GRO) { |
dd65beac SM |
945 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); |
946 | if (!gro_skb) | |
947 | goto next; | |
948 | ||
949 | nr = mlx4_en_complete_rx_desc(priv, | |
950 | rx_desc, frags, gro_skb, | |
951 | length); | |
952 | if (!nr) | |
953 | goto next; | |
954 | ||
f8c6455b SM |
955 | if (ip_summed == CHECKSUM_COMPLETE) { |
956 | void *va = skb_frag_address(skb_shinfo(gro_skb)->frags); | |
79a25852 IS |
957 | if (check_csum(cqe, gro_skb, va, |
958 | dev->features)) { | |
f8c6455b SM |
959 | ip_summed = CHECKSUM_NONE; |
960 | ring->csum_none++; | |
961 | ring->csum_complete--; | |
962 | } | |
963 | } | |
964 | ||
dd65beac SM |
965 | skb_shinfo(gro_skb)->nr_frags = nr; |
966 | gro_skb->len = length; | |
967 | gro_skb->data_len = length; | |
968 | gro_skb->ip_summed = ip_summed; | |
969 | ||
970 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) | |
c58942f2 OG |
971 | gro_skb->csum_level = 1; |
972 | ||
dd65beac | 973 | if ((cqe->vlan_my_qpn & |
e802f8e4 | 974 | cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) && |
dd65beac SM |
975 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { |
976 | u16 vid = be16_to_cpu(cqe->sl_vid); | |
977 | ||
978 | __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); | |
e38af4fa HHZ |
979 | } else if ((be32_to_cpu(cqe->vlan_my_qpn) & |
980 | MLX4_CQE_SVLAN_PRESENT_MASK) && | |
981 | (dev->features & NETIF_F_HW_VLAN_STAG_RX)) { | |
982 | __vlan_hwaccel_put_tag(gro_skb, | |
983 | htons(ETH_P_8021AD), | |
984 | be16_to_cpu(cqe->sl_vid)); | |
dd65beac SM |
985 | } |
986 | ||
987 | if (dev->features & NETIF_F_RXHASH) | |
988 | skb_set_hash(gro_skb, | |
989 | be32_to_cpu(cqe->immed_rss_invalid), | |
0a6d4245 ED |
990 | (ip_summed == CHECKSUM_UNNECESSARY) ? |
991 | PKT_HASH_TYPE_L4 : | |
992 | PKT_HASH_TYPE_L3); | |
dd65beac SM |
993 | |
994 | skb_record_rx_queue(gro_skb, cq->ring); | |
dd65beac SM |
995 | |
996 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { | |
997 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
998 | mlx4_en_fill_hwtstamps(mdev, | |
999 | skb_hwtstamps(gro_skb), | |
1000 | timestamp); | |
1001 | } | |
1002 | ||
1003 | napi_gro_frags(&cq->napi); | |
1004 | goto next; | |
1005 | } | |
1006 | ||
1007 | /* GRO not possible, complete processing here */ | |
4cce66cd | 1008 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
c27a02cd | 1009 | if (!skb) { |
d21ed3a3 | 1010 | ring->dropped++; |
c27a02cd YP |
1011 | goto next; |
1012 | } | |
1013 | ||
e7c1c2c4 YP |
1014 | if (unlikely(priv->validate_loopback)) { |
1015 | validate_loopback(priv, skb); | |
1016 | goto next; | |
1017 | } | |
1018 | ||
f8c6455b | 1019 | if (ip_summed == CHECKSUM_COMPLETE) { |
79a25852 | 1020 | if (check_csum(cqe, skb, skb->data, dev->features)) { |
f8c6455b SM |
1021 | ip_summed = CHECKSUM_NONE; |
1022 | ring->csum_complete--; | |
1023 | ring->csum_none++; | |
1024 | } | |
1025 | } | |
1026 | ||
c27a02cd YP |
1027 | skb->ip_summed = ip_summed; |
1028 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 1029 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 1030 | |
9ca8600e TH |
1031 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) |
1032 | skb->csum_level = 1; | |
837052d0 | 1033 | |
ad86107f | 1034 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
1035 | skb_set_hash(skb, |
1036 | be32_to_cpu(cqe->immed_rss_invalid), | |
0a6d4245 ED |
1037 | (ip_summed == CHECKSUM_UNNECESSARY) ? |
1038 | PKT_HASH_TYPE_L4 : | |
1039 | PKT_HASH_TYPE_L3); | |
ad86107f | 1040 | |
ec693d47 | 1041 | if ((be32_to_cpu(cqe->vlan_my_qpn) & |
e802f8e4 | 1042 | MLX4_CQE_CVLAN_PRESENT_MASK) && |
ec693d47 | 1043 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) |
86a9bad3 | 1044 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); |
e38af4fa HHZ |
1045 | else if ((be32_to_cpu(cqe->vlan_my_qpn) & |
1046 | MLX4_CQE_SVLAN_PRESENT_MASK) && | |
1047 | (dev->features & NETIF_F_HW_VLAN_STAG_RX)) | |
1048 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), | |
1049 | be16_to_cpu(cqe->sl_vid)); | |
f1b553fb | 1050 | |
ec693d47 AV |
1051 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
1052 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
1053 | mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), | |
1054 | timestamp); | |
1055 | } | |
1056 | ||
868fdb06 | 1057 | napi_gro_receive(&cq->napi, skb); |
c27a02cd | 1058 | next: |
4cce66cd TLSC |
1059 | for (nr = 0; nr < priv->num_frags; nr++) |
1060 | mlx4_en_free_frag(priv, frags, nr); | |
1061 | ||
d576acf0 | 1062 | consumed: |
c27a02cd YP |
1063 | ++cq->mcq.cons_index; |
1064 | index = (cq->mcq.cons_index) & ring->size_mask; | |
b1b6b4da | 1065 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
f1d29a3f | 1066 | if (++polled == budget) |
c27a02cd | 1067 | goto out; |
c27a02cd YP |
1068 | } |
1069 | ||
c27a02cd YP |
1070 | out: |
1071 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
1072 | mlx4_cq_set_ci(&cq->mcq); | |
1073 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
1074 | ring->cons = cq->mcq.cons_index; | |
4cce66cd | 1075 | mlx4_en_refill_rx_buffers(priv, ring); |
c27a02cd YP |
1076 | mlx4_en_update_rx_prod_db(ring); |
1077 | return polled; | |
1078 | } | |
1079 | ||
1080 | ||
1081 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
1082 | { | |
1083 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
1084 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
1085 | ||
477b35b4 ED |
1086 | if (likely(priv->port_up)) |
1087 | napi_schedule_irqoff(&cq->napi); | |
c27a02cd YP |
1088 | else |
1089 | mlx4_en_arm_cq(priv, cq); | |
1090 | } | |
1091 | ||
1092 | /* Rx CQ polling - called by NAPI */ | |
1093 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
1094 | { | |
1095 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
1096 | struct net_device *dev = cq->dev; | |
1097 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1098 | int done; | |
1099 | ||
1100 | done = mlx4_en_process_rx_cq(dev, cq, budget); | |
1101 | ||
1102 | /* If we used up all the quota - we're probably not done yet... */ | |
2eacc23c | 1103 | if (done == budget) { |
35f6f453 | 1104 | const struct cpumask *aff; |
dc2ec62f TG |
1105 | struct irq_data *idata; |
1106 | int cpu_curr; | |
35f6f453 | 1107 | |
c27a02cd | 1108 | INC_PERF_COUNTER(priv->pstats.napi_quota); |
35f6f453 AV |
1109 | |
1110 | cpu_curr = smp_processor_id(); | |
dc2ec62f TG |
1111 | idata = irq_desc_get_irq_data(cq->irq_desc); |
1112 | aff = irq_data_get_affinity_mask(idata); | |
35f6f453 | 1113 | |
2e1af7d7 ED |
1114 | if (likely(cpumask_test_cpu(cpu_curr, aff))) |
1115 | return budget; | |
1116 | ||
1117 | /* Current cpu is not according to smp_irq_affinity - | |
1118 | * probably affinity changed. need to stop this NAPI | |
1119 | * poll, and restart it on the right CPU | |
1120 | */ | |
1121 | done = 0; | |
c27a02cd | 1122 | } |
1a288172 ED |
1123 | /* Done for now */ |
1124 | napi_complete_done(napi, done); | |
1125 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
1126 | return done; |
1127 | } | |
1128 | ||
51151a16 | 1129 | static const int frag_sizes[] = { |
c27a02cd YP |
1130 | FRAG_SZ0, |
1131 | FRAG_SZ1, | |
1132 | FRAG_SZ2, | |
1133 | FRAG_SZ3 | |
1134 | }; | |
1135 | ||
1136 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
1137 | { | |
d576acf0 | 1138 | enum dma_data_direction dma_dir = PCI_DMA_FROMDEVICE; |
c27a02cd | 1139 | struct mlx4_en_priv *priv = netdev_priv(dev); |
47a38e15 | 1140 | int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu); |
d576acf0 BB |
1141 | int order = MLX4_EN_ALLOC_PREFER_ORDER; |
1142 | u32 align = SMP_CACHE_BYTES; | |
c27a02cd YP |
1143 | int buf_size = 0; |
1144 | int i = 0; | |
1145 | ||
d576acf0 BB |
1146 | /* bpf requires buffers to be set up as 1 packet per page. |
1147 | * This only works when num_frags == 1. | |
1148 | */ | |
1149 | if (priv->xdp_ring_num) { | |
1150 | /* This will gain efficient xdp frame recycling at the expense | |
1151 | * of more costly truesize accounting | |
1152 | */ | |
1153 | align = PAGE_SIZE; | |
1154 | order = 0; | |
1155 | } | |
1156 | ||
c27a02cd | 1157 | while (buf_size < eff_mtu) { |
d576acf0 | 1158 | priv->frag_info[i].order = order; |
c27a02cd YP |
1159 | priv->frag_info[i].frag_size = |
1160 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
1161 | frag_sizes[i] : eff_mtu - buf_size; | |
1162 | priv->frag_info[i].frag_prefix_size = buf_size; | |
e8e7f018 | 1163 | priv->frag_info[i].frag_stride = |
d576acf0 BB |
1164 | ALIGN(priv->frag_info[i].frag_size, align); |
1165 | priv->frag_info[i].dma_dir = dma_dir; | |
c27a02cd YP |
1166 | buf_size += priv->frag_info[i].frag_size; |
1167 | i++; | |
1168 | } | |
1169 | ||
1170 | priv->num_frags = i; | |
1171 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 1172 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 1173 | |
1a91de28 JP |
1174 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", |
1175 | eff_mtu, priv->num_frags); | |
c27a02cd | 1176 | for (i = 0; i < priv->num_frags; i++) { |
51151a16 | 1177 | en_err(priv, |
5f6e9800 | 1178 | " frag:%d - size:%d prefix:%d stride:%d\n", |
51151a16 ED |
1179 | i, |
1180 | priv->frag_info[i].frag_size, | |
1181 | priv->frag_info[i].frag_prefix_size, | |
51151a16 | 1182 | priv->frag_info[i].frag_stride); |
c27a02cd YP |
1183 | } |
1184 | } | |
1185 | ||
1186 | /* RSS related functions */ | |
1187 | ||
9f519f68 YP |
1188 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
1189 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
1190 | enum mlx4_qp_state *state, |
1191 | struct mlx4_qp *qp) | |
1192 | { | |
1193 | struct mlx4_en_dev *mdev = priv->mdev; | |
1194 | struct mlx4_qp_context *context; | |
1195 | int err = 0; | |
1196 | ||
14f8dc49 JP |
1197 | context = kmalloc(sizeof(*context), GFP_KERNEL); |
1198 | if (!context) | |
c27a02cd | 1199 | return -ENOMEM; |
c27a02cd | 1200 | |
40f2287b | 1201 | err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); |
c27a02cd | 1202 | if (err) { |
453a6082 | 1203 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 1204 | goto out; |
c27a02cd YP |
1205 | } |
1206 | qp->event = mlx4_en_sqp_event; | |
1207 | ||
1208 | memset(context, 0, sizeof *context); | |
00d7d7bc | 1209 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 1210 | qpn, ring->cqn, -1, context); |
9f519f68 | 1211 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 1212 | |
f3a9d1f2 | 1213 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 1214 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 1215 | context->param3 |= cpu_to_be32(1 << 29); |
f0df3503 MM |
1216 | if (priv->dev->features & NETIF_F_RXFCS) |
1217 | ring->fcs_del = 0; | |
1218 | else | |
1219 | ring->fcs_del = ETH_FCS_LEN; | |
4a5f4dd8 YP |
1220 | } else |
1221 | ring->fcs_del = 0; | |
f3a9d1f2 | 1222 | |
9f519f68 | 1223 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
1224 | if (err) { |
1225 | mlx4_qp_remove(mdev->dev, qp); | |
1226 | mlx4_qp_free(mdev->dev, qp); | |
1227 | } | |
9f519f68 | 1228 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
1229 | out: |
1230 | kfree(context); | |
1231 | return err; | |
1232 | } | |
1233 | ||
cabdc8ee HHZ |
1234 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
1235 | { | |
1236 | int err; | |
1237 | u32 qpn; | |
1238 | ||
d57febe1 MB |
1239 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, |
1240 | MLX4_RESERVE_A0_QP); | |
cabdc8ee HHZ |
1241 | if (err) { |
1242 | en_err(priv, "Failed reserving drop qpn\n"); | |
1243 | return err; | |
1244 | } | |
40f2287b | 1245 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); |
cabdc8ee HHZ |
1246 | if (err) { |
1247 | en_err(priv, "Failed allocating drop qp\n"); | |
1248 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1249 | return err; | |
1250 | } | |
1251 | ||
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
1256 | { | |
1257 | u32 qpn; | |
1258 | ||
1259 | qpn = priv->drop_qp.qpn; | |
1260 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
1261 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
1262 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1263 | } | |
1264 | ||
c27a02cd YP |
1265 | /* Allocate rx qp's and configure them according to rss map */ |
1266 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
1267 | { | |
1268 | struct mlx4_en_dev *mdev = priv->mdev; | |
1269 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1270 | struct mlx4_qp_context context; | |
876f6e67 | 1271 | struct mlx4_rss_context *rss_context; |
93d3e367 | 1272 | int rss_rings; |
c27a02cd | 1273 | void *ptr; |
876f6e67 | 1274 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 1275 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 1276 | int i, qpn; |
c27a02cd YP |
1277 | int err = 0; |
1278 | int good_qps = 0; | |
1279 | ||
453a6082 | 1280 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
1281 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
1282 | priv->rx_ring_num, | |
ddae0349 | 1283 | &rss_map->base_qpn, 0); |
c27a02cd | 1284 | if (err) { |
b6b912e0 | 1285 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
1286 | return err; |
1287 | } | |
1288 | ||
b6b912e0 | 1289 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 1290 | qpn = rss_map->base_qpn + i; |
41d942d5 | 1291 | err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], |
c27a02cd YP |
1292 | &rss_map->state[i], |
1293 | &rss_map->qps[i]); | |
1294 | if (err) | |
1295 | goto rss_err; | |
1296 | ||
1297 | ++good_qps; | |
1298 | } | |
1299 | ||
1300 | /* Configure RSS indirection qp */ | |
40f2287b | 1301 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); |
c27a02cd | 1302 | if (err) { |
453a6082 | 1303 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 1304 | goto rss_err; |
c27a02cd YP |
1305 | } |
1306 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1307 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
41d942d5 | 1308 | priv->rx_ring[0]->cqn, -1, &context); |
c27a02cd | 1309 | |
93d3e367 YP |
1310 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
1311 | rss_rings = priv->rx_ring_num; | |
1312 | else | |
1313 | rss_rings = priv->prof->rss_rings; | |
1314 | ||
876f6e67 OG |
1315 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
1316 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 1317 | rss_context = ptr; |
93d3e367 | 1318 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 1319 | (rss_map->base_qpn)); |
89efea25 | 1320 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
1321 | if (priv->mdev->profile.udp_rss) { |
1322 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
1323 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
1324 | } | |
837052d0 OG |
1325 | |
1326 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { | |
1327 | en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); | |
1328 | rss_mask |= MLX4_RSS_BY_INNER_HEADERS; | |
1329 | } | |
1330 | ||
0533943c | 1331 | rss_context->flags = rss_mask; |
876f6e67 | 1332 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
947cbb0a EP |
1333 | if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) { |
1334 | rss_context->hash_fn = MLX4_RSS_HASH_XOR; | |
1335 | } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) { | |
1336 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; | |
1337 | memcpy(rss_context->rss_key, priv->rss_key, | |
1338 | MLX4_EN_RSS_KEY_SIZE); | |
947cbb0a EP |
1339 | } else { |
1340 | en_err(priv, "Unknown RSS hash function requested\n"); | |
1341 | err = -EINVAL; | |
1342 | goto indir_err; | |
1343 | } | |
c27a02cd YP |
1344 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, |
1345 | &rss_map->indir_qp, &rss_map->indir_state); | |
1346 | if (err) | |
1347 | goto indir_err; | |
1348 | ||
1349 | return 0; | |
1350 | ||
1351 | indir_err: | |
1352 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1353 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1354 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1355 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
1356 | rss_err: |
1357 | for (i = 0; i < good_qps; i++) { | |
1358 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1359 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1360 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1361 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1362 | } | |
b6b912e0 | 1363 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
1364 | return err; |
1365 | } | |
1366 | ||
1367 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1368 | { | |
1369 | struct mlx4_en_dev *mdev = priv->mdev; | |
1370 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1371 | int i; | |
1372 | ||
1373 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1374 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1375 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1376 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1377 | |
b6b912e0 | 1378 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1379 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1380 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1381 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1382 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1383 | } | |
b6b912e0 | 1384 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1385 | } |