]> git.ipfire.org Git - thirdparty/linux.git/blame - drivers/net/ethernet/mellanox/mlx5/core/cmd.c
projects / thirdparty / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5: No command allowed when command interface is not ready
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / cmd.c
CommitLineData
e126ba97 1/*
b3f63c3d 2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97 34#include <linux/module.h>
e126ba97
EC		 35#include <linux/errno.h>
36#include <linux/pci.h>
37#include <linux/dma-mapping.h>
38#include <linux/slab.h>
39#include <linux/delay.h>
40#include <linux/random.h>
41#include <linux/io-mapping.h>
42#include <linux/mlx5/driver.h>
71edc69c 43#include <linux/mlx5/eq.h>
e126ba97
EC		 44#include <linux/debugfs.h>
45
46#include "mlx5_core.h"
71edc69c 47#include "lib/eq.h"
e126ba97
EC		 48
49enum {
0a324f31 50 CMD_IF_REV = 5,
e126ba97
EC		 51};
52
53enum {
54 CMD_MODE_POLLING,
55 CMD_MODE_EVENTS
56};
57
e126ba97
EC		 58enum {
59 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
60 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
61 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
62 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
63 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
64 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
65 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
66 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
67 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
68 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
69 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
70};
71
e126ba97
EC		 72static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
73 struct mlx5_cmd_msg *in,
74 struct mlx5_cmd_msg *out,
746b5583 75 void *uout, int uout_size,
e126ba97
EC		 76 mlx5_cmd_cbk_t cbk,
77 void *context, int page_queue)
78{
79 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
80 struct mlx5_cmd_work_ent *ent;
81
82 ent = kzalloc(sizeof(*ent), alloc_flags);
83 if (!ent)
84 return ERR_PTR(-ENOMEM);
85
86 ent->in = in;
87 ent->out = out;
746b5583
EC		 88 ent->uout = uout;
89 ent->uout_size = uout_size;
e126ba97
EC		 90 ent->callback = cbk;
91 ent->context = context;
92 ent->cmd = cmd;
93 ent->page_queue = page_queue;
94
95 return ent;
96}
97
98static u8 alloc_token(struct mlx5_cmd *cmd)
99{
100 u8 token;
101
102 spin_lock(&cmd->token_lock);
4cbdd27c
AS		 103 cmd->token++;
104 if (cmd->token == 0)
105 cmd->token++;
106 token = cmd->token;
e126ba97
EC		 107 spin_unlock(&cmd->token_lock);
108
109 return token;
110}
111
112static int alloc_ent(struct mlx5_cmd *cmd)
113{
114 unsigned long flags;
115 int ret;
116
117 spin_lock_irqsave(&cmd->alloc_lock, flags);
118 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
119 if (ret < cmd->max_reg_cmds)
120 clear_bit(ret, &cmd->bitmask);
121 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
122
123 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
124}
125
126static void free_ent(struct mlx5_cmd *cmd, int idx)
127{
128 unsigned long flags;
129
130 spin_lock_irqsave(&cmd->alloc_lock, flags);
131 set_bit(idx, &cmd->bitmask);
132 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
133}
134
135static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
136{
137 return cmd->cmd_buf + (idx << cmd->log_stride);
138}
139
ed644fab
MS		 140static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
141{
142 int size = msg->len;
143 int blen = size - min_t(int, sizeof(msg->first.data), size);
144
145 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
146}
147
2c0f8ce1 148static u8 xor8_buf(void *buf, size_t offset, int len)
e126ba97
EC		 149{
150 u8 *ptr = buf;
151 u8 sum = 0;
152 int i;
2c0f8ce1 153 int end = len + offset;
e126ba97 154
2c0f8ce1 155 for (i = offset; i < end; i++)
e126ba97
EC		 156 sum ^= ptr[i];
157
158 return sum;
159}
160
161static int verify_block_sig(struct mlx5_cmd_prot_block *block)
162{
2c0f8ce1
PB		 163 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
164 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
165
166 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
e126ba97
EC		 167 return -EINVAL;
168
2c0f8ce1 169 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
e126ba97
EC		 170 return -EINVAL;
171
172 return 0;
173}
174
2c0f8ce1 175static void calc_block_sig(struct mlx5_cmd_prot_block *block)
e126ba97 176{
2c0f8ce1
PB		 177 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
178 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
179
180 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
181 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
e126ba97
EC		 182}
183
2c0f8ce1 184static void calc_chain_sig(struct mlx5_cmd_msg *msg)
e126ba97
EC		 185{
186 struct mlx5_cmd_mailbox *next = msg->next;
ed644fab 187 int n = mlx5_calc_cmd_blocks(msg);
2c0f8ce1
PB		 188 int i = 0;
189
190 for (i = 0; i < n && next; i++) {
191 calc_block_sig(next->buf);
e126ba97
EC		 192 next = next->next;
193 }
194}
195
c1868b82 196static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
e126ba97 197{
2c0f8ce1
PB		 198 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
199 if (csum) {
200 calc_chain_sig(ent->in);
201 calc_chain_sig(ent->out);
202 }
e126ba97
EC		 203}
204
205static void poll_timeout(struct mlx5_cmd_work_ent *ent)
206{
207 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
208 u8 own;
209
210 do {
250ae0d4 211 own = READ_ONCE(ent->lay->status_own);
e126ba97
EC		 212 if (!(own & CMD_OWNER_HW)) {
213 ent->ret = 0;
214 return;
215 }
269d26f4 216 cond_resched();
e126ba97
EC		 217 } while (time_before(jiffies, poll_end));
218
219 ent->ret = -ETIMEDOUT;
220}
221
222static void free_cmd(struct mlx5_cmd_work_ent *ent)
223{
224 kfree(ent);
225}
226
e126ba97
EC		 227static int verify_signature(struct mlx5_cmd_work_ent *ent)
228{
229 struct mlx5_cmd_mailbox *next = ent->out->next;
ed644fab 230 int n = mlx5_calc_cmd_blocks(ent->out);
e126ba97
EC		 231 int err;
232 u8 sig;
2c0f8ce1 233 int i = 0;
e126ba97 234
2c0f8ce1 235 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
e126ba97
EC		 236 if (sig != 0xff)
237 return -EINVAL;
238
2c0f8ce1 239 for (i = 0; i < n && next; i++) {
e126ba97
EC		 240 err = verify_block_sig(next->buf);
241 if (err)
242 return err;
243
244 next = next->next;
245 }
246
247 return 0;
248}
249
250static void dump_buf(void *buf, int size, int data_only, int offset)
251{
252 __be32 *p = buf;
253 int i;
254
255 for (i = 0; i < size; i += 16) {
256 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
257 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
258 be32_to_cpu(p[3]));
259 p += 4;
260 offset += 16;
261 }
262 if (!data_only)
263 pr_debug("\n");
264}
265
89d44f0a
MD		 266static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
267 u32 *synd, u8 *status)
268{
269 *synd = 0;
270 *status = 0;
271
272 switch (op) {
273 case MLX5_CMD_OP_TEARDOWN_HCA:
274 case MLX5_CMD_OP_DISABLE_HCA:
275 case MLX5_CMD_OP_MANAGE_PAGES:
276 case MLX5_CMD_OP_DESTROY_MKEY:
277 case MLX5_CMD_OP_DESTROY_EQ:
278 case MLX5_CMD_OP_DESTROY_CQ:
279 case MLX5_CMD_OP_DESTROY_QP:
280 case MLX5_CMD_OP_DESTROY_PSV:
281 case MLX5_CMD_OP_DESTROY_SRQ:
282 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
a4517339 283 case MLX5_CMD_OP_DESTROY_XRQ:
89d44f0a
MD		 284 case MLX5_CMD_OP_DESTROY_DCT:
285 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
a750276f
OG		 286 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
287 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
89d44f0a
MD		 288 case MLX5_CMD_OP_DEALLOC_PD:
289 case MLX5_CMD_OP_DEALLOC_UAR:
20bb566b 290 case MLX5_CMD_OP_DETACH_FROM_MCG:
89d44f0a
MD		 291 case MLX5_CMD_OP_DEALLOC_XRCD:
292 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
293 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
294 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
84df61eb
AH		 295 case MLX5_CMD_OP_DESTROY_LAG:
296 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
89d44f0a
MD		 297 case MLX5_CMD_OP_DESTROY_TIR:
298 case MLX5_CMD_OP_DESTROY_SQ:
299 case MLX5_CMD_OP_DESTROY_RQ:
300 case MLX5_CMD_OP_DESTROY_RMP:
301 case MLX5_CMD_OP_DESTROY_TIS:
302 case MLX5_CMD_OP_DESTROY_RQT:
303 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
304 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
305 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
9dc0b289 306 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
0d834442
MHY		 307 case MLX5_CMD_OP_2ERR_QP:
308 case MLX5_CMD_OP_2RST_QP:
309 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
310 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
311 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
312 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
60786f09 313 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
2de24fed 314 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
6062118d 315 case MLX5_CMD_OP_FPGA_DESTROY_QP:
38b7ca92 316 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
09adbb5d 317 case MLX5_CMD_OP_DEALLOC_MEMIC:
ef90c5e9 318 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
89d44f0a
MD		 319 return MLX5_CMD_STAT_OK;
320
321 case MLX5_CMD_OP_QUERY_HCA_CAP:
322 case MLX5_CMD_OP_QUERY_ADAPTER:
323 case MLX5_CMD_OP_INIT_HCA:
324 case MLX5_CMD_OP_ENABLE_HCA:
325 case MLX5_CMD_OP_QUERY_PAGES:
326 case MLX5_CMD_OP_SET_HCA_CAP:
327 case MLX5_CMD_OP_QUERY_ISSI:
328 case MLX5_CMD_OP_SET_ISSI:
329 case MLX5_CMD_OP_CREATE_MKEY:
330 case MLX5_CMD_OP_QUERY_MKEY:
331 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
89d44f0a
MD		 332 case MLX5_CMD_OP_CREATE_EQ:
333 case MLX5_CMD_OP_QUERY_EQ:
334 case MLX5_CMD_OP_GEN_EQE:
335 case MLX5_CMD_OP_CREATE_CQ:
336 case MLX5_CMD_OP_QUERY_CQ:
337 case MLX5_CMD_OP_MODIFY_CQ:
338 case MLX5_CMD_OP_CREATE_QP:
339 case MLX5_CMD_OP_RST2INIT_QP:
340 case MLX5_CMD_OP_INIT2RTR_QP:
341 case MLX5_CMD_OP_RTR2RTS_QP:
342 case MLX5_CMD_OP_RTS2RTS_QP:
343 case MLX5_CMD_OP_SQERR2RTS_QP:
89d44f0a
MD		 344 case MLX5_CMD_OP_QUERY_QP:
345 case MLX5_CMD_OP_SQD_RTS_QP:
346 case MLX5_CMD_OP_INIT2INIT_QP:
347 case MLX5_CMD_OP_CREATE_PSV:
348 case MLX5_CMD_OP_CREATE_SRQ:
349 case MLX5_CMD_OP_QUERY_SRQ:
350 case MLX5_CMD_OP_ARM_RQ:
351 case MLX5_CMD_OP_CREATE_XRC_SRQ:
352 case MLX5_CMD_OP_QUERY_XRC_SRQ:
353 case MLX5_CMD_OP_ARM_XRC_SRQ:
a4517339
MG		 354 case MLX5_CMD_OP_CREATE_XRQ:
355 case MLX5_CMD_OP_QUERY_XRQ:
356 case MLX5_CMD_OP_ARM_XRQ:
89d44f0a
MD		 357 case MLX5_CMD_OP_CREATE_DCT:
358 case MLX5_CMD_OP_DRAIN_DCT:
359 case MLX5_CMD_OP_QUERY_DCT:
360 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
361 case MLX5_CMD_OP_QUERY_VPORT_STATE:
362 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
363 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
364 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
365 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
89d44f0a
MD		 366 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
367 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
368 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
369 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
370 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
371 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
61c5b5c9 372 case MLX5_CMD_OP_QUERY_VNIC_ENV:
89d44f0a
MD		 373 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
374 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
375 case MLX5_CMD_OP_QUERY_Q_COUNTER:
fd4572b3
ED		 376 case MLX5_CMD_OP_SET_MONITOR_COUNTER:
377 case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
37e92a9d 378 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
1f30a86c 379 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
a750276f
OG		 380 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
381 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
382 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
383 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
89d44f0a
MD		 384 case MLX5_CMD_OP_ALLOC_PD:
385 case MLX5_CMD_OP_ALLOC_UAR:
386 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
387 case MLX5_CMD_OP_ACCESS_REG:
388 case MLX5_CMD_OP_ATTACH_TO_MCG:
389 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
390 case MLX5_CMD_OP_MAD_IFC:
391 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
392 case MLX5_CMD_OP_SET_MAD_DEMUX:
393 case MLX5_CMD_OP_NOP:
394 case MLX5_CMD_OP_ALLOC_XRCD:
395 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
396 case MLX5_CMD_OP_QUERY_CONG_STATUS:
397 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
398 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
399 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
400 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
401 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
402 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
403 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
84df61eb
AH		 404 case MLX5_CMD_OP_CREATE_LAG:
405 case MLX5_CMD_OP_MODIFY_LAG:
406 case MLX5_CMD_OP_QUERY_LAG:
407 case MLX5_CMD_OP_CREATE_VPORT_LAG:
89d44f0a
MD		 408 case MLX5_CMD_OP_CREATE_TIR:
409 case MLX5_CMD_OP_MODIFY_TIR:
410 case MLX5_CMD_OP_QUERY_TIR:
411 case MLX5_CMD_OP_CREATE_SQ:
412 case MLX5_CMD_OP_MODIFY_SQ:
413 case MLX5_CMD_OP_QUERY_SQ:
414 case MLX5_CMD_OP_CREATE_RQ:
415 case MLX5_CMD_OP_MODIFY_RQ:
416 case MLX5_CMD_OP_QUERY_RQ:
417 case MLX5_CMD_OP_CREATE_RMP:
418 case MLX5_CMD_OP_MODIFY_RMP:
419 case MLX5_CMD_OP_QUERY_RMP:
420 case MLX5_CMD_OP_CREATE_TIS:
421 case MLX5_CMD_OP_MODIFY_TIS:
422 case MLX5_CMD_OP_QUERY_TIS:
423 case MLX5_CMD_OP_CREATE_RQT:
424 case MLX5_CMD_OP_MODIFY_RQT:
425 case MLX5_CMD_OP_QUERY_RQT:
0d834442 426
89d44f0a
MD		 427 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
428 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
429 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
430 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
89d44f0a 431 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
9dc0b289
AV		 432 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
433 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
60786f09 434 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
2de24fed 435 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
6062118d
IT		 436 case MLX5_CMD_OP_FPGA_CREATE_QP:
437 case MLX5_CMD_OP_FPGA_MODIFY_QP:
438 case MLX5_CMD_OP_FPGA_QUERY_QP:
439 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
38b7ca92 440 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
e662e14d
YH		 441 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
442 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
09adbb5d 443 case MLX5_CMD_OP_ALLOC_MEMIC:
89d44f0a
MD		 444 *status = MLX5_DRIVER_STATUS_ABORTED;
445 *synd = MLX5_DRIVER_SYND;
446 return -EIO;
447 default:
448 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
449 return -EINVAL;
450 }
451}
452
e126ba97
EC		 453const char *mlx5_command_str(int command)
454{
42ca502e 455#define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
b3f63c3d 456
42ca502e
AV		 457 switch (command) {
458 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
459 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
460 MLX5_COMMAND_STR_CASE(INIT_HCA);
461 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
462 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
463 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
464 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
465 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
466 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
467 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
468 MLX5_COMMAND_STR_CASE(SET_ISSI);
0f403910 469 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
42ca502e
AV		 470 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
471 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
472 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
473 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
474 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
475 MLX5_COMMAND_STR_CASE(CREATE_EQ);
476 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
477 MLX5_COMMAND_STR_CASE(QUERY_EQ);
478 MLX5_COMMAND_STR_CASE(GEN_EQE);
479 MLX5_COMMAND_STR_CASE(CREATE_CQ);
480 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
481 MLX5_COMMAND_STR_CASE(QUERY_CQ);
482 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
483 MLX5_COMMAND_STR_CASE(CREATE_QP);
484 MLX5_COMMAND_STR_CASE(DESTROY_QP);
485 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
486 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
487 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
488 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
489 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
490 MLX5_COMMAND_STR_CASE(2ERR_QP);
491 MLX5_COMMAND_STR_CASE(2RST_QP);
492 MLX5_COMMAND_STR_CASE(QUERY_QP);
493 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
494 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
495 MLX5_COMMAND_STR_CASE(CREATE_PSV);
496 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
497 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
498 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
499 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
500 MLX5_COMMAND_STR_CASE(ARM_RQ);
501 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
502 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
503 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
504 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
505 MLX5_COMMAND_STR_CASE(CREATE_DCT);
506 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
507 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
508 MLX5_COMMAND_STR_CASE(QUERY_DCT);
509 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
510 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
511 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
512 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
513 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
514 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
515 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
516 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
517 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
518 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
519 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
520 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
521 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
61c5b5c9 522 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
42ca502e
AV		 523 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
524 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
525 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
526 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
fd4572b3
ED		 527 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
528 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
37e92a9d 529 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
1f30a86c 530 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
a750276f
OG		 531 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
532 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
533 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
534 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
535 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
536 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
42ca502e
AV		 537 MLX5_COMMAND_STR_CASE(ALLOC_PD);
538 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
539 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
540 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
541 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
542 MLX5_COMMAND_STR_CASE(ACCESS_REG);
543 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
20bb566b 544 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
42ca502e
AV		 545 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
546 MLX5_COMMAND_STR_CASE(MAD_IFC);
547 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
548 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
549 MLX5_COMMAND_STR_CASE(NOP);
550 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
551 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
552 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
553 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
554 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
555 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
556 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
557 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
558 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
559 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
560 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
561 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
562 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
563 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
564 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
565 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
84df61eb
AH		 566 MLX5_COMMAND_STR_CASE(CREATE_LAG);
567 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
568 MLX5_COMMAND_STR_CASE(QUERY_LAG);
569 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
570 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
571 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
42ca502e
AV		 572 MLX5_COMMAND_STR_CASE(CREATE_TIR);
573 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
574 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
575 MLX5_COMMAND_STR_CASE(QUERY_TIR);
576 MLX5_COMMAND_STR_CASE(CREATE_SQ);
577 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
578 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
579 MLX5_COMMAND_STR_CASE(QUERY_SQ);
580 MLX5_COMMAND_STR_CASE(CREATE_RQ);
581 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
582 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
583 MLX5_COMMAND_STR_CASE(QUERY_RQ);
584 MLX5_COMMAND_STR_CASE(CREATE_RMP);
585 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
586 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
587 MLX5_COMMAND_STR_CASE(QUERY_RMP);
588 MLX5_COMMAND_STR_CASE(CREATE_TIS);
589 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
590 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
591 MLX5_COMMAND_STR_CASE(QUERY_TIS);
592 MLX5_COMMAND_STR_CASE(CREATE_RQT);
593 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
594 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
595 MLX5_COMMAND_STR_CASE(QUERY_RQT);
596 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
597 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
598 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
599 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
600 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
601 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
602 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
603 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
604 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
605 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
9dc0b289
AV		 606 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
607 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
608 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
5be1ea89 609 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
60786f09
MB		 610 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
611 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
2de24fed
OG		 612 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
613 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
6062118d
IT		 614 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
615 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
616 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
617 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
618 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
a4517339
MG		 619 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
620 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
621 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
622 MLX5_COMMAND_STR_CASE(ARM_XRQ);
38b7ca92
YH		 623 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
624 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
e662e14d
YH		 625 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
626 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
627 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
09adbb5d
AL		 628 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
629 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
e126ba97
EC		 630 default: return "unknown command opcode";
631 }
632}
633
c4f287c4
SM		 634static const char *cmd_status_str(u8 status)
635{
636 switch (status) {
637 case MLX5_CMD_STAT_OK:
638 return "OK";
639 case MLX5_CMD_STAT_INT_ERR:
640 return "internal error";
641 case MLX5_CMD_STAT_BAD_OP_ERR:
642 return "bad operation";
643 case MLX5_CMD_STAT_BAD_PARAM_ERR:
644 return "bad parameter";
645 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
646 return "bad system state";
647 case MLX5_CMD_STAT_BAD_RES_ERR:
648 return "bad resource";
649 case MLX5_CMD_STAT_RES_BUSY:
650 return "resource busy";
651 case MLX5_CMD_STAT_LIM_ERR:
652 return "limits exceeded";
653 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
654 return "bad resource state";
655 case MLX5_CMD_STAT_IX_ERR:
656 return "bad index";
657 case MLX5_CMD_STAT_NO_RES_ERR:
658 return "no resources";
659 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
660 return "bad input length";
661 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
662 return "bad output length";
663 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
664 return "bad QP state";
665 case MLX5_CMD_STAT_BAD_PKT_ERR:
666 return "bad packet (discarded)";
667 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
668 return "bad size too many outstanding CQEs";
669 default:
670 return "unknown status";
671 }
672}
673
674static int cmd_status_to_err(u8 status)
675{
676 switch (status) {
677 case MLX5_CMD_STAT_OK: return 0;
678 case MLX5_CMD_STAT_INT_ERR: return -EIO;
679 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
680 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
681 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
682 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
683 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
684 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
685 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
686 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
687 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
688 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
689 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
690 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
691 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
692 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
693 default: return -EIO;
694 }
695}
696
697struct mlx5_ifc_mbox_out_bits {
698 u8 status[0x8];
699 u8 reserved_at_8[0x18];
700
701 u8 syndrome[0x20];
702
703 u8 reserved_at_40[0x40];
704};
705
706struct mlx5_ifc_mbox_in_bits {
707 u8 opcode[0x10];
fc6c391a 708 u8 uid[0x10];
c4f287c4
SM		 709
710 u8 reserved_at_20[0x10];
711 u8 op_mod[0x10];
712
713 u8 reserved_at_40[0x40];
714};
715
716void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
717{
718 *status = MLX5_GET(mbox_out, out, status);
719 *syndrome = MLX5_GET(mbox_out, out, syndrome);
720}
721
722static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
723{
724 u32 syndrome;
725 u8 status;
726 u16 opcode;
727 u16 op_mod;
fc6c391a 728 u16 uid;
c4f287c4
SM		 729
730 mlx5_cmd_mbox_status(out, &status, &syndrome);
731 if (!status)
732 return 0;
733
734 opcode = MLX5_GET(mbox_in, in, opcode);
735 op_mod = MLX5_GET(mbox_in, in, op_mod);
fc6c391a 736 uid = MLX5_GET(mbox_in, in, uid);
c4f287c4 737
fc6c391a 738 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
b30408d7
LR		 739 mlx5_core_err_rl(dev,
740 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
741 mlx5_command_str(opcode), opcode, op_mod,
742 cmd_status_str(status), status, syndrome);
fc6c391a
YH		 743 else
744 mlx5_core_dbg(dev,
c4f287c4
SM		 745 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
746 mlx5_command_str(opcode),
747 opcode, op_mod,
748 cmd_status_str(status),
749 status,
750 syndrome);
751
752 return cmd_status_to_err(status);
753}
754
e126ba97
EC		 755static void dump_command(struct mlx5_core_dev *dev,
756 struct mlx5_cmd_work_ent *ent, int input)
757{
e126ba97 758 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
c4f287c4 759 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
e126ba97 760 struct mlx5_cmd_mailbox *next = msg->next;
12b996d1 761 int n = mlx5_calc_cmd_blocks(msg);
e126ba97 762 int data_only;
f241e749 763 u32 offset = 0;
e126ba97 764 int dump_len;
12b996d1 765 int i;
e126ba97
EC		 766
767 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
768
769 if (data_only)
770 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
771 "dump command data %s(0x%x) %s\n",
772 mlx5_command_str(op), op,
773 input ? "INPUT" : "OUTPUT");
774 else
775 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
776 mlx5_command_str(op), op,
777 input ? "INPUT" : "OUTPUT");
778
779 if (data_only) {
780 if (input) {
781 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
782 offset += sizeof(ent->lay->in);
783 } else {
784 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
785 offset += sizeof(ent->lay->out);
786 }
787 } else {
788 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
789 offset += sizeof(*ent->lay);
790 }
791
12b996d1 792 for (i = 0; i < n && next; i++) {
e126ba97
EC		 793 if (data_only) {
794 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
795 dump_buf(next->buf, dump_len, 1, offset);
796 offset += MLX5_CMD_DATA_BLOCK_SIZE;
797 } else {
798 mlx5_core_dbg(dev, "command block:\n");
799 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
800 offset += sizeof(struct mlx5_cmd_prot_block);
801 }
802 next = next->next;
803 }
804
805 if (data_only)
806 pr_debug("\n");
807}
808
65ee6708
MHY		 809static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
810{
c4f287c4 811 return MLX5_GET(mbox_in, in->first.data, opcode);
65ee6708
MHY		 812}
813
71edc69c
SM		 814static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
815
65ee6708
MHY		 816static void cb_timeout_handler(struct work_struct *work)
817{
818 struct delayed_work *dwork = container_of(work, struct delayed_work,
819 work);
820 struct mlx5_cmd_work_ent *ent = container_of(dwork,
821 struct mlx5_cmd_work_ent,
822 cb_timeout_work);
823 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
824 cmd);
825
826 ent->ret = -ETIMEDOUT;
827 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
828 mlx5_command_str(msg_to_opcode(ent->in)),
829 msg_to_opcode(ent->in));
73dd3a48 830 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
65ee6708
MHY		 831}
832
219c81f7
MS		 833static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
834static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
835 struct mlx5_cmd_msg *msg);
836
e126ba97
EC		 837static void cmd_work_handler(struct work_struct *work)
838{
839 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
840 struct mlx5_cmd *cmd = ent->cmd;
841 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
65ee6708 842 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
e126ba97
EC		 843 struct mlx5_cmd_layout *lay;
844 struct semaphore *sem;
020446e0 845 unsigned long flags;
4525abea 846 bool poll_cmd = ent->polling;
219c81f7 847 int alloc_ret;
d412c31d 848 int cmd_mode;
4525abea 849
e126ba97
EC		 850 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
851 down(sem);
852 if (!ent->page_queue) {
219c81f7
MS		 853 alloc_ret = alloc_ent(cmd);
854 if (alloc_ret < 0) {
e126ba97 855 mlx5_core_err(dev, "failed to allocate command entry\n");
219c81f7
MS		 856 if (ent->callback) {
857 ent->callback(-EAGAIN, ent->context);
858 mlx5_free_cmd_msg(dev, ent->out);
859 free_msg(dev, ent->in);
860 free_cmd(ent);
861 } else {
862 ent->ret = -EAGAIN;
863 complete(&ent->done);
864 }
e126ba97
EC		 865 up(sem);
866 return;
867 }
219c81f7 868 ent->idx = alloc_ret;
e126ba97
EC		 869 } else {
870 ent->idx = cmd->max_reg_cmds;
020446e0
EC		 871 spin_lock_irqsave(&cmd->alloc_lock, flags);
872 clear_bit(ent->idx, &cmd->bitmask);
873 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
e126ba97
EC		 874 }
875
e126ba97 876 cmd->ent_arr[ent->idx] = ent;
73dd3a48 877 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
e126ba97
EC		 878 lay = get_inst(cmd, ent->idx);
879 ent->lay = lay;
880 memset(lay, 0, sizeof(*lay));
881 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
746b5583 882 ent->op = be32_to_cpu(lay->in[0]) >> 16;
e126ba97
EC		 883 if (ent->in->next)
884 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
885 lay->inlen = cpu_to_be32(ent->in->len);
886 if (ent->out->next)
887 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
888 lay->outlen = cpu_to_be32(ent->out->len);
889 lay->type = MLX5_PCI_CMD_XPORT;
890 lay->token = ent->token;
891 lay->status_own = CMD_OWNER_HW;
c1868b82 892 set_signature(ent, !cmd->checksum_disabled);
e126ba97 893 dump_command(dev, ent, 1);
14a70046 894 ent->ts1 = ktime_get_ns();
d412c31d 895 cmd_mode = cmd->mode;
e126ba97 896
65ee6708
MHY		 897 if (ent->callback)
898 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
899
73dd3a48
MHY		 900 /* Skip sending command to fw if internal error */
901 if (pci_channel_offline(dev->pdev) ||
902 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
903 u8 status = 0;
904 u32 drv_synd;
905
906 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
907 MLX5_SET(mbox_out, ent->out, status, status);
908 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
909
910 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
911 return;
912 }
913
e126ba97 914 /* ring doorbell after the descriptor is valid */
21db5074 915 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
e126ba97
EC		 916 wmb();
917 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
e126ba97 918 mmiowb();
21db5074 919 /* if not in polling don't use ent after this point */
d412c31d 920 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
e126ba97
EC		 921 poll_timeout(ent);
922 /* make sure we read the descriptor after ownership is SW */
923 rmb();
73dd3a48 924 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
e126ba97
EC		 925 }
926}
927
928static const char *deliv_status_to_str(u8 status)
929{
930 switch (status) {
931 case MLX5_CMD_DELIVERY_STAT_OK:
932 return "no errors";
933 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
934 return "signature error";
935 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
936 return "token error";
937 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
938 return "bad block number";
939 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
940 return "output pointer not aligned to block size";
941 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
942 return "input pointer not aligned to block size";
943 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
944 return "firmware internal error";
945 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
946 return "command input length error";
947 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
bd10838a 948 return "command output length error";
e126ba97
EC		 949 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
950 return "reserved fields not cleared";
951 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
952 return "bad command descriptor type";
953 default:
954 return "unknown status code";
955 }
956}
957
e126ba97
EC		 958static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
959{
960 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
961 struct mlx5_cmd *cmd = &dev->cmd;
962 int err;
963
4525abea 964 if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
e126ba97 965 wait_for_completion(&ent->done);
9cba4ebc
MHY		 966 } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
967 ent->ret = -ETIMEDOUT;
73dd3a48 968 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
e126ba97 969 }
9cba4ebc
MHY		 970
971 err = ent->ret;
972
e126ba97
EC		 973 if (err == -ETIMEDOUT) {
974 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
975 mlx5_command_str(msg_to_opcode(ent->in)),
976 msg_to_opcode(ent->in));
977 }
1a91de28
JP		 978 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
979 err, deliv_status_to_str(ent->status), ent->status);
e126ba97
EC		 980
981 return err;
982}
983
984/* Notes:
985 * 1. Callback functions may not sleep
986 * 2. page queue commands do not support asynchrous completion
987 */
988static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
746b5583
EC		 989 struct mlx5_cmd_msg *out, void *uout, int uout_size,
990 mlx5_cmd_cbk_t callback,
2c0f8ce1 991 void *context, int page_queue, u8 *status,
4525abea 992 u8 token, bool force_polling)
e126ba97
EC		 993{
994 struct mlx5_cmd *cmd = &dev->cmd;
995 struct mlx5_cmd_work_ent *ent;
e126ba97
EC		 996 struct mlx5_cmd_stats *stats;
997 int err = 0;
998 s64 ds;
999 u16 op;
1000
1001 if (callback && page_queue)
1002 return -EINVAL;
1003
746b5583
EC		 1004 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
1005 page_queue);
e126ba97
EC		 1006 if (IS_ERR(ent))
1007 return PTR_ERR(ent);
1008
2c0f8ce1 1009 ent->token = token;
4525abea 1010 ent->polling = force_polling;
2c0f8ce1 1011
e126ba97
EC		 1012 if (!callback)
1013 init_completion(&ent->done);
1014
65ee6708 1015 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
e126ba97
EC		 1016 INIT_WORK(&ent->work, cmd_work_handler);
1017 if (page_queue) {
1018 cmd_work_handler(&ent->work);
1019 } else if (!queue_work(cmd->wq, &ent->work)) {
1020 mlx5_core_warn(dev, "failed to queue work\n");
1021 err = -ENOMEM;
1022 goto out_free;
1023 }
1024
9cba4ebc
MHY		 1025 if (callback)
1026 goto out;
e126ba97 1027
9cba4ebc
MHY		 1028 err = wait_func(dev, ent);
1029 if (err == -ETIMEDOUT)
06187080 1030 goto out;
9cba4ebc
MHY		 1031
1032 ds = ent->ts2 - ent->ts1;
c4f287c4 1033 op = MLX5_GET(mbox_in, in->first.data, opcode);
9cba4ebc
MHY		 1034 if (op < ARRAY_SIZE(cmd->stats)) {
1035 stats = &cmd->stats[op];
1036 spin_lock_irq(&stats->lock);
1037 stats->sum += ds;
1038 ++stats->n;
1039 spin_unlock_irq(&stats->lock);
1040 }
1041 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1042 "fw exec time for %s is %lld nsec\n",
1043 mlx5_command_str(op), ds);
1044 *status = ent->status;
e126ba97
EC		 1045
1046out_free:
1047 free_cmd(ent);
1048out:
1049 return err;
1050}
1051
1052static ssize_t dbg_write(struct file *filp, const char __user *buf,
1053 size_t count, loff_t *pos)
1054{
1055 struct mlx5_core_dev *dev = filp->private_data;
1056 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1057 char lbuf[3];
1058 int err;
1059
1060 if (!dbg->in_msg || !dbg->out_msg)
1061 return -ENOMEM;
1062
31e33a5b
JH		 1063 if (count < sizeof(lbuf) - 1)
1064 return -EINVAL;
1065
1066 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
5e631a03 1067 return -EFAULT;
e126ba97
EC		 1068
1069 lbuf[sizeof(lbuf) - 1] = 0;
1070
1071 if (strcmp(lbuf, "go"))
1072 return -EINVAL;
1073
1074 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1075
1076 return err ? err : count;
1077}
1078
e126ba97
EC		 1079static const struct file_operations fops = {
1080 .owner = THIS_MODULE,
1081 .open = simple_open,
1082 .write = dbg_write,
1083};
1084
2c0f8ce1
PB		 1085static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1086 u8 token)
e126ba97
EC		 1087{
1088 struct mlx5_cmd_prot_block *block;
1089 struct mlx5_cmd_mailbox *next;
1090 int copy;
1091
1092 if (!to || !from)
1093 return -ENOMEM;
1094
1095 copy = min_t(int, size, sizeof(to->first.data));
1096 memcpy(to->first.data, from, copy);
1097 size -= copy;
1098 from += copy;
1099
1100 next = to->next;
1101 while (size) {
1102 if (!next) {
1103 /* this is a BUG */
1104 return -ENOMEM;
1105 }
1106
1107 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1108 block = next->buf;
1109 memcpy(block->data, from, copy);
1110 from += copy;
1111 size -= copy;
2c0f8ce1 1112 block->token = token;
e126ba97
EC		 1113 next = next->next;
1114 }
1115
1116 return 0;
1117}
1118
1119static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1120{
1121 struct mlx5_cmd_prot_block *block;
1122 struct mlx5_cmd_mailbox *next;
1123 int copy;
1124
1125 if (!to || !from)
1126 return -ENOMEM;
1127
1128 copy = min_t(int, size, sizeof(from->first.data));
1129 memcpy(to, from->first.data, copy);
1130 size -= copy;
1131 to += copy;
1132
1133 next = from->next;
1134 while (size) {
1135 if (!next) {
1136 /* this is a BUG */
1137 return -ENOMEM;
1138 }
1139
1140 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1141 block = next->buf;
e126ba97
EC		 1142
1143 memcpy(to, block->data, copy);
1144 to += copy;
1145 size -= copy;
1146 next = next->next;
1147 }
1148
1149 return 0;
1150}
1151
1152static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1153 gfp_t flags)
1154{
1155 struct mlx5_cmd_mailbox *mailbox;
1156
1157 mailbox = kmalloc(sizeof(*mailbox), flags);
1158 if (!mailbox)
1159 return ERR_PTR(-ENOMEM);
1160
18c90df9 1161 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
fec668d3 1162 &mailbox->dma);
e126ba97
EC		 1163 if (!mailbox->buf) {
1164 mlx5_core_dbg(dev, "failed allocation\n");
1165 kfree(mailbox);
1166 return ERR_PTR(-ENOMEM);
1167 }
e126ba97
EC		 1168 mailbox->next = NULL;
1169
1170 return mailbox;
1171}
1172
1173static void free_cmd_box(struct mlx5_core_dev *dev,
1174 struct mlx5_cmd_mailbox *mailbox)
1175{
18c90df9 1176 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
e126ba97
EC		 1177 kfree(mailbox);
1178}
1179
1180static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
2c0f8ce1
PB		 1181 gfp_t flags, int size,
1182 u8 token)
e126ba97
EC		 1183{
1184 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1185 struct mlx5_cmd_prot_block *block;
1186 struct mlx5_cmd_msg *msg;
e126ba97
EC		 1187 int err;
1188 int n;
1189 int i;
1190
746b5583 1191 msg = kzalloc(sizeof(*msg), flags);
e126ba97
EC		 1192 if (!msg)
1193 return ERR_PTR(-ENOMEM);
1194
ed644fab
MS		 1195 msg->len = size;
1196 n = mlx5_calc_cmd_blocks(msg);
e126ba97
EC		 1197
1198 for (i = 0; i < n; i++) {
1199 tmp = alloc_cmd_box(dev, flags);
1200 if (IS_ERR(tmp)) {
1201 mlx5_core_warn(dev, "failed allocating block\n");
1202 err = PTR_ERR(tmp);
1203 goto err_alloc;
1204 }
1205
1206 block = tmp->buf;
1207 tmp->next = head;
1208 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1209 block->block_num = cpu_to_be32(n - i - 1);
2c0f8ce1 1210 block->token = token;
e126ba97
EC		 1211 head = tmp;
1212 }
1213 msg->next = head;
e126ba97
EC		 1214 return msg;
1215
1216err_alloc:
1217 while (head) {
1218 tmp = head->next;
1219 free_cmd_box(dev, head);
1220 head = tmp;
1221 }
1222 kfree(msg);
1223
1224 return ERR_PTR(err);
1225}
1226
1227static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
e53eef63 1228 struct mlx5_cmd_msg *msg)
e126ba97
EC		 1229{
1230 struct mlx5_cmd_mailbox *head = msg->next;
1231 struct mlx5_cmd_mailbox *next;
1232
1233 while (head) {
1234 next = head->next;
1235 free_cmd_box(dev, head);
1236 head = next;
1237 }
1238 kfree(msg);
1239}
1240
1241static ssize_t data_write(struct file *filp, const char __user *buf,
1242 size_t count, loff_t *pos)
1243{
1244 struct mlx5_core_dev *dev = filp->private_data;
1245 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1246 void *ptr;
e126ba97
EC		 1247
1248 if (*pos != 0)
1249 return -EINVAL;
1250
1251 kfree(dbg->in_msg);
1252 dbg->in_msg = NULL;
1253 dbg->inlen = 0;
6f0b826d
ME		 1254 ptr = memdup_user(buf, count);
1255 if (IS_ERR(ptr))
1256 return PTR_ERR(ptr);
e126ba97
EC		 1257 dbg->in_msg = ptr;
1258 dbg->inlen = count;
1259
1260 *pos = count;
1261
1262 return count;
e126ba97
EC		 1263}
1264
1265static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1266 loff_t *pos)
1267{
1268 struct mlx5_core_dev *dev = filp->private_data;
1269 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
e126ba97
EC		 1270
1271 if (!dbg->out_msg)
1272 return -ENOMEM;
1273
31e33a5b
JH		 1274 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1275 dbg->outlen);
e126ba97
EC		 1276}
1277
1278static const struct file_operations dfops = {
1279 .owner = THIS_MODULE,
1280 .open = simple_open,
1281 .write = data_write,
1282 .read = data_read,
1283};
1284
1285static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1286 loff_t *pos)
1287{
1288 struct mlx5_core_dev *dev = filp->private_data;
1289 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1290 char outlen[8];
1291 int err;
1292
e126ba97
EC		 1293 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1294 if (err < 0)
1295 return err;
1296
31e33a5b 1297 return simple_read_from_buffer(buf, count, pos, outlen, err);
e126ba97
EC		 1298}
1299
1300static ssize_t outlen_write(struct file *filp, const char __user *buf,
1301 size_t count, loff_t *pos)
1302{
1303 struct mlx5_core_dev *dev = filp->private_data;
1304 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
603b7bcf 1305 char outlen_str[8] = {0};
e126ba97
EC		 1306 int outlen;
1307 void *ptr;
1308 int err;
1309
1310 if (*pos != 0 || count > 6)
1311 return -EINVAL;
1312
1313 kfree(dbg->out_msg);
1314 dbg->out_msg = NULL;
1315 dbg->outlen = 0;
1316
1317 if (copy_from_user(outlen_str, buf, count))
5e631a03 1318 return -EFAULT;
e126ba97 1319
e126ba97
EC		 1320 err = sscanf(outlen_str, "%d", &outlen);
1321 if (err < 0)
1322 return err;
1323
1324 ptr = kzalloc(outlen, GFP_KERNEL);
1325 if (!ptr)
1326 return -ENOMEM;
1327
1328 dbg->out_msg = ptr;
1329 dbg->outlen = outlen;
1330
1331 *pos = count;
1332
1333 return count;
1334}
1335
1336static const struct file_operations olfops = {
1337 .owner = THIS_MODULE,
1338 .open = simple_open,
1339 .write = outlen_write,
1340 .read = outlen_read,
1341};
1342
1343static void set_wqname(struct mlx5_core_dev *dev)
1344{
1345 struct mlx5_cmd *cmd = &dev->cmd;
1346
1347 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1348 dev_name(&dev->pdev->dev));
1349}
1350
1351static void clean_debug_files(struct mlx5_core_dev *dev)
1352{
1353 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1354
1355 if (!mlx5_debugfs_root)
1356 return;
1357
1358 mlx5_cmdif_debugfs_cleanup(dev);
1359 debugfs_remove_recursive(dbg->dbg_root);
1360}
1361
1362static int create_debugfs_files(struct mlx5_core_dev *dev)
1363{
1364 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1365 int err = -ENOMEM;
1366
1367 if (!mlx5_debugfs_root)
1368 return 0;
1369
1370 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1371 if (!dbg->dbg_root)
1372 return err;
1373
1374 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1375 dev, &dfops);
1376 if (!dbg->dbg_in)
1377 goto err_dbg;
1378
1379 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1380 dev, &dfops);
1381 if (!dbg->dbg_out)
1382 goto err_dbg;
1383
1384 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1385 dev, &olfops);
1386 if (!dbg->dbg_outlen)
1387 goto err_dbg;
1388
1389 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1390 &dbg->status);
1391 if (!dbg->dbg_status)
1392 goto err_dbg;
1393
1394 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1395 if (!dbg->dbg_run)
1396 goto err_dbg;
1397
1398 mlx5_cmdif_debugfs_init(dev);
1399
1400 return 0;
1401
1402err_dbg:
1403 clean_debug_files(dev);
1404 return err;
1405}
1406
9cba4ebc 1407static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
e126ba97
EC		 1408{
1409 struct mlx5_cmd *cmd = &dev->cmd;
1410 int i;
1411
1412 for (i = 0; i < cmd->max_reg_cmds; i++)
1413 down(&cmd->sem);
e126ba97
EC		 1414 down(&cmd->pages_sem);
1415
9cba4ebc 1416 cmd->mode = mode;
e126ba97
EC		 1417
1418 up(&cmd->pages_sem);
1419 for (i = 0; i < cmd->max_reg_cmds; i++)
1420 up(&cmd->sem);
1421}
1422
71edc69c
SM		 1423static int cmd_comp_notifier(struct notifier_block *nb,
1424 unsigned long type, void *data)
1425{
1426 struct mlx5_core_dev *dev;
1427 struct mlx5_cmd *cmd;
1428 struct mlx5_eqe *eqe;
1429
1430 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1431 dev = container_of(cmd, struct mlx5_core_dev, cmd);
1432 eqe = data;
1433
1434 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1435
1436 return NOTIFY_OK;
1437}
9cba4ebc 1438void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
e126ba97 1439{
71edc69c
SM		 1440 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1441 mlx5_eq_notifier_register(dev, &dev->cmd.nb);
9cba4ebc
MHY		 1442 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1443}
e126ba97 1444
9cba4ebc
MHY		 1445void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1446{
1447 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
71edc69c 1448 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
e126ba97
EC		 1449}
1450
746b5583
EC		 1451static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1452{
1453 unsigned long flags;
1454
0ac3ea70
MHY		 1455 if (msg->parent) {
1456 spin_lock_irqsave(&msg->parent->lock, flags);
1457 list_add_tail(&msg->list, &msg->parent->head);
1458 spin_unlock_irqrestore(&msg->parent->lock, flags);
746b5583
EC		 1459 } else {
1460 mlx5_free_cmd_msg(dev, msg);
1461 }
1462}
1463
71edc69c 1464static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
e126ba97
EC		 1465{
1466 struct mlx5_cmd *cmd = &dev->cmd;
1467 struct mlx5_cmd_work_ent *ent;
1468 mlx5_cmd_cbk_t callback;
1469 void *context;
1470 int err;
1471 int i;
746b5583
EC		 1472 s64 ds;
1473 struct mlx5_cmd_stats *stats;
1474 unsigned long flags;
020446e0 1475 unsigned long vector;
e126ba97 1476
020446e0
EC		 1477 /* there can be at most 32 command queues */
1478 vector = vec & 0xffffffff;
e126ba97
EC		 1479 for (i = 0; i < (1 << cmd->log_sz); i++) {
1480 if (test_bit(i, &vector)) {
11940c87
DC		 1481 struct semaphore *sem;
1482
e126ba97 1483 ent = cmd->ent_arr[i];
73dd3a48
MHY		 1484
1485 /* if we already completed the command, ignore it */
1486 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1487 &ent->state)) {
1488 /* only real completion can free the cmd slot */
1489 if (!forced) {
1490 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1491 ent->idx);
1492 free_ent(cmd, ent->idx);
06187080 1493 free_cmd(ent);
73dd3a48
MHY		 1494 }
1495 continue;
1496 }
1497
65ee6708
MHY		 1498 if (ent->callback)
1499 cancel_delayed_work(&ent->cb_timeout_work);
11940c87
DC		 1500 if (ent->page_queue)
1501 sem = &cmd->pages_sem;
1502 else
1503 sem = &cmd->sem;
14a70046 1504 ent->ts2 = ktime_get_ns();
e126ba97
EC		 1505 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1506 dump_command(dev, ent, 0);
1507 if (!ent->ret) {
1508 if (!cmd->checksum_disabled)
1509 ent->ret = verify_signature(ent);
1510 else
1511 ent->ret = 0;
020446e0
EC		 1512 if (vec & MLX5_TRIGGERED_CMD_COMP)
1513 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1514 else
1515 ent->status = ent->lay->status_own >> 1;
1516
e126ba97
EC		 1517 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1518 ent->ret, deliv_status_to_str(ent->status), ent->status);
1519 }
73dd3a48
MHY		 1520
1521 /* only real completion will free the entry slot */
1522 if (!forced)
1523 free_ent(cmd, ent->idx);
020446e0 1524
e126ba97 1525 if (ent->callback) {
14a70046 1526 ds = ent->ts2 - ent->ts1;
746b5583
EC		 1527 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1528 stats = &cmd->stats[ent->op];
1529 spin_lock_irqsave(&stats->lock, flags);
1530 stats->sum += ds;
1531 ++stats->n;
1532 spin_unlock_irqrestore(&stats->lock, flags);
1533 }
1534
e126ba97
EC		 1535 callback = ent->callback;
1536 context = ent->context;
1537 err = ent->ret;
ec22eb53 1538 if (!err) {
746b5583
EC		 1539 err = mlx5_copy_from_msg(ent->uout,
1540 ent->out,
1541 ent->uout_size);
1542
c4f287c4
SM		 1543 err = err ? err : mlx5_cmd_check(dev,
1544 ent->in->first.data,
1545 ent->uout);
ec22eb53 1546 }
746b5583
EC		 1547
1548 mlx5_free_cmd_msg(dev, ent->out);
1549 free_msg(dev, ent->in);
1550
be87544d 1551 err = err ? err : ent->status;
06187080
MS		 1552 if (!forced)
1553 free_cmd(ent);
e126ba97
EC		 1554 callback(err, context);
1555 } else {
1556 complete(&ent->done);
1557 }
11940c87 1558 up(sem);
e126ba97
EC		 1559 }
1560 }
1561}
71edc69c
SM		 1562
1563void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1564{
1565 unsigned long flags;
1566 u64 vector;
1567
1568 /* wait for pending handlers to complete */
1569 mlx5_eq_synchronize_cmd_irq(dev);
1570 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1571 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
1572 if (!vector)
1573 goto no_trig;
1574
1575 vector |= MLX5_TRIGGERED_CMD_COMP;
1576 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1577
1578 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1579 mlx5_cmd_comp_handler(dev, vector, true);
1580 return;
1581
1582no_trig:
1583 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1584}
e126ba97 1585
4cab346b
HN		 1586void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1587{
1588 struct mlx5_cmd *cmd = &dev->cmd;
1589 int i;
1590
1591 for (i = 0; i < cmd->max_reg_cmds; i++)
1592 while (down_trylock(&cmd->sem))
1593 mlx5_cmd_trigger_completions(dev);
1594
1595 while (down_trylock(&cmd->pages_sem))
1596 mlx5_cmd_trigger_completions(dev);
1597
1598 /* Unlock cmdif */
1599 up(&cmd->pages_sem);
1600 for (i = 0; i < cmd->max_reg_cmds; i++)
1601 up(&cmd->sem);
1602}
1603
e126ba97
EC		 1604static int status_to_err(u8 status)
1605{
1606 return status ? -1 : 0; /* TBD more meaningful codes */
1607}
1608
746b5583
EC		 1609static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1610 gfp_t gfp)
e126ba97
EC		 1611{
1612 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
0ac3ea70 1613 struct cmd_msg_cache *ch = NULL;
e126ba97 1614 struct mlx5_cmd *cmd = &dev->cmd;
0ac3ea70
MHY		 1615 int i;
1616
1617 if (in_size <= 16)
1618 goto cache_miss;
1619
1620 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1621 ch = &cmd->cache[i];
1622 if (in_size > ch->max_inbox_size)
1623 continue;
1624 spin_lock_irq(&ch->lock);
1625 if (list_empty(&ch->head)) {
1626 spin_unlock_irq(&ch->lock);
1627 continue;
e126ba97 1628 }
0ac3ea70
MHY		 1629 msg = list_entry(ch->head.next, typeof(*msg), list);
1630 /* For cached lists, we must explicitly state what is
1631 * the real size
1632 */
1633 msg->len = in_size;
1634 list_del(&msg->list);
1635 spin_unlock_irq(&ch->lock);
1636 break;
e126ba97
EC		 1637 }
1638
0ac3ea70
MHY		 1639 if (!IS_ERR(msg))
1640 return msg;
e126ba97 1641
0ac3ea70
MHY		 1642cache_miss:
1643 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
e126ba97
EC		 1644 return msg;
1645}
1646
c4f287c4 1647static int is_manage_pages(void *in)
e126ba97 1648{
c4f287c4 1649 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
e126ba97
EC		 1650}
1651
746b5583 1652static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
4525abea
MD		 1653 int out_size, mlx5_cmd_cbk_t callback, void *context,
1654 bool force_polling)
e126ba97
EC		 1655{
1656 struct mlx5_cmd_msg *inb;
1657 struct mlx5_cmd_msg *outb;
1658 int pages_queue;
746b5583 1659 gfp_t gfp;
e126ba97
EC		 1660 int err;
1661 u8 status = 0;
89d44f0a 1662 u32 drv_synd;
2c0f8ce1 1663 u8 token;
89d44f0a
MD		 1664
1665 if (pci_channel_offline(dev->pdev) ||
1666 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
c4f287c4
SM		 1667 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1668
1669 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1670 MLX5_SET(mbox_out, out, status, status);
1671 MLX5_SET(mbox_out, out, syndrome, drv_synd);
89d44f0a
MD		 1672 return err;
1673 }
e126ba97
EC		 1674
1675 pages_queue = is_manage_pages(in);
746b5583 1676 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
e126ba97 1677
746b5583 1678 inb = alloc_msg(dev, in_size, gfp);
e126ba97
EC		 1679 if (IS_ERR(inb)) {
1680 err = PTR_ERR(inb);
1681 return err;
1682 }
1683
2c0f8ce1
PB		 1684 token = alloc_token(&dev->cmd);
1685
1686 err = mlx5_copy_to_msg(inb, in, in_size, token);
e126ba97
EC		 1687 if (err) {
1688 mlx5_core_warn(dev, "err %d\n", err);
1689 goto out_in;
1690 }
1691
2c0f8ce1 1692 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
e126ba97
EC		 1693 if (IS_ERR(outb)) {
1694 err = PTR_ERR(outb);
1695 goto out_in;
1696 }
1697
746b5583 1698 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
4525abea 1699 pages_queue, &status, token, force_polling);
e126ba97
EC		 1700 if (err)
1701 goto out_out;
1702
1703 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1704 if (status) {
1705 err = status_to_err(status);
1706 goto out_out;
1707 }
1708
05e4ecd1
EC		 1709 if (!callback)
1710 err = mlx5_copy_from_msg(out, outb, out_size);
e126ba97
EC		 1711
1712out_out:
746b5583
EC		 1713 if (!callback)
1714 mlx5_free_cmd_msg(dev, outb);
e126ba97
EC		 1715
1716out_in:
746b5583
EC		 1717 if (!callback)
1718 free_msg(dev, inb);
e126ba97
EC		 1719 return err;
1720}
746b5583
EC		 1721
1722int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1723 int out_size)
1724{
c4f287c4
SM		 1725 int err;
1726
4525abea 1727 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
c4f287c4 1728 return err ? : mlx5_cmd_check(dev, in, out);
746b5583 1729}
e126ba97
EC		 1730EXPORT_SYMBOL(mlx5_cmd_exec);
1731
746b5583
EC		 1732int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1733 void *out, int out_size, mlx5_cmd_cbk_t callback,
1734 void *context)
1735{
4525abea
MD		 1736 return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1737 false);
746b5583
EC		 1738}
1739EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1740
4525abea
MD		 1741int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1742 void *out, int out_size)
1743{
1744 int err;
1745
1746 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1747
1748 return err ? : mlx5_cmd_check(dev, in, out);
1749}
1750EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1751
e126ba97
EC		 1752static void destroy_msg_cache(struct mlx5_core_dev *dev)
1753{
0ac3ea70 1754 struct cmd_msg_cache *ch;
e126ba97
EC		 1755 struct mlx5_cmd_msg *msg;
1756 struct mlx5_cmd_msg *n;
0ac3ea70 1757 int i;
e126ba97 1758
0ac3ea70
MHY		 1759 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1760 ch = &dev->cmd.cache[i];
1761 list_for_each_entry_safe(msg, n, &ch->head, list) {
1762 list_del(&msg->list);
1763 mlx5_free_cmd_msg(dev, msg);
1764 }
e126ba97
EC		 1765 }
1766}
1767
0ac3ea70
MHY		 1768static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1769 512, 32, 16, 8, 2
1770};
1771
1772static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1773 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1774 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1775 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1776 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1777 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1778};
1779
1780static void create_msg_cache(struct mlx5_core_dev *dev)
e126ba97
EC		 1781{
1782 struct mlx5_cmd *cmd = &dev->cmd;
0ac3ea70 1783 struct cmd_msg_cache *ch;
e126ba97 1784 struct mlx5_cmd_msg *msg;
e126ba97 1785 int i;
0ac3ea70
MHY		 1786 int k;
1787
1788 /* Initialize and fill the caches with initial entries */
1789 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1790 ch = &cmd->cache[k];
1791 spin_lock_init(&ch->lock);
1792 INIT_LIST_HEAD(&ch->head);
1793 ch->num_ent = cmd_cache_num_ent[k];
1794 ch->max_inbox_size = cmd_cache_ent_size[k];
1795 for (i = 0; i < ch->num_ent; i++) {
1796 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1797 ch->max_inbox_size, 0);
1798 if (IS_ERR(msg))
1799 break;
1800 msg->parent = ch;
1801 list_add_tail(&msg->list, &ch->head);
e126ba97 1802 }
e126ba97 1803 }
e126ba97
EC		 1804}
1805
64599cca
EC		 1806static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1807{
1808 struct device *ddev = &dev->pdev->dev;
1809
750afb08
LC		 1810 cmd->cmd_alloc_buf = dma_alloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1811 &cmd->alloc_dma, GFP_KERNEL);
64599cca
EC		 1812 if (!cmd->cmd_alloc_buf)
1813 return -ENOMEM;
1814
1815 /* make sure it is aligned to 4K */
1816 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1817 cmd->cmd_buf = cmd->cmd_alloc_buf;
1818 cmd->dma = cmd->alloc_dma;
1819 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1820 return 0;
1821 }
1822
1823 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1824 cmd->alloc_dma);
750afb08
LC		 1825 cmd->cmd_alloc_buf = dma_alloc_coherent(ddev,
1826 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1827 &cmd->alloc_dma, GFP_KERNEL);
64599cca
EC		 1828 if (!cmd->cmd_alloc_buf)
1829 return -ENOMEM;
1830
1831 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1832 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1833 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1834 return 0;
1835}
1836
1837static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1838{
1839 struct device *ddev = &dev->pdev->dev;
1840
1841 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1842 cmd->alloc_dma);
1843}
1844
e126ba97
EC		 1845int mlx5_cmd_init(struct mlx5_core_dev *dev)
1846{
1847 int size = sizeof(struct mlx5_cmd_prot_block);
1848 int align = roundup_pow_of_two(size);
1849 struct mlx5_cmd *cmd = &dev->cmd;
1850 u32 cmd_h, cmd_l;
1851 u16 cmd_if_rev;
1852 int err;
1853 int i;
1854
a31208b1 1855 memset(cmd, 0, sizeof(*cmd));
e126ba97
EC		 1856 cmd_if_rev = cmdif_rev(dev);
1857 if (cmd_if_rev != CMD_IF_REV) {
1858 dev_err(&dev->pdev->dev,
1859 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1860 CMD_IF_REV, cmd_if_rev);
1861 return -EINVAL;
1862 }
1863
18c90df9
RP		 1864 cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1865 0);
e126ba97
EC		 1866 if (!cmd->pool)
1867 return -ENOMEM;
1868
64599cca
EC		 1869 err = alloc_cmd_page(dev, cmd);
1870 if (err)
e126ba97 1871 goto err_free_pool;
e126ba97
EC		 1872
1873 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1874 cmd->log_sz = cmd_l >> 4 & 0xf;
1875 cmd->log_stride = cmd_l & 0xf;
1876 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1877 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1878 1 << cmd->log_sz);
1879 err = -EINVAL;
64599cca 1880 goto err_free_page;
e126ba97
EC		 1881 }
1882
2d446d18 1883 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
e126ba97
EC		 1884 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1885 err = -EINVAL;
64599cca 1886 goto err_free_page;
e126ba97
EC		 1887 }
1888
c1868b82 1889 cmd->checksum_disabled = 1;
e126ba97 1890 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
957f6ba8 1891 cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
e126ba97
EC		 1892
1893 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1894 if (cmd->cmdif_rev > CMD_IF_REV) {
1895 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1896 CMD_IF_REV, cmd->cmdif_rev);
9eb78923 1897 err = -EOPNOTSUPP;
64599cca 1898 goto err_free_page;
e126ba97
EC		 1899 }
1900
1901 spin_lock_init(&cmd->alloc_lock);
1902 spin_lock_init(&cmd->token_lock);
1903 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1904 spin_lock_init(&cmd->stats[i].lock);
1905
1906 sema_init(&cmd->sem, cmd->max_reg_cmds);
1907 sema_init(&cmd->pages_sem, 1);
1908
1909 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1910 cmd_l = (u32)(cmd->dma);
1911 if (cmd_l & 0xfff) {
1912 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1913 err = -ENOMEM;
64599cca 1914 goto err_free_page;
e126ba97
EC		 1915 }
1916
1917 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1918 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1919
1920 /* Make sure firmware sees the complete address before we proceed */
1921 wmb();
1922
1923 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1924
1925 cmd->mode = CMD_MODE_POLLING;
1926
0ac3ea70 1927 create_msg_cache(dev);
e126ba97
EC		 1928
1929 set_wqname(dev);
1930 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1931 if (!cmd->wq) {
1932 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1933 err = -ENOMEM;
1934 goto err_cache;
1935 }
1936
1937 err = create_debugfs_files(dev);
1938 if (err) {
1939 err = -ENOMEM;
1940 goto err_wq;
1941 }
1942
1943 return 0;
1944
1945err_wq:
1946 destroy_workqueue(cmd->wq);
1947
1948err_cache:
1949 destroy_msg_cache(dev);
1950
64599cca
EC		 1951err_free_page:
1952 free_cmd_page(dev, cmd);
e126ba97
EC		 1953
1954err_free_pool:
18c90df9 1955 dma_pool_destroy(cmd->pool);
e126ba97
EC		 1956
1957 return err;
1958}
1959EXPORT_SYMBOL(mlx5_cmd_init);
1960
1961void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1962{
1963 struct mlx5_cmd *cmd = &dev->cmd;
1964
1965 clean_debug_files(dev);
1966 destroy_workqueue(cmd->wq);
1967 destroy_msg_cache(dev);
64599cca 1968 free_cmd_page(dev, cmd);
18c90df9 1969 dma_pool_destroy(cmd->pool);
e126ba97
EC		 1970}
1971EXPORT_SYMBOL(mlx5_cmd_cleanup);
A mirror of Linus' kernel repository