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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
f62b8bb8 | 47 | #include "wq.h" |
f62b8bb8 | 48 | #include "mlx5_core.h" |
9218b44d | 49 | #include "en_stats.h" |
f62b8bb8 AV |
50 | |
51 | #define MLX5E_MAX_NUM_TC 8 | |
52 | ||
e842b100 | 53 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
54 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
55 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
56 | ||
e842b100 | 57 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
58 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
59 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
60 | ||
461017cb TT |
61 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
62 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4 | |
63 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 | |
64 | ||
65 | #define MLX5_MPWRQ_LOG_NUM_STRIDES 11 /* >= 9, HW restriction */ | |
66 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ | |
67 | #define MLX5_MPWRQ_NUM_STRIDES BIT(MLX5_MPWRQ_LOG_NUM_STRIDES) | |
68 | #define MLX5_MPWRQ_STRIDE_SIZE BIT(MLX5_MPWRQ_LOG_STRIDE_SIZE) | |
69 | #define MLX5_MPWRQ_LOG_WQE_SZ (MLX5_MPWRQ_LOG_NUM_STRIDES +\ | |
70 | MLX5_MPWRQ_LOG_STRIDE_SIZE) | |
71 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ | |
72 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
73 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
74 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
75 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
bc77b240 TT |
76 | #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \ |
77 | BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW)) | |
78 | #define MLX5_UMR_ALIGN (2048) | |
461017cb TT |
79 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
80 | ||
d9a40271 | 81 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 AV |
82 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
83 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
84 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
85 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
86 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 87 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 88 | |
936896e9 AS |
89 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
90 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
91 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
f62b8bb8 AV |
92 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
93 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 94 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 95 | |
86d722ad | 96 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 97 | |
461017cb TT |
98 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
99 | { | |
100 | switch (wq_type) { | |
101 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
102 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
103 | wq_size / 2); | |
104 | default: | |
105 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
106 | wq_size / 2); | |
107 | } | |
108 | } | |
109 | ||
110 | static inline int mlx5_min_log_rq_size(int wq_type) | |
111 | { | |
112 | switch (wq_type) { | |
113 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
114 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
115 | default: | |
116 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
117 | } | |
118 | } | |
119 | ||
120 | static inline int mlx5_max_log_rq_size(int wq_type) | |
121 | { | |
122 | switch (wq_type) { | |
123 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
124 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
125 | default: | |
126 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
127 | } | |
128 | } | |
129 | ||
2f48af12 TT |
130 | struct mlx5e_tx_wqe { |
131 | struct mlx5_wqe_ctrl_seg ctrl; | |
132 | struct mlx5_wqe_eth_seg eth; | |
133 | }; | |
134 | ||
135 | struct mlx5e_rx_wqe { | |
136 | struct mlx5_wqe_srq_next_seg next; | |
137 | struct mlx5_wqe_data_seg data; | |
138 | }; | |
86d722ad | 139 | |
bc77b240 TT |
140 | struct mlx5e_umr_wqe { |
141 | struct mlx5_wqe_ctrl_seg ctrl; | |
142 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
143 | struct mlx5_mkey_seg mkc; | |
144 | struct mlx5_wqe_data_seg data; | |
145 | }; | |
146 | ||
08fb1dac SM |
147 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
148 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
149 | #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */ | |
150 | #endif | |
151 | ||
f62b8bb8 AV |
152 | struct mlx5e_params { |
153 | u8 log_sq_size; | |
461017cb | 154 | u8 rq_wq_type; |
f62b8bb8 AV |
155 | u8 log_rq_size; |
156 | u16 num_channels; | |
f62b8bb8 AV |
157 | u8 num_tc; |
158 | u16 rx_cq_moderation_usec; | |
159 | u16 rx_cq_moderation_pkts; | |
160 | u16 tx_cq_moderation_usec; | |
161 | u16 tx_cq_moderation_pkts; | |
162 | u16 min_rx_wqes; | |
f62b8bb8 AV |
163 | bool lro_en; |
164 | u32 lro_wqe_sz; | |
58d52291 | 165 | u16 tx_max_inline; |
2d75b2bc AS |
166 | u8 rss_hfunc; |
167 | u8 toeplitz_hash_key[40]; | |
168 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 169 | bool vlan_strip_disable; |
08fb1dac SM |
170 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
171 | struct ieee_ets ets; | |
172 | #endif | |
f62b8bb8 AV |
173 | }; |
174 | ||
ef9814de EBE |
175 | struct mlx5e_tstamp { |
176 | rwlock_t lock; | |
177 | struct cyclecounter cycles; | |
178 | struct timecounter clock; | |
179 | struct hwtstamp_config hwtstamp_config; | |
180 | u32 nominal_c_mult; | |
181 | unsigned long overflow_period; | |
182 | struct delayed_work overflow_work; | |
183 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
184 | struct ptp_clock *ptp; |
185 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
186 | }; |
187 | ||
f62b8bb8 AV |
188 | enum { |
189 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
bc77b240 | 190 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
f62b8bb8 AV |
191 | }; |
192 | ||
f62b8bb8 AV |
193 | struct mlx5e_cq { |
194 | /* data path - accessed per cqe */ | |
195 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
196 | |
197 | /* data path - accessed per napi poll */ | |
198 | struct napi_struct *napi; | |
199 | struct mlx5_core_cq mcq; | |
200 | struct mlx5e_channel *channel; | |
50cfa25a | 201 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
202 | |
203 | /* control */ | |
204 | struct mlx5_wq_ctrl wq_ctrl; | |
205 | } ____cacheline_aligned_in_smp; | |
206 | ||
2f48af12 TT |
207 | struct mlx5e_rq; |
208 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
209 | struct mlx5_cqe64 *cqe); | |
210 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
211 | u16 ix); | |
212 | ||
461017cb TT |
213 | struct mlx5e_dma_info { |
214 | struct page *page; | |
215 | dma_addr_t addr; | |
216 | }; | |
217 | ||
f62b8bb8 AV |
218 | struct mlx5e_rq { |
219 | /* data path */ | |
220 | struct mlx5_wq_ll wq; | |
221 | u32 wqe_sz; | |
222 | struct sk_buff **skb; | |
461017cb | 223 | struct mlx5e_mpw_info *wqe_info; |
bc77b240 TT |
224 | __be32 mkey_be; |
225 | __be32 umr_mkey_be; | |
f62b8bb8 AV |
226 | |
227 | struct device *pdev; | |
228 | struct net_device *netdev; | |
ef9814de | 229 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
230 | struct mlx5e_rq_stats stats; |
231 | struct mlx5e_cq cq; | |
2f48af12 TT |
232 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
233 | mlx5e_fp_alloc_wqe alloc_wqe; | |
f62b8bb8 AV |
234 | |
235 | unsigned long state; | |
236 | int ix; | |
237 | ||
238 | /* control */ | |
239 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 240 | u8 wq_type; |
f62b8bb8 AV |
241 | u32 rqn; |
242 | struct mlx5e_channel *channel; | |
50cfa25a | 243 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
244 | } ____cacheline_aligned_in_smp; |
245 | ||
bc77b240 TT |
246 | struct mlx5e_umr_dma_info { |
247 | __be64 *mtt; | |
248 | __be64 *mtt_no_align; | |
249 | dma_addr_t mtt_addr; | |
250 | struct mlx5e_dma_info *dma_info; | |
251 | }; | |
252 | ||
253 | struct mlx5e_mpw_info { | |
254 | union { | |
255 | struct mlx5e_dma_info dma_info; | |
256 | struct mlx5e_umr_dma_info umr; | |
257 | }; | |
258 | u16 consumed_strides; | |
259 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
260 | ||
261 | void (*dma_pre_sync)(struct device *pdev, | |
262 | struct mlx5e_mpw_info *wi, | |
263 | u32 wqe_offset, u32 len); | |
264 | void (*add_skb_frag)(struct device *pdev, | |
265 | struct sk_buff *skb, | |
266 | struct mlx5e_mpw_info *wi, | |
267 | u32 page_idx, u32 frag_offset, u32 len); | |
268 | void (*copy_skb_header)(struct device *pdev, | |
269 | struct sk_buff *skb, | |
270 | struct mlx5e_mpw_info *wi, | |
271 | u32 page_idx, u32 offset, | |
272 | u32 headlen); | |
273 | void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
274 | }; | |
275 | ||
34802a42 | 276 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
277 | u32 num_bytes; |
278 | u8 num_wqebbs; | |
279 | u8 num_dma; | |
280 | }; | |
281 | ||
d4e28cbd AS |
282 | enum mlx5e_dma_map_type { |
283 | MLX5E_DMA_MAP_SINGLE, | |
284 | MLX5E_DMA_MAP_PAGE | |
285 | }; | |
286 | ||
f62b8bb8 | 287 | struct mlx5e_sq_dma { |
d4e28cbd AS |
288 | dma_addr_t addr; |
289 | u32 size; | |
290 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
291 | }; |
292 | ||
293 | enum { | |
294 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
0ba42241 | 295 | MLX5E_SQ_STATE_BF_ENABLE, |
f62b8bb8 AV |
296 | }; |
297 | ||
d3c9bc27 TT |
298 | struct mlx5e_ico_wqe_info { |
299 | u8 opcode; | |
300 | u8 num_wqebbs; | |
301 | }; | |
302 | ||
f62b8bb8 AV |
303 | struct mlx5e_sq { |
304 | /* data path */ | |
305 | ||
306 | /* dirtied @completion */ | |
307 | u16 cc; | |
308 | u32 dma_fifo_cc; | |
309 | ||
310 | /* dirtied @xmit */ | |
311 | u16 pc ____cacheline_aligned_in_smp; | |
312 | u32 dma_fifo_pc; | |
88a85f99 AS |
313 | u16 bf_offset; |
314 | u16 prev_cc; | |
315 | u8 bf_budget; | |
f62b8bb8 AV |
316 | struct mlx5e_sq_stats stats; |
317 | ||
318 | struct mlx5e_cq cq; | |
319 | ||
320 | /* pointers to per packet info: write@xmit, read@completion */ | |
321 | struct sk_buff **skb; | |
322 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 323 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
324 | |
325 | /* read only */ | |
326 | struct mlx5_wq_cyc wq; | |
327 | u32 dma_fifo_mask; | |
328 | void __iomem *uar_map; | |
329 | struct netdev_queue *txq; | |
330 | u32 sqn; | |
88a85f99 | 331 | u16 bf_buf_size; |
12be4b21 SM |
332 | u16 max_inline; |
333 | u16 edge; | |
f62b8bb8 | 334 | struct device *pdev; |
ef9814de | 335 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
336 | __be32 mkey_be; |
337 | unsigned long state; | |
338 | ||
339 | /* control path */ | |
340 | struct mlx5_wq_ctrl wq_ctrl; | |
341 | struct mlx5_uar uar; | |
342 | struct mlx5e_channel *channel; | |
343 | int tc; | |
d3c9bc27 | 344 | struct mlx5e_ico_wqe_info *ico_wqe_info; |
f62b8bb8 AV |
345 | } ____cacheline_aligned_in_smp; |
346 | ||
347 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
348 | { | |
349 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
350 | (sq->cc == sq->pc)); | |
351 | } | |
352 | ||
353 | enum channel_flags { | |
354 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
355 | }; | |
356 | ||
357 | struct mlx5e_channel { | |
358 | /* data path */ | |
359 | struct mlx5e_rq rq; | |
360 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
d3c9bc27 | 361 | struct mlx5e_sq icosq; /* internal control operations */ |
f62b8bb8 AV |
362 | struct napi_struct napi; |
363 | struct device *pdev; | |
364 | struct net_device *netdev; | |
365 | __be32 mkey_be; | |
366 | u8 num_tc; | |
367 | unsigned long flags; | |
368 | ||
369 | /* control */ | |
370 | struct mlx5e_priv *priv; | |
371 | int ix; | |
372 | int cpu; | |
373 | }; | |
374 | ||
375 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
376 | MLX5E_TT_IPV4_TCP, |
377 | MLX5E_TT_IPV6_TCP, | |
378 | MLX5E_TT_IPV4_UDP, | |
379 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
380 | MLX5E_TT_IPV4_IPSEC_AH, |
381 | MLX5E_TT_IPV6_IPSEC_AH, | |
382 | MLX5E_TT_IPV4_IPSEC_ESP, | |
383 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
384 | MLX5E_TT_IPV4, |
385 | MLX5E_TT_IPV6, | |
386 | MLX5E_TT_ANY, | |
387 | MLX5E_NUM_TT, | |
1da36696 | 388 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
389 | }; |
390 | ||
391 | struct mlx5e_eth_addr_info { | |
392 | u8 addr[ETH_ALEN + 2]; | |
393 | u32 tt_vec; | |
86d722ad | 394 | struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; |
f62b8bb8 AV |
395 | }; |
396 | ||
397 | #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) | |
398 | ||
399 | struct mlx5e_eth_addr_db { | |
400 | struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
401 | struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
402 | struct mlx5e_eth_addr_info broadcast; | |
403 | struct mlx5e_eth_addr_info allmulti; | |
404 | struct mlx5e_eth_addr_info promisc; | |
405 | bool broadcast_enabled; | |
406 | bool allmulti_enabled; | |
407 | bool promisc_enabled; | |
408 | }; | |
409 | ||
410 | enum { | |
411 | MLX5E_STATE_ASYNC_EVENTS_ENABLE, | |
412 | MLX5E_STATE_OPENED, | |
9b37b07f | 413 | MLX5E_STATE_DESTROYING, |
f62b8bb8 AV |
414 | }; |
415 | ||
416 | struct mlx5e_vlan_db { | |
aad9e6e4 | 417 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
418 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
419 | struct mlx5_flow_rule *untagged_rule; | |
420 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
421 | bool filter_disabled; |
422 | }; | |
423 | ||
b3f63c3d MF |
424 | struct mlx5e_vxlan_db { |
425 | spinlock_t lock; /* protect vxlan table */ | |
426 | struct radix_tree_root tree; | |
427 | }; | |
428 | ||
f62b8bb8 | 429 | struct mlx5e_flow_table { |
86d722ad MG |
430 | int num_groups; |
431 | struct mlx5_flow_table *t; | |
432 | struct mlx5_flow_group **g; | |
433 | }; | |
434 | ||
e8f887ac AV |
435 | struct mlx5e_tc_flow_table { |
436 | struct mlx5_flow_table *t; | |
437 | ||
438 | struct rhashtable_params ht_params; | |
439 | struct rhashtable ht; | |
440 | }; | |
441 | ||
86d722ad MG |
442 | struct mlx5e_flow_tables { |
443 | struct mlx5_flow_namespace *ns; | |
e8f887ac | 444 | struct mlx5e_tc_flow_table tc; |
86d722ad MG |
445 | struct mlx5e_flow_table vlan; |
446 | struct mlx5e_flow_table main; | |
f62b8bb8 AV |
447 | }; |
448 | ||
1da36696 TT |
449 | struct mlx5e_direct_tir { |
450 | u32 tirn; | |
451 | u32 rqtn; | |
452 | }; | |
453 | ||
f62b8bb8 AV |
454 | struct mlx5e_priv { |
455 | /* priv data path fields - start */ | |
03289b88 | 456 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 457 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
458 | /* priv data path fields - end */ |
459 | ||
460 | unsigned long state; | |
461 | struct mutex state_lock; /* Protects Interface state */ | |
462 | struct mlx5_uar cq_uar; | |
463 | u32 pdn; | |
3191e05f | 464 | u32 tdn; |
a606b0f6 | 465 | struct mlx5_core_mkey mkey; |
bc77b240 | 466 | struct mlx5_core_mkey umr_mkey; |
50cfa25a | 467 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
468 | |
469 | struct mlx5e_channel **channel; | |
470 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
1da36696 TT |
471 | u32 indir_rqtn; |
472 | u32 indir_tirn[MLX5E_NUM_INDIR_TIRS]; | |
473 | struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
f62b8bb8 | 474 | |
86d722ad | 475 | struct mlx5e_flow_tables fts; |
f62b8bb8 AV |
476 | struct mlx5e_eth_addr_db eth_addr; |
477 | struct mlx5e_vlan_db vlan; | |
b3f63c3d | 478 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
479 | |
480 | struct mlx5e_params params; | |
f62b8bb8 AV |
481 | struct work_struct update_carrier_work; |
482 | struct work_struct set_rx_mode_work; | |
483 | struct delayed_work update_stats_work; | |
484 | ||
485 | struct mlx5_core_dev *mdev; | |
486 | struct net_device *netdev; | |
487 | struct mlx5e_stats stats; | |
ef9814de | 488 | struct mlx5e_tstamp tstamp; |
593cf338 | 489 | u16 q_counter; |
f62b8bb8 AV |
490 | }; |
491 | ||
f62b8bb8 AV |
492 | enum mlx5e_link_mode { |
493 | MLX5E_1000BASE_CX_SGMII = 0, | |
494 | MLX5E_1000BASE_KX = 1, | |
495 | MLX5E_10GBASE_CX4 = 2, | |
496 | MLX5E_10GBASE_KX4 = 3, | |
497 | MLX5E_10GBASE_KR = 4, | |
498 | MLX5E_20GBASE_KR2 = 5, | |
499 | MLX5E_40GBASE_CR4 = 6, | |
500 | MLX5E_40GBASE_KR4 = 7, | |
501 | MLX5E_56GBASE_R4 = 8, | |
502 | MLX5E_10GBASE_CR = 12, | |
503 | MLX5E_10GBASE_SR = 13, | |
504 | MLX5E_10GBASE_ER = 14, | |
505 | MLX5E_40GBASE_SR4 = 15, | |
506 | MLX5E_40GBASE_LR4 = 16, | |
507 | MLX5E_100GBASE_CR4 = 20, | |
508 | MLX5E_100GBASE_SR4 = 21, | |
509 | MLX5E_100GBASE_KR4 = 22, | |
510 | MLX5E_100GBASE_LR4 = 23, | |
511 | MLX5E_100BASE_TX = 24, | |
6e4c2189 | 512 | MLX5E_1000BASE_T = 25, |
f62b8bb8 AV |
513 | MLX5E_10GBASE_T = 26, |
514 | MLX5E_25GBASE_CR = 27, | |
515 | MLX5E_25GBASE_KR = 28, | |
516 | MLX5E_25GBASE_SR = 29, | |
517 | MLX5E_50GBASE_CR2 = 30, | |
518 | MLX5E_50GBASE_KR2 = 31, | |
519 | MLX5E_LINK_MODES_NUMBER, | |
520 | }; | |
521 | ||
522 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
523 | ||
12be4b21 | 524 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
525 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
526 | void *accel_priv, select_queue_fallback_t fallback); | |
527 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
528 | |
529 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
530 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
531 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 532 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 533 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
461017cb | 534 | |
2f48af12 | 535 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 536 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 537 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 538 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
461017cb | 539 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
bc77b240 TT |
540 | void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq); |
541 | void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
542 | struct mlx5_cqe64 *cqe, | |
543 | u16 byte_cnt, | |
544 | struct mlx5e_mpw_info *wi, | |
545 | struct sk_buff *skb); | |
546 | void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
547 | struct mlx5_cqe64 *cqe, | |
548 | u16 byte_cnt, | |
549 | struct mlx5e_mpw_info *wi, | |
550 | struct sk_buff *skb); | |
551 | void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
552 | struct mlx5e_mpw_info *wi); | |
553 | void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
554 | struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
555 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
556 | ||
557 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
558 | ||
40ab6a6e AS |
559 | int mlx5e_create_flow_tables(struct mlx5e_priv *priv); |
560 | void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv); | |
f62b8bb8 | 561 | void mlx5e_init_eth_addr(struct mlx5e_priv *priv); |
f62b8bb8 AV |
562 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
563 | ||
ef9814de EBE |
564 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
565 | struct skb_shared_hwtstamps *hwts); | |
566 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
567 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
568 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
569 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
570 | ||
f62b8bb8 AV |
571 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
572 | u16 vid); | |
573 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
574 | u16 vid); | |
575 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
576 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 577 | |
36350114 GP |
578 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
579 | ||
1da36696 | 580 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 581 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 582 | |
f62b8bb8 AV |
583 | int mlx5e_open_locked(struct net_device *netdev); |
584 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
585 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
586 | u32 *indirection_rqt, int len, | |
85082dba | 587 | int num_channels); |
f62b8bb8 AV |
588 | |
589 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
bc77b240 | 590 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 591 | { |
88a85f99 AS |
592 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
593 | ||
f62b8bb8 AV |
594 | /* ensure wqe is visible to device before updating doorbell record */ |
595 | dma_wmb(); | |
596 | ||
597 | *sq->wq.db = cpu_to_be32(sq->pc); | |
598 | ||
599 | /* ensure doorbell record is visible to device before ringing the | |
600 | * doorbell | |
601 | */ | |
602 | wmb(); | |
0ba42241 | 603 | if (bf_sz) |
bc77b240 | 604 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 605 | else |
bc77b240 | 606 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
607 | /* flush the write-combining mapped buffer */ |
608 | wmb(); | |
f62b8bb8 AV |
609 | |
610 | sq->bf_offset ^= sq->bf_buf_size; | |
611 | } | |
612 | ||
613 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
614 | { | |
615 | struct mlx5_core_cq *mcq; | |
616 | ||
617 | mcq = &cq->mcq; | |
618 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
619 | } | |
620 | ||
3435ab59 AS |
621 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
622 | { | |
623 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
624 | MLX5E_MAX_NUM_CHANNELS); | |
625 | } | |
626 | ||
bc77b240 TT |
627 | static inline int mlx5e_get_mtt_octw(int npages) |
628 | { | |
629 | return ALIGN(npages, 8) / 2; | |
630 | } | |
631 | ||
f62b8bb8 | 632 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
633 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
634 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
635 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
636 | #endif | |
637 | ||
58d52291 | 638 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
1afff42c MF |
639 | |
640 | #endif /* __MLX5_EN_H__ */ |