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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
48935bbb | 40 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
41 | #include <linux/mlx5/driver.h> |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/cq.h> | |
ada68c31 | 44 | #include <linux/mlx5/port.h> |
d18a9470 | 45 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 46 | #include <linux/mlx5/transobj.h> |
1ae1df3a | 47 | #include <linux/mlx5/fs.h> |
e8f887ac | 48 | #include <linux/rhashtable.h> |
cb67b832 | 49 | #include <net/switchdev.h> |
0ddf5432 | 50 | #include <net/xdp.h> |
4c4dbb4a | 51 | #include <linux/net_dim.h> |
f62b8bb8 | 52 | #include "wq.h" |
f62b8bb8 | 53 | #include "mlx5_core.h" |
9218b44d | 54 | #include "en_stats.h" |
f62b8bb8 | 55 | |
60bbf7ee JDB |
56 | struct page_pool; |
57 | ||
bb909416 IL |
58 | #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) |
59 | #define MLX5E_METADATA_ETHER_LEN 8 | |
60 | ||
1cabe6b0 MG |
61 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
62 | ||
c139dbfd ES |
63 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
64 | ||
472a1e44 TT |
65 | #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) |
66 | #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) | |
d8bec2b2 | 67 | |
0696d608 | 68 | #define MLX5E_MAX_PRIORITY 8 |
2a5e7a13 | 69 | #define MLX5E_MAX_DSCP 64 |
f62b8bb8 AV |
70 | #define MLX5E_MAX_NUM_TC 8 |
71 | ||
1bfecfca | 72 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
73 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
74 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 75 | |
f32f5bd2 DJ |
76 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
77 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
78 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
79 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
80 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | |
81 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | |
696a97cf EE |
82 | #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \ |
83 | (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \ | |
84 | MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)) | |
f32f5bd2 | 85 | |
7e426671 | 86 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
87 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
88 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
89 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
90 | |
91 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
73281b78 | 92 | #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) |
b8a98a4c | 93 | #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS)) |
73281b78 TT |
94 | #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) |
95 | #define MLX5E_MAX_RQ_NUM_MTTS \ | |
96 | ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ | |
97 | #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) | |
98 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ | |
99 | (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) | |
100 | #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ | |
101 | (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ | |
102 | (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) | |
103 | ||
069d1146 TT |
104 | #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) |
105 | #define MLX5E_LOG_MAX_RX_WQE_BULK \ | |
106 | (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) | |
107 | ||
73281b78 TT |
108 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
109 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
110 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
111 | ||
069d1146 | 112 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) |
73281b78 TT |
113 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
114 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ | |
115 | MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) | |
116 | ||
117 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 | |
fe4c988b | 118 | |
75aa889f | 119 | #define MLX5E_RX_MAX_HEAD (256) |
461017cb | 120 | |
d9a40271 | 121 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
122 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
123 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
124 | ||
f62b8bb8 | 125 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 126 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
127 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
128 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 129 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
130 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
131 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 132 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 133 | |
936896e9 AS |
134 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
135 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 136 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 137 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 138 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 | 139 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
db75373c | 140 | #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ |
f62b8bb8 | 141 | |
ea3886ca TT |
142 | #define MLX5E_UMR_WQE_INLINE_SZ \ |
143 | (sizeof(struct mlx5e_umr_wqe) + \ | |
144 | ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ | |
145 | MLX5_UMR_MTT_ALIGNMENT)) | |
146 | #define MLX5E_UMR_WQEBBS \ | |
147 | (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) | |
148 | #define MLX5E_ICOSQ_MAX_WQEBBS MLX5E_UMR_WQEBBS | |
f10b7cc7 | 149 | |
86d722ad | 150 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 151 | |
79c48764 GP |
152 | #define MLX5E_MSG_LEVEL NETIF_MSG_LINK |
153 | ||
154 | #define mlx5e_dbg(mlevel, priv, format, ...) \ | |
155 | do { \ | |
156 | if (NETIF_MSG_##mlevel & (priv)->msglevel) \ | |
157 | netdev_warn(priv->netdev, format, \ | |
158 | ##__VA_ARGS__); \ | |
159 | } while (0) | |
160 | ||
161 | ||
461017cb TT |
162 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
163 | { | |
164 | switch (wq_type) { | |
165 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
166 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
167 | wq_size / 2); | |
168 | default: | |
169 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
170 | wq_size / 2); | |
171 | } | |
172 | } | |
173 | ||
48935bbb SM |
174 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
175 | { | |
176 | return is_kdump_kernel() ? | |
177 | MLX5E_MIN_NUM_CHANNELS : | |
178 | min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
179 | MLX5E_MAX_NUM_CHANNELS); | |
180 | } | |
181 | ||
2f48af12 TT |
182 | struct mlx5e_tx_wqe { |
183 | struct mlx5_wqe_ctrl_seg ctrl; | |
184 | struct mlx5_wqe_eth_seg eth; | |
043dc78e | 185 | struct mlx5_wqe_data_seg data[0]; |
2f48af12 TT |
186 | }; |
187 | ||
99cbfa93 | 188 | struct mlx5e_rx_wqe_ll { |
2f48af12 | 189 | struct mlx5_wqe_srq_next_seg next; |
99cbfa93 TT |
190 | struct mlx5_wqe_data_seg data[0]; |
191 | }; | |
192 | ||
193 | struct mlx5e_rx_wqe_cyc { | |
194 | struct mlx5_wqe_data_seg data[0]; | |
2f48af12 | 195 | }; |
86d722ad | 196 | |
bc77b240 TT |
197 | struct mlx5e_umr_wqe { |
198 | struct mlx5_wqe_ctrl_seg ctrl; | |
199 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
200 | struct mlx5_mkey_seg mkc; | |
ea3886ca | 201 | struct mlx5_mtt inline_mtts[0]; |
bc77b240 TT |
202 | }; |
203 | ||
d605d668 KH |
204 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
205 | ||
4e59e288 | 206 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 207 | "rx_cqe_moder", |
0088cbbc | 208 | "tx_cqe_moder", |
9bcc8606 | 209 | "rx_cqe_compress", |
2ccb0a79 | 210 | "rx_striding_rq", |
4e59e288 GP |
211 | }; |
212 | ||
213 | enum mlx5e_priv_flag { | |
9908aa29 | 214 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
0088cbbc TG |
215 | MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1), |
216 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2), | |
2ccb0a79 | 217 | MLX5E_PFLAG_RX_STRIDING_RQ = (1 << 3), |
4e59e288 GP |
218 | }; |
219 | ||
6a9764ef | 220 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
221 | do { \ |
222 | if (enable) \ | |
6a9764ef | 223 | (params)->pflags |= (pflag); \ |
59ece1c9 | 224 | else \ |
6a9764ef | 225 | (params)->pflags &= ~(pflag); \ |
4e59e288 GP |
226 | } while (0) |
227 | ||
6a9764ef | 228 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag))) |
59ece1c9 | 229 | |
08fb1dac SM |
230 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
231 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
232 | #endif |
233 | ||
f62b8bb8 AV |
234 | struct mlx5e_params { |
235 | u8 log_sq_size; | |
461017cb | 236 | u8 rq_wq_type; |
73281b78 | 237 | u8 log_rq_mtu_frames; |
f62b8bb8 | 238 | u16 num_channels; |
f62b8bb8 | 239 | u8 num_tc; |
9bcc8606 | 240 | bool rx_cqe_compress_def; |
9a317425 AG |
241 | struct net_dim_cq_moder rx_cq_moderation; |
242 | struct net_dim_cq_moder tx_cq_moderation; | |
f62b8bb8 AV |
243 | bool lro_en; |
244 | u32 lro_wqe_sz; | |
cff92d7c | 245 | u8 tx_min_inline_mode; |
2d75b2bc AS |
246 | u8 rss_hfunc; |
247 | u8 toeplitz_hash_key[40]; | |
248 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 249 | bool vlan_strip_disable; |
102722fc | 250 | bool scatter_fcs_en; |
9a317425 | 251 | bool rx_dim_enabled; |
cbce4f44 | 252 | bool tx_dim_enabled; |
2b029556 | 253 | u32 lro_timeout; |
59ece1c9 | 254 | u32 pflags; |
6a9764ef | 255 | struct bpf_prog *xdp_prog; |
472a1e44 TT |
256 | unsigned int sw_mtu; |
257 | int hard_mtu; | |
f62b8bb8 AV |
258 | }; |
259 | ||
3a6a931d HN |
260 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
261 | struct mlx5e_cee_config { | |
262 | /* bw pct for priority group */ | |
263 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
264 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
265 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
266 | bool pfc_enable; | |
267 | }; | |
268 | ||
269 | enum { | |
270 | MLX5_DCB_CHG_RESET, | |
271 | MLX5_DCB_NO_CHG, | |
272 | MLX5_DCB_CHG_NO_RESET, | |
273 | }; | |
274 | ||
275 | struct mlx5e_dcbx { | |
e207b7e9 | 276 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 277 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
2a5e7a13 | 278 | u8 dscp_app_cnt; |
820c2c5e HN |
279 | |
280 | /* The only setting that cannot be read from FW */ | |
281 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
9e10bf1d | 282 | u8 cap; |
0696d608 HN |
283 | |
284 | /* Buffer configuration */ | |
ecdf2dad | 285 | bool manual_buffer; |
0696d608 HN |
286 | u32 cable_len; |
287 | u32 xoff; | |
3a6a931d | 288 | }; |
2a5e7a13 HN |
289 | |
290 | struct mlx5e_dcbx_dp { | |
291 | u8 dscp2prio[MLX5E_MAX_DSCP]; | |
292 | u8 trust_state; | |
293 | }; | |
3a6a931d HN |
294 | #endif |
295 | ||
f62b8bb8 | 296 | enum { |
c0f1147d | 297 | MLX5E_RQ_STATE_ENABLED, |
cb3c7fd4 | 298 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
299 | }; |
300 | ||
f62b8bb8 AV |
301 | struct mlx5e_cq { |
302 | /* data path - accessed per cqe */ | |
303 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
304 | |
305 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 306 | u16 event_ctr; |
f62b8bb8 AV |
307 | struct napi_struct *napi; |
308 | struct mlx5_core_cq mcq; | |
309 | struct mlx5e_channel *channel; | |
310 | ||
7219ab34 TT |
311 | /* cqe decompression */ |
312 | struct mlx5_cqe64 title; | |
313 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
314 | u8 mini_arr_idx; | |
315 | u16 decmprs_left; | |
316 | u16 decmprs_wqe_counter; | |
317 | ||
f62b8bb8 | 318 | /* control */ |
a43b25da | 319 | struct mlx5_core_dev *mdev; |
3a2f7033 | 320 | struct mlx5_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
321 | } ____cacheline_aligned_in_smp; |
322 | ||
eba2db2b | 323 | struct mlx5e_tx_wqe_info { |
77bdf895 | 324 | struct sk_buff *skb; |
eba2db2b SM |
325 | u32 num_bytes; |
326 | u8 num_wqebbs; | |
327 | u8 num_dma; | |
328 | }; | |
329 | ||
330 | enum mlx5e_dma_map_type { | |
331 | MLX5E_DMA_MAP_SINGLE, | |
332 | MLX5E_DMA_MAP_PAGE | |
333 | }; | |
334 | ||
335 | struct mlx5e_sq_dma { | |
336 | dma_addr_t addr; | |
337 | u32 size; | |
338 | enum mlx5e_dma_map_type type; | |
339 | }; | |
340 | ||
341 | enum { | |
342 | MLX5E_SQ_STATE_ENABLED, | |
db75373c | 343 | MLX5E_SQ_STATE_RECOVERING, |
2ac9cfe7 | 344 | MLX5E_SQ_STATE_IPSEC, |
cbce4f44 | 345 | MLX5E_SQ_STATE_AM, |
bf239741 | 346 | MLX5E_SQ_STATE_TLS, |
eba2db2b SM |
347 | }; |
348 | ||
349 | struct mlx5e_sq_wqe_info { | |
350 | u8 opcode; | |
eba2db2b | 351 | }; |
2f48af12 | 352 | |
31391048 | 353 | struct mlx5e_txqsq { |
eba2db2b SM |
354 | /* data path */ |
355 | ||
356 | /* dirtied @completion */ | |
357 | u16 cc; | |
358 | u32 dma_fifo_cc; | |
cbce4f44 | 359 | struct net_dim dim; /* Adaptive Moderation */ |
eba2db2b SM |
360 | |
361 | /* dirtied @xmit */ | |
362 | u16 pc ____cacheline_aligned_in_smp; | |
363 | u32 dma_fifo_pc; | |
eba2db2b SM |
364 | |
365 | struct mlx5e_cq cq; | |
366 | ||
31391048 SM |
367 | /* write@xmit, read@completion */ |
368 | struct { | |
31391048 SM |
369 | struct mlx5e_sq_dma *dma_fifo; |
370 | struct mlx5e_tx_wqe_info *wqe_info; | |
eba2db2b SM |
371 | } db; |
372 | ||
373 | /* read only */ | |
374 | struct mlx5_wq_cyc wq; | |
375 | u32 dma_fifo_mask; | |
05909bab | 376 | struct mlx5e_sq_stats *stats; |
eba2db2b SM |
377 | void __iomem *uar_map; |
378 | struct netdev_queue *txq; | |
379 | u32 sqn; | |
eba2db2b | 380 | u8 min_inline_mode; |
eba2db2b | 381 | struct device *pdev; |
eba2db2b SM |
382 | __be32 mkey_be; |
383 | unsigned long state; | |
7c39afb3 FD |
384 | struct hwtstamp_config *tstamp; |
385 | struct mlx5_clock *clock; | |
eba2db2b SM |
386 | |
387 | /* control path */ | |
388 | struct mlx5_wq_ctrl wq_ctrl; | |
389 | struct mlx5e_channel *channel; | |
acc6c595 | 390 | int txq_ix; |
eba2db2b | 391 | u32 rate_limit; |
db75373c EBE |
392 | struct mlx5e_txqsq_recover { |
393 | struct work_struct recover_work; | |
394 | u64 last_recover; | |
395 | } recover; | |
31391048 SM |
396 | } ____cacheline_aligned_in_smp; |
397 | ||
c94e4f11 TT |
398 | struct mlx5e_dma_info { |
399 | struct page *page; | |
400 | dma_addr_t addr; | |
401 | }; | |
402 | ||
403 | struct mlx5e_xdp_info { | |
404 | struct xdp_frame *xdpf; | |
405 | dma_addr_t dma_addr; | |
406 | struct mlx5e_dma_info di; | |
407 | }; | |
408 | ||
31391048 SM |
409 | struct mlx5e_xdpsq { |
410 | /* data path */ | |
411 | ||
412 | /* dirtied @rx completion */ | |
413 | u16 cc; | |
414 | u16 pc; | |
415 | ||
416 | struct mlx5e_cq cq; | |
417 | ||
418 | /* write@xmit, read@completion */ | |
419 | struct { | |
c94e4f11 | 420 | struct mlx5e_xdp_info *xdpi; |
31391048 | 421 | bool doorbell; |
5168d732 | 422 | bool redirect_flush; |
31391048 SM |
423 | } db; |
424 | ||
425 | /* read only */ | |
426 | struct mlx5_wq_cyc wq; | |
890388ad | 427 | struct mlx5e_xdpsq_stats *stats; |
31391048 SM |
428 | void __iomem *uar_map; |
429 | u32 sqn; | |
430 | struct device *pdev; | |
431 | __be32 mkey_be; | |
432 | u8 min_inline_mode; | |
433 | unsigned long state; | |
c94e4f11 | 434 | unsigned int hw_mtu; |
31391048 SM |
435 | |
436 | /* control path */ | |
437 | struct mlx5_wq_ctrl wq_ctrl; | |
438 | struct mlx5e_channel *channel; | |
439 | } ____cacheline_aligned_in_smp; | |
440 | ||
441 | struct mlx5e_icosq { | |
442 | /* data path */ | |
443 | ||
31391048 SM |
444 | /* dirtied @xmit */ |
445 | u16 pc ____cacheline_aligned_in_smp; | |
31391048 SM |
446 | |
447 | struct mlx5e_cq cq; | |
448 | ||
449 | /* write@xmit, read@completion */ | |
450 | struct { | |
451 | struct mlx5e_sq_wqe_info *ico_wqe; | |
452 | } db; | |
453 | ||
454 | /* read only */ | |
455 | struct mlx5_wq_cyc wq; | |
456 | void __iomem *uar_map; | |
457 | u32 sqn; | |
31391048 SM |
458 | unsigned long state; |
459 | ||
460 | /* control path */ | |
461 | struct mlx5_wq_ctrl wq_ctrl; | |
462 | struct mlx5e_channel *channel; | |
eba2db2b SM |
463 | } ____cacheline_aligned_in_smp; |
464 | ||
864b2d71 SM |
465 | static inline bool |
466 | mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) | |
eba2db2b | 467 | { |
ddf385e3 | 468 | return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc); |
eba2db2b | 469 | } |
6cd392a0 | 470 | |
accd5883 | 471 | struct mlx5e_wqe_frag_info { |
069d1146 | 472 | struct mlx5e_dma_info *di; |
accd5883 | 473 | u32 offset; |
069d1146 | 474 | bool last_in_page; |
accd5883 TT |
475 | }; |
476 | ||
eba2db2b | 477 | struct mlx5e_umr_dma_info { |
eba2db2b | 478 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
eba2db2b SM |
479 | }; |
480 | ||
481 | struct mlx5e_mpw_info { | |
482 | struct mlx5e_umr_dma_info umr; | |
483 | u16 consumed_strides; | |
22f45398 | 484 | DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); |
eba2db2b SM |
485 | }; |
486 | ||
069d1146 TT |
487 | #define MLX5E_MAX_RX_FRAGS 4 |
488 | ||
4415a031 TT |
489 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
490 | * or a MPWQE (for striding rq). | |
491 | */ | |
492 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
493 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
29c2849e | 494 | #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) |
4415a031 TT |
495 | struct mlx5e_page_cache { |
496 | u32 head; | |
497 | u32 tail; | |
498 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
499 | }; | |
500 | ||
eba2db2b SM |
501 | struct mlx5e_rq; |
502 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
619a8f2a TT |
503 | typedef struct sk_buff * |
504 | (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
505 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
506 | typedef struct sk_buff * |
507 | (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
508 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
7cc6d77b | 509 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b SM |
510 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
511 | ||
121e8927 TT |
512 | enum mlx5e_rq_flag { |
513 | MLX5E_RQ_FLAG_XDP_XMIT = BIT(0), | |
514 | }; | |
515 | ||
069d1146 TT |
516 | struct mlx5e_rq_frag_info { |
517 | int frag_size; | |
518 | int frag_stride; | |
519 | }; | |
520 | ||
521 | struct mlx5e_rq_frags_info { | |
522 | struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; | |
523 | u8 num_frags; | |
524 | u8 log_num_frags; | |
525 | u8 wqe_bulk; | |
526 | }; | |
527 | ||
f62b8bb8 AV |
528 | struct mlx5e_rq { |
529 | /* data path */ | |
21c59685 | 530 | union { |
accd5883 | 531 | struct { |
069d1146 TT |
532 | struct mlx5_wq_cyc wq; |
533 | struct mlx5e_wqe_frag_info *frags; | |
534 | struct mlx5e_dma_info *di; | |
535 | struct mlx5e_rq_frags_info info; | |
536 | mlx5e_fp_skb_from_cqe skb_from_cqe; | |
accd5883 | 537 | } wqe; |
21c59685 | 538 | struct { |
422d4c40 | 539 | struct mlx5_wq_ll wq; |
b8a98a4c | 540 | struct mlx5e_umr_wqe umr_wqe; |
21c59685 | 541 | struct mlx5e_mpw_info *info; |
619a8f2a | 542 | mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; |
b45d8b50 | 543 | u16 num_strides; |
89e89f7a | 544 | u8 log_stride_sz; |
a071cb9f | 545 | bool umr_in_progress; |
21c59685 SM |
546 | } mpwqe; |
547 | }; | |
1bfecfca | 548 | struct { |
b45d8b50 | 549 | u16 headroom; |
b5503b99 | 550 | u8 map_dir; /* dma map direction */ |
1bfecfca | 551 | } buff; |
f62b8bb8 | 552 | |
7cc6d77b | 553 | struct mlx5e_channel *channel; |
f62b8bb8 AV |
554 | struct device *pdev; |
555 | struct net_device *netdev; | |
05909bab | 556 | struct mlx5e_rq_stats *stats; |
f62b8bb8 | 557 | struct mlx5e_cq cq; |
4415a031 | 558 | struct mlx5e_page_cache page_cache; |
7c39afb3 FD |
559 | struct hwtstamp_config *tstamp; |
560 | struct mlx5_clock *clock; | |
4415a031 | 561 | |
2f48af12 | 562 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 563 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 564 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
565 | |
566 | unsigned long state; | |
567 | int ix; | |
568 | ||
9a317425 | 569 | struct net_dim dim; /* Dynamic Interrupt Moderation */ |
31871f87 SM |
570 | |
571 | /* XDP */ | |
86994156 | 572 | struct bpf_prog *xdp_prog; |
31391048 | 573 | struct mlx5e_xdpsq xdpsq; |
121e8927 | 574 | DECLARE_BITMAP(flags, 8); |
60bbf7ee | 575 | struct page_pool *page_pool; |
cb3c7fd4 | 576 | |
f62b8bb8 AV |
577 | /* control */ |
578 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 579 | __be32 mkey_be; |
461017cb | 580 | u8 wq_type; |
f62b8bb8 | 581 | u32 rqn; |
a43b25da | 582 | struct mlx5_core_dev *mdev; |
ec8b9981 | 583 | struct mlx5_core_mkey umr_mkey; |
0ddf5432 JDB |
584 | |
585 | /* XDP read-mostly */ | |
586 | struct xdp_rxq_info xdp_rxq; | |
f62b8bb8 AV |
587 | } ____cacheline_aligned_in_smp; |
588 | ||
f62b8bb8 AV |
589 | struct mlx5e_channel { |
590 | /* data path */ | |
591 | struct mlx5e_rq rq; | |
31391048 SM |
592 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
593 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 594 | bool xdp; |
f62b8bb8 AV |
595 | struct napi_struct napi; |
596 | struct device *pdev; | |
597 | struct net_device *netdev; | |
598 | __be32 mkey_be; | |
599 | u8 num_tc; | |
f62b8bb8 | 600 | |
a8c2eb15 TT |
601 | /* data path - accessed per napi poll */ |
602 | struct irq_desc *irq_desc; | |
05909bab | 603 | struct mlx5e_ch_stats *stats; |
f62b8bb8 AV |
604 | |
605 | /* control */ | |
606 | struct mlx5e_priv *priv; | |
a43b25da | 607 | struct mlx5_core_dev *mdev; |
7c39afb3 | 608 | struct hwtstamp_config *tstamp; |
f62b8bb8 | 609 | int ix; |
231243c8 | 610 | int cpu; |
f62b8bb8 AV |
611 | }; |
612 | ||
ff9c852f SM |
613 | struct mlx5e_channels { |
614 | struct mlx5e_channel **c; | |
615 | unsigned int num; | |
6a9764ef | 616 | struct mlx5e_params params; |
ff9c852f SM |
617 | }; |
618 | ||
05909bab EBE |
619 | struct mlx5e_channel_stats { |
620 | struct mlx5e_ch_stats ch; | |
621 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
622 | struct mlx5e_rq_stats rq; | |
890388ad | 623 | struct mlx5e_xdpsq_stats rq_xdpsq; |
05909bab EBE |
624 | } ____cacheline_aligned_in_smp; |
625 | ||
f62b8bb8 | 626 | enum mlx5e_traffic_types { |
5a6f8aef AS |
627 | MLX5E_TT_IPV4_TCP, |
628 | MLX5E_TT_IPV6_TCP, | |
629 | MLX5E_TT_IPV4_UDP, | |
630 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
631 | MLX5E_TT_IPV4_IPSEC_AH, |
632 | MLX5E_TT_IPV6_IPSEC_AH, | |
633 | MLX5E_TT_IPV4_IPSEC_ESP, | |
634 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
635 | MLX5E_TT_IPV4, |
636 | MLX5E_TT_IPV6, | |
637 | MLX5E_TT_ANY, | |
638 | MLX5E_NUM_TT, | |
1da36696 | 639 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
640 | }; |
641 | ||
7b3722fa GP |
642 | enum mlx5e_tunnel_types { |
643 | MLX5E_TT_IPV4_GRE, | |
644 | MLX5E_TT_IPV6_GRE, | |
645 | MLX5E_NUM_TUNNEL_TT, | |
646 | }; | |
647 | ||
acff797c | 648 | enum { |
e0f46eb9 | 649 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
650 | MLX5E_STATE_OPENED, |
651 | MLX5E_STATE_DESTROYING, | |
652 | }; | |
653 | ||
654 | struct mlx5e_vxlan_db { | |
655 | spinlock_t lock; /* protect vxlan table */ | |
656 | struct radix_tree_root tree; | |
657 | }; | |
658 | ||
33cfaaa8 | 659 | struct mlx5e_l2_rule { |
f62b8bb8 | 660 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 661 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
662 | }; |
663 | ||
acff797c MG |
664 | struct mlx5e_flow_table { |
665 | int num_groups; | |
666 | struct mlx5_flow_table *t; | |
667 | struct mlx5_flow_group **g; | |
668 | }; | |
669 | ||
33cfaaa8 | 670 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 671 | |
acff797c MG |
672 | struct mlx5e_tc_table { |
673 | struct mlx5_flow_table *t; | |
674 | ||
acff797c | 675 | struct rhashtable ht; |
11c9c548 OG |
676 | |
677 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); | |
5c65c564 | 678 | DECLARE_HASHTABLE(hairpin_tbl, 8); |
f62b8bb8 AV |
679 | }; |
680 | ||
acff797c MG |
681 | struct mlx5e_vlan_table { |
682 | struct mlx5e_flow_table ft; | |
03eda954 | 683 | DECLARE_BITMAP(active_cvlans, VLAN_N_VID); |
7d92d580 | 684 | DECLARE_BITMAP(active_svlans, VLAN_N_VID); |
2b52a283 | 685 | struct mlx5_flow_handle *active_cvlans_rule[VLAN_N_VID]; |
7d92d580 | 686 | struct mlx5_flow_handle *active_svlans_rule[VLAN_N_VID]; |
74491de9 | 687 | struct mlx5_flow_handle *untagged_rule; |
8a271746 MHY |
688 | struct mlx5_flow_handle *any_cvlan_rule; |
689 | struct mlx5_flow_handle *any_svlan_rule; | |
2b52a283 | 690 | bool cvlan_filter_disabled; |
f62b8bb8 AV |
691 | }; |
692 | ||
33cfaaa8 MG |
693 | struct mlx5e_l2_table { |
694 | struct mlx5e_flow_table ft; | |
695 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
696 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
697 | struct mlx5e_l2_rule broadcast; | |
698 | struct mlx5e_l2_rule allmulti; | |
699 | struct mlx5e_l2_rule promisc; | |
700 | bool broadcast_enabled; | |
701 | bool allmulti_enabled; | |
702 | bool promisc_enabled; | |
703 | }; | |
704 | ||
705 | /* L3/L4 traffic type classifier */ | |
706 | struct mlx5e_ttc_table { | |
707 | struct mlx5e_flow_table ft; | |
74491de9 | 708 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
7b3722fa | 709 | struct mlx5_flow_handle *tunnel_rules[MLX5E_NUM_TUNNEL_TT]; |
33cfaaa8 MG |
710 | }; |
711 | ||
18c908e4 MG |
712 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
713 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
714 | struct arfs_table { |
715 | struct mlx5e_flow_table ft; | |
74491de9 | 716 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 717 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
718 | }; |
719 | ||
720 | enum arfs_type { | |
721 | ARFS_IPV4_TCP, | |
722 | ARFS_IPV6_TCP, | |
723 | ARFS_IPV4_UDP, | |
724 | ARFS_IPV6_UDP, | |
725 | ARFS_NUM_TYPES, | |
726 | }; | |
727 | ||
728 | struct mlx5e_arfs_tables { | |
729 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
730 | /* Protect aRFS rules list */ |
731 | spinlock_t arfs_lock; | |
732 | struct list_head rules; | |
733 | int last_filter_id; | |
734 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
735 | }; |
736 | ||
737 | /* NIC prio FTS */ | |
738 | enum { | |
739 | MLX5E_VLAN_FT_LEVEL = 0, | |
740 | MLX5E_L2_FT_LEVEL, | |
741 | MLX5E_TTC_FT_LEVEL, | |
7b3722fa | 742 | MLX5E_INNER_TTC_FT_LEVEL, |
1cabe6b0 MG |
743 | MLX5E_ARFS_FT_LEVEL |
744 | }; | |
745 | ||
3f6d08d1 OG |
746 | enum { |
747 | MLX5E_TC_FT_LEVEL = 0, | |
748 | MLX5E_TC_TTC_FT_LEVEL, | |
749 | }; | |
750 | ||
6dc6071c MG |
751 | struct mlx5e_ethtool_table { |
752 | struct mlx5_flow_table *ft; | |
753 | int num_rules; | |
754 | }; | |
755 | ||
1174fce8 | 756 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
757 | #define ETHTOOL_NUM_L2_FTS 4 |
758 | ||
759 | struct mlx5e_ethtool_steering { | |
1174fce8 | 760 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
761 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
762 | struct list_head rules; | |
763 | int tot_num_rules; | |
764 | }; | |
765 | ||
acff797c MG |
766 | struct mlx5e_flow_steering { |
767 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 768 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
769 | struct mlx5e_tc_table tc; |
770 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
771 | struct mlx5e_l2_table l2; |
772 | struct mlx5e_ttc_table ttc; | |
7b3722fa | 773 | struct mlx5e_ttc_table inner_ttc; |
1cabe6b0 | 774 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
775 | }; |
776 | ||
398f3351 | 777 | struct mlx5e_rqt { |
1da36696 | 778 | u32 rqtn; |
398f3351 HHZ |
779 | bool enabled; |
780 | }; | |
781 | ||
782 | struct mlx5e_tir { | |
783 | u32 tirn; | |
784 | struct mlx5e_rqt rqt; | |
785 | struct list_head list; | |
1da36696 TT |
786 | }; |
787 | ||
acff797c MG |
788 | enum { |
789 | MLX5E_TC_PRIO = 0, | |
790 | MLX5E_NIC_PRIO | |
791 | }; | |
792 | ||
f62b8bb8 AV |
793 | struct mlx5e_priv { |
794 | /* priv data path fields - start */ | |
acc6c595 SM |
795 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
796 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
2a5e7a13 HN |
797 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
798 | struct mlx5e_dcbx_dp dcbx_dp; | |
799 | #endif | |
f62b8bb8 AV |
800 | /* priv data path fields - end */ |
801 | ||
79c48764 | 802 | u32 msglevel; |
f62b8bb8 AV |
803 | unsigned long state; |
804 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 805 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 806 | |
ff9c852f | 807 | struct mlx5e_channels channels; |
f62b8bb8 | 808 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 809 | struct mlx5e_rqt indir_rqt; |
724b2aa1 | 810 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
7b3722fa | 811 | struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; |
724b2aa1 | 812 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; |
507f0c81 | 813 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 814 | |
acff797c | 815 | struct mlx5e_flow_steering fs; |
b3f63c3d | 816 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 | 817 | |
7bb29755 | 818 | struct workqueue_struct *wq; |
f62b8bb8 AV |
819 | struct work_struct update_carrier_work; |
820 | struct work_struct set_rx_mode_work; | |
3947ca18 | 821 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
822 | struct delayed_work update_stats_work; |
823 | ||
824 | struct mlx5_core_dev *mdev; | |
825 | struct net_device *netdev; | |
826 | struct mlx5e_stats stats; | |
05909bab EBE |
827 | struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS]; |
828 | u8 max_opened_tc; | |
7c39afb3 | 829 | struct hwtstamp_config tstamp; |
7cbaf9a3 MS |
830 | u16 q_counter; |
831 | u16 drop_rq_q_counter; | |
3a6a931d HN |
832 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
833 | struct mlx5e_dcbx dcbx; | |
834 | #endif | |
835 | ||
6bfd390b | 836 | const struct mlx5e_profile *profile; |
127ea380 | 837 | void *ppriv; |
547eede0 IT |
838 | #ifdef CONFIG_MLX5_EN_IPSEC |
839 | struct mlx5e_ipsec *ipsec; | |
840 | #endif | |
43585a41 IL |
841 | #ifdef CONFIG_MLX5_EN_TLS |
842 | struct mlx5e_tls *tls; | |
843 | #endif | |
f62b8bb8 AV |
844 | }; |
845 | ||
a43b25da SM |
846 | struct mlx5e_profile { |
847 | void (*init)(struct mlx5_core_dev *mdev, | |
848 | struct net_device *netdev, | |
849 | const struct mlx5e_profile *profile, void *ppriv); | |
850 | void (*cleanup)(struct mlx5e_priv *priv); | |
851 | int (*init_rx)(struct mlx5e_priv *priv); | |
852 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
853 | int (*init_tx)(struct mlx5e_priv *priv); | |
854 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
855 | void (*enable)(struct mlx5e_priv *priv); | |
856 | void (*disable)(struct mlx5e_priv *priv); | |
857 | void (*update_stats)(struct mlx5e_priv *priv); | |
7ca42c80 | 858 | void (*update_carrier)(struct mlx5e_priv *priv); |
a43b25da | 859 | int (*max_nch)(struct mlx5_core_dev *mdev); |
20fd0c19 SM |
860 | struct { |
861 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
862 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
863 | } rx_handlers; | |
2a5e7a13 HN |
864 | void (*netdev_registered_init)(struct mlx5e_priv *priv); |
865 | void (*netdev_registered_remove)(struct mlx5e_priv *priv); | |
a43b25da SM |
866 | int max_tc; |
867 | }; | |
868 | ||
665bc539 GP |
869 | void mlx5e_build_ptys2ethtool_map(void); |
870 | ||
f62b8bb8 | 871 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
4f49dec9 AD |
872 | struct net_device *sb_dev, |
873 | select_queue_fallback_t fallback); | |
f62b8bb8 | 874 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); |
bf239741 IL |
875 | netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
876 | struct mlx5e_tx_wqe *wqe, u16 pi); | |
f62b8bb8 AV |
877 | |
878 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
879 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
880 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 881 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 882 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
31391048 | 883 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
461017cb | 884 | |
2ccb0a79 TT |
885 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); |
886 | bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, | |
887 | struct mlx5e_params *params); | |
888 | ||
159d2131 | 889 | void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info); |
4415a031 TT |
890 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
891 | bool recycle); | |
2f48af12 | 892 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 893 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 894 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
7cc6d77b | 895 | bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq); |
6cd392a0 DJ |
896 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
897 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
619a8f2a TT |
898 | struct sk_buff * |
899 | mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
900 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
901 | struct sk_buff * | |
902 | mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
903 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
904 | struct sk_buff * |
905 | mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
906 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
907 | struct sk_buff * | |
908 | mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
909 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
f62b8bb8 | 910 | |
19386177 | 911 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
f62b8bb8 | 912 | |
acff797c MG |
913 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
914 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 915 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 916 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
917 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
918 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
919 | u64 *buf); | |
f913a72a MG |
920 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
921 | int location); | |
922 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
923 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
924 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
925 | struct ethtool_rx_flow_spec *fs); | |
926 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
927 | int location); | |
928 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
929 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
930 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
931 | ||
1170fbd8 FD |
932 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
933 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 934 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 935 | |
f62b8bb8 AV |
936 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
937 | u16 vid); | |
938 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
939 | u16 vid); | |
2b52a283 GP |
940 | void mlx5e_enable_cvlan_filter(struct mlx5e_priv *priv); |
941 | void mlx5e_disable_cvlan_filter(struct mlx5e_priv *priv); | |
237f258c | 942 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
f62b8bb8 | 943 | |
a5f97fee SM |
944 | struct mlx5e_redirect_rqt_param { |
945 | bool is_rss; | |
946 | union { | |
947 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
948 | struct { | |
949 | u8 hfunc; | |
950 | struct mlx5e_channels *channels; | |
951 | } rss; /* RSS data */ | |
952 | }; | |
953 | }; | |
954 | ||
955 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
956 | struct mlx5e_redirect_rqt_param rrp); | |
6a9764ef SM |
957 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
958 | enum mlx5e_traffic_types tt, | |
7b3722fa | 959 | void *tirc, bool inner); |
2d75b2bc | 960 | |
f62b8bb8 AV |
961 | int mlx5e_open_locked(struct net_device *netdev); |
962 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
963 | |
964 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
965 | struct mlx5e_channels *chs); | |
966 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 SM |
967 | |
968 | /* Function pointer to be used to modify WH settings while | |
969 | * switching channels | |
970 | */ | |
971 | typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); | |
55c2503d | 972 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
973 | struct mlx5e_channels *new_chs, |
974 | mlx5e_fp_hw_modify hw_modify); | |
603f4a45 SM |
975 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
976 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
55c2503d | 977 | |
d4b6c488 | 978 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba | 979 | int num_channels); |
0088cbbc TG |
980 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, |
981 | u8 cq_period_mode); | |
9908aa29 TT |
982 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
983 | u8 cq_period_mode); | |
2ccb0a79 | 984 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params); |
696a97cf | 985 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
2a0f561b | 986 | struct mlx5e_params *params); |
9908aa29 | 987 | |
7b3722fa GP |
988 | static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev) |
989 | { | |
990 | return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) && | |
991 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version)); | |
992 | } | |
993 | ||
bf239741 IL |
994 | static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq, |
995 | struct mlx5e_tx_wqe **wqe, | |
996 | u16 *pi) | |
997 | { | |
ddf385e3 | 998 | struct mlx5_wq_cyc *wq = &sq->wq; |
bf239741 | 999 | |
ddf385e3 | 1000 | *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
bf239741 IL |
1001 | *wqe = mlx5_wq_cyc_get_wqe(wq, *pi); |
1002 | memset(*wqe, 0, sizeof(**wqe)); | |
1003 | } | |
1004 | ||
864b2d71 SM |
1005 | static inline |
1006 | struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) | |
f62b8bb8 | 1007 | { |
ddf385e3 | 1008 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc); |
864b2d71 SM |
1009 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); |
1010 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
1011 | ||
1012 | memset(cseg, 0, sizeof(*cseg)); | |
1013 | ||
1014 | cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); | |
1015 | cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); | |
1016 | ||
1017 | (*pc)++; | |
1018 | ||
1019 | return wqe; | |
1020 | } | |
1021 | ||
1022 | static inline | |
1023 | void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, | |
1024 | void __iomem *uar_map, | |
1025 | struct mlx5_wqe_ctrl_seg *ctrl) | |
1026 | { | |
1027 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
f62b8bb8 AV |
1028 | /* ensure wqe is visible to device before updating doorbell record */ |
1029 | dma_wmb(); | |
1030 | ||
864b2d71 | 1031 | *wq->db = cpu_to_be32(pc); |
f62b8bb8 AV |
1032 | |
1033 | /* ensure doorbell record is visible to device before ringing the | |
1034 | * doorbell | |
1035 | */ | |
1036 | wmb(); | |
f62b8bb8 | 1037 | |
864b2d71 | 1038 | mlx5_write64((__be32 *)ctrl, uar_map, NULL); |
f62b8bb8 AV |
1039 | } |
1040 | ||
1041 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
1042 | { | |
1043 | struct mlx5_core_cq *mcq; | |
1044 | ||
1045 | mcq = &cq->mcq; | |
5fe9dec0 | 1046 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
1047 | } |
1048 | ||
1049 | extern const struct ethtool_ops mlx5e_ethtool_ops; | |
08fb1dac SM |
1050 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
1051 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
1052 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 1053 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
2a5e7a13 HN |
1054 | void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv); |
1055 | void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv); | |
08fb1dac SM |
1056 | #endif |
1057 | ||
1cabe6b0 MG |
1058 | #ifndef CONFIG_RFS_ACCEL |
1059 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
1060 | { | |
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
1065 | |
1066 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
1067 | { | |
9eb78923 | 1068 | return -EOPNOTSUPP; |
45bf454a MG |
1069 | } |
1070 | ||
1071 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
1072 | { | |
9eb78923 | 1073 | return -EOPNOTSUPP; |
45bf454a | 1074 | } |
1cabe6b0 MG |
1075 | #else |
1076 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
1077 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
1078 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
1079 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
1080 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
1081 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
1082 | #endif |
1083 | ||
724b2aa1 HHZ |
1084 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
1085 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
1086 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
1087 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
1088 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1089 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 1090 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 1091 | |
bc81b9d3 | 1092 | /* common netdev helpers */ |
8f493ffd SM |
1093 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
1094 | ||
1095 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv); | |
1096 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv); | |
1097 | ||
cb67b832 | 1098 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); |
8f493ffd | 1099 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1100 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); |
1101 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
8f493ffd SM |
1102 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); |
1103 | ||
1ae1df3a OG |
1104 | struct ttc_params { |
1105 | struct mlx5_flow_table_attr ft_attr; | |
1106 | u32 any_tt_tirn; | |
1107 | u32 indir_tirn[MLX5E_NUM_INDIR_TIRS]; | |
1108 | struct mlx5e_ttc_table *inner_ttc; | |
1109 | }; | |
1110 | ||
1111 | void mlx5e_set_ttc_basic_params(struct mlx5e_priv *priv, struct ttc_params *ttc_params); | |
1112 | void mlx5e_set_ttc_ft_params(struct ttc_params *ttc_params); | |
1113 | void mlx5e_set_inner_ttc_ft_params(struct ttc_params *ttc_params); | |
1114 | ||
1115 | int mlx5e_create_ttc_table(struct mlx5e_priv *priv, struct ttc_params *params, | |
1116 | struct mlx5e_ttc_table *ttc); | |
1117 | void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv, | |
1118 | struct mlx5e_ttc_table *ttc); | |
bc81b9d3 | 1119 | |
1ae1df3a OG |
1120 | int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv, struct ttc_params *params, |
1121 | struct mlx5e_ttc_table *ttc); | |
1122 | void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv, | |
1123 | struct mlx5e_ttc_table *ttc); | |
458821c7 | 1124 | |
5426a0b2 SM |
1125 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
1126 | u32 underlay_qpn, u32 *tisn); | |
1127 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); | |
1128 | ||
cb67b832 HHZ |
1129 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
1130 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
1131 | int mlx5e_close(struct net_device *netdev); | |
1132 | int mlx5e_open(struct net_device *netdev); | |
1133 | void mlx5e_update_stats_work(struct work_struct *work); | |
cb67b832 | 1134 | |
3f6d08d1 OG |
1135 | int mlx5e_bits_invert(unsigned long a, int size); |
1136 | ||
250a42b6 AN |
1137 | typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv); |
1138 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, | |
1139 | change_hw_mtu_cb set_mtu_cb); | |
1140 | ||
076b0936 ES |
1141 | /* ethtool helpers */ |
1142 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1143 | struct ethtool_drvinfo *drvinfo); | |
1144 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1145 | uint32_t stringset, uint8_t *data); | |
1146 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1147 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1148 | struct ethtool_stats *stats, u64 *data); | |
1149 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
1150 | struct ethtool_ringparam *param); | |
1151 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
1152 | struct ethtool_ringparam *param); | |
1153 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1154 | struct ethtool_channels *ch); | |
1155 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1156 | struct ethtool_channels *ch); | |
1157 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
1158 | struct ethtool_coalesce *coal); | |
1159 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
1160 | struct ethtool_coalesce *coal); | |
3844b07e FD |
1161 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1162 | struct ethtool_ts_info *info); | |
3ffaabec OG |
1163 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1164 | struct ethtool_flash *flash); | |
076b0936 | 1165 | |
2c3b5bee SM |
1166 | /* mlx5e generic netdev management API */ |
1167 | struct net_device* | |
1168 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, | |
1169 | void *ppriv); | |
1170 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); | |
1171 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1172 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
8f493ffd SM |
1173 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
1174 | struct mlx5e_params *params, | |
472a1e44 | 1175 | u16 max_channels, u16 mtu); |
fbcb127e | 1176 | u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev); |
9a317425 | 1177 | void mlx5e_rx_dim_work(struct work_struct *work); |
cbce4f44 | 1178 | void mlx5e_tx_dim_work(struct work_struct *work); |
1afff42c | 1179 | #endif /* __MLX5_EN_H__ */ |