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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
48935bbb | 40 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
41 | #include <linux/mlx5/driver.h> |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/cq.h> | |
ada68c31 | 44 | #include <linux/mlx5/port.h> |
d18a9470 | 45 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 46 | #include <linux/mlx5/transobj.h> |
1ae1df3a | 47 | #include <linux/mlx5/fs.h> |
e8f887ac | 48 | #include <linux/rhashtable.h> |
cb67b832 | 49 | #include <net/switchdev.h> |
0ddf5432 | 50 | #include <net/xdp.h> |
4c4dbb4a | 51 | #include <linux/net_dim.h> |
8ff57c18 | 52 | #include <linux/bits.h> |
f62b8bb8 | 53 | #include "wq.h" |
f62b8bb8 | 54 | #include "mlx5_core.h" |
9218b44d | 55 | #include "en_stats.h" |
fe6d86b3 | 56 | #include "en/fs.h" |
f62b8bb8 | 57 | |
4d8fcf21 | 58 | extern const struct net_device_ops mlx5e_netdev_ops; |
60bbf7ee JDB |
59 | struct page_pool; |
60 | ||
bb909416 IL |
61 | #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) |
62 | #define MLX5E_METADATA_ETHER_LEN 8 | |
63 | ||
1cabe6b0 MG |
64 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
65 | ||
c139dbfd ES |
66 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
67 | ||
472a1e44 TT |
68 | #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) |
69 | #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) | |
d8bec2b2 | 70 | |
0696d608 | 71 | #define MLX5E_MAX_PRIORITY 8 |
2a5e7a13 | 72 | #define MLX5E_MAX_DSCP 64 |
f62b8bb8 AV |
73 | #define MLX5E_MAX_NUM_TC 8 |
74 | ||
1bfecfca | 75 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
76 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
77 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 78 | |
94816278 TT |
79 | #define MLX5E_RX_MAX_HEAD (256) |
80 | ||
f32f5bd2 DJ |
81 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
82 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
83 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
84 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
94816278 TT |
85 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ |
86 | MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) | |
f32f5bd2 | 87 | |
7e426671 | 88 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
89 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
90 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
91 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
92 | |
93 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
73281b78 | 94 | #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) |
b8a98a4c | 95 | #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS)) |
73281b78 TT |
96 | #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) |
97 | #define MLX5E_MAX_RQ_NUM_MTTS \ | |
98 | ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ | |
99 | #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) | |
100 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ | |
101 | (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) | |
102 | #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ | |
103 | (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ | |
104 | (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) | |
105 | ||
069d1146 TT |
106 | #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) |
107 | #define MLX5E_LOG_MAX_RX_WQE_BULK \ | |
108 | (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) | |
109 | ||
73281b78 TT |
110 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
111 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
112 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
113 | ||
069d1146 | 114 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) |
73281b78 TT |
115 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
116 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ | |
117 | MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) | |
118 | ||
119 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 | |
fe4c988b | 120 | |
d9a40271 | 121 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
122 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
123 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
124 | ||
f62b8bb8 | 125 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 126 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
127 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
128 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 129 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
130 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
131 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 132 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 133 | |
936896e9 AS |
134 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
135 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 136 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 137 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 138 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 | 139 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
db75373c | 140 | #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ |
f62b8bb8 | 141 | |
ea3886ca TT |
142 | #define MLX5E_UMR_WQE_INLINE_SZ \ |
143 | (sizeof(struct mlx5e_umr_wqe) + \ | |
144 | ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ | |
145 | MLX5_UMR_MTT_ALIGNMENT)) | |
146 | #define MLX5E_UMR_WQEBBS \ | |
147 | (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) | |
2f48af12 | 148 | |
79c48764 GP |
149 | #define MLX5E_MSG_LEVEL NETIF_MSG_LINK |
150 | ||
151 | #define mlx5e_dbg(mlevel, priv, format, ...) \ | |
152 | do { \ | |
153 | if (NETIF_MSG_##mlevel & (priv)->msglevel) \ | |
154 | netdev_warn(priv->netdev, format, \ | |
155 | ##__VA_ARGS__); \ | |
156 | } while (0) | |
157 | ||
158 | ||
461017cb TT |
159 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
160 | { | |
161 | switch (wq_type) { | |
162 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
163 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
164 | wq_size / 2); | |
165 | default: | |
166 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
167 | wq_size / 2); | |
168 | } | |
169 | } | |
170 | ||
779d986d | 171 | /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ |
48935bbb SM |
172 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
173 | { | |
174 | return is_kdump_kernel() ? | |
175 | MLX5E_MIN_NUM_CHANNELS : | |
f2f3df55 | 176 | min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS); |
48935bbb SM |
177 | } |
178 | ||
779d986d FD |
179 | /* Use this function to get max num channels after netdev was created */ |
180 | static inline int mlx5e_get_netdev_max_channels(struct net_device *netdev) | |
181 | { | |
182 | return min_t(unsigned int, netdev->num_rx_queues, | |
183 | netdev->num_tx_queues); | |
184 | } | |
185 | ||
2f48af12 TT |
186 | struct mlx5e_tx_wqe { |
187 | struct mlx5_wqe_ctrl_seg ctrl; | |
188 | struct mlx5_wqe_eth_seg eth; | |
043dc78e | 189 | struct mlx5_wqe_data_seg data[0]; |
2f48af12 TT |
190 | }; |
191 | ||
99cbfa93 | 192 | struct mlx5e_rx_wqe_ll { |
2f48af12 | 193 | struct mlx5_wqe_srq_next_seg next; |
99cbfa93 TT |
194 | struct mlx5_wqe_data_seg data[0]; |
195 | }; | |
196 | ||
197 | struct mlx5e_rx_wqe_cyc { | |
198 | struct mlx5_wqe_data_seg data[0]; | |
2f48af12 | 199 | }; |
86d722ad | 200 | |
bc77b240 TT |
201 | struct mlx5e_umr_wqe { |
202 | struct mlx5_wqe_ctrl_seg ctrl; | |
203 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
204 | struct mlx5_mkey_seg mkc; | |
ea3886ca | 205 | struct mlx5_mtt inline_mtts[0]; |
bc77b240 TT |
206 | }; |
207 | ||
d605d668 KH |
208 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
209 | ||
4e59e288 | 210 | enum mlx5e_priv_flag { |
8ff57c18 TT |
211 | MLX5E_PFLAG_RX_CQE_BASED_MODER, |
212 | MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
213 | MLX5E_PFLAG_RX_CQE_COMPRESS, | |
214 | MLX5E_PFLAG_RX_STRIDING_RQ, | |
215 | MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, | |
6277053a | 216 | MLX5E_PFLAG_XDP_TX_MPWQE, |
8ff57c18 | 217 | MLX5E_NUM_PFLAGS, /* Keep last */ |
4e59e288 GP |
218 | }; |
219 | ||
6a9764ef | 220 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
221 | do { \ |
222 | if (enable) \ | |
8ff57c18 | 223 | (params)->pflags |= BIT(pflag); \ |
59ece1c9 | 224 | else \ |
8ff57c18 | 225 | (params)->pflags &= ~(BIT(pflag)); \ |
4e59e288 GP |
226 | } while (0) |
227 | ||
8ff57c18 | 228 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) |
59ece1c9 | 229 | |
08fb1dac SM |
230 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
231 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
232 | #endif |
233 | ||
f62b8bb8 AV |
234 | struct mlx5e_params { |
235 | u8 log_sq_size; | |
461017cb | 236 | u8 rq_wq_type; |
73281b78 | 237 | u8 log_rq_mtu_frames; |
f62b8bb8 | 238 | u16 num_channels; |
f62b8bb8 | 239 | u8 num_tc; |
9bcc8606 | 240 | bool rx_cqe_compress_def; |
69dad68d | 241 | bool tunneled_offload_en; |
8960b389 TG |
242 | struct dim_cq_moder rx_cq_moderation; |
243 | struct dim_cq_moder tx_cq_moderation; | |
f62b8bb8 | 244 | bool lro_en; |
cff92d7c | 245 | u8 tx_min_inline_mode; |
36350114 | 246 | bool vlan_strip_disable; |
102722fc | 247 | bool scatter_fcs_en; |
9a317425 | 248 | bool rx_dim_enabled; |
cbce4f44 | 249 | bool tx_dim_enabled; |
2b029556 | 250 | u32 lro_timeout; |
59ece1c9 | 251 | u32 pflags; |
6a9764ef | 252 | struct bpf_prog *xdp_prog; |
472a1e44 TT |
253 | unsigned int sw_mtu; |
254 | int hard_mtu; | |
f62b8bb8 AV |
255 | }; |
256 | ||
3a6a931d HN |
257 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
258 | struct mlx5e_cee_config { | |
259 | /* bw pct for priority group */ | |
260 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
261 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
262 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
263 | bool pfc_enable; | |
264 | }; | |
265 | ||
266 | enum { | |
267 | MLX5_DCB_CHG_RESET, | |
268 | MLX5_DCB_NO_CHG, | |
269 | MLX5_DCB_CHG_NO_RESET, | |
270 | }; | |
271 | ||
272 | struct mlx5e_dcbx { | |
e207b7e9 | 273 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 274 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
2a5e7a13 | 275 | u8 dscp_app_cnt; |
820c2c5e HN |
276 | |
277 | /* The only setting that cannot be read from FW */ | |
278 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
9e10bf1d | 279 | u8 cap; |
0696d608 HN |
280 | |
281 | /* Buffer configuration */ | |
ecdf2dad | 282 | bool manual_buffer; |
0696d608 HN |
283 | u32 cable_len; |
284 | u32 xoff; | |
3a6a931d | 285 | }; |
2a5e7a13 HN |
286 | |
287 | struct mlx5e_dcbx_dp { | |
288 | u8 dscp2prio[MLX5E_MAX_DSCP]; | |
289 | u8 trust_state; | |
290 | }; | |
3a6a931d HN |
291 | #endif |
292 | ||
f62b8bb8 | 293 | enum { |
c0f1147d | 294 | MLX5E_RQ_STATE_ENABLED, |
cb3c7fd4 | 295 | MLX5E_RQ_STATE_AM, |
b856df28 | 296 | MLX5E_RQ_STATE_NO_CSUM_COMPLETE, |
f62b8bb8 AV |
297 | }; |
298 | ||
f62b8bb8 AV |
299 | struct mlx5e_cq { |
300 | /* data path - accessed per cqe */ | |
301 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
302 | |
303 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 304 | u16 event_ctr; |
f62b8bb8 AV |
305 | struct napi_struct *napi; |
306 | struct mlx5_core_cq mcq; | |
307 | struct mlx5e_channel *channel; | |
308 | ||
79d356ef TT |
309 | /* control */ |
310 | struct mlx5_core_dev *mdev; | |
311 | struct mlx5_wq_ctrl wq_ctrl; | |
312 | } ____cacheline_aligned_in_smp; | |
313 | ||
314 | struct mlx5e_cq_decomp { | |
7219ab34 TT |
315 | /* cqe decompression */ |
316 | struct mlx5_cqe64 title; | |
317 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
318 | u8 mini_arr_idx; | |
79d356ef TT |
319 | u16 left; |
320 | u16 wqe_counter; | |
f62b8bb8 AV |
321 | } ____cacheline_aligned_in_smp; |
322 | ||
eba2db2b | 323 | struct mlx5e_tx_wqe_info { |
77bdf895 | 324 | struct sk_buff *skb; |
eba2db2b SM |
325 | u32 num_bytes; |
326 | u8 num_wqebbs; | |
327 | u8 num_dma; | |
328 | }; | |
329 | ||
330 | enum mlx5e_dma_map_type { | |
331 | MLX5E_DMA_MAP_SINGLE, | |
332 | MLX5E_DMA_MAP_PAGE | |
333 | }; | |
334 | ||
335 | struct mlx5e_sq_dma { | |
336 | dma_addr_t addr; | |
337 | u32 size; | |
338 | enum mlx5e_dma_map_type type; | |
339 | }; | |
340 | ||
341 | enum { | |
342 | MLX5E_SQ_STATE_ENABLED, | |
db75373c | 343 | MLX5E_SQ_STATE_RECOVERING, |
2ac9cfe7 | 344 | MLX5E_SQ_STATE_IPSEC, |
cbce4f44 | 345 | MLX5E_SQ_STATE_AM, |
bf239741 | 346 | MLX5E_SQ_STATE_TLS, |
eba2db2b SM |
347 | }; |
348 | ||
349 | struct mlx5e_sq_wqe_info { | |
350 | u8 opcode; | |
eba2db2b | 351 | }; |
2f48af12 | 352 | |
31391048 | 353 | struct mlx5e_txqsq { |
eba2db2b SM |
354 | /* data path */ |
355 | ||
356 | /* dirtied @completion */ | |
357 | u16 cc; | |
358 | u32 dma_fifo_cc; | |
8960b389 | 359 | struct dim dim; /* Adaptive Moderation */ |
eba2db2b SM |
360 | |
361 | /* dirtied @xmit */ | |
362 | u16 pc ____cacheline_aligned_in_smp; | |
363 | u32 dma_fifo_pc; | |
eba2db2b SM |
364 | |
365 | struct mlx5e_cq cq; | |
366 | ||
eba2db2b SM |
367 | /* read only */ |
368 | struct mlx5_wq_cyc wq; | |
369 | u32 dma_fifo_mask; | |
05909bab | 370 | struct mlx5e_sq_stats *stats; |
9a3956da TT |
371 | struct { |
372 | struct mlx5e_sq_dma *dma_fifo; | |
373 | struct mlx5e_tx_wqe_info *wqe_info; | |
374 | } db; | |
eba2db2b SM |
375 | void __iomem *uar_map; |
376 | struct netdev_queue *txq; | |
377 | u32 sqn; | |
eba2db2b | 378 | u8 min_inline_mode; |
eba2db2b | 379 | struct device *pdev; |
eba2db2b SM |
380 | __be32 mkey_be; |
381 | unsigned long state; | |
7c39afb3 FD |
382 | struct hwtstamp_config *tstamp; |
383 | struct mlx5_clock *clock; | |
eba2db2b SM |
384 | |
385 | /* control path */ | |
386 | struct mlx5_wq_ctrl wq_ctrl; | |
387 | struct mlx5e_channel *channel; | |
acc6c595 | 388 | int txq_ix; |
eba2db2b | 389 | u32 rate_limit; |
de8650a8 | 390 | struct work_struct recover_work; |
31391048 SM |
391 | } ____cacheline_aligned_in_smp; |
392 | ||
c94e4f11 TT |
393 | struct mlx5e_dma_info { |
394 | struct page *page; | |
395 | dma_addr_t addr; | |
396 | }; | |
397 | ||
398 | struct mlx5e_xdp_info { | |
399 | struct xdp_frame *xdpf; | |
400 | dma_addr_t dma_addr; | |
401 | struct mlx5e_dma_info di; | |
402 | }; | |
403 | ||
fea28dd6 TT |
404 | struct mlx5e_xdp_info_fifo { |
405 | struct mlx5e_xdp_info *xi; | |
406 | u32 *cc; | |
407 | u32 *pc; | |
408 | u32 mask; | |
409 | }; | |
410 | ||
1feeab80 TT |
411 | struct mlx5e_xdp_wqe_info { |
412 | u8 num_wqebbs; | |
c2273219 | 413 | u8 num_pkts; |
1feeab80 TT |
414 | }; |
415 | ||
5e0d2eef TT |
416 | struct mlx5e_xdp_mpwqe { |
417 | /* Current MPWQE session */ | |
418 | struct mlx5e_tx_wqe *wqe; | |
419 | u8 ds_count; | |
c2273219 | 420 | u8 pkt_count; |
5e0d2eef | 421 | u8 max_ds_count; |
c2273219 SA |
422 | u8 complete; |
423 | u8 inline_on; | |
5e0d2eef TT |
424 | }; |
425 | ||
426 | struct mlx5e_xdpsq; | |
427 | typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq*, | |
428 | struct mlx5e_xdp_info*); | |
31391048 SM |
429 | struct mlx5e_xdpsq { |
430 | /* data path */ | |
431 | ||
dac0d15f | 432 | /* dirtied @completion */ |
fea28dd6 | 433 | u32 xdpi_fifo_cc; |
31391048 | 434 | u16 cc; |
31391048 | 435 | |
dac0d15f | 436 | /* dirtied @xmit */ |
fea28dd6 TT |
437 | u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; |
438 | u16 pc; | |
b8180392 | 439 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
5e0d2eef | 440 | struct mlx5e_xdp_mpwqe mpwqe; |
31391048 | 441 | |
dac0d15f | 442 | struct mlx5e_cq cq; |
31391048 SM |
443 | |
444 | /* read only */ | |
445 | struct mlx5_wq_cyc wq; | |
890388ad | 446 | struct mlx5e_xdpsq_stats *stats; |
5e0d2eef | 447 | mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; |
dac0d15f | 448 | struct { |
1feeab80 | 449 | struct mlx5e_xdp_wqe_info *wqe_info; |
fea28dd6 | 450 | struct mlx5e_xdp_info_fifo xdpi_fifo; |
dac0d15f | 451 | } db; |
31391048 SM |
452 | void __iomem *uar_map; |
453 | u32 sqn; | |
454 | struct device *pdev; | |
455 | __be32 mkey_be; | |
456 | u8 min_inline_mode; | |
457 | unsigned long state; | |
c94e4f11 | 458 | unsigned int hw_mtu; |
31391048 SM |
459 | |
460 | /* control path */ | |
461 | struct mlx5_wq_ctrl wq_ctrl; | |
462 | struct mlx5e_channel *channel; | |
463 | } ____cacheline_aligned_in_smp; | |
464 | ||
465 | struct mlx5e_icosq { | |
466 | /* data path */ | |
fd9b4be8 TT |
467 | u16 cc; |
468 | u16 pc; | |
31391048 | 469 | |
fd9b4be8 | 470 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
31391048 SM |
471 | struct mlx5e_cq cq; |
472 | ||
473 | /* write@xmit, read@completion */ | |
474 | struct { | |
475 | struct mlx5e_sq_wqe_info *ico_wqe; | |
476 | } db; | |
477 | ||
478 | /* read only */ | |
479 | struct mlx5_wq_cyc wq; | |
480 | void __iomem *uar_map; | |
481 | u32 sqn; | |
31391048 SM |
482 | unsigned long state; |
483 | ||
484 | /* control path */ | |
485 | struct mlx5_wq_ctrl wq_ctrl; | |
486 | struct mlx5e_channel *channel; | |
eba2db2b SM |
487 | } ____cacheline_aligned_in_smp; |
488 | ||
864b2d71 SM |
489 | static inline bool |
490 | mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) | |
eba2db2b | 491 | { |
ddf385e3 | 492 | return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc); |
eba2db2b | 493 | } |
6cd392a0 | 494 | |
accd5883 | 495 | struct mlx5e_wqe_frag_info { |
069d1146 | 496 | struct mlx5e_dma_info *di; |
accd5883 | 497 | u32 offset; |
069d1146 | 498 | bool last_in_page; |
accd5883 TT |
499 | }; |
500 | ||
eba2db2b | 501 | struct mlx5e_umr_dma_info { |
eba2db2b | 502 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
eba2db2b SM |
503 | }; |
504 | ||
505 | struct mlx5e_mpw_info { | |
506 | struct mlx5e_umr_dma_info umr; | |
507 | u16 consumed_strides; | |
22f45398 | 508 | DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); |
eba2db2b SM |
509 | }; |
510 | ||
069d1146 TT |
511 | #define MLX5E_MAX_RX_FRAGS 4 |
512 | ||
4415a031 TT |
513 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
514 | * or a MPWQE (for striding rq). | |
515 | */ | |
516 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
517 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
29c2849e | 518 | #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) |
4415a031 TT |
519 | struct mlx5e_page_cache { |
520 | u32 head; | |
521 | u32 tail; | |
522 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
523 | }; | |
524 | ||
eba2db2b SM |
525 | struct mlx5e_rq; |
526 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
619a8f2a TT |
527 | typedef struct sk_buff * |
528 | (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
529 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
530 | typedef struct sk_buff * |
531 | (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
532 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
7cc6d77b | 533 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b SM |
534 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
535 | ||
121e8927 | 536 | enum mlx5e_rq_flag { |
f03590f7 | 537 | MLX5E_RQ_FLAG_XDP_XMIT, |
15143bf5 | 538 | MLX5E_RQ_FLAG_XDP_REDIRECT, |
121e8927 TT |
539 | }; |
540 | ||
069d1146 TT |
541 | struct mlx5e_rq_frag_info { |
542 | int frag_size; | |
543 | int frag_stride; | |
544 | }; | |
545 | ||
546 | struct mlx5e_rq_frags_info { | |
547 | struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; | |
548 | u8 num_frags; | |
549 | u8 log_num_frags; | |
550 | u8 wqe_bulk; | |
551 | }; | |
552 | ||
f62b8bb8 AV |
553 | struct mlx5e_rq { |
554 | /* data path */ | |
21c59685 | 555 | union { |
accd5883 | 556 | struct { |
069d1146 TT |
557 | struct mlx5_wq_cyc wq; |
558 | struct mlx5e_wqe_frag_info *frags; | |
559 | struct mlx5e_dma_info *di; | |
560 | struct mlx5e_rq_frags_info info; | |
561 | mlx5e_fp_skb_from_cqe skb_from_cqe; | |
accd5883 | 562 | } wqe; |
21c59685 | 563 | struct { |
422d4c40 | 564 | struct mlx5_wq_ll wq; |
b8a98a4c | 565 | struct mlx5e_umr_wqe umr_wqe; |
21c59685 | 566 | struct mlx5e_mpw_info *info; |
619a8f2a | 567 | mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; |
b45d8b50 | 568 | u16 num_strides; |
fd9b4be8 | 569 | u16 actual_wq_head; |
89e89f7a | 570 | u8 log_stride_sz; |
fd9b4be8 TT |
571 | u8 umr_in_progress; |
572 | u8 umr_last_bulk; | |
21c59685 SM |
573 | } mpwqe; |
574 | }; | |
1bfecfca | 575 | struct { |
b45d8b50 | 576 | u16 headroom; |
b5503b99 | 577 | u8 map_dir; /* dma map direction */ |
1bfecfca | 578 | } buff; |
f62b8bb8 | 579 | |
7cc6d77b | 580 | struct mlx5e_channel *channel; |
f62b8bb8 AV |
581 | struct device *pdev; |
582 | struct net_device *netdev; | |
05909bab | 583 | struct mlx5e_rq_stats *stats; |
f62b8bb8 | 584 | struct mlx5e_cq cq; |
79d356ef | 585 | struct mlx5e_cq_decomp cqd; |
4415a031 | 586 | struct mlx5e_page_cache page_cache; |
7c39afb3 FD |
587 | struct hwtstamp_config *tstamp; |
588 | struct mlx5_clock *clock; | |
4415a031 | 589 | |
2f48af12 | 590 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 591 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 592 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
593 | |
594 | unsigned long state; | |
595 | int ix; | |
0073c8f7 | 596 | unsigned int hw_mtu; |
f62b8bb8 | 597 | |
8960b389 | 598 | struct dim dim; /* Dynamic Interrupt Moderation */ |
31871f87 SM |
599 | |
600 | /* XDP */ | |
86994156 | 601 | struct bpf_prog *xdp_prog; |
31391048 | 602 | struct mlx5e_xdpsq xdpsq; |
121e8927 | 603 | DECLARE_BITMAP(flags, 8); |
60bbf7ee | 604 | struct page_pool *page_pool; |
cb3c7fd4 | 605 | |
f62b8bb8 AV |
606 | /* control */ |
607 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 608 | __be32 mkey_be; |
461017cb | 609 | u8 wq_type; |
f62b8bb8 | 610 | u32 rqn; |
a43b25da | 611 | struct mlx5_core_dev *mdev; |
ec8b9981 | 612 | struct mlx5_core_mkey umr_mkey; |
0ddf5432 JDB |
613 | |
614 | /* XDP read-mostly */ | |
615 | struct xdp_rxq_info xdp_rxq; | |
f62b8bb8 AV |
616 | } ____cacheline_aligned_in_smp; |
617 | ||
f62b8bb8 AV |
618 | struct mlx5e_channel { |
619 | /* data path */ | |
620 | struct mlx5e_rq rq; | |
31391048 SM |
621 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
622 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 623 | bool xdp; |
f62b8bb8 AV |
624 | struct napi_struct napi; |
625 | struct device *pdev; | |
626 | struct net_device *netdev; | |
627 | __be32 mkey_be; | |
628 | u8 num_tc; | |
f62b8bb8 | 629 | |
58b99ee3 TT |
630 | /* XDP_REDIRECT */ |
631 | struct mlx5e_xdpsq xdpsq; | |
632 | ||
a8c2eb15 TT |
633 | /* data path - accessed per napi poll */ |
634 | struct irq_desc *irq_desc; | |
05909bab | 635 | struct mlx5e_ch_stats *stats; |
f62b8bb8 AV |
636 | |
637 | /* control */ | |
638 | struct mlx5e_priv *priv; | |
a43b25da | 639 | struct mlx5_core_dev *mdev; |
7c39afb3 | 640 | struct hwtstamp_config *tstamp; |
f62b8bb8 | 641 | int ix; |
231243c8 | 642 | int cpu; |
149e566f | 643 | cpumask_var_t xps_cpumask; |
f62b8bb8 AV |
644 | }; |
645 | ||
ff9c852f SM |
646 | struct mlx5e_channels { |
647 | struct mlx5e_channel **c; | |
648 | unsigned int num; | |
6a9764ef | 649 | struct mlx5e_params params; |
ff9c852f SM |
650 | }; |
651 | ||
05909bab EBE |
652 | struct mlx5e_channel_stats { |
653 | struct mlx5e_ch_stats ch; | |
654 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
655 | struct mlx5e_rq_stats rq; | |
890388ad | 656 | struct mlx5e_xdpsq_stats rq_xdpsq; |
58b99ee3 | 657 | struct mlx5e_xdpsq_stats xdpsq; |
05909bab EBE |
658 | } ____cacheline_aligned_in_smp; |
659 | ||
acff797c | 660 | enum { |
acff797c MG |
661 | MLX5E_STATE_OPENED, |
662 | MLX5E_STATE_DESTROYING, | |
407e17b1 | 663 | MLX5E_STATE_XDP_TX_ENABLED, |
acff797c MG |
664 | }; |
665 | ||
398f3351 | 666 | struct mlx5e_rqt { |
1da36696 | 667 | u32 rqtn; |
398f3351 HHZ |
668 | bool enabled; |
669 | }; | |
670 | ||
671 | struct mlx5e_tir { | |
672 | u32 tirn; | |
673 | struct mlx5e_rqt rqt; | |
674 | struct list_head list; | |
1da36696 TT |
675 | }; |
676 | ||
acff797c MG |
677 | enum { |
678 | MLX5E_TC_PRIO = 0, | |
679 | MLX5E_NIC_PRIO | |
680 | }; | |
681 | ||
bbeb53b8 AL |
682 | struct mlx5e_rss_params { |
683 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
756c4160 | 684 | u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS]; |
bbeb53b8 AL |
685 | u8 toeplitz_hash_key[40]; |
686 | u8 hfunc; | |
687 | }; | |
688 | ||
de8650a8 EBE |
689 | struct mlx5e_modify_sq_param { |
690 | int curr_state; | |
691 | int next_state; | |
692 | int rl_update; | |
693 | int rl_index; | |
694 | }; | |
695 | ||
f62b8bb8 AV |
696 | struct mlx5e_priv { |
697 | /* priv data path fields - start */ | |
acc6c595 SM |
698 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
699 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
2a5e7a13 HN |
700 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
701 | struct mlx5e_dcbx_dp dcbx_dp; | |
702 | #endif | |
f62b8bb8 AV |
703 | /* priv data path fields - end */ |
704 | ||
79c48764 | 705 | u32 msglevel; |
f62b8bb8 AV |
706 | unsigned long state; |
707 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 708 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 709 | |
ff9c852f | 710 | struct mlx5e_channels channels; |
f62b8bb8 | 711 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 712 | struct mlx5e_rqt indir_rqt; |
724b2aa1 | 713 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
7b3722fa | 714 | struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; |
724b2aa1 | 715 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; |
bbeb53b8 | 716 | struct mlx5e_rss_params rss_params; |
507f0c81 | 717 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 718 | |
acff797c | 719 | struct mlx5e_flow_steering fs; |
f62b8bb8 | 720 | |
7bb29755 | 721 | struct workqueue_struct *wq; |
f62b8bb8 AV |
722 | struct work_struct update_carrier_work; |
723 | struct work_struct set_rx_mode_work; | |
3947ca18 | 724 | struct work_struct tx_timeout_work; |
cdeef2b1 | 725 | struct work_struct update_stats_work; |
5c7e8bbb ED |
726 | struct work_struct monitor_counters_work; |
727 | struct mlx5_nb monitor_counters_nb; | |
f62b8bb8 AV |
728 | |
729 | struct mlx5_core_dev *mdev; | |
730 | struct net_device *netdev; | |
731 | struct mlx5e_stats stats; | |
05909bab EBE |
732 | struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS]; |
733 | u8 max_opened_tc; | |
7c39afb3 | 734 | struct hwtstamp_config tstamp; |
7cbaf9a3 MS |
735 | u16 q_counter; |
736 | u16 drop_rq_q_counter; | |
7cffaddd SM |
737 | struct notifier_block events_nb; |
738 | ||
3a6a931d HN |
739 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
740 | struct mlx5e_dcbx dcbx; | |
741 | #endif | |
742 | ||
6bfd390b | 743 | const struct mlx5e_profile *profile; |
127ea380 | 744 | void *ppriv; |
547eede0 IT |
745 | #ifdef CONFIG_MLX5_EN_IPSEC |
746 | struct mlx5e_ipsec *ipsec; | |
747 | #endif | |
43585a41 IL |
748 | #ifdef CONFIG_MLX5_EN_TLS |
749 | struct mlx5e_tls *tls; | |
750 | #endif | |
de8650a8 | 751 | struct devlink_health_reporter *tx_reporter; |
f62b8bb8 AV |
752 | }; |
753 | ||
a43b25da | 754 | struct mlx5e_profile { |
182570b2 | 755 | int (*init)(struct mlx5_core_dev *mdev, |
a43b25da SM |
756 | struct net_device *netdev, |
757 | const struct mlx5e_profile *profile, void *ppriv); | |
758 | void (*cleanup)(struct mlx5e_priv *priv); | |
759 | int (*init_rx)(struct mlx5e_priv *priv); | |
760 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
761 | int (*init_tx)(struct mlx5e_priv *priv); | |
762 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
763 | void (*enable)(struct mlx5e_priv *priv); | |
764 | void (*disable)(struct mlx5e_priv *priv); | |
765 | void (*update_stats)(struct mlx5e_priv *priv); | |
7ca42c80 | 766 | void (*update_carrier)(struct mlx5e_priv *priv); |
20fd0c19 SM |
767 | struct { |
768 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
769 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
770 | } rx_handlers; | |
a43b25da SM |
771 | int max_tc; |
772 | }; | |
773 | ||
665bc539 GP |
774 | void mlx5e_build_ptys2ethtool_map(void); |
775 | ||
f62b8bb8 | 776 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
a350ecce | 777 | struct net_device *sb_dev); |
f62b8bb8 | 778 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); |
bf239741 | 779 | netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
3c31ff22 | 780 | struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more); |
f62b8bb8 | 781 | |
63d26b49 | 782 | void mlx5e_trigger_irq(struct mlx5e_icosq *sq); |
f62b8bb8 AV |
783 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); |
784 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
785 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 786 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 787 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
31391048 | 788 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
461017cb | 789 | |
2ccb0a79 TT |
790 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); |
791 | bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, | |
792 | struct mlx5e_params *params); | |
793 | ||
159d2131 | 794 | void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info); |
4415a031 TT |
795 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
796 | bool recycle); | |
2f48af12 | 797 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 798 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 799 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
7cc6d77b | 800 | bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq); |
6cd392a0 DJ |
801 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
802 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
619a8f2a TT |
803 | struct sk_buff * |
804 | mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
805 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
806 | struct sk_buff * | |
807 | mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
808 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
809 | struct sk_buff * |
810 | mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
811 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
812 | struct sk_buff * | |
813 | mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
814 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
f62b8bb8 | 815 | |
19386177 | 816 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
d9ee0491 | 817 | void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); |
b832d4fd | 818 | void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); |
f62b8bb8 | 819 | |
33cfaaa8 | 820 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
d605d668 KH |
821 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
822 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
823 | u64 *buf); | |
f62b8bb8 AV |
824 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
825 | ||
1170fbd8 FD |
826 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
827 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 828 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 829 | |
f62b8bb8 AV |
830 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
831 | u16 vid); | |
832 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
833 | u16 vid); | |
237f258c | 834 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
f62b8bb8 | 835 | |
a5f97fee SM |
836 | struct mlx5e_redirect_rqt_param { |
837 | bool is_rss; | |
838 | union { | |
839 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
840 | struct { | |
841 | u8 hfunc; | |
842 | struct mlx5e_channels *channels; | |
843 | } rss; /* RSS data */ | |
844 | }; | |
845 | }; | |
846 | ||
847 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
848 | struct mlx5e_redirect_rqt_param rrp); | |
bbeb53b8 | 849 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params, |
d930ac79 | 850 | const struct mlx5e_tirc_config *ttconfig, |
7b3722fa | 851 | void *tirc, bool inner); |
080d1b17 | 852 | void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen); |
d930ac79 | 853 | struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt); |
2d75b2bc | 854 | |
f62b8bb8 AV |
855 | int mlx5e_open_locked(struct net_device *netdev); |
856 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
857 | |
858 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
859 | struct mlx5e_channels *chs); | |
860 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 SM |
861 | |
862 | /* Function pointer to be used to modify WH settings while | |
863 | * switching channels | |
864 | */ | |
865 | typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); | |
484c1ada | 866 | int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); |
877662e2 TT |
867 | int mlx5e_safe_switch_channels(struct mlx5e_priv *priv, |
868 | struct mlx5e_channels *new_chs, | |
869 | mlx5e_fp_hw_modify hw_modify); | |
603f4a45 SM |
870 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
871 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
55c2503d | 872 | |
d4b6c488 | 873 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba | 874 | int num_channels); |
0088cbbc TG |
875 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, |
876 | u8 cq_period_mode); | |
9908aa29 TT |
877 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
878 | u8 cq_period_mode); | |
2ccb0a79 | 879 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params); |
696a97cf | 880 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
2a0f561b | 881 | struct mlx5e_params *params); |
9908aa29 | 882 | |
de8650a8 EBE |
883 | int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
884 | struct mlx5e_modify_sq_param *p); | |
885 | void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); | |
886 | void mlx5e_tx_disable_queue(struct netdev_queue *txq); | |
887 | ||
7b3722fa GP |
888 | static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev) |
889 | { | |
890 | return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) && | |
891 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version)); | |
892 | } | |
893 | ||
e3cfc7e6 MS |
894 | static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) |
895 | { | |
896 | return MLX5_CAP_ETH(mdev, swp) && | |
897 | MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); | |
898 | } | |
899 | ||
cac018b8 MS |
900 | struct mlx5e_swp_spec { |
901 | __be16 l3_proto; | |
902 | u8 l4_proto; | |
903 | u8 is_tun; | |
904 | __be16 tun_l3_proto; | |
905 | u8 tun_l4_proto; | |
906 | }; | |
907 | ||
908 | static inline void | |
909 | mlx5e_set_eseg_swp(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg, | |
910 | struct mlx5e_swp_spec *swp_spec) | |
911 | { | |
912 | /* SWP offsets are in 2-bytes words */ | |
913 | eseg->swp_outer_l3_offset = skb_network_offset(skb) / 2; | |
914 | if (swp_spec->l3_proto == htons(ETH_P_IPV6)) | |
915 | eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L3_IPV6; | |
916 | if (swp_spec->l4_proto) { | |
917 | eseg->swp_outer_l4_offset = skb_transport_offset(skb) / 2; | |
918 | if (swp_spec->l4_proto == IPPROTO_UDP) | |
919 | eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_UDP; | |
920 | } | |
921 | ||
922 | if (swp_spec->is_tun) { | |
923 | eseg->swp_inner_l3_offset = skb_inner_network_offset(skb) / 2; | |
924 | if (swp_spec->tun_l3_proto == htons(ETH_P_IPV6)) | |
925 | eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6; | |
926 | } else { /* typically for ipsec when xfrm mode != XFRM_MODE_TUNNEL */ | |
927 | eseg->swp_inner_l3_offset = skb_network_offset(skb) / 2; | |
928 | if (swp_spec->l3_proto == htons(ETH_P_IPV6)) | |
929 | eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6; | |
930 | } | |
931 | switch (swp_spec->tun_l4_proto) { | |
932 | case IPPROTO_UDP: | |
933 | eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L4_UDP; | |
934 | /* fall through */ | |
935 | case IPPROTO_TCP: | |
936 | eseg->swp_inner_l4_offset = skb_inner_transport_offset(skb) / 2; | |
937 | break; | |
938 | } | |
939 | } | |
940 | ||
bf239741 IL |
941 | static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq, |
942 | struct mlx5e_tx_wqe **wqe, | |
943 | u16 *pi) | |
944 | { | |
ddf385e3 | 945 | struct mlx5_wq_cyc *wq = &sq->wq; |
bf239741 | 946 | |
ddf385e3 | 947 | *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
bf239741 IL |
948 | *wqe = mlx5_wq_cyc_get_wqe(wq, *pi); |
949 | memset(*wqe, 0, sizeof(**wqe)); | |
950 | } | |
951 | ||
864b2d71 SM |
952 | static inline |
953 | struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) | |
f62b8bb8 | 954 | { |
ddf385e3 | 955 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc); |
864b2d71 SM |
956 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); |
957 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
958 | ||
959 | memset(cseg, 0, sizeof(*cseg)); | |
960 | ||
961 | cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); | |
962 | cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); | |
963 | ||
964 | (*pc)++; | |
965 | ||
966 | return wqe; | |
967 | } | |
968 | ||
969 | static inline | |
970 | void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, | |
971 | void __iomem *uar_map, | |
972 | struct mlx5_wqe_ctrl_seg *ctrl) | |
973 | { | |
974 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
f62b8bb8 AV |
975 | /* ensure wqe is visible to device before updating doorbell record */ |
976 | dma_wmb(); | |
977 | ||
864b2d71 | 978 | *wq->db = cpu_to_be32(pc); |
f62b8bb8 AV |
979 | |
980 | /* ensure doorbell record is visible to device before ringing the | |
981 | * doorbell | |
982 | */ | |
983 | wmb(); | |
f62b8bb8 | 984 | |
bbf29f61 | 985 | mlx5_write64((__be32 *)ctrl, uar_map); |
f62b8bb8 AV |
986 | } |
987 | ||
988 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
989 | { | |
990 | struct mlx5_core_cq *mcq; | |
991 | ||
992 | mcq = &cq->mcq; | |
5fe9dec0 | 993 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
994 | } |
995 | ||
996 | extern const struct ethtool_ops mlx5e_ethtool_ops; | |
08fb1dac SM |
997 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
998 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
999 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 1000 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
2a5e7a13 HN |
1001 | void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv); |
1002 | void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv); | |
08fb1dac SM |
1003 | #endif |
1004 | ||
724b2aa1 HHZ |
1005 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
1006 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
1007 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
1008 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
1009 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1010 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 1011 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 1012 | |
bc81b9d3 | 1013 | /* common netdev helpers */ |
1462e48d RD |
1014 | void mlx5e_create_q_counters(struct mlx5e_priv *priv); |
1015 | void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); | |
1016 | int mlx5e_open_drop_rq(struct mlx5e_priv *priv, | |
1017 | struct mlx5e_rq *drop_rq); | |
1018 | void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); | |
1019 | ||
8f493ffd SM |
1020 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
1021 | ||
46dc933c OG |
1022 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc); |
1023 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc); | |
8f493ffd | 1024 | |
cb67b832 | 1025 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); |
8f493ffd | 1026 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1027 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); |
1028 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
8f493ffd SM |
1029 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); |
1030 | ||
5426a0b2 SM |
1031 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
1032 | u32 underlay_qpn, u32 *tisn); | |
1033 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); | |
1034 | ||
cb67b832 | 1035 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
b36cdb42 | 1036 | void mlx5e_update_carrier(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1037 | int mlx5e_close(struct net_device *netdev); |
1038 | int mlx5e_open(struct net_device *netdev); | |
5c7e8bbb | 1039 | void mlx5e_update_ndo_stats(struct mlx5e_priv *priv); |
cb67b832 | 1040 | |
cdeef2b1 | 1041 | void mlx5e_queue_update_stats(struct mlx5e_priv *priv); |
3f6d08d1 OG |
1042 | int mlx5e_bits_invert(unsigned long a, int size); |
1043 | ||
250a42b6 | 1044 | typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv); |
d9ee0491 | 1045 | int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); |
250a42b6 AN |
1046 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, |
1047 | change_hw_mtu_cb set_mtu_cb); | |
1048 | ||
076b0936 ES |
1049 | /* ethtool helpers */ |
1050 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1051 | struct ethtool_drvinfo *drvinfo); | |
1052 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1053 | uint32_t stringset, uint8_t *data); | |
1054 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1055 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1056 | struct ethtool_stats *stats, u64 *data); | |
1057 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
1058 | struct ethtool_ringparam *param); | |
1059 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
1060 | struct ethtool_ringparam *param); | |
1061 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1062 | struct ethtool_channels *ch); | |
1063 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1064 | struct ethtool_channels *ch); | |
1065 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
1066 | struct ethtool_coalesce *coal); | |
1067 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
1068 | struct ethtool_coalesce *coal); | |
371289b6 OG |
1069 | int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, |
1070 | struct ethtool_link_ksettings *link_ksettings); | |
1071 | int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, | |
1072 | const struct ethtool_link_ksettings *link_ksettings); | |
a5355de8 OG |
1073 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); |
1074 | u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); | |
3844b07e FD |
1075 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1076 | struct ethtool_ts_info *info); | |
3ffaabec OG |
1077 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1078 | struct ethtool_flash *flash); | |
371289b6 OG |
1079 | void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, |
1080 | struct ethtool_pauseparam *pauseparam); | |
1081 | int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, | |
1082 | struct ethtool_pauseparam *pauseparam); | |
076b0936 | 1083 | |
2c3b5bee | 1084 | /* mlx5e generic netdev management API */ |
519a0bf5 SM |
1085 | int mlx5e_netdev_init(struct net_device *netdev, |
1086 | struct mlx5e_priv *priv, | |
1087 | struct mlx5_core_dev *mdev, | |
1088 | const struct mlx5e_profile *profile, | |
1089 | void *ppriv); | |
182570b2 | 1090 | void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv); |
2c3b5bee SM |
1091 | struct net_device* |
1092 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, | |
779d986d | 1093 | int nch, void *ppriv); |
2c3b5bee SM |
1094 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); |
1095 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1096 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
6d7ee2ed | 1097 | void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); |
8f493ffd | 1098 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
bbeb53b8 | 1099 | struct mlx5e_rss_params *rss_params, |
8f493ffd | 1100 | struct mlx5e_params *params, |
472a1e44 | 1101 | u16 max_channels, u16 mtu); |
749359f4 GT |
1102 | void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, |
1103 | struct mlx5e_params *params); | |
bbeb53b8 AL |
1104 | void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params, |
1105 | u16 num_channels); | |
fbcb127e | 1106 | u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev); |
9a317425 | 1107 | void mlx5e_rx_dim_work(struct work_struct *work); |
cbce4f44 | 1108 | void mlx5e_tx_dim_work(struct work_struct *work); |
073caf50 OG |
1109 | |
1110 | void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti); | |
1111 | void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti); | |
1112 | netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
1113 | struct net_device *netdev, | |
1114 | netdev_features_t features); | |
1115 | #ifdef CONFIG_MLX5_ESWITCH | |
1116 | int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); | |
1117 | int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); | |
1118 | int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); | |
1119 | int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); | |
1120 | #endif | |
1afff42c | 1121 | #endif /* __MLX5_EN_H__ */ |