]>
Commit | Line | Data |
---|---|---|
f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
48935bbb | 39 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
1ae1df3a | 46 | #include <linux/mlx5/fs.h> |
e8f887ac | 47 | #include <linux/rhashtable.h> |
18a2b7f9 | 48 | #include <net/udp_tunnel.h> |
cb67b832 | 49 | #include <net/switchdev.h> |
0ddf5432 | 50 | #include <net/xdp.h> |
4f75da36 | 51 | #include <linux/dim.h> |
8ff57c18 | 52 | #include <linux/bits.h> |
f62b8bb8 | 53 | #include "wq.h" |
f62b8bb8 | 54 | #include "mlx5_core.h" |
9218b44d | 55 | #include "en_stats.h" |
3f3ab178 | 56 | #include "en/dcbnl.h" |
fe6d86b3 | 57 | #include "en/fs.h" |
214baf22 | 58 | #include "en/qos.h" |
cef35af3 | 59 | #include "lib/hv_vhca.h" |
432119de | 60 | #include "lib/clock.h" |
3f22d6c7 | 61 | #include "en/rx_res.h" |
8bf30be7 | 62 | #include "en/selq.h" |
f62b8bb8 | 63 | |
4d8fcf21 | 64 | extern const struct net_device_ops mlx5e_netdev_ops; |
60bbf7ee JDB |
65 | struct page_pool; |
66 | ||
bb909416 IL |
67 | #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) |
68 | #define MLX5E_METADATA_ETHER_LEN 8 | |
69 | ||
c139dbfd ES |
70 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
71 | ||
472a1e44 TT |
72 | #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) |
73 | #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) | |
d8bec2b2 | 74 | |
f62b8bb8 | 75 | #define MLX5E_MAX_NUM_TC 8 |
ec60c458 | 76 | #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE |
f62b8bb8 | 77 | |
1bfecfca | 78 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
79 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
80 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 81 | |
94816278 | 82 | #define MLX5E_RX_MAX_HEAD (256) |
e5ca8fb0 BBI |
83 | #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9) |
84 | #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) | |
85 | #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) | |
86 | #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) | |
87 | #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) | |
94816278 | 88 | |
f32f5bd2 DJ |
89 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
90 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
91 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
92 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
94816278 TT |
93 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ |
94 | MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) | |
f32f5bd2 | 95 | |
e5a3cc83 MM |
96 | #define MLX5_MPWRQ_MAX_LOG_WQE_SZ 18 |
97 | ||
98 | /* Keep in sync with mlx5e_mpwrq_log_wqe_sz. | |
99 | * These are theoretical maximums, which can be further restricted by | |
100 | * capabilities. These values are used for static resource allocations and | |
101 | * sanity checks. | |
102 | * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE | |
103 | * size actually used at runtime, but it's not a problem when calculating static | |
104 | * array sizes. | |
105 | */ | |
02648b4b | 106 | #define MLX5_UMR_MAX_FLEX_SPACE \ |
e5a3cc83 | 107 | (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \ |
02648b4b | 108 | MLX5_UMR_FLEX_ALIGNMENT)) |
e5a3cc83 | 109 | #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \ |
02648b4b | 110 | rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt)) |
fe4c988b | 111 | |
73281b78 | 112 | #define MLX5E_MAX_RQ_NUM_MTTS \ |
9f123f74 | 113 | (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */ |
6470d2e7 | 114 | #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */ |
73281b78 | 115 | #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) |
73281b78 | 116 | |
069d1146 TT |
117 | #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) |
118 | #define MLX5E_LOG_MAX_RX_WQE_BULK \ | |
119 | (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) | |
120 | ||
73281b78 TT |
121 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
122 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
123 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
124 | ||
069d1146 | 125 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) |
73281b78 | 126 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
e5a3cc83 | 127 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd |
73281b78 TT |
128 | |
129 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 | |
fe4c988b | 130 | |
2b029556 SM |
131 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
132 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
133 | ||
f62b8bb8 | 134 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 135 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
136 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
137 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 138 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
139 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
140 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 141 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 142 | |
b4e029da | 143 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
6dd6eaf4 | 144 | #define MLX5E_MAX_NUM_CHANNELS 256 |
f62b8bb8 | 145 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
db05815b | 146 | #define MLX5E_TX_XSK_POLL_BUDGET 64 |
db75373c | 147 | #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ |
f62b8bb8 | 148 | |
d7b896ac BBI |
149 | #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\ |
150 | (sizeof(struct mlx5e_umr_wqe) +\ | |
151 | (sizeof(struct mlx5_klm) * (sgl_len))) | |
152 | ||
153 | #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \ | |
154 | (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB)) | |
155 | ||
156 | #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\ | |
157 | (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS)) | |
158 | ||
159 | #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\ | |
160 | (((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm)) | |
161 | ||
162 | #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\ | |
daab2e9c | 163 | ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT) |
d7b896ac | 164 | |
76c31e5f | 165 | #define MLX5E_MAX_KLM_PER_WQE(mdev) \ |
ed5c92ff | 166 | MLX5E_KLM_ENTRIES_PER_WQE(MLX5_SEND_WQE_BB * mlx5e_get_max_sq_aligned_wqebbs(mdev)) |
d7b896ac | 167 | |
214baf22 MM |
168 | #define mlx5e_state_dereference(priv, p) \ |
169 | rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) | |
170 | ||
82f9378c PH |
171 | enum mlx5e_devcom_events { |
172 | MPV_DEVCOM_MASTER_UP, | |
173 | MPV_DEVCOM_MASTER_DOWN, | |
174 | MPV_DEVCOM_IPSEC_MASTER_UP, | |
175 | MPV_DEVCOM_IPSEC_MASTER_DOWN, | |
176 | }; | |
177 | ||
45f171b1 MM |
178 | static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) |
179 | { | |
180 | if (mlx5_lag_is_lacp_owner(mdev)) | |
181 | return 1; | |
182 | ||
183 | return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); | |
184 | } | |
185 | ||
461017cb TT |
186 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
187 | { | |
188 | switch (wq_type) { | |
189 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
190 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
191 | wq_size / 2); | |
192 | default: | |
193 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
194 | wq_size / 2); | |
195 | } | |
196 | } | |
197 | ||
779d986d | 198 | /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ |
48935bbb SM |
199 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
200 | { | |
201 | return is_kdump_kernel() ? | |
202 | MLX5E_MIN_NUM_CHANNELS : | |
74a8dada AF |
203 | min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS, |
204 | (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size))); | |
48935bbb SM |
205 | } |
206 | ||
c27bd171 AL |
207 | /* The maximum WQE size can be retrieved by max_wqe_sz_sq in |
208 | * bytes units. Driver hardens the limitation to 1KB (16 | |
209 | * WQEBBs), unless firmware capability is stricter. | |
210 | */ | |
f060ccc2 | 211 | static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) |
c27bd171 | 212 | { |
f060ccc2 MM |
213 | BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX); |
214 | ||
215 | return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS, | |
216 | MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB); | |
c27bd171 AL |
217 | } |
218 | ||
ed5c92ff | 219 | static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev) |
76c31e5f AL |
220 | { |
221 | /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS. | |
222 | * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16, | |
223 | * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64) | |
224 | * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower | |
225 | * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be | |
226 | * cache-aligned. | |
227 | */ | |
ed5c92ff | 228 | u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev); |
677e78c8 | 229 | |
ed5c92ff | 230 | wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1); |
677e78c8 MM |
231 | #if L1_CACHE_BYTES >= 128 |
232 | wqebbs = ALIGN_DOWN(wqebbs, 2); | |
76c31e5f | 233 | #endif |
677e78c8 | 234 | return wqebbs; |
76c31e5f AL |
235 | } |
236 | ||
2f48af12 TT |
237 | struct mlx5e_tx_wqe { |
238 | struct mlx5_wqe_ctrl_seg ctrl; | |
7d0d0d86 | 239 | struct mlx5_wqe_eth_seg eth; |
ad518573 | 240 | struct mlx5_wqe_data_seg data[]; |
2f48af12 TT |
241 | }; |
242 | ||
99cbfa93 | 243 | struct mlx5e_rx_wqe_ll { |
2f48af12 | 244 | struct mlx5_wqe_srq_next_seg next; |
339ffae5 | 245 | struct mlx5_wqe_data_seg data[]; |
99cbfa93 TT |
246 | }; |
247 | ||
248 | struct mlx5e_rx_wqe_cyc { | |
7bd1099c | 249 | DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data); |
2f48af12 | 250 | }; |
86d722ad | 251 | |
bc77b240 TT |
252 | struct mlx5e_umr_wqe { |
253 | struct mlx5_wqe_ctrl_seg ctrl; | |
254 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
255 | struct mlx5_mkey_seg mkc; | |
d7b896ac | 256 | union { |
ad518573 KC |
257 | DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); |
258 | DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); | |
6470d2e7 | 259 | DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms); |
d7b896ac | 260 | }; |
bc77b240 TT |
261 | }; |
262 | ||
4e59e288 | 263 | enum mlx5e_priv_flag { |
8ff57c18 TT |
264 | MLX5E_PFLAG_RX_CQE_BASED_MODER, |
265 | MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
266 | MLX5E_PFLAG_RX_CQE_COMPRESS, | |
267 | MLX5E_PFLAG_RX_STRIDING_RQ, | |
268 | MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, | |
6277053a | 269 | MLX5E_PFLAG_XDP_TX_MPWQE, |
5af75c74 | 270 | MLX5E_PFLAG_SKB_TX_MPWQE, |
145e5637 | 271 | MLX5E_PFLAG_TX_PORT_TS, |
8ff57c18 | 272 | MLX5E_NUM_PFLAGS, /* Keep last */ |
4e59e288 GP |
273 | }; |
274 | ||
6a9764ef | 275 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
276 | do { \ |
277 | if (enable) \ | |
8ff57c18 | 278 | (params)->pflags |= BIT(pflag); \ |
59ece1c9 | 279 | else \ |
8ff57c18 | 280 | (params)->pflags &= ~(BIT(pflag)); \ |
4e59e288 GP |
281 | } while (0) |
282 | ||
8ff57c18 | 283 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) |
59ece1c9 | 284 | |
eaee12f0 KM |
285 | enum packet_merge { |
286 | MLX5E_PACKET_MERGE_NONE, | |
287 | MLX5E_PACKET_MERGE_LRO, | |
288 | MLX5E_PACKET_MERGE_SHAMPO, | |
289 | }; | |
290 | ||
291 | struct mlx5e_packet_merge_param { | |
292 | enum packet_merge type; | |
293 | u32 timeout; | |
e5ca8fb0 BBI |
294 | struct { |
295 | u8 match_criteria_type; | |
296 | u8 alignment_granularity; | |
297 | } shampo; | |
eaee12f0 KM |
298 | }; |
299 | ||
f62b8bb8 AV |
300 | struct mlx5e_params { |
301 | u8 log_sq_size; | |
461017cb | 302 | u8 rq_wq_type; |
73281b78 | 303 | u8 log_rq_mtu_frames; |
f62b8bb8 | 304 | u16 num_channels; |
86d747a3 | 305 | struct { |
e2aeac44 | 306 | u16 mode; |
86d747a3 | 307 | u8 num_tc; |
7dbc849b | 308 | struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; |
80743c4f | 309 | struct { |
0bb7228f MT |
310 | u64 max_rate[TC_MAX_QUEUE]; |
311 | u32 hw_id[TC_MAX_QUEUE]; | |
80743c4f | 312 | } channel; |
86d747a3 | 313 | } mqprio; |
9bcc8606 | 314 | bool rx_cqe_compress_def; |
8960b389 TG |
315 | struct dim_cq_moder rx_cq_moderation; |
316 | struct dim_cq_moder tx_cq_moderation; | |
eaee12f0 | 317 | struct mlx5e_packet_merge_param packet_merge; |
cff92d7c | 318 | u8 tx_min_inline_mode; |
36350114 | 319 | bool vlan_strip_disable; |
102722fc | 320 | bool scatter_fcs_en; |
9a317425 | 321 | bool rx_dim_enabled; |
cbce4f44 | 322 | bool tx_dim_enabled; |
59ece1c9 | 323 | u32 pflags; |
6a9764ef | 324 | struct bpf_prog *xdp_prog; |
db05815b | 325 | struct mlx5e_xsk *xsk; |
472a1e44 TT |
326 | unsigned int sw_mtu; |
327 | int hard_mtu; | |
960fbfe2 | 328 | bool ptp_rx; |
1db1f21c | 329 | __be32 terminate_lkey_be; |
f62b8bb8 AV |
330 | }; |
331 | ||
86d747a3 TT |
332 | static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) |
333 | { | |
e2aeac44 TT |
334 | return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? |
335 | params->mqprio.num_tc : 1; | |
86d747a3 TT |
336 | } |
337 | ||
1fe7bc10 AF |
338 | /* Keep this enum consistent with the corresponding strings array |
339 | * declared in en/reporter_rx.c | |
340 | */ | |
f62b8bb8 | 341 | enum { |
1fe7bc10 | 342 | MLX5E_RQ_STATE_ENABLED = 0, |
8276ea13 | 343 | MLX5E_RQ_STATE_RECOVERING, |
2b5bd5b1 | 344 | MLX5E_RQ_STATE_DIM, |
b856df28 | 345 | MLX5E_RQ_STATE_NO_CSUM_COMPLETE, |
db849faa | 346 | MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ |
e5ca8fb0 BBI |
347 | MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ |
348 | MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ | |
2c925db0 | 349 | MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */ |
bb76d250 | 350 | MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */ |
1fe7bc10 | 351 | MLX5E_NUM_RQ_STATES, /* Must be kept last */ |
f62b8bb8 AV |
352 | }; |
353 | ||
f62b8bb8 AV |
354 | struct mlx5e_cq { |
355 | /* data path - accessed per cqe */ | |
356 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
357 | |
358 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 359 | u16 event_ctr; |
f62b8bb8 AV |
360 | struct napi_struct *napi; |
361 | struct mlx5_core_cq mcq; | |
4d0b7ef9 | 362 | struct mlx5e_ch_stats *ch_stats; |
f62b8bb8 | 363 | |
79d356ef | 364 | /* control */ |
4d0b7ef9 | 365 | struct net_device *netdev; |
79d356ef | 366 | struct mlx5_core_dev *mdev; |
4d0b7ef9 | 367 | struct mlx5e_priv *priv; |
79d356ef TT |
368 | struct mlx5_wq_ctrl wq_ctrl; |
369 | } ____cacheline_aligned_in_smp; | |
370 | ||
371 | struct mlx5e_cq_decomp { | |
7219ab34 TT |
372 | /* cqe decompression */ |
373 | struct mlx5_cqe64 title; | |
374 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
375 | u8 mini_arr_idx; | |
79d356ef TT |
376 | u16 left; |
377 | u16 wqe_counter; | |
2c925db0 | 378 | bool last_cqe_title; |
f62b8bb8 AV |
379 | } ____cacheline_aligned_in_smp; |
380 | ||
eba2db2b SM |
381 | enum mlx5e_dma_map_type { |
382 | MLX5E_DMA_MAP_SINGLE, | |
383 | MLX5E_DMA_MAP_PAGE | |
384 | }; | |
385 | ||
386 | struct mlx5e_sq_dma { | |
387 | dma_addr_t addr; | |
388 | u32 size; | |
389 | enum mlx5e_dma_map_type type; | |
390 | }; | |
391 | ||
fc9d982a AF |
392 | /* Keep this enum consistent with with the corresponding strings array |
393 | * declared in en/reporter_tx.c | |
394 | */ | |
eba2db2b | 395 | enum { |
fc9d982a | 396 | MLX5E_SQ_STATE_ENABLED = 0, |
5af75c74 | 397 | MLX5E_SQ_STATE_MPWQE, |
db75373c | 398 | MLX5E_SQ_STATE_RECOVERING, |
2ac9cfe7 | 399 | MLX5E_SQ_STATE_IPSEC, |
2b5bd5b1 | 400 | MLX5E_SQ_STATE_DIM, |
b431302e | 401 | MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, |
e7e0004a | 402 | MLX5E_SQ_STATE_PENDING_XSK_TX, |
e9ce991b | 403 | MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, |
9ded70fa | 404 | MLX5E_SQ_STATE_XDP_MULTIBUF, |
fc9d982a | 405 | MLX5E_NUM_SQ_STATES, /* Must be kept last */ |
eba2db2b SM |
406 | }; |
407 | ||
b39fe61e MM |
408 | struct mlx5e_tx_mpwqe { |
409 | /* Current MPWQE session */ | |
410 | struct mlx5e_tx_wqe *wqe; | |
5af75c74 | 411 | u32 bytes_count; |
b39fe61e MM |
412 | u8 ds_count; |
413 | u8 pkt_count; | |
414 | u8 inline_on; | |
415 | }; | |
416 | ||
0b676aae EBE |
417 | struct mlx5e_skb_fifo { |
418 | struct sk_buff **fifo; | |
419 | u16 *pc; | |
420 | u16 *cc; | |
421 | u16 mask; | |
422 | }; | |
423 | ||
145e5637 EBE |
424 | struct mlx5e_ptpsq; |
425 | ||
31391048 | 426 | struct mlx5e_txqsq { |
eba2db2b SM |
427 | /* data path */ |
428 | ||
429 | /* dirtied @completion */ | |
430 | u16 cc; | |
338c46c6 | 431 | u16 skb_fifo_cc; |
eba2db2b | 432 | u32 dma_fifo_cc; |
8960b389 | 433 | struct dim dim; /* Adaptive Moderation */ |
eba2db2b SM |
434 | |
435 | /* dirtied @xmit */ | |
436 | u16 pc ____cacheline_aligned_in_smp; | |
338c46c6 | 437 | u16 skb_fifo_pc; |
eba2db2b | 438 | u32 dma_fifo_pc; |
5af75c74 | 439 | struct mlx5e_tx_mpwqe mpwqe; |
eba2db2b SM |
440 | |
441 | struct mlx5e_cq cq; | |
442 | ||
eba2db2b SM |
443 | /* read only */ |
444 | struct mlx5_wq_cyc wq; | |
445 | u32 dma_fifo_mask; | |
05909bab | 446 | struct mlx5e_sq_stats *stats; |
9a3956da TT |
447 | struct { |
448 | struct mlx5e_sq_dma *dma_fifo; | |
0b676aae | 449 | struct mlx5e_skb_fifo skb_fifo; |
9a3956da TT |
450 | struct mlx5e_tx_wqe_info *wqe_info; |
451 | } db; | |
eba2db2b SM |
452 | void __iomem *uar_map; |
453 | struct netdev_queue *txq; | |
454 | u32 sqn; | |
01614d4f | 455 | u16 stop_room; |
677e78c8 | 456 | u8 max_sq_mpw_wqebbs; |
eba2db2b | 457 | u8 min_inline_mode; |
eba2db2b | 458 | struct device *pdev; |
eba2db2b SM |
459 | __be32 mkey_be; |
460 | unsigned long state; | |
84d1bb2b | 461 | unsigned int hw_mtu; |
7c39afb3 | 462 | struct mlx5_clock *clock; |
4ad40d8e EBE |
463 | struct net_device *netdev; |
464 | struct mlx5_core_dev *mdev; | |
79efecb4 | 465 | struct mlx5e_channel *channel; |
4ad40d8e | 466 | struct mlx5e_priv *priv; |
eba2db2b SM |
467 | |
468 | /* control path */ | |
469 | struct mlx5_wq_ctrl wq_ctrl; | |
57c70d87 | 470 | int ch_ix; |
acc6c595 | 471 | int txq_ix; |
eba2db2b | 472 | u32 rate_limit; |
de8650a8 | 473 | struct work_struct recover_work; |
145e5637 | 474 | struct mlx5e_ptpsq *ptpsq; |
432119de | 475 | cqe_ts_to_ns ptp_cyc2time; |
31391048 SM |
476 | } ____cacheline_aligned_in_smp; |
477 | ||
fea28dd6 | 478 | struct mlx5e_xdp_info_fifo { |
3f734b8c | 479 | union mlx5e_xdp_info *xi; |
fea28dd6 TT |
480 | u32 *cc; |
481 | u32 *pc; | |
482 | u32 mask; | |
483 | }; | |
484 | ||
5e0d2eef | 485 | struct mlx5e_xdpsq; |
e32654f1 | 486 | struct mlx5e_xmit_data; |
db05815b | 487 | typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); |
d963fa15 | 488 | typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, |
b39fe61e | 489 | struct mlx5e_xmit_data *, |
db05815b | 490 | int); |
d963fa15 | 491 | |
31391048 SM |
492 | struct mlx5e_xdpsq { |
493 | /* data path */ | |
494 | ||
dac0d15f | 495 | /* dirtied @completion */ |
fea28dd6 | 496 | u32 xdpi_fifo_cc; |
31391048 | 497 | u16 cc; |
31391048 | 498 | |
dac0d15f | 499 | /* dirtied @xmit */ |
fea28dd6 TT |
500 | u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; |
501 | u16 pc; | |
b8180392 | 502 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
b39fe61e | 503 | struct mlx5e_tx_mpwqe mpwqe; |
31391048 | 504 | |
dac0d15f | 505 | struct mlx5e_cq cq; |
31391048 SM |
506 | |
507 | /* read only */ | |
1742b3d5 | 508 | struct xsk_buff_pool *xsk_pool; |
31391048 | 509 | struct mlx5_wq_cyc wq; |
890388ad | 510 | struct mlx5e_xdpsq_stats *stats; |
db05815b | 511 | mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; |
5e0d2eef | 512 | mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; |
dac0d15f | 513 | struct { |
1feeab80 | 514 | struct mlx5e_xdp_wqe_info *wqe_info; |
fea28dd6 | 515 | struct mlx5e_xdp_info_fifo xdpi_fifo; |
dac0d15f | 516 | } db; |
31391048 SM |
517 | void __iomem *uar_map; |
518 | u32 sqn; | |
519 | struct device *pdev; | |
520 | __be32 mkey_be; | |
c27bd171 | 521 | u16 stop_room; |
677e78c8 | 522 | u8 max_sq_mpw_wqebbs; |
31391048 SM |
523 | u8 min_inline_mode; |
524 | unsigned long state; | |
c94e4f11 | 525 | unsigned int hw_mtu; |
31391048 SM |
526 | |
527 | /* control path */ | |
528 | struct mlx5_wq_ctrl wq_ctrl; | |
529 | struct mlx5e_channel *channel; | |
530 | } ____cacheline_aligned_in_smp; | |
531 | ||
e9ce991b TT |
532 | struct mlx5e_ktls_resync_resp; |
533 | ||
31391048 SM |
534 | struct mlx5e_icosq { |
535 | /* data path */ | |
fd9b4be8 TT |
536 | u16 cc; |
537 | u16 pc; | |
31391048 | 538 | |
fd9b4be8 | 539 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
31391048 SM |
540 | struct mlx5e_cq cq; |
541 | ||
542 | /* write@xmit, read@completion */ | |
543 | struct { | |
7d42c8e9 | 544 | struct mlx5e_icosq_wqe_info *wqe_info; |
31391048 SM |
545 | } db; |
546 | ||
547 | /* read only */ | |
548 | struct mlx5_wq_cyc wq; | |
549 | void __iomem *uar_map; | |
550 | u32 sqn; | |
3ff3874f | 551 | u16 reserved_room; |
31391048 | 552 | unsigned long state; |
e9ce991b | 553 | struct mlx5e_ktls_resync_resp *ktls_resync; |
31391048 SM |
554 | |
555 | /* control path */ | |
556 | struct mlx5_wq_ctrl wq_ctrl; | |
557 | struct mlx5e_channel *channel; | |
be5323c8 AL |
558 | |
559 | struct work_struct recover_work; | |
eba2db2b SM |
560 | } ____cacheline_aligned_in_smp; |
561 | ||
6f574284 DT |
562 | struct mlx5e_frag_page { |
563 | struct page *page; | |
564 | u16 frags; | |
565 | }; | |
566 | ||
625dff29 DT |
567 | enum mlx5e_wqe_frag_flag { |
568 | MLX5E_WQE_FRAG_LAST_IN_PAGE, | |
3f93f829 | 569 | MLX5E_WQE_FRAG_SKIP_RELEASE, |
625dff29 DT |
570 | }; |
571 | ||
accd5883 | 572 | struct mlx5e_wqe_frag_info { |
8fb1814f | 573 | union { |
6f574284 | 574 | struct mlx5e_frag_page *frag_page; |
8fb1814f DT |
575 | struct xdp_buff **xskp; |
576 | }; | |
accd5883 | 577 | u32 offset; |
625dff29 | 578 | u8 flags; |
accd5883 TT |
579 | }; |
580 | ||
8fb1814f | 581 | union mlx5e_alloc_units { |
6f574284 | 582 | DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages); |
8fb1814f DT |
583 | DECLARE_FLEX_ARRAY(struct page *, pages); |
584 | DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs); | |
585 | }; | |
586 | ||
eba2db2b | 587 | struct mlx5e_mpw_info { |
eba2db2b | 588 | u16 consumed_strides; |
38a36efc | 589 | DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE); |
f52ac702 | 590 | struct mlx5e_frag_page linear_page; |
d39092ca | 591 | union mlx5e_alloc_units alloc_units; |
eba2db2b SM |
592 | }; |
593 | ||
069d1146 TT |
594 | #define MLX5E_MAX_RX_FRAGS 4 |
595 | ||
eba2db2b SM |
596 | struct mlx5e_rq; |
597 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
619a8f2a TT |
598 | typedef struct sk_buff * |
599 | (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
bc8d405b THJ |
600 | struct mlx5_cqe64 *cqe, u16 cqe_bcnt, |
601 | u32 head_offset, u32 page_idx); | |
069d1146 | 602 | typedef struct sk_buff * |
84a137f0 | 603 | (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, |
bc8d405b | 604 | struct mlx5_cqe64 *cqe, u32 cqe_bcnt); |
7cc6d77b | 605 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b | 606 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
e5ca8fb0 | 607 | typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); |
eba2db2b | 608 | |
5adf4c47 | 609 | int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); |
5543e989 | 610 | void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); |
5adf4c47 | 611 | |
121e8927 | 612 | enum mlx5e_rq_flag { |
f03590f7 | 613 | MLX5E_RQ_FLAG_XDP_XMIT, |
15143bf5 | 614 | MLX5E_RQ_FLAG_XDP_REDIRECT, |
121e8927 TT |
615 | }; |
616 | ||
069d1146 TT |
617 | struct mlx5e_rq_frag_info { |
618 | int frag_size; | |
619 | int frag_stride; | |
620 | }; | |
621 | ||
622 | struct mlx5e_rq_frags_info { | |
623 | struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; | |
624 | u8 num_frags; | |
625 | u8 log_num_frags; | |
4ba2b498 | 626 | u16 wqe_bulk; |
cd640b05 | 627 | u16 refill_unit; |
a064c609 | 628 | u8 wqe_index_mask; |
069d1146 TT |
629 | }; |
630 | ||
79008676 MM |
631 | struct mlx5e_dma_info { |
632 | dma_addr_t addr; | |
ca6ef9f0 | 633 | union { |
6f574284 | 634 | struct mlx5e_frag_page *frag_page; |
ca6ef9f0 DT |
635 | struct page *page; |
636 | }; | |
79008676 MM |
637 | }; |
638 | ||
e5ca8fb0 | 639 | struct mlx5e_shampo_hd { |
573bce9e | 640 | u32 mkey; |
e5ca8fb0 | 641 | struct mlx5e_dma_info *info; |
6f574284 | 642 | struct mlx5e_frag_page *pages; |
ca6ef9f0 | 643 | u16 curr_page_index; |
e5ca8fb0 BBI |
644 | u16 hd_per_wq; |
645 | u16 hd_per_wqe; | |
646 | unsigned long *bitmap; | |
647 | u16 pi; | |
648 | u16 ci; | |
649 | __be32 key; | |
650 | u64 last_addr; | |
651 | }; | |
652 | ||
92552d3a KM |
653 | struct mlx5e_hw_gro_data { |
654 | struct sk_buff *skb; | |
655 | struct flow_keys fk; | |
656 | int second_ip_id; | |
657 | }; | |
658 | ||
168723c1 MM |
659 | enum mlx5e_mpwrq_umr_mode { |
660 | MLX5E_MPWRQ_UMR_MODE_ALIGNED, | |
661 | MLX5E_MPWRQ_UMR_MODE_UNALIGNED, | |
13921345 | 662 | MLX5E_MPWRQ_UMR_MODE_OVERSIZED, |
c2c9e31d | 663 | MLX5E_MPWRQ_UMR_MODE_TRIPLE, |
168723c1 MM |
664 | }; |
665 | ||
f62b8bb8 AV |
666 | struct mlx5e_rq { |
667 | /* data path */ | |
21c59685 | 668 | union { |
accd5883 | 669 | struct { |
069d1146 TT |
670 | struct mlx5_wq_cyc wq; |
671 | struct mlx5e_wqe_frag_info *frags; | |
8fb1814f | 672 | union mlx5e_alloc_units *alloc_units; |
069d1146 TT |
673 | struct mlx5e_rq_frags_info info; |
674 | mlx5e_fp_skb_from_cqe skb_from_cqe; | |
accd5883 | 675 | } wqe; |
21c59685 | 676 | struct { |
422d4c40 | 677 | struct mlx5_wq_ll wq; |
b8a98a4c | 678 | struct mlx5e_umr_wqe umr_wqe; |
21c59685 | 679 | struct mlx5e_mpw_info *info; |
619a8f2a | 680 | mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; |
ecc7ad2e | 681 | __be32 umr_mkey_be; |
b45d8b50 | 682 | u16 num_strides; |
fd9b4be8 | 683 | u16 actual_wq_head; |
89e89f7a | 684 | u8 log_stride_sz; |
fd9b4be8 TT |
685 | u8 umr_in_progress; |
686 | u8 umr_last_bulk; | |
ed084fb6 | 687 | u8 umr_completed; |
4b5fba4a | 688 | u8 min_wqe_bulk; |
997ce6af MM |
689 | u8 page_shift; |
690 | u8 pages_per_wqe; | |
691 | u8 umr_wqebbs; | |
692 | u8 mtts_per_wqe; | |
168723c1 | 693 | u8 umr_mode; |
e5ca8fb0 | 694 | struct mlx5e_shampo_hd *shampo; |
21c59685 SM |
695 | } mpwqe; |
696 | }; | |
1bfecfca | 697 | struct { |
b45d8b50 | 698 | u16 headroom; |
d628ee4f | 699 | u32 frame0_sz; |
b5503b99 | 700 | u8 map_dir; /* dma map direction */ |
1bfecfca | 701 | } buff; |
f62b8bb8 AV |
702 | |
703 | struct device *pdev; | |
704 | struct net_device *netdev; | |
05909bab | 705 | struct mlx5e_rq_stats *stats; |
f62b8bb8 | 706 | struct mlx5e_cq cq; |
79d356ef | 707 | struct mlx5e_cq_decomp cqd; |
7c39afb3 FD |
708 | struct hwtstamp_config *tstamp; |
709 | struct mlx5_clock *clock; | |
521f31af AL |
710 | struct mlx5e_icosq *icosq; |
711 | struct mlx5e_priv *priv; | |
4415a031 | 712 | |
92552d3a KM |
713 | struct mlx5e_hw_gro_data *hw_gro_data; |
714 | ||
2f48af12 | 715 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 716 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 717 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
718 | |
719 | unsigned long state; | |
720 | int ix; | |
0073c8f7 | 721 | unsigned int hw_mtu; |
f62b8bb8 | 722 | |
8960b389 | 723 | struct dim dim; /* Dynamic Interrupt Moderation */ |
31871f87 SM |
724 | |
725 | /* XDP */ | |
fe45386a | 726 | struct bpf_prog __rcu *xdp_prog; |
b9673cf5 | 727 | struct mlx5e_xdpsq *xdpsq; |
121e8927 | 728 | DECLARE_BITMAP(flags, 8); |
60bbf7ee | 729 | struct page_pool *page_pool; |
cb3c7fd4 | 730 | |
db05815b | 731 | /* AF_XDP zero-copy */ |
1742b3d5 | 732 | struct xsk_buff_pool *xsk_pool; |
db05815b | 733 | |
8276ea13 AL |
734 | struct work_struct recover_work; |
735 | ||
f62b8bb8 AV |
736 | /* control */ |
737 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 738 | __be32 mkey_be; |
461017cb | 739 | u8 wq_type; |
f62b8bb8 | 740 | u32 rqn; |
a43b25da | 741 | struct mlx5_core_dev *mdev; |
2e642afb | 742 | struct mlx5e_channel *channel; |
c3c94023 | 743 | struct mlx5e_dma_info wqe_overflow; |
0ddf5432 JDB |
744 | |
745 | /* XDP read-mostly */ | |
746 | struct xdp_rxq_info xdp_rxq; | |
432119de | 747 | cqe_ts_to_ns ptp_cyc2time; |
f62b8bb8 AV |
748 | } ____cacheline_aligned_in_smp; |
749 | ||
db05815b MM |
750 | enum mlx5e_channel_state { |
751 | MLX5E_CHANNEL_STATE_XSK, | |
752 | MLX5E_CHANNEL_NUM_STATES | |
753 | }; | |
754 | ||
f62b8bb8 AV |
755 | struct mlx5e_channel { |
756 | /* data path */ | |
757 | struct mlx5e_rq rq; | |
b9673cf5 | 758 | struct mlx5e_xdpsq rq_xdpsq; |
31391048 SM |
759 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
760 | struct mlx5e_icosq icosq; /* internal control operations */ | |
214baf22 | 761 | struct mlx5e_txqsq __rcu * __rcu *qos_sqs; |
b5503b99 | 762 | bool xdp; |
f62b8bb8 AV |
763 | struct napi_struct napi; |
764 | struct device *pdev; | |
765 | struct net_device *netdev; | |
766 | __be32 mkey_be; | |
214baf22 | 767 | u16 qos_sqs_size; |
f62b8bb8 | 768 | u8 num_tc; |
45f171b1 | 769 | u8 lag_port; |
f62b8bb8 | 770 | |
58b99ee3 TT |
771 | /* XDP_REDIRECT */ |
772 | struct mlx5e_xdpsq xdpsq; | |
773 | ||
db05815b MM |
774 | /* AF_XDP zero-copy */ |
775 | struct mlx5e_rq xskrq; | |
776 | struct mlx5e_xdpsq xsksq; | |
8d94b590 TT |
777 | |
778 | /* Async ICOSQ */ | |
779 | struct mlx5e_icosq async_icosq; | |
780 | /* async_icosq can be accessed from any CPU - the spinlock protects it. */ | |
781 | spinlock_t async_icosq_lock; | |
db05815b | 782 | |
a8c2eb15 | 783 | /* data path - accessed per napi poll */ |
6e745db4 | 784 | const struct cpumask *aff_mask; |
05909bab | 785 | struct mlx5e_ch_stats *stats; |
f62b8bb8 AV |
786 | |
787 | /* control */ | |
788 | struct mlx5e_priv *priv; | |
a43b25da | 789 | struct mlx5_core_dev *mdev; |
7c39afb3 | 790 | struct hwtstamp_config *tstamp; |
db05815b | 791 | DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); |
f62b8bb8 | 792 | int ix; |
231243c8 | 793 | int cpu; |
17958d7c MM |
794 | /* Sync between icosq recovery and XSK enable/disable. */ |
795 | struct mutex icosq_recovery_lock; | |
f62b8bb8 AV |
796 | }; |
797 | ||
b0d35de4 | 798 | struct mlx5e_ptp; |
145e5637 | 799 | |
ff9c852f SM |
800 | struct mlx5e_channels { |
801 | struct mlx5e_channel **c; | |
b0d35de4 | 802 | struct mlx5e_ptp *ptp; |
ff9c852f | 803 | unsigned int num; |
6a9764ef | 804 | struct mlx5e_params params; |
ff9c852f SM |
805 | }; |
806 | ||
05909bab EBE |
807 | struct mlx5e_channel_stats { |
808 | struct mlx5e_ch_stats ch; | |
809 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
810 | struct mlx5e_rq_stats rq; | |
db05815b | 811 | struct mlx5e_rq_stats xskrq; |
890388ad | 812 | struct mlx5e_xdpsq_stats rq_xdpsq; |
58b99ee3 | 813 | struct mlx5e_xdpsq_stats xdpsq; |
db05815b | 814 | struct mlx5e_xdpsq_stats xsksq; |
05909bab EBE |
815 | } ____cacheline_aligned_in_smp; |
816 | ||
b0d35de4 | 817 | struct mlx5e_ptp_stats { |
145e5637 EBE |
818 | struct mlx5e_ch_stats ch; |
819 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
1880bc4e | 820 | struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC]; |
a099da8f | 821 | struct mlx5e_rq_stats rq; |
145e5637 EBE |
822 | } ____cacheline_aligned_in_smp; |
823 | ||
acff797c | 824 | enum { |
acff797c MG |
825 | MLX5E_STATE_OPENED, |
826 | MLX5E_STATE_DESTROYING, | |
407e17b1 | 827 | MLX5E_STATE_XDP_TX_ENABLED, |
9cf88808 | 828 | MLX5E_STATE_XDP_ACTIVE, |
eab0da38 | 829 | MLX5E_STATE_CHANNELS_ACTIVE, |
acff797c MG |
830 | }; |
831 | ||
de8650a8 EBE |
832 | struct mlx5e_modify_sq_param { |
833 | int curr_state; | |
834 | int next_state; | |
835 | int rl_update; | |
836 | int rl_index; | |
214baf22 MM |
837 | bool qos_update; |
838 | u16 qos_queue_group_id; | |
de8650a8 EBE |
839 | }; |
840 | ||
cef35af3 EBE |
841 | #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) |
842 | struct mlx5e_hv_vhca_stats_agent { | |
843 | struct mlx5_hv_vhca_agent *agent; | |
844 | struct delayed_work work; | |
845 | u16 delay; | |
846 | void *buf; | |
847 | }; | |
848 | #endif | |
849 | ||
db05815b | 850 | struct mlx5e_xsk { |
1742b3d5 MK |
851 | /* XSK buffer pools are stored separately from channels, |
852 | * because we don't want to lose them when channels are | |
853 | * recreated. The kernel also stores buffer pool, but it doesn't | |
854 | * distinguish between zero-copy and non-zero-copy UMEMs, so | |
855 | * rely on our mechanism. | |
db05815b | 856 | */ |
1742b3d5 | 857 | struct xsk_buff_pool **pools; |
db05815b MM |
858 | u16 refcnt; |
859 | bool ever_used; | |
860 | }; | |
861 | ||
3909a12e MM |
862 | /* Temporary storage for variables that are allocated when struct mlx5e_priv is |
863 | * initialized, and used where we can't allocate them because that functions | |
864 | * must not fail. Use with care and make sure the same variable is not used | |
865 | * simultaneously by multiple users. | |
866 | */ | |
867 | struct mlx5e_scratchpad { | |
868 | cpumask_var_t cpumask; | |
869 | }; | |
870 | ||
5543e989 | 871 | struct mlx5e_trap; |
aaffda6b | 872 | struct mlx5e_htb; |
5543e989 | 873 | |
f62b8bb8 AV |
874 | struct mlx5e_priv { |
875 | /* priv data path fields - start */ | |
8bf30be7 | 876 | struct mlx5e_selq selq; |
0246a57a | 877 | struct mlx5e_txqsq **txq2sq; |
2a5e7a13 HN |
878 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
879 | struct mlx5e_dcbx_dp dcbx_dp; | |
880 | #endif | |
f62b8bb8 AV |
881 | /* priv data path fields - end */ |
882 | ||
883 | unsigned long state; | |
884 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 885 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 886 | |
ff9c852f | 887 | struct mlx5e_channels channels; |
45f171b1 | 888 | u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC]; |
3f22d6c7 | 889 | struct mlx5e_rx_res *rx_res; |
0246a57a | 890 | u32 *tx_rates; |
f62b8bb8 | 891 | |
af8bbf73 | 892 | struct mlx5e_flow_steering *fs; |
f62b8bb8 | 893 | |
7bb29755 | 894 | struct workqueue_struct *wq; |
f62b8bb8 AV |
895 | struct work_struct update_carrier_work; |
896 | struct work_struct set_rx_mode_work; | |
3947ca18 | 897 | struct work_struct tx_timeout_work; |
cdeef2b1 | 898 | struct work_struct update_stats_work; |
5c7e8bbb ED |
899 | struct work_struct monitor_counters_work; |
900 | struct mlx5_nb monitor_counters_nb; | |
f62b8bb8 AV |
901 | |
902 | struct mlx5_core_dev *mdev; | |
903 | struct net_device *netdev; | |
5543e989 | 904 | struct mlx5e_trap *en_trap; |
f62b8bb8 | 905 | struct mlx5e_stats stats; |
be98737a | 906 | struct mlx5e_channel_stats **channel_stats; |
5543e989 | 907 | struct mlx5e_channel_stats trap_stats; |
b0d35de4 | 908 | struct mlx5e_ptp_stats ptp_stats; |
db83f24d MT |
909 | struct mlx5e_sq_stats **htb_qos_sq_stats; |
910 | u16 htb_max_qos_sqs; | |
9d758d4a | 911 | u16 stats_nch; |
694826e3 | 912 | u16 max_nch; |
05909bab | 913 | u8 max_opened_tc; |
b0d35de4 | 914 | bool tx_ptp_opened; |
a28359e9 | 915 | bool rx_ptp_opened; |
7c39afb3 | 916 | struct hwtstamp_config tstamp; |
7cbaf9a3 MS |
917 | u16 q_counter; |
918 | u16 drop_rq_q_counter; | |
7cffaddd | 919 | struct notifier_block events_nb; |
70038b73 | 920 | struct notifier_block blocking_events_nb; |
7cffaddd | 921 | |
18a2b7f9 | 922 | struct udp_tunnel_nic_info nic_info; |
3a6a931d HN |
923 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
924 | struct mlx5e_dcbx dcbx; | |
925 | #endif | |
926 | ||
6bfd390b | 927 | const struct mlx5e_profile *profile; |
127ea380 | 928 | void *ppriv; |
7390762a | 929 | #ifdef CONFIG_MLX5_MACSEC |
8ff0ac5b LN |
930 | struct mlx5e_macsec *macsec; |
931 | #endif | |
547eede0 IT |
932 | #ifdef CONFIG_MLX5_EN_IPSEC |
933 | struct mlx5e_ipsec *ipsec; | |
934 | #endif | |
43585a41 IL |
935 | #ifdef CONFIG_MLX5_EN_TLS |
936 | struct mlx5e_tls *tls; | |
937 | #endif | |
de8650a8 | 938 | struct devlink_health_reporter *tx_reporter; |
9032e719 | 939 | struct devlink_health_reporter *rx_reporter; |
db05815b | 940 | struct mlx5e_xsk xsk; |
cef35af3 EBE |
941 | #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) |
942 | struct mlx5e_hv_vhca_stats_agent stats_agent; | |
943 | #endif | |
3909a12e | 944 | struct mlx5e_scratchpad scratchpad; |
aaffda6b | 945 | struct mlx5e_htb *htb; |
80743c4f | 946 | struct mlx5e_mqprio_rl *mqprio_rl; |
288eca60 | 947 | struct dentry *dfs_root; |
bf11485f | 948 | struct mlx5_devcom_comp_dev *devcom; |
f62b8bb8 AV |
949 | }; |
950 | ||
ee75f1fc JP |
951 | struct mlx5e_dev { |
952 | struct mlx5e_priv *priv; | |
c30f3faa | 953 | struct devlink_port dl_port; |
ee75f1fc JP |
954 | }; |
955 | ||
5adf4c47 TT |
956 | struct mlx5e_rx_handlers { |
957 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
958 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
f97d5c2a | 959 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; |
5adf4c47 TT |
960 | }; |
961 | ||
962 | extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; | |
963 | ||
6c72cb05 TT |
964 | enum mlx5e_profile_feature { |
965 | MLX5E_PROFILE_FEATURE_PTP_RX, | |
1958c2bd TT |
966 | MLX5E_PROFILE_FEATURE_PTP_TX, |
967 | MLX5E_PROFILE_FEATURE_QOS_HTB, | |
454533aa LK |
968 | MLX5E_PROFILE_FEATURE_FS_VLAN, |
969 | MLX5E_PROFILE_FEATURE_FS_TC, | |
6c72cb05 TT |
970 | }; |
971 | ||
a43b25da | 972 | struct mlx5e_profile { |
182570b2 | 973 | int (*init)(struct mlx5_core_dev *mdev, |
3ef14e46 | 974 | struct net_device *netdev); |
a43b25da SM |
975 | void (*cleanup)(struct mlx5e_priv *priv); |
976 | int (*init_rx)(struct mlx5e_priv *priv); | |
977 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
978 | int (*init_tx)(struct mlx5e_priv *priv); | |
979 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
980 | void (*enable)(struct mlx5e_priv *priv); | |
981 | void (*disable)(struct mlx5e_priv *priv); | |
a90f88fe | 982 | int (*update_rx)(struct mlx5e_priv *priv); |
a43b25da | 983 | void (*update_stats)(struct mlx5e_priv *priv); |
7ca42c80 | 984 | void (*update_carrier)(struct mlx5e_priv *priv); |
473baf2e | 985 | int (*max_nch_limit)(struct mlx5_core_dev *mdev); |
3460c184 | 986 | unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); |
f0ff8e8c | 987 | mlx5e_stats_grp_t *stats_grps; |
5adf4c47 | 988 | const struct mlx5e_rx_handlers *rx_handlers; |
a43b25da | 989 | int max_tc; |
6c72cb05 | 990 | u32 features; |
a43b25da SM |
991 | }; |
992 | ||
6c72cb05 | 993 | #define mlx5e_profile_feature_cap(profile, feature) \ |
bc2a7b5c | 994 | ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature)) |
6c72cb05 | 995 | |
665bc539 GP |
996 | void mlx5e_build_ptys2ethtool_map(void); |
997 | ||
6470d2e7 | 998 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, |
168723c1 | 999 | enum mlx5e_mpwrq_umr_mode umr_mode); |
2ccb0a79 | 1000 | |
e5ca8fb0 | 1001 | void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close); |
d9ee0491 | 1002 | void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); |
b832d4fd | 1003 | void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); |
f62b8bb8 | 1004 | |
d605d668 | 1005 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
7990b1b5 | 1006 | int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); |
d605d668 KH |
1007 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, |
1008 | u64 *buf); | |
f62b8bb8 AV |
1009 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
1010 | ||
1170fbd8 FD |
1011 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
1012 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
c91c1da7 | 1013 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); |
ef9814de | 1014 | |
f62b8bb8 AV |
1015 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
1016 | u16 vid); | |
1017 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
1018 | u16 vid); | |
237f258c | 1019 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
f62b8bb8 | 1020 | |
db05815b MM |
1021 | struct mlx5e_xsk_param; |
1022 | ||
1023 | struct mlx5e_rq_param; | |
869c5f92 AL |
1024 | int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, |
1025 | struct mlx5e_xsk_param *xsk, int node, | |
1026 | struct mlx5e_rq *rq); | |
082a9edf | 1027 | #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ |
db05815b | 1028 | int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); |
db05815b | 1029 | void mlx5e_close_rq(struct mlx5e_rq *rq); |
5543e989 AL |
1030 | int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param); |
1031 | void mlx5e_destroy_rq(struct mlx5e_rq *rq); | |
db05815b MM |
1032 | |
1033 | struct mlx5e_sq_param; | |
db05815b | 1034 | int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, |
1742b3d5 | 1035 | struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, |
db05815b MM |
1036 | struct mlx5e_xdpsq *sq, bool is_redirect); |
1037 | void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); | |
1038 | ||
4d0b7ef9 AL |
1039 | struct mlx5e_create_cq_param { |
1040 | struct napi_struct *napi; | |
1041 | struct mlx5e_ch_stats *ch_stats; | |
1042 | int node; | |
1043 | int ix; | |
1044 | }; | |
1045 | ||
db05815b | 1046 | struct mlx5e_cq_param; |
4d0b7ef9 AL |
1047 | int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, |
1048 | struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, | |
1049 | struct mlx5e_cq *cq); | |
db05815b MM |
1050 | void mlx5e_close_cq(struct mlx5e_cq *cq); |
1051 | ||
f62b8bb8 AV |
1052 | int mlx5e_open_locked(struct net_device *netdev); |
1053 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d | 1054 | |
2e642afb MM |
1055 | void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c); |
1056 | void mlx5e_trigger_napi_sched(struct napi_struct *napi); | |
1057 | ||
55c2503d SM |
1058 | int mlx5e_open_channels(struct mlx5e_priv *priv, |
1059 | struct mlx5e_channels *chs); | |
1060 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 | 1061 | |
dca147b3 | 1062 | /* Function pointer to be used to modify HW or kernel settings while |
2e20a151 SM |
1063 | * switching channels |
1064 | */ | |
b9ab5d0e MM |
1065 | typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); |
1066 | #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ | |
1067 | int fn##_ctx(struct mlx5e_priv *priv, void *context) \ | |
1068 | { \ | |
1069 | return fn(priv); \ | |
1070 | } | |
484c1ada | 1071 | int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); |
94872d4e MM |
1072 | int mlx5e_safe_switch_params(struct mlx5e_priv *priv, |
1073 | struct mlx5e_params *new_params, | |
1074 | mlx5e_fp_preactivate preactivate, | |
1075 | void *context, bool reset); | |
214baf22 | 1076 | int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); |
b9ab5d0e | 1077 | int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); |
603f4a45 SM |
1078 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
1079 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
885b8cfb | 1080 | int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); |
55c2503d | 1081 | |
d9ba64de | 1082 | int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state); |
be5323c8 AL |
1083 | void mlx5e_activate_rq(struct mlx5e_rq *rq); |
1084 | void mlx5e_deactivate_rq(struct mlx5e_rq *rq); | |
be5323c8 AL |
1085 | void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); |
1086 | void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); | |
9908aa29 | 1087 | |
de8650a8 EBE |
1088 | int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
1089 | struct mlx5e_modify_sq_param *p); | |
214baf22 MM |
1090 | int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, |
1091 | struct mlx5e_params *params, struct mlx5e_sq_param *param, | |
e0ee6891 TT |
1092 | struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, |
1093 | struct mlx5e_sq_stats *sq_stats); | |
de8650a8 | 1094 | void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); |
145e5637 EBE |
1095 | void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); |
1096 | void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); | |
de8650a8 | 1097 | void mlx5e_tx_disable_queue(struct netdev_queue *txq); |
145e5637 EBE |
1098 | int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); |
1099 | void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); | |
1100 | struct mlx5e_create_sq_param; | |
1101 | int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, | |
1102 | struct mlx5e_sq_param *param, | |
1103 | struct mlx5e_create_sq_param *csp, | |
214baf22 | 1104 | u16 qos_queue_group_id, |
145e5637 EBE |
1105 | u32 *sqn); |
1106 | void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); | |
214baf22 | 1107 | void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); |
de8650a8 | 1108 | |
e3cfc7e6 MS |
1109 | static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) |
1110 | { | |
1111 | return MLX5_CAP_ETH(mdev, swp) && | |
1112 | MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); | |
1113 | } | |
1114 | ||
f62b8bb8 | 1115 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac | 1116 | |
0e1e03c0 | 1117 | int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); |
b50d292b HHZ |
1118 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1119 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
80639b19 ES |
1120 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, |
1121 | bool enable_mc_lb); | |
17347d54 | 1122 | void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); |
1afff42c | 1123 | |
bc81b9d3 | 1124 | /* common netdev helpers */ |
1462e48d RD |
1125 | void mlx5e_create_q_counters(struct mlx5e_priv *priv); |
1126 | void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); | |
1127 | int mlx5e_open_drop_rq(struct mlx5e_priv *priv, | |
1128 | struct mlx5e_rq *drop_rq); | |
1129 | void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); | |
1130 | ||
2b257a6e | 1131 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); |
5426a0b2 SM |
1132 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); |
1133 | ||
cb67b832 | 1134 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
3c145626 | 1135 | void mlx5e_destroy_tises(struct mlx5e_priv *priv); |
a90f88fe | 1136 | int mlx5e_update_nic_rx(struct mlx5e_priv *priv); |
b36cdb42 | 1137 | void mlx5e_update_carrier(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1138 | int mlx5e_close(struct net_device *netdev); |
1139 | int mlx5e_open(struct net_device *netdev); | |
cb67b832 | 1140 | |
cdeef2b1 | 1141 | void mlx5e_queue_update_stats(struct mlx5e_priv *priv); |
3f6d08d1 | 1142 | |
d9ee0491 | 1143 | int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); |
b9ab5d0e | 1144 | int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); |
250a42b6 | 1145 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, |
b9ab5d0e | 1146 | mlx5e_fp_preactivate preactivate); |
18a2b7f9 | 1147 | void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); |
250a42b6 | 1148 | |
076b0936 ES |
1149 | /* ethtool helpers */ |
1150 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1151 | struct ethtool_drvinfo *drvinfo); | |
1152 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1153 | uint32_t stringset, uint8_t *data); | |
1154 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1155 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1156 | struct ethtool_stats *stats, u64 *data); | |
1157 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
07071e47 GP |
1158 | struct ethtool_ringparam *param, |
1159 | struct kernel_ethtool_ringparam *kernel_param); | |
076b0936 ES |
1160 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, |
1161 | struct ethtool_ringparam *param); | |
1162 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1163 | struct ethtool_channels *ch); | |
1164 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1165 | struct ethtool_channels *ch); | |
1166 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
bc541621 SM |
1167 | struct ethtool_coalesce *coal, |
1168 | struct kernel_ethtool_coalesce *kernel_coal); | |
076b0936 | 1169 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, |
bc541621 SM |
1170 | struct ethtool_coalesce *coal, |
1171 | struct kernel_ethtool_coalesce *kernel_coal, | |
1172 | struct netlink_ext_ack *extack); | |
371289b6 OG |
1173 | int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, |
1174 | struct ethtool_link_ksettings *link_ksettings); | |
1175 | int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, | |
1176 | const struct ethtool_link_ksettings *link_ksettings); | |
01013ad3 VB |
1177 | int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc); |
1178 | int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key, | |
1179 | const u8 hfunc); | |
a5355de8 OG |
1180 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); |
1181 | u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); | |
3844b07e FD |
1182 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1183 | struct ethtool_ts_info *info); | |
f43d48d1 EBE |
1184 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1185 | struct ethtool_flash *flash); | |
371289b6 OG |
1186 | void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, |
1187 | struct ethtool_pauseparam *pauseparam); | |
1188 | int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, | |
1189 | struct ethtool_pauseparam *pauseparam); | |
076b0936 | 1190 | |
2c3b5bee | 1191 | /* mlx5e generic netdev management API */ |
040ee617 AH |
1192 | static inline bool |
1193 | mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) | |
1194 | { | |
1195 | return !is_kdump_kernel() && | |
1196 | MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); | |
1197 | } | |
1198 | ||
6d0ba493 | 1199 | int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev); |
c9fd1e33 | 1200 | int mlx5e_priv_init(struct mlx5e_priv *priv, |
9d758d4a | 1201 | const struct mlx5e_profile *profile, |
c9fd1e33 RD |
1202 | struct net_device *netdev, |
1203 | struct mlx5_core_dev *mdev); | |
1204 | void mlx5e_priv_cleanup(struct mlx5e_priv *priv); | |
3ef14e46 | 1205 | struct net_device * |
1958c2bd | 1206 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile); |
2c3b5bee SM |
1207 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); |
1208 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1209 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
c4d7eb57 SM |
1210 | int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, |
1211 | const struct mlx5e_profile *new_profile, void *new_ppriv); | |
7a9fb35e | 1212 | void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv); |
6d7ee2ed | 1213 | void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); |
3ef14e46 | 1214 | void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); |
9a317425 | 1215 | void mlx5e_rx_dim_work(struct work_struct *work); |
cbce4f44 | 1216 | void mlx5e_tx_dim_work(struct work_struct *work); |
073caf50 | 1217 | |
4d5ab0ad | 1218 | void mlx5e_set_xdp_feature(struct net_device *netdev); |
073caf50 OG |
1219 | netdev_features_t mlx5e_features_check(struct sk_buff *skb, |
1220 | struct net_device *netdev, | |
1221 | netdev_features_t features); | |
d3cbd425 | 1222 | int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); |
073caf50 OG |
1223 | #ifdef CONFIG_MLX5_ESWITCH |
1224 | int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); | |
1225 | int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); | |
1226 | int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); | |
1227 | int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); | |
1228 | #endif | |
8518d05b | 1229 | int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); |
1afff42c | 1230 | #endif /* __MLX5_EN_H__ */ |