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f62b8bb8 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include "en.h" | |
2c81bfd5 | 34 | #include "en/port.h" |
6dbc80ca | 35 | #include "lib/clock.h" |
f62b8bb8 | 36 | |
076b0936 ES |
37 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, |
38 | struct ethtool_drvinfo *drvinfo) | |
f62b8bb8 | 39 | { |
f62b8bb8 AV |
40 | struct mlx5_core_dev *mdev = priv->mdev; |
41 | ||
42 | strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver)); | |
7913d205 | 43 | strlcpy(drvinfo->version, DRIVER_VERSION, |
f62b8bb8 AV |
44 | sizeof(drvinfo->version)); |
45 | snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), | |
84e11edb IK |
46 | "%d.%d.%04d (%.16s)", |
47 | fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev), | |
48 | mdev->board_id); | |
f62b8bb8 AV |
49 | strlcpy(drvinfo->bus_info, pci_name(mdev->pdev), |
50 | sizeof(drvinfo->bus_info)); | |
51 | } | |
52 | ||
076b0936 ES |
53 | static void mlx5e_get_drvinfo(struct net_device *dev, |
54 | struct ethtool_drvinfo *drvinfo) | |
55 | { | |
56 | struct mlx5e_priv *priv = netdev_priv(dev); | |
57 | ||
58 | mlx5e_ethtool_get_drvinfo(priv, drvinfo); | |
59 | } | |
60 | ||
665bc539 GP |
61 | struct ptys2ethtool_config { |
62 | __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); | |
63 | __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); | |
f62b8bb8 AV |
64 | }; |
65 | ||
6a897372 AL |
66 | static |
67 | struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER]; | |
68 | static | |
69 | struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER]; | |
665bc539 | 70 | |
6a897372 | 71 | #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \ |
665bc539 GP |
72 | ({ \ |
73 | struct ptys2ethtool_config *cfg; \ | |
74 | const unsigned int modes[] = { __VA_ARGS__ }; \ | |
6a897372 AL |
75 | unsigned int i, bit, idx; \ |
76 | cfg = &ptys2##table##_ethtool_table[reg_]; \ | |
665bc539 GP |
77 | bitmap_zero(cfg->supported, \ |
78 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
79 | bitmap_zero(cfg->advertised, \ | |
80 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
81 | for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ | |
6a897372 AL |
82 | bit = modes[i] % 64; \ |
83 | idx = modes[i] / 64; \ | |
84 | __set_bit(bit, &cfg->supported[idx]); \ | |
85 | __set_bit(bit, &cfg->advertised[idx]); \ | |
665bc539 GP |
86 | } \ |
87 | }) | |
88 | ||
89 | void mlx5e_build_ptys2ethtool_map(void) | |
90 | { | |
6a897372 AL |
91 | memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table)); |
92 | memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table)); | |
93 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy, | |
665bc539 | 94 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); |
6a897372 | 95 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy, |
665bc539 | 96 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); |
6a897372 | 97 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy, |
665bc539 | 98 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); |
6a897372 | 99 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy, |
665bc539 | 100 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); |
6a897372 | 101 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy, |
665bc539 | 102 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); |
6a897372 | 103 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy, |
665bc539 | 104 | ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); |
6a897372 | 105 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy, |
665bc539 | 106 | ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); |
6a897372 | 107 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy, |
665bc539 | 108 | ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); |
6a897372 | 109 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy, |
665bc539 | 110 | ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); |
6a897372 | 111 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy, |
665bc539 | 112 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); |
6a897372 | 113 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy, |
665bc539 | 114 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); |
6a897372 | 115 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy, |
665bc539 | 116 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); |
6a897372 | 117 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy, |
665bc539 | 118 | ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); |
6a897372 | 119 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy, |
665bc539 | 120 | ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); |
6a897372 | 121 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy, |
665bc539 | 122 | ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); |
6a897372 | 123 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy, |
665bc539 | 124 | ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT); |
6a897372 | 125 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy, |
665bc539 | 126 | ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT); |
6a897372 | 127 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy, |
665bc539 | 128 | ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT); |
6a897372 | 129 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy, |
665bc539 | 130 | ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); |
6a897372 | 131 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy, |
665bc539 | 132 | ETHTOOL_LINK_MODE_10000baseT_Full_BIT); |
6a897372 | 133 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy, |
665bc539 | 134 | ETHTOOL_LINK_MODE_25000baseCR_Full_BIT); |
6a897372 | 135 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy, |
665bc539 | 136 | ETHTOOL_LINK_MODE_25000baseKR_Full_BIT); |
6a897372 | 137 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy, |
665bc539 | 138 | ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); |
6a897372 | 139 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy, |
665bc539 | 140 | ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT); |
6a897372 | 141 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy, |
665bc539 | 142 | ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT); |
6a897372 AL |
143 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext, |
144 | ETHTOOL_LINK_MODE_100baseT_Full_BIT); | |
145 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext, | |
146 | ETHTOOL_LINK_MODE_1000baseT_Full_BIT, | |
147 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, | |
148 | ETHTOOL_LINK_MODE_1000baseX_Full_BIT); | |
149 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext, | |
150 | ETHTOOL_LINK_MODE_5000baseT_Full_BIT); | |
151 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext, | |
152 | ETHTOOL_LINK_MODE_10000baseT_Full_BIT, | |
153 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, | |
154 | ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, | |
155 | ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, | |
156 | ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, | |
157 | ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, | |
158 | ETHTOOL_LINK_MODE_10000baseER_Full_BIT); | |
159 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext, | |
160 | ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, | |
161 | ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, | |
162 | ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, | |
163 | ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); | |
164 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext, | |
165 | ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, | |
166 | ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, | |
167 | ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); | |
168 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2, | |
169 | ext, | |
170 | ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, | |
171 | ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, | |
172 | ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); | |
173 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext, | |
174 | ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, | |
175 | ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, | |
176 | ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, | |
177 | ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, | |
178 | ETHTOOL_LINK_MODE_50000baseDR_Full_BIT); | |
179 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext, | |
180 | ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, | |
181 | ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, | |
182 | ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, | |
183 | ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); | |
184 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext, | |
185 | ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, | |
186 | ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, | |
187 | ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, | |
188 | ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, | |
189 | ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT); | |
190 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext, | |
191 | ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, | |
192 | ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, | |
193 | ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, | |
194 | ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT, | |
195 | ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT); | |
196 | } | |
197 | ||
198 | static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev, | |
199 | struct ptys2ethtool_config **arr, | |
200 | u32 *size) | |
201 | { | |
202 | bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); | |
203 | ||
204 | *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; | |
205 | *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : | |
206 | ARRAY_SIZE(ptys2legacy_ethtool_table); | |
665bc539 GP |
207 | } |
208 | ||
8ff57c18 TT |
209 | typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable); |
210 | ||
211 | struct pflag_desc { | |
212 | char name[ETH_GSTRING_LEN]; | |
213 | mlx5e_pflag_handler handler; | |
d2408205 KH |
214 | }; |
215 | ||
8ff57c18 TT |
216 | static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS]; |
217 | ||
076b0936 | 218 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset) |
f62b8bb8 | 219 | { |
c0752f2b KH |
220 | int i, num_stats = 0; |
221 | ||
f62b8bb8 AV |
222 | switch (sset) { |
223 | case ETH_SS_STATS: | |
c0752f2b KH |
224 | for (i = 0; i < mlx5e_num_stats_grps; i++) |
225 | num_stats += mlx5e_stats_grps[i].get_num_stats(priv); | |
1fe85006 | 226 | return num_stats; |
4e59e288 | 227 | case ETH_SS_PRIV_FLAGS: |
8ff57c18 | 228 | return MLX5E_NUM_PFLAGS; |
d605d668 KH |
229 | case ETH_SS_TEST: |
230 | return mlx5e_self_test_num(priv); | |
f62b8bb8 AV |
231 | /* fallthrough */ |
232 | default: | |
233 | return -EOPNOTSUPP; | |
234 | } | |
235 | } | |
236 | ||
076b0936 ES |
237 | static int mlx5e_get_sset_count(struct net_device *dev, int sset) |
238 | { | |
239 | struct mlx5e_priv *priv = netdev_priv(dev); | |
240 | ||
241 | return mlx5e_ethtool_get_sset_count(priv, sset); | |
242 | } | |
243 | ||
c045deef | 244 | static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data) |
9218b44d | 245 | { |
1fe85006 | 246 | int i, idx = 0; |
9218b44d | 247 | |
c0752f2b KH |
248 | for (i = 0; i < mlx5e_num_stats_grps; i++) |
249 | idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx); | |
9218b44d GP |
250 | } |
251 | ||
c045deef | 252 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data) |
f62b8bb8 | 253 | { |
4e59e288 | 254 | int i; |
f62b8bb8 AV |
255 | |
256 | switch (stringset) { | |
257 | case ETH_SS_PRIV_FLAGS: | |
8ff57c18 TT |
258 | for (i = 0; i < MLX5E_NUM_PFLAGS; i++) |
259 | strcpy(data + i * ETH_GSTRING_LEN, | |
260 | mlx5e_priv_flags[i].name); | |
f62b8bb8 AV |
261 | break; |
262 | ||
263 | case ETH_SS_TEST: | |
d605d668 KH |
264 | for (i = 0; i < mlx5e_self_test_num(priv); i++) |
265 | strcpy(data + i * ETH_GSTRING_LEN, | |
266 | mlx5e_self_tests[i]); | |
f62b8bb8 AV |
267 | break; |
268 | ||
269 | case ETH_SS_STATS: | |
9218b44d | 270 | mlx5e_fill_stats_strings(priv, data); |
f62b8bb8 AV |
271 | break; |
272 | } | |
273 | } | |
274 | ||
c045deef | 275 | static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
f62b8bb8 AV |
276 | { |
277 | struct mlx5e_priv *priv = netdev_priv(dev); | |
076b0936 ES |
278 | |
279 | mlx5e_ethtool_get_strings(priv, stringset, data); | |
280 | } | |
281 | ||
282 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
283 | struct ethtool_stats *stats, u64 *data) | |
284 | { | |
1fe85006 | 285 | int i, idx = 0; |
f62b8bb8 | 286 | |
f62b8bb8 | 287 | mutex_lock(&priv->state_lock); |
19386177 | 288 | mlx5e_update_stats(priv); |
f62b8bb8 AV |
289 | mutex_unlock(&priv->state_lock); |
290 | ||
c0752f2b KH |
291 | for (i = 0; i < mlx5e_num_stats_grps; i++) |
292 | idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx); | |
f62b8bb8 AV |
293 | } |
294 | ||
076b0936 ES |
295 | static void mlx5e_get_ethtool_stats(struct net_device *dev, |
296 | struct ethtool_stats *stats, | |
297 | u64 *data) | |
298 | { | |
299 | struct mlx5e_priv *priv = netdev_priv(dev); | |
300 | ||
301 | mlx5e_ethtool_get_ethtool_stats(priv, stats, data); | |
302 | } | |
303 | ||
076b0936 ES |
304 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, |
305 | struct ethtool_ringparam *param) | |
f62b8bb8 | 306 | { |
73281b78 | 307 | param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; |
f62b8bb8 | 308 | param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE; |
73281b78 | 309 | param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames; |
6a9764ef | 310 | param->tx_pending = 1 << priv->channels.params.log_sq_size; |
f62b8bb8 AV |
311 | } |
312 | ||
076b0936 ES |
313 | static void mlx5e_get_ringparam(struct net_device *dev, |
314 | struct ethtool_ringparam *param) | |
f62b8bb8 AV |
315 | { |
316 | struct mlx5e_priv *priv = netdev_priv(dev); | |
076b0936 ES |
317 | |
318 | mlx5e_ethtool_get_ringparam(priv, param); | |
319 | } | |
320 | ||
321 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
322 | struct ethtool_ringparam *param) | |
323 | { | |
546f18ed | 324 | struct mlx5e_channels new_channels = {}; |
f62b8bb8 AV |
325 | u8 log_rq_size; |
326 | u8 log_sq_size; | |
327 | int err = 0; | |
328 | ||
329 | if (param->rx_jumbo_pending) { | |
076b0936 | 330 | netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n", |
f62b8bb8 AV |
331 | __func__); |
332 | return -EINVAL; | |
333 | } | |
334 | if (param->rx_mini_pending) { | |
076b0936 | 335 | netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n", |
f62b8bb8 AV |
336 | __func__); |
337 | return -EINVAL; | |
338 | } | |
cc8e9ebf | 339 | |
73281b78 | 340 | if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) { |
076b0936 | 341 | netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n", |
f62b8bb8 | 342 | __func__, param->rx_pending, |
73281b78 | 343 | 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE); |
fe4c988b SM |
344 | return -EINVAL; |
345 | } | |
346 | ||
f62b8bb8 | 347 | if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) { |
076b0936 | 348 | netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n", |
f62b8bb8 AV |
349 | __func__, param->tx_pending, |
350 | 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); | |
351 | return -EINVAL; | |
352 | } | |
f62b8bb8 | 353 | |
73281b78 | 354 | log_rq_size = order_base_2(param->rx_pending); |
f62b8bb8 | 355 | log_sq_size = order_base_2(param->tx_pending); |
f62b8bb8 | 356 | |
73281b78 | 357 | if (log_rq_size == priv->channels.params.log_rq_mtu_frames && |
6a9764ef | 358 | log_sq_size == priv->channels.params.log_sq_size) |
f62b8bb8 AV |
359 | return 0; |
360 | ||
361 | mutex_lock(&priv->state_lock); | |
98e81b0a | 362 | |
546f18ed | 363 | new_channels.params = priv->channels.params; |
73281b78 | 364 | new_channels.params.log_rq_mtu_frames = log_rq_size; |
546f18ed | 365 | new_channels.params.log_sq_size = log_sq_size; |
98e81b0a | 366 | |
546f18ed SM |
367 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
368 | priv->channels.params = new_channels.params; | |
369 | goto unlock; | |
370 | } | |
98e81b0a | 371 | |
877662e2 | 372 | err = mlx5e_safe_switch_channels(priv, &new_channels, NULL); |
98e81b0a | 373 | |
546f18ed | 374 | unlock: |
f62b8bb8 AV |
375 | mutex_unlock(&priv->state_lock); |
376 | ||
377 | return err; | |
378 | } | |
379 | ||
076b0936 ES |
380 | static int mlx5e_set_ringparam(struct net_device *dev, |
381 | struct ethtool_ringparam *param) | |
f62b8bb8 AV |
382 | { |
383 | struct mlx5e_priv *priv = netdev_priv(dev); | |
f62b8bb8 | 384 | |
076b0936 ES |
385 | return mlx5e_ethtool_set_ringparam(priv, param); |
386 | } | |
387 | ||
388 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
389 | struct ethtool_channels *ch) | |
390 | { | |
779d986d | 391 | ch->max_combined = mlx5e_get_netdev_max_channels(priv->netdev); |
6a9764ef | 392 | ch->combined_count = priv->channels.params.num_channels; |
f62b8bb8 AV |
393 | } |
394 | ||
076b0936 ES |
395 | static void mlx5e_get_channels(struct net_device *dev, |
396 | struct ethtool_channels *ch) | |
f62b8bb8 AV |
397 | { |
398 | struct mlx5e_priv *priv = netdev_priv(dev); | |
076b0936 ES |
399 | |
400 | mlx5e_ethtool_get_channels(priv, ch); | |
401 | } | |
402 | ||
403 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
404 | struct ethtool_channels *ch) | |
405 | { | |
f62b8bb8 | 406 | unsigned int count = ch->combined_count; |
55c2503d | 407 | struct mlx5e_channels new_channels = {}; |
45bf454a | 408 | bool arfs_enabled; |
f62b8bb8 AV |
409 | int err = 0; |
410 | ||
411 | if (!count) { | |
076b0936 | 412 | netdev_info(priv->netdev, "%s: combined_count=0 not supported\n", |
f62b8bb8 AV |
413 | __func__); |
414 | return -EINVAL; | |
415 | } | |
f62b8bb8 | 416 | |
6a9764ef | 417 | if (priv->channels.params.num_channels == count) |
f62b8bb8 AV |
418 | return 0; |
419 | ||
420 | mutex_lock(&priv->state_lock); | |
98e81b0a | 421 | |
55c2503d SM |
422 | new_channels.params = priv->channels.params; |
423 | new_channels.params.num_channels = count; | |
55c2503d SM |
424 | |
425 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
426 | priv->channels.params = new_channels.params; | |
c475e11e TT |
427 | if (!netif_is_rxfh_configured(priv->netdev)) |
428 | mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt, | |
429 | MLX5E_INDIR_RQT_SIZE, count); | |
55c2503d SM |
430 | goto out; |
431 | } | |
432 | ||
076b0936 | 433 | arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE; |
45bf454a MG |
434 | if (arfs_enabled) |
435 | mlx5e_arfs_disable(priv); | |
436 | ||
fb35c534 MP |
437 | if (!netif_is_rxfh_configured(priv->netdev)) |
438 | mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt, | |
439 | MLX5E_INDIR_RQT_SIZE, count); | |
440 | ||
55c2503d | 441 | /* Switch to new channels, set new parameters and close old ones */ |
877662e2 | 442 | err = mlx5e_safe_switch_channels(priv, &new_channels, NULL); |
45bf454a MG |
443 | |
444 | if (arfs_enabled) { | |
877662e2 TT |
445 | int err2 = mlx5e_arfs_enable(priv); |
446 | ||
447 | if (err2) | |
076b0936 | 448 | netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n", |
877662e2 | 449 | __func__, err2); |
45bf454a | 450 | } |
98e81b0a | 451 | |
45bf454a | 452 | out: |
f62b8bb8 AV |
453 | mutex_unlock(&priv->state_lock); |
454 | ||
455 | return err; | |
456 | } | |
457 | ||
076b0936 ES |
458 | static int mlx5e_set_channels(struct net_device *dev, |
459 | struct ethtool_channels *ch) | |
f62b8bb8 | 460 | { |
076b0936 ES |
461 | struct mlx5e_priv *priv = netdev_priv(dev); |
462 | ||
463 | return mlx5e_ethtool_set_channels(priv, ch); | |
464 | } | |
f62b8bb8 | 465 | |
076b0936 ES |
466 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, |
467 | struct ethtool_coalesce *coal) | |
468 | { | |
cbce4f44 TG |
469 | struct net_dim_cq_moder *rx_moder, *tx_moder; |
470 | ||
7524a5d8 | 471 | if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) |
9eb78923 | 472 | return -EOPNOTSUPP; |
7524a5d8 | 473 | |
cbce4f44 TG |
474 | rx_moder = &priv->channels.params.rx_cq_moderation; |
475 | coal->rx_coalesce_usecs = rx_moder->usec; | |
476 | coal->rx_max_coalesced_frames = rx_moder->pkts; | |
477 | coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled; | |
478 | ||
479 | tx_moder = &priv->channels.params.tx_cq_moderation; | |
480 | coal->tx_coalesce_usecs = tx_moder->usec; | |
481 | coal->tx_max_coalesced_frames = tx_moder->pkts; | |
482 | coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled; | |
f62b8bb8 AV |
483 | |
484 | return 0; | |
485 | } | |
486 | ||
076b0936 ES |
487 | static int mlx5e_get_coalesce(struct net_device *netdev, |
488 | struct ethtool_coalesce *coal) | |
489 | { | |
490 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
491 | ||
492 | return mlx5e_ethtool_get_coalesce(priv, coal); | |
493 | } | |
494 | ||
b392a207 MS |
495 | #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD |
496 | #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT | |
497 | ||
546f18ed SM |
498 | static void |
499 | mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal) | |
f62b8bb8 | 500 | { |
f62b8bb8 | 501 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 AV |
502 | int tc; |
503 | int i; | |
504 | ||
ff9c852f SM |
505 | for (i = 0; i < priv->channels.num; ++i) { |
506 | struct mlx5e_channel *c = priv->channels.c[i]; | |
f62b8bb8 AV |
507 | |
508 | for (tc = 0; tc < c->num_tc; tc++) { | |
509 | mlx5_core_modify_cq_moderation(mdev, | |
510 | &c->sq[tc].cq.mcq, | |
511 | coal->tx_coalesce_usecs, | |
512 | coal->tx_max_coalesced_frames); | |
513 | } | |
514 | ||
515 | mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq, | |
516 | coal->rx_coalesce_usecs, | |
517 | coal->rx_max_coalesced_frames); | |
518 | } | |
546f18ed | 519 | } |
f62b8bb8 | 520 | |
076b0936 ES |
521 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, |
522 | struct ethtool_coalesce *coal) | |
546f18ed | 523 | { |
cbce4f44 | 524 | struct net_dim_cq_moder *rx_moder, *tx_moder; |
546f18ed SM |
525 | struct mlx5_core_dev *mdev = priv->mdev; |
526 | struct mlx5e_channels new_channels = {}; | |
527 | int err = 0; | |
528 | bool reset; | |
cb3c7fd4 | 529 | |
546f18ed SM |
530 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
531 | return -EOPNOTSUPP; | |
532 | ||
b392a207 MS |
533 | if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || |
534 | coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { | |
535 | netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n", | |
536 | __func__, MLX5E_MAX_COAL_TIME); | |
537 | return -ERANGE; | |
538 | } | |
539 | ||
540 | if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || | |
541 | coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { | |
542 | netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n", | |
543 | __func__, MLX5E_MAX_COAL_FRAMES); | |
544 | return -ERANGE; | |
545 | } | |
546 | ||
546f18ed SM |
547 | mutex_lock(&priv->state_lock); |
548 | new_channels.params = priv->channels.params; | |
549 | ||
cbce4f44 TG |
550 | rx_moder = &new_channels.params.rx_cq_moderation; |
551 | rx_moder->usec = coal->rx_coalesce_usecs; | |
552 | rx_moder->pkts = coal->rx_max_coalesced_frames; | |
553 | new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce; | |
554 | ||
555 | tx_moder = &new_channels.params.tx_cq_moderation; | |
556 | tx_moder->usec = coal->tx_coalesce_usecs; | |
557 | tx_moder->pkts = coal->tx_max_coalesced_frames; | |
558 | new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce; | |
546f18ed SM |
559 | |
560 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
561 | priv->channels.params = new_channels.params; | |
562 | goto out; | |
563 | } | |
564 | /* we are opened */ | |
565 | ||
cbce4f44 TG |
566 | reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) || |
567 | (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled); | |
568 | ||
546f18ed SM |
569 | if (!reset) { |
570 | mlx5e_set_priv_channels_coalesce(priv, coal); | |
571 | priv->channels.params = new_channels.params; | |
572 | goto out; | |
573 | } | |
574 | ||
877662e2 | 575 | err = mlx5e_safe_switch_channels(priv, &new_channels, NULL); |
546f18ed SM |
576 | |
577 | out: | |
2fcb92fb | 578 | mutex_unlock(&priv->state_lock); |
cb3c7fd4 | 579 | return err; |
f62b8bb8 AV |
580 | } |
581 | ||
076b0936 ES |
582 | static int mlx5e_set_coalesce(struct net_device *netdev, |
583 | struct ethtool_coalesce *coal) | |
584 | { | |
585 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
586 | ||
587 | return mlx5e_ethtool_set_coalesce(priv, coal); | |
588 | } | |
589 | ||
6a897372 AL |
590 | static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev, |
591 | unsigned long *supported_modes, | |
665bc539 | 592 | u32 eth_proto_cap) |
f62b8bb8 | 593 | { |
7abc2110 | 594 | unsigned long proto_cap = eth_proto_cap; |
6a897372 AL |
595 | struct ptys2ethtool_config *table; |
596 | u32 max_size; | |
665bc539 | 597 | int proto; |
f62b8bb8 | 598 | |
6a897372 AL |
599 | mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size); |
600 | for_each_set_bit(proto, &proto_cap, max_size) | |
665bc539 | 601 | bitmap_or(supported_modes, supported_modes, |
6a897372 | 602 | table[proto].supported, |
665bc539 | 603 | __ETHTOOL_LINK_MODE_MASK_NBITS); |
f62b8bb8 AV |
604 | } |
605 | ||
dd1b9e09 AL |
606 | static void ptys2ethtool_adver_link(unsigned long *advertising_modes, |
607 | u32 eth_proto_cap, bool ext) | |
f62b8bb8 | 608 | { |
7abc2110 | 609 | unsigned long proto_cap = eth_proto_cap; |
6a897372 AL |
610 | struct ptys2ethtool_config *table; |
611 | u32 max_size; | |
665bc539 | 612 | int proto; |
f62b8bb8 | 613 | |
dd1b9e09 AL |
614 | table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; |
615 | max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : | |
616 | ARRAY_SIZE(ptys2legacy_ethtool_table); | |
617 | ||
6a897372 | 618 | for_each_set_bit(proto, &proto_cap, max_size) |
665bc539 | 619 | bitmap_or(advertising_modes, advertising_modes, |
6a897372 | 620 | table[proto].advertised, |
665bc539 | 621 | __ETHTOOL_LINK_MODE_MASK_NBITS); |
f62b8bb8 AV |
622 | } |
623 | ||
6cfa9460 SA |
624 | static const u32 pplm_fec_2_ethtool[] = { |
625 | [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF, | |
626 | [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER, | |
627 | [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS, | |
628 | }; | |
629 | ||
630 | static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size) | |
631 | { | |
632 | int mode = 0; | |
633 | ||
634 | if (!fec_mode) | |
635 | return ETHTOOL_FEC_AUTO; | |
636 | ||
637 | mode = find_first_bit(&fec_mode, size); | |
638 | ||
639 | if (mode < ARRAY_SIZE(pplm_fec_2_ethtool)) | |
640 | return pplm_fec_2_ethtool[mode]; | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
645 | /* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */ | |
646 | static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code) | |
647 | { | |
648 | u32 offset; | |
649 | ||
650 | offset = find_first_bit(ðtool_fec_code, sizeof(u32)); | |
651 | offset -= ETHTOOL_FEC_OFF_BIT; | |
652 | offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT; | |
653 | ||
654 | return offset; | |
655 | } | |
656 | ||
657 | static int get_fec_supported_advertised(struct mlx5_core_dev *dev, | |
658 | struct ethtool_link_ksettings *link_ksettings) | |
659 | { | |
660 | u_long fec_caps = 0; | |
661 | u32 active_fec = 0; | |
662 | u32 offset; | |
663 | u32 bitn; | |
664 | int err; | |
665 | ||
666 | err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps); | |
667 | if (err) | |
668 | return (err == -EOPNOTSUPP) ? 0 : err; | |
669 | ||
670 | err = mlx5e_get_fec_mode(dev, &active_fec, NULL); | |
671 | if (err) | |
672 | return err; | |
673 | ||
674 | for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) { | |
675 | u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn]; | |
676 | ||
677 | offset = ethtool_fec2ethtool_caps(ethtool_bitmask); | |
678 | __set_bit(offset, link_ksettings->link_modes.supported); | |
679 | } | |
680 | ||
681 | active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE); | |
682 | offset = ethtool_fec2ethtool_caps(active_fec); | |
683 | __set_bit(offset, link_ksettings->link_modes.advertising); | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
46e9d0b6 EBE |
688 | static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings, |
689 | u32 eth_proto_cap, | |
690 | u8 connector_type) | |
f62b8bb8 | 691 | { |
46e9d0b6 EBE |
692 | if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) { |
693 | if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | |
694 | | MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | |
695 | | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | |
696 | | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | |
697 | | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | |
698 | | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { | |
699 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
700 | supported, | |
701 | FIBRE); | |
702 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
703 | advertising, | |
704 | FIBRE); | |
705 | } | |
706 | ||
707 | if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4) | |
708 | | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | |
709 | | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | |
710 | | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | |
711 | | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) { | |
712 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
713 | supported, | |
714 | Backplane); | |
715 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
716 | advertising, | |
717 | Backplane); | |
718 | } | |
719 | return; | |
f62b8bb8 AV |
720 | } |
721 | ||
46e9d0b6 EBE |
722 | switch (connector_type) { |
723 | case MLX5E_PORT_TP: | |
724 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
725 | supported, TP); | |
726 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
727 | advertising, TP); | |
728 | break; | |
729 | case MLX5E_PORT_AUI: | |
730 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
731 | supported, AUI); | |
732 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
733 | advertising, AUI); | |
734 | break; | |
735 | case MLX5E_PORT_BNC: | |
736 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
737 | supported, BNC); | |
738 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
739 | advertising, BNC); | |
740 | break; | |
741 | case MLX5E_PORT_MII: | |
742 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
743 | supported, MII); | |
744 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
745 | advertising, MII); | |
746 | break; | |
747 | case MLX5E_PORT_FIBRE: | |
748 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
749 | supported, FIBRE); | |
750 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
751 | advertising, FIBRE); | |
752 | break; | |
753 | case MLX5E_PORT_DA: | |
754 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
755 | supported, Backplane); | |
756 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
757 | advertising, Backplane); | |
758 | break; | |
759 | case MLX5E_PORT_NONE: | |
760 | case MLX5E_PORT_OTHER: | |
761 | default: | |
762 | break; | |
f62b8bb8 | 763 | } |
f62b8bb8 AV |
764 | } |
765 | ||
766 | static void get_speed_duplex(struct net_device *netdev, | |
767 | u32 eth_proto_oper, | |
665bc539 | 768 | struct ethtool_link_ksettings *link_ksettings) |
f62b8bb8 | 769 | { |
a08b4ed1 | 770 | struct mlx5e_priv *priv = netdev_priv(netdev); |
f62b8bb8 AV |
771 | u32 speed = SPEED_UNKNOWN; |
772 | u8 duplex = DUPLEX_UNKNOWN; | |
773 | ||
774 | if (!netif_carrier_ok(netdev)) | |
775 | goto out; | |
776 | ||
a08b4ed1 | 777 | speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper); |
2c81bfd5 HN |
778 | if (!speed) { |
779 | speed = SPEED_UNKNOWN; | |
780 | goto out; | |
f62b8bb8 | 781 | } |
2c81bfd5 HN |
782 | |
783 | duplex = DUPLEX_FULL; | |
784 | ||
f62b8bb8 | 785 | out: |
665bc539 GP |
786 | link_ksettings->base.speed = speed; |
787 | link_ksettings->base.duplex = duplex; | |
f62b8bb8 AV |
788 | } |
789 | ||
6a897372 | 790 | static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap, |
665bc539 | 791 | struct ethtool_link_ksettings *link_ksettings) |
f62b8bb8 | 792 | { |
665bc539 | 793 | unsigned long *supported = link_ksettings->link_modes.supported; |
6a897372 | 794 | ptys2ethtool_supported_link(mdev, supported, eth_proto_cap); |
665bc539 | 795 | |
665bc539 | 796 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause); |
f62b8bb8 AV |
797 | } |
798 | ||
dd1b9e09 AL |
799 | static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause, |
800 | struct ethtool_link_ksettings *link_ksettings, | |
801 | bool ext) | |
f62b8bb8 | 802 | { |
665bc539 | 803 | unsigned long *advertising = link_ksettings->link_modes.advertising; |
dd1b9e09 | 804 | ptys2ethtool_adver_link(advertising, eth_proto_cap, ext); |
665bc539 | 805 | |
e3c19503 | 806 | if (rx_pause) |
665bc539 GP |
807 | ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause); |
808 | if (tx_pause ^ rx_pause) | |
809 | ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause); | |
f62b8bb8 AV |
810 | } |
811 | ||
5b4793f8 EBE |
812 | static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = { |
813 | [MLX5E_PORT_UNKNOWN] = PORT_OTHER, | |
814 | [MLX5E_PORT_NONE] = PORT_NONE, | |
815 | [MLX5E_PORT_TP] = PORT_TP, | |
816 | [MLX5E_PORT_AUI] = PORT_AUI, | |
817 | [MLX5E_PORT_BNC] = PORT_BNC, | |
818 | [MLX5E_PORT_MII] = PORT_MII, | |
819 | [MLX5E_PORT_FIBRE] = PORT_FIBRE, | |
820 | [MLX5E_PORT_DA] = PORT_DA, | |
821 | [MLX5E_PORT_OTHER] = PORT_OTHER, | |
822 | }; | |
823 | ||
824 | static u8 get_connector_port(u32 eth_proto, u8 connector_type) | |
f62b8bb8 | 825 | { |
5b4793f8 EBE |
826 | if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER) |
827 | return ptys2connector_type[connector_type]; | |
828 | ||
61bf2125 OG |
829 | if (eth_proto & |
830 | (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | | |
831 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | | |
832 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | | |
833 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { | |
834 | return PORT_FIBRE; | |
f62b8bb8 AV |
835 | } |
836 | ||
61bf2125 OG |
837 | if (eth_proto & |
838 | (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | | |
839 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | | |
840 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) { | |
841 | return PORT_DA; | |
f62b8bb8 AV |
842 | } |
843 | ||
61bf2125 OG |
844 | if (eth_proto & |
845 | (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | | |
846 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | | |
847 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | | |
848 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) { | |
849 | return PORT_NONE; | |
f62b8bb8 AV |
850 | } |
851 | ||
852 | return PORT_OTHER; | |
853 | } | |
854 | ||
6a897372 | 855 | static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp, |
665bc539 | 856 | struct ethtool_link_ksettings *link_ksettings) |
f62b8bb8 | 857 | { |
665bc539 | 858 | unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising; |
dd1b9e09 | 859 | bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); |
665bc539 | 860 | |
dd1b9e09 | 861 | ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext); |
f62b8bb8 AV |
862 | } |
863 | ||
371289b6 OG |
864 | int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, |
865 | struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 866 | { |
f62b8bb8 | 867 | struct mlx5_core_dev *mdev = priv->mdev; |
c4f287c4 | 868 | u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; |
b383b544 GP |
869 | u32 rx_pause = 0; |
870 | u32 tx_pause = 0; | |
f62b8bb8 AV |
871 | u32 eth_proto_cap; |
872 | u32 eth_proto_admin; | |
873 | u32 eth_proto_lp; | |
874 | u32 eth_proto_oper; | |
52244d96 GP |
875 | u8 an_disable_admin; |
876 | u8 an_status; | |
5b4793f8 | 877 | u8 connector_type; |
dd1b9e09 | 878 | bool admin_ext; |
6a897372 | 879 | bool ext; |
f62b8bb8 AV |
880 | int err; |
881 | ||
a05bdefa | 882 | err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1); |
f62b8bb8 | 883 | if (err) { |
371289b6 | 884 | netdev_err(priv->netdev, "%s: query port ptys failed: %d\n", |
f62b8bb8 | 885 | __func__, err); |
6cfa9460 | 886 | goto err_query_regs; |
f62b8bb8 | 887 | } |
6a897372 AL |
888 | ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); |
889 | eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, | |
890 | eth_proto_capability); | |
891 | eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, | |
892 | eth_proto_admin); | |
dd1b9e09 AL |
893 | /* Fields: eth_proto_admin and ext_eth_proto_admin are |
894 | * mutually exclusive. Hence try reading legacy advertising | |
895 | * when extended advertising is zero. | |
896 | * admin_ext indicates how eth_proto_admin should be | |
897 | * interpreted | |
898 | */ | |
899 | admin_ext = ext; | |
900 | if (ext && !eth_proto_admin) { | |
901 | eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false, | |
902 | eth_proto_admin); | |
903 | admin_ext = false; | |
904 | } | |
905 | ||
6a897372 AL |
906 | eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, |
907 | eth_proto_oper); | |
908 | eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise); | |
909 | an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin); | |
910 | an_status = MLX5_GET(ptys_reg, out, an_status); | |
911 | connector_type = MLX5_GET(ptys_reg, out, connector_type); | |
f62b8bb8 | 912 | |
b383b544 GP |
913 | mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); |
914 | ||
665bc539 GP |
915 | ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); |
916 | ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); | |
f62b8bb8 | 917 | |
6a897372 | 918 | get_supported(mdev, eth_proto_cap, link_ksettings); |
dd1b9e09 AL |
919 | get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings, |
920 | admin_ext); | |
371289b6 | 921 | get_speed_duplex(priv->netdev, eth_proto_oper, link_ksettings); |
f62b8bb8 AV |
922 | |
923 | eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap; | |
924 | ||
5b4793f8 EBE |
925 | link_ksettings->base.port = get_connector_port(eth_proto_oper, |
926 | connector_type); | |
46e9d0b6 EBE |
927 | ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin, |
928 | connector_type); | |
6a897372 | 929 | get_lp_advertising(mdev, eth_proto_lp, link_ksettings); |
f62b8bb8 | 930 | |
52244d96 GP |
931 | if (an_status == MLX5_AN_COMPLETE) |
932 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
933 | lp_advertising, Autoneg); | |
934 | ||
935 | link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE : | |
936 | AUTONEG_ENABLE; | |
937 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, | |
938 | Autoneg); | |
6cfa9460 | 939 | |
2eb1e425 SA |
940 | err = get_fec_supported_advertised(mdev, link_ksettings); |
941 | if (err) { | |
371289b6 | 942 | netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n", |
6cfa9460 | 943 | __func__, err); |
2eb1e425 SA |
944 | err = 0; /* don't fail caps query because of FEC error */ |
945 | } | |
6cfa9460 | 946 | |
52244d96 GP |
947 | if (!an_disable_admin) |
948 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
949 | advertising, Autoneg); | |
950 | ||
6cfa9460 | 951 | err_query_regs: |
f62b8bb8 AV |
952 | return err; |
953 | } | |
954 | ||
371289b6 OG |
955 | static int mlx5e_get_link_ksettings(struct net_device *netdev, |
956 | struct ethtool_link_ksettings *link_ksettings) | |
957 | { | |
958 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
959 | ||
960 | return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings); | |
961 | } | |
962 | ||
665bc539 | 963 | static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) |
f62b8bb8 AV |
964 | { |
965 | u32 i, ptys_modes = 0; | |
966 | ||
967 | for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { | |
6a897372 AL |
968 | if (*ptys2legacy_ethtool_table[i].advertised == 0) |
969 | continue; | |
970 | if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised, | |
665bc539 GP |
971 | link_modes, |
972 | __ETHTOOL_LINK_MODE_MASK_NBITS)) | |
f62b8bb8 AV |
973 | ptys_modes |= MLX5E_PROT_MASK(i); |
974 | } | |
975 | ||
976 | return ptys_modes; | |
977 | } | |
978 | ||
6a897372 AL |
979 | static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes) |
980 | { | |
981 | u32 i, ptys_modes = 0; | |
982 | unsigned long modes[2]; | |
983 | ||
984 | for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) { | |
985 | if (*ptys2ext_ethtool_table[i].advertised == 0) | |
986 | continue; | |
987 | memset(modes, 0, sizeof(modes)); | |
988 | bitmap_and(modes, ptys2ext_ethtool_table[i].advertised, | |
989 | link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
990 | ||
991 | if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] && | |
992 | modes[1] == ptys2ext_ethtool_table[i].advertised[1]) | |
993 | ptys_modes |= MLX5E_PROT_MASK(i); | |
994 | } | |
995 | return ptys_modes; | |
996 | } | |
997 | ||
371289b6 OG |
998 | int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, |
999 | const struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 1000 | { |
f62b8bb8 | 1001 | struct mlx5_core_dev *mdev = priv->mdev; |
bc4e12ff | 1002 | struct mlx5e_port_eth_proto eproto; |
52244d96 GP |
1003 | bool an_changes = false; |
1004 | u8 an_disable_admin; | |
6a897372 AL |
1005 | bool ext_supported; |
1006 | bool ext_requested; | |
52244d96 GP |
1007 | u8 an_disable_cap; |
1008 | bool an_disable; | |
f62b8bb8 | 1009 | u32 link_modes; |
52244d96 | 1010 | u8 an_status; |
f62b8bb8 | 1011 | u32 speed; |
f62b8bb8 AV |
1012 | int err; |
1013 | ||
6a897372 | 1014 | u32 (*ethtool2ptys_adver_func)(const unsigned long *adver); |
f62b8bb8 | 1015 | |
6a897372 AL |
1016 | #define MLX5E_PTYS_EXT ((1ULL << ETHTOOL_LINK_MODE_50000baseKR_Full_BIT) - 1) |
1017 | ||
8d047bf5 AL |
1018 | ext_requested = !!(link_ksettings->link_modes.advertising[0] > |
1019 | MLX5E_PTYS_EXT || | |
1020 | link_ksettings->link_modes.advertising[1]); | |
6a897372 | 1021 | ext_supported = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); |
dd1b9e09 | 1022 | ext_requested &= ext_supported; |
f62b8bb8 | 1023 | |
6a897372 AL |
1024 | speed = link_ksettings->base.speed; |
1025 | ethtool2ptys_adver_func = ext_requested ? | |
1026 | mlx5e_ethtool2ptys_ext_adver_link : | |
1027 | mlx5e_ethtool2ptys_adver_link; | |
dd1b9e09 | 1028 | err = mlx5_port_query_eth_proto(mdev, 1, ext_requested, &eproto); |
f62b8bb8 | 1029 | if (err) { |
bc4e12ff | 1030 | netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n", |
f62b8bb8 AV |
1031 | __func__, err); |
1032 | goto out; | |
1033 | } | |
6a897372 AL |
1034 | link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ? |
1035 | ethtool2ptys_adver_func(link_ksettings->link_modes.advertising) : | |
1036 | mlx5e_port_speed2linkmodes(mdev, speed); | |
f62b8bb8 | 1037 | |
bc4e12ff | 1038 | link_modes = link_modes & eproto.cap; |
f62b8bb8 | 1039 | if (!link_modes) { |
371289b6 | 1040 | netdev_err(priv->netdev, "%s: Not supported link mode(s) requested", |
f62b8bb8 AV |
1041 | __func__); |
1042 | err = -EINVAL; | |
1043 | goto out; | |
1044 | } | |
1045 | ||
bc4e12ff AL |
1046 | mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap, |
1047 | &an_disable_admin); | |
52244d96 GP |
1048 | |
1049 | an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE; | |
1050 | an_changes = ((!an_disable && an_disable_admin) || | |
1051 | (an_disable && !an_disable_admin)); | |
1052 | ||
bc4e12ff | 1053 | if (!an_changes && link_modes == eproto.admin) |
f62b8bb8 AV |
1054 | goto out; |
1055 | ||
dd1b9e09 | 1056 | mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext_requested); |
667daeda | 1057 | mlx5_toggle_port_link(mdev); |
f62b8bb8 | 1058 | |
f62b8bb8 AV |
1059 | out: |
1060 | return err; | |
1061 | } | |
1062 | ||
371289b6 OG |
1063 | static int mlx5e_set_link_ksettings(struct net_device *netdev, |
1064 | const struct ethtool_link_ksettings *link_ksettings) | |
1065 | { | |
1066 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1067 | ||
1068 | return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings); | |
1069 | } | |
1070 | ||
a5355de8 OG |
1071 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv) |
1072 | { | |
bbeb53b8 | 1073 | return sizeof(priv->rss_params.toeplitz_hash_key); |
a5355de8 OG |
1074 | } |
1075 | ||
2d75b2bc AS |
1076 | static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) |
1077 | { | |
1078 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1079 | ||
a5355de8 | 1080 | return mlx5e_ethtool_get_rxfh_key_size(priv); |
2d75b2bc AS |
1081 | } |
1082 | ||
a5355de8 | 1083 | u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv) |
2d75b2bc AS |
1084 | { |
1085 | return MLX5E_INDIR_RQT_SIZE; | |
1086 | } | |
1087 | ||
a5355de8 OG |
1088 | static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev) |
1089 | { | |
1090 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1091 | ||
1092 | return mlx5e_ethtool_get_rxfh_indir_size(priv); | |
1093 | } | |
1094 | ||
2be6967c SM |
1095 | static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, |
1096 | u8 *hfunc) | |
1097 | { | |
1098 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
bbeb53b8 | 1099 | struct mlx5e_rss_params *rss = &priv->rss_params; |
2be6967c | 1100 | |
2d75b2bc | 1101 | if (indir) |
bbeb53b8 AL |
1102 | memcpy(indir, rss->indirection_rqt, |
1103 | sizeof(rss->indirection_rqt)); | |
2d75b2bc AS |
1104 | |
1105 | if (key) | |
bbeb53b8 AL |
1106 | memcpy(key, rss->toeplitz_hash_key, |
1107 | sizeof(rss->toeplitz_hash_key)); | |
2d75b2bc | 1108 | |
2be6967c | 1109 | if (hfunc) |
bbeb53b8 | 1110 | *hfunc = rss->hfunc; |
2be6967c SM |
1111 | |
1112 | return 0; | |
1113 | } | |
1114 | ||
98e81b0a | 1115 | static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, |
2be6967c SM |
1116 | const u8 *key, const u8 hfunc) |
1117 | { | |
98e81b0a | 1118 | struct mlx5e_priv *priv = netdev_priv(dev); |
bbeb53b8 | 1119 | struct mlx5e_rss_params *rss = &priv->rss_params; |
bdfc028d | 1120 | int inlen = MLX5_ST_SZ_BYTES(modify_tir_in); |
1d3398fa | 1121 | bool hash_changed = false; |
bdfc028d | 1122 | void *in; |
2be6967c | 1123 | |
2d75b2bc AS |
1124 | if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && |
1125 | (hfunc != ETH_RSS_HASH_XOR) && | |
2be6967c SM |
1126 | (hfunc != ETH_RSS_HASH_TOP)) |
1127 | return -EINVAL; | |
1128 | ||
1b9a07ee | 1129 | in = kvzalloc(inlen, GFP_KERNEL); |
bdfc028d TT |
1130 | if (!in) |
1131 | return -ENOMEM; | |
1132 | ||
2be6967c SM |
1133 | mutex_lock(&priv->state_lock); |
1134 | ||
bbeb53b8 AL |
1135 | if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) { |
1136 | rss->hfunc = hfunc; | |
1d3398fa GP |
1137 | hash_changed = true; |
1138 | } | |
1139 | ||
a5f97fee | 1140 | if (indir) { |
bbeb53b8 AL |
1141 | memcpy(rss->indirection_rqt, indir, |
1142 | sizeof(rss->indirection_rqt)); | |
a5f97fee SM |
1143 | |
1144 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
1145 | u32 rqtn = priv->indir_rqt.rqtn; | |
1146 | struct mlx5e_redirect_rqt_param rrp = { | |
1147 | .is_rss = true, | |
e270e966 AM |
1148 | { |
1149 | .rss = { | |
bbeb53b8 | 1150 | .hfunc = rss->hfunc, |
e270e966 AM |
1151 | .channels = &priv->channels, |
1152 | }, | |
1153 | }, | |
a5f97fee SM |
1154 | }; |
1155 | ||
1156 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); | |
1157 | } | |
1158 | } | |
1159 | ||
1d3398fa | 1160 | if (key) { |
bbeb53b8 AL |
1161 | memcpy(rss->toeplitz_hash_key, key, |
1162 | sizeof(rss->toeplitz_hash_key)); | |
1163 | hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP; | |
1d3398fa | 1164 | } |
2d75b2bc | 1165 | |
1d3398fa GP |
1166 | if (hash_changed) |
1167 | mlx5e_modify_tirs_hash(priv, in, inlen); | |
2d75b2bc | 1168 | |
2be6967c SM |
1169 | mutex_unlock(&priv->state_lock); |
1170 | ||
bdfc028d TT |
1171 | kvfree(in); |
1172 | ||
1173 | return 0; | |
2be6967c SM |
1174 | } |
1175 | ||
2afa609f IK |
1176 | #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100 |
1177 | #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000 | |
1178 | #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85 | |
1179 | #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80 | |
1180 | #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \ | |
1181 | max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \ | |
1182 | (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100) | |
1183 | ||
1184 | static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev, | |
1185 | u16 *pfc_prevention_tout) | |
1186 | { | |
1187 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1188 | struct mlx5_core_dev *mdev = priv->mdev; | |
1189 | ||
1190 | if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || | |
1191 | !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) | |
1192 | return -EOPNOTSUPP; | |
1193 | ||
1194 | return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL); | |
1195 | } | |
1196 | ||
1197 | static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev, | |
1198 | u16 pfc_preven) | |
1199 | { | |
1200 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1201 | struct mlx5_core_dev *mdev = priv->mdev; | |
1202 | u16 critical_tout; | |
1203 | u16 minor; | |
1204 | ||
1205 | if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || | |
1206 | !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) | |
1207 | return -EOPNOTSUPP; | |
1208 | ||
1209 | critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ? | |
1210 | MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC : | |
1211 | pfc_preven; | |
1212 | ||
1213 | if (critical_tout != PFC_STORM_PREVENTION_DISABLE && | |
1214 | (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC || | |
1215 | critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) { | |
1216 | netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n", | |
1217 | __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, | |
1218 | MLX5E_PFC_PREVEN_TOUT_MAX_MSEC); | |
1219 | return -EINVAL; | |
1220 | } | |
1221 | ||
1222 | minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout); | |
1223 | return mlx5_set_port_stall_watermark(mdev, critical_tout, | |
1224 | minor); | |
1225 | } | |
1226 | ||
58d52291 AS |
1227 | static int mlx5e_get_tunable(struct net_device *dev, |
1228 | const struct ethtool_tunable *tuna, | |
1229 | void *data) | |
1230 | { | |
c4554fbc | 1231 | int err; |
58d52291 AS |
1232 | |
1233 | switch (tuna->id) { | |
2afa609f IK |
1234 | case ETHTOOL_PFC_PREVENTION_TOUT: |
1235 | err = mlx5e_get_pfc_prevention_tout(dev, data); | |
1236 | break; | |
58d52291 AS |
1237 | default: |
1238 | err = -EINVAL; | |
1239 | break; | |
1240 | } | |
1241 | ||
1242 | return err; | |
1243 | } | |
1244 | ||
1245 | static int mlx5e_set_tunable(struct net_device *dev, | |
1246 | const struct ethtool_tunable *tuna, | |
1247 | const void *data) | |
1248 | { | |
1249 | struct mlx5e_priv *priv = netdev_priv(dev); | |
c4554fbc | 1250 | int err; |
546f18ed SM |
1251 | |
1252 | mutex_lock(&priv->state_lock); | |
58d52291 AS |
1253 | |
1254 | switch (tuna->id) { | |
2afa609f IK |
1255 | case ETHTOOL_PFC_PREVENTION_TOUT: |
1256 | err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data); | |
58d52291 AS |
1257 | break; |
1258 | default: | |
1259 | err = -EINVAL; | |
1260 | break; | |
1261 | } | |
1262 | ||
546f18ed | 1263 | mutex_unlock(&priv->state_lock); |
58d52291 AS |
1264 | return err; |
1265 | } | |
1266 | ||
371289b6 OG |
1267 | void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, |
1268 | struct ethtool_pauseparam *pauseparam) | |
3c2d18ef | 1269 | { |
3c2d18ef AS |
1270 | struct mlx5_core_dev *mdev = priv->mdev; |
1271 | int err; | |
1272 | ||
1273 | err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause, | |
1274 | &pauseparam->tx_pause); | |
1275 | if (err) { | |
371289b6 | 1276 | netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n", |
3c2d18ef AS |
1277 | __func__, err); |
1278 | } | |
1279 | } | |
1280 | ||
371289b6 OG |
1281 | static void mlx5e_get_pauseparam(struct net_device *netdev, |
1282 | struct ethtool_pauseparam *pauseparam) | |
1283 | { | |
1284 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1285 | ||
1286 | mlx5e_ethtool_get_pauseparam(priv, pauseparam); | |
1287 | } | |
1288 | ||
1289 | int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, | |
1290 | struct ethtool_pauseparam *pauseparam) | |
3c2d18ef | 1291 | { |
3c2d18ef AS |
1292 | struct mlx5_core_dev *mdev = priv->mdev; |
1293 | int err; | |
1294 | ||
1295 | if (pauseparam->autoneg) | |
1296 | return -EINVAL; | |
1297 | ||
1298 | err = mlx5_set_port_pause(mdev, | |
1299 | pauseparam->rx_pause ? 1 : 0, | |
1300 | pauseparam->tx_pause ? 1 : 0); | |
1301 | if (err) { | |
371289b6 | 1302 | netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n", |
3c2d18ef AS |
1303 | __func__, err); |
1304 | } | |
1305 | ||
1306 | return err; | |
1307 | } | |
1308 | ||
371289b6 OG |
1309 | static int mlx5e_set_pauseparam(struct net_device *netdev, |
1310 | struct ethtool_pauseparam *pauseparam) | |
1311 | { | |
1312 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1313 | ||
1314 | return mlx5e_ethtool_set_pauseparam(priv, pauseparam); | |
1315 | } | |
1316 | ||
3844b07e FD |
1317 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1318 | struct ethtool_ts_info *info) | |
ef9814de | 1319 | { |
7c39afb3 | 1320 | struct mlx5_core_dev *mdev = priv->mdev; |
ef9814de | 1321 | |
6dbc80ca | 1322 | info->phc_index = mlx5_clock_get_ptp_index(mdev); |
ef9814de | 1323 | |
6dbc80ca MS |
1324 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || |
1325 | info->phc_index == -1) | |
ef9814de EBE |
1326 | return 0; |
1327 | ||
47654204 AH |
1328 | info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | |
1329 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1330 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
ef9814de | 1331 | |
f0b38117 MD |
1332 | info->tx_types = BIT(HWTSTAMP_TX_OFF) | |
1333 | BIT(HWTSTAMP_TX_ON); | |
ef9814de | 1334 | |
f0b38117 MD |
1335 | info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | |
1336 | BIT(HWTSTAMP_FILTER_ALL); | |
ef9814de EBE |
1337 | |
1338 | return 0; | |
1339 | } | |
1340 | ||
3844b07e FD |
1341 | static int mlx5e_get_ts_info(struct net_device *dev, |
1342 | struct ethtool_ts_info *info) | |
1343 | { | |
1344 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1345 | ||
1346 | return mlx5e_ethtool_get_ts_info(priv, info); | |
1347 | } | |
1348 | ||
928cfe87 TT |
1349 | static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev) |
1350 | { | |
1351 | __u32 ret = 0; | |
1352 | ||
1353 | if (MLX5_CAP_GEN(mdev, wol_g)) | |
1354 | ret |= WAKE_MAGIC; | |
1355 | ||
1356 | if (MLX5_CAP_GEN(mdev, wol_s)) | |
1357 | ret |= WAKE_MAGICSECURE; | |
1358 | ||
1359 | if (MLX5_CAP_GEN(mdev, wol_a)) | |
1360 | ret |= WAKE_ARP; | |
1361 | ||
1362 | if (MLX5_CAP_GEN(mdev, wol_b)) | |
1363 | ret |= WAKE_BCAST; | |
1364 | ||
1365 | if (MLX5_CAP_GEN(mdev, wol_m)) | |
1366 | ret |= WAKE_MCAST; | |
1367 | ||
1368 | if (MLX5_CAP_GEN(mdev, wol_u)) | |
1369 | ret |= WAKE_UCAST; | |
1370 | ||
1371 | if (MLX5_CAP_GEN(mdev, wol_p)) | |
1372 | ret |= WAKE_PHY; | |
1373 | ||
1374 | return ret; | |
1375 | } | |
1376 | ||
1377 | static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode) | |
1378 | { | |
1379 | __u32 ret = 0; | |
1380 | ||
1381 | if (mode & MLX5_WOL_MAGIC) | |
1382 | ret |= WAKE_MAGIC; | |
1383 | ||
1384 | if (mode & MLX5_WOL_SECURED_MAGIC) | |
1385 | ret |= WAKE_MAGICSECURE; | |
1386 | ||
1387 | if (mode & MLX5_WOL_ARP) | |
1388 | ret |= WAKE_ARP; | |
1389 | ||
1390 | if (mode & MLX5_WOL_BROADCAST) | |
1391 | ret |= WAKE_BCAST; | |
1392 | ||
1393 | if (mode & MLX5_WOL_MULTICAST) | |
1394 | ret |= WAKE_MCAST; | |
1395 | ||
1396 | if (mode & MLX5_WOL_UNICAST) | |
1397 | ret |= WAKE_UCAST; | |
1398 | ||
1399 | if (mode & MLX5_WOL_PHY_ACTIVITY) | |
1400 | ret |= WAKE_PHY; | |
1401 | ||
1402 | return ret; | |
1403 | } | |
1404 | ||
1405 | static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode) | |
1406 | { | |
1407 | u8 ret = 0; | |
1408 | ||
1409 | if (mode & WAKE_MAGIC) | |
1410 | ret |= MLX5_WOL_MAGIC; | |
1411 | ||
1412 | if (mode & WAKE_MAGICSECURE) | |
1413 | ret |= MLX5_WOL_SECURED_MAGIC; | |
1414 | ||
1415 | if (mode & WAKE_ARP) | |
1416 | ret |= MLX5_WOL_ARP; | |
1417 | ||
1418 | if (mode & WAKE_BCAST) | |
1419 | ret |= MLX5_WOL_BROADCAST; | |
1420 | ||
1421 | if (mode & WAKE_MCAST) | |
1422 | ret |= MLX5_WOL_MULTICAST; | |
1423 | ||
1424 | if (mode & WAKE_UCAST) | |
1425 | ret |= MLX5_WOL_UNICAST; | |
1426 | ||
1427 | if (mode & WAKE_PHY) | |
1428 | ret |= MLX5_WOL_PHY_ACTIVITY; | |
1429 | ||
1430 | return ret; | |
1431 | } | |
1432 | ||
1433 | static void mlx5e_get_wol(struct net_device *netdev, | |
1434 | struct ethtool_wolinfo *wol) | |
1435 | { | |
1436 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1437 | struct mlx5_core_dev *mdev = priv->mdev; | |
1438 | u8 mlx5_wol_mode; | |
1439 | int err; | |
1440 | ||
1441 | memset(wol, 0, sizeof(*wol)); | |
1442 | ||
1443 | wol->supported = mlx5e_get_wol_supported(mdev); | |
1444 | if (!wol->supported) | |
1445 | return; | |
1446 | ||
1447 | err = mlx5_query_port_wol(mdev, &mlx5_wol_mode); | |
1448 | if (err) | |
1449 | return; | |
1450 | ||
1451 | wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode); | |
1452 | } | |
1453 | ||
1454 | static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
1455 | { | |
1456 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1457 | struct mlx5_core_dev *mdev = priv->mdev; | |
1458 | __u32 wol_supported = mlx5e_get_wol_supported(mdev); | |
1459 | u32 mlx5_wol_mode; | |
1460 | ||
1461 | if (!wol_supported) | |
9eb78923 | 1462 | return -EOPNOTSUPP; |
928cfe87 TT |
1463 | |
1464 | if (wol->wolopts & ~wol_supported) | |
1465 | return -EINVAL; | |
1466 | ||
1467 | mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts); | |
1468 | ||
1469 | return mlx5_set_port_wol(mdev, mlx5_wol_mode); | |
1470 | } | |
1471 | ||
6cfa9460 SA |
1472 | static int mlx5e_get_fecparam(struct net_device *netdev, |
1473 | struct ethtool_fecparam *fecparam) | |
1474 | { | |
1475 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1476 | struct mlx5_core_dev *mdev = priv->mdev; | |
1477 | u8 fec_configured = 0; | |
1478 | u32 fec_active = 0; | |
1479 | int err; | |
1480 | ||
1481 | err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured); | |
1482 | ||
1483 | if (err) | |
1484 | return err; | |
1485 | ||
1486 | fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active, | |
1487 | sizeof(u32) * BITS_PER_BYTE); | |
1488 | ||
1489 | if (!fecparam->active_fec) | |
1490 | return -EOPNOTSUPP; | |
1491 | ||
1492 | fecparam->fec = pplm2ethtool_fec((u_long)fec_configured, | |
1493 | sizeof(u8) * BITS_PER_BYTE); | |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
1498 | static int mlx5e_set_fecparam(struct net_device *netdev, | |
1499 | struct ethtool_fecparam *fecparam) | |
1500 | { | |
1501 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1502 | struct mlx5_core_dev *mdev = priv->mdev; | |
1503 | u8 fec_policy = 0; | |
1504 | int mode; | |
1505 | int err; | |
1506 | ||
1507 | for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) { | |
1508 | if (!(pplm_fec_2_ethtool[mode] & fecparam->fec)) | |
1509 | continue; | |
1510 | fec_policy |= (1 << mode); | |
1511 | break; | |
1512 | } | |
1513 | ||
1514 | err = mlx5e_set_fec_mode(mdev, fec_policy); | |
1515 | ||
1516 | if (err) | |
1517 | return err; | |
1518 | ||
1519 | mlx5_toggle_port_link(mdev); | |
1520 | ||
1521 | return 0; | |
1522 | } | |
1523 | ||
79c48764 GP |
1524 | static u32 mlx5e_get_msglevel(struct net_device *dev) |
1525 | { | |
1526 | return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel; | |
1527 | } | |
1528 | ||
1529 | static void mlx5e_set_msglevel(struct net_device *dev, u32 val) | |
1530 | { | |
1531 | ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val; | |
1532 | } | |
1533 | ||
da54d24e GP |
1534 | static int mlx5e_set_phys_id(struct net_device *dev, |
1535 | enum ethtool_phys_id_state state) | |
1536 | { | |
1537 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1538 | struct mlx5_core_dev *mdev = priv->mdev; | |
1539 | u16 beacon_duration; | |
1540 | ||
1541 | if (!MLX5_CAP_GEN(mdev, beacon_led)) | |
1542 | return -EOPNOTSUPP; | |
1543 | ||
1544 | switch (state) { | |
1545 | case ETHTOOL_ID_ACTIVE: | |
1546 | beacon_duration = MLX5_BEACON_DURATION_INF; | |
1547 | break; | |
1548 | case ETHTOOL_ID_INACTIVE: | |
1549 | beacon_duration = MLX5_BEACON_DURATION_OFF; | |
1550 | break; | |
1551 | default: | |
1552 | return -EOPNOTSUPP; | |
1553 | } | |
1554 | ||
1555 | return mlx5_set_port_beacon(mdev, beacon_duration); | |
1556 | } | |
1557 | ||
bb64143e GP |
1558 | static int mlx5e_get_module_info(struct net_device *netdev, |
1559 | struct ethtool_modinfo *modinfo) | |
1560 | { | |
1561 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1562 | struct mlx5_core_dev *dev = priv->mdev; | |
1563 | int size_read = 0; | |
1564 | u8 data[4]; | |
1565 | ||
1566 | size_read = mlx5_query_module_eeprom(dev, 0, 2, data); | |
1567 | if (size_read < 2) | |
1568 | return -EIO; | |
1569 | ||
1570 | /* data[0] = identifier byte */ | |
1571 | switch (data[0]) { | |
1572 | case MLX5_MODULE_ID_QSFP: | |
1573 | modinfo->type = ETH_MODULE_SFF_8436; | |
1574 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1575 | break; | |
1576 | case MLX5_MODULE_ID_QSFP_PLUS: | |
1577 | case MLX5_MODULE_ID_QSFP28: | |
1578 | /* data[1] = revision id */ | |
1579 | if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) { | |
1580 | modinfo->type = ETH_MODULE_SFF_8636; | |
1581 | modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; | |
1582 | } else { | |
1583 | modinfo->type = ETH_MODULE_SFF_8436; | |
1584 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1585 | } | |
1586 | break; | |
1587 | case MLX5_MODULE_ID_SFP: | |
1588 | modinfo->type = ETH_MODULE_SFF_8472; | |
1589 | modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; | |
1590 | break; | |
1591 | default: | |
1592 | netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n", | |
1593 | __func__, data[0]); | |
1594 | return -EINVAL; | |
1595 | } | |
1596 | ||
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | static int mlx5e_get_module_eeprom(struct net_device *netdev, | |
1601 | struct ethtool_eeprom *ee, | |
1602 | u8 *data) | |
1603 | { | |
1604 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1605 | struct mlx5_core_dev *mdev = priv->mdev; | |
1606 | int offset = ee->offset; | |
1607 | int size_read; | |
1608 | int i = 0; | |
1609 | ||
1610 | if (!ee->len) | |
1611 | return -EINVAL; | |
1612 | ||
1613 | memset(data, 0, ee->len); | |
1614 | ||
1615 | while (i < ee->len) { | |
1616 | size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i, | |
1617 | data + i); | |
1618 | ||
1619 | if (!size_read) | |
1620 | /* Done reading */ | |
1621 | return 0; | |
1622 | ||
1623 | if (size_read < 0) { | |
1624 | netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n", | |
1625 | __func__, size_read); | |
1626 | return 0; | |
1627 | } | |
1628 | ||
1629 | i += size_read; | |
1630 | offset += size_read; | |
1631 | } | |
1632 | ||
1633 | return 0; | |
1634 | } | |
1635 | ||
0088cbbc TG |
1636 | static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable, |
1637 | bool is_rx_cq) | |
4e59e288 | 1638 | { |
9908aa29 TT |
1639 | struct mlx5e_priv *priv = netdev_priv(netdev); |
1640 | struct mlx5_core_dev *mdev = priv->mdev; | |
be7e87f9 | 1641 | struct mlx5e_channels new_channels = {}; |
0088cbbc TG |
1642 | bool mode_changed; |
1643 | u8 cq_period_mode, current_cq_period_mode; | |
9908aa29 | 1644 | |
0088cbbc | 1645 | cq_period_mode = enable ? |
9908aa29 TT |
1646 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : |
1647 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
0088cbbc TG |
1648 | current_cq_period_mode = is_rx_cq ? |
1649 | priv->channels.params.rx_cq_moderation.cq_period_mode : | |
1650 | priv->channels.params.tx_cq_moderation.cq_period_mode; | |
1651 | mode_changed = cq_period_mode != current_cq_period_mode; | |
9908aa29 | 1652 | |
0088cbbc | 1653 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE && |
9908aa29 | 1654 | !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe)) |
9eb78923 | 1655 | return -EOPNOTSUPP; |
9908aa29 | 1656 | |
0088cbbc | 1657 | if (!mode_changed) |
9908aa29 TT |
1658 | return 0; |
1659 | ||
be7e87f9 | 1660 | new_channels.params = priv->channels.params; |
0088cbbc TG |
1661 | if (is_rx_cq) |
1662 | mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode); | |
1663 | else | |
1664 | mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode); | |
9908aa29 | 1665 | |
be7e87f9 SM |
1666 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
1667 | priv->channels.params = new_channels.params; | |
1668 | return 0; | |
1669 | } | |
1670 | ||
877662e2 | 1671 | return mlx5e_safe_switch_channels(priv, &new_channels, NULL); |
be7e87f9 | 1672 | } |
9908aa29 | 1673 | |
0088cbbc TG |
1674 | static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable) |
1675 | { | |
1676 | return set_pflag_cqe_based_moder(netdev, enable, false); | |
1677 | } | |
1678 | ||
1679 | static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable) | |
1680 | { | |
1681 | return set_pflag_cqe_based_moder(netdev, enable, true); | |
1682 | } | |
1683 | ||
be7e87f9 SM |
1684 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val) |
1685 | { | |
1686 | bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS); | |
1687 | struct mlx5e_channels new_channels = {}; | |
1688 | int err = 0; | |
1689 | ||
1690 | if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) | |
1691 | return new_val ? -EOPNOTSUPP : 0; | |
1692 | ||
1693 | if (curr_val == new_val) | |
1694 | return 0; | |
1695 | ||
1696 | new_channels.params = priv->channels.params; | |
1697 | MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val); | |
1698 | ||
be7e87f9 SM |
1699 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
1700 | priv->channels.params = new_channels.params; | |
1701 | return 0; | |
1702 | } | |
1703 | ||
877662e2 | 1704 | err = mlx5e_safe_switch_channels(priv, &new_channels, NULL); |
be7e87f9 SM |
1705 | if (err) |
1706 | return err; | |
1707 | ||
696a97cf EE |
1708 | mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n", |
1709 | MLX5E_GET_PFLAG(&priv->channels.params, | |
1710 | MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF"); | |
1711 | ||
be7e87f9 | 1712 | return 0; |
4e59e288 GP |
1713 | } |
1714 | ||
9bcc8606 SD |
1715 | static int set_pflag_rx_cqe_compress(struct net_device *netdev, |
1716 | bool enable) | |
1717 | { | |
1718 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1719 | struct mlx5_core_dev *mdev = priv->mdev; | |
9bcc8606 SD |
1720 | |
1721 | if (!MLX5_CAP_GEN(mdev, cqe_compression)) | |
9eb78923 | 1722 | return -EOPNOTSUPP; |
9bcc8606 | 1723 | |
7c39afb3 | 1724 | if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) { |
9bcc8606 SD |
1725 | netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n"); |
1726 | return -EINVAL; | |
1727 | } | |
1728 | ||
5eb0249b | 1729 | mlx5e_modify_rx_cqe_compression_locked(priv, enable); |
6a9764ef | 1730 | priv->channels.params.rx_cqe_compress_def = enable; |
9bcc8606 | 1731 | |
5eb0249b | 1732 | return 0; |
9bcc8606 SD |
1733 | } |
1734 | ||
2ccb0a79 TT |
1735 | static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable) |
1736 | { | |
1737 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1738 | struct mlx5_core_dev *mdev = priv->mdev; | |
1739 | struct mlx5e_channels new_channels = {}; | |
2ccb0a79 TT |
1740 | |
1741 | if (enable) { | |
1742 | if (!mlx5e_check_fragmented_striding_rq_cap(mdev)) | |
1743 | return -EOPNOTSUPP; | |
1744 | if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params)) | |
1745 | return -EINVAL; | |
6c3a823e TT |
1746 | } else if (priv->channels.params.lro_en) { |
1747 | netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n"); | |
1748 | return -EINVAL; | |
2ccb0a79 TT |
1749 | } |
1750 | ||
1751 | new_channels.params = priv->channels.params; | |
1752 | ||
1753 | MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable); | |
1754 | mlx5e_set_rq_type(mdev, &new_channels.params); | |
1755 | ||
1756 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
1757 | priv->channels.params = new_channels.params; | |
1758 | return 0; | |
1759 | } | |
1760 | ||
877662e2 | 1761 | return mlx5e_safe_switch_channels(priv, &new_channels, NULL); |
2ccb0a79 TT |
1762 | } |
1763 | ||
b856df28 OG |
1764 | static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable) |
1765 | { | |
1766 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1767 | struct mlx5e_channels *channels = &priv->channels; | |
1768 | struct mlx5e_channel *c; | |
1769 | int i; | |
1770 | ||
1771 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1772 | return 0; | |
1773 | ||
1774 | for (i = 0; i < channels->num; i++) { | |
1775 | c = channels->c[i]; | |
1776 | if (enable) | |
1777 | __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); | |
1778 | else | |
1779 | __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); | |
1780 | } | |
1781 | ||
1782 | return 0; | |
1783 | } | |
1784 | ||
6277053a TT |
1785 | static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable) |
1786 | { | |
1787 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1788 | struct mlx5_core_dev *mdev = priv->mdev; | |
1789 | struct mlx5e_channels new_channels = {}; | |
1790 | int err; | |
1791 | ||
1792 | if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) | |
1793 | return -EOPNOTSUPP; | |
1794 | ||
1795 | new_channels.params = priv->channels.params; | |
1796 | ||
1797 | MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable); | |
1798 | ||
1799 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
1800 | priv->channels.params = new_channels.params; | |
1801 | return 0; | |
1802 | } | |
1803 | ||
877662e2 TT |
1804 | err = mlx5e_safe_switch_channels(priv, &new_channels, NULL); |
1805 | return err; | |
6277053a TT |
1806 | } |
1807 | ||
8ff57c18 TT |
1808 | static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = { |
1809 | { "rx_cqe_moder", set_pflag_rx_cqe_based_moder }, | |
1810 | { "tx_cqe_moder", set_pflag_tx_cqe_based_moder }, | |
1811 | { "rx_cqe_compress", set_pflag_rx_cqe_compress }, | |
1812 | { "rx_striding_rq", set_pflag_rx_striding_rq }, | |
1813 | { "rx_no_csum_complete", set_pflag_rx_no_csum_complete }, | |
6277053a | 1814 | { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe }, |
8ff57c18 TT |
1815 | }; |
1816 | ||
4e59e288 GP |
1817 | static int mlx5e_handle_pflag(struct net_device *netdev, |
1818 | u32 wanted_flags, | |
8ff57c18 | 1819 | enum mlx5e_priv_flag flag) |
4e59e288 GP |
1820 | { |
1821 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
8ff57c18 | 1822 | bool enable = !!(wanted_flags & BIT(flag)); |
6a9764ef | 1823 | u32 changes = wanted_flags ^ priv->channels.params.pflags; |
4e59e288 GP |
1824 | int err; |
1825 | ||
8ff57c18 | 1826 | if (!(changes & BIT(flag))) |
4e59e288 GP |
1827 | return 0; |
1828 | ||
8ff57c18 | 1829 | err = mlx5e_priv_flags[flag].handler(netdev, enable); |
4e59e288 | 1830 | if (err) { |
8ff57c18 TT |
1831 | netdev_err(netdev, "%s private flag '%s' failed err %d\n", |
1832 | enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err); | |
4e59e288 GP |
1833 | return err; |
1834 | } | |
1835 | ||
6a9764ef | 1836 | MLX5E_SET_PFLAG(&priv->channels.params, flag, enable); |
4e59e288 GP |
1837 | return 0; |
1838 | } | |
1839 | ||
1840 | static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags) | |
1841 | { | |
1842 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
8ff57c18 | 1843 | enum mlx5e_priv_flag pflag; |
4e59e288 GP |
1844 | int err; |
1845 | ||
1846 | mutex_lock(&priv->state_lock); | |
2ccb0a79 | 1847 | |
8ff57c18 TT |
1848 | for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) { |
1849 | err = mlx5e_handle_pflag(netdev, pflags, pflag); | |
1850 | if (err) | |
1851 | break; | |
1852 | } | |
9bcc8606 | 1853 | |
4e59e288 | 1854 | mutex_unlock(&priv->state_lock); |
6c3a823e TT |
1855 | |
1856 | /* Need to fix some features.. */ | |
1857 | netdev_update_features(netdev); | |
1858 | ||
9bcc8606 | 1859 | return err; |
4e59e288 GP |
1860 | } |
1861 | ||
1862 | static u32 mlx5e_get_priv_flags(struct net_device *netdev) | |
1863 | { | |
1864 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1865 | ||
6a9764ef | 1866 | return priv->channels.params.pflags; |
4e59e288 GP |
1867 | } |
1868 | ||
3ffaabec OG |
1869 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1870 | struct ethtool_flash *flash) | |
1871 | { | |
1872 | struct mlx5_core_dev *mdev = priv->mdev; | |
1873 | struct net_device *dev = priv->netdev; | |
1874 | const struct firmware *fw; | |
1875 | int err; | |
1876 | ||
1877 | if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) | |
1878 | return -EOPNOTSUPP; | |
1879 | ||
1880 | err = request_firmware_direct(&fw, flash->data, &dev->dev); | |
1881 | if (err) | |
1882 | return err; | |
1883 | ||
1884 | dev_hold(dev); | |
1885 | rtnl_unlock(); | |
1886 | ||
1887 | err = mlx5_firmware_flash(mdev, fw); | |
1888 | release_firmware(fw); | |
1889 | ||
1890 | rtnl_lock(); | |
1891 | dev_put(dev); | |
1892 | return err; | |
1893 | } | |
1894 | ||
1895 | static int mlx5e_flash_device(struct net_device *dev, | |
1896 | struct ethtool_flash *flash) | |
1897 | { | |
1898 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1899 | ||
1900 | return mlx5e_ethtool_flash_device(priv, flash); | |
1901 | } | |
1902 | ||
f62b8bb8 AV |
1903 | const struct ethtool_ops mlx5e_ethtool_ops = { |
1904 | .get_drvinfo = mlx5e_get_drvinfo, | |
1905 | .get_link = ethtool_op_get_link, | |
1906 | .get_strings = mlx5e_get_strings, | |
1907 | .get_sset_count = mlx5e_get_sset_count, | |
1908 | .get_ethtool_stats = mlx5e_get_ethtool_stats, | |
1909 | .get_ringparam = mlx5e_get_ringparam, | |
1910 | .set_ringparam = mlx5e_set_ringparam, | |
1911 | .get_channels = mlx5e_get_channels, | |
1912 | .set_channels = mlx5e_set_channels, | |
1913 | .get_coalesce = mlx5e_get_coalesce, | |
1914 | .set_coalesce = mlx5e_set_coalesce, | |
665bc539 GP |
1915 | .get_link_ksettings = mlx5e_get_link_ksettings, |
1916 | .set_link_ksettings = mlx5e_set_link_ksettings, | |
2d75b2bc AS |
1917 | .get_rxfh_key_size = mlx5e_get_rxfh_key_size, |
1918 | .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size, | |
2be6967c SM |
1919 | .get_rxfh = mlx5e_get_rxfh, |
1920 | .set_rxfh = mlx5e_set_rxfh, | |
fe6d86b3 | 1921 | #ifdef CONFIG_MLX5_EN_RXNFC |
2d75b2bc | 1922 | .get_rxnfc = mlx5e_get_rxnfc, |
6dc6071c | 1923 | .set_rxnfc = mlx5e_set_rxnfc, |
fe6d86b3 | 1924 | #endif |
3ffaabec | 1925 | .flash_device = mlx5e_flash_device, |
58d52291 AS |
1926 | .get_tunable = mlx5e_get_tunable, |
1927 | .set_tunable = mlx5e_set_tunable, | |
3c2d18ef AS |
1928 | .get_pauseparam = mlx5e_get_pauseparam, |
1929 | .set_pauseparam = mlx5e_set_pauseparam, | |
ef9814de | 1930 | .get_ts_info = mlx5e_get_ts_info, |
da54d24e | 1931 | .set_phys_id = mlx5e_set_phys_id, |
928cfe87 TT |
1932 | .get_wol = mlx5e_get_wol, |
1933 | .set_wol = mlx5e_set_wol, | |
bb64143e GP |
1934 | .get_module_info = mlx5e_get_module_info, |
1935 | .get_module_eeprom = mlx5e_get_module_eeprom, | |
4e59e288 | 1936 | .get_priv_flags = mlx5e_get_priv_flags, |
d605d668 KH |
1937 | .set_priv_flags = mlx5e_set_priv_flags, |
1938 | .self_test = mlx5e_self_test, | |
79c48764 GP |
1939 | .get_msglevel = mlx5e_get_msglevel, |
1940 | .set_msglevel = mlx5e_set_msglevel, | |
6cfa9460 SA |
1941 | .get_fecparam = mlx5e_get_fecparam, |
1942 | .set_fecparam = mlx5e_set_fecparam, | |
f62b8bb8 | 1943 | }; |