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Merge tag 'x86-fpu-2020-06-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
2c81bfd5 34#include "en/port.h"
db05815b 35#include "en/xsk/umem.h"
6dbc80ca 36#include "lib/clock.h"
f62b8bb8 37
076b0936
ES		 38void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
39 struct ethtool_drvinfo *drvinfo)
f62b8bb8 40{
f62b8bb8
AV		 41 struct mlx5_core_dev *mdev = priv->mdev;
42
43 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
7913d205 44 strlcpy(drvinfo->version, DRIVER_VERSION,
f62b8bb8
AV		 45 sizeof(drvinfo->version));
46 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
84e11edb
IK		 47 "%d.%d.%04d (%.16s)",
48 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
49 mdev->board_id);
f72e6c3e 50 strlcpy(drvinfo->bus_info, dev_name(mdev->device),
f62b8bb8
AV		 51 sizeof(drvinfo->bus_info));
52}
53
076b0936
ES		 54static void mlx5e_get_drvinfo(struct net_device *dev,
55 struct ethtool_drvinfo *drvinfo)
56{
57 struct mlx5e_priv *priv = netdev_priv(dev);
58
59 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
60}
61
665bc539
GP		 62struct ptys2ethtool_config {
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
64 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8
AV		 65};
66
6a897372
AL		 67static
68struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
69static
70struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
665bc539 71
6a897372 72#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
665bc539
GP		 73 ({ \
74 struct ptys2ethtool_config *cfg; \
75 const unsigned int modes[] = { __VA_ARGS__ }; \
6a897372
AL		 76 unsigned int i, bit, idx; \
77 cfg = &ptys2##table##_ethtool_table[reg_]; \
665bc539
GP		 78 bitmap_zero(cfg->supported, \
79 __ETHTOOL_LINK_MODE_MASK_NBITS); \
80 bitmap_zero(cfg->advertised, \
81 __ETHTOOL_LINK_MODE_MASK_NBITS); \
82 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
6a897372
AL		 83 bit = modes[i] % 64; \
84 idx = modes[i] / 64; \
85 __set_bit(bit, &cfg->supported[idx]); \
86 __set_bit(bit, &cfg->advertised[idx]); \
665bc539
GP		 87 } \
88 })
89
90void mlx5e_build_ptys2ethtool_map(void)
91{
6a897372
AL		 92 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
93 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
665bc539 95 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
6a897372 96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
665bc539 97 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
6a897372 98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
665bc539 99 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
6a897372 100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
665bc539 101 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
6a897372 102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
665bc539 103 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
665bc539 105 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
6a897372 106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
665bc539 107 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
6a897372 108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
665bc539 109 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
6a897372 110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
665bc539 111 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
6a897372 112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
665bc539 113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
665bc539 115 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
665bc539 117 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
665bc539 119 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
6a897372 120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
665bc539 121 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
6a897372 122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
665bc539 123 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
6a897372 124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
665bc539 125 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
6a897372 126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
665bc539 127 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
6a897372 128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
665bc539 129 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
6a897372 130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
665bc539 131 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
6a897372 132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
665bc539 133 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
6a897372 134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
665bc539 135 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
6a897372 136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
665bc539 137 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
6a897372 138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
665bc539 139 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
6a897372 140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
665bc539 141 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
6a897372 142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
665bc539 143 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
6a897372
AL		 144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
145 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
146 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
147 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
149 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
151 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
152 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
153 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
155 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
156 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
159 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
160 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
161 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
164 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
166 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
168 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
170 ext,
171 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
173 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
174 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
175 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
179 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
181 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
184 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
185 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
186 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
190 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
191 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
192 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
196 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
197}
198
199static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
200 struct ptys2ethtool_config **arr,
201 u32 *size)
202{
203 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
204
205 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
206 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
207 ARRAY_SIZE(ptys2legacy_ethtool_table);
665bc539
GP		 208}
209
8ff57c18
TT		 210typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
211
212struct pflag_desc {
213 char name[ETH_GSTRING_LEN];
214 mlx5e_pflag_handler handler;
d2408205
KH		 215};
216
8ff57c18
TT		 217static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
218
076b0936 219int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
f62b8bb8 220{
f62b8bb8
AV		 221 switch (sset) {
222 case ETH_SS_STATS:
3460c184 223 return mlx5e_stats_total_num(priv);
4e59e288 224 case ETH_SS_PRIV_FLAGS:
8ff57c18 225 return MLX5E_NUM_PFLAGS;
d605d668
KH		 226 case ETH_SS_TEST:
227 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 228 /* fallthrough */
229 default:
230 return -EOPNOTSUPP;
231 }
232}
233
076b0936
ES		 234static int mlx5e_get_sset_count(struct net_device *dev, int sset)
235{
236 struct mlx5e_priv *priv = netdev_priv(dev);
237
238 return mlx5e_ethtool_get_sset_count(priv, sset);
239}
240
c045deef 241void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
f62b8bb8 242{
4e59e288 243 int i;
f62b8bb8
AV		 244
245 switch (stringset) {
246 case ETH_SS_PRIV_FLAGS:
8ff57c18
TT		 247 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
248 strcpy(data + i * ETH_GSTRING_LEN,
249 mlx5e_priv_flags[i].name);
f62b8bb8
AV		 250 break;
251
252 case ETH_SS_TEST:
d605d668
KH		 253 for (i = 0; i < mlx5e_self_test_num(priv); i++)
254 strcpy(data + i * ETH_GSTRING_LEN,
255 mlx5e_self_tests[i]);
f62b8bb8
AV		 256 break;
257
258 case ETH_SS_STATS:
3460c184 259 mlx5e_stats_fill_strings(priv, data);
f62b8bb8
AV		 260 break;
261 }
262}
263
c045deef 264static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
f62b8bb8
AV		 265{
266 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 267
268 mlx5e_ethtool_get_strings(priv, stringset, data);
269}
270
271void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
272 struct ethtool_stats *stats, u64 *data)
273{
3460c184 274 int idx = 0;
f62b8bb8 275
f62b8bb8 276 mutex_lock(&priv->state_lock);
3460c184 277 mlx5e_stats_update(priv);
f62b8bb8
AV		 278 mutex_unlock(&priv->state_lock);
279
3460c184 280 mlx5e_stats_fill(priv, data, idx);
f62b8bb8
AV		 281}
282
076b0936
ES		 283static void mlx5e_get_ethtool_stats(struct net_device *dev,
284 struct ethtool_stats *stats,
285 u64 *data)
286{
287 struct mlx5e_priv *priv = netdev_priv(dev);
288
289 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
290}
291
076b0936
ES		 292void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
293 struct ethtool_ringparam *param)
f62b8bb8 294{
73281b78 295 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
f62b8bb8 296 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
73281b78 297 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
6a9764ef 298 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 299}
300
076b0936
ES		 301static void mlx5e_get_ringparam(struct net_device *dev,
302 struct ethtool_ringparam *param)
f62b8bb8
AV		 303{
304 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 305
306 mlx5e_ethtool_get_ringparam(priv, param);
307}
308
309int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
310 struct ethtool_ringparam *param)
311{
546f18ed 312 struct mlx5e_channels new_channels = {};
f62b8bb8
AV		 313 u8 log_rq_size;
314 u8 log_sq_size;
315 int err = 0;
316
317 if (param->rx_jumbo_pending) {
076b0936 318 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
f62b8bb8
AV		 319 __func__);
320 return -EINVAL;
321 }
322 if (param->rx_mini_pending) {
076b0936 323 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
f62b8bb8
AV		 324 __func__);
325 return -EINVAL;
326 }
cc8e9ebf 327
73281b78 328 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
076b0936 329 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
f62b8bb8 330 __func__, param->rx_pending,
73281b78 331 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
fe4c988b
SM		 332 return -EINVAL;
333 }
334
f62b8bb8 335 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
076b0936 336 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
f62b8bb8
AV		 337 __func__, param->tx_pending,
338 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
339 return -EINVAL;
340 }
f62b8bb8 341
73281b78 342 log_rq_size = order_base_2(param->rx_pending);
f62b8bb8 343 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 344
73281b78 345 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
6a9764ef 346 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 347 return 0;
348
349 mutex_lock(&priv->state_lock);
98e81b0a 350
546f18ed 351 new_channels.params = priv->channels.params;
73281b78 352 new_channels.params.log_rq_mtu_frames = log_rq_size;
546f18ed 353 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 354
546f18ed
SM		 355 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
356 priv->channels.params = new_channels.params;
357 goto unlock;
358 }
98e81b0a 359
b9ab5d0e 360 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
98e81b0a 361
546f18ed 362unlock:
f62b8bb8
AV		 363 mutex_unlock(&priv->state_lock);
364
365 return err;
366}
367
076b0936
ES		 368static int mlx5e_set_ringparam(struct net_device *dev,
369 struct ethtool_ringparam *param)
f62b8bb8
AV		 370{
371 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 372
076b0936
ES		 373 return mlx5e_ethtool_set_ringparam(priv, param);
374}
375
376void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
377 struct ethtool_channels *ch)
378{
db05815b
MM		 379 mutex_lock(&priv->state_lock);
380
694826e3 381 ch->max_combined = priv->max_nch;
6a9764ef 382 ch->combined_count = priv->channels.params.num_channels;
db05815b
MM		 383 if (priv->xsk.refcnt) {
384 /* The upper half are XSK queues. */
385 ch->max_combined *= 2;
386 ch->combined_count *= 2;
387 }
388
389 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 390}
391
076b0936
ES		 392static void mlx5e_get_channels(struct net_device *dev,
393 struct ethtool_channels *ch)
f62b8bb8
AV		 394{
395 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 396
397 mlx5e_ethtool_get_channels(priv, ch);
398}
399
400int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
401 struct ethtool_channels *ch)
402{
db05815b 403 struct mlx5e_params *cur_params = &priv->channels.params;
f62b8bb8 404 unsigned int count = ch->combined_count;
55c2503d 405 struct mlx5e_channels new_channels = {};
45bf454a 406 bool arfs_enabled;
f62b8bb8
AV		 407 int err = 0;
408
409 if (!count) {
076b0936 410 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
f62b8bb8
AV		 411 __func__);
412 return -EINVAL;
413 }
f62b8bb8 414
db05815b 415 if (cur_params->num_channels == count)
f62b8bb8
AV		 416 return 0;
417
418 mutex_lock(&priv->state_lock);
98e81b0a 419
db05815b
MM		 420 /* Don't allow changing the number of channels if there is an active
421 * XSK, because the numeration of the XSK and regular RQs will change.
422 */
423 if (priv->xsk.refcnt) {
424 err = -EINVAL;
425 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
426 __func__);
427 goto out;
428 }
429
55c2503d
SM		 430 new_channels.params = priv->channels.params;
431 new_channels.params.num_channels = count;
55c2503d
SM		 432
433 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
db05815b 434 *cur_params = new_channels.params;
fe867cac 435 mlx5e_num_channels_changed(priv);
55c2503d
SM		 436 goto out;
437 }
438
076b0936 439 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
45bf454a
MG		 440 if (arfs_enabled)
441 mlx5e_arfs_disable(priv);
442
55c2503d 443 /* Switch to new channels, set new parameters and close old ones */
b9ab5d0e
MM		 444 err = mlx5e_safe_switch_channels(priv, &new_channels,
445 mlx5e_num_channels_changed_ctx, NULL);
45bf454a
MG		 446
447 if (arfs_enabled) {
877662e2
TT		 448 int err2 = mlx5e_arfs_enable(priv);
449
450 if (err2)
076b0936 451 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
877662e2 452 __func__, err2);
45bf454a 453 }
98e81b0a 454
45bf454a 455out:
f62b8bb8
AV		 456 mutex_unlock(&priv->state_lock);
457
458 return err;
459}
460
076b0936
ES		 461static int mlx5e_set_channels(struct net_device *dev,
462 struct ethtool_channels *ch)
f62b8bb8 463{
076b0936
ES		 464 struct mlx5e_priv *priv = netdev_priv(dev);
465
466 return mlx5e_ethtool_set_channels(priv, ch);
467}
f62b8bb8 468
076b0936
ES		 469int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
470 struct ethtool_coalesce *coal)
471{
8960b389 472 struct dim_cq_moder *rx_moder, *tx_moder;
cbce4f44 473
7524a5d8 474 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 475 return -EOPNOTSUPP;
7524a5d8 476
cbce4f44
TG		 477 rx_moder = &priv->channels.params.rx_cq_moderation;
478 coal->rx_coalesce_usecs = rx_moder->usec;
479 coal->rx_max_coalesced_frames = rx_moder->pkts;
480 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
481
482 tx_moder = &priv->channels.params.tx_cq_moderation;
483 coal->tx_coalesce_usecs = tx_moder->usec;
484 coal->tx_max_coalesced_frames = tx_moder->pkts;
485 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
f62b8bb8
AV		 486
487 return 0;
488}
489
076b0936
ES		 490static int mlx5e_get_coalesce(struct net_device *netdev,
491 struct ethtool_coalesce *coal)
492{
493 struct mlx5e_priv *priv = netdev_priv(netdev);
494
495 return mlx5e_ethtool_get_coalesce(priv, coal);
496}
497
b392a207
MS		 498#define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
499#define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
500
546f18ed
SM		 501static void
502mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 503{
f62b8bb8 504 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 505 int tc;
506 int i;
507
ff9c852f
SM		 508 for (i = 0; i < priv->channels.num; ++i) {
509 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 510
511 for (tc = 0; tc < c->num_tc; tc++) {
512 mlx5_core_modify_cq_moderation(mdev,
513 &c->sq[tc].cq.mcq,
514 coal->tx_coalesce_usecs,
515 coal->tx_max_coalesced_frames);
516 }
517
518 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
519 coal->rx_coalesce_usecs,
520 coal->rx_max_coalesced_frames);
521 }
546f18ed 522}
f62b8bb8 523
076b0936
ES		 524int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
525 struct ethtool_coalesce *coal)
546f18ed 526{
8960b389 527 struct dim_cq_moder *rx_moder, *tx_moder;
546f18ed
SM		 528 struct mlx5_core_dev *mdev = priv->mdev;
529 struct mlx5e_channels new_channels = {};
ebeaf084 530 bool reset_rx, reset_tx;
546f18ed 531 int err = 0;
cb3c7fd4 532
546f18ed
SM		 533 if (!MLX5_CAP_GEN(mdev, cq_moderation))
534 return -EOPNOTSUPP;
535
b392a207
MS		 536 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
537 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
538 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
539 __func__, MLX5E_MAX_COAL_TIME);
540 return -ERANGE;
541 }
542
543 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
544 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
545 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
546 __func__, MLX5E_MAX_COAL_FRAMES);
547 return -ERANGE;
548 }
549
546f18ed
SM		 550 mutex_lock(&priv->state_lock);
551 new_channels.params = priv->channels.params;
552
cbce4f44
TG		 553 rx_moder = &new_channels.params.rx_cq_moderation;
554 rx_moder->usec = coal->rx_coalesce_usecs;
555 rx_moder->pkts = coal->rx_max_coalesced_frames;
556 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
557
558 tx_moder = &new_channels.params.tx_cq_moderation;
559 tx_moder->usec = coal->tx_coalesce_usecs;
560 tx_moder->pkts = coal->tx_max_coalesced_frames;
561 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
546f18ed
SM		 562
563 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
564 priv->channels.params = new_channels.params;
565 goto out;
566 }
567 /* we are opened */
568
ebeaf084
TG		 569 reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled;
570 reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled;
cbce4f44 571
ebeaf084 572 if (!reset_rx && !reset_tx) {
546f18ed
SM		 573 mlx5e_set_priv_channels_coalesce(priv, coal);
574 priv->channels.params = new_channels.params;
575 goto out;
576 }
577
ebeaf084
TG		 578 if (reset_rx) {
579 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
580 MLX5E_PFLAG_RX_CQE_BASED_MODER);
581
582 mlx5e_reset_rx_moderation(&new_channels.params, mode);
583 }
584 if (reset_tx) {
585 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
586 MLX5E_PFLAG_TX_CQE_BASED_MODER);
587
588 mlx5e_reset_tx_moderation(&new_channels.params, mode);
589 }
590
b9ab5d0e 591 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
546f18ed
SM		 592
593out:
2fcb92fb 594 mutex_unlock(&priv->state_lock);
cb3c7fd4 595 return err;
f62b8bb8
AV		 596}
597
076b0936
ES		 598static int mlx5e_set_coalesce(struct net_device *netdev,
599 struct ethtool_coalesce *coal)
600{
601 struct mlx5e_priv *priv = netdev_priv(netdev);
602
603 return mlx5e_ethtool_set_coalesce(priv, coal);
604}
605
6a897372
AL		 606static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
607 unsigned long *supported_modes,
665bc539 608 u32 eth_proto_cap)
f62b8bb8 609{
7abc2110 610 unsigned long proto_cap = eth_proto_cap;
6a897372
AL		 611 struct ptys2ethtool_config *table;
612 u32 max_size;
665bc539 613 int proto;
f62b8bb8 614
6a897372
AL		 615 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
616 for_each_set_bit(proto, &proto_cap, max_size)
665bc539 617 bitmap_or(supported_modes, supported_modes,
6a897372 618 table[proto].supported,
665bc539 619 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 620}
621
dd1b9e09
AL		 622static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
623 u32 eth_proto_cap, bool ext)
f62b8bb8 624{
7abc2110 625 unsigned long proto_cap = eth_proto_cap;
6a897372
AL		 626 struct ptys2ethtool_config *table;
627 u32 max_size;
665bc539 628 int proto;
f62b8bb8 629
dd1b9e09
AL		 630 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
631 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
632 ARRAY_SIZE(ptys2legacy_ethtool_table);
633
6a897372 634 for_each_set_bit(proto, &proto_cap, max_size)
665bc539 635 bitmap_or(advertising_modes, advertising_modes,
6a897372 636 table[proto].advertised,
665bc539 637 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 638}
639
6cfa9460
SA		 640static const u32 pplm_fec_2_ethtool[] = {
641 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
642 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
643 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
b5ede32d
AL		 644 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
645 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
6cfa9460
SA		 646};
647
648static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
649{
650 int mode = 0;
651
652 if (!fec_mode)
653 return ETHTOOL_FEC_AUTO;
654
655 mode = find_first_bit(&fec_mode, size);
656
657 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
658 return pplm_fec_2_ethtool[mode];
659
660 return 0;
661}
662
2132b71f
AL		 663#define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
664 do { \
665 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
666 __set_bit(ethtool_fec, \
667 link_ksettings->link_modes.supported);\
668 } while (0)
669
670static const u32 pplm_fec_2_ethtool_linkmodes[] = {
671 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
672 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
673 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
b5ede32d
AL		 674 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
675 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2132b71f 676};
6cfa9460
SA		 677
678static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
679 struct ethtool_link_ksettings *link_ksettings)
680{
b623603b
AL		 681 unsigned long active_fec_long;
682 u32 active_fec;
6cfa9460
SA		 683 u32 bitn;
684 int err;
685
b623603b 686 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
6cfa9460
SA		 687 if (err)
688 return (err == -EOPNOTSUPP) ? 0 : err;
689
2132b71f
AL		 690 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
691 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
692 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
693 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
694 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
695 ETHTOOL_LINK_MODE_FEC_RS_BIT);
b5ede32d
AL		 696 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
697 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
6cfa9460 698
b623603b 699 active_fec_long = active_fec;
2132b71f
AL		 700 /* active fec is a bit set, find out which bit is set and
701 * advertise the corresponding ethtool bit
702 */
b623603b 703 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
2132b71f
AL		 704 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
705 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
706 link_ksettings->link_modes.advertising);
6cfa9460
SA		 707
708 return 0;
709}
710
46e9d0b6
EBE		 711static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
712 u32 eth_proto_cap,
24960574 713 u8 connector_type, bool ext)
f62b8bb8 714{
24960574 715 if ((!connector_type && !ext) || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
46e9d0b6
EBE		 716 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
717 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
718 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
719 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
720 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
721 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
722 ethtool_link_ksettings_add_link_mode(link_ksettings,
723 supported,
724 FIBRE);
725 ethtool_link_ksettings_add_link_mode(link_ksettings,
726 advertising,
727 FIBRE);
728 }
729
730 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
731 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
732 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
733 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
734 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
735 ethtool_link_ksettings_add_link_mode(link_ksettings,
736 supported,
737 Backplane);
738 ethtool_link_ksettings_add_link_mode(link_ksettings,
739 advertising,
740 Backplane);
741 }
742 return;
f62b8bb8
AV		 743 }
744
46e9d0b6
EBE		 745 switch (connector_type) {
746 case MLX5E_PORT_TP:
747 ethtool_link_ksettings_add_link_mode(link_ksettings,
748 supported, TP);
749 ethtool_link_ksettings_add_link_mode(link_ksettings,
750 advertising, TP);
751 break;
752 case MLX5E_PORT_AUI:
753 ethtool_link_ksettings_add_link_mode(link_ksettings,
754 supported, AUI);
755 ethtool_link_ksettings_add_link_mode(link_ksettings,
756 advertising, AUI);
757 break;
758 case MLX5E_PORT_BNC:
759 ethtool_link_ksettings_add_link_mode(link_ksettings,
760 supported, BNC);
761 ethtool_link_ksettings_add_link_mode(link_ksettings,
762 advertising, BNC);
763 break;
764 case MLX5E_PORT_MII:
765 ethtool_link_ksettings_add_link_mode(link_ksettings,
766 supported, MII);
767 ethtool_link_ksettings_add_link_mode(link_ksettings,
768 advertising, MII);
769 break;
770 case MLX5E_PORT_FIBRE:
771 ethtool_link_ksettings_add_link_mode(link_ksettings,
772 supported, FIBRE);
773 ethtool_link_ksettings_add_link_mode(link_ksettings,
774 advertising, FIBRE);
775 break;
776 case MLX5E_PORT_DA:
777 ethtool_link_ksettings_add_link_mode(link_ksettings,
778 supported, Backplane);
779 ethtool_link_ksettings_add_link_mode(link_ksettings,
780 advertising, Backplane);
781 break;
782 case MLX5E_PORT_NONE:
783 case MLX5E_PORT_OTHER:
784 default:
785 break;
f62b8bb8 786 }
f62b8bb8
AV		 787}
788
789static void get_speed_duplex(struct net_device *netdev,
4b95840a 790 u32 eth_proto_oper, bool force_legacy,
c268ca60 791 u16 data_rate_oper,
665bc539 792 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 793{
a08b4ed1 794 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8
AV		 795 u32 speed = SPEED_UNKNOWN;
796 u8 duplex = DUPLEX_UNKNOWN;
797
798 if (!netif_carrier_ok(netdev))
799 goto out;
800
4b95840a 801 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
2c81bfd5 802 if (!speed) {
c268ca60
MB		 803 if (data_rate_oper)
804 speed = 100 * data_rate_oper;
805 else
806 speed = SPEED_UNKNOWN;
2c81bfd5 807 goto out;
f62b8bb8 808 }
2c81bfd5
HN		 809
810 duplex = DUPLEX_FULL;
811
f62b8bb8 812out:
665bc539
GP		 813 link_ksettings->base.speed = speed;
814 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 815}
816
6a897372 817static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
665bc539 818 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 819{
665bc539 820 unsigned long *supported = link_ksettings->link_modes.supported;
6a897372 821 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
665bc539 822
665bc539 823 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
f62b8bb8
AV		 824}
825
dd1b9e09
AL		 826static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
827 struct ethtool_link_ksettings *link_ksettings,
828 bool ext)
f62b8bb8 829{
665bc539 830 unsigned long *advertising = link_ksettings->link_modes.advertising;
dd1b9e09 831 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
665bc539 832
e3c19503 833 if (rx_pause)
665bc539
GP		 834 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
835 if (tx_pause ^ rx_pause)
836 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 837}
838
5b4793f8
EBE		 839static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
840 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
841 [MLX5E_PORT_NONE] = PORT_NONE,
842 [MLX5E_PORT_TP] = PORT_TP,
843 [MLX5E_PORT_AUI] = PORT_AUI,
844 [MLX5E_PORT_BNC] = PORT_BNC,
845 [MLX5E_PORT_MII] = PORT_MII,
846 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
847 [MLX5E_PORT_DA] = PORT_DA,
848 [MLX5E_PORT_OTHER] = PORT_OTHER,
849 };
850
24960574 851static u8 get_connector_port(u32 eth_proto, u8 connector_type, bool ext)
f62b8bb8 852{
24960574 853 if ((connector_type || ext) && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
5b4793f8
EBE		 854 return ptys2connector_type[connector_type];
855
61bf2125
OG		 856 if (eth_proto &
857 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
858 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
859 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
860 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
861 return PORT_FIBRE;
f62b8bb8
AV		 862 }
863
61bf2125
OG		 864 if (eth_proto &
865 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
866 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
867 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
868 return PORT_DA;
f62b8bb8
AV		 869 }
870
61bf2125
OG		 871 if (eth_proto &
872 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
873 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
874 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
875 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
876 return PORT_NONE;
f62b8bb8
AV		 877 }
878
879 return PORT_OTHER;
880}
881
6a897372 882static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
665bc539 883 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 884{
665bc539 885 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
dd1b9e09 886 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
665bc539 887
dd1b9e09 888 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
f62b8bb8
AV		 889}
890
371289b6
OG		 891int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
892 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 893{
f62b8bb8 894 struct mlx5_core_dev *mdev = priv->mdev;
2f5438ca
MB		 895 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
896 u32 eth_proto_admin;
897 u8 an_disable_admin;
c268ca60 898 u16 data_rate_oper;
2f5438ca
MB		 899 u32 eth_proto_oper;
900 u32 eth_proto_cap;
901 u8 connector_type;
b383b544
GP		 902 u32 rx_pause = 0;
903 u32 tx_pause = 0;
f62b8bb8 904 u32 eth_proto_lp;
dd1b9e09 905 bool admin_ext;
2f5438ca 906 u8 an_status;
6a897372 907 bool ext;
f62b8bb8
AV		 908 int err;
909
a05bdefa 910 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8 911 if (err) {
371289b6 912 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
f62b8bb8 913 __func__, err);
6cfa9460 914 goto err_query_regs;
f62b8bb8 915 }
6a897372
AL		 916 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
917 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
918 eth_proto_capability);
919 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
920 eth_proto_admin);
dd1b9e09
AL		 921 /* Fields: eth_proto_admin and ext_eth_proto_admin are
922 * mutually exclusive. Hence try reading legacy advertising
923 * when extended advertising is zero.
4b95840a
AL		 924 * admin_ext indicates which proto_admin (ext vs. legacy)
925 * should be read and interpreted
dd1b9e09
AL		 926 */
927 admin_ext = ext;
928 if (ext && !eth_proto_admin) {
929 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
930 eth_proto_admin);
931 admin_ext = false;
932 }
933
4b95840a 934 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
6a897372
AL		 935 eth_proto_oper);
936 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
937 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
938 an_status = MLX5_GET(ptys_reg, out, an_status);
939 connector_type = MLX5_GET(ptys_reg, out, connector_type);
c268ca60 940 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
f62b8bb8 941
b383b544
GP		 942 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
943
665bc539
GP		 944 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
945 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 946
6a897372 947 get_supported(mdev, eth_proto_cap, link_ksettings);
dd1b9e09
AL		 948 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
949 admin_ext);
4b95840a 950 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
c268ca60 951 data_rate_oper, link_ksettings);
f62b8bb8
AV		 952
953 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
954
5b4793f8 955 link_ksettings->base.port = get_connector_port(eth_proto_oper,
24960574 956 connector_type, ext);
46e9d0b6 957 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
24960574 958 connector_type, ext);
6a897372 959 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
f62b8bb8 960
52244d96
GP		 961 if (an_status == MLX5_AN_COMPLETE)
962 ethtool_link_ksettings_add_link_mode(link_ksettings,
963 lp_advertising, Autoneg);
964
965 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
966 AUTONEG_ENABLE;
967 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
968 Autoneg);
6cfa9460 969
2eb1e425
SA		 970 err = get_fec_supported_advertised(mdev, link_ksettings);
971 if (err) {
371289b6 972 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
6cfa9460 973 __func__, err);
2eb1e425
SA		 974 err = 0; /* don't fail caps query because of FEC error */
975 }
6cfa9460 976
52244d96
GP		 977 if (!an_disable_admin)
978 ethtool_link_ksettings_add_link_mode(link_ksettings,
979 advertising, Autoneg);
980
6cfa9460 981err_query_regs:
f62b8bb8
AV		 982 return err;
983}
984
371289b6
OG		 985static int mlx5e_get_link_ksettings(struct net_device *netdev,
986 struct ethtool_link_ksettings *link_ksettings)
987{
988 struct mlx5e_priv *priv = netdev_priv(netdev);
989
990 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
991}
992
665bc539 993static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 994{
995 u32 i, ptys_modes = 0;
996
997 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
6a897372
AL		 998 if (*ptys2legacy_ethtool_table[i].advertised == 0)
999 continue;
1000 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
665bc539
GP		 1001 link_modes,
1002 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 1003 ptys_modes |= MLX5E_PROT_MASK(i);
1004 }
1005
1006 return ptys_modes;
1007}
1008
6a897372
AL		 1009static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1010{
1011 u32 i, ptys_modes = 0;
1012 unsigned long modes[2];
1013
1014 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1015 if (*ptys2ext_ethtool_table[i].advertised == 0)
1016 continue;
1017 memset(modes, 0, sizeof(modes));
1018 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1019 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1020
1021 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1022 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1023 ptys_modes |= MLX5E_PROT_MASK(i);
1024 }
1025 return ptys_modes;
1026}
1027
4b95840a
AL		 1028static bool ext_link_mode_requested(const unsigned long *adver)
1029{
1030#define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1031 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
926b37f7 1032 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
4b95840a
AL		 1033
1034 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1035 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1036}
1037
3d7cadae 1038static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported)
4b95840a
AL		 1039{
1040 bool ext_link_mode = ext_link_mode_requested(adver);
4b95840a 1041
3d7cadae 1042 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported;
4b95840a
AL		 1043}
1044
371289b6
OG		 1045int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1046 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 1047{
f62b8bb8 1048 struct mlx5_core_dev *mdev = priv->mdev;
bc4e12ff 1049 struct mlx5e_port_eth_proto eproto;
4b95840a 1050 const unsigned long *adver;
52244d96
GP		 1051 bool an_changes = false;
1052 u8 an_disable_admin;
6a897372 1053 bool ext_supported;
52244d96
GP		 1054 u8 an_disable_cap;
1055 bool an_disable;
f62b8bb8 1056 u32 link_modes;
52244d96 1057 u8 an_status;
4b95840a 1058 u8 autoneg;
f62b8bb8 1059 u32 speed;
4b95840a 1060 bool ext;
f62b8bb8
AV		 1061 int err;
1062
6a897372 1063 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
f62b8bb8 1064
4b95840a
AL		 1065 adver = link_ksettings->link_modes.advertising;
1066 autoneg = link_ksettings->base.autoneg;
1067 speed = link_ksettings->base.speed;
6a897372 1068
6a897372 1069 ext_supported = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
3d7cadae 1070 ext = ext_requested(autoneg, adver, ext_supported);
4b95840a
AL		 1071 if (!ext_supported && ext)
1072 return -EOPNOTSUPP;
f62b8bb8 1073
4b95840a 1074 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
6a897372 1075 mlx5e_ethtool2ptys_adver_link;
4b95840a 1076 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
f62b8bb8 1077 if (err) {
bc4e12ff 1078 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
f62b8bb8
AV		 1079 __func__, err);
1080 goto out;
1081 }
4b95840a
AL		 1082 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1083 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
f62b8bb8 1084
5faf5b70
MH		 1085 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1086 autoneg != AUTONEG_ENABLE) {
1087 netdev_err(priv->netdev, "%s: 56G link speed requires autoneg enabled\n",
1088 __func__);
1089 err = -EINVAL;
1090 goto out;
1091 }
1092
bc4e12ff 1093 link_modes = link_modes & eproto.cap;
f62b8bb8 1094 if (!link_modes) {
371289b6 1095 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
f62b8bb8
AV		 1096 __func__);
1097 err = -EINVAL;
1098 goto out;
1099 }
1100
bc4e12ff
AL		 1101 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1102 &an_disable_admin);
52244d96 1103
4b95840a 1104 an_disable = autoneg == AUTONEG_DISABLE;
52244d96
GP		 1105 an_changes = ((!an_disable && an_disable_admin) ||
1106 (an_disable && !an_disable_admin));
1107
bc4e12ff 1108 if (!an_changes && link_modes == eproto.admin)
f62b8bb8
AV		 1109 goto out;
1110
4b95840a 1111 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
667daeda 1112 mlx5_toggle_port_link(mdev);
f62b8bb8 1113
f62b8bb8
AV		 1114out:
1115 return err;
1116}
1117
371289b6
OG		 1118static int mlx5e_set_link_ksettings(struct net_device *netdev,
1119 const struct ethtool_link_ksettings *link_ksettings)
1120{
1121 struct mlx5e_priv *priv = netdev_priv(netdev);
1122
1123 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1124}
1125
a5355de8
OG		 1126u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1127{
bbeb53b8 1128 return sizeof(priv->rss_params.toeplitz_hash_key);
a5355de8
OG		 1129}
1130
2d75b2bc
AS		 1131static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1132{
1133 struct mlx5e_priv *priv = netdev_priv(netdev);
1134
a5355de8 1135 return mlx5e_ethtool_get_rxfh_key_size(priv);
2d75b2bc
AS		 1136}
1137
a5355de8 1138u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
2d75b2bc
AS		 1139{
1140 return MLX5E_INDIR_RQT_SIZE;
1141}
1142
a5355de8
OG		 1143static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1144{
1145 struct mlx5e_priv *priv = netdev_priv(netdev);
1146
1147 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1148}
1149
01013ad3
VB		 1150int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1151 u8 *hfunc)
2be6967c
SM		 1152{
1153 struct mlx5e_priv *priv = netdev_priv(netdev);
bbeb53b8 1154 struct mlx5e_rss_params *rss = &priv->rss_params;
2be6967c 1155
2d75b2bc 1156 if (indir)
bbeb53b8
AL		 1157 memcpy(indir, rss->indirection_rqt,
1158 sizeof(rss->indirection_rqt));
2d75b2bc
AS		 1159
1160 if (key)
bbeb53b8
AL		 1161 memcpy(key, rss->toeplitz_hash_key,
1162 sizeof(rss->toeplitz_hash_key));
2d75b2bc 1163
2be6967c 1164 if (hfunc)
bbeb53b8 1165 *hfunc = rss->hfunc;
2be6967c
SM		 1166
1167 return 0;
1168}
1169
01013ad3
VB		 1170int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1171 const u8 *key, const u8 hfunc)
2be6967c 1172{
98e81b0a 1173 struct mlx5e_priv *priv = netdev_priv(dev);
bbeb53b8 1174 struct mlx5e_rss_params *rss = &priv->rss_params;
bdfc028d 1175 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1176 bool hash_changed = false;
bdfc028d 1177 void *in;
2be6967c 1178
2d75b2bc
AS		 1179 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1180 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1181 (hfunc != ETH_RSS_HASH_TOP))
1182 return -EINVAL;
1183
1b9a07ee 1184 in = kvzalloc(inlen, GFP_KERNEL);
bdfc028d
TT		 1185 if (!in)
1186 return -ENOMEM;
1187
2be6967c
SM		 1188 mutex_lock(&priv->state_lock);
1189
bbeb53b8
AL		 1190 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1191 rss->hfunc = hfunc;
1d3398fa
GP		 1192 hash_changed = true;
1193 }
1194
a5f97fee 1195 if (indir) {
bbeb53b8
AL		 1196 memcpy(rss->indirection_rqt, indir,
1197 sizeof(rss->indirection_rqt));
a5f97fee
SM		 1198
1199 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1200 u32 rqtn = priv->indir_rqt.rqtn;
1201 struct mlx5e_redirect_rqt_param rrp = {
1202 .is_rss = true,
e270e966
AM		 1203 {
1204 .rss = {
bbeb53b8 1205 .hfunc = rss->hfunc,
e270e966
AM		 1206 .channels = &priv->channels,
1207 },
1208 },
a5f97fee
SM		 1209 };
1210
1211 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1212 }
1213 }
1214
1d3398fa 1215 if (key) {
bbeb53b8
AL		 1216 memcpy(rss->toeplitz_hash_key, key,
1217 sizeof(rss->toeplitz_hash_key));
1218 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1219 }
2d75b2bc 1220
1d3398fa
GP		 1221 if (hash_changed)
1222 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1223
2be6967c
SM		 1224 mutex_unlock(&priv->state_lock);
1225
bdfc028d
TT		 1226 kvfree(in);
1227
1228 return 0;
2be6967c
SM		 1229}
1230
2afa609f
IK		 1231#define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1232#define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1233#define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1234#define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1235#define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1236 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1237 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1238
1239static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1240 u16 *pfc_prevention_tout)
1241{
1242 struct mlx5e_priv *priv = netdev_priv(netdev);
1243 struct mlx5_core_dev *mdev = priv->mdev;
1244
1245 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1246 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1247 return -EOPNOTSUPP;
1248
1249 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1250}
1251
1252static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1253 u16 pfc_preven)
1254{
1255 struct mlx5e_priv *priv = netdev_priv(netdev);
1256 struct mlx5_core_dev *mdev = priv->mdev;
1257 u16 critical_tout;
1258 u16 minor;
1259
1260 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1261 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1262 return -EOPNOTSUPP;
1263
1264 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1265 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1266 pfc_preven;
1267
1268 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1269 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1270 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1271 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1272 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1273 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1274 return -EINVAL;
1275 }
1276
1277 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1278 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1279 minor);
1280}
1281
58d52291
AS		 1282static int mlx5e_get_tunable(struct net_device *dev,
1283 const struct ethtool_tunable *tuna,
1284 void *data)
1285{
c4554fbc 1286 int err;
58d52291
AS		 1287
1288 switch (tuna->id) {
2afa609f
IK		 1289 case ETHTOOL_PFC_PREVENTION_TOUT:
1290 err = mlx5e_get_pfc_prevention_tout(dev, data);
1291 break;
58d52291
AS		 1292 default:
1293 err = -EINVAL;
1294 break;
1295 }
1296
1297 return err;
1298}
1299
1300static int mlx5e_set_tunable(struct net_device *dev,
1301 const struct ethtool_tunable *tuna,
1302 const void *data)
1303{
1304 struct mlx5e_priv *priv = netdev_priv(dev);
c4554fbc 1305 int err;
546f18ed
SM		 1306
1307 mutex_lock(&priv->state_lock);
58d52291
AS		 1308
1309 switch (tuna->id) {
2afa609f
IK		 1310 case ETHTOOL_PFC_PREVENTION_TOUT:
1311 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
58d52291
AS		 1312 break;
1313 default:
1314 err = -EINVAL;
1315 break;
1316 }
1317
546f18ed 1318 mutex_unlock(&priv->state_lock);
58d52291
AS		 1319 return err;
1320}
1321
371289b6
OG		 1322void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1323 struct ethtool_pauseparam *pauseparam)
3c2d18ef 1324{
3c2d18ef
AS		 1325 struct mlx5_core_dev *mdev = priv->mdev;
1326 int err;
1327
1328 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1329 &pauseparam->tx_pause);
1330 if (err) {
371289b6 1331 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
3c2d18ef
AS		 1332 __func__, err);
1333 }
1334}
1335
371289b6
OG		 1336static void mlx5e_get_pauseparam(struct net_device *netdev,
1337 struct ethtool_pauseparam *pauseparam)
1338{
1339 struct mlx5e_priv *priv = netdev_priv(netdev);
1340
1341 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1342}
1343
1344int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1345 struct ethtool_pauseparam *pauseparam)
3c2d18ef 1346{
3c2d18ef
AS		 1347 struct mlx5_core_dev *mdev = priv->mdev;
1348 int err;
1349
466df6eb
HN		 1350 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1351 return -EOPNOTSUPP;
1352
3c2d18ef
AS		 1353 if (pauseparam->autoneg)
1354 return -EINVAL;
1355
1356 err = mlx5_set_port_pause(mdev,
1357 pauseparam->rx_pause ? 1 : 0,
1358 pauseparam->tx_pause ? 1 : 0);
1359 if (err) {
371289b6 1360 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
3c2d18ef
AS		 1361 __func__, err);
1362 }
1363
1364 return err;
1365}
1366
371289b6
OG		 1367static int mlx5e_set_pauseparam(struct net_device *netdev,
1368 struct ethtool_pauseparam *pauseparam)
1369{
1370 struct mlx5e_priv *priv = netdev_priv(netdev);
1371
1372 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1373}
1374
3844b07e
FD		 1375int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1376 struct ethtool_ts_info *info)
ef9814de 1377{
7c39afb3 1378 struct mlx5_core_dev *mdev = priv->mdev;
ef9814de 1379
6dbc80ca 1380 info->phc_index = mlx5_clock_get_ptp_index(mdev);
ef9814de 1381
6dbc80ca
MS		 1382 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1383 info->phc_index == -1)
ef9814de
EBE		 1384 return 0;
1385
47654204
AH		 1386 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1387 SOF_TIMESTAMPING_RX_HARDWARE |
1388 SOF_TIMESTAMPING_RAW_HARDWARE;
ef9814de 1389
f0b38117
MD		 1390 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1391 BIT(HWTSTAMP_TX_ON);
ef9814de 1392
f0b38117
MD		 1393 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1394 BIT(HWTSTAMP_FILTER_ALL);
ef9814de
EBE		 1395
1396 return 0;
1397}
1398
3844b07e
FD		 1399static int mlx5e_get_ts_info(struct net_device *dev,
1400 struct ethtool_ts_info *info)
1401{
1402 struct mlx5e_priv *priv = netdev_priv(dev);
1403
1404 return mlx5e_ethtool_get_ts_info(priv, info);
1405}
1406
928cfe87
TT		 1407static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1408{
1409 __u32 ret = 0;
1410
1411 if (MLX5_CAP_GEN(mdev, wol_g))
1412 ret |= WAKE_MAGIC;
1413
1414 if (MLX5_CAP_GEN(mdev, wol_s))
1415 ret |= WAKE_MAGICSECURE;
1416
1417 if (MLX5_CAP_GEN(mdev, wol_a))
1418 ret |= WAKE_ARP;
1419
1420 if (MLX5_CAP_GEN(mdev, wol_b))
1421 ret |= WAKE_BCAST;
1422
1423 if (MLX5_CAP_GEN(mdev, wol_m))
1424 ret |= WAKE_MCAST;
1425
1426 if (MLX5_CAP_GEN(mdev, wol_u))
1427 ret |= WAKE_UCAST;
1428
1429 if (MLX5_CAP_GEN(mdev, wol_p))
1430 ret |= WAKE_PHY;
1431
1432 return ret;
1433}
1434
d5e1c0ef 1435static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
928cfe87
TT		 1436{
1437 __u32 ret = 0;
1438
1439 if (mode & MLX5_WOL_MAGIC)
1440 ret |= WAKE_MAGIC;
1441
1442 if (mode & MLX5_WOL_SECURED_MAGIC)
1443 ret |= WAKE_MAGICSECURE;
1444
1445 if (mode & MLX5_WOL_ARP)
1446 ret |= WAKE_ARP;
1447
1448 if (mode & MLX5_WOL_BROADCAST)
1449 ret |= WAKE_BCAST;
1450
1451 if (mode & MLX5_WOL_MULTICAST)
1452 ret |= WAKE_MCAST;
1453
1454 if (mode & MLX5_WOL_UNICAST)
1455 ret |= WAKE_UCAST;
1456
1457 if (mode & MLX5_WOL_PHY_ACTIVITY)
1458 ret |= WAKE_PHY;
1459
1460 return ret;
1461}
1462
d5e1c0ef 1463static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
928cfe87
TT		 1464{
1465 u8 ret = 0;
1466
1467 if (mode & WAKE_MAGIC)
1468 ret |= MLX5_WOL_MAGIC;
1469
1470 if (mode & WAKE_MAGICSECURE)
1471 ret |= MLX5_WOL_SECURED_MAGIC;
1472
1473 if (mode & WAKE_ARP)
1474 ret |= MLX5_WOL_ARP;
1475
1476 if (mode & WAKE_BCAST)
1477 ret |= MLX5_WOL_BROADCAST;
1478
1479 if (mode & WAKE_MCAST)
1480 ret |= MLX5_WOL_MULTICAST;
1481
1482 if (mode & WAKE_UCAST)
1483 ret |= MLX5_WOL_UNICAST;
1484
1485 if (mode & WAKE_PHY)
1486 ret |= MLX5_WOL_PHY_ACTIVITY;
1487
1488 return ret;
1489}
1490
1491static void mlx5e_get_wol(struct net_device *netdev,
1492 struct ethtool_wolinfo *wol)
1493{
1494 struct mlx5e_priv *priv = netdev_priv(netdev);
1495 struct mlx5_core_dev *mdev = priv->mdev;
1496 u8 mlx5_wol_mode;
1497 int err;
1498
1499 memset(wol, 0, sizeof(*wol));
1500
1501 wol->supported = mlx5e_get_wol_supported(mdev);
1502 if (!wol->supported)
1503 return;
1504
1505 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1506 if (err)
1507 return;
1508
d5e1c0ef 1509 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
928cfe87
TT		 1510}
1511
1512static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1513{
1514 struct mlx5e_priv *priv = netdev_priv(netdev);
1515 struct mlx5_core_dev *mdev = priv->mdev;
1516 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1517 u32 mlx5_wol_mode;
1518
1519 if (!wol_supported)
9eb78923 1520 return -EOPNOTSUPP;
928cfe87
TT		 1521
1522 if (wol->wolopts & ~wol_supported)
1523 return -EINVAL;
1524
d5e1c0ef 1525 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
928cfe87
TT		 1526
1527 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1528}
1529
6cfa9460
SA		 1530static int mlx5e_get_fecparam(struct net_device *netdev,
1531 struct ethtool_fecparam *fecparam)
1532{
1533 struct mlx5e_priv *priv = netdev_priv(netdev);
1534 struct mlx5_core_dev *mdev = priv->mdev;
b623603b
AL		 1535 u16 fec_configured;
1536 u32 fec_active;
6cfa9460
SA		 1537 int err;
1538
1539 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1540
1541 if (err)
1542 return err;
1543
b623603b
AL		 1544 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1545 sizeof(unsigned long) * BITS_PER_BYTE);
6cfa9460
SA		 1546
1547 if (!fecparam->active_fec)
1548 return -EOPNOTSUPP;
1549
b623603b
AL		 1550 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1551 sizeof(unsigned long) * BITS_PER_BYTE);
6cfa9460
SA		 1552
1553 return 0;
1554}
1555
1556static int mlx5e_set_fecparam(struct net_device *netdev,
1557 struct ethtool_fecparam *fecparam)
1558{
1559 struct mlx5e_priv *priv = netdev_priv(netdev);
1560 struct mlx5_core_dev *mdev = priv->mdev;
b5ede32d 1561 u16 fec_policy = 0;
6cfa9460
SA		 1562 int mode;
1563 int err;
1564
4bd9d507 1565 if (bitmap_weight((unsigned long *)&fecparam->fec,
b5ede32d 1566 ETHTOOL_FEC_LLRS_BIT + 1) > 1)
4bd9d507
AL		 1567 return -EOPNOTSUPP;
1568
6cfa9460
SA		 1569 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1570 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1571 continue;
1572 fec_policy |= (1 << mode);
1573 break;
1574 }
1575
1576 err = mlx5e_set_fec_mode(mdev, fec_policy);
1577
1578 if (err)
1579 return err;
1580
1581 mlx5_toggle_port_link(mdev);
1582
1583 return 0;
1584}
1585
79c48764
GP		 1586static u32 mlx5e_get_msglevel(struct net_device *dev)
1587{
1588 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1589}
1590
1591static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1592{
1593 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1594}
1595
da54d24e
GP		 1596static int mlx5e_set_phys_id(struct net_device *dev,
1597 enum ethtool_phys_id_state state)
1598{
1599 struct mlx5e_priv *priv = netdev_priv(dev);
1600 struct mlx5_core_dev *mdev = priv->mdev;
1601 u16 beacon_duration;
1602
1603 if (!MLX5_CAP_GEN(mdev, beacon_led))
1604 return -EOPNOTSUPP;
1605
1606 switch (state) {
1607 case ETHTOOL_ID_ACTIVE:
1608 beacon_duration = MLX5_BEACON_DURATION_INF;
1609 break;
1610 case ETHTOOL_ID_INACTIVE:
1611 beacon_duration = MLX5_BEACON_DURATION_OFF;
1612 break;
1613 default:
1614 return -EOPNOTSUPP;
1615 }
1616
1617 return mlx5_set_port_beacon(mdev, beacon_duration);
1618}
1619
bb64143e
GP		 1620static int mlx5e_get_module_info(struct net_device *netdev,
1621 struct ethtool_modinfo *modinfo)
1622{
1623 struct mlx5e_priv *priv = netdev_priv(netdev);
1624 struct mlx5_core_dev *dev = priv->mdev;
1625 int size_read = 0;
a708fb7b 1626 u8 data[4] = {0};
bb64143e
GP		 1627
1628 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1629 if (size_read < 2)
1630 return -EIO;
1631
1632 /* data[0] = identifier byte */
1633 switch (data[0]) {
1634 case MLX5_MODULE_ID_QSFP:
1635 modinfo->type = ETH_MODULE_SFF_8436;
a708fb7b 1636 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
bb64143e
GP		 1637 break;
1638 case MLX5_MODULE_ID_QSFP_PLUS:
1639 case MLX5_MODULE_ID_QSFP28:
1640 /* data[1] = revision id */
1641 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1642 modinfo->type = ETH_MODULE_SFF_8636;
a708fb7b 1643 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
bb64143e
GP		 1644 } else {
1645 modinfo->type = ETH_MODULE_SFF_8436;
a708fb7b 1646 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
bb64143e
GP		 1647 }
1648 break;
1649 case MLX5_MODULE_ID_SFP:
1650 modinfo->type = ETH_MODULE_SFF_8472;
c431f859 1651 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
bb64143e
GP		 1652 break;
1653 default:
1654 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1655 __func__, data[0]);
1656 return -EINVAL;
1657 }
1658
1659 return 0;
1660}
1661
1662static int mlx5e_get_module_eeprom(struct net_device *netdev,
1663 struct ethtool_eeprom *ee,
1664 u8 *data)
1665{
1666 struct mlx5e_priv *priv = netdev_priv(netdev);
1667 struct mlx5_core_dev *mdev = priv->mdev;
1668 int offset = ee->offset;
1669 int size_read;
1670 int i = 0;
1671
1672 if (!ee->len)
1673 return -EINVAL;
1674
1675 memset(data, 0, ee->len);
1676
1677 while (i < ee->len) {
1678 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1679 data + i);
1680
1681 if (!size_read)
1682 /* Done reading */
1683 return 0;
1684
1685 if (size_read < 0) {
1686 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1687 __func__, size_read);
1688 return 0;
1689 }
1690
1691 i += size_read;
1692 offset += size_read;
1693 }
1694
1695 return 0;
1696}
1697
f43d48d1
EBE		 1698int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1699 struct ethtool_flash *flash)
1700{
1701 struct mlx5_core_dev *mdev = priv->mdev;
1702 struct net_device *dev = priv->netdev;
1703 const struct firmware *fw;
1704 int err;
1705
1706 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1707 return -EOPNOTSUPP;
1708
1709 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1710 if (err)
1711 return err;
1712
1713 dev_hold(dev);
1714 rtnl_unlock();
1715
1716 err = mlx5_firmware_flash(mdev, fw, NULL);
1717 release_firmware(fw);
1718
1719 rtnl_lock();
1720 dev_put(dev);
1721 return err;
1722}
1723
1724static int mlx5e_flash_device(struct net_device *dev,
1725 struct ethtool_flash *flash)
1726{
1727 struct mlx5e_priv *priv = netdev_priv(dev);
1728
1729 return mlx5e_ethtool_flash_device(priv, flash);
1730}
1731
0088cbbc
TG		 1732static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1733 bool is_rx_cq)
4e59e288 1734{
9908aa29
TT		 1735 struct mlx5e_priv *priv = netdev_priv(netdev);
1736 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1737 struct mlx5e_channels new_channels = {};
0088cbbc
TG		 1738 bool mode_changed;
1739 u8 cq_period_mode, current_cq_period_mode;
9908aa29 1740
0088cbbc 1741 cq_period_mode = enable ?
9908aa29
TT		 1742 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1743 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
0088cbbc
TG		 1744 current_cq_period_mode = is_rx_cq ?
1745 priv->channels.params.rx_cq_moderation.cq_period_mode :
1746 priv->channels.params.tx_cq_moderation.cq_period_mode;
1747 mode_changed = cq_period_mode != current_cq_period_mode;
9908aa29 1748
0088cbbc 1749 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
9908aa29 1750 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1751 return -EOPNOTSUPP;
9908aa29 1752
0088cbbc 1753 if (!mode_changed)
9908aa29
TT		 1754 return 0;
1755
be7e87f9 1756 new_channels.params = priv->channels.params;
0088cbbc
TG		 1757 if (is_rx_cq)
1758 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1759 else
1760 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
9908aa29 1761
be7e87f9
SM		 1762 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1763 priv->channels.params = new_channels.params;
1764 return 0;
1765 }
1766
b9ab5d0e 1767 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
be7e87f9 1768}
9908aa29 1769
0088cbbc
TG		 1770static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1771{
1772 return set_pflag_cqe_based_moder(netdev, enable, false);
1773}
1774
1775static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1776{
1777 return set_pflag_cqe_based_moder(netdev, enable, true);
1778}
1779
be7e87f9
SM		 1780int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1781{
1782 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1783 struct mlx5e_channels new_channels = {};
1784 int err = 0;
1785
1786 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1787 return new_val ? -EOPNOTSUPP : 0;
1788
1789 if (curr_val == new_val)
1790 return 0;
1791
1792 new_channels.params = priv->channels.params;
1793 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1794
be7e87f9
SM		 1795 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1796 priv->channels.params = new_channels.params;
1797 return 0;
1798 }
1799
b9ab5d0e 1800 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
be7e87f9
SM		 1801 if (err)
1802 return err;
1803
696a97cf
EE		 1804 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1805 MLX5E_GET_PFLAG(&priv->channels.params,
1806 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1807
be7e87f9 1808 return 0;
4e59e288
GP		 1809}
1810
9bcc8606
SD		 1811static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1812 bool enable)
1813{
1814 struct mlx5e_priv *priv = netdev_priv(netdev);
1815 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1816
1817 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1818 return -EOPNOTSUPP;
9bcc8606 1819
7c39afb3 1820 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
9bcc8606
SD		 1821 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1822 return -EINVAL;
1823 }
1824
5eb0249b 1825 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1826 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1827
5eb0249b 1828 return 0;
9bcc8606
SD		 1829}
1830
2ccb0a79
TT		 1831static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1832{
1833 struct mlx5e_priv *priv = netdev_priv(netdev);
1834 struct mlx5_core_dev *mdev = priv->mdev;
1835 struct mlx5e_channels new_channels = {};
2ccb0a79
TT		 1836
1837 if (enable) {
1838 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1839 return -EOPNOTSUPP;
1840 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1841 return -EINVAL;
6c3a823e
TT		 1842 } else if (priv->channels.params.lro_en) {
1843 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1844 return -EINVAL;
2ccb0a79
TT		 1845 }
1846
1847 new_channels.params = priv->channels.params;
1848
1849 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1850 mlx5e_set_rq_type(mdev, &new_channels.params);
1851
1852 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1853 priv->channels.params = new_channels.params;
1854 return 0;
1855 }
1856
b9ab5d0e 1857 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
2ccb0a79
TT		 1858}
1859
b856df28
OG		 1860static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1861{
1862 struct mlx5e_priv *priv = netdev_priv(netdev);
1863 struct mlx5e_channels *channels = &priv->channels;
1864 struct mlx5e_channel *c;
1865 int i;
1866
5d0bb3ba
SM		 1867 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1868 priv->channels.params.xdp_prog)
b856df28
OG		 1869 return 0;
1870
1871 for (i = 0; i < channels->num; i++) {
1872 c = channels->c[i];
1873 if (enable)
1874 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1875 else
1876 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1877 }
1878
1879 return 0;
1880}
1881
6277053a
TT		 1882static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1883{
1884 struct mlx5e_priv *priv = netdev_priv(netdev);
1885 struct mlx5_core_dev *mdev = priv->mdev;
1886 struct mlx5e_channels new_channels = {};
1887 int err;
1888
1889 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1890 return -EOPNOTSUPP;
1891
1892 new_channels.params = priv->channels.params;
1893
1894 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1895
1896 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1897 priv->channels.params = new_channels.params;
1898 return 0;
1899 }
1900
b9ab5d0e 1901 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
877662e2 1902 return err;
6277053a
TT		 1903}
1904
8ff57c18
TT		 1905static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1906 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1907 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1908 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1909 { "rx_striding_rq", set_pflag_rx_striding_rq },
1910 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
6277053a 1911 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
8ff57c18
TT		 1912};
1913
4e59e288
GP		 1914static int mlx5e_handle_pflag(struct net_device *netdev,
1915 u32 wanted_flags,
8ff57c18 1916 enum mlx5e_priv_flag flag)
4e59e288
GP		 1917{
1918 struct mlx5e_priv *priv = netdev_priv(netdev);
8ff57c18 1919 bool enable = !!(wanted_flags & BIT(flag));
6a9764ef 1920 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1921 int err;
1922
8ff57c18 1923 if (!(changes & BIT(flag)))
4e59e288
GP		 1924 return 0;
1925
8ff57c18 1926 err = mlx5e_priv_flags[flag].handler(netdev, enable);
4e59e288 1927 if (err) {
8ff57c18
TT		 1928 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1929 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
4e59e288
GP		 1930 return err;
1931 }
1932
6a9764ef 1933 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1934 return 0;
1935}
1936
1937static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1938{
1939 struct mlx5e_priv *priv = netdev_priv(netdev);
8ff57c18 1940 enum mlx5e_priv_flag pflag;
4e59e288
GP		 1941 int err;
1942
1943 mutex_lock(&priv->state_lock);
2ccb0a79 1944
8ff57c18
TT		 1945 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1946 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1947 if (err)
1948 break;
1949 }
9bcc8606 1950
4e59e288 1951 mutex_unlock(&priv->state_lock);
6c3a823e
TT		 1952
1953 /* Need to fix some features.. */
1954 netdev_update_features(netdev);
1955
9bcc8606 1956 return err;
4e59e288
GP		 1957}
1958
1959static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1960{
1961 struct mlx5e_priv *priv = netdev_priv(netdev);
1962
6a9764ef 1963 return priv->channels.params.pflags;
4e59e288
GP		 1964}
1965
b63293e7
VB		 1966int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1967 u32 *rule_locs)
8f0916c6
SM		 1968{
1969 struct mlx5e_priv *priv = netdev_priv(dev);
1970
79ce39be
SM		 1971 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
1972 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
1973 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
1974 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
1975 */
1976 if (info->cmd == ETHTOOL_GRXRINGS) {
1977 info->data = priv->channels.params.num_channels;
1978 return 0;
1979 }
1980
1981 return mlx5e_ethtool_get_rxnfc(dev, info, rule_locs);
1982}
1983
b63293e7 1984int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
79ce39be
SM		 1985{
1986 return mlx5e_ethtool_set_rxnfc(dev, cmd);
8f0916c6 1987}
8f0916c6 1988
f62b8bb8 1989const struct ethtool_ops mlx5e_ethtool_ops = {
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JK		 1990 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1991 ETHTOOL_COALESCE_MAX_FRAMES |
1992 ETHTOOL_COALESCE_USE_ADAPTIVE,
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AV		 1993 .get_drvinfo = mlx5e_get_drvinfo,
1994 .get_link = ethtool_op_get_link,
1995 .get_strings = mlx5e_get_strings,
1996 .get_sset_count = mlx5e_get_sset_count,
1997 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1998 .get_ringparam = mlx5e_get_ringparam,
1999 .set_ringparam = mlx5e_set_ringparam,
2000 .get_channels = mlx5e_get_channels,
2001 .set_channels = mlx5e_set_channels,
2002 .get_coalesce = mlx5e_get_coalesce,
2003 .set_coalesce = mlx5e_set_coalesce,
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GP		 2004 .get_link_ksettings = mlx5e_get_link_ksettings,
2005 .set_link_ksettings = mlx5e_set_link_ksettings,
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AS		 2006 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
2007 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
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SM		 2008 .get_rxfh = mlx5e_get_rxfh,
2009 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 2010 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 2011 .set_rxnfc = mlx5e_set_rxnfc,
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AS		 2012 .get_tunable = mlx5e_get_tunable,
2013 .set_tunable = mlx5e_set_tunable,
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AS		 2014 .get_pauseparam = mlx5e_get_pauseparam,
2015 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 2016 .get_ts_info = mlx5e_get_ts_info,
da54d24e 2017 .set_phys_id = mlx5e_set_phys_id,
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TT		 2018 .get_wol = mlx5e_get_wol,
2019 .set_wol = mlx5e_set_wol,
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GP		 2020 .get_module_info = mlx5e_get_module_info,
2021 .get_module_eeprom = mlx5e_get_module_eeprom,
f43d48d1 2022 .flash_device = mlx5e_flash_device,
4e59e288 2023 .get_priv_flags = mlx5e_get_priv_flags,
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KH		 2024 .set_priv_flags = mlx5e_set_priv_flags,
2025 .self_test = mlx5e_self_test,
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GP		 2026 .get_msglevel = mlx5e_get_msglevel,
2027 .set_msglevel = mlx5e_set_msglevel,
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SA		 2028 .get_fecparam = mlx5e_get_fecparam,
2029 .set_fecparam = mlx5e_set_fecparam,
f62b8bb8 2030};
A mirror of Linus' kernel repository