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f62b8bb8 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include "en.h" | |
2c81bfd5 | 34 | #include "en/port.h" |
6dbc80ca | 35 | #include "lib/clock.h" |
f62b8bb8 | 36 | |
076b0936 ES |
37 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, |
38 | struct ethtool_drvinfo *drvinfo) | |
f62b8bb8 | 39 | { |
f62b8bb8 AV |
40 | struct mlx5_core_dev *mdev = priv->mdev; |
41 | ||
42 | strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver)); | |
7913d205 | 43 | strlcpy(drvinfo->version, DRIVER_VERSION, |
f62b8bb8 AV |
44 | sizeof(drvinfo->version)); |
45 | snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), | |
84e11edb IK |
46 | "%d.%d.%04d (%.16s)", |
47 | fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev), | |
48 | mdev->board_id); | |
f62b8bb8 AV |
49 | strlcpy(drvinfo->bus_info, pci_name(mdev->pdev), |
50 | sizeof(drvinfo->bus_info)); | |
51 | } | |
52 | ||
076b0936 ES |
53 | static void mlx5e_get_drvinfo(struct net_device *dev, |
54 | struct ethtool_drvinfo *drvinfo) | |
55 | { | |
56 | struct mlx5e_priv *priv = netdev_priv(dev); | |
57 | ||
58 | mlx5e_ethtool_get_drvinfo(priv, drvinfo); | |
59 | } | |
60 | ||
665bc539 GP |
61 | struct ptys2ethtool_config { |
62 | __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); | |
63 | __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); | |
f62b8bb8 AV |
64 | }; |
65 | ||
665bc539 GP |
66 | static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER]; |
67 | ||
2c81bfd5 | 68 | #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, ...) \ |
665bc539 GP |
69 | ({ \ |
70 | struct ptys2ethtool_config *cfg; \ | |
71 | const unsigned int modes[] = { __VA_ARGS__ }; \ | |
72 | unsigned int i; \ | |
73 | cfg = &ptys2ethtool_table[reg_]; \ | |
665bc539 GP |
74 | bitmap_zero(cfg->supported, \ |
75 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
76 | bitmap_zero(cfg->advertised, \ | |
77 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
78 | for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ | |
79 | __set_bit(modes[i], cfg->supported); \ | |
80 | __set_bit(modes[i], cfg->advertised); \ | |
81 | } \ | |
82 | }) | |
83 | ||
84 | void mlx5e_build_ptys2ethtool_map(void) | |
85 | { | |
2c81bfd5 | 86 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, |
665bc539 | 87 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); |
2c81bfd5 | 88 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, |
665bc539 | 89 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); |
2c81bfd5 | 90 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, |
665bc539 | 91 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); |
2c81bfd5 | 92 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, |
665bc539 | 93 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); |
2c81bfd5 | 94 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, |
665bc539 | 95 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); |
2c81bfd5 | 96 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, |
665bc539 | 97 | ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); |
2c81bfd5 | 98 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, |
665bc539 | 99 | ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); |
2c81bfd5 | 100 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, |
665bc539 | 101 | ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); |
2c81bfd5 | 102 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, |
665bc539 | 103 | ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); |
2c81bfd5 | 104 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, |
665bc539 | 105 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); |
2c81bfd5 | 106 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, |
665bc539 | 107 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); |
2c81bfd5 | 108 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, |
665bc539 | 109 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); |
2c81bfd5 | 110 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, |
665bc539 | 111 | ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); |
2c81bfd5 | 112 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, |
665bc539 | 113 | ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); |
2c81bfd5 | 114 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, |
665bc539 | 115 | ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); |
2c81bfd5 | 116 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, |
665bc539 | 117 | ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT); |
2c81bfd5 | 118 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, |
665bc539 | 119 | ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT); |
2c81bfd5 | 120 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, |
665bc539 | 121 | ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT); |
2c81bfd5 | 122 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, |
665bc539 | 123 | ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); |
2c81bfd5 | 124 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, |
665bc539 | 125 | ETHTOOL_LINK_MODE_10000baseT_Full_BIT); |
2c81bfd5 | 126 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, |
665bc539 | 127 | ETHTOOL_LINK_MODE_25000baseCR_Full_BIT); |
2c81bfd5 | 128 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, |
665bc539 | 129 | ETHTOOL_LINK_MODE_25000baseKR_Full_BIT); |
2c81bfd5 | 130 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, |
665bc539 | 131 | ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); |
2c81bfd5 | 132 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, |
665bc539 | 133 | ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT); |
2c81bfd5 | 134 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, |
665bc539 GP |
135 | ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT); |
136 | } | |
137 | ||
8ff57c18 TT |
138 | typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable); |
139 | ||
140 | struct pflag_desc { | |
141 | char name[ETH_GSTRING_LEN]; | |
142 | mlx5e_pflag_handler handler; | |
d2408205 KH |
143 | }; |
144 | ||
8ff57c18 TT |
145 | static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS]; |
146 | ||
076b0936 | 147 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset) |
f62b8bb8 | 148 | { |
c0752f2b KH |
149 | int i, num_stats = 0; |
150 | ||
f62b8bb8 AV |
151 | switch (sset) { |
152 | case ETH_SS_STATS: | |
c0752f2b KH |
153 | for (i = 0; i < mlx5e_num_stats_grps; i++) |
154 | num_stats += mlx5e_stats_grps[i].get_num_stats(priv); | |
1fe85006 | 155 | return num_stats; |
4e59e288 | 156 | case ETH_SS_PRIV_FLAGS: |
8ff57c18 | 157 | return MLX5E_NUM_PFLAGS; |
d605d668 KH |
158 | case ETH_SS_TEST: |
159 | return mlx5e_self_test_num(priv); | |
f62b8bb8 AV |
160 | /* fallthrough */ |
161 | default: | |
162 | return -EOPNOTSUPP; | |
163 | } | |
164 | } | |
165 | ||
076b0936 ES |
166 | static int mlx5e_get_sset_count(struct net_device *dev, int sset) |
167 | { | |
168 | struct mlx5e_priv *priv = netdev_priv(dev); | |
169 | ||
170 | return mlx5e_ethtool_get_sset_count(priv, sset); | |
171 | } | |
172 | ||
c045deef | 173 | static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data) |
9218b44d | 174 | { |
1fe85006 | 175 | int i, idx = 0; |
9218b44d | 176 | |
c0752f2b KH |
177 | for (i = 0; i < mlx5e_num_stats_grps; i++) |
178 | idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx); | |
9218b44d GP |
179 | } |
180 | ||
c045deef | 181 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data) |
f62b8bb8 | 182 | { |
4e59e288 | 183 | int i; |
f62b8bb8 AV |
184 | |
185 | switch (stringset) { | |
186 | case ETH_SS_PRIV_FLAGS: | |
8ff57c18 TT |
187 | for (i = 0; i < MLX5E_NUM_PFLAGS; i++) |
188 | strcpy(data + i * ETH_GSTRING_LEN, | |
189 | mlx5e_priv_flags[i].name); | |
f62b8bb8 AV |
190 | break; |
191 | ||
192 | case ETH_SS_TEST: | |
d605d668 KH |
193 | for (i = 0; i < mlx5e_self_test_num(priv); i++) |
194 | strcpy(data + i * ETH_GSTRING_LEN, | |
195 | mlx5e_self_tests[i]); | |
f62b8bb8 AV |
196 | break; |
197 | ||
198 | case ETH_SS_STATS: | |
9218b44d | 199 | mlx5e_fill_stats_strings(priv, data); |
f62b8bb8 AV |
200 | break; |
201 | } | |
202 | } | |
203 | ||
c045deef | 204 | static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
f62b8bb8 AV |
205 | { |
206 | struct mlx5e_priv *priv = netdev_priv(dev); | |
076b0936 ES |
207 | |
208 | mlx5e_ethtool_get_strings(priv, stringset, data); | |
209 | } | |
210 | ||
211 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
212 | struct ethtool_stats *stats, u64 *data) | |
213 | { | |
1fe85006 | 214 | int i, idx = 0; |
f62b8bb8 | 215 | |
f62b8bb8 | 216 | mutex_lock(&priv->state_lock); |
19386177 | 217 | mlx5e_update_stats(priv); |
f62b8bb8 AV |
218 | mutex_unlock(&priv->state_lock); |
219 | ||
c0752f2b KH |
220 | for (i = 0; i < mlx5e_num_stats_grps; i++) |
221 | idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx); | |
f62b8bb8 AV |
222 | } |
223 | ||
076b0936 ES |
224 | static void mlx5e_get_ethtool_stats(struct net_device *dev, |
225 | struct ethtool_stats *stats, | |
226 | u64 *data) | |
227 | { | |
228 | struct mlx5e_priv *priv = netdev_priv(dev); | |
229 | ||
230 | mlx5e_ethtool_get_ethtool_stats(priv, stats, data); | |
231 | } | |
232 | ||
076b0936 ES |
233 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, |
234 | struct ethtool_ringparam *param) | |
f62b8bb8 | 235 | { |
73281b78 | 236 | param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; |
f62b8bb8 | 237 | param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE; |
73281b78 | 238 | param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames; |
6a9764ef | 239 | param->tx_pending = 1 << priv->channels.params.log_sq_size; |
f62b8bb8 AV |
240 | } |
241 | ||
076b0936 ES |
242 | static void mlx5e_get_ringparam(struct net_device *dev, |
243 | struct ethtool_ringparam *param) | |
f62b8bb8 AV |
244 | { |
245 | struct mlx5e_priv *priv = netdev_priv(dev); | |
076b0936 ES |
246 | |
247 | mlx5e_ethtool_get_ringparam(priv, param); | |
248 | } | |
249 | ||
250 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
251 | struct ethtool_ringparam *param) | |
252 | { | |
546f18ed | 253 | struct mlx5e_channels new_channels = {}; |
f62b8bb8 AV |
254 | u8 log_rq_size; |
255 | u8 log_sq_size; | |
256 | int err = 0; | |
257 | ||
258 | if (param->rx_jumbo_pending) { | |
076b0936 | 259 | netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n", |
f62b8bb8 AV |
260 | __func__); |
261 | return -EINVAL; | |
262 | } | |
263 | if (param->rx_mini_pending) { | |
076b0936 | 264 | netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n", |
f62b8bb8 AV |
265 | __func__); |
266 | return -EINVAL; | |
267 | } | |
cc8e9ebf | 268 | |
73281b78 | 269 | if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) { |
076b0936 | 270 | netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n", |
f62b8bb8 | 271 | __func__, param->rx_pending, |
73281b78 | 272 | 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE); |
fe4c988b SM |
273 | return -EINVAL; |
274 | } | |
275 | ||
f62b8bb8 | 276 | if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) { |
076b0936 | 277 | netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n", |
f62b8bb8 AV |
278 | __func__, param->tx_pending, |
279 | 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); | |
280 | return -EINVAL; | |
281 | } | |
f62b8bb8 | 282 | |
73281b78 | 283 | log_rq_size = order_base_2(param->rx_pending); |
f62b8bb8 | 284 | log_sq_size = order_base_2(param->tx_pending); |
f62b8bb8 | 285 | |
73281b78 | 286 | if (log_rq_size == priv->channels.params.log_rq_mtu_frames && |
6a9764ef | 287 | log_sq_size == priv->channels.params.log_sq_size) |
f62b8bb8 AV |
288 | return 0; |
289 | ||
290 | mutex_lock(&priv->state_lock); | |
98e81b0a | 291 | |
546f18ed | 292 | new_channels.params = priv->channels.params; |
73281b78 | 293 | new_channels.params.log_rq_mtu_frames = log_rq_size; |
546f18ed | 294 | new_channels.params.log_sq_size = log_sq_size; |
98e81b0a | 295 | |
546f18ed SM |
296 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
297 | priv->channels.params = new_channels.params; | |
298 | goto unlock; | |
299 | } | |
98e81b0a | 300 | |
546f18ed SM |
301 | err = mlx5e_open_channels(priv, &new_channels); |
302 | if (err) | |
303 | goto unlock; | |
304 | ||
2e20a151 | 305 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
98e81b0a | 306 | |
546f18ed | 307 | unlock: |
f62b8bb8 AV |
308 | mutex_unlock(&priv->state_lock); |
309 | ||
310 | return err; | |
311 | } | |
312 | ||
076b0936 ES |
313 | static int mlx5e_set_ringparam(struct net_device *dev, |
314 | struct ethtool_ringparam *param) | |
f62b8bb8 AV |
315 | { |
316 | struct mlx5e_priv *priv = netdev_priv(dev); | |
f62b8bb8 | 317 | |
076b0936 ES |
318 | return mlx5e_ethtool_set_ringparam(priv, param); |
319 | } | |
320 | ||
321 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
322 | struct ethtool_channels *ch) | |
323 | { | |
779d986d | 324 | ch->max_combined = mlx5e_get_netdev_max_channels(priv->netdev); |
6a9764ef | 325 | ch->combined_count = priv->channels.params.num_channels; |
f62b8bb8 AV |
326 | } |
327 | ||
076b0936 ES |
328 | static void mlx5e_get_channels(struct net_device *dev, |
329 | struct ethtool_channels *ch) | |
f62b8bb8 AV |
330 | { |
331 | struct mlx5e_priv *priv = netdev_priv(dev); | |
076b0936 ES |
332 | |
333 | mlx5e_ethtool_get_channels(priv, ch); | |
334 | } | |
335 | ||
336 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
337 | struct ethtool_channels *ch) | |
338 | { | |
f62b8bb8 | 339 | unsigned int count = ch->combined_count; |
55c2503d | 340 | struct mlx5e_channels new_channels = {}; |
45bf454a | 341 | bool arfs_enabled; |
f62b8bb8 AV |
342 | int err = 0; |
343 | ||
344 | if (!count) { | |
076b0936 | 345 | netdev_info(priv->netdev, "%s: combined_count=0 not supported\n", |
f62b8bb8 AV |
346 | __func__); |
347 | return -EINVAL; | |
348 | } | |
f62b8bb8 | 349 | |
6a9764ef | 350 | if (priv->channels.params.num_channels == count) |
f62b8bb8 AV |
351 | return 0; |
352 | ||
353 | mutex_lock(&priv->state_lock); | |
98e81b0a | 354 | |
55c2503d SM |
355 | new_channels.params = priv->channels.params; |
356 | new_channels.params.num_channels = count; | |
5a8e1267 | 357 | if (!netif_is_rxfh_configured(priv->netdev)) |
bbeb53b8 | 358 | mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt, |
5a8e1267 | 359 | MLX5E_INDIR_RQT_SIZE, count); |
55c2503d SM |
360 | |
361 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
362 | priv->channels.params = new_channels.params; | |
363 | goto out; | |
364 | } | |
365 | ||
366 | /* Create fresh channels with new parameters */ | |
367 | err = mlx5e_open_channels(priv, &new_channels); | |
368 | if (err) | |
369 | goto out; | |
98e81b0a | 370 | |
076b0936 | 371 | arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE; |
45bf454a MG |
372 | if (arfs_enabled) |
373 | mlx5e_arfs_disable(priv); | |
374 | ||
55c2503d | 375 | /* Switch to new channels, set new parameters and close old ones */ |
2e20a151 | 376 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
45bf454a MG |
377 | |
378 | if (arfs_enabled) { | |
379 | err = mlx5e_arfs_enable(priv); | |
380 | if (err) | |
076b0936 | 381 | netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n", |
45bf454a MG |
382 | __func__, err); |
383 | } | |
98e81b0a | 384 | |
45bf454a | 385 | out: |
f62b8bb8 AV |
386 | mutex_unlock(&priv->state_lock); |
387 | ||
388 | return err; | |
389 | } | |
390 | ||
076b0936 ES |
391 | static int mlx5e_set_channels(struct net_device *dev, |
392 | struct ethtool_channels *ch) | |
f62b8bb8 | 393 | { |
076b0936 ES |
394 | struct mlx5e_priv *priv = netdev_priv(dev); |
395 | ||
396 | return mlx5e_ethtool_set_channels(priv, ch); | |
397 | } | |
f62b8bb8 | 398 | |
076b0936 ES |
399 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, |
400 | struct ethtool_coalesce *coal) | |
401 | { | |
cbce4f44 TG |
402 | struct net_dim_cq_moder *rx_moder, *tx_moder; |
403 | ||
7524a5d8 | 404 | if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) |
9eb78923 | 405 | return -EOPNOTSUPP; |
7524a5d8 | 406 | |
cbce4f44 TG |
407 | rx_moder = &priv->channels.params.rx_cq_moderation; |
408 | coal->rx_coalesce_usecs = rx_moder->usec; | |
409 | coal->rx_max_coalesced_frames = rx_moder->pkts; | |
410 | coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled; | |
411 | ||
412 | tx_moder = &priv->channels.params.tx_cq_moderation; | |
413 | coal->tx_coalesce_usecs = tx_moder->usec; | |
414 | coal->tx_max_coalesced_frames = tx_moder->pkts; | |
415 | coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled; | |
f62b8bb8 AV |
416 | |
417 | return 0; | |
418 | } | |
419 | ||
076b0936 ES |
420 | static int mlx5e_get_coalesce(struct net_device *netdev, |
421 | struct ethtool_coalesce *coal) | |
422 | { | |
423 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
424 | ||
425 | return mlx5e_ethtool_get_coalesce(priv, coal); | |
426 | } | |
427 | ||
b392a207 MS |
428 | #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD |
429 | #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT | |
430 | ||
546f18ed SM |
431 | static void |
432 | mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal) | |
f62b8bb8 | 433 | { |
f62b8bb8 | 434 | struct mlx5_core_dev *mdev = priv->mdev; |
f62b8bb8 AV |
435 | int tc; |
436 | int i; | |
437 | ||
ff9c852f SM |
438 | for (i = 0; i < priv->channels.num; ++i) { |
439 | struct mlx5e_channel *c = priv->channels.c[i]; | |
f62b8bb8 AV |
440 | |
441 | for (tc = 0; tc < c->num_tc; tc++) { | |
442 | mlx5_core_modify_cq_moderation(mdev, | |
443 | &c->sq[tc].cq.mcq, | |
444 | coal->tx_coalesce_usecs, | |
445 | coal->tx_max_coalesced_frames); | |
446 | } | |
447 | ||
448 | mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq, | |
449 | coal->rx_coalesce_usecs, | |
450 | coal->rx_max_coalesced_frames); | |
451 | } | |
546f18ed | 452 | } |
f62b8bb8 | 453 | |
076b0936 ES |
454 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, |
455 | struct ethtool_coalesce *coal) | |
546f18ed | 456 | { |
cbce4f44 | 457 | struct net_dim_cq_moder *rx_moder, *tx_moder; |
546f18ed SM |
458 | struct mlx5_core_dev *mdev = priv->mdev; |
459 | struct mlx5e_channels new_channels = {}; | |
460 | int err = 0; | |
461 | bool reset; | |
cb3c7fd4 | 462 | |
546f18ed SM |
463 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
464 | return -EOPNOTSUPP; | |
465 | ||
b392a207 MS |
466 | if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || |
467 | coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { | |
468 | netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n", | |
469 | __func__, MLX5E_MAX_COAL_TIME); | |
470 | return -ERANGE; | |
471 | } | |
472 | ||
473 | if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || | |
474 | coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { | |
475 | netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n", | |
476 | __func__, MLX5E_MAX_COAL_FRAMES); | |
477 | return -ERANGE; | |
478 | } | |
479 | ||
546f18ed SM |
480 | mutex_lock(&priv->state_lock); |
481 | new_channels.params = priv->channels.params; | |
482 | ||
cbce4f44 TG |
483 | rx_moder = &new_channels.params.rx_cq_moderation; |
484 | rx_moder->usec = coal->rx_coalesce_usecs; | |
485 | rx_moder->pkts = coal->rx_max_coalesced_frames; | |
486 | new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce; | |
487 | ||
488 | tx_moder = &new_channels.params.tx_cq_moderation; | |
489 | tx_moder->usec = coal->tx_coalesce_usecs; | |
490 | tx_moder->pkts = coal->tx_max_coalesced_frames; | |
491 | new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce; | |
546f18ed SM |
492 | |
493 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
494 | priv->channels.params = new_channels.params; | |
495 | goto out; | |
496 | } | |
497 | /* we are opened */ | |
498 | ||
cbce4f44 TG |
499 | reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) || |
500 | (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled); | |
501 | ||
546f18ed SM |
502 | if (!reset) { |
503 | mlx5e_set_priv_channels_coalesce(priv, coal); | |
504 | priv->channels.params = new_channels.params; | |
505 | goto out; | |
506 | } | |
507 | ||
508 | /* open fresh channels with new coal parameters */ | |
509 | err = mlx5e_open_channels(priv, &new_channels); | |
510 | if (err) | |
511 | goto out; | |
512 | ||
2e20a151 | 513 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
546f18ed SM |
514 | |
515 | out: | |
2fcb92fb | 516 | mutex_unlock(&priv->state_lock); |
cb3c7fd4 | 517 | return err; |
f62b8bb8 AV |
518 | } |
519 | ||
076b0936 ES |
520 | static int mlx5e_set_coalesce(struct net_device *netdev, |
521 | struct ethtool_coalesce *coal) | |
522 | { | |
523 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
524 | ||
525 | return mlx5e_ethtool_set_coalesce(priv, coal); | |
526 | } | |
527 | ||
665bc539 GP |
528 | static void ptys2ethtool_supported_link(unsigned long *supported_modes, |
529 | u32 eth_proto_cap) | |
f62b8bb8 | 530 | { |
7abc2110 | 531 | unsigned long proto_cap = eth_proto_cap; |
665bc539 | 532 | int proto; |
f62b8bb8 | 533 | |
7abc2110 | 534 | for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER) |
665bc539 GP |
535 | bitmap_or(supported_modes, supported_modes, |
536 | ptys2ethtool_table[proto].supported, | |
537 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
f62b8bb8 AV |
538 | } |
539 | ||
665bc539 GP |
540 | static void ptys2ethtool_adver_link(unsigned long *advertising_modes, |
541 | u32 eth_proto_cap) | |
f62b8bb8 | 542 | { |
7abc2110 | 543 | unsigned long proto_cap = eth_proto_cap; |
665bc539 | 544 | int proto; |
f62b8bb8 | 545 | |
7abc2110 | 546 | for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER) |
665bc539 GP |
547 | bitmap_or(advertising_modes, advertising_modes, |
548 | ptys2ethtool_table[proto].advertised, | |
549 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
f62b8bb8 AV |
550 | } |
551 | ||
6cfa9460 SA |
552 | static const u32 pplm_fec_2_ethtool[] = { |
553 | [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF, | |
554 | [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER, | |
555 | [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS, | |
556 | }; | |
557 | ||
558 | static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size) | |
559 | { | |
560 | int mode = 0; | |
561 | ||
562 | if (!fec_mode) | |
563 | return ETHTOOL_FEC_AUTO; | |
564 | ||
565 | mode = find_first_bit(&fec_mode, size); | |
566 | ||
567 | if (mode < ARRAY_SIZE(pplm_fec_2_ethtool)) | |
568 | return pplm_fec_2_ethtool[mode]; | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | /* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */ | |
574 | static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code) | |
575 | { | |
576 | u32 offset; | |
577 | ||
578 | offset = find_first_bit(ðtool_fec_code, sizeof(u32)); | |
579 | offset -= ETHTOOL_FEC_OFF_BIT; | |
580 | offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT; | |
581 | ||
582 | return offset; | |
583 | } | |
584 | ||
585 | static int get_fec_supported_advertised(struct mlx5_core_dev *dev, | |
586 | struct ethtool_link_ksettings *link_ksettings) | |
587 | { | |
588 | u_long fec_caps = 0; | |
589 | u32 active_fec = 0; | |
590 | u32 offset; | |
591 | u32 bitn; | |
592 | int err; | |
593 | ||
594 | err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps); | |
595 | if (err) | |
596 | return (err == -EOPNOTSUPP) ? 0 : err; | |
597 | ||
598 | err = mlx5e_get_fec_mode(dev, &active_fec, NULL); | |
599 | if (err) | |
600 | return err; | |
601 | ||
602 | for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) { | |
603 | u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn]; | |
604 | ||
605 | offset = ethtool_fec2ethtool_caps(ethtool_bitmask); | |
606 | __set_bit(offset, link_ksettings->link_modes.supported); | |
607 | } | |
608 | ||
609 | active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE); | |
610 | offset = ethtool_fec2ethtool_caps(active_fec); | |
611 | __set_bit(offset, link_ksettings->link_modes.advertising); | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
46e9d0b6 EBE |
616 | static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings, |
617 | u32 eth_proto_cap, | |
618 | u8 connector_type) | |
f62b8bb8 | 619 | { |
46e9d0b6 EBE |
620 | if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) { |
621 | if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | |
622 | | MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | |
623 | | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | |
624 | | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | |
625 | | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | |
626 | | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { | |
627 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
628 | supported, | |
629 | FIBRE); | |
630 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
631 | advertising, | |
632 | FIBRE); | |
633 | } | |
634 | ||
635 | if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4) | |
636 | | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | |
637 | | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | |
638 | | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | |
639 | | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) { | |
640 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
641 | supported, | |
642 | Backplane); | |
643 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
644 | advertising, | |
645 | Backplane); | |
646 | } | |
647 | return; | |
f62b8bb8 AV |
648 | } |
649 | ||
46e9d0b6 EBE |
650 | switch (connector_type) { |
651 | case MLX5E_PORT_TP: | |
652 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
653 | supported, TP); | |
654 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
655 | advertising, TP); | |
656 | break; | |
657 | case MLX5E_PORT_AUI: | |
658 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
659 | supported, AUI); | |
660 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
661 | advertising, AUI); | |
662 | break; | |
663 | case MLX5E_PORT_BNC: | |
664 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
665 | supported, BNC); | |
666 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
667 | advertising, BNC); | |
668 | break; | |
669 | case MLX5E_PORT_MII: | |
670 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
671 | supported, MII); | |
672 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
673 | advertising, MII); | |
674 | break; | |
675 | case MLX5E_PORT_FIBRE: | |
676 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
677 | supported, FIBRE); | |
678 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
679 | advertising, FIBRE); | |
680 | break; | |
681 | case MLX5E_PORT_DA: | |
682 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
683 | supported, Backplane); | |
684 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
685 | advertising, Backplane); | |
686 | break; | |
687 | case MLX5E_PORT_NONE: | |
688 | case MLX5E_PORT_OTHER: | |
689 | default: | |
690 | break; | |
f62b8bb8 | 691 | } |
f62b8bb8 AV |
692 | } |
693 | ||
694 | static void get_speed_duplex(struct net_device *netdev, | |
695 | u32 eth_proto_oper, | |
665bc539 | 696 | struct ethtool_link_ksettings *link_ksettings) |
f62b8bb8 | 697 | { |
f62b8bb8 AV |
698 | u32 speed = SPEED_UNKNOWN; |
699 | u8 duplex = DUPLEX_UNKNOWN; | |
700 | ||
701 | if (!netif_carrier_ok(netdev)) | |
702 | goto out; | |
703 | ||
2c81bfd5 HN |
704 | speed = mlx5e_port_ptys2speed(eth_proto_oper); |
705 | if (!speed) { | |
706 | speed = SPEED_UNKNOWN; | |
707 | goto out; | |
f62b8bb8 | 708 | } |
2c81bfd5 HN |
709 | |
710 | duplex = DUPLEX_FULL; | |
711 | ||
f62b8bb8 | 712 | out: |
665bc539 GP |
713 | link_ksettings->base.speed = speed; |
714 | link_ksettings->base.duplex = duplex; | |
f62b8bb8 AV |
715 | } |
716 | ||
665bc539 GP |
717 | static void get_supported(u32 eth_proto_cap, |
718 | struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 719 | { |
665bc539 GP |
720 | unsigned long *supported = link_ksettings->link_modes.supported; |
721 | ||
665bc539 GP |
722 | ptys2ethtool_supported_link(supported, eth_proto_cap); |
723 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause); | |
f62b8bb8 AV |
724 | } |
725 | ||
726 | static void get_advertising(u32 eth_proto_cap, u8 tx_pause, | |
665bc539 GP |
727 | u8 rx_pause, |
728 | struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 729 | { |
665bc539 GP |
730 | unsigned long *advertising = link_ksettings->link_modes.advertising; |
731 | ||
732 | ptys2ethtool_adver_link(advertising, eth_proto_cap); | |
e3c19503 | 733 | if (rx_pause) |
665bc539 GP |
734 | ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause); |
735 | if (tx_pause ^ rx_pause) | |
736 | ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause); | |
f62b8bb8 AV |
737 | } |
738 | ||
5b4793f8 EBE |
739 | static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = { |
740 | [MLX5E_PORT_UNKNOWN] = PORT_OTHER, | |
741 | [MLX5E_PORT_NONE] = PORT_NONE, | |
742 | [MLX5E_PORT_TP] = PORT_TP, | |
743 | [MLX5E_PORT_AUI] = PORT_AUI, | |
744 | [MLX5E_PORT_BNC] = PORT_BNC, | |
745 | [MLX5E_PORT_MII] = PORT_MII, | |
746 | [MLX5E_PORT_FIBRE] = PORT_FIBRE, | |
747 | [MLX5E_PORT_DA] = PORT_DA, | |
748 | [MLX5E_PORT_OTHER] = PORT_OTHER, | |
749 | }; | |
750 | ||
751 | static u8 get_connector_port(u32 eth_proto, u8 connector_type) | |
f62b8bb8 | 752 | { |
5b4793f8 EBE |
753 | if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER) |
754 | return ptys2connector_type[connector_type]; | |
755 | ||
61bf2125 OG |
756 | if (eth_proto & |
757 | (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | | |
758 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | | |
759 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | | |
760 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { | |
761 | return PORT_FIBRE; | |
f62b8bb8 AV |
762 | } |
763 | ||
61bf2125 OG |
764 | if (eth_proto & |
765 | (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | | |
766 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | | |
767 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) { | |
768 | return PORT_DA; | |
f62b8bb8 AV |
769 | } |
770 | ||
61bf2125 OG |
771 | if (eth_proto & |
772 | (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | | |
773 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | | |
774 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | | |
775 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) { | |
776 | return PORT_NONE; | |
f62b8bb8 AV |
777 | } |
778 | ||
779 | return PORT_OTHER; | |
780 | } | |
781 | ||
665bc539 GP |
782 | static void get_lp_advertising(u32 eth_proto_lp, |
783 | struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 784 | { |
665bc539 GP |
785 | unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising; |
786 | ||
787 | ptys2ethtool_adver_link(lp_advertising, eth_proto_lp); | |
f62b8bb8 AV |
788 | } |
789 | ||
371289b6 OG |
790 | int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, |
791 | struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 792 | { |
f62b8bb8 | 793 | struct mlx5_core_dev *mdev = priv->mdev; |
c4f287c4 | 794 | u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; |
b383b544 GP |
795 | u32 rx_pause = 0; |
796 | u32 tx_pause = 0; | |
f62b8bb8 AV |
797 | u32 eth_proto_cap; |
798 | u32 eth_proto_admin; | |
799 | u32 eth_proto_lp; | |
800 | u32 eth_proto_oper; | |
52244d96 GP |
801 | u8 an_disable_admin; |
802 | u8 an_status; | |
5b4793f8 | 803 | u8 connector_type; |
f62b8bb8 AV |
804 | int err; |
805 | ||
a05bdefa | 806 | err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1); |
f62b8bb8 | 807 | if (err) { |
371289b6 | 808 | netdev_err(priv->netdev, "%s: query port ptys failed: %d\n", |
f62b8bb8 | 809 | __func__, err); |
6cfa9460 | 810 | goto err_query_regs; |
f62b8bb8 AV |
811 | } |
812 | ||
52244d96 GP |
813 | eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability); |
814 | eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin); | |
815 | eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper); | |
816 | eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise); | |
817 | an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin); | |
818 | an_status = MLX5_GET(ptys_reg, out, an_status); | |
5b4793f8 | 819 | connector_type = MLX5_GET(ptys_reg, out, connector_type); |
f62b8bb8 | 820 | |
b383b544 GP |
821 | mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); |
822 | ||
665bc539 GP |
823 | ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); |
824 | ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); | |
f62b8bb8 | 825 | |
665bc539 | 826 | get_supported(eth_proto_cap, link_ksettings); |
b383b544 | 827 | get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings); |
371289b6 | 828 | get_speed_duplex(priv->netdev, eth_proto_oper, link_ksettings); |
f62b8bb8 AV |
829 | |
830 | eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap; | |
831 | ||
5b4793f8 EBE |
832 | link_ksettings->base.port = get_connector_port(eth_proto_oper, |
833 | connector_type); | |
46e9d0b6 EBE |
834 | ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin, |
835 | connector_type); | |
665bc539 | 836 | get_lp_advertising(eth_proto_lp, link_ksettings); |
f62b8bb8 | 837 | |
52244d96 GP |
838 | if (an_status == MLX5_AN_COMPLETE) |
839 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
840 | lp_advertising, Autoneg); | |
841 | ||
842 | link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE : | |
843 | AUTONEG_ENABLE; | |
844 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, | |
845 | Autoneg); | |
6cfa9460 | 846 | |
2eb1e425 SA |
847 | err = get_fec_supported_advertised(mdev, link_ksettings); |
848 | if (err) { | |
371289b6 | 849 | netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n", |
6cfa9460 | 850 | __func__, err); |
2eb1e425 SA |
851 | err = 0; /* don't fail caps query because of FEC error */ |
852 | } | |
6cfa9460 | 853 | |
52244d96 GP |
854 | if (!an_disable_admin) |
855 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
856 | advertising, Autoneg); | |
857 | ||
6cfa9460 | 858 | err_query_regs: |
f62b8bb8 AV |
859 | return err; |
860 | } | |
861 | ||
371289b6 OG |
862 | static int mlx5e_get_link_ksettings(struct net_device *netdev, |
863 | struct ethtool_link_ksettings *link_ksettings) | |
864 | { | |
865 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
866 | ||
867 | return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings); | |
868 | } | |
869 | ||
665bc539 | 870 | static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) |
f62b8bb8 AV |
871 | { |
872 | u32 i, ptys_modes = 0; | |
873 | ||
874 | for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { | |
665bc539 GP |
875 | if (bitmap_intersects(ptys2ethtool_table[i].advertised, |
876 | link_modes, | |
877 | __ETHTOOL_LINK_MODE_MASK_NBITS)) | |
f62b8bb8 AV |
878 | ptys_modes |= MLX5E_PROT_MASK(i); |
879 | } | |
880 | ||
881 | return ptys_modes; | |
882 | } | |
883 | ||
371289b6 OG |
884 | int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, |
885 | const struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 886 | { |
f62b8bb8 | 887 | struct mlx5_core_dev *mdev = priv->mdev; |
52244d96 GP |
888 | u32 eth_proto_cap, eth_proto_admin; |
889 | bool an_changes = false; | |
890 | u8 an_disable_admin; | |
891 | u8 an_disable_cap; | |
892 | bool an_disable; | |
f62b8bb8 | 893 | u32 link_modes; |
52244d96 | 894 | u8 an_status; |
f62b8bb8 | 895 | u32 speed; |
f62b8bb8 AV |
896 | int err; |
897 | ||
665bc539 | 898 | speed = link_ksettings->base.speed; |
f62b8bb8 | 899 | |
665bc539 GP |
900 | link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ? |
901 | mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) : | |
2c81bfd5 | 902 | mlx5e_port_speed2linkmodes(speed); |
f62b8bb8 AV |
903 | |
904 | err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN); | |
905 | if (err) { | |
371289b6 | 906 | netdev_err(priv->netdev, "%s: query port eth proto cap failed: %d\n", |
f62b8bb8 AV |
907 | __func__, err); |
908 | goto out; | |
909 | } | |
910 | ||
911 | link_modes = link_modes & eth_proto_cap; | |
912 | if (!link_modes) { | |
371289b6 | 913 | netdev_err(priv->netdev, "%s: Not supported link mode(s) requested", |
f62b8bb8 AV |
914 | __func__); |
915 | err = -EINVAL; | |
916 | goto out; | |
917 | } | |
918 | ||
919 | err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN); | |
920 | if (err) { | |
371289b6 | 921 | netdev_err(priv->netdev, "%s: query port eth proto admin failed: %d\n", |
f62b8bb8 AV |
922 | __func__, err); |
923 | goto out; | |
924 | } | |
925 | ||
52244d96 GP |
926 | mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status, |
927 | &an_disable_cap, &an_disable_admin); | |
928 | ||
929 | an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE; | |
930 | an_changes = ((!an_disable && an_disable_admin) || | |
931 | (an_disable && !an_disable_admin)); | |
932 | ||
933 | if (!an_changes && link_modes == eth_proto_admin) | |
f62b8bb8 AV |
934 | goto out; |
935 | ||
52244d96 | 936 | mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN); |
667daeda | 937 | mlx5_toggle_port_link(mdev); |
f62b8bb8 | 938 | |
f62b8bb8 AV |
939 | out: |
940 | return err; | |
941 | } | |
942 | ||
371289b6 OG |
943 | static int mlx5e_set_link_ksettings(struct net_device *netdev, |
944 | const struct ethtool_link_ksettings *link_ksettings) | |
945 | { | |
946 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
947 | ||
948 | return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings); | |
949 | } | |
950 | ||
a5355de8 OG |
951 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv) |
952 | { | |
bbeb53b8 | 953 | return sizeof(priv->rss_params.toeplitz_hash_key); |
a5355de8 OG |
954 | } |
955 | ||
2d75b2bc AS |
956 | static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) |
957 | { | |
958 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
959 | ||
a5355de8 | 960 | return mlx5e_ethtool_get_rxfh_key_size(priv); |
2d75b2bc AS |
961 | } |
962 | ||
a5355de8 | 963 | u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv) |
2d75b2bc AS |
964 | { |
965 | return MLX5E_INDIR_RQT_SIZE; | |
966 | } | |
967 | ||
a5355de8 OG |
968 | static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev) |
969 | { | |
970 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
971 | ||
972 | return mlx5e_ethtool_get_rxfh_indir_size(priv); | |
973 | } | |
974 | ||
2be6967c SM |
975 | static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, |
976 | u8 *hfunc) | |
977 | { | |
978 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
bbeb53b8 | 979 | struct mlx5e_rss_params *rss = &priv->rss_params; |
2be6967c | 980 | |
2d75b2bc | 981 | if (indir) |
bbeb53b8 AL |
982 | memcpy(indir, rss->indirection_rqt, |
983 | sizeof(rss->indirection_rqt)); | |
2d75b2bc AS |
984 | |
985 | if (key) | |
bbeb53b8 AL |
986 | memcpy(key, rss->toeplitz_hash_key, |
987 | sizeof(rss->toeplitz_hash_key)); | |
2d75b2bc | 988 | |
2be6967c | 989 | if (hfunc) |
bbeb53b8 | 990 | *hfunc = rss->hfunc; |
2be6967c SM |
991 | |
992 | return 0; | |
993 | } | |
994 | ||
98e81b0a | 995 | static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, |
2be6967c SM |
996 | const u8 *key, const u8 hfunc) |
997 | { | |
98e81b0a | 998 | struct mlx5e_priv *priv = netdev_priv(dev); |
bbeb53b8 | 999 | struct mlx5e_rss_params *rss = &priv->rss_params; |
bdfc028d | 1000 | int inlen = MLX5_ST_SZ_BYTES(modify_tir_in); |
1d3398fa | 1001 | bool hash_changed = false; |
bdfc028d | 1002 | void *in; |
2be6967c | 1003 | |
2d75b2bc AS |
1004 | if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && |
1005 | (hfunc != ETH_RSS_HASH_XOR) && | |
2be6967c SM |
1006 | (hfunc != ETH_RSS_HASH_TOP)) |
1007 | return -EINVAL; | |
1008 | ||
1b9a07ee | 1009 | in = kvzalloc(inlen, GFP_KERNEL); |
bdfc028d TT |
1010 | if (!in) |
1011 | return -ENOMEM; | |
1012 | ||
2be6967c SM |
1013 | mutex_lock(&priv->state_lock); |
1014 | ||
bbeb53b8 AL |
1015 | if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) { |
1016 | rss->hfunc = hfunc; | |
1d3398fa GP |
1017 | hash_changed = true; |
1018 | } | |
1019 | ||
a5f97fee | 1020 | if (indir) { |
bbeb53b8 AL |
1021 | memcpy(rss->indirection_rqt, indir, |
1022 | sizeof(rss->indirection_rqt)); | |
a5f97fee SM |
1023 | |
1024 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
1025 | u32 rqtn = priv->indir_rqt.rqtn; | |
1026 | struct mlx5e_redirect_rqt_param rrp = { | |
1027 | .is_rss = true, | |
e270e966 AM |
1028 | { |
1029 | .rss = { | |
bbeb53b8 | 1030 | .hfunc = rss->hfunc, |
e270e966 AM |
1031 | .channels = &priv->channels, |
1032 | }, | |
1033 | }, | |
a5f97fee SM |
1034 | }; |
1035 | ||
1036 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); | |
1037 | } | |
1038 | } | |
1039 | ||
1d3398fa | 1040 | if (key) { |
bbeb53b8 AL |
1041 | memcpy(rss->toeplitz_hash_key, key, |
1042 | sizeof(rss->toeplitz_hash_key)); | |
1043 | hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP; | |
1d3398fa | 1044 | } |
2d75b2bc | 1045 | |
1d3398fa GP |
1046 | if (hash_changed) |
1047 | mlx5e_modify_tirs_hash(priv, in, inlen); | |
2d75b2bc | 1048 | |
2be6967c SM |
1049 | mutex_unlock(&priv->state_lock); |
1050 | ||
bdfc028d TT |
1051 | kvfree(in); |
1052 | ||
1053 | return 0; | |
2be6967c SM |
1054 | } |
1055 | ||
2afa609f IK |
1056 | #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100 |
1057 | #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000 | |
1058 | #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85 | |
1059 | #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80 | |
1060 | #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \ | |
1061 | max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \ | |
1062 | (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100) | |
1063 | ||
1064 | static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev, | |
1065 | u16 *pfc_prevention_tout) | |
1066 | { | |
1067 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1068 | struct mlx5_core_dev *mdev = priv->mdev; | |
1069 | ||
1070 | if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || | |
1071 | !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) | |
1072 | return -EOPNOTSUPP; | |
1073 | ||
1074 | return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL); | |
1075 | } | |
1076 | ||
1077 | static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev, | |
1078 | u16 pfc_preven) | |
1079 | { | |
1080 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1081 | struct mlx5_core_dev *mdev = priv->mdev; | |
1082 | u16 critical_tout; | |
1083 | u16 minor; | |
1084 | ||
1085 | if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || | |
1086 | !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) | |
1087 | return -EOPNOTSUPP; | |
1088 | ||
1089 | critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ? | |
1090 | MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC : | |
1091 | pfc_preven; | |
1092 | ||
1093 | if (critical_tout != PFC_STORM_PREVENTION_DISABLE && | |
1094 | (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC || | |
1095 | critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) { | |
1096 | netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n", | |
1097 | __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, | |
1098 | MLX5E_PFC_PREVEN_TOUT_MAX_MSEC); | |
1099 | return -EINVAL; | |
1100 | } | |
1101 | ||
1102 | minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout); | |
1103 | return mlx5_set_port_stall_watermark(mdev, critical_tout, | |
1104 | minor); | |
1105 | } | |
1106 | ||
58d52291 AS |
1107 | static int mlx5e_get_tunable(struct net_device *dev, |
1108 | const struct ethtool_tunable *tuna, | |
1109 | void *data) | |
1110 | { | |
c4554fbc | 1111 | int err; |
58d52291 AS |
1112 | |
1113 | switch (tuna->id) { | |
2afa609f IK |
1114 | case ETHTOOL_PFC_PREVENTION_TOUT: |
1115 | err = mlx5e_get_pfc_prevention_tout(dev, data); | |
1116 | break; | |
58d52291 AS |
1117 | default: |
1118 | err = -EINVAL; | |
1119 | break; | |
1120 | } | |
1121 | ||
1122 | return err; | |
1123 | } | |
1124 | ||
1125 | static int mlx5e_set_tunable(struct net_device *dev, | |
1126 | const struct ethtool_tunable *tuna, | |
1127 | const void *data) | |
1128 | { | |
1129 | struct mlx5e_priv *priv = netdev_priv(dev); | |
c4554fbc | 1130 | int err; |
546f18ed SM |
1131 | |
1132 | mutex_lock(&priv->state_lock); | |
58d52291 AS |
1133 | |
1134 | switch (tuna->id) { | |
2afa609f IK |
1135 | case ETHTOOL_PFC_PREVENTION_TOUT: |
1136 | err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data); | |
58d52291 AS |
1137 | break; |
1138 | default: | |
1139 | err = -EINVAL; | |
1140 | break; | |
1141 | } | |
1142 | ||
546f18ed | 1143 | mutex_unlock(&priv->state_lock); |
58d52291 AS |
1144 | return err; |
1145 | } | |
1146 | ||
371289b6 OG |
1147 | void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, |
1148 | struct ethtool_pauseparam *pauseparam) | |
3c2d18ef | 1149 | { |
3c2d18ef AS |
1150 | struct mlx5_core_dev *mdev = priv->mdev; |
1151 | int err; | |
1152 | ||
1153 | err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause, | |
1154 | &pauseparam->tx_pause); | |
1155 | if (err) { | |
371289b6 | 1156 | netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n", |
3c2d18ef AS |
1157 | __func__, err); |
1158 | } | |
1159 | } | |
1160 | ||
371289b6 OG |
1161 | static void mlx5e_get_pauseparam(struct net_device *netdev, |
1162 | struct ethtool_pauseparam *pauseparam) | |
1163 | { | |
1164 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1165 | ||
1166 | mlx5e_ethtool_get_pauseparam(priv, pauseparam); | |
1167 | } | |
1168 | ||
1169 | int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, | |
1170 | struct ethtool_pauseparam *pauseparam) | |
3c2d18ef | 1171 | { |
3c2d18ef AS |
1172 | struct mlx5_core_dev *mdev = priv->mdev; |
1173 | int err; | |
1174 | ||
1175 | if (pauseparam->autoneg) | |
1176 | return -EINVAL; | |
1177 | ||
1178 | err = mlx5_set_port_pause(mdev, | |
1179 | pauseparam->rx_pause ? 1 : 0, | |
1180 | pauseparam->tx_pause ? 1 : 0); | |
1181 | if (err) { | |
371289b6 | 1182 | netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n", |
3c2d18ef AS |
1183 | __func__, err); |
1184 | } | |
1185 | ||
1186 | return err; | |
1187 | } | |
1188 | ||
371289b6 OG |
1189 | static int mlx5e_set_pauseparam(struct net_device *netdev, |
1190 | struct ethtool_pauseparam *pauseparam) | |
1191 | { | |
1192 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1193 | ||
1194 | return mlx5e_ethtool_set_pauseparam(priv, pauseparam); | |
1195 | } | |
1196 | ||
3844b07e FD |
1197 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1198 | struct ethtool_ts_info *info) | |
ef9814de | 1199 | { |
7c39afb3 | 1200 | struct mlx5_core_dev *mdev = priv->mdev; |
ef9814de | 1201 | |
6dbc80ca | 1202 | info->phc_index = mlx5_clock_get_ptp_index(mdev); |
ef9814de | 1203 | |
6dbc80ca MS |
1204 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || |
1205 | info->phc_index == -1) | |
ef9814de EBE |
1206 | return 0; |
1207 | ||
47654204 AH |
1208 | info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | |
1209 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1210 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
ef9814de | 1211 | |
f0b38117 MD |
1212 | info->tx_types = BIT(HWTSTAMP_TX_OFF) | |
1213 | BIT(HWTSTAMP_TX_ON); | |
ef9814de | 1214 | |
f0b38117 MD |
1215 | info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | |
1216 | BIT(HWTSTAMP_FILTER_ALL); | |
ef9814de EBE |
1217 | |
1218 | return 0; | |
1219 | } | |
1220 | ||
3844b07e FD |
1221 | static int mlx5e_get_ts_info(struct net_device *dev, |
1222 | struct ethtool_ts_info *info) | |
1223 | { | |
1224 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1225 | ||
1226 | return mlx5e_ethtool_get_ts_info(priv, info); | |
1227 | } | |
1228 | ||
928cfe87 TT |
1229 | static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev) |
1230 | { | |
1231 | __u32 ret = 0; | |
1232 | ||
1233 | if (MLX5_CAP_GEN(mdev, wol_g)) | |
1234 | ret |= WAKE_MAGIC; | |
1235 | ||
1236 | if (MLX5_CAP_GEN(mdev, wol_s)) | |
1237 | ret |= WAKE_MAGICSECURE; | |
1238 | ||
1239 | if (MLX5_CAP_GEN(mdev, wol_a)) | |
1240 | ret |= WAKE_ARP; | |
1241 | ||
1242 | if (MLX5_CAP_GEN(mdev, wol_b)) | |
1243 | ret |= WAKE_BCAST; | |
1244 | ||
1245 | if (MLX5_CAP_GEN(mdev, wol_m)) | |
1246 | ret |= WAKE_MCAST; | |
1247 | ||
1248 | if (MLX5_CAP_GEN(mdev, wol_u)) | |
1249 | ret |= WAKE_UCAST; | |
1250 | ||
1251 | if (MLX5_CAP_GEN(mdev, wol_p)) | |
1252 | ret |= WAKE_PHY; | |
1253 | ||
1254 | return ret; | |
1255 | } | |
1256 | ||
1257 | static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode) | |
1258 | { | |
1259 | __u32 ret = 0; | |
1260 | ||
1261 | if (mode & MLX5_WOL_MAGIC) | |
1262 | ret |= WAKE_MAGIC; | |
1263 | ||
1264 | if (mode & MLX5_WOL_SECURED_MAGIC) | |
1265 | ret |= WAKE_MAGICSECURE; | |
1266 | ||
1267 | if (mode & MLX5_WOL_ARP) | |
1268 | ret |= WAKE_ARP; | |
1269 | ||
1270 | if (mode & MLX5_WOL_BROADCAST) | |
1271 | ret |= WAKE_BCAST; | |
1272 | ||
1273 | if (mode & MLX5_WOL_MULTICAST) | |
1274 | ret |= WAKE_MCAST; | |
1275 | ||
1276 | if (mode & MLX5_WOL_UNICAST) | |
1277 | ret |= WAKE_UCAST; | |
1278 | ||
1279 | if (mode & MLX5_WOL_PHY_ACTIVITY) | |
1280 | ret |= WAKE_PHY; | |
1281 | ||
1282 | return ret; | |
1283 | } | |
1284 | ||
1285 | static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode) | |
1286 | { | |
1287 | u8 ret = 0; | |
1288 | ||
1289 | if (mode & WAKE_MAGIC) | |
1290 | ret |= MLX5_WOL_MAGIC; | |
1291 | ||
1292 | if (mode & WAKE_MAGICSECURE) | |
1293 | ret |= MLX5_WOL_SECURED_MAGIC; | |
1294 | ||
1295 | if (mode & WAKE_ARP) | |
1296 | ret |= MLX5_WOL_ARP; | |
1297 | ||
1298 | if (mode & WAKE_BCAST) | |
1299 | ret |= MLX5_WOL_BROADCAST; | |
1300 | ||
1301 | if (mode & WAKE_MCAST) | |
1302 | ret |= MLX5_WOL_MULTICAST; | |
1303 | ||
1304 | if (mode & WAKE_UCAST) | |
1305 | ret |= MLX5_WOL_UNICAST; | |
1306 | ||
1307 | if (mode & WAKE_PHY) | |
1308 | ret |= MLX5_WOL_PHY_ACTIVITY; | |
1309 | ||
1310 | return ret; | |
1311 | } | |
1312 | ||
1313 | static void mlx5e_get_wol(struct net_device *netdev, | |
1314 | struct ethtool_wolinfo *wol) | |
1315 | { | |
1316 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1317 | struct mlx5_core_dev *mdev = priv->mdev; | |
1318 | u8 mlx5_wol_mode; | |
1319 | int err; | |
1320 | ||
1321 | memset(wol, 0, sizeof(*wol)); | |
1322 | ||
1323 | wol->supported = mlx5e_get_wol_supported(mdev); | |
1324 | if (!wol->supported) | |
1325 | return; | |
1326 | ||
1327 | err = mlx5_query_port_wol(mdev, &mlx5_wol_mode); | |
1328 | if (err) | |
1329 | return; | |
1330 | ||
1331 | wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode); | |
1332 | } | |
1333 | ||
1334 | static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
1335 | { | |
1336 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1337 | struct mlx5_core_dev *mdev = priv->mdev; | |
1338 | __u32 wol_supported = mlx5e_get_wol_supported(mdev); | |
1339 | u32 mlx5_wol_mode; | |
1340 | ||
1341 | if (!wol_supported) | |
9eb78923 | 1342 | return -EOPNOTSUPP; |
928cfe87 TT |
1343 | |
1344 | if (wol->wolopts & ~wol_supported) | |
1345 | return -EINVAL; | |
1346 | ||
1347 | mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts); | |
1348 | ||
1349 | return mlx5_set_port_wol(mdev, mlx5_wol_mode); | |
1350 | } | |
1351 | ||
6cfa9460 SA |
1352 | static int mlx5e_get_fecparam(struct net_device *netdev, |
1353 | struct ethtool_fecparam *fecparam) | |
1354 | { | |
1355 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1356 | struct mlx5_core_dev *mdev = priv->mdev; | |
1357 | u8 fec_configured = 0; | |
1358 | u32 fec_active = 0; | |
1359 | int err; | |
1360 | ||
1361 | err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured); | |
1362 | ||
1363 | if (err) | |
1364 | return err; | |
1365 | ||
1366 | fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active, | |
1367 | sizeof(u32) * BITS_PER_BYTE); | |
1368 | ||
1369 | if (!fecparam->active_fec) | |
1370 | return -EOPNOTSUPP; | |
1371 | ||
1372 | fecparam->fec = pplm2ethtool_fec((u_long)fec_configured, | |
1373 | sizeof(u8) * BITS_PER_BYTE); | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
1378 | static int mlx5e_set_fecparam(struct net_device *netdev, | |
1379 | struct ethtool_fecparam *fecparam) | |
1380 | { | |
1381 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1382 | struct mlx5_core_dev *mdev = priv->mdev; | |
1383 | u8 fec_policy = 0; | |
1384 | int mode; | |
1385 | int err; | |
1386 | ||
1387 | for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) { | |
1388 | if (!(pplm_fec_2_ethtool[mode] & fecparam->fec)) | |
1389 | continue; | |
1390 | fec_policy |= (1 << mode); | |
1391 | break; | |
1392 | } | |
1393 | ||
1394 | err = mlx5e_set_fec_mode(mdev, fec_policy); | |
1395 | ||
1396 | if (err) | |
1397 | return err; | |
1398 | ||
1399 | mlx5_toggle_port_link(mdev); | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | ||
79c48764 GP |
1404 | static u32 mlx5e_get_msglevel(struct net_device *dev) |
1405 | { | |
1406 | return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel; | |
1407 | } | |
1408 | ||
1409 | static void mlx5e_set_msglevel(struct net_device *dev, u32 val) | |
1410 | { | |
1411 | ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val; | |
1412 | } | |
1413 | ||
da54d24e GP |
1414 | static int mlx5e_set_phys_id(struct net_device *dev, |
1415 | enum ethtool_phys_id_state state) | |
1416 | { | |
1417 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1418 | struct mlx5_core_dev *mdev = priv->mdev; | |
1419 | u16 beacon_duration; | |
1420 | ||
1421 | if (!MLX5_CAP_GEN(mdev, beacon_led)) | |
1422 | return -EOPNOTSUPP; | |
1423 | ||
1424 | switch (state) { | |
1425 | case ETHTOOL_ID_ACTIVE: | |
1426 | beacon_duration = MLX5_BEACON_DURATION_INF; | |
1427 | break; | |
1428 | case ETHTOOL_ID_INACTIVE: | |
1429 | beacon_duration = MLX5_BEACON_DURATION_OFF; | |
1430 | break; | |
1431 | default: | |
1432 | return -EOPNOTSUPP; | |
1433 | } | |
1434 | ||
1435 | return mlx5_set_port_beacon(mdev, beacon_duration); | |
1436 | } | |
1437 | ||
bb64143e GP |
1438 | static int mlx5e_get_module_info(struct net_device *netdev, |
1439 | struct ethtool_modinfo *modinfo) | |
1440 | { | |
1441 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1442 | struct mlx5_core_dev *dev = priv->mdev; | |
1443 | int size_read = 0; | |
1444 | u8 data[4]; | |
1445 | ||
1446 | size_read = mlx5_query_module_eeprom(dev, 0, 2, data); | |
1447 | if (size_read < 2) | |
1448 | return -EIO; | |
1449 | ||
1450 | /* data[0] = identifier byte */ | |
1451 | switch (data[0]) { | |
1452 | case MLX5_MODULE_ID_QSFP: | |
1453 | modinfo->type = ETH_MODULE_SFF_8436; | |
1454 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1455 | break; | |
1456 | case MLX5_MODULE_ID_QSFP_PLUS: | |
1457 | case MLX5_MODULE_ID_QSFP28: | |
1458 | /* data[1] = revision id */ | |
1459 | if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) { | |
1460 | modinfo->type = ETH_MODULE_SFF_8636; | |
1461 | modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; | |
1462 | } else { | |
1463 | modinfo->type = ETH_MODULE_SFF_8436; | |
1464 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1465 | } | |
1466 | break; | |
1467 | case MLX5_MODULE_ID_SFP: | |
1468 | modinfo->type = ETH_MODULE_SFF_8472; | |
1469 | modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; | |
1470 | break; | |
1471 | default: | |
1472 | netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n", | |
1473 | __func__, data[0]); | |
1474 | return -EINVAL; | |
1475 | } | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | static int mlx5e_get_module_eeprom(struct net_device *netdev, | |
1481 | struct ethtool_eeprom *ee, | |
1482 | u8 *data) | |
1483 | { | |
1484 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1485 | struct mlx5_core_dev *mdev = priv->mdev; | |
1486 | int offset = ee->offset; | |
1487 | int size_read; | |
1488 | int i = 0; | |
1489 | ||
1490 | if (!ee->len) | |
1491 | return -EINVAL; | |
1492 | ||
1493 | memset(data, 0, ee->len); | |
1494 | ||
1495 | while (i < ee->len) { | |
1496 | size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i, | |
1497 | data + i); | |
1498 | ||
1499 | if (!size_read) | |
1500 | /* Done reading */ | |
1501 | return 0; | |
1502 | ||
1503 | if (size_read < 0) { | |
1504 | netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n", | |
1505 | __func__, size_read); | |
1506 | return 0; | |
1507 | } | |
1508 | ||
1509 | i += size_read; | |
1510 | offset += size_read; | |
1511 | } | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
0088cbbc TG |
1516 | static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable, |
1517 | bool is_rx_cq) | |
4e59e288 | 1518 | { |
9908aa29 TT |
1519 | struct mlx5e_priv *priv = netdev_priv(netdev); |
1520 | struct mlx5_core_dev *mdev = priv->mdev; | |
be7e87f9 | 1521 | struct mlx5e_channels new_channels = {}; |
0088cbbc TG |
1522 | bool mode_changed; |
1523 | u8 cq_period_mode, current_cq_period_mode; | |
9908aa29 | 1524 | int err = 0; |
9908aa29 | 1525 | |
0088cbbc | 1526 | cq_period_mode = enable ? |
9908aa29 TT |
1527 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : |
1528 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
0088cbbc TG |
1529 | current_cq_period_mode = is_rx_cq ? |
1530 | priv->channels.params.rx_cq_moderation.cq_period_mode : | |
1531 | priv->channels.params.tx_cq_moderation.cq_period_mode; | |
1532 | mode_changed = cq_period_mode != current_cq_period_mode; | |
9908aa29 | 1533 | |
0088cbbc | 1534 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE && |
9908aa29 | 1535 | !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe)) |
9eb78923 | 1536 | return -EOPNOTSUPP; |
9908aa29 | 1537 | |
0088cbbc | 1538 | if (!mode_changed) |
9908aa29 TT |
1539 | return 0; |
1540 | ||
be7e87f9 | 1541 | new_channels.params = priv->channels.params; |
0088cbbc TG |
1542 | if (is_rx_cq) |
1543 | mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode); | |
1544 | else | |
1545 | mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode); | |
9908aa29 | 1546 | |
be7e87f9 SM |
1547 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
1548 | priv->channels.params = new_channels.params; | |
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | err = mlx5e_open_channels(priv, &new_channels); | |
1553 | if (err) | |
1554 | return err; | |
9908aa29 | 1555 | |
2e20a151 | 1556 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
be7e87f9 SM |
1557 | return 0; |
1558 | } | |
9908aa29 | 1559 | |
0088cbbc TG |
1560 | static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable) |
1561 | { | |
1562 | return set_pflag_cqe_based_moder(netdev, enable, false); | |
1563 | } | |
1564 | ||
1565 | static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable) | |
1566 | { | |
1567 | return set_pflag_cqe_based_moder(netdev, enable, true); | |
1568 | } | |
1569 | ||
be7e87f9 SM |
1570 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val) |
1571 | { | |
1572 | bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS); | |
1573 | struct mlx5e_channels new_channels = {}; | |
1574 | int err = 0; | |
1575 | ||
1576 | if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) | |
1577 | return new_val ? -EOPNOTSUPP : 0; | |
1578 | ||
1579 | if (curr_val == new_val) | |
1580 | return 0; | |
1581 | ||
1582 | new_channels.params = priv->channels.params; | |
1583 | MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val); | |
1584 | ||
be7e87f9 SM |
1585 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
1586 | priv->channels.params = new_channels.params; | |
1587 | return 0; | |
1588 | } | |
1589 | ||
1590 | err = mlx5e_open_channels(priv, &new_channels); | |
1591 | if (err) | |
1592 | return err; | |
1593 | ||
2e20a151 | 1594 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
696a97cf EE |
1595 | mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n", |
1596 | MLX5E_GET_PFLAG(&priv->channels.params, | |
1597 | MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF"); | |
1598 | ||
be7e87f9 | 1599 | return 0; |
4e59e288 GP |
1600 | } |
1601 | ||
9bcc8606 SD |
1602 | static int set_pflag_rx_cqe_compress(struct net_device *netdev, |
1603 | bool enable) | |
1604 | { | |
1605 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1606 | struct mlx5_core_dev *mdev = priv->mdev; | |
9bcc8606 SD |
1607 | |
1608 | if (!MLX5_CAP_GEN(mdev, cqe_compression)) | |
9eb78923 | 1609 | return -EOPNOTSUPP; |
9bcc8606 | 1610 | |
7c39afb3 | 1611 | if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) { |
9bcc8606 SD |
1612 | netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n"); |
1613 | return -EINVAL; | |
1614 | } | |
1615 | ||
5eb0249b | 1616 | mlx5e_modify_rx_cqe_compression_locked(priv, enable); |
6a9764ef | 1617 | priv->channels.params.rx_cqe_compress_def = enable; |
9bcc8606 | 1618 | |
5eb0249b | 1619 | return 0; |
9bcc8606 SD |
1620 | } |
1621 | ||
2ccb0a79 TT |
1622 | static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable) |
1623 | { | |
1624 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1625 | struct mlx5_core_dev *mdev = priv->mdev; | |
1626 | struct mlx5e_channels new_channels = {}; | |
1627 | int err; | |
1628 | ||
1629 | if (enable) { | |
1630 | if (!mlx5e_check_fragmented_striding_rq_cap(mdev)) | |
1631 | return -EOPNOTSUPP; | |
1632 | if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params)) | |
1633 | return -EINVAL; | |
6c3a823e TT |
1634 | } else if (priv->channels.params.lro_en) { |
1635 | netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n"); | |
1636 | return -EINVAL; | |
2ccb0a79 TT |
1637 | } |
1638 | ||
1639 | new_channels.params = priv->channels.params; | |
1640 | ||
1641 | MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable); | |
1642 | mlx5e_set_rq_type(mdev, &new_channels.params); | |
1643 | ||
1644 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
1645 | priv->channels.params = new_channels.params; | |
1646 | return 0; | |
1647 | } | |
1648 | ||
1649 | err = mlx5e_open_channels(priv, &new_channels); | |
1650 | if (err) | |
1651 | return err; | |
1652 | ||
1653 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); | |
1654 | return 0; | |
1655 | } | |
1656 | ||
b856df28 OG |
1657 | static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable) |
1658 | { | |
1659 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1660 | struct mlx5e_channels *channels = &priv->channels; | |
1661 | struct mlx5e_channel *c; | |
1662 | int i; | |
1663 | ||
1664 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1665 | return 0; | |
1666 | ||
1667 | for (i = 0; i < channels->num; i++) { | |
1668 | c = channels->c[i]; | |
1669 | if (enable) | |
1670 | __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); | |
1671 | else | |
1672 | __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); | |
1673 | } | |
1674 | ||
1675 | return 0; | |
1676 | } | |
1677 | ||
6277053a TT |
1678 | static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable) |
1679 | { | |
1680 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1681 | struct mlx5_core_dev *mdev = priv->mdev; | |
1682 | struct mlx5e_channels new_channels = {}; | |
1683 | int err; | |
1684 | ||
1685 | if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) | |
1686 | return -EOPNOTSUPP; | |
1687 | ||
1688 | new_channels.params = priv->channels.params; | |
1689 | ||
1690 | MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable); | |
1691 | ||
1692 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
1693 | priv->channels.params = new_channels.params; | |
1694 | return 0; | |
1695 | } | |
1696 | ||
1697 | err = mlx5e_open_channels(priv, &new_channels); | |
1698 | if (err) | |
1699 | return err; | |
1700 | ||
1701 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); | |
1702 | return 0; | |
1703 | } | |
1704 | ||
8ff57c18 TT |
1705 | static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = { |
1706 | { "rx_cqe_moder", set_pflag_rx_cqe_based_moder }, | |
1707 | { "tx_cqe_moder", set_pflag_tx_cqe_based_moder }, | |
1708 | { "rx_cqe_compress", set_pflag_rx_cqe_compress }, | |
1709 | { "rx_striding_rq", set_pflag_rx_striding_rq }, | |
1710 | { "rx_no_csum_complete", set_pflag_rx_no_csum_complete }, | |
6277053a | 1711 | { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe }, |
8ff57c18 TT |
1712 | }; |
1713 | ||
4e59e288 GP |
1714 | static int mlx5e_handle_pflag(struct net_device *netdev, |
1715 | u32 wanted_flags, | |
8ff57c18 | 1716 | enum mlx5e_priv_flag flag) |
4e59e288 GP |
1717 | { |
1718 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
8ff57c18 | 1719 | bool enable = !!(wanted_flags & BIT(flag)); |
6a9764ef | 1720 | u32 changes = wanted_flags ^ priv->channels.params.pflags; |
4e59e288 GP |
1721 | int err; |
1722 | ||
8ff57c18 | 1723 | if (!(changes & BIT(flag))) |
4e59e288 GP |
1724 | return 0; |
1725 | ||
8ff57c18 | 1726 | err = mlx5e_priv_flags[flag].handler(netdev, enable); |
4e59e288 | 1727 | if (err) { |
8ff57c18 TT |
1728 | netdev_err(netdev, "%s private flag '%s' failed err %d\n", |
1729 | enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err); | |
4e59e288 GP |
1730 | return err; |
1731 | } | |
1732 | ||
6a9764ef | 1733 | MLX5E_SET_PFLAG(&priv->channels.params, flag, enable); |
4e59e288 GP |
1734 | return 0; |
1735 | } | |
1736 | ||
1737 | static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags) | |
1738 | { | |
1739 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
8ff57c18 | 1740 | enum mlx5e_priv_flag pflag; |
4e59e288 GP |
1741 | int err; |
1742 | ||
1743 | mutex_lock(&priv->state_lock); | |
2ccb0a79 | 1744 | |
8ff57c18 TT |
1745 | for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) { |
1746 | err = mlx5e_handle_pflag(netdev, pflags, pflag); | |
1747 | if (err) | |
1748 | break; | |
1749 | } | |
9bcc8606 | 1750 | |
4e59e288 | 1751 | mutex_unlock(&priv->state_lock); |
6c3a823e TT |
1752 | |
1753 | /* Need to fix some features.. */ | |
1754 | netdev_update_features(netdev); | |
1755 | ||
9bcc8606 | 1756 | return err; |
4e59e288 GP |
1757 | } |
1758 | ||
1759 | static u32 mlx5e_get_priv_flags(struct net_device *netdev) | |
1760 | { | |
1761 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1762 | ||
6a9764ef | 1763 | return priv->channels.params.pflags; |
4e59e288 GP |
1764 | } |
1765 | ||
3ffaabec OG |
1766 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1767 | struct ethtool_flash *flash) | |
1768 | { | |
1769 | struct mlx5_core_dev *mdev = priv->mdev; | |
1770 | struct net_device *dev = priv->netdev; | |
1771 | const struct firmware *fw; | |
1772 | int err; | |
1773 | ||
1774 | if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) | |
1775 | return -EOPNOTSUPP; | |
1776 | ||
1777 | err = request_firmware_direct(&fw, flash->data, &dev->dev); | |
1778 | if (err) | |
1779 | return err; | |
1780 | ||
1781 | dev_hold(dev); | |
1782 | rtnl_unlock(); | |
1783 | ||
1784 | err = mlx5_firmware_flash(mdev, fw); | |
1785 | release_firmware(fw); | |
1786 | ||
1787 | rtnl_lock(); | |
1788 | dev_put(dev); | |
1789 | return err; | |
1790 | } | |
1791 | ||
1792 | static int mlx5e_flash_device(struct net_device *dev, | |
1793 | struct ethtool_flash *flash) | |
1794 | { | |
1795 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1796 | ||
1797 | return mlx5e_ethtool_flash_device(priv, flash); | |
1798 | } | |
1799 | ||
f62b8bb8 AV |
1800 | const struct ethtool_ops mlx5e_ethtool_ops = { |
1801 | .get_drvinfo = mlx5e_get_drvinfo, | |
1802 | .get_link = ethtool_op_get_link, | |
1803 | .get_strings = mlx5e_get_strings, | |
1804 | .get_sset_count = mlx5e_get_sset_count, | |
1805 | .get_ethtool_stats = mlx5e_get_ethtool_stats, | |
1806 | .get_ringparam = mlx5e_get_ringparam, | |
1807 | .set_ringparam = mlx5e_set_ringparam, | |
1808 | .get_channels = mlx5e_get_channels, | |
1809 | .set_channels = mlx5e_set_channels, | |
1810 | .get_coalesce = mlx5e_get_coalesce, | |
1811 | .set_coalesce = mlx5e_set_coalesce, | |
665bc539 GP |
1812 | .get_link_ksettings = mlx5e_get_link_ksettings, |
1813 | .set_link_ksettings = mlx5e_set_link_ksettings, | |
2d75b2bc AS |
1814 | .get_rxfh_key_size = mlx5e_get_rxfh_key_size, |
1815 | .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size, | |
2be6967c SM |
1816 | .get_rxfh = mlx5e_get_rxfh, |
1817 | .set_rxfh = mlx5e_set_rxfh, | |
fe6d86b3 | 1818 | #ifdef CONFIG_MLX5_EN_RXNFC |
2d75b2bc | 1819 | .get_rxnfc = mlx5e_get_rxnfc, |
6dc6071c | 1820 | .set_rxnfc = mlx5e_set_rxnfc, |
fe6d86b3 | 1821 | #endif |
3ffaabec | 1822 | .flash_device = mlx5e_flash_device, |
58d52291 AS |
1823 | .get_tunable = mlx5e_get_tunable, |
1824 | .set_tunable = mlx5e_set_tunable, | |
3c2d18ef AS |
1825 | .get_pauseparam = mlx5e_get_pauseparam, |
1826 | .set_pauseparam = mlx5e_set_pauseparam, | |
ef9814de | 1827 | .get_ts_info = mlx5e_get_ts_info, |
da54d24e | 1828 | .set_phys_id = mlx5e_set_phys_id, |
928cfe87 TT |
1829 | .get_wol = mlx5e_get_wol, |
1830 | .set_wol = mlx5e_set_wol, | |
bb64143e GP |
1831 | .get_module_info = mlx5e_get_module_info, |
1832 | .get_module_eeprom = mlx5e_get_module_eeprom, | |
4e59e288 | 1833 | .get_priv_flags = mlx5e_get_priv_flags, |
d605d668 KH |
1834 | .set_priv_flags = mlx5e_set_priv_flags, |
1835 | .self_test = mlx5e_self_test, | |
79c48764 GP |
1836 | .get_msglevel = mlx5e_get_msglevel, |
1837 | .set_msglevel = mlx5e_set_msglevel, | |
6cfa9460 SA |
1838 | .get_fecparam = mlx5e_get_fecparam, |
1839 | .set_fecparam = mlx5e_set_fecparam, | |
f62b8bb8 | 1840 | }; |