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net/mlx5e: Change FW sub_minor display to 4 zeros padding
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
34
35static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
37{
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
40
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
6543b78e 45 "%d.%d.%04d",
f62b8bb8
AV		 46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
49}
50
665bc539
GP		 51struct ptys2ethtool_config {
52 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
53 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8 54 u32 speed;
f62b8bb8
AV		 55};
56
665bc539
GP		 57static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
58
59#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
60 ({ \
61 struct ptys2ethtool_config *cfg; \
62 const unsigned int modes[] = { __VA_ARGS__ }; \
63 unsigned int i; \
64 cfg = &ptys2ethtool_table[reg_]; \
65 cfg->speed = speed_; \
66 bitmap_zero(cfg->supported, \
67 __ETHTOOL_LINK_MODE_MASK_NBITS); \
68 bitmap_zero(cfg->advertised, \
69 __ETHTOOL_LINK_MODE_MASK_NBITS); \
70 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
71 __set_bit(modes[i], cfg->supported); \
72 __set_bit(modes[i], cfg->advertised); \
73 } \
74 })
75
76void mlx5e_build_ptys2ethtool_map(void)
77{
78 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
79 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
80 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
81 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
82 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
83 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
84 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
85 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
87 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
89 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
91 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
93 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
95 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
97 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
99 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
101 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
103 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
105 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
107 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
109 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
111 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
113 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
115 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
117 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
119 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
121 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
123 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
125 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
127 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
128}
129
cf678570
GP		 130static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
131{
132 struct mlx5_core_dev *mdev = priv->mdev;
133 u8 pfc_en_tx;
134 u8 pfc_en_rx;
135 int err;
136
137 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
138
139 return err ? 0 : pfc_en_tx | pfc_en_rx;
140}
141
e989d5a5
GP		 142static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
143{
144 struct mlx5_core_dev *mdev = priv->mdev;
145 u32 rx_pause;
146 u32 tx_pause;
147 int err;
148
149 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
150
151 return err ? false : rx_pause | tx_pause;
152}
153
593cf338 154#define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
ff9c852f 155#define MLX5E_NUM_RQ_STATS(priv) (NUM_RQ_STATS * (priv)->channels.num)
9218b44d 156#define MLX5E_NUM_SQ_STATS(priv) \
6a9764ef 157 (NUM_SQ_STATS * (priv)->channels.num * (priv)->channels.params.num_tc)
ed80ec4c 158#define MLX5E_NUM_PFC_COUNTERS(priv) \
e989d5a5
GP		 159 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
160 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
593cf338 161
f62b8bb8
AV		 162static int mlx5e_get_sset_count(struct net_device *dev, int sset)
163{
164 struct mlx5e_priv *priv = netdev_priv(dev);
165
166 switch (sset) {
167 case ETH_SS_STATS:
9218b44d 168 return NUM_SW_COUNTERS +
593cf338 169 MLX5E_NUM_Q_CNTRS(priv) +
5db0a4f6 170 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS(priv) +
0f7f3481 171 NUM_PCIE_COUNTERS(priv) +
9218b44d 172 MLX5E_NUM_RQ_STATS(priv) +
cf678570 173 MLX5E_NUM_SQ_STATS(priv) +
bedb7c90
HN		 174 MLX5E_NUM_PFC_COUNTERS(priv) +
175 ARRAY_SIZE(mlx5e_pme_status_desc) +
176 ARRAY_SIZE(mlx5e_pme_error_desc);
177
4e59e288
GP		 178 case ETH_SS_PRIV_FLAGS:
179 return ARRAY_SIZE(mlx5e_priv_flags);
d605d668
KH		 180 case ETH_SS_TEST:
181 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 182 /* fallthrough */
183 default:
184 return -EOPNOTSUPP;
185 }
186}
187
9218b44d
GP		 188static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
189{
cf678570
GP		 190 int i, j, tc, prio, idx = 0;
191 unsigned long pfc_combined;
9218b44d
GP		 192
193 /* SW counters */
194 for (i = 0; i < NUM_SW_COUNTERS; i++)
bfe6d8d1 195 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
9218b44d
GP		 196
197 /* Q counters */
198 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
bfe6d8d1 199 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
9218b44d
GP		 200
201 /* VPORT counters */
202 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
203 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 204 vport_stats_desc[i].format);
9218b44d
GP		 205
206 /* PPORT counters */
207 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
208 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 209 pport_802_3_stats_desc[i].format);
9218b44d
GP		 210
211 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
212 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 213 pport_2863_stats_desc[i].format);
9218b44d
GP		 214
215 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
216 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 217 pport_2819_stats_desc[i].format);
9218b44d 218
5db0a4f6
GP		 219 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
220 strcpy(data + (idx++) * ETH_GSTRING_LEN,
221 pport_phy_statistical_stats_desc[i].format);
222
0f7f3481
GP		 223 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
224 strcpy(data + (idx++) * ETH_GSTRING_LEN,
225 pcie_perf_stats_desc[i].format);
226
cf678570
GP		 227 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
228 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
bfe6d8d1
GP		 229 sprintf(data + (idx++) * ETH_GSTRING_LEN,
230 pport_per_prio_traffic_stats_desc[i].format, prio);
cf678570
GP		 231 }
232
233 pfc_combined = mlx5e_query_pfc_combined(priv);
234 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
235 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
e989d5a5
GP		 236 char pfc_string[ETH_GSTRING_LEN];
237
238 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
bfe6d8d1 239 sprintf(data + (idx++) * ETH_GSTRING_LEN,
e989d5a5
GP		 240 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
241 }
242 }
243
244 if (mlx5e_query_global_pause_combined(priv)) {
245 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
246 sprintf(data + (idx++) * ETH_GSTRING_LEN,
247 pport_per_prio_pfc_stats_desc[i].format, "global");
cf678570
GP		 248 }
249 }
250
bedb7c90
HN		 251 /* port module event counters */
252 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
253 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
254
255 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
256 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
257
9218b44d
GP		 258 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
259 return;
260
261 /* per channel counters */
ff9c852f 262 for (i = 0; i < priv->channels.num; i++)
9218b44d 263 for (j = 0; j < NUM_RQ_STATS; j++)
bfe6d8d1
GP		 264 sprintf(data + (idx++) * ETH_GSTRING_LEN,
265 rq_stats_desc[j].format, i);
9218b44d 266
6a9764ef 267 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 268 for (i = 0; i < priv->channels.num; i++)
9218b44d
GP		 269 for (j = 0; j < NUM_SQ_STATS; j++)
270 sprintf(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 271 sq_stats_desc[j].format,
acc6c595 272 priv->channel_tc2txq[i][tc]);
9218b44d
GP		 273}
274
f62b8bb8
AV		 275static void mlx5e_get_strings(struct net_device *dev,
276 uint32_t stringset, uint8_t *data)
277{
f62b8bb8 278 struct mlx5e_priv *priv = netdev_priv(dev);
4e59e288 279 int i;
f62b8bb8
AV		 280
281 switch (stringset) {
282 case ETH_SS_PRIV_FLAGS:
4e59e288
GP		 283 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
284 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
f62b8bb8
AV		 285 break;
286
287 case ETH_SS_TEST:
d605d668
KH		 288 for (i = 0; i < mlx5e_self_test_num(priv); i++)
289 strcpy(data + i * ETH_GSTRING_LEN,
290 mlx5e_self_tests[i]);
f62b8bb8
AV		 291 break;
292
293 case ETH_SS_STATS:
9218b44d 294 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 295 break;
296 }
297}
298
299static void mlx5e_get_ethtool_stats(struct net_device *dev,
300 struct ethtool_stats *stats, u64 *data)
301{
302 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f 303 struct mlx5e_channels *channels;
bedb7c90 304 struct mlx5_priv *mlx5_priv;
cf678570
GP		 305 int i, j, tc, prio, idx = 0;
306 unsigned long pfc_combined;
f62b8bb8
AV		 307
308 if (!data)
309 return;
310
311 mutex_lock(&priv->state_lock);
312 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
313 mlx5e_update_stats(priv);
ff9c852f 314 channels = &priv->channels;
f62b8bb8
AV		 315 mutex_unlock(&priv->state_lock);
316
9218b44d
GP		 317 for (i = 0; i < NUM_SW_COUNTERS; i++)
318 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
319 sw_stats_desc, i);
f62b8bb8 320
593cf338 321 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
9218b44d
GP		 322 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
323 q_stats_desc, i);
324
325 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
326 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
327 vport_stats_desc, i);
593cf338 328
9218b44d
GP		 329 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
330 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
331 pport_802_3_stats_desc, i);
332
333 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
334 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
335 pport_2863_stats_desc, i);
336
337 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
338 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
339 pport_2819_stats_desc, i);
340
5db0a4f6
GP		 341 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
342 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
343 pport_phy_statistical_stats_desc, i);
344
0f7f3481
GP		 345 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
346 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
347 pcie_perf_stats_desc, i);
348
cf678570
GP		 349 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
350 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
351 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
352 pport_per_prio_traffic_stats_desc, i);
353 }
354
355 pfc_combined = mlx5e_query_pfc_combined(priv);
356 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
357 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
358 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
359 pport_per_prio_pfc_stats_desc, i);
360 }
361 }
362
e989d5a5
GP		 363 if (mlx5e_query_global_pause_combined(priv)) {
364 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
365 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
4e39883d 366 pport_per_prio_pfc_stats_desc, i);
e989d5a5
GP		 367 }
368 }
369
bedb7c90
HN		 370 /* port module event counters */
371 mlx5_priv = &priv->mdev->priv;
372 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
373 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
374 mlx5e_pme_status_desc, i);
375
376 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
377 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
378 mlx5e_pme_error_desc, i);
379
9218b44d
GP		 380 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
381 return;
efea389d 382
f62b8bb8 383 /* per channel counters */
ff9c852f 384 for (i = 0; i < channels->num; i++)
f62b8bb8 385 for (j = 0; j < NUM_RQ_STATS; j++)
9218b44d 386 data[idx++] =
ff9c852f 387 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
9218b44d 388 rq_stats_desc, j);
f62b8bb8 389
6a9764ef 390 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 391 for (i = 0; i < channels->num; i++)
f62b8bb8 392 for (j = 0; j < NUM_SQ_STATS; j++)
ff9c852f 393 data[idx++] = MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
9218b44d 394 sq_stats_desc, j);
f62b8bb8
AV		 395}
396
cc8e9ebf
EBE		 397static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
398 int num_wqe)
399{
400 int packets_per_wqe;
401 int stride_size;
402 int num_strides;
403 int wqe_size;
404
405 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
406 return num_wqe;
407
6a9764ef
SM		 408 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
409 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 410 wqe_size = stride_size * num_strides;
411
412 packets_per_wqe = wqe_size /
413 ALIGN(ETH_DATA_LEN, stride_size);
414 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
415}
416
417static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
418 int num_packets)
419{
420 int packets_per_wqe;
421 int stride_size;
422 int num_strides;
423 int wqe_size;
424 int num_wqes;
425
426 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
427 return num_packets;
428
6a9764ef
SM		 429 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
430 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 431 wqe_size = stride_size * num_strides;
432
433 num_packets = (1 << order_base_2(num_packets));
434
435 packets_per_wqe = wqe_size /
436 ALIGN(ETH_DATA_LEN, stride_size);
437 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
438 return 1 << (order_base_2(num_wqes));
439}
440
f62b8bb8
AV		 441static void mlx5e_get_ringparam(struct net_device *dev,
442 struct ethtool_ringparam *param)
443{
444 struct mlx5e_priv *priv = netdev_priv(dev);
6a9764ef 445 int rq_wq_type = priv->channels.params.rq_wq_type;
f62b8bb8 446
cc8e9ebf
EBE		 447 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
448 1 << mlx5_max_log_rq_size(rq_wq_type));
f62b8bb8 449 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
cc8e9ebf 450 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
6a9764ef
SM		 451 1 << priv->channels.params.log_rq_size);
452 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 453}
454
455static int mlx5e_set_ringparam(struct net_device *dev,
456 struct ethtool_ringparam *param)
457{
458 struct mlx5e_priv *priv = netdev_priv(dev);
6a9764ef 459 int rq_wq_type = priv->channels.params.rq_wq_type;
546f18ed 460 struct mlx5e_channels new_channels = {};
cc8e9ebf
EBE		 461 u32 rx_pending_wqes;
462 u32 min_rq_size;
463 u32 max_rq_size;
f62b8bb8
AV		 464 u8 log_rq_size;
465 u8 log_sq_size;
fe4c988b 466 u32 num_mtts;
f62b8bb8
AV		 467 int err = 0;
468
469 if (param->rx_jumbo_pending) {
470 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
471 __func__);
472 return -EINVAL;
473 }
474 if (param->rx_mini_pending) {
475 netdev_info(dev, "%s: rx_mini_pending not supported\n",
476 __func__);
477 return -EINVAL;
478 }
cc8e9ebf
EBE		 479
480 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
481 1 << mlx5_min_log_rq_size(rq_wq_type));
482 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
483 1 << mlx5_max_log_rq_size(rq_wq_type));
484 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
485 param->rx_pending);
486
487 if (param->rx_pending < min_rq_size) {
f62b8bb8
AV		 488 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
489 __func__, param->rx_pending,
cc8e9ebf 490 min_rq_size);
f62b8bb8
AV		 491 return -EINVAL;
492 }
cc8e9ebf 493 if (param->rx_pending > max_rq_size) {
f62b8bb8
AV		 494 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
495 __func__, param->rx_pending,
cc8e9ebf 496 max_rq_size);
f62b8bb8
AV		 497 return -EINVAL;
498 }
fe4c988b 499
ec8b9981 500 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
6a9764ef 501 if (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
fe4c988b
SM		 502 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
503 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
504 __func__, param->rx_pending);
505 return -EINVAL;
506 }
507
f62b8bb8
AV		 508 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
509 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
510 __func__, param->tx_pending,
511 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
512 return -EINVAL;
513 }
514 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
515 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
516 __func__, param->tx_pending,
517 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
518 return -EINVAL;
519 }
520
cc8e9ebf 521 log_rq_size = order_base_2(rx_pending_wqes);
f62b8bb8 522 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 523
6a9764ef
SM		 524 if (log_rq_size == priv->channels.params.log_rq_size &&
525 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 526 return 0;
527
528 mutex_lock(&priv->state_lock);
98e81b0a 529
546f18ed
SM		 530 new_channels.params = priv->channels.params;
531 new_channels.params.log_rq_size = log_rq_size;
532 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 533
546f18ed
SM		 534 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
535 priv->channels.params = new_channels.params;
536 goto unlock;
537 }
98e81b0a 538
546f18ed
SM		 539 err = mlx5e_open_channels(priv, &new_channels);
540 if (err)
541 goto unlock;
542
2e20a151 543 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 544
546f18ed 545unlock:
f62b8bb8
AV		 546 mutex_unlock(&priv->state_lock);
547
548 return err;
549}
550
551static void mlx5e_get_channels(struct net_device *dev,
552 struct ethtool_channels *ch)
553{
554 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 555
b4e029da 556 ch->max_combined = priv->profile->max_nch(priv->mdev);
6a9764ef 557 ch->combined_count = priv->channels.params.num_channels;
f62b8bb8
AV		 558}
559
560static int mlx5e_set_channels(struct net_device *dev,
561 struct ethtool_channels *ch)
562{
563 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 564 unsigned int count = ch->combined_count;
55c2503d 565 struct mlx5e_channels new_channels = {};
45bf454a 566 bool arfs_enabled;
f62b8bb8
AV		 567 int err = 0;
568
569 if (!count) {
570 netdev_info(dev, "%s: combined_count=0 not supported\n",
571 __func__);
572 return -EINVAL;
573 }
f62b8bb8 574
6a9764ef 575 if (priv->channels.params.num_channels == count)
f62b8bb8
AV		 576 return 0;
577
578 mutex_lock(&priv->state_lock);
98e81b0a 579
55c2503d
SM		 580 new_channels.params = priv->channels.params;
581 new_channels.params.num_channels = count;
582 mlx5e_build_default_indir_rqt(priv->mdev, new_channels.params.indirection_rqt,
583 MLX5E_INDIR_RQT_SIZE, count);
584
585 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
586 priv->channels.params = new_channels.params;
587 goto out;
588 }
589
590 /* Create fresh channels with new parameters */
591 err = mlx5e_open_channels(priv, &new_channels);
592 if (err)
593 goto out;
98e81b0a 594
45bf454a
MG		 595 arfs_enabled = dev->features & NETIF_F_NTUPLE;
596 if (arfs_enabled)
597 mlx5e_arfs_disable(priv);
598
55c2503d 599 /* Switch to new channels, set new parameters and close old ones */
2e20a151 600 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
45bf454a
MG		 601
602 if (arfs_enabled) {
603 err = mlx5e_arfs_enable(priv);
604 if (err)
605 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
606 __func__, err);
607 }
98e81b0a 608
45bf454a 609out:
f62b8bb8
AV		 610 mutex_unlock(&priv->state_lock);
611
612 return err;
613}
614
615static int mlx5e_get_coalesce(struct net_device *netdev,
616 struct ethtool_coalesce *coal)
617{
618 struct mlx5e_priv *priv = netdev_priv(netdev);
619
7524a5d8 620 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 621 return -EOPNOTSUPP;
7524a5d8 622
6a9764ef
SM		 623 coal->rx_coalesce_usecs = priv->channels.params.rx_cq_moderation.usec;
624 coal->rx_max_coalesced_frames = priv->channels.params.rx_cq_moderation.pkts;
625 coal->tx_coalesce_usecs = priv->channels.params.tx_cq_moderation.usec;
626 coal->tx_max_coalesced_frames = priv->channels.params.tx_cq_moderation.pkts;
627 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_am_enabled;
f62b8bb8
AV		 628
629 return 0;
630}
631
546f18ed
SM		 632static void
633mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 634{
f62b8bb8 635 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 636 int tc;
637 int i;
638
ff9c852f
SM		 639 for (i = 0; i < priv->channels.num; ++i) {
640 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 641
642 for (tc = 0; tc < c->num_tc; tc++) {
643 mlx5_core_modify_cq_moderation(mdev,
644 &c->sq[tc].cq.mcq,
645 coal->tx_coalesce_usecs,
646 coal->tx_max_coalesced_frames);
647 }
648
649 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
650 coal->rx_coalesce_usecs,
651 coal->rx_max_coalesced_frames);
652 }
546f18ed 653}
f62b8bb8 654
546f18ed
SM		 655static int mlx5e_set_coalesce(struct net_device *netdev,
656 struct ethtool_coalesce *coal)
657{
658 struct mlx5e_priv *priv = netdev_priv(netdev);
659 struct mlx5_core_dev *mdev = priv->mdev;
660 struct mlx5e_channels new_channels = {};
661 int err = 0;
662 bool reset;
cb3c7fd4 663
546f18ed
SM		 664 if (!MLX5_CAP_GEN(mdev, cq_moderation))
665 return -EOPNOTSUPP;
666
667 mutex_lock(&priv->state_lock);
668 new_channels.params = priv->channels.params;
669
670 new_channels.params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
671 new_channels.params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
672 new_channels.params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
673 new_channels.params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
674 new_channels.params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
675
676 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
677 priv->channels.params = new_channels.params;
678 goto out;
679 }
680 /* we are opened */
681
682 reset = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_am_enabled;
683 if (!reset) {
684 mlx5e_set_priv_channels_coalesce(priv, coal);
685 priv->channels.params = new_channels.params;
686 goto out;
687 }
688
689 /* open fresh channels with new coal parameters */
690 err = mlx5e_open_channels(priv, &new_channels);
691 if (err)
692 goto out;
693
2e20a151 694 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
546f18ed
SM		 695
696out:
2fcb92fb 697 mutex_unlock(&priv->state_lock);
cb3c7fd4 698 return err;
f62b8bb8
AV		 699}
700
665bc539
GP		 701static void ptys2ethtool_supported_link(unsigned long *supported_modes,
702 u32 eth_proto_cap)
f62b8bb8 703{
7abc2110 704 unsigned long proto_cap = eth_proto_cap;
665bc539 705 int proto;
f62b8bb8 706
7abc2110 707 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 708 bitmap_or(supported_modes, supported_modes,
709 ptys2ethtool_table[proto].supported,
710 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 711}
712
665bc539
GP		 713static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
714 u32 eth_proto_cap)
f62b8bb8 715{
7abc2110 716 unsigned long proto_cap = eth_proto_cap;
665bc539 717 int proto;
f62b8bb8 718
7abc2110 719 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 720 bitmap_or(advertising_modes, advertising_modes,
721 ptys2ethtool_table[proto].advertised,
722 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 723}
724
665bc539
GP		 725static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
726 u32 eth_proto_cap)
f62b8bb8
AV		 727{
728 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
729 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
730 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
731 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
732 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
733 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
665bc539 734 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
f62b8bb8
AV		 735 }
736
737 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
738 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
739 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
740 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
741 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
665bc539 742 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
f62b8bb8 743 }
f62b8bb8
AV		 744}
745
b797a684
SM		 746int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
747{
748 u32 max_speed = 0;
749 u32 proto_cap;
750 int err;
751 int i;
752
753 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
754 if (err)
755 return err;
756
757 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
758 if (proto_cap & MLX5E_PROT_MASK(i))
759 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
760
761 *speed = max_speed;
762 return 0;
763}
764
f62b8bb8
AV		 765static void get_speed_duplex(struct net_device *netdev,
766 u32 eth_proto_oper,
665bc539 767 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 768{
769 int i;
770 u32 speed = SPEED_UNKNOWN;
771 u8 duplex = DUPLEX_UNKNOWN;
772
773 if (!netif_carrier_ok(netdev))
774 goto out;
775
776 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
777 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
778 speed = ptys2ethtool_table[i].speed;
779 duplex = DUPLEX_FULL;
780 break;
781 }
782 }
783out:
665bc539
GP		 784 link_ksettings->base.speed = speed;
785 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 786}
787
665bc539
GP		 788static void get_supported(u32 eth_proto_cap,
789 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 790{
665bc539
GP		 791 unsigned long *supported = link_ksettings->link_modes.supported;
792
793 ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
794 ptys2ethtool_supported_link(supported, eth_proto_cap);
795 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
796 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause);
f62b8bb8
AV		 797}
798
799static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
665bc539
GP		 800 u8 rx_pause,
801 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 802{
665bc539
GP		 803 unsigned long *advertising = link_ksettings->link_modes.advertising;
804
805 ptys2ethtool_adver_link(advertising, eth_proto_cap);
806 if (tx_pause)
807 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
808 if (tx_pause ^ rx_pause)
809 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 810}
811
812static u8 get_connector_port(u32 eth_proto)
813{
814 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
815 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
816 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
817 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
818 return PORT_FIBRE;
819 }
820
821 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
822 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
823 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
824 return PORT_DA;
825 }
826
827 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
828 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
829 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
830 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
831 return PORT_NONE;
832 }
833
834 return PORT_OTHER;
835}
836
665bc539
GP		 837static void get_lp_advertising(u32 eth_proto_lp,
838 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 839{
665bc539
GP		 840 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
841
842 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
f62b8bb8
AV		 843}
844
665bc539
GP		 845static int mlx5e_get_link_ksettings(struct net_device *netdev,
846 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 847{
848 struct mlx5e_priv *priv = netdev_priv(netdev);
849 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 850 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
f62b8bb8
AV		 851 u32 eth_proto_cap;
852 u32 eth_proto_admin;
853 u32 eth_proto_lp;
854 u32 eth_proto_oper;
52244d96
GP		 855 u8 an_disable_admin;
856 u8 an_status;
f62b8bb8
AV		 857 int err;
858
a05bdefa 859 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV		 860 if (err) {
861 netdev_err(netdev, "%s: query port ptys failed: %d\n",
862 __func__, err);
863 goto err_query_ptys;
864 }
865
52244d96
GP		 866 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
867 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
868 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
869 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
870 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
871 an_status = MLX5_GET(ptys_reg, out, an_status);
f62b8bb8 872
665bc539
GP		 873 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
874 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 875
665bc539
GP		 876 get_supported(eth_proto_cap, link_ksettings);
877 get_advertising(eth_proto_admin, 0, 0, link_ksettings);
878 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 879
880 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
881
665bc539
GP		 882 link_ksettings->base.port = get_connector_port(eth_proto_oper);
883 get_lp_advertising(eth_proto_lp, link_ksettings);
f62b8bb8 884
52244d96
GP		 885 if (an_status == MLX5_AN_COMPLETE)
886 ethtool_link_ksettings_add_link_mode(link_ksettings,
887 lp_advertising, Autoneg);
888
889 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
890 AUTONEG_ENABLE;
891 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
892 Autoneg);
893 if (!an_disable_admin)
894 ethtool_link_ksettings_add_link_mode(link_ksettings,
895 advertising, Autoneg);
896
f62b8bb8
AV		 897err_query_ptys:
898 return err;
899}
900
665bc539 901static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 902{
903 u32 i, ptys_modes = 0;
904
905 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
665bc539
GP		 906 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
907 link_modes,
908 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 909 ptys_modes |= MLX5E_PROT_MASK(i);
910 }
911
912 return ptys_modes;
913}
914
915static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
916{
917 u32 i, speed_links = 0;
918
919 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
920 if (ptys2ethtool_table[i].speed == speed)
921 speed_links |= MLX5E_PROT_MASK(i);
922 }
923
924 return speed_links;
925}
926
665bc539
GP		 927static int mlx5e_set_link_ksettings(struct net_device *netdev,
928 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 929{
930 struct mlx5e_priv *priv = netdev_priv(netdev);
931 struct mlx5_core_dev *mdev = priv->mdev;
52244d96
GP		 932 u32 eth_proto_cap, eth_proto_admin;
933 bool an_changes = false;
934 u8 an_disable_admin;
935 u8 an_disable_cap;
936 bool an_disable;
f62b8bb8 937 u32 link_modes;
52244d96 938 u8 an_status;
f62b8bb8 939 u32 speed;
f62b8bb8
AV		 940 int err;
941
665bc539 942 speed = link_ksettings->base.speed;
f62b8bb8 943
665bc539
GP		 944 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
945 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
f62b8bb8
AV		 946 mlx5e_ethtool2ptys_speed_link(speed);
947
948 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
949 if (err) {
950 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
951 __func__, err);
952 goto out;
953 }
954
955 link_modes = link_modes & eth_proto_cap;
956 if (!link_modes) {
957 netdev_err(netdev, "%s: Not supported link mode(s) requested",
958 __func__);
959 err = -EINVAL;
960 goto out;
961 }
962
963 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
964 if (err) {
965 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
966 __func__, err);
967 goto out;
968 }
969
52244d96
GP		 970 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
971 &an_disable_cap, &an_disable_admin);
972
973 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
974 an_changes = ((!an_disable && an_disable_admin) ||
975 (an_disable && !an_disable_admin));
976
977 if (!an_changes && link_modes == eth_proto_admin)
f62b8bb8
AV		 978 goto out;
979
52244d96 980 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
667daeda 981 mlx5_toggle_port_link(mdev);
f62b8bb8 982
f62b8bb8
AV		 983out:
984 return err;
985}
986
2d75b2bc
AS		 987static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
988{
989 struct mlx5e_priv *priv = netdev_priv(netdev);
990
6a9764ef 991 return sizeof(priv->channels.params.toeplitz_hash_key);
2d75b2bc
AS		 992}
993
994static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
995{
996 return MLX5E_INDIR_RQT_SIZE;
997}
998
2be6967c
SM		 999static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1000 u8 *hfunc)
1001{
1002 struct mlx5e_priv *priv = netdev_priv(netdev);
1003
2d75b2bc 1004 if (indir)
6a9764ef
SM		 1005 memcpy(indir, priv->channels.params.indirection_rqt,
1006 sizeof(priv->channels.params.indirection_rqt));
2d75b2bc
AS		 1007
1008 if (key)
6a9764ef
SM		 1009 memcpy(key, priv->channels.params.toeplitz_hash_key,
1010 sizeof(priv->channels.params.toeplitz_hash_key));
2d75b2bc 1011
2be6967c 1012 if (hfunc)
6a9764ef 1013 *hfunc = priv->channels.params.rss_hfunc;
2be6967c
SM		 1014
1015 return 0;
1016}
1017
bdfc028d
TT		 1018static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
1019{
bdfc028d 1020 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
a100ff3e
GP		 1021 struct mlx5_core_dev *mdev = priv->mdev;
1022 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
1023 int tt;
bdfc028d
TT		 1024
1025 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
bdfc028d 1026
a100ff3e
GP		 1027 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1028 memset(tirc, 0, ctxlen);
6a9764ef 1029 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
a100ff3e
GP		 1030 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
1031 }
bdfc028d
TT		 1032}
1033
98e81b0a 1034static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 1035 const u8 *key, const u8 hfunc)
1036{
98e81b0a 1037 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d 1038 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1039 bool hash_changed = false;
bdfc028d 1040 void *in;
2be6967c 1041
2d75b2bc
AS		 1042 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1043 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1044 (hfunc != ETH_RSS_HASH_TOP))
1045 return -EINVAL;
1046
bdfc028d
TT		 1047 in = mlx5_vzalloc(inlen);
1048 if (!in)
1049 return -ENOMEM;
1050
2be6967c
SM		 1051 mutex_lock(&priv->state_lock);
1052
1d3398fa 1053 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
6a9764ef
SM		 1054 hfunc != priv->channels.params.rss_hfunc) {
1055 priv->channels.params.rss_hfunc = hfunc;
1d3398fa
GP		 1056 hash_changed = true;
1057 }
1058
a5f97fee 1059 if (indir) {
6a9764ef
SM		 1060 memcpy(priv->channels.params.indirection_rqt, indir,
1061 sizeof(priv->channels.params.indirection_rqt));
a5f97fee
SM		 1062
1063 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1064 u32 rqtn = priv->indir_rqt.rqtn;
1065 struct mlx5e_redirect_rqt_param rrp = {
1066 .is_rss = true,
e270e966
AM		 1067 {
1068 .rss = {
1069 .hfunc = priv->channels.params.rss_hfunc,
1070 .channels = &priv->channels,
1071 },
1072 },
a5f97fee
SM		 1073 };
1074
1075 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1076 }
1077 }
1078
1d3398fa 1079 if (key) {
6a9764ef
SM		 1080 memcpy(priv->channels.params.toeplitz_hash_key, key,
1081 sizeof(priv->channels.params.toeplitz_hash_key));
1d3398fa 1082 hash_changed = hash_changed ||
6a9764ef 1083 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1084 }
2d75b2bc 1085
1d3398fa
GP		 1086 if (hash_changed)
1087 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1088
2be6967c
SM		 1089 mutex_unlock(&priv->state_lock);
1090
bdfc028d
TT		 1091 kvfree(in);
1092
1093 return 0;
2be6967c
SM		 1094}
1095
2d75b2bc
AS		 1096static int mlx5e_get_rxnfc(struct net_device *netdev,
1097 struct ethtool_rxnfc *info, u32 *rule_locs)
1098{
1099 struct mlx5e_priv *priv = netdev_priv(netdev);
1100 int err = 0;
1101
1102 switch (info->cmd) {
1103 case ETHTOOL_GRXRINGS:
6a9764ef 1104 info->data = priv->channels.params.num_channels;
2d75b2bc 1105 break;
f913a72a
MG		 1106 case ETHTOOL_GRXCLSRLCNT:
1107 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1108 break;
1109 case ETHTOOL_GRXCLSRULE:
1110 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1111 break;
1112 case ETHTOOL_GRXCLSRLALL:
1113 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1114 break;
2d75b2bc
AS		 1115 default:
1116 err = -EOPNOTSUPP;
1117 break;
1118 }
1119
1120 return err;
1121}
1122
58d52291
AS		 1123static int mlx5e_get_tunable(struct net_device *dev,
1124 const struct ethtool_tunable *tuna,
1125 void *data)
1126{
1127 const struct mlx5e_priv *priv = netdev_priv(dev);
1128 int err = 0;
1129
1130 switch (tuna->id) {
1131 case ETHTOOL_TX_COPYBREAK:
6a9764ef 1132 *(u32 *)data = priv->channels.params.tx_max_inline;
58d52291
AS		 1133 break;
1134 default:
1135 err = -EINVAL;
1136 break;
1137 }
1138
1139 return err;
1140}
1141
1142static int mlx5e_set_tunable(struct net_device *dev,
1143 const struct ethtool_tunable *tuna,
1144 const void *data)
1145{
1146 struct mlx5e_priv *priv = netdev_priv(dev);
1147 struct mlx5_core_dev *mdev = priv->mdev;
546f18ed 1148 struct mlx5e_channels new_channels = {};
58d52291 1149 int err = 0;
546f18ed
SM		 1150 u32 val;
1151
1152 mutex_lock(&priv->state_lock);
58d52291
AS		 1153
1154 switch (tuna->id) {
1155 case ETHTOOL_TX_COPYBREAK:
1156 val = *(u32 *)data;
1157 if (val > mlx5e_get_max_inline_cap(mdev)) {
1158 err = -EINVAL;
1159 break;
1160 }
1161
546f18ed
SM		 1162 new_channels.params = priv->channels.params;
1163 new_channels.params.tx_max_inline = val;
98e81b0a 1164
546f18ed
SM		 1165 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1166 priv->channels.params = new_channels.params;
1167 break;
1168 }
98e81b0a 1169
546f18ed
SM		 1170 err = mlx5e_open_channels(priv, &new_channels);
1171 if (err)
1172 break;
2e20a151 1173 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 1174
58d52291
AS		 1175 break;
1176 default:
1177 err = -EINVAL;
1178 break;
1179 }
1180
546f18ed 1181 mutex_unlock(&priv->state_lock);
58d52291
AS		 1182 return err;
1183}
1184
3c2d18ef
AS		 1185static void mlx5e_get_pauseparam(struct net_device *netdev,
1186 struct ethtool_pauseparam *pauseparam)
1187{
1188 struct mlx5e_priv *priv = netdev_priv(netdev);
1189 struct mlx5_core_dev *mdev = priv->mdev;
1190 int err;
1191
1192 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1193 &pauseparam->tx_pause);
1194 if (err) {
1195 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1196 __func__, err);
1197 }
1198}
1199
1200static int mlx5e_set_pauseparam(struct net_device *netdev,
1201 struct ethtool_pauseparam *pauseparam)
1202{
1203 struct mlx5e_priv *priv = netdev_priv(netdev);
1204 struct mlx5_core_dev *mdev = priv->mdev;
1205 int err;
1206
1207 if (pauseparam->autoneg)
1208 return -EINVAL;
1209
1210 err = mlx5_set_port_pause(mdev,
1211 pauseparam->rx_pause ? 1 : 0,
1212 pauseparam->tx_pause ? 1 : 0);
1213 if (err) {
1214 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1215 __func__, err);
1216 }
1217
1218 return err;
1219}
1220
ef9814de
EBE		 1221static int mlx5e_get_ts_info(struct net_device *dev,
1222 struct ethtool_ts_info *info)
1223{
1224 struct mlx5e_priv *priv = netdev_priv(dev);
1225 int ret;
1226
1227 ret = ethtool_op_get_ts_info(dev, info);
1228 if (ret)
1229 return ret;
1230
3d8c38af
EBE		 1231 info->phc_index = priv->tstamp.ptp ?
1232 ptp_clock_index(priv->tstamp.ptp) : -1;
ef9814de
EBE		 1233
1234 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1235 return 0;
1236
1237 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1238 SOF_TIMESTAMPING_RX_HARDWARE |
1239 SOF_TIMESTAMPING_RAW_HARDWARE;
1240
1241 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1242 (BIT(1) << HWTSTAMP_TX_ON);
1243
1244 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1245 (BIT(1) << HWTSTAMP_FILTER_ALL);
1246
1247 return 0;
1248}
1249
928cfe87
TT		 1250static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1251{
1252 __u32 ret = 0;
1253
1254 if (MLX5_CAP_GEN(mdev, wol_g))
1255 ret |= WAKE_MAGIC;
1256
1257 if (MLX5_CAP_GEN(mdev, wol_s))
1258 ret |= WAKE_MAGICSECURE;
1259
1260 if (MLX5_CAP_GEN(mdev, wol_a))
1261 ret |= WAKE_ARP;
1262
1263 if (MLX5_CAP_GEN(mdev, wol_b))
1264 ret |= WAKE_BCAST;
1265
1266 if (MLX5_CAP_GEN(mdev, wol_m))
1267 ret |= WAKE_MCAST;
1268
1269 if (MLX5_CAP_GEN(mdev, wol_u))
1270 ret |= WAKE_UCAST;
1271
1272 if (MLX5_CAP_GEN(mdev, wol_p))
1273 ret |= WAKE_PHY;
1274
1275 return ret;
1276}
1277
1278static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1279{
1280 __u32 ret = 0;
1281
1282 if (mode & MLX5_WOL_MAGIC)
1283 ret |= WAKE_MAGIC;
1284
1285 if (mode & MLX5_WOL_SECURED_MAGIC)
1286 ret |= WAKE_MAGICSECURE;
1287
1288 if (mode & MLX5_WOL_ARP)
1289 ret |= WAKE_ARP;
1290
1291 if (mode & MLX5_WOL_BROADCAST)
1292 ret |= WAKE_BCAST;
1293
1294 if (mode & MLX5_WOL_MULTICAST)
1295 ret |= WAKE_MCAST;
1296
1297 if (mode & MLX5_WOL_UNICAST)
1298 ret |= WAKE_UCAST;
1299
1300 if (mode & MLX5_WOL_PHY_ACTIVITY)
1301 ret |= WAKE_PHY;
1302
1303 return ret;
1304}
1305
1306static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1307{
1308 u8 ret = 0;
1309
1310 if (mode & WAKE_MAGIC)
1311 ret |= MLX5_WOL_MAGIC;
1312
1313 if (mode & WAKE_MAGICSECURE)
1314 ret |= MLX5_WOL_SECURED_MAGIC;
1315
1316 if (mode & WAKE_ARP)
1317 ret |= MLX5_WOL_ARP;
1318
1319 if (mode & WAKE_BCAST)
1320 ret |= MLX5_WOL_BROADCAST;
1321
1322 if (mode & WAKE_MCAST)
1323 ret |= MLX5_WOL_MULTICAST;
1324
1325 if (mode & WAKE_UCAST)
1326 ret |= MLX5_WOL_UNICAST;
1327
1328 if (mode & WAKE_PHY)
1329 ret |= MLX5_WOL_PHY_ACTIVITY;
1330
1331 return ret;
1332}
1333
1334static void mlx5e_get_wol(struct net_device *netdev,
1335 struct ethtool_wolinfo *wol)
1336{
1337 struct mlx5e_priv *priv = netdev_priv(netdev);
1338 struct mlx5_core_dev *mdev = priv->mdev;
1339 u8 mlx5_wol_mode;
1340 int err;
1341
1342 memset(wol, 0, sizeof(*wol));
1343
1344 wol->supported = mlx5e_get_wol_supported(mdev);
1345 if (!wol->supported)
1346 return;
1347
1348 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1349 if (err)
1350 return;
1351
1352 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1353}
1354
1355static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1356{
1357 struct mlx5e_priv *priv = netdev_priv(netdev);
1358 struct mlx5_core_dev *mdev = priv->mdev;
1359 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1360 u32 mlx5_wol_mode;
1361
1362 if (!wol_supported)
9eb78923 1363 return -EOPNOTSUPP;
928cfe87
TT		 1364
1365 if (wol->wolopts & ~wol_supported)
1366 return -EINVAL;
1367
1368 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1369
1370 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1371}
1372
da54d24e
GP		 1373static int mlx5e_set_phys_id(struct net_device *dev,
1374 enum ethtool_phys_id_state state)
1375{
1376 struct mlx5e_priv *priv = netdev_priv(dev);
1377 struct mlx5_core_dev *mdev = priv->mdev;
1378 u16 beacon_duration;
1379
1380 if (!MLX5_CAP_GEN(mdev, beacon_led))
1381 return -EOPNOTSUPP;
1382
1383 switch (state) {
1384 case ETHTOOL_ID_ACTIVE:
1385 beacon_duration = MLX5_BEACON_DURATION_INF;
1386 break;
1387 case ETHTOOL_ID_INACTIVE:
1388 beacon_duration = MLX5_BEACON_DURATION_OFF;
1389 break;
1390 default:
1391 return -EOPNOTSUPP;
1392 }
1393
1394 return mlx5_set_port_beacon(mdev, beacon_duration);
1395}
1396
bb64143e
GP		 1397static int mlx5e_get_module_info(struct net_device *netdev,
1398 struct ethtool_modinfo *modinfo)
1399{
1400 struct mlx5e_priv *priv = netdev_priv(netdev);
1401 struct mlx5_core_dev *dev = priv->mdev;
1402 int size_read = 0;
1403 u8 data[4];
1404
1405 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1406 if (size_read < 2)
1407 return -EIO;
1408
1409 /* data[0] = identifier byte */
1410 switch (data[0]) {
1411 case MLX5_MODULE_ID_QSFP:
1412 modinfo->type = ETH_MODULE_SFF_8436;
1413 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1414 break;
1415 case MLX5_MODULE_ID_QSFP_PLUS:
1416 case MLX5_MODULE_ID_QSFP28:
1417 /* data[1] = revision id */
1418 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1419 modinfo->type = ETH_MODULE_SFF_8636;
1420 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1421 } else {
1422 modinfo->type = ETH_MODULE_SFF_8436;
1423 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1424 }
1425 break;
1426 case MLX5_MODULE_ID_SFP:
1427 modinfo->type = ETH_MODULE_SFF_8472;
1428 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1429 break;
1430 default:
1431 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1432 __func__, data[0]);
1433 return -EINVAL;
1434 }
1435
1436 return 0;
1437}
1438
1439static int mlx5e_get_module_eeprom(struct net_device *netdev,
1440 struct ethtool_eeprom *ee,
1441 u8 *data)
1442{
1443 struct mlx5e_priv *priv = netdev_priv(netdev);
1444 struct mlx5_core_dev *mdev = priv->mdev;
1445 int offset = ee->offset;
1446 int size_read;
1447 int i = 0;
1448
1449 if (!ee->len)
1450 return -EINVAL;
1451
1452 memset(data, 0, ee->len);
1453
1454 while (i < ee->len) {
1455 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1456 data + i);
1457
1458 if (!size_read)
1459 /* Done reading */
1460 return 0;
1461
1462 if (size_read < 0) {
1463 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1464 __func__, size_read);
1465 return 0;
1466 }
1467
1468 i += size_read;
1469 offset += size_read;
1470 }
1471
1472 return 0;
1473}
1474
4e59e288
GP		 1475typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1476
9908aa29 1477static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
4e59e288 1478{
9908aa29
TT		 1479 struct mlx5e_priv *priv = netdev_priv(netdev);
1480 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1481 struct mlx5e_channels new_channels = {};
9908aa29
TT		 1482 bool rx_mode_changed;
1483 u8 rx_cq_period_mode;
1484 int err = 0;
9908aa29
TT		 1485
1486 rx_cq_period_mode = enable ?
1487 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1488 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
6a9764ef 1489 rx_mode_changed = rx_cq_period_mode != priv->channels.params.rx_cq_period_mode;
9908aa29
TT		 1490
1491 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1492 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1493 return -EOPNOTSUPP;
9908aa29
TT		 1494
1495 if (!rx_mode_changed)
1496 return 0;
1497
be7e87f9
SM		 1498 new_channels.params = priv->channels.params;
1499 mlx5e_set_rx_cq_mode_params(&new_channels.params, rx_cq_period_mode);
9908aa29 1500
be7e87f9
SM		 1501 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1502 priv->channels.params = new_channels.params;
1503 return 0;
1504 }
1505
1506 err = mlx5e_open_channels(priv, &new_channels);
1507 if (err)
1508 return err;
9908aa29 1509
2e20a151 1510 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9
SM		 1511 return 0;
1512}
9908aa29 1513
be7e87f9
SM		 1514int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1515{
1516 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1517 struct mlx5e_channels new_channels = {};
1518 int err = 0;
1519
1520 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1521 return new_val ? -EOPNOTSUPP : 0;
1522
1523 if (curr_val == new_val)
1524 return 0;
1525
1526 new_channels.params = priv->channels.params;
1527 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1528
1529 mlx5e_set_rq_type_params(priv->mdev, &new_channels.params,
1530 new_channels.params.rq_wq_type);
1531
1532 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1533 priv->channels.params = new_channels.params;
1534 return 0;
1535 }
1536
1537 err = mlx5e_open_channels(priv, &new_channels);
1538 if (err)
1539 return err;
1540
2e20a151 1541 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9 1542 return 0;
4e59e288
GP		 1543}
1544
9bcc8606
SD		 1545static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1546 bool enable)
1547{
1548 struct mlx5e_priv *priv = netdev_priv(netdev);
1549 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1550
1551 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1552 return -EOPNOTSUPP;
9bcc8606
SD		 1553
1554 if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1555 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1556 return -EINVAL;
1557 }
1558
5eb0249b 1559 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1560 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1561
5eb0249b 1562 return 0;
9bcc8606
SD		 1563}
1564
4e59e288
GP		 1565static int mlx5e_handle_pflag(struct net_device *netdev,
1566 u32 wanted_flags,
1567 enum mlx5e_priv_flag flag,
1568 mlx5e_pflag_handler pflag_handler)
1569{
1570 struct mlx5e_priv *priv = netdev_priv(netdev);
1571 bool enable = !!(wanted_flags & flag);
6a9764ef 1572 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1573 int err;
1574
1575 if (!(changes & flag))
1576 return 0;
1577
1578 err = pflag_handler(netdev, enable);
1579 if (err) {
1580 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1581 enable ? "Enable" : "Disable", flag, err);
1582 return err;
1583 }
1584
6a9764ef 1585 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1586 return 0;
1587}
1588
1589static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1590{
1591 struct mlx5e_priv *priv = netdev_priv(netdev);
1592 int err;
1593
1594 mutex_lock(&priv->state_lock);
9908aa29
TT		 1595 err = mlx5e_handle_pflag(netdev, pflags,
1596 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1597 set_pflag_rx_cqe_based_moder);
9bcc8606
SD		 1598 if (err)
1599 goto out;
4e59e288 1600
9bcc8606
SD		 1601 err = mlx5e_handle_pflag(netdev, pflags,
1602 MLX5E_PFLAG_RX_CQE_COMPRESS,
1603 set_pflag_rx_cqe_compress);
1604
1605out:
4e59e288 1606 mutex_unlock(&priv->state_lock);
9bcc8606 1607 return err;
4e59e288
GP		 1608}
1609
1610static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1611{
1612 struct mlx5e_priv *priv = netdev_priv(netdev);
1613
6a9764ef 1614 return priv->channels.params.pflags;
4e59e288
GP		 1615}
1616
6dc6071c
MG		 1617static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1618{
1619 int err = 0;
1620 struct mlx5e_priv *priv = netdev_priv(dev);
1621
1622 switch (cmd->cmd) {
1623 case ETHTOOL_SRXCLSRLINS:
1624 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1625 break;
1626 case ETHTOOL_SRXCLSRLDEL:
1627 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1628 break;
1629 default:
1630 err = -EOPNOTSUPP;
1631 break;
1632 }
1633
1634 return err;
1635}
1636
f62b8bb8
AV		 1637const struct ethtool_ops mlx5e_ethtool_ops = {
1638 .get_drvinfo = mlx5e_get_drvinfo,
1639 .get_link = ethtool_op_get_link,
1640 .get_strings = mlx5e_get_strings,
1641 .get_sset_count = mlx5e_get_sset_count,
1642 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1643 .get_ringparam = mlx5e_get_ringparam,
1644 .set_ringparam = mlx5e_set_ringparam,
1645 .get_channels = mlx5e_get_channels,
1646 .set_channels = mlx5e_set_channels,
1647 .get_coalesce = mlx5e_get_coalesce,
1648 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1649 .get_link_ksettings = mlx5e_get_link_ksettings,
1650 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1651 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1652 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1653 .get_rxfh = mlx5e_get_rxfh,
1654 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1655 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1656 .set_rxnfc = mlx5e_set_rxnfc,
58d52291
AS		 1657 .get_tunable = mlx5e_get_tunable,
1658 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1659 .get_pauseparam = mlx5e_get_pauseparam,
1660 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1661 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1662 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1663 .get_wol = mlx5e_get_wol,
1664 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1665 .get_module_info = mlx5e_get_module_info,
1666 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1667 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1668 .set_priv_flags = mlx5e_set_priv_flags,
1669 .self_test = mlx5e_self_test,
f62b8bb8 1670};
A mirror of Linus' kernel repository